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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c MR |
52 | DRM_FORMAT_XRGB1555, |
53 | DRM_FORMAT_ARGB1555, | |
67fe7dc5 DL |
54 | DRM_FORMAT_XRGB8888, |
55 | DRM_FORMAT_ARGB8888, | |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
67fe7dc5 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
465c120c | 63 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 64 | DRM_FORMAT_ARGB8888, |
465c120c MR |
65 | DRM_FORMAT_ABGR8888, |
66 | DRM_FORMAT_XRGB2101010, | |
465c120c | 67 | DRM_FORMAT_XBGR2101010, |
465c120c MR |
68 | }; |
69 | ||
3d7d6510 MR |
70 | /* Cursor formats */ |
71 | static const uint32_t intel_cursor_formats[] = { | |
72 | DRM_FORMAT_ARGB8888, | |
73 | }; | |
74 | ||
6b383a7f | 75 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 76 | |
f1f644dc | 77 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 78 | struct intel_crtc_state *pipe_config); |
18442d08 | 79 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 80 | struct intel_crtc_state *pipe_config); |
f1f644dc | 81 | |
8c7b5ccb | 82 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 83 | struct drm_atomic_state *state); |
eb1bfe80 JB |
84 | static int intel_framebuffer_init(struct drm_device *dev, |
85 | struct intel_framebuffer *ifb, | |
86 | struct drm_mode_fb_cmd2 *mode_cmd, | |
87 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
88 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
89 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 90 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
91 | struct intel_link_m_n *m_n, |
92 | struct intel_link_m_n *m2_n2); | |
29407aab | 93 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
94 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
95 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 96 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 97 | const struct intel_crtc_state *pipe_config); |
d288f65f | 98 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 99 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
100 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
101 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
102 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
103 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
104 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
105 | int num_connectors); | |
ce22dba9 ML |
106 | static void intel_crtc_enable_planes(struct drm_crtc *crtc); |
107 | static void intel_crtc_disable_planes(struct drm_crtc *crtc); | |
e7457a9a | 108 | |
0e32b39c DA |
109 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
110 | { | |
111 | if (!connector->mst_port) | |
112 | return connector->encoder; | |
113 | else | |
114 | return &connector->mst_port->mst_encoders[pipe]->base; | |
115 | } | |
116 | ||
79e53945 | 117 | typedef struct { |
0206e353 | 118 | int min, max; |
79e53945 JB |
119 | } intel_range_t; |
120 | ||
121 | typedef struct { | |
0206e353 AJ |
122 | int dot_limit; |
123 | int p2_slow, p2_fast; | |
79e53945 JB |
124 | } intel_p2_t; |
125 | ||
d4906093 ML |
126 | typedef struct intel_limit intel_limit_t; |
127 | struct intel_limit { | |
0206e353 AJ |
128 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
129 | intel_p2_t p2; | |
d4906093 | 130 | }; |
79e53945 | 131 | |
d2acd215 DV |
132 | int |
133 | intel_pch_rawclk(struct drm_device *dev) | |
134 | { | |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
136 | ||
137 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
138 | ||
139 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
140 | } | |
141 | ||
021357ac CW |
142 | static inline u32 /* units of 100MHz */ |
143 | intel_fdi_link_freq(struct drm_device *dev) | |
144 | { | |
8b99e68c CW |
145 | if (IS_GEN5(dev)) { |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
148 | } else | |
149 | return 27; | |
021357ac CW |
150 | } |
151 | ||
5d536e28 | 152 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 153 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 154 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 155 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
156 | .m = { .min = 96, .max = 140 }, |
157 | .m1 = { .min = 18, .max = 26 }, | |
158 | .m2 = { .min = 6, .max = 16 }, | |
159 | .p = { .min = 4, .max = 128 }, | |
160 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
161 | .p2 = { .dot_limit = 165000, |
162 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
163 | }; |
164 | ||
5d536e28 DV |
165 | static const intel_limit_t intel_limits_i8xx_dvo = { |
166 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 167 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 168 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
169 | .m = { .min = 96, .max = 140 }, |
170 | .m1 = { .min = 18, .max = 26 }, | |
171 | .m2 = { .min = 6, .max = 16 }, | |
172 | .p = { .min = 4, .max = 128 }, | |
173 | .p1 = { .min = 2, .max = 33 }, | |
174 | .p2 = { .dot_limit = 165000, | |
175 | .p2_slow = 4, .p2_fast = 4 }, | |
176 | }; | |
177 | ||
e4b36699 | 178 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 179 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 180 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 181 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
182 | .m = { .min = 96, .max = 140 }, |
183 | .m1 = { .min = 18, .max = 26 }, | |
184 | .m2 = { .min = 6, .max = 16 }, | |
185 | .p = { .min = 4, .max = 128 }, | |
186 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
187 | .p2 = { .dot_limit = 165000, |
188 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 189 | }; |
273e27ca | 190 | |
e4b36699 | 191 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
192 | .dot = { .min = 20000, .max = 400000 }, |
193 | .vco = { .min = 1400000, .max = 2800000 }, | |
194 | .n = { .min = 1, .max = 6 }, | |
195 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
196 | .m1 = { .min = 8, .max = 18 }, |
197 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
198 | .p = { .min = 5, .max = 80 }, |
199 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
200 | .p2 = { .dot_limit = 200000, |
201 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
202 | }; |
203 | ||
204 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
205 | .dot = { .min = 20000, .max = 400000 }, |
206 | .vco = { .min = 1400000, .max = 2800000 }, | |
207 | .n = { .min = 1, .max = 6 }, | |
208 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
209 | .m1 = { .min = 8, .max = 18 }, |
210 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
211 | .p = { .min = 7, .max = 98 }, |
212 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
213 | .p2 = { .dot_limit = 112000, |
214 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
215 | }; |
216 | ||
273e27ca | 217 | |
e4b36699 | 218 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
219 | .dot = { .min = 25000, .max = 270000 }, |
220 | .vco = { .min = 1750000, .max = 3500000}, | |
221 | .n = { .min = 1, .max = 4 }, | |
222 | .m = { .min = 104, .max = 138 }, | |
223 | .m1 = { .min = 17, .max = 23 }, | |
224 | .m2 = { .min = 5, .max = 11 }, | |
225 | .p = { .min = 10, .max = 30 }, | |
226 | .p1 = { .min = 1, .max = 3}, | |
227 | .p2 = { .dot_limit = 270000, | |
228 | .p2_slow = 10, | |
229 | .p2_fast = 10 | |
044c7c41 | 230 | }, |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
234 | .dot = { .min = 22000, .max = 400000 }, |
235 | .vco = { .min = 1750000, .max = 3500000}, | |
236 | .n = { .min = 1, .max = 4 }, | |
237 | .m = { .min = 104, .max = 138 }, | |
238 | .m1 = { .min = 16, .max = 23 }, | |
239 | .m2 = { .min = 5, .max = 11 }, | |
240 | .p = { .min = 5, .max = 80 }, | |
241 | .p1 = { .min = 1, .max = 8}, | |
242 | .p2 = { .dot_limit = 165000, | |
243 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
244 | }; |
245 | ||
246 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
247 | .dot = { .min = 20000, .max = 115000 }, |
248 | .vco = { .min = 1750000, .max = 3500000 }, | |
249 | .n = { .min = 1, .max = 3 }, | |
250 | .m = { .min = 104, .max = 138 }, | |
251 | .m1 = { .min = 17, .max = 23 }, | |
252 | .m2 = { .min = 5, .max = 11 }, | |
253 | .p = { .min = 28, .max = 112 }, | |
254 | .p1 = { .min = 2, .max = 8 }, | |
255 | .p2 = { .dot_limit = 0, | |
256 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 257 | }, |
e4b36699 KP |
258 | }; |
259 | ||
260 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
261 | .dot = { .min = 80000, .max = 224000 }, |
262 | .vco = { .min = 1750000, .max = 3500000 }, | |
263 | .n = { .min = 1, .max = 3 }, | |
264 | .m = { .min = 104, .max = 138 }, | |
265 | .m1 = { .min = 17, .max = 23 }, | |
266 | .m2 = { .min = 5, .max = 11 }, | |
267 | .p = { .min = 14, .max = 42 }, | |
268 | .p1 = { .min = 2, .max = 6 }, | |
269 | .p2 = { .dot_limit = 0, | |
270 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 271 | }, |
e4b36699 KP |
272 | }; |
273 | ||
f2b115e6 | 274 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
275 | .dot = { .min = 20000, .max = 400000}, |
276 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 277 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
278 | .n = { .min = 3, .max = 6 }, |
279 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 280 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
281 | .m1 = { .min = 0, .max = 0 }, |
282 | .m2 = { .min = 0, .max = 254 }, | |
283 | .p = { .min = 5, .max = 80 }, | |
284 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
285 | .p2 = { .dot_limit = 200000, |
286 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
287 | }; |
288 | ||
f2b115e6 | 289 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
290 | .dot = { .min = 20000, .max = 400000 }, |
291 | .vco = { .min = 1700000, .max = 3500000 }, | |
292 | .n = { .min = 3, .max = 6 }, | |
293 | .m = { .min = 2, .max = 256 }, | |
294 | .m1 = { .min = 0, .max = 0 }, | |
295 | .m2 = { .min = 0, .max = 254 }, | |
296 | .p = { .min = 7, .max = 112 }, | |
297 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 112000, |
299 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
300 | }; |
301 | ||
273e27ca EA |
302 | /* Ironlake / Sandybridge |
303 | * | |
304 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
305 | * the range value for them is (actual_value - 2). | |
306 | */ | |
b91ad0ec | 307 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, | |
310 | .n = { .min = 1, .max = 5 }, | |
311 | .m = { .min = 79, .max = 127 }, | |
312 | .m1 = { .min = 12, .max = 22 }, | |
313 | .m2 = { .min = 5, .max = 9 }, | |
314 | .p = { .min = 5, .max = 80 }, | |
315 | .p1 = { .min = 1, .max = 8 }, | |
316 | .p2 = { .dot_limit = 225000, | |
317 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
318 | }; |
319 | ||
b91ad0ec | 320 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 3 }, | |
324 | .m = { .min = 79, .max = 118 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 28, .max = 112 }, | |
328 | .p1 = { .min = 2, .max = 8 }, | |
329 | .p2 = { .dot_limit = 225000, | |
330 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
331 | }; |
332 | ||
333 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 3 }, | |
337 | .m = { .min = 79, .max = 127 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 14, .max = 56 }, | |
341 | .p1 = { .min = 2, .max = 8 }, | |
342 | .p2 = { .dot_limit = 225000, | |
343 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
344 | }; |
345 | ||
273e27ca | 346 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 347 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 2 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
358 | }; |
359 | ||
360 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
361 | .dot = { .min = 25000, .max = 350000 }, |
362 | .vco = { .min = 1760000, .max = 3510000 }, | |
363 | .n = { .min = 1, .max = 3 }, | |
364 | .m = { .min = 79, .max = 126 }, | |
365 | .m1 = { .min = 12, .max = 22 }, | |
366 | .m2 = { .min = 5, .max = 9 }, | |
367 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 368 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
369 | .p2 = { .dot_limit = 225000, |
370 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
371 | }; |
372 | ||
dc730512 | 373 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
374 | /* |
375 | * These are the data rate limits (measured in fast clocks) | |
376 | * since those are the strictest limits we have. The fast | |
377 | * clock and actual rate limits are more relaxed, so checking | |
378 | * them would make no difference. | |
379 | */ | |
380 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 381 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 382 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
383 | .m1 = { .min = 2, .max = 3 }, |
384 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 385 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 386 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
387 | }; |
388 | ||
ef9348c8 CML |
389 | static const intel_limit_t intel_limits_chv = { |
390 | /* | |
391 | * These are the data rate limits (measured in fast clocks) | |
392 | * since those are the strictest limits we have. The fast | |
393 | * clock and actual rate limits are more relaxed, so checking | |
394 | * them would make no difference. | |
395 | */ | |
396 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 397 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
398 | .n = { .min = 1, .max = 1 }, |
399 | .m1 = { .min = 2, .max = 2 }, | |
400 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
401 | .p1 = { .min = 2, .max = 4 }, | |
402 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
403 | }; | |
404 | ||
5ab7b0b7 ID |
405 | static const intel_limit_t intel_limits_bxt = { |
406 | /* FIXME: find real dot limits */ | |
407 | .dot = { .min = 0, .max = INT_MAX }, | |
408 | .vco = { .min = 4800000, .max = 6480000 }, | |
409 | .n = { .min = 1, .max = 1 }, | |
410 | .m1 = { .min = 2, .max = 2 }, | |
411 | /* FIXME: find real m2 limits */ | |
412 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
413 | .p1 = { .min = 2, .max = 4 }, | |
414 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
415 | }; | |
416 | ||
6b4bf1c4 VS |
417 | static void vlv_clock(int refclk, intel_clock_t *clock) |
418 | { | |
419 | clock->m = clock->m1 * clock->m2; | |
420 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
421 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
422 | return; | |
fb03ac01 VS |
423 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
424 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
425 | } |
426 | ||
e0638cdf PZ |
427 | /** |
428 | * Returns whether any output on the specified pipe is of the specified type | |
429 | */ | |
4093561b | 430 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 431 | { |
409ee761 | 432 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
433 | struct intel_encoder *encoder; |
434 | ||
409ee761 | 435 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
436 | if (encoder->type == type) |
437 | return true; | |
438 | ||
439 | return false; | |
440 | } | |
441 | ||
d0737e1d ACO |
442 | /** |
443 | * Returns whether any output on the specified pipe will have the specified | |
444 | * type after a staged modeset is complete, i.e., the same as | |
445 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
446 | * encoder->crtc. | |
447 | */ | |
a93e255f ACO |
448 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
449 | int type) | |
d0737e1d | 450 | { |
a93e255f | 451 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 452 | struct drm_connector *connector; |
a93e255f | 453 | struct drm_connector_state *connector_state; |
d0737e1d | 454 | struct intel_encoder *encoder; |
a93e255f ACO |
455 | int i, num_connectors = 0; |
456 | ||
da3ced29 | 457 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
458 | if (connector_state->crtc != crtc_state->base.crtc) |
459 | continue; | |
460 | ||
461 | num_connectors++; | |
d0737e1d | 462 | |
a93e255f ACO |
463 | encoder = to_intel_encoder(connector_state->best_encoder); |
464 | if (encoder->type == type) | |
d0737e1d | 465 | return true; |
a93e255f ACO |
466 | } |
467 | ||
468 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
469 | |
470 | return false; | |
471 | } | |
472 | ||
a93e255f ACO |
473 | static const intel_limit_t * |
474 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 475 | { |
a93e255f | 476 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 477 | const intel_limit_t *limit; |
b91ad0ec | 478 | |
a93e255f | 479 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 480 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 481 | if (refclk == 100000) |
b91ad0ec ZW |
482 | limit = &intel_limits_ironlake_dual_lvds_100m; |
483 | else | |
484 | limit = &intel_limits_ironlake_dual_lvds; | |
485 | } else { | |
1b894b59 | 486 | if (refclk == 100000) |
b91ad0ec ZW |
487 | limit = &intel_limits_ironlake_single_lvds_100m; |
488 | else | |
489 | limit = &intel_limits_ironlake_single_lvds; | |
490 | } | |
c6bb3538 | 491 | } else |
b91ad0ec | 492 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
493 | |
494 | return limit; | |
495 | } | |
496 | ||
a93e255f ACO |
497 | static const intel_limit_t * |
498 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 499 | { |
a93e255f | 500 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
501 | const intel_limit_t *limit; |
502 | ||
a93e255f | 503 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 504 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 505 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 506 | else |
e4b36699 | 507 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
508 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
509 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 510 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 511 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 512 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 513 | } else /* The option is for other outputs */ |
e4b36699 | 514 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
515 | |
516 | return limit; | |
517 | } | |
518 | ||
a93e255f ACO |
519 | static const intel_limit_t * |
520 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 521 | { |
a93e255f | 522 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
523 | const intel_limit_t *limit; |
524 | ||
5ab7b0b7 ID |
525 | if (IS_BROXTON(dev)) |
526 | limit = &intel_limits_bxt; | |
527 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 528 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 529 | else if (IS_G4X(dev)) { |
a93e255f | 530 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 531 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 532 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 533 | limit = &intel_limits_pineview_lvds; |
2177832f | 534 | else |
f2b115e6 | 535 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
536 | } else if (IS_CHERRYVIEW(dev)) { |
537 | limit = &intel_limits_chv; | |
a0c4da24 | 538 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 539 | limit = &intel_limits_vlv; |
a6c45cf0 | 540 | } else if (!IS_GEN2(dev)) { |
a93e255f | 541 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
542 | limit = &intel_limits_i9xx_lvds; |
543 | else | |
544 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 545 | } else { |
a93e255f | 546 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 547 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 548 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 549 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
550 | else |
551 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
552 | } |
553 | return limit; | |
554 | } | |
555 | ||
f2b115e6 AJ |
556 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
557 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 558 | { |
2177832f SL |
559 | clock->m = clock->m2 + 2; |
560 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
561 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
562 | return; | |
fb03ac01 VS |
563 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
564 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
565 | } |
566 | ||
7429e9d4 DV |
567 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
568 | { | |
569 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
570 | } | |
571 | ||
ac58c3f0 | 572 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 573 | { |
7429e9d4 | 574 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 575 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
576 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
577 | return; | |
fb03ac01 VS |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
580 | } |
581 | ||
ef9348c8 CML |
582 | static void chv_clock(int refclk, intel_clock_t *clock) |
583 | { | |
584 | clock->m = clock->m1 * clock->m2; | |
585 | clock->p = clock->p1 * clock->p2; | |
586 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
587 | return; | |
588 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
589 | clock->n << 22); | |
590 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
591 | } | |
592 | ||
7c04d1d9 | 593 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
594 | /** |
595 | * Returns whether the given set of divisors are valid for a given refclk with | |
596 | * the given connectors. | |
597 | */ | |
598 | ||
1b894b59 CW |
599 | static bool intel_PLL_is_valid(struct drm_device *dev, |
600 | const intel_limit_t *limit, | |
601 | const intel_clock_t *clock) | |
79e53945 | 602 | { |
f01b7962 VS |
603 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
604 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 605 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 606 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 607 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 608 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 609 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 610 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 611 | |
5ab7b0b7 | 612 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
613 | if (clock->m1 <= clock->m2) |
614 | INTELPllInvalid("m1 <= m2\n"); | |
615 | ||
5ab7b0b7 | 616 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
617 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
618 | INTELPllInvalid("p out of range\n"); | |
619 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
620 | INTELPllInvalid("m out of range\n"); | |
621 | } | |
622 | ||
79e53945 | 623 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 624 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
625 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
626 | * connector, etc., rather than just a single range. | |
627 | */ | |
628 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 629 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
630 | |
631 | return true; | |
632 | } | |
633 | ||
d4906093 | 634 | static bool |
a93e255f ACO |
635 | i9xx_find_best_dpll(const intel_limit_t *limit, |
636 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
637 | int target, int refclk, intel_clock_t *match_clock, |
638 | intel_clock_t *best_clock) | |
79e53945 | 639 | { |
a93e255f | 640 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 641 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 642 | intel_clock_t clock; |
79e53945 JB |
643 | int err = target; |
644 | ||
a93e255f | 645 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 646 | /* |
a210b028 DV |
647 | * For LVDS just rely on its current settings for dual-channel. |
648 | * We haven't figured out how to reliably set up different | |
649 | * single/dual channel state, if we even can. | |
79e53945 | 650 | */ |
1974cad0 | 651 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
652 | clock.p2 = limit->p2.p2_fast; |
653 | else | |
654 | clock.p2 = limit->p2.p2_slow; | |
655 | } else { | |
656 | if (target < limit->p2.dot_limit) | |
657 | clock.p2 = limit->p2.p2_slow; | |
658 | else | |
659 | clock.p2 = limit->p2.p2_fast; | |
660 | } | |
661 | ||
0206e353 | 662 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 663 | |
42158660 ZY |
664 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
665 | clock.m1++) { | |
666 | for (clock.m2 = limit->m2.min; | |
667 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 668 | if (clock.m2 >= clock.m1) |
42158660 ZY |
669 | break; |
670 | for (clock.n = limit->n.min; | |
671 | clock.n <= limit->n.max; clock.n++) { | |
672 | for (clock.p1 = limit->p1.min; | |
673 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
674 | int this_err; |
675 | ||
ac58c3f0 DV |
676 | i9xx_clock(refclk, &clock); |
677 | if (!intel_PLL_is_valid(dev, limit, | |
678 | &clock)) | |
679 | continue; | |
680 | if (match_clock && | |
681 | clock.p != match_clock->p) | |
682 | continue; | |
683 | ||
684 | this_err = abs(clock.dot - target); | |
685 | if (this_err < err) { | |
686 | *best_clock = clock; | |
687 | err = this_err; | |
688 | } | |
689 | } | |
690 | } | |
691 | } | |
692 | } | |
693 | ||
694 | return (err != target); | |
695 | } | |
696 | ||
697 | static bool | |
a93e255f ACO |
698 | pnv_find_best_dpll(const intel_limit_t *limit, |
699 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
700 | int target, int refclk, intel_clock_t *match_clock, |
701 | intel_clock_t *best_clock) | |
79e53945 | 702 | { |
a93e255f | 703 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 704 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 705 | intel_clock_t clock; |
79e53945 JB |
706 | int err = target; |
707 | ||
a93e255f | 708 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 709 | /* |
a210b028 DV |
710 | * For LVDS just rely on its current settings for dual-channel. |
711 | * We haven't figured out how to reliably set up different | |
712 | * single/dual channel state, if we even can. | |
79e53945 | 713 | */ |
1974cad0 | 714 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
715 | clock.p2 = limit->p2.p2_fast; |
716 | else | |
717 | clock.p2 = limit->p2.p2_slow; | |
718 | } else { | |
719 | if (target < limit->p2.dot_limit) | |
720 | clock.p2 = limit->p2.p2_slow; | |
721 | else | |
722 | clock.p2 = limit->p2.p2_fast; | |
723 | } | |
724 | ||
0206e353 | 725 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 726 | |
42158660 ZY |
727 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
728 | clock.m1++) { | |
729 | for (clock.m2 = limit->m2.min; | |
730 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
731 | for (clock.n = limit->n.min; |
732 | clock.n <= limit->n.max; clock.n++) { | |
733 | for (clock.p1 = limit->p1.min; | |
734 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
735 | int this_err; |
736 | ||
ac58c3f0 | 737 | pineview_clock(refclk, &clock); |
1b894b59 CW |
738 | if (!intel_PLL_is_valid(dev, limit, |
739 | &clock)) | |
79e53945 | 740 | continue; |
cec2f356 SP |
741 | if (match_clock && |
742 | clock.p != match_clock->p) | |
743 | continue; | |
79e53945 JB |
744 | |
745 | this_err = abs(clock.dot - target); | |
746 | if (this_err < err) { | |
747 | *best_clock = clock; | |
748 | err = this_err; | |
749 | } | |
750 | } | |
751 | } | |
752 | } | |
753 | } | |
754 | ||
755 | return (err != target); | |
756 | } | |
757 | ||
d4906093 | 758 | static bool |
a93e255f ACO |
759 | g4x_find_best_dpll(const intel_limit_t *limit, |
760 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
761 | int target, int refclk, intel_clock_t *match_clock, |
762 | intel_clock_t *best_clock) | |
d4906093 | 763 | { |
a93e255f | 764 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 765 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
766 | intel_clock_t clock; |
767 | int max_n; | |
768 | bool found; | |
6ba770dc AJ |
769 | /* approximately equals target * 0.00585 */ |
770 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
771 | found = false; |
772 | ||
a93e255f | 773 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 774 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
775 | clock.p2 = limit->p2.p2_fast; |
776 | else | |
777 | clock.p2 = limit->p2.p2_slow; | |
778 | } else { | |
779 | if (target < limit->p2.dot_limit) | |
780 | clock.p2 = limit->p2.p2_slow; | |
781 | else | |
782 | clock.p2 = limit->p2.p2_fast; | |
783 | } | |
784 | ||
785 | memset(best_clock, 0, sizeof(*best_clock)); | |
786 | max_n = limit->n.max; | |
f77f13e2 | 787 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 788 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 789 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
790 | for (clock.m1 = limit->m1.max; |
791 | clock.m1 >= limit->m1.min; clock.m1--) { | |
792 | for (clock.m2 = limit->m2.max; | |
793 | clock.m2 >= limit->m2.min; clock.m2--) { | |
794 | for (clock.p1 = limit->p1.max; | |
795 | clock.p1 >= limit->p1.min; clock.p1--) { | |
796 | int this_err; | |
797 | ||
ac58c3f0 | 798 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
799 | if (!intel_PLL_is_valid(dev, limit, |
800 | &clock)) | |
d4906093 | 801 | continue; |
1b894b59 CW |
802 | |
803 | this_err = abs(clock.dot - target); | |
d4906093 ML |
804 | if (this_err < err_most) { |
805 | *best_clock = clock; | |
806 | err_most = this_err; | |
807 | max_n = clock.n; | |
808 | found = true; | |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
813 | } | |
2c07245f ZW |
814 | return found; |
815 | } | |
816 | ||
d5dd62bd ID |
817 | /* |
818 | * Check if the calculated PLL configuration is more optimal compared to the | |
819 | * best configuration and error found so far. Return the calculated error. | |
820 | */ | |
821 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
822 | const intel_clock_t *calculated_clock, | |
823 | const intel_clock_t *best_clock, | |
824 | unsigned int best_error_ppm, | |
825 | unsigned int *error_ppm) | |
826 | { | |
9ca3ba01 ID |
827 | /* |
828 | * For CHV ignore the error and consider only the P value. | |
829 | * Prefer a bigger P value based on HW requirements. | |
830 | */ | |
831 | if (IS_CHERRYVIEW(dev)) { | |
832 | *error_ppm = 0; | |
833 | ||
834 | return calculated_clock->p > best_clock->p; | |
835 | } | |
836 | ||
24be4e46 ID |
837 | if (WARN_ON_ONCE(!target_freq)) |
838 | return false; | |
839 | ||
d5dd62bd ID |
840 | *error_ppm = div_u64(1000000ULL * |
841 | abs(target_freq - calculated_clock->dot), | |
842 | target_freq); | |
843 | /* | |
844 | * Prefer a better P value over a better (smaller) error if the error | |
845 | * is small. Ensure this preference for future configurations too by | |
846 | * setting the error to 0. | |
847 | */ | |
848 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
849 | *error_ppm = 0; | |
850 | ||
851 | return true; | |
852 | } | |
853 | ||
854 | return *error_ppm + 10 < best_error_ppm; | |
855 | } | |
856 | ||
a0c4da24 | 857 | static bool |
a93e255f ACO |
858 | vlv_find_best_dpll(const intel_limit_t *limit, |
859 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
860 | int target, int refclk, intel_clock_t *match_clock, |
861 | intel_clock_t *best_clock) | |
a0c4da24 | 862 | { |
a93e255f | 863 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 864 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 865 | intel_clock_t clock; |
69e4f900 | 866 | unsigned int bestppm = 1000000; |
27e639bf VS |
867 | /* min update 19.2 MHz */ |
868 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 869 | bool found = false; |
a0c4da24 | 870 | |
6b4bf1c4 VS |
871 | target *= 5; /* fast clock */ |
872 | ||
873 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
874 | |
875 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 876 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 877 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 878 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 879 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 880 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 881 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 882 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 883 | unsigned int ppm; |
69e4f900 | 884 | |
6b4bf1c4 VS |
885 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
886 | refclk * clock.m1); | |
887 | ||
888 | vlv_clock(refclk, &clock); | |
43b0ac53 | 889 | |
f01b7962 VS |
890 | if (!intel_PLL_is_valid(dev, limit, |
891 | &clock)) | |
43b0ac53 VS |
892 | continue; |
893 | ||
d5dd62bd ID |
894 | if (!vlv_PLL_is_optimal(dev, target, |
895 | &clock, | |
896 | best_clock, | |
897 | bestppm, &ppm)) | |
898 | continue; | |
6b4bf1c4 | 899 | |
d5dd62bd ID |
900 | *best_clock = clock; |
901 | bestppm = ppm; | |
902 | found = true; | |
a0c4da24 JB |
903 | } |
904 | } | |
905 | } | |
906 | } | |
a0c4da24 | 907 | |
49e497ef | 908 | return found; |
a0c4da24 | 909 | } |
a4fc5ed6 | 910 | |
ef9348c8 | 911 | static bool |
a93e255f ACO |
912 | chv_find_best_dpll(const intel_limit_t *limit, |
913 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
914 | int target, int refclk, intel_clock_t *match_clock, |
915 | intel_clock_t *best_clock) | |
916 | { | |
a93e255f | 917 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 918 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 919 | unsigned int best_error_ppm; |
ef9348c8 CML |
920 | intel_clock_t clock; |
921 | uint64_t m2; | |
922 | int found = false; | |
923 | ||
924 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 925 | best_error_ppm = 1000000; |
ef9348c8 CML |
926 | |
927 | /* | |
928 | * Based on hardware doc, the n always set to 1, and m1 always | |
929 | * set to 2. If requires to support 200Mhz refclk, we need to | |
930 | * revisit this because n may not 1 anymore. | |
931 | */ | |
932 | clock.n = 1, clock.m1 = 2; | |
933 | target *= 5; /* fast clock */ | |
934 | ||
935 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
936 | for (clock.p2 = limit->p2.p2_fast; | |
937 | clock.p2 >= limit->p2.p2_slow; | |
938 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 939 | unsigned int error_ppm; |
ef9348c8 CML |
940 | |
941 | clock.p = clock.p1 * clock.p2; | |
942 | ||
943 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
944 | clock.n) << 22, refclk * clock.m1); | |
945 | ||
946 | if (m2 > INT_MAX/clock.m1) | |
947 | continue; | |
948 | ||
949 | clock.m2 = m2; | |
950 | ||
951 | chv_clock(refclk, &clock); | |
952 | ||
953 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
954 | continue; | |
955 | ||
9ca3ba01 ID |
956 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
957 | best_error_ppm, &error_ppm)) | |
958 | continue; | |
959 | ||
960 | *best_clock = clock; | |
961 | best_error_ppm = error_ppm; | |
962 | found = true; | |
ef9348c8 CML |
963 | } |
964 | } | |
965 | ||
966 | return found; | |
967 | } | |
968 | ||
5ab7b0b7 ID |
969 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
970 | intel_clock_t *best_clock) | |
971 | { | |
972 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
973 | ||
974 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
975 | target_clock, refclk, NULL, best_clock); | |
976 | } | |
977 | ||
20ddf665 VS |
978 | bool intel_crtc_active(struct drm_crtc *crtc) |
979 | { | |
980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
981 | ||
982 | /* Be paranoid as we can arrive here with only partial | |
983 | * state retrieved from the hardware during setup. | |
984 | * | |
241bfc38 | 985 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
986 | * as Haswell has gained clock readout/fastboot support. |
987 | * | |
66e514c1 | 988 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 989 | * properly reconstruct framebuffers. |
c3d1f436 MR |
990 | * |
991 | * FIXME: The intel_crtc->active here should be switched to | |
992 | * crtc->state->active once we have proper CRTC states wired up | |
993 | * for atomic. | |
20ddf665 | 994 | */ |
c3d1f436 | 995 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 996 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
997 | } |
998 | ||
a5c961d1 PZ |
999 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1000 | enum pipe pipe) | |
1001 | { | |
1002 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1004 | ||
6e3c9717 | 1005 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1006 | } |
1007 | ||
fbf49ea2 VS |
1008 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1009 | { | |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011 | u32 reg = PIPEDSL(pipe); | |
1012 | u32 line1, line2; | |
1013 | u32 line_mask; | |
1014 | ||
1015 | if (IS_GEN2(dev)) | |
1016 | line_mask = DSL_LINEMASK_GEN2; | |
1017 | else | |
1018 | line_mask = DSL_LINEMASK_GEN3; | |
1019 | ||
1020 | line1 = I915_READ(reg) & line_mask; | |
1021 | mdelay(5); | |
1022 | line2 = I915_READ(reg) & line_mask; | |
1023 | ||
1024 | return line1 == line2; | |
1025 | } | |
1026 | ||
ab7ad7f6 KP |
1027 | /* |
1028 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1029 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1030 | * |
1031 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1032 | * spinning on the vblank interrupt status bit, since we won't actually | |
1033 | * see an interrupt when the pipe is disabled. | |
1034 | * | |
ab7ad7f6 KP |
1035 | * On Gen4 and above: |
1036 | * wait for the pipe register state bit to turn off | |
1037 | * | |
1038 | * Otherwise: | |
1039 | * wait for the display line value to settle (it usually | |
1040 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1041 | * |
9d0498a2 | 1042 | */ |
575f7ab7 | 1043 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1044 | { |
575f7ab7 | 1045 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1046 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1047 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1048 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1049 | |
1050 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1051 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1052 | |
1053 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1054 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1055 | 100)) | |
284637d9 | 1056 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1057 | } else { |
ab7ad7f6 | 1058 | /* Wait for the display line to settle */ |
fbf49ea2 | 1059 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1060 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1061 | } |
79e53945 JB |
1062 | } |
1063 | ||
b0ea7d37 DL |
1064 | /* |
1065 | * ibx_digital_port_connected - is the specified port connected? | |
1066 | * @dev_priv: i915 private structure | |
1067 | * @port: the port to test | |
1068 | * | |
1069 | * Returns true if @port is connected, false otherwise. | |
1070 | */ | |
1071 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1072 | struct intel_digital_port *port) | |
1073 | { | |
1074 | u32 bit; | |
1075 | ||
c36346e3 | 1076 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1077 | switch (port->port) { |
c36346e3 DL |
1078 | case PORT_B: |
1079 | bit = SDE_PORTB_HOTPLUG; | |
1080 | break; | |
1081 | case PORT_C: | |
1082 | bit = SDE_PORTC_HOTPLUG; | |
1083 | break; | |
1084 | case PORT_D: | |
1085 | bit = SDE_PORTD_HOTPLUG; | |
1086 | break; | |
1087 | default: | |
1088 | return true; | |
1089 | } | |
1090 | } else { | |
eba905b2 | 1091 | switch (port->port) { |
c36346e3 DL |
1092 | case PORT_B: |
1093 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1094 | break; | |
1095 | case PORT_C: | |
1096 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1097 | break; | |
1098 | case PORT_D: | |
1099 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1100 | break; | |
1101 | default: | |
1102 | return true; | |
1103 | } | |
b0ea7d37 DL |
1104 | } |
1105 | ||
1106 | return I915_READ(SDEISR) & bit; | |
1107 | } | |
1108 | ||
b24e7179 JB |
1109 | static const char *state_string(bool enabled) |
1110 | { | |
1111 | return enabled ? "on" : "off"; | |
1112 | } | |
1113 | ||
1114 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1115 | void assert_pll(struct drm_i915_private *dev_priv, |
1116 | enum pipe pipe, bool state) | |
b24e7179 JB |
1117 | { |
1118 | int reg; | |
1119 | u32 val; | |
1120 | bool cur_state; | |
1121 | ||
1122 | reg = DPLL(pipe); | |
1123 | val = I915_READ(reg); | |
1124 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1125 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1126 | "PLL state assertion failure (expected %s, current %s)\n", |
1127 | state_string(state), state_string(cur_state)); | |
1128 | } | |
b24e7179 | 1129 | |
23538ef1 JN |
1130 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1131 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1132 | { | |
1133 | u32 val; | |
1134 | bool cur_state; | |
1135 | ||
1136 | mutex_lock(&dev_priv->dpio_lock); | |
1137 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1138 | mutex_unlock(&dev_priv->dpio_lock); | |
1139 | ||
1140 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1141 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1142 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1143 | state_string(state), state_string(cur_state)); | |
1144 | } | |
1145 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1146 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1147 | ||
55607e8a | 1148 | struct intel_shared_dpll * |
e2b78267 DV |
1149 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1150 | { | |
1151 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1152 | ||
6e3c9717 | 1153 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1154 | return NULL; |
1155 | ||
6e3c9717 | 1156 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1157 | } |
1158 | ||
040484af | 1159 | /* For ILK+ */ |
55607e8a DV |
1160 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1161 | struct intel_shared_dpll *pll, | |
1162 | bool state) | |
040484af | 1163 | { |
040484af | 1164 | bool cur_state; |
5358901f | 1165 | struct intel_dpll_hw_state hw_state; |
040484af | 1166 | |
92b27b08 | 1167 | if (WARN (!pll, |
46edb027 | 1168 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1169 | return; |
ee7b9f93 | 1170 | |
5358901f | 1171 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1172 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1173 | "%s assertion failure (expected %s, current %s)\n", |
1174 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1175 | } |
040484af JB |
1176 | |
1177 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1178 | enum pipe pipe, bool state) | |
1179 | { | |
1180 | int reg; | |
1181 | u32 val; | |
1182 | bool cur_state; | |
ad80a810 PZ |
1183 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1184 | pipe); | |
040484af | 1185 | |
affa9354 PZ |
1186 | if (HAS_DDI(dev_priv->dev)) { |
1187 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1188 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1189 | val = I915_READ(reg); |
ad80a810 | 1190 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1191 | } else { |
1192 | reg = FDI_TX_CTL(pipe); | |
1193 | val = I915_READ(reg); | |
1194 | cur_state = !!(val & FDI_TX_ENABLE); | |
1195 | } | |
e2c719b7 | 1196 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1197 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1198 | state_string(state), state_string(cur_state)); | |
1199 | } | |
1200 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1201 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1202 | ||
1203 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1204 | enum pipe pipe, bool state) | |
1205 | { | |
1206 | int reg; | |
1207 | u32 val; | |
1208 | bool cur_state; | |
1209 | ||
d63fa0dc PZ |
1210 | reg = FDI_RX_CTL(pipe); |
1211 | val = I915_READ(reg); | |
1212 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1213 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1214 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1215 | state_string(state), state_string(cur_state)); | |
1216 | } | |
1217 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1218 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1219 | ||
1220 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1221 | enum pipe pipe) | |
1222 | { | |
1223 | int reg; | |
1224 | u32 val; | |
1225 | ||
1226 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1227 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1228 | return; |
1229 | ||
bf507ef7 | 1230 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1231 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1232 | return; |
1233 | ||
040484af JB |
1234 | reg = FDI_TX_CTL(pipe); |
1235 | val = I915_READ(reg); | |
e2c719b7 | 1236 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1237 | } |
1238 | ||
55607e8a DV |
1239 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1240 | enum pipe pipe, bool state) | |
040484af JB |
1241 | { |
1242 | int reg; | |
1243 | u32 val; | |
55607e8a | 1244 | bool cur_state; |
040484af JB |
1245 | |
1246 | reg = FDI_RX_CTL(pipe); | |
1247 | val = I915_READ(reg); | |
55607e8a | 1248 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1249 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1250 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1251 | state_string(state), state_string(cur_state)); | |
040484af JB |
1252 | } |
1253 | ||
b680c37a DV |
1254 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1255 | enum pipe pipe) | |
ea0760cf | 1256 | { |
bedd4dba JN |
1257 | struct drm_device *dev = dev_priv->dev; |
1258 | int pp_reg; | |
ea0760cf JB |
1259 | u32 val; |
1260 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1261 | bool locked = true; |
ea0760cf | 1262 | |
bedd4dba JN |
1263 | if (WARN_ON(HAS_DDI(dev))) |
1264 | return; | |
1265 | ||
1266 | if (HAS_PCH_SPLIT(dev)) { | |
1267 | u32 port_sel; | |
1268 | ||
ea0760cf | 1269 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1270 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1271 | ||
1272 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1273 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1274 | panel_pipe = PIPE_B; | |
1275 | /* XXX: else fix for eDP */ | |
1276 | } else if (IS_VALLEYVIEW(dev)) { | |
1277 | /* presumably write lock depends on pipe, not port select */ | |
1278 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1279 | panel_pipe = pipe; | |
ea0760cf JB |
1280 | } else { |
1281 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1282 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1283 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1284 | } |
1285 | ||
1286 | val = I915_READ(pp_reg); | |
1287 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1288 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1289 | locked = false; |
1290 | ||
e2c719b7 | 1291 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1292 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1293 | pipe_name(pipe)); |
ea0760cf JB |
1294 | } |
1295 | ||
93ce0ba6 JN |
1296 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1297 | enum pipe pipe, bool state) | |
1298 | { | |
1299 | struct drm_device *dev = dev_priv->dev; | |
1300 | bool cur_state; | |
1301 | ||
d9d82081 | 1302 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1303 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1304 | else |
5efb3e28 | 1305 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1306 | |
e2c719b7 | 1307 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1308 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1309 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1310 | } | |
1311 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1312 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1313 | ||
b840d907 JB |
1314 | void assert_pipe(struct drm_i915_private *dev_priv, |
1315 | enum pipe pipe, bool state) | |
b24e7179 JB |
1316 | { |
1317 | int reg; | |
1318 | u32 val; | |
63d7bbe9 | 1319 | bool cur_state; |
702e7a56 PZ |
1320 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1321 | pipe); | |
b24e7179 | 1322 | |
b6b5d049 VS |
1323 | /* if we need the pipe quirk it must be always on */ |
1324 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1325 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1326 | state = true; |
1327 | ||
f458ebbc | 1328 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1329 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1330 | cur_state = false; |
1331 | } else { | |
1332 | reg = PIPECONF(cpu_transcoder); | |
1333 | val = I915_READ(reg); | |
1334 | cur_state = !!(val & PIPECONF_ENABLE); | |
1335 | } | |
1336 | ||
e2c719b7 | 1337 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1338 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1339 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1340 | } |
1341 | ||
931872fc CW |
1342 | static void assert_plane(struct drm_i915_private *dev_priv, |
1343 | enum plane plane, bool state) | |
b24e7179 JB |
1344 | { |
1345 | int reg; | |
1346 | u32 val; | |
931872fc | 1347 | bool cur_state; |
b24e7179 JB |
1348 | |
1349 | reg = DSPCNTR(plane); | |
1350 | val = I915_READ(reg); | |
931872fc | 1351 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1352 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1353 | "plane %c assertion failure (expected %s, current %s)\n", |
1354 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1355 | } |
1356 | ||
931872fc CW |
1357 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1358 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1359 | ||
b24e7179 JB |
1360 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1361 | enum pipe pipe) | |
1362 | { | |
653e1026 | 1363 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1364 | int reg, i; |
1365 | u32 val; | |
1366 | int cur_pipe; | |
1367 | ||
653e1026 VS |
1368 | /* Primary planes are fixed to pipes on gen4+ */ |
1369 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1370 | reg = DSPCNTR(pipe); |
1371 | val = I915_READ(reg); | |
e2c719b7 | 1372 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1373 | "plane %c assertion failure, should be disabled but not\n", |
1374 | plane_name(pipe)); | |
19ec1358 | 1375 | return; |
28c05794 | 1376 | } |
19ec1358 | 1377 | |
b24e7179 | 1378 | /* Need to check both planes against the pipe */ |
055e393f | 1379 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1380 | reg = DSPCNTR(i); |
1381 | val = I915_READ(reg); | |
1382 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1383 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1384 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1385 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1386 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1387 | } |
1388 | } | |
1389 | ||
19332d7a JB |
1390 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1391 | enum pipe pipe) | |
1392 | { | |
20674eef | 1393 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1394 | int reg, sprite; |
19332d7a JB |
1395 | u32 val; |
1396 | ||
7feb8b88 | 1397 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1398 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1399 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1400 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1401 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1402 | sprite, pipe_name(pipe)); | |
1403 | } | |
1404 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1405 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1406 | reg = SPCNTR(pipe, sprite); |
20674eef | 1407 | val = I915_READ(reg); |
e2c719b7 | 1408 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1409 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1410 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1411 | } |
1412 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1413 | reg = SPRCTL(pipe); | |
19332d7a | 1414 | val = I915_READ(reg); |
e2c719b7 | 1415 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1416 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1417 | plane_name(pipe), pipe_name(pipe)); |
1418 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1419 | reg = DVSCNTR(pipe); | |
19332d7a | 1420 | val = I915_READ(reg); |
e2c719b7 | 1421 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1422 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1423 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1424 | } |
1425 | } | |
1426 | ||
08c71e5e VS |
1427 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1428 | { | |
e2c719b7 | 1429 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1430 | drm_crtc_vblank_put(crtc); |
1431 | } | |
1432 | ||
89eff4be | 1433 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1434 | { |
1435 | u32 val; | |
1436 | bool enabled; | |
1437 | ||
e2c719b7 | 1438 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1439 | |
92f2584a JB |
1440 | val = I915_READ(PCH_DREF_CONTROL); |
1441 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1442 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1443 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1444 | } |
1445 | ||
ab9412ba DV |
1446 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1447 | enum pipe pipe) | |
92f2584a JB |
1448 | { |
1449 | int reg; | |
1450 | u32 val; | |
1451 | bool enabled; | |
1452 | ||
ab9412ba | 1453 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1454 | val = I915_READ(reg); |
1455 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1456 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1457 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1458 | pipe_name(pipe)); | |
92f2584a JB |
1459 | } |
1460 | ||
4e634389 KP |
1461 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1462 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1463 | { |
1464 | if ((val & DP_PORT_EN) == 0) | |
1465 | return false; | |
1466 | ||
1467 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1468 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1469 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1470 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1471 | return false; | |
44f37d1f CML |
1472 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1473 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1474 | return false; | |
f0575e92 KP |
1475 | } else { |
1476 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1477 | return false; | |
1478 | } | |
1479 | return true; | |
1480 | } | |
1481 | ||
1519b995 KP |
1482 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1483 | enum pipe pipe, u32 val) | |
1484 | { | |
dc0fa718 | 1485 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1486 | return false; |
1487 | ||
1488 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1489 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1490 | return false; |
44f37d1f CML |
1491 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1492 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1493 | return false; | |
1519b995 | 1494 | } else { |
dc0fa718 | 1495 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1496 | return false; |
1497 | } | |
1498 | return true; | |
1499 | } | |
1500 | ||
1501 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1502 | enum pipe pipe, u32 val) | |
1503 | { | |
1504 | if ((val & LVDS_PORT_EN) == 0) | |
1505 | return false; | |
1506 | ||
1507 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1508 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1509 | return false; | |
1510 | } else { | |
1511 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1512 | return false; | |
1513 | } | |
1514 | return true; | |
1515 | } | |
1516 | ||
1517 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1518 | enum pipe pipe, u32 val) | |
1519 | { | |
1520 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1521 | return false; | |
1522 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1523 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1524 | return false; | |
1525 | } else { | |
1526 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1527 | return false; | |
1528 | } | |
1529 | return true; | |
1530 | } | |
1531 | ||
291906f1 | 1532 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1533 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1534 | { |
47a05eca | 1535 | u32 val = I915_READ(reg); |
e2c719b7 | 1536 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1537 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1538 | reg, pipe_name(pipe)); |
de9a35ab | 1539 | |
e2c719b7 | 1540 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1541 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1542 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1543 | } |
1544 | ||
1545 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1546 | enum pipe pipe, int reg) | |
1547 | { | |
47a05eca | 1548 | u32 val = I915_READ(reg); |
e2c719b7 | 1549 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1550 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1551 | reg, pipe_name(pipe)); |
de9a35ab | 1552 | |
e2c719b7 | 1553 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1554 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1555 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1556 | } |
1557 | ||
1558 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1559 | enum pipe pipe) | |
1560 | { | |
1561 | int reg; | |
1562 | u32 val; | |
291906f1 | 1563 | |
f0575e92 KP |
1564 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1565 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1566 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1567 | |
1568 | reg = PCH_ADPA; | |
1569 | val = I915_READ(reg); | |
e2c719b7 | 1570 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1571 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1572 | pipe_name(pipe)); |
291906f1 JB |
1573 | |
1574 | reg = PCH_LVDS; | |
1575 | val = I915_READ(reg); | |
e2c719b7 | 1576 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1577 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1578 | pipe_name(pipe)); |
291906f1 | 1579 | |
e2debe91 PZ |
1580 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1581 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1582 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1583 | } |
1584 | ||
40e9cf64 JB |
1585 | static void intel_init_dpio(struct drm_device *dev) |
1586 | { | |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | ||
1589 | if (!IS_VALLEYVIEW(dev)) | |
1590 | return; | |
1591 | ||
a09caddd CML |
1592 | /* |
1593 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1594 | * CHV x1 PHY (DP/HDMI D) | |
1595 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1596 | */ | |
1597 | if (IS_CHERRYVIEW(dev)) { | |
1598 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1599 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1600 | } else { | |
1601 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1602 | } | |
5382f5f3 JB |
1603 | } |
1604 | ||
d288f65f | 1605 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1606 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1607 | { |
426115cf DV |
1608 | struct drm_device *dev = crtc->base.dev; |
1609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1610 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1611 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1612 | |
426115cf | 1613 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1614 | |
1615 | /* No really, not for ILK+ */ | |
1616 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1617 | ||
1618 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1619 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1620 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1621 | |
426115cf DV |
1622 | I915_WRITE(reg, dpll); |
1623 | POSTING_READ(reg); | |
1624 | udelay(150); | |
1625 | ||
1626 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1627 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1628 | ||
d288f65f | 1629 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1630 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1631 | |
1632 | /* We do this three times for luck */ | |
426115cf | 1633 | I915_WRITE(reg, dpll); |
87442f73 DV |
1634 | POSTING_READ(reg); |
1635 | udelay(150); /* wait for warmup */ | |
426115cf | 1636 | I915_WRITE(reg, dpll); |
87442f73 DV |
1637 | POSTING_READ(reg); |
1638 | udelay(150); /* wait for warmup */ | |
426115cf | 1639 | I915_WRITE(reg, dpll); |
87442f73 DV |
1640 | POSTING_READ(reg); |
1641 | udelay(150); /* wait for warmup */ | |
1642 | } | |
1643 | ||
d288f65f | 1644 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1645 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1646 | { |
1647 | struct drm_device *dev = crtc->base.dev; | |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1649 | int pipe = crtc->pipe; | |
1650 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1651 | u32 tmp; |
1652 | ||
1653 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1654 | ||
1655 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1656 | ||
1657 | mutex_lock(&dev_priv->dpio_lock); | |
1658 | ||
1659 | /* Enable back the 10bit clock to display controller */ | |
1660 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1661 | tmp |= DPIO_DCLKP_EN; | |
1662 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1663 | ||
1664 | /* | |
1665 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1666 | */ | |
1667 | udelay(1); | |
1668 | ||
1669 | /* Enable PLL */ | |
d288f65f | 1670 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1671 | |
1672 | /* Check PLL is locked */ | |
a11b0703 | 1673 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1674 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1675 | ||
a11b0703 | 1676 | /* not sure when this should be written */ |
d288f65f | 1677 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1678 | POSTING_READ(DPLL_MD(pipe)); |
1679 | ||
9d556c99 CML |
1680 | mutex_unlock(&dev_priv->dpio_lock); |
1681 | } | |
1682 | ||
1c4e0274 VS |
1683 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1684 | { | |
1685 | struct intel_crtc *crtc; | |
1686 | int count = 0; | |
1687 | ||
1688 | for_each_intel_crtc(dev, crtc) | |
1689 | count += crtc->active && | |
409ee761 | 1690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1691 | |
1692 | return count; | |
1693 | } | |
1694 | ||
66e3d5c0 | 1695 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1696 | { |
66e3d5c0 DV |
1697 | struct drm_device *dev = crtc->base.dev; |
1698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1699 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1700 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1701 | |
66e3d5c0 | 1702 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1703 | |
63d7bbe9 | 1704 | /* No really, not for ILK+ */ |
3d13ef2e | 1705 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1706 | |
1707 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1708 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1709 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1710 | |
1c4e0274 VS |
1711 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1712 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1713 | /* | |
1714 | * It appears to be important that we don't enable this | |
1715 | * for the current pipe before otherwise configuring the | |
1716 | * PLL. No idea how this should be handled if multiple | |
1717 | * DVO outputs are enabled simultaneosly. | |
1718 | */ | |
1719 | dpll |= DPLL_DVO_2X_MODE; | |
1720 | I915_WRITE(DPLL(!crtc->pipe), | |
1721 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1722 | } | |
66e3d5c0 DV |
1723 | |
1724 | /* Wait for the clocks to stabilize. */ | |
1725 | POSTING_READ(reg); | |
1726 | udelay(150); | |
1727 | ||
1728 | if (INTEL_INFO(dev)->gen >= 4) { | |
1729 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1730 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1731 | } else { |
1732 | /* The pixel multiplier can only be updated once the | |
1733 | * DPLL is enabled and the clocks are stable. | |
1734 | * | |
1735 | * So write it again. | |
1736 | */ | |
1737 | I915_WRITE(reg, dpll); | |
1738 | } | |
63d7bbe9 JB |
1739 | |
1740 | /* We do this three times for luck */ | |
66e3d5c0 | 1741 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1742 | POSTING_READ(reg); |
1743 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1744 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1745 | POSTING_READ(reg); |
1746 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1747 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1748 | POSTING_READ(reg); |
1749 | udelay(150); /* wait for warmup */ | |
1750 | } | |
1751 | ||
1752 | /** | |
50b44a44 | 1753 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1754 | * @dev_priv: i915 private structure |
1755 | * @pipe: pipe PLL to disable | |
1756 | * | |
1757 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1758 | * | |
1759 | * Note! This is for pre-ILK only. | |
1760 | */ | |
1c4e0274 | 1761 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1762 | { |
1c4e0274 VS |
1763 | struct drm_device *dev = crtc->base.dev; |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1765 | enum pipe pipe = crtc->pipe; | |
1766 | ||
1767 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1768 | if (IS_I830(dev) && | |
409ee761 | 1769 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1770 | intel_num_dvo_pipes(dev) == 1) { |
1771 | I915_WRITE(DPLL(PIPE_B), | |
1772 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1773 | I915_WRITE(DPLL(PIPE_A), | |
1774 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1775 | } | |
1776 | ||
b6b5d049 VS |
1777 | /* Don't disable pipe or pipe PLLs if needed */ |
1778 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1779 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1780 | return; |
1781 | ||
1782 | /* Make sure the pipe isn't still relying on us */ | |
1783 | assert_pipe_disabled(dev_priv, pipe); | |
1784 | ||
50b44a44 DV |
1785 | I915_WRITE(DPLL(pipe), 0); |
1786 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1787 | } |
1788 | ||
f6071166 JB |
1789 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1790 | { | |
1791 | u32 val = 0; | |
1792 | ||
1793 | /* Make sure the pipe isn't still relying on us */ | |
1794 | assert_pipe_disabled(dev_priv, pipe); | |
1795 | ||
e5cbfbfb ID |
1796 | /* |
1797 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1798 | * The latter is needed for VGA hotplug / manual detection. | |
1799 | */ | |
f6071166 | 1800 | if (pipe == PIPE_B) |
e5cbfbfb | 1801 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1802 | I915_WRITE(DPLL(pipe), val); |
1803 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1804 | |
1805 | } | |
1806 | ||
1807 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1808 | { | |
d752048d | 1809 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1810 | u32 val; |
1811 | ||
a11b0703 VS |
1812 | /* Make sure the pipe isn't still relying on us */ |
1813 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1814 | |
a11b0703 | 1815 | /* Set PLL en = 0 */ |
d17ec4ce | 1816 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1817 | if (pipe != PIPE_A) |
1818 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1819 | I915_WRITE(DPLL(pipe), val); | |
1820 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1821 | |
1822 | mutex_lock(&dev_priv->dpio_lock); | |
1823 | ||
1824 | /* Disable 10bit clock to display controller */ | |
1825 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1826 | val &= ~DPIO_DCLKP_EN; | |
1827 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1828 | ||
61407f6d VS |
1829 | /* disable left/right clock distribution */ |
1830 | if (pipe != PIPE_B) { | |
1831 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1832 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1833 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1834 | } else { | |
1835 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1836 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1837 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1838 | } | |
1839 | ||
d752048d | 1840 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1841 | } |
1842 | ||
e4607fcf | 1843 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1844 | struct intel_digital_port *dport, |
1845 | unsigned int expected_mask) | |
89b667f8 JB |
1846 | { |
1847 | u32 port_mask; | |
00fc31b7 | 1848 | int dpll_reg; |
89b667f8 | 1849 | |
e4607fcf CML |
1850 | switch (dport->port) { |
1851 | case PORT_B: | |
89b667f8 | 1852 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1853 | dpll_reg = DPLL(0); |
e4607fcf CML |
1854 | break; |
1855 | case PORT_C: | |
89b667f8 | 1856 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1857 | dpll_reg = DPLL(0); |
9b6de0a1 | 1858 | expected_mask <<= 4; |
00fc31b7 CML |
1859 | break; |
1860 | case PORT_D: | |
1861 | port_mask = DPLL_PORTD_READY_MASK; | |
1862 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1863 | break; |
1864 | default: | |
1865 | BUG(); | |
1866 | } | |
89b667f8 | 1867 | |
9b6de0a1 VS |
1868 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1869 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1870 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1871 | } |
1872 | ||
b14b1055 DV |
1873 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1874 | { | |
1875 | struct drm_device *dev = crtc->base.dev; | |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1877 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1878 | ||
be19f0ff CW |
1879 | if (WARN_ON(pll == NULL)) |
1880 | return; | |
1881 | ||
3e369b76 | 1882 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1883 | if (pll->active == 0) { |
1884 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1885 | WARN_ON(pll->on); | |
1886 | assert_shared_dpll_disabled(dev_priv, pll); | |
1887 | ||
1888 | pll->mode_set(dev_priv, pll); | |
1889 | } | |
1890 | } | |
1891 | ||
92f2584a | 1892 | /** |
85b3894f | 1893 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1894 | * @dev_priv: i915 private structure |
1895 | * @pipe: pipe PLL to enable | |
1896 | * | |
1897 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1898 | * drives the transcoder clock. | |
1899 | */ | |
85b3894f | 1900 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1901 | { |
3d13ef2e DL |
1902 | struct drm_device *dev = crtc->base.dev; |
1903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1904 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1905 | |
87a875bb | 1906 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1907 | return; |
1908 | ||
3e369b76 | 1909 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1910 | return; |
ee7b9f93 | 1911 | |
74dd6928 | 1912 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1913 | pll->name, pll->active, pll->on, |
e2b78267 | 1914 | crtc->base.base.id); |
92f2584a | 1915 | |
cdbd2316 DV |
1916 | if (pll->active++) { |
1917 | WARN_ON(!pll->on); | |
e9d6944e | 1918 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1919 | return; |
1920 | } | |
f4a091c7 | 1921 | WARN_ON(pll->on); |
ee7b9f93 | 1922 | |
bd2bb1b9 PZ |
1923 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1924 | ||
46edb027 | 1925 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1926 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1927 | pll->on = true; |
92f2584a JB |
1928 | } |
1929 | ||
f6daaec2 | 1930 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1931 | { |
3d13ef2e DL |
1932 | struct drm_device *dev = crtc->base.dev; |
1933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1934 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1935 | |
92f2584a | 1936 | /* PCH only available on ILK+ */ |
3d13ef2e | 1937 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1938 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1939 | return; |
92f2584a | 1940 | |
3e369b76 | 1941 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1942 | return; |
7a419866 | 1943 | |
46edb027 DV |
1944 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1945 | pll->name, pll->active, pll->on, | |
e2b78267 | 1946 | crtc->base.base.id); |
7a419866 | 1947 | |
48da64a8 | 1948 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1949 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1950 | return; |
1951 | } | |
1952 | ||
e9d6944e | 1953 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1954 | WARN_ON(!pll->on); |
cdbd2316 | 1955 | if (--pll->active) |
7a419866 | 1956 | return; |
ee7b9f93 | 1957 | |
46edb027 | 1958 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1959 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1960 | pll->on = false; |
bd2bb1b9 PZ |
1961 | |
1962 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1963 | } |
1964 | ||
b8a4f404 PZ |
1965 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1966 | enum pipe pipe) | |
040484af | 1967 | { |
23670b32 | 1968 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1969 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1971 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1972 | |
1973 | /* PCH only available on ILK+ */ | |
55522f37 | 1974 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1975 | |
1976 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1977 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1978 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1979 | |
1980 | /* FDI must be feeding us bits for PCH ports */ | |
1981 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1982 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1983 | ||
23670b32 DV |
1984 | if (HAS_PCH_CPT(dev)) { |
1985 | /* Workaround: Set the timing override bit before enabling the | |
1986 | * pch transcoder. */ | |
1987 | reg = TRANS_CHICKEN2(pipe); | |
1988 | val = I915_READ(reg); | |
1989 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1990 | I915_WRITE(reg, val); | |
59c859d6 | 1991 | } |
23670b32 | 1992 | |
ab9412ba | 1993 | reg = PCH_TRANSCONF(pipe); |
040484af | 1994 | val = I915_READ(reg); |
5f7f726d | 1995 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1996 | |
1997 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1998 | /* | |
1999 | * make the BPC in transcoder be consistent with | |
2000 | * that in pipeconf reg. | |
2001 | */ | |
dfd07d72 DV |
2002 | val &= ~PIPECONF_BPC_MASK; |
2003 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2004 | } |
5f7f726d PZ |
2005 | |
2006 | val &= ~TRANS_INTERLACE_MASK; | |
2007 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2008 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2009 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2010 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2011 | else | |
2012 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2013 | else |
2014 | val |= TRANS_PROGRESSIVE; | |
2015 | ||
040484af JB |
2016 | I915_WRITE(reg, val | TRANS_ENABLE); |
2017 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2018 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2019 | } |
2020 | ||
8fb033d7 | 2021 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2022 | enum transcoder cpu_transcoder) |
040484af | 2023 | { |
8fb033d7 | 2024 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2025 | |
2026 | /* PCH only available on ILK+ */ | |
55522f37 | 2027 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2028 | |
8fb033d7 | 2029 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2030 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2031 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2032 | |
223a6fdf PZ |
2033 | /* Workaround: set timing override bit. */ |
2034 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2035 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2036 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2037 | ||
25f3ef11 | 2038 | val = TRANS_ENABLE; |
937bb610 | 2039 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2040 | |
9a76b1c6 PZ |
2041 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2042 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2043 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2044 | else |
2045 | val |= TRANS_PROGRESSIVE; | |
2046 | ||
ab9412ba DV |
2047 | I915_WRITE(LPT_TRANSCONF, val); |
2048 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2049 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2050 | } |
2051 | ||
b8a4f404 PZ |
2052 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2053 | enum pipe pipe) | |
040484af | 2054 | { |
23670b32 DV |
2055 | struct drm_device *dev = dev_priv->dev; |
2056 | uint32_t reg, val; | |
040484af JB |
2057 | |
2058 | /* FDI relies on the transcoder */ | |
2059 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2060 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2061 | ||
291906f1 JB |
2062 | /* Ports must be off as well */ |
2063 | assert_pch_ports_disabled(dev_priv, pipe); | |
2064 | ||
ab9412ba | 2065 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2066 | val = I915_READ(reg); |
2067 | val &= ~TRANS_ENABLE; | |
2068 | I915_WRITE(reg, val); | |
2069 | /* wait for PCH transcoder off, transcoder state */ | |
2070 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2071 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2072 | |
2073 | if (!HAS_PCH_IBX(dev)) { | |
2074 | /* Workaround: Clear the timing override chicken bit again. */ | |
2075 | reg = TRANS_CHICKEN2(pipe); | |
2076 | val = I915_READ(reg); | |
2077 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2078 | I915_WRITE(reg, val); | |
2079 | } | |
040484af JB |
2080 | } |
2081 | ||
ab4d966c | 2082 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2083 | { |
8fb033d7 PZ |
2084 | u32 val; |
2085 | ||
ab9412ba | 2086 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2087 | val &= ~TRANS_ENABLE; |
ab9412ba | 2088 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2089 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2090 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2091 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2092 | |
2093 | /* Workaround: clear timing override bit. */ | |
2094 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2095 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2096 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2097 | } |
2098 | ||
b24e7179 | 2099 | /** |
309cfea8 | 2100 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2101 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2102 | * |
0372264a | 2103 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2104 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2105 | */ |
e1fdc473 | 2106 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2107 | { |
0372264a PZ |
2108 | struct drm_device *dev = crtc->base.dev; |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2110 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2111 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2112 | pipe); | |
1a240d4d | 2113 | enum pipe pch_transcoder; |
b24e7179 JB |
2114 | int reg; |
2115 | u32 val; | |
2116 | ||
58c6eaa2 | 2117 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2118 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2119 | assert_sprites_disabled(dev_priv, pipe); |
2120 | ||
681e5811 | 2121 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2122 | pch_transcoder = TRANSCODER_A; |
2123 | else | |
2124 | pch_transcoder = pipe; | |
2125 | ||
b24e7179 JB |
2126 | /* |
2127 | * A pipe without a PLL won't actually be able to drive bits from | |
2128 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2129 | * need the check. | |
2130 | */ | |
50360403 | 2131 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2132 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2133 | assert_dsi_pll_enabled(dev_priv); |
2134 | else | |
2135 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2136 | else { |
6e3c9717 | 2137 | if (crtc->config->has_pch_encoder) { |
040484af | 2138 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2139 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2140 | assert_fdi_tx_pll_enabled(dev_priv, |
2141 | (enum pipe) cpu_transcoder); | |
040484af JB |
2142 | } |
2143 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2144 | } | |
b24e7179 | 2145 | |
702e7a56 | 2146 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2147 | val = I915_READ(reg); |
7ad25d48 | 2148 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2149 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2150 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2151 | return; |
7ad25d48 | 2152 | } |
00d70b15 CW |
2153 | |
2154 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2155 | POSTING_READ(reg); |
b24e7179 JB |
2156 | } |
2157 | ||
2158 | /** | |
309cfea8 | 2159 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2160 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2161 | * |
575f7ab7 VS |
2162 | * Disable the pipe of @crtc, making sure that various hardware |
2163 | * specific requirements are met, if applicable, e.g. plane | |
2164 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2165 | * |
2166 | * Will wait until the pipe has shut down before returning. | |
2167 | */ | |
575f7ab7 | 2168 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2169 | { |
575f7ab7 | 2170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2171 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2172 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2173 | int reg; |
2174 | u32 val; | |
2175 | ||
2176 | /* | |
2177 | * Make sure planes won't keep trying to pump pixels to us, | |
2178 | * or we might hang the display. | |
2179 | */ | |
2180 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2181 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2182 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2183 | |
702e7a56 | 2184 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2185 | val = I915_READ(reg); |
00d70b15 CW |
2186 | if ((val & PIPECONF_ENABLE) == 0) |
2187 | return; | |
2188 | ||
67adc644 VS |
2189 | /* |
2190 | * Double wide has implications for planes | |
2191 | * so best keep it disabled when not needed. | |
2192 | */ | |
6e3c9717 | 2193 | if (crtc->config->double_wide) |
67adc644 VS |
2194 | val &= ~PIPECONF_DOUBLE_WIDE; |
2195 | ||
2196 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2197 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2198 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2199 | val &= ~PIPECONF_ENABLE; |
2200 | ||
2201 | I915_WRITE(reg, val); | |
2202 | if ((val & PIPECONF_ENABLE) == 0) | |
2203 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2204 | } |
2205 | ||
d74362c9 KP |
2206 | /* |
2207 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2208 | * trigger in order to latch. The display address reg provides this. | |
2209 | */ | |
1dba99f4 VS |
2210 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2211 | enum plane plane) | |
d74362c9 | 2212 | { |
3d13ef2e DL |
2213 | struct drm_device *dev = dev_priv->dev; |
2214 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2215 | |
2216 | I915_WRITE(reg, I915_READ(reg)); | |
2217 | POSTING_READ(reg); | |
d74362c9 KP |
2218 | } |
2219 | ||
b24e7179 | 2220 | /** |
262ca2b0 | 2221 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2222 | * @plane: plane to be enabled |
2223 | * @crtc: crtc for the plane | |
b24e7179 | 2224 | * |
fdd508a6 | 2225 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2226 | */ |
fdd508a6 VS |
2227 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2228 | struct drm_crtc *crtc) | |
b24e7179 | 2229 | { |
fdd508a6 VS |
2230 | struct drm_device *dev = plane->dev; |
2231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2232 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2233 | |
2234 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2235 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2236 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2237 | |
fdd508a6 VS |
2238 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2239 | crtc->x, crtc->y); | |
b24e7179 JB |
2240 | } |
2241 | ||
693db184 CW |
2242 | static bool need_vtd_wa(struct drm_device *dev) |
2243 | { | |
2244 | #ifdef CONFIG_INTEL_IOMMU | |
2245 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2246 | return true; | |
2247 | #endif | |
2248 | return false; | |
2249 | } | |
2250 | ||
50470bb0 | 2251 | unsigned int |
6761dd31 TU |
2252 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2253 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2254 | { |
6761dd31 TU |
2255 | unsigned int tile_height; |
2256 | uint32_t pixel_bytes; | |
a57ce0b2 | 2257 | |
b5d0e9bf DL |
2258 | switch (fb_format_modifier) { |
2259 | case DRM_FORMAT_MOD_NONE: | |
2260 | tile_height = 1; | |
2261 | break; | |
2262 | case I915_FORMAT_MOD_X_TILED: | |
2263 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2264 | break; | |
2265 | case I915_FORMAT_MOD_Y_TILED: | |
2266 | tile_height = 32; | |
2267 | break; | |
2268 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2269 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2270 | switch (pixel_bytes) { | |
b5d0e9bf | 2271 | default: |
6761dd31 | 2272 | case 1: |
b5d0e9bf DL |
2273 | tile_height = 64; |
2274 | break; | |
6761dd31 TU |
2275 | case 2: |
2276 | case 4: | |
b5d0e9bf DL |
2277 | tile_height = 32; |
2278 | break; | |
6761dd31 | 2279 | case 8: |
b5d0e9bf DL |
2280 | tile_height = 16; |
2281 | break; | |
6761dd31 | 2282 | case 16: |
b5d0e9bf DL |
2283 | WARN_ONCE(1, |
2284 | "128-bit pixels are not supported for display!"); | |
2285 | tile_height = 16; | |
2286 | break; | |
2287 | } | |
2288 | break; | |
2289 | default: | |
2290 | MISSING_CASE(fb_format_modifier); | |
2291 | tile_height = 1; | |
2292 | break; | |
2293 | } | |
091df6cb | 2294 | |
6761dd31 TU |
2295 | return tile_height; |
2296 | } | |
2297 | ||
2298 | unsigned int | |
2299 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2300 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2301 | { | |
2302 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2303 | fb_format_modifier)); | |
a57ce0b2 JB |
2304 | } |
2305 | ||
f64b98cd TU |
2306 | static int |
2307 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2308 | const struct drm_plane_state *plane_state) | |
2309 | { | |
50470bb0 | 2310 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2311 | |
f64b98cd TU |
2312 | *view = i915_ggtt_view_normal; |
2313 | ||
50470bb0 TU |
2314 | if (!plane_state) |
2315 | return 0; | |
2316 | ||
121920fa | 2317 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2318 | return 0; |
2319 | ||
9abc4648 | 2320 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2321 | |
2322 | info->height = fb->height; | |
2323 | info->pixel_format = fb->pixel_format; | |
2324 | info->pitch = fb->pitches[0]; | |
2325 | info->fb_modifier = fb->modifier[0]; | |
2326 | ||
f64b98cd TU |
2327 | return 0; |
2328 | } | |
2329 | ||
127bd2ac | 2330 | int |
850c4cdc TU |
2331 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2332 | struct drm_framebuffer *fb, | |
82bc3b2d | 2333 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2334 | struct intel_engine_cs *pipelined) |
6b95a207 | 2335 | { |
850c4cdc | 2336 | struct drm_device *dev = fb->dev; |
ce453d81 | 2337 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2338 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2339 | struct i915_ggtt_view view; |
6b95a207 KH |
2340 | u32 alignment; |
2341 | int ret; | |
2342 | ||
ebcdd39e MR |
2343 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2344 | ||
7b911adc TU |
2345 | switch (fb->modifier[0]) { |
2346 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2347 | if (INTEL_INFO(dev)->gen >= 9) |
2348 | alignment = 256 * 1024; | |
2349 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2350 | alignment = 128 * 1024; |
a6c45cf0 | 2351 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2352 | alignment = 4 * 1024; |
2353 | else | |
2354 | alignment = 64 * 1024; | |
6b95a207 | 2355 | break; |
7b911adc | 2356 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2357 | if (INTEL_INFO(dev)->gen >= 9) |
2358 | alignment = 256 * 1024; | |
2359 | else { | |
2360 | /* pin() will align the object as required by fence */ | |
2361 | alignment = 0; | |
2362 | } | |
6b95a207 | 2363 | break; |
7b911adc | 2364 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2365 | case I915_FORMAT_MOD_Yf_TILED: |
2366 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2367 | "Y tiling bo slipped through, driver bug!\n")) | |
2368 | return -EINVAL; | |
2369 | alignment = 1 * 1024 * 1024; | |
2370 | break; | |
6b95a207 | 2371 | default: |
7b911adc TU |
2372 | MISSING_CASE(fb->modifier[0]); |
2373 | return -EINVAL; | |
6b95a207 KH |
2374 | } |
2375 | ||
f64b98cd TU |
2376 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2377 | if (ret) | |
2378 | return ret; | |
2379 | ||
693db184 CW |
2380 | /* Note that the w/a also requires 64 PTE of padding following the |
2381 | * bo. We currently fill all unused PTE with the shadow page and so | |
2382 | * we should always have valid PTE following the scanout preventing | |
2383 | * the VT-d warning. | |
2384 | */ | |
2385 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2386 | alignment = 256 * 1024; | |
2387 | ||
d6dd6843 PZ |
2388 | /* |
2389 | * Global gtt pte registers are special registers which actually forward | |
2390 | * writes to a chunk of system memory. Which means that there is no risk | |
2391 | * that the register values disappear as soon as we call | |
2392 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2393 | * pin/unpin/fence and not more. | |
2394 | */ | |
2395 | intel_runtime_pm_get(dev_priv); | |
2396 | ||
ce453d81 | 2397 | dev_priv->mm.interruptible = false; |
e6617330 | 2398 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2399 | &view); |
48b956c5 | 2400 | if (ret) |
ce453d81 | 2401 | goto err_interruptible; |
6b95a207 KH |
2402 | |
2403 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2404 | * fence, whereas 965+ only requires a fence if using | |
2405 | * framebuffer compression. For simplicity, we always install | |
2406 | * a fence as the cost is not that onerous. | |
2407 | */ | |
06d98131 | 2408 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2409 | if (ret) |
2410 | goto err_unpin; | |
1690e1eb | 2411 | |
9a5a53b3 | 2412 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2413 | |
ce453d81 | 2414 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2415 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2416 | return 0; |
48b956c5 CW |
2417 | |
2418 | err_unpin: | |
f64b98cd | 2419 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2420 | err_interruptible: |
2421 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2422 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2423 | return ret; |
6b95a207 KH |
2424 | } |
2425 | ||
82bc3b2d TU |
2426 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2427 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2428 | { |
82bc3b2d | 2429 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2430 | struct i915_ggtt_view view; |
2431 | int ret; | |
82bc3b2d | 2432 | |
ebcdd39e MR |
2433 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2434 | ||
f64b98cd TU |
2435 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2436 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2437 | ||
1690e1eb | 2438 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2439 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2440 | } |
2441 | ||
c2c75131 DV |
2442 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2443 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2444 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2445 | unsigned int tiling_mode, | |
2446 | unsigned int cpp, | |
2447 | unsigned int pitch) | |
c2c75131 | 2448 | { |
bc752862 CW |
2449 | if (tiling_mode != I915_TILING_NONE) { |
2450 | unsigned int tile_rows, tiles; | |
c2c75131 | 2451 | |
bc752862 CW |
2452 | tile_rows = *y / 8; |
2453 | *y %= 8; | |
c2c75131 | 2454 | |
bc752862 CW |
2455 | tiles = *x / (512/cpp); |
2456 | *x %= 512/cpp; | |
2457 | ||
2458 | return tile_rows * pitch * 8 + tiles * 4096; | |
2459 | } else { | |
2460 | unsigned int offset; | |
2461 | ||
2462 | offset = *y * pitch + *x * cpp; | |
2463 | *y = 0; | |
2464 | *x = (offset & 4095) / cpp; | |
2465 | return offset & -4096; | |
2466 | } | |
c2c75131 DV |
2467 | } |
2468 | ||
b35d63fa | 2469 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2470 | { |
2471 | switch (format) { | |
2472 | case DISPPLANE_8BPP: | |
2473 | return DRM_FORMAT_C8; | |
2474 | case DISPPLANE_BGRX555: | |
2475 | return DRM_FORMAT_XRGB1555; | |
2476 | case DISPPLANE_BGRX565: | |
2477 | return DRM_FORMAT_RGB565; | |
2478 | default: | |
2479 | case DISPPLANE_BGRX888: | |
2480 | return DRM_FORMAT_XRGB8888; | |
2481 | case DISPPLANE_RGBX888: | |
2482 | return DRM_FORMAT_XBGR8888; | |
2483 | case DISPPLANE_BGRX101010: | |
2484 | return DRM_FORMAT_XRGB2101010; | |
2485 | case DISPPLANE_RGBX101010: | |
2486 | return DRM_FORMAT_XBGR2101010; | |
2487 | } | |
2488 | } | |
2489 | ||
bc8d7dff DL |
2490 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2491 | { | |
2492 | switch (format) { | |
2493 | case PLANE_CTL_FORMAT_RGB_565: | |
2494 | return DRM_FORMAT_RGB565; | |
2495 | default: | |
2496 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2497 | if (rgb_order) { | |
2498 | if (alpha) | |
2499 | return DRM_FORMAT_ABGR8888; | |
2500 | else | |
2501 | return DRM_FORMAT_XBGR8888; | |
2502 | } else { | |
2503 | if (alpha) | |
2504 | return DRM_FORMAT_ARGB8888; | |
2505 | else | |
2506 | return DRM_FORMAT_XRGB8888; | |
2507 | } | |
2508 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2509 | if (rgb_order) | |
2510 | return DRM_FORMAT_XBGR2101010; | |
2511 | else | |
2512 | return DRM_FORMAT_XRGB2101010; | |
2513 | } | |
2514 | } | |
2515 | ||
5724dbd1 | 2516 | static bool |
f6936e29 DV |
2517 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2518 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2519 | { |
2520 | struct drm_device *dev = crtc->base.dev; | |
2521 | struct drm_i915_gem_object *obj = NULL; | |
2522 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2523 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2524 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2525 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2526 | PAGE_SIZE); | |
2527 | ||
2528 | size_aligned -= base_aligned; | |
46f297fb | 2529 | |
ff2652ea CW |
2530 | if (plane_config->size == 0) |
2531 | return false; | |
2532 | ||
f37b5c2b DV |
2533 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2534 | base_aligned, | |
2535 | base_aligned, | |
2536 | size_aligned); | |
46f297fb | 2537 | if (!obj) |
484b41dd | 2538 | return false; |
46f297fb | 2539 | |
49af449b DL |
2540 | obj->tiling_mode = plane_config->tiling; |
2541 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2542 | obj->stride = fb->pitches[0]; |
46f297fb | 2543 | |
6bf129df DL |
2544 | mode_cmd.pixel_format = fb->pixel_format; |
2545 | mode_cmd.width = fb->width; | |
2546 | mode_cmd.height = fb->height; | |
2547 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2548 | mode_cmd.modifier[0] = fb->modifier[0]; |
2549 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2550 | |
2551 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2552 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2553 | &mode_cmd, obj)) { |
46f297fb JB |
2554 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2555 | goto out_unref_obj; | |
2556 | } | |
46f297fb | 2557 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2558 | |
f6936e29 | 2559 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2560 | return true; |
46f297fb JB |
2561 | |
2562 | out_unref_obj: | |
2563 | drm_gem_object_unreference(&obj->base); | |
2564 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2565 | return false; |
2566 | } | |
2567 | ||
afd65eb4 MR |
2568 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2569 | static void | |
2570 | update_state_fb(struct drm_plane *plane) | |
2571 | { | |
2572 | if (plane->fb == plane->state->fb) | |
2573 | return; | |
2574 | ||
2575 | if (plane->state->fb) | |
2576 | drm_framebuffer_unreference(plane->state->fb); | |
2577 | plane->state->fb = plane->fb; | |
2578 | if (plane->state->fb) | |
2579 | drm_framebuffer_reference(plane->state->fb); | |
2580 | } | |
2581 | ||
5724dbd1 | 2582 | static void |
f6936e29 DV |
2583 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2584 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2585 | { |
2586 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2588 | struct drm_crtc *c; |
2589 | struct intel_crtc *i; | |
2ff8fde1 | 2590 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2591 | struct drm_plane *primary = intel_crtc->base.primary; |
2592 | struct drm_framebuffer *fb; | |
484b41dd | 2593 | |
2d14030b | 2594 | if (!plane_config->fb) |
484b41dd JB |
2595 | return; |
2596 | ||
f6936e29 | 2597 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2598 | fb = &plane_config->fb->base; |
2599 | goto valid_fb; | |
f55548b5 | 2600 | } |
484b41dd | 2601 | |
2d14030b | 2602 | kfree(plane_config->fb); |
484b41dd JB |
2603 | |
2604 | /* | |
2605 | * Failed to alloc the obj, check to see if we should share | |
2606 | * an fb with another CRTC instead | |
2607 | */ | |
70e1e0ec | 2608 | for_each_crtc(dev, c) { |
484b41dd JB |
2609 | i = to_intel_crtc(c); |
2610 | ||
2611 | if (c == &intel_crtc->base) | |
2612 | continue; | |
2613 | ||
2ff8fde1 MR |
2614 | if (!i->active) |
2615 | continue; | |
2616 | ||
88595ac9 DV |
2617 | fb = c->primary->fb; |
2618 | if (!fb) | |
484b41dd JB |
2619 | continue; |
2620 | ||
88595ac9 | 2621 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2622 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2623 | drm_framebuffer_reference(fb); |
2624 | goto valid_fb; | |
484b41dd JB |
2625 | } |
2626 | } | |
88595ac9 DV |
2627 | |
2628 | return; | |
2629 | ||
2630 | valid_fb: | |
2631 | obj = intel_fb_obj(fb); | |
2632 | if (obj->tiling_mode != I915_TILING_NONE) | |
2633 | dev_priv->preserve_bios_swizzle = true; | |
2634 | ||
2635 | primary->fb = fb; | |
2636 | primary->state->crtc = &intel_crtc->base; | |
2637 | primary->crtc = &intel_crtc->base; | |
2638 | update_state_fb(primary); | |
2639 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2640 | } |
2641 | ||
29b9bde6 DV |
2642 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2643 | struct drm_framebuffer *fb, | |
2644 | int x, int y) | |
81255565 JB |
2645 | { |
2646 | struct drm_device *dev = crtc->dev; | |
2647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2649 | struct drm_plane *primary = crtc->primary; |
2650 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2651 | struct drm_i915_gem_object *obj; |
81255565 | 2652 | int plane = intel_crtc->plane; |
e506a0c6 | 2653 | unsigned long linear_offset; |
81255565 | 2654 | u32 dspcntr; |
f45651ba | 2655 | u32 reg = DSPCNTR(plane); |
48404c1e | 2656 | int pixel_size; |
f45651ba | 2657 | |
b70709a6 | 2658 | if (!visible || !fb) { |
fdd508a6 VS |
2659 | I915_WRITE(reg, 0); |
2660 | if (INTEL_INFO(dev)->gen >= 4) | |
2661 | I915_WRITE(DSPSURF(plane), 0); | |
2662 | else | |
2663 | I915_WRITE(DSPADDR(plane), 0); | |
2664 | POSTING_READ(reg); | |
2665 | return; | |
2666 | } | |
2667 | ||
c9ba6fad VS |
2668 | obj = intel_fb_obj(fb); |
2669 | if (WARN_ON(obj == NULL)) | |
2670 | return; | |
2671 | ||
2672 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2673 | ||
f45651ba VS |
2674 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2675 | ||
fdd508a6 | 2676 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2677 | |
2678 | if (INTEL_INFO(dev)->gen < 4) { | |
2679 | if (intel_crtc->pipe == PIPE_B) | |
2680 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2681 | ||
2682 | /* pipesrc and dspsize control the size that is scaled from, | |
2683 | * which should always be the user's requested size. | |
2684 | */ | |
2685 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2686 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2687 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2688 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2689 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2690 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2691 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2692 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2693 | I915_WRITE(PRIMPOS(plane), 0); |
2694 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2695 | } |
81255565 | 2696 | |
57779d06 VS |
2697 | switch (fb->pixel_format) { |
2698 | case DRM_FORMAT_C8: | |
81255565 JB |
2699 | dspcntr |= DISPPLANE_8BPP; |
2700 | break; | |
57779d06 VS |
2701 | case DRM_FORMAT_XRGB1555: |
2702 | case DRM_FORMAT_ARGB1555: | |
2703 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2704 | break; |
57779d06 VS |
2705 | case DRM_FORMAT_RGB565: |
2706 | dspcntr |= DISPPLANE_BGRX565; | |
2707 | break; | |
2708 | case DRM_FORMAT_XRGB8888: | |
2709 | case DRM_FORMAT_ARGB8888: | |
2710 | dspcntr |= DISPPLANE_BGRX888; | |
2711 | break; | |
2712 | case DRM_FORMAT_XBGR8888: | |
2713 | case DRM_FORMAT_ABGR8888: | |
2714 | dspcntr |= DISPPLANE_RGBX888; | |
2715 | break; | |
2716 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2717 | dspcntr |= DISPPLANE_BGRX101010; |
2718 | break; | |
2719 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2720 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2721 | break; |
2722 | default: | |
baba133a | 2723 | BUG(); |
81255565 | 2724 | } |
57779d06 | 2725 | |
f45651ba VS |
2726 | if (INTEL_INFO(dev)->gen >= 4 && |
2727 | obj->tiling_mode != I915_TILING_NONE) | |
2728 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2729 | |
de1aa629 VS |
2730 | if (IS_G4X(dev)) |
2731 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2732 | ||
b9897127 | 2733 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2734 | |
c2c75131 DV |
2735 | if (INTEL_INFO(dev)->gen >= 4) { |
2736 | intel_crtc->dspaddr_offset = | |
bc752862 | 2737 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2738 | pixel_size, |
bc752862 | 2739 | fb->pitches[0]); |
c2c75131 DV |
2740 | linear_offset -= intel_crtc->dspaddr_offset; |
2741 | } else { | |
e506a0c6 | 2742 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2743 | } |
e506a0c6 | 2744 | |
8e7d688b | 2745 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2746 | dspcntr |= DISPPLANE_ROTATE_180; |
2747 | ||
6e3c9717 ACO |
2748 | x += (intel_crtc->config->pipe_src_w - 1); |
2749 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2750 | |
2751 | /* Finding the last pixel of the last line of the display | |
2752 | data and adding to linear_offset*/ | |
2753 | linear_offset += | |
6e3c9717 ACO |
2754 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2755 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2756 | } |
2757 | ||
2758 | I915_WRITE(reg, dspcntr); | |
2759 | ||
01f2c773 | 2760 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2761 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2762 | I915_WRITE(DSPSURF(plane), |
2763 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2764 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2765 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2766 | } else |
f343c5f6 | 2767 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2768 | POSTING_READ(reg); |
17638cd6 JB |
2769 | } |
2770 | ||
29b9bde6 DV |
2771 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2772 | struct drm_framebuffer *fb, | |
2773 | int x, int y) | |
17638cd6 JB |
2774 | { |
2775 | struct drm_device *dev = crtc->dev; | |
2776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2778 | struct drm_plane *primary = crtc->primary; |
2779 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2780 | struct drm_i915_gem_object *obj; |
17638cd6 | 2781 | int plane = intel_crtc->plane; |
e506a0c6 | 2782 | unsigned long linear_offset; |
17638cd6 | 2783 | u32 dspcntr; |
f45651ba | 2784 | u32 reg = DSPCNTR(plane); |
48404c1e | 2785 | int pixel_size; |
f45651ba | 2786 | |
b70709a6 | 2787 | if (!visible || !fb) { |
fdd508a6 VS |
2788 | I915_WRITE(reg, 0); |
2789 | I915_WRITE(DSPSURF(plane), 0); | |
2790 | POSTING_READ(reg); | |
2791 | return; | |
2792 | } | |
2793 | ||
c9ba6fad VS |
2794 | obj = intel_fb_obj(fb); |
2795 | if (WARN_ON(obj == NULL)) | |
2796 | return; | |
2797 | ||
2798 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2799 | ||
f45651ba VS |
2800 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2801 | ||
fdd508a6 | 2802 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2803 | |
2804 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2805 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2806 | |
57779d06 VS |
2807 | switch (fb->pixel_format) { |
2808 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2809 | dspcntr |= DISPPLANE_8BPP; |
2810 | break; | |
57779d06 VS |
2811 | case DRM_FORMAT_RGB565: |
2812 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2813 | break; |
57779d06 VS |
2814 | case DRM_FORMAT_XRGB8888: |
2815 | case DRM_FORMAT_ARGB8888: | |
2816 | dspcntr |= DISPPLANE_BGRX888; | |
2817 | break; | |
2818 | case DRM_FORMAT_XBGR8888: | |
2819 | case DRM_FORMAT_ABGR8888: | |
2820 | dspcntr |= DISPPLANE_RGBX888; | |
2821 | break; | |
2822 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2823 | dspcntr |= DISPPLANE_BGRX101010; |
2824 | break; | |
2825 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2826 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2827 | break; |
2828 | default: | |
baba133a | 2829 | BUG(); |
17638cd6 JB |
2830 | } |
2831 | ||
2832 | if (obj->tiling_mode != I915_TILING_NONE) | |
2833 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2834 | |
f45651ba | 2835 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2836 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2837 | |
b9897127 | 2838 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2839 | intel_crtc->dspaddr_offset = |
bc752862 | 2840 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2841 | pixel_size, |
bc752862 | 2842 | fb->pitches[0]); |
c2c75131 | 2843 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2844 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2845 | dspcntr |= DISPPLANE_ROTATE_180; |
2846 | ||
2847 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2848 | x += (intel_crtc->config->pipe_src_w - 1); |
2849 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2850 | |
2851 | /* Finding the last pixel of the last line of the display | |
2852 | data and adding to linear_offset*/ | |
2853 | linear_offset += | |
6e3c9717 ACO |
2854 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2855 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2856 | } |
2857 | } | |
2858 | ||
2859 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2860 | |
01f2c773 | 2861 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2862 | I915_WRITE(DSPSURF(plane), |
2863 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2864 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2865 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2866 | } else { | |
2867 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2868 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2869 | } | |
17638cd6 | 2870 | POSTING_READ(reg); |
17638cd6 JB |
2871 | } |
2872 | ||
b321803d DL |
2873 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2874 | uint32_t pixel_format) | |
2875 | { | |
2876 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2877 | ||
2878 | /* | |
2879 | * The stride is either expressed as a multiple of 64 bytes | |
2880 | * chunks for linear buffers or in number of tiles for tiled | |
2881 | * buffers. | |
2882 | */ | |
2883 | switch (fb_modifier) { | |
2884 | case DRM_FORMAT_MOD_NONE: | |
2885 | return 64; | |
2886 | case I915_FORMAT_MOD_X_TILED: | |
2887 | if (INTEL_INFO(dev)->gen == 2) | |
2888 | return 128; | |
2889 | return 512; | |
2890 | case I915_FORMAT_MOD_Y_TILED: | |
2891 | /* No need to check for old gens and Y tiling since this is | |
2892 | * about the display engine and those will be blocked before | |
2893 | * we get here. | |
2894 | */ | |
2895 | return 128; | |
2896 | case I915_FORMAT_MOD_Yf_TILED: | |
2897 | if (bits_per_pixel == 8) | |
2898 | return 64; | |
2899 | else | |
2900 | return 128; | |
2901 | default: | |
2902 | MISSING_CASE(fb_modifier); | |
2903 | return 64; | |
2904 | } | |
2905 | } | |
2906 | ||
121920fa TU |
2907 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2908 | struct drm_i915_gem_object *obj) | |
2909 | { | |
9abc4648 | 2910 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2911 | |
2912 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2913 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2914 | |
2915 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2916 | } | |
2917 | ||
a1b2278e CK |
2918 | /* |
2919 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2920 | */ | |
2921 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2922 | { | |
2923 | struct drm_device *dev; | |
2924 | struct drm_i915_private *dev_priv; | |
2925 | struct intel_crtc_scaler_state *scaler_state; | |
2926 | int i; | |
2927 | ||
2928 | if (!intel_crtc || !intel_crtc->config) | |
2929 | return; | |
2930 | ||
2931 | dev = intel_crtc->base.dev; | |
2932 | dev_priv = dev->dev_private; | |
2933 | scaler_state = &intel_crtc->config->scaler_state; | |
2934 | ||
2935 | /* loop through and disable scalers that aren't in use */ | |
2936 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2937 | if (!scaler_state->scalers[i].in_use) { | |
2938 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2939 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2940 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2941 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2942 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2943 | } | |
2944 | } | |
2945 | } | |
2946 | ||
6156a456 | 2947 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2948 | { |
6156a456 | 2949 | switch (pixel_format) { |
d161cf7a | 2950 | case DRM_FORMAT_C8: |
c34ce3d1 | 2951 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2952 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2953 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2954 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2955 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2956 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2957 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2958 | /* |
2959 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2960 | * to be already pre-multiplied. We need to add a knob (or a different | |
2961 | * DRM_FORMAT) for user-space to configure that. | |
2962 | */ | |
f75fb42a | 2963 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2964 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2965 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2966 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2967 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2968 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2969 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2970 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2971 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2972 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2973 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2974 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2975 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2976 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2977 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2978 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2979 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2980 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2981 | default: |
4249eeef | 2982 | MISSING_CASE(pixel_format); |
70d21f0e | 2983 | } |
8cfcba41 | 2984 | |
c34ce3d1 | 2985 | return 0; |
6156a456 | 2986 | } |
70d21f0e | 2987 | |
6156a456 CK |
2988 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2989 | { | |
6156a456 | 2990 | switch (fb_modifier) { |
30af77c4 | 2991 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2992 | break; |
30af77c4 | 2993 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2994 | return PLANE_CTL_TILED_X; |
b321803d | 2995 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2996 | return PLANE_CTL_TILED_Y; |
b321803d | 2997 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2998 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2999 | default: |
6156a456 | 3000 | MISSING_CASE(fb_modifier); |
70d21f0e | 3001 | } |
8cfcba41 | 3002 | |
c34ce3d1 | 3003 | return 0; |
6156a456 | 3004 | } |
70d21f0e | 3005 | |
6156a456 CK |
3006 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3007 | { | |
3b7a5119 | 3008 | switch (rotation) { |
6156a456 CK |
3009 | case BIT(DRM_ROTATE_0): |
3010 | break; | |
3b7a5119 | 3011 | case BIT(DRM_ROTATE_90): |
c34ce3d1 | 3012 | return PLANE_CTL_ROTATE_90; |
3b7a5119 | 3013 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3014 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3015 | case BIT(DRM_ROTATE_270): |
c34ce3d1 | 3016 | return PLANE_CTL_ROTATE_270; |
6156a456 CK |
3017 | default: |
3018 | MISSING_CASE(rotation); | |
3019 | } | |
3020 | ||
c34ce3d1 | 3021 | return 0; |
6156a456 CK |
3022 | } |
3023 | ||
3024 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3025 | struct drm_framebuffer *fb, | |
3026 | int x, int y) | |
3027 | { | |
3028 | struct drm_device *dev = crtc->dev; | |
3029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3031 | struct drm_plane *plane = crtc->primary; |
3032 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3033 | struct drm_i915_gem_object *obj; |
3034 | int pipe = intel_crtc->pipe; | |
3035 | u32 plane_ctl, stride_div, stride; | |
3036 | u32 tile_height, plane_offset, plane_size; | |
3037 | unsigned int rotation; | |
3038 | int x_offset, y_offset; | |
3039 | unsigned long surf_addr; | |
6156a456 CK |
3040 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3041 | struct intel_plane_state *plane_state; | |
3042 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3043 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3044 | int scaler_id = -1; | |
3045 | ||
6156a456 CK |
3046 | plane_state = to_intel_plane_state(plane->state); |
3047 | ||
b70709a6 | 3048 | if (!visible || !fb) { |
6156a456 CK |
3049 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3050 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3051 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3052 | return; | |
3b7a5119 | 3053 | } |
70d21f0e | 3054 | |
6156a456 CK |
3055 | plane_ctl = PLANE_CTL_ENABLE | |
3056 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3057 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3058 | ||
3059 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3060 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3061 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3062 | ||
3063 | rotation = plane->state->rotation; | |
3064 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3065 | ||
b321803d DL |
3066 | obj = intel_fb_obj(fb); |
3067 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3068 | fb->pixel_format); | |
3b7a5119 SJ |
3069 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3070 | ||
6156a456 CK |
3071 | /* |
3072 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3073 | * update_plane helpers are called from legacy paths. | |
3074 | * Once full atomic crtc is available, below check can be avoided. | |
3075 | */ | |
3076 | if (drm_rect_width(&plane_state->src)) { | |
3077 | scaler_id = plane_state->scaler_id; | |
3078 | src_x = plane_state->src.x1 >> 16; | |
3079 | src_y = plane_state->src.y1 >> 16; | |
3080 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3081 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3082 | dst_x = plane_state->dst.x1; | |
3083 | dst_y = plane_state->dst.y1; | |
3084 | dst_w = drm_rect_width(&plane_state->dst); | |
3085 | dst_h = drm_rect_height(&plane_state->dst); | |
3086 | ||
3087 | WARN_ON(x != src_x || y != src_y); | |
3088 | } else { | |
3089 | src_w = intel_crtc->config->pipe_src_w; | |
3090 | src_h = intel_crtc->config->pipe_src_h; | |
3091 | } | |
3092 | ||
3b7a5119 SJ |
3093 | if (intel_rotation_90_or_270(rotation)) { |
3094 | /* stride = Surface height in tiles */ | |
2614f17d | 3095 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3b7a5119 SJ |
3096 | fb->modifier[0]); |
3097 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3098 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3099 | y_offset = x; |
6156a456 | 3100 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3101 | } else { |
3102 | stride = fb->pitches[0] / stride_div; | |
3103 | x_offset = x; | |
3104 | y_offset = y; | |
6156a456 | 3105 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3106 | } |
3107 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3108 | |
70d21f0e | 3109 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3110 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3111 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3112 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3113 | |
3114 | if (scaler_id >= 0) { | |
3115 | uint32_t ps_ctrl = 0; | |
3116 | ||
3117 | WARN_ON(!dst_w || !dst_h); | |
3118 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3119 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3120 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3121 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3122 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3123 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3124 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3125 | } else { | |
3126 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3127 | } | |
3128 | ||
121920fa | 3129 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3130 | |
3131 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3132 | } | |
3133 | ||
17638cd6 JB |
3134 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3135 | static int | |
3136 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3137 | int x, int y, enum mode_set_atomic state) | |
3138 | { | |
3139 | struct drm_device *dev = crtc->dev; | |
3140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3141 | |
6b8e6ed0 CW |
3142 | if (dev_priv->display.disable_fbc) |
3143 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3144 | |
29b9bde6 DV |
3145 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3146 | ||
3147 | return 0; | |
81255565 JB |
3148 | } |
3149 | ||
7514747d | 3150 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3151 | { |
96a02917 VS |
3152 | struct drm_crtc *crtc; |
3153 | ||
70e1e0ec | 3154 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3156 | enum plane plane = intel_crtc->plane; | |
3157 | ||
3158 | intel_prepare_page_flip(dev, plane); | |
3159 | intel_finish_page_flip_plane(dev, plane); | |
3160 | } | |
7514747d VS |
3161 | } |
3162 | ||
3163 | static void intel_update_primary_planes(struct drm_device *dev) | |
3164 | { | |
3165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3166 | struct drm_crtc *crtc; | |
96a02917 | 3167 | |
70e1e0ec | 3168 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3170 | ||
51fd371b | 3171 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3172 | /* |
3173 | * FIXME: Once we have proper support for primary planes (and | |
3174 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3175 | * a NULL crtc->primary->fb. |
947fdaad | 3176 | */ |
f4510a27 | 3177 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3178 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3179 | crtc->primary->fb, |
262ca2b0 MR |
3180 | crtc->x, |
3181 | crtc->y); | |
51fd371b | 3182 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3183 | } |
3184 | } | |
3185 | ||
ce22dba9 ML |
3186 | void intel_crtc_reset(struct intel_crtc *crtc) |
3187 | { | |
3188 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
3189 | ||
3190 | if (!crtc->active) | |
3191 | return; | |
3192 | ||
3193 | intel_crtc_disable_planes(&crtc->base); | |
3194 | dev_priv->display.crtc_disable(&crtc->base); | |
3195 | dev_priv->display.crtc_enable(&crtc->base); | |
3196 | intel_crtc_enable_planes(&crtc->base); | |
3197 | } | |
3198 | ||
7514747d VS |
3199 | void intel_prepare_reset(struct drm_device *dev) |
3200 | { | |
f98ce92f VS |
3201 | struct drm_i915_private *dev_priv = to_i915(dev); |
3202 | struct intel_crtc *crtc; | |
3203 | ||
7514747d VS |
3204 | /* no reset support for gen2 */ |
3205 | if (IS_GEN2(dev)) | |
3206 | return; | |
3207 | ||
3208 | /* reset doesn't touch the display */ | |
3209 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3210 | return; | |
3211 | ||
3212 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3213 | |
3214 | /* | |
3215 | * Disabling the crtcs gracefully seems nicer. Also the | |
3216 | * g33 docs say we should at least disable all the planes. | |
3217 | */ | |
3218 | for_each_intel_crtc(dev, crtc) { | |
ce22dba9 ML |
3219 | if (!crtc->active) |
3220 | continue; | |
3221 | ||
3222 | intel_crtc_disable_planes(&crtc->base); | |
3223 | dev_priv->display.crtc_disable(&crtc->base); | |
f98ce92f | 3224 | } |
7514747d VS |
3225 | } |
3226 | ||
3227 | void intel_finish_reset(struct drm_device *dev) | |
3228 | { | |
3229 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3230 | ||
3231 | /* | |
3232 | * Flips in the rings will be nuked by the reset, | |
3233 | * so complete all pending flips so that user space | |
3234 | * will get its events and not get stuck. | |
3235 | */ | |
3236 | intel_complete_page_flips(dev); | |
3237 | ||
3238 | /* no reset support for gen2 */ | |
3239 | if (IS_GEN2(dev)) | |
3240 | return; | |
3241 | ||
3242 | /* reset doesn't touch the display */ | |
3243 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3244 | /* | |
3245 | * Flips in the rings have been nuked by the reset, | |
3246 | * so update the base address of all primary | |
3247 | * planes to the the last fb to make sure we're | |
3248 | * showing the correct fb after a reset. | |
3249 | */ | |
3250 | intel_update_primary_planes(dev); | |
3251 | return; | |
3252 | } | |
3253 | ||
3254 | /* | |
3255 | * The display has been reset as well, | |
3256 | * so need a full re-initialization. | |
3257 | */ | |
3258 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3259 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3260 | ||
3261 | intel_modeset_init_hw(dev); | |
3262 | ||
3263 | spin_lock_irq(&dev_priv->irq_lock); | |
3264 | if (dev_priv->display.hpd_irq_setup) | |
3265 | dev_priv->display.hpd_irq_setup(dev); | |
3266 | spin_unlock_irq(&dev_priv->irq_lock); | |
3267 | ||
3268 | intel_modeset_setup_hw_state(dev, true); | |
3269 | ||
3270 | intel_hpd_init(dev_priv); | |
3271 | ||
3272 | drm_modeset_unlock_all(dev); | |
3273 | } | |
3274 | ||
2e2f351d | 3275 | static void |
14667a4b CW |
3276 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3277 | { | |
2ff8fde1 | 3278 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3279 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3280 | bool was_interruptible = dev_priv->mm.interruptible; |
3281 | int ret; | |
3282 | ||
14667a4b CW |
3283 | /* Big Hammer, we also need to ensure that any pending |
3284 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3285 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3286 | * framebuffer. Note that we rely on userspace rendering |
3287 | * into the buffer attached to the pipe they are waiting | |
3288 | * on. If not, userspace generates a GPU hang with IPEHR | |
3289 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3290 | * |
3291 | * This should only fail upon a hung GPU, in which case we | |
3292 | * can safely continue. | |
3293 | */ | |
3294 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3295 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3296 | dev_priv->mm.interruptible = was_interruptible; |
3297 | ||
2e2f351d | 3298 | WARN_ON(ret); |
14667a4b CW |
3299 | } |
3300 | ||
7d5e3799 CW |
3301 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3302 | { | |
3303 | struct drm_device *dev = crtc->dev; | |
3304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3306 | bool pending; |
3307 | ||
3308 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3309 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3310 | return false; | |
3311 | ||
5e2d7afc | 3312 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3313 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3314 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3315 | |
3316 | return pending; | |
3317 | } | |
3318 | ||
e30e8f75 GP |
3319 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3320 | { | |
3321 | struct drm_device *dev = crtc->base.dev; | |
3322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3323 | const struct drm_display_mode *adjusted_mode; | |
3324 | ||
3325 | if (!i915.fastboot) | |
3326 | return; | |
3327 | ||
3328 | /* | |
3329 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3330 | * that in compute_mode_changes we check the native mode (not the pfit | |
3331 | * mode) to see if we can flip rather than do a full mode set. In the | |
3332 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3333 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3334 | * sized surface. | |
3335 | * | |
3336 | * To fix this properly, we need to hoist the checks up into | |
3337 | * compute_mode_changes (or above), check the actual pfit state and | |
3338 | * whether the platform allows pfit disable with pipe active, and only | |
3339 | * then update the pipesrc and pfit state, even on the flip path. | |
3340 | */ | |
3341 | ||
6e3c9717 | 3342 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3343 | |
3344 | I915_WRITE(PIPESRC(crtc->pipe), | |
3345 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3346 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3347 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3348 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3349 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3350 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3351 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3352 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3353 | } | |
6e3c9717 ACO |
3354 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3355 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3356 | } |
3357 | ||
5e84e1a4 ZW |
3358 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3359 | { | |
3360 | struct drm_device *dev = crtc->dev; | |
3361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3363 | int pipe = intel_crtc->pipe; | |
3364 | u32 reg, temp; | |
3365 | ||
3366 | /* enable normal train */ | |
3367 | reg = FDI_TX_CTL(pipe); | |
3368 | temp = I915_READ(reg); | |
61e499bf | 3369 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3370 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3371 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3372 | } else { |
3373 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3374 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3375 | } |
5e84e1a4 ZW |
3376 | I915_WRITE(reg, temp); |
3377 | ||
3378 | reg = FDI_RX_CTL(pipe); | |
3379 | temp = I915_READ(reg); | |
3380 | if (HAS_PCH_CPT(dev)) { | |
3381 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3382 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3383 | } else { | |
3384 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3385 | temp |= FDI_LINK_TRAIN_NONE; | |
3386 | } | |
3387 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3388 | ||
3389 | /* wait one idle pattern time */ | |
3390 | POSTING_READ(reg); | |
3391 | udelay(1000); | |
357555c0 JB |
3392 | |
3393 | /* IVB wants error correction enabled */ | |
3394 | if (IS_IVYBRIDGE(dev)) | |
3395 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3396 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3397 | } |
3398 | ||
8db9d77b ZW |
3399 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3400 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3401 | { | |
3402 | struct drm_device *dev = crtc->dev; | |
3403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3404 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3405 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3406 | u32 reg, temp, tries; |
8db9d77b | 3407 | |
1c8562f6 | 3408 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3409 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3410 | |
e1a44743 AJ |
3411 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3412 | for train result */ | |
5eddb70b CW |
3413 | reg = FDI_RX_IMR(pipe); |
3414 | temp = I915_READ(reg); | |
e1a44743 AJ |
3415 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3416 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3417 | I915_WRITE(reg, temp); |
3418 | I915_READ(reg); | |
e1a44743 AJ |
3419 | udelay(150); |
3420 | ||
8db9d77b | 3421 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3422 | reg = FDI_TX_CTL(pipe); |
3423 | temp = I915_READ(reg); | |
627eb5a3 | 3424 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3425 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3426 | temp &= ~FDI_LINK_TRAIN_NONE; |
3427 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3428 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3429 | |
5eddb70b CW |
3430 | reg = FDI_RX_CTL(pipe); |
3431 | temp = I915_READ(reg); | |
8db9d77b ZW |
3432 | temp &= ~FDI_LINK_TRAIN_NONE; |
3433 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3434 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3435 | ||
3436 | POSTING_READ(reg); | |
8db9d77b ZW |
3437 | udelay(150); |
3438 | ||
5b2adf89 | 3439 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3440 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3441 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3442 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3443 | |
5eddb70b | 3444 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3445 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3446 | temp = I915_READ(reg); |
8db9d77b ZW |
3447 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3448 | ||
3449 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3450 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3451 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3452 | break; |
3453 | } | |
8db9d77b | 3454 | } |
e1a44743 | 3455 | if (tries == 5) |
5eddb70b | 3456 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3457 | |
3458 | /* Train 2 */ | |
5eddb70b CW |
3459 | reg = FDI_TX_CTL(pipe); |
3460 | temp = I915_READ(reg); | |
8db9d77b ZW |
3461 | temp &= ~FDI_LINK_TRAIN_NONE; |
3462 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3463 | I915_WRITE(reg, temp); |
8db9d77b | 3464 | |
5eddb70b CW |
3465 | reg = FDI_RX_CTL(pipe); |
3466 | temp = I915_READ(reg); | |
8db9d77b ZW |
3467 | temp &= ~FDI_LINK_TRAIN_NONE; |
3468 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3469 | I915_WRITE(reg, temp); |
8db9d77b | 3470 | |
5eddb70b CW |
3471 | POSTING_READ(reg); |
3472 | udelay(150); | |
8db9d77b | 3473 | |
5eddb70b | 3474 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3475 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3476 | temp = I915_READ(reg); |
8db9d77b ZW |
3477 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3478 | ||
3479 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3480 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3481 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3482 | break; | |
3483 | } | |
8db9d77b | 3484 | } |
e1a44743 | 3485 | if (tries == 5) |
5eddb70b | 3486 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3487 | |
3488 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3489 | |
8db9d77b ZW |
3490 | } |
3491 | ||
0206e353 | 3492 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3493 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3494 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3495 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3496 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3497 | }; | |
3498 | ||
3499 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3500 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3501 | { | |
3502 | struct drm_device *dev = crtc->dev; | |
3503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3505 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3506 | u32 reg, temp, i, retry; |
8db9d77b | 3507 | |
e1a44743 AJ |
3508 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3509 | for train result */ | |
5eddb70b CW |
3510 | reg = FDI_RX_IMR(pipe); |
3511 | temp = I915_READ(reg); | |
e1a44743 AJ |
3512 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3513 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3514 | I915_WRITE(reg, temp); |
3515 | ||
3516 | POSTING_READ(reg); | |
e1a44743 AJ |
3517 | udelay(150); |
3518 | ||
8db9d77b | 3519 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3520 | reg = FDI_TX_CTL(pipe); |
3521 | temp = I915_READ(reg); | |
627eb5a3 | 3522 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3523 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3524 | temp &= ~FDI_LINK_TRAIN_NONE; |
3525 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3526 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3527 | /* SNB-B */ | |
3528 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3529 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3530 | |
d74cf324 DV |
3531 | I915_WRITE(FDI_RX_MISC(pipe), |
3532 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3533 | ||
5eddb70b CW |
3534 | reg = FDI_RX_CTL(pipe); |
3535 | temp = I915_READ(reg); | |
8db9d77b ZW |
3536 | if (HAS_PCH_CPT(dev)) { |
3537 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3538 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3539 | } else { | |
3540 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3541 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3542 | } | |
5eddb70b CW |
3543 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3544 | ||
3545 | POSTING_READ(reg); | |
8db9d77b ZW |
3546 | udelay(150); |
3547 | ||
0206e353 | 3548 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3549 | reg = FDI_TX_CTL(pipe); |
3550 | temp = I915_READ(reg); | |
8db9d77b ZW |
3551 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3552 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3553 | I915_WRITE(reg, temp); |
3554 | ||
3555 | POSTING_READ(reg); | |
8db9d77b ZW |
3556 | udelay(500); |
3557 | ||
fa37d39e SP |
3558 | for (retry = 0; retry < 5; retry++) { |
3559 | reg = FDI_RX_IIR(pipe); | |
3560 | temp = I915_READ(reg); | |
3561 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3562 | if (temp & FDI_RX_BIT_LOCK) { | |
3563 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3564 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3565 | break; | |
3566 | } | |
3567 | udelay(50); | |
8db9d77b | 3568 | } |
fa37d39e SP |
3569 | if (retry < 5) |
3570 | break; | |
8db9d77b ZW |
3571 | } |
3572 | if (i == 4) | |
5eddb70b | 3573 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3574 | |
3575 | /* Train 2 */ | |
5eddb70b CW |
3576 | reg = FDI_TX_CTL(pipe); |
3577 | temp = I915_READ(reg); | |
8db9d77b ZW |
3578 | temp &= ~FDI_LINK_TRAIN_NONE; |
3579 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3580 | if (IS_GEN6(dev)) { | |
3581 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3582 | /* SNB-B */ | |
3583 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3584 | } | |
5eddb70b | 3585 | I915_WRITE(reg, temp); |
8db9d77b | 3586 | |
5eddb70b CW |
3587 | reg = FDI_RX_CTL(pipe); |
3588 | temp = I915_READ(reg); | |
8db9d77b ZW |
3589 | if (HAS_PCH_CPT(dev)) { |
3590 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3591 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3592 | } else { | |
3593 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3594 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3595 | } | |
5eddb70b CW |
3596 | I915_WRITE(reg, temp); |
3597 | ||
3598 | POSTING_READ(reg); | |
8db9d77b ZW |
3599 | udelay(150); |
3600 | ||
0206e353 | 3601 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3602 | reg = FDI_TX_CTL(pipe); |
3603 | temp = I915_READ(reg); | |
8db9d77b ZW |
3604 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3605 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3606 | I915_WRITE(reg, temp); |
3607 | ||
3608 | POSTING_READ(reg); | |
8db9d77b ZW |
3609 | udelay(500); |
3610 | ||
fa37d39e SP |
3611 | for (retry = 0; retry < 5; retry++) { |
3612 | reg = FDI_RX_IIR(pipe); | |
3613 | temp = I915_READ(reg); | |
3614 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3615 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3616 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3617 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3618 | break; | |
3619 | } | |
3620 | udelay(50); | |
8db9d77b | 3621 | } |
fa37d39e SP |
3622 | if (retry < 5) |
3623 | break; | |
8db9d77b ZW |
3624 | } |
3625 | if (i == 4) | |
5eddb70b | 3626 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3627 | |
3628 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3629 | } | |
3630 | ||
357555c0 JB |
3631 | /* Manual link training for Ivy Bridge A0 parts */ |
3632 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3633 | { | |
3634 | struct drm_device *dev = crtc->dev; | |
3635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3637 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3638 | u32 reg, temp, i, j; |
357555c0 JB |
3639 | |
3640 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3641 | for train result */ | |
3642 | reg = FDI_RX_IMR(pipe); | |
3643 | temp = I915_READ(reg); | |
3644 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3645 | temp &= ~FDI_RX_BIT_LOCK; | |
3646 | I915_WRITE(reg, temp); | |
3647 | ||
3648 | POSTING_READ(reg); | |
3649 | udelay(150); | |
3650 | ||
01a415fd DV |
3651 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3652 | I915_READ(FDI_RX_IIR(pipe))); | |
3653 | ||
139ccd3f JB |
3654 | /* Try each vswing and preemphasis setting twice before moving on */ |
3655 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3656 | /* disable first in case we need to retry */ | |
3657 | reg = FDI_TX_CTL(pipe); | |
3658 | temp = I915_READ(reg); | |
3659 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3660 | temp &= ~FDI_TX_ENABLE; | |
3661 | I915_WRITE(reg, temp); | |
357555c0 | 3662 | |
139ccd3f JB |
3663 | reg = FDI_RX_CTL(pipe); |
3664 | temp = I915_READ(reg); | |
3665 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3666 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3667 | temp &= ~FDI_RX_ENABLE; | |
3668 | I915_WRITE(reg, temp); | |
357555c0 | 3669 | |
139ccd3f | 3670 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3671 | reg = FDI_TX_CTL(pipe); |
3672 | temp = I915_READ(reg); | |
139ccd3f | 3673 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3674 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3675 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3676 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3677 | temp |= snb_b_fdi_train_param[j/2]; |
3678 | temp |= FDI_COMPOSITE_SYNC; | |
3679 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3680 | |
139ccd3f JB |
3681 | I915_WRITE(FDI_RX_MISC(pipe), |
3682 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3683 | |
139ccd3f | 3684 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3685 | temp = I915_READ(reg); |
139ccd3f JB |
3686 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3687 | temp |= FDI_COMPOSITE_SYNC; | |
3688 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3689 | |
139ccd3f JB |
3690 | POSTING_READ(reg); |
3691 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3692 | |
139ccd3f JB |
3693 | for (i = 0; i < 4; i++) { |
3694 | reg = FDI_RX_IIR(pipe); | |
3695 | temp = I915_READ(reg); | |
3696 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3697 | |
139ccd3f JB |
3698 | if (temp & FDI_RX_BIT_LOCK || |
3699 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3700 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3701 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3702 | i); | |
3703 | break; | |
3704 | } | |
3705 | udelay(1); /* should be 0.5us */ | |
3706 | } | |
3707 | if (i == 4) { | |
3708 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3709 | continue; | |
3710 | } | |
357555c0 | 3711 | |
139ccd3f | 3712 | /* Train 2 */ |
357555c0 JB |
3713 | reg = FDI_TX_CTL(pipe); |
3714 | temp = I915_READ(reg); | |
139ccd3f JB |
3715 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3716 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3717 | I915_WRITE(reg, temp); | |
3718 | ||
3719 | reg = FDI_RX_CTL(pipe); | |
3720 | temp = I915_READ(reg); | |
3721 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3722 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3723 | I915_WRITE(reg, temp); |
3724 | ||
3725 | POSTING_READ(reg); | |
139ccd3f | 3726 | udelay(2); /* should be 1.5us */ |
357555c0 | 3727 | |
139ccd3f JB |
3728 | for (i = 0; i < 4; i++) { |
3729 | reg = FDI_RX_IIR(pipe); | |
3730 | temp = I915_READ(reg); | |
3731 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3732 | |
139ccd3f JB |
3733 | if (temp & FDI_RX_SYMBOL_LOCK || |
3734 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3735 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3736 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3737 | i); | |
3738 | goto train_done; | |
3739 | } | |
3740 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3741 | } |
139ccd3f JB |
3742 | if (i == 4) |
3743 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3744 | } |
357555c0 | 3745 | |
139ccd3f | 3746 | train_done: |
357555c0 JB |
3747 | DRM_DEBUG_KMS("FDI train done.\n"); |
3748 | } | |
3749 | ||
88cefb6c | 3750 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3751 | { |
88cefb6c | 3752 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3753 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3754 | int pipe = intel_crtc->pipe; |
5eddb70b | 3755 | u32 reg, temp; |
79e53945 | 3756 | |
c64e311e | 3757 | |
c98e9dcf | 3758 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3759 | reg = FDI_RX_CTL(pipe); |
3760 | temp = I915_READ(reg); | |
627eb5a3 | 3761 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3762 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3763 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3764 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3765 | ||
3766 | POSTING_READ(reg); | |
c98e9dcf JB |
3767 | udelay(200); |
3768 | ||
3769 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3770 | temp = I915_READ(reg); |
3771 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3772 | ||
3773 | POSTING_READ(reg); | |
c98e9dcf JB |
3774 | udelay(200); |
3775 | ||
20749730 PZ |
3776 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3777 | reg = FDI_TX_CTL(pipe); | |
3778 | temp = I915_READ(reg); | |
3779 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3780 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3781 | |
20749730 PZ |
3782 | POSTING_READ(reg); |
3783 | udelay(100); | |
6be4a607 | 3784 | } |
0e23b99d JB |
3785 | } |
3786 | ||
88cefb6c DV |
3787 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3788 | { | |
3789 | struct drm_device *dev = intel_crtc->base.dev; | |
3790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3791 | int pipe = intel_crtc->pipe; | |
3792 | u32 reg, temp; | |
3793 | ||
3794 | /* Switch from PCDclk to Rawclk */ | |
3795 | reg = FDI_RX_CTL(pipe); | |
3796 | temp = I915_READ(reg); | |
3797 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3798 | ||
3799 | /* Disable CPU FDI TX PLL */ | |
3800 | reg = FDI_TX_CTL(pipe); | |
3801 | temp = I915_READ(reg); | |
3802 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3803 | ||
3804 | POSTING_READ(reg); | |
3805 | udelay(100); | |
3806 | ||
3807 | reg = FDI_RX_CTL(pipe); | |
3808 | temp = I915_READ(reg); | |
3809 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3810 | ||
3811 | /* Wait for the clocks to turn off. */ | |
3812 | POSTING_READ(reg); | |
3813 | udelay(100); | |
3814 | } | |
3815 | ||
0fc932b8 JB |
3816 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3817 | { | |
3818 | struct drm_device *dev = crtc->dev; | |
3819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3821 | int pipe = intel_crtc->pipe; | |
3822 | u32 reg, temp; | |
3823 | ||
3824 | /* disable CPU FDI tx and PCH FDI rx */ | |
3825 | reg = FDI_TX_CTL(pipe); | |
3826 | temp = I915_READ(reg); | |
3827 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3828 | POSTING_READ(reg); | |
3829 | ||
3830 | reg = FDI_RX_CTL(pipe); | |
3831 | temp = I915_READ(reg); | |
3832 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3833 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3834 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3835 | ||
3836 | POSTING_READ(reg); | |
3837 | udelay(100); | |
3838 | ||
3839 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3840 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3841 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3842 | |
3843 | /* still set train pattern 1 */ | |
3844 | reg = FDI_TX_CTL(pipe); | |
3845 | temp = I915_READ(reg); | |
3846 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3847 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3848 | I915_WRITE(reg, temp); | |
3849 | ||
3850 | reg = FDI_RX_CTL(pipe); | |
3851 | temp = I915_READ(reg); | |
3852 | if (HAS_PCH_CPT(dev)) { | |
3853 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3854 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3855 | } else { | |
3856 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3857 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3858 | } | |
3859 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3860 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3861 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3862 | I915_WRITE(reg, temp); |
3863 | ||
3864 | POSTING_READ(reg); | |
3865 | udelay(100); | |
3866 | } | |
3867 | ||
5dce5b93 CW |
3868 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3869 | { | |
3870 | struct intel_crtc *crtc; | |
3871 | ||
3872 | /* Note that we don't need to be called with mode_config.lock here | |
3873 | * as our list of CRTC objects is static for the lifetime of the | |
3874 | * device and so cannot disappear as we iterate. Similarly, we can | |
3875 | * happily treat the predicates as racy, atomic checks as userspace | |
3876 | * cannot claim and pin a new fb without at least acquring the | |
3877 | * struct_mutex and so serialising with us. | |
3878 | */ | |
d3fcc808 | 3879 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3880 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3881 | continue; | |
3882 | ||
3883 | if (crtc->unpin_work) | |
3884 | intel_wait_for_vblank(dev, crtc->pipe); | |
3885 | ||
3886 | return true; | |
3887 | } | |
3888 | ||
3889 | return false; | |
3890 | } | |
3891 | ||
d6bbafa1 CW |
3892 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3893 | { | |
3894 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3895 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3896 | ||
3897 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3898 | smp_rmb(); | |
3899 | intel_crtc->unpin_work = NULL; | |
3900 | ||
3901 | if (work->event) | |
3902 | drm_send_vblank_event(intel_crtc->base.dev, | |
3903 | intel_crtc->pipe, | |
3904 | work->event); | |
3905 | ||
3906 | drm_crtc_vblank_put(&intel_crtc->base); | |
3907 | ||
3908 | wake_up_all(&dev_priv->pending_flip_queue); | |
3909 | queue_work(dev_priv->wq, &work->work); | |
3910 | ||
3911 | trace_i915_flip_complete(intel_crtc->plane, | |
3912 | work->pending_flip_obj); | |
3913 | } | |
3914 | ||
46a55d30 | 3915 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3916 | { |
0f91128d | 3917 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3918 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3919 | |
2c10d571 | 3920 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3921 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3922 | !intel_crtc_has_pending_flip(crtc), | |
3923 | 60*HZ) == 0)) { | |
3924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3925 | |
5e2d7afc | 3926 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3927 | if (intel_crtc->unpin_work) { |
3928 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3929 | page_flip_completed(intel_crtc); | |
3930 | } | |
5e2d7afc | 3931 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3932 | } |
5bb61643 | 3933 | |
975d568a CW |
3934 | if (crtc->primary->fb) { |
3935 | mutex_lock(&dev->struct_mutex); | |
3936 | intel_finish_fb(crtc->primary->fb); | |
3937 | mutex_unlock(&dev->struct_mutex); | |
3938 | } | |
e6c3a2a6 CW |
3939 | } |
3940 | ||
e615efe4 ED |
3941 | /* Program iCLKIP clock to the desired frequency */ |
3942 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3943 | { | |
3944 | struct drm_device *dev = crtc->dev; | |
3945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3946 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3947 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3948 | u32 temp; | |
3949 | ||
09153000 DV |
3950 | mutex_lock(&dev_priv->dpio_lock); |
3951 | ||
e615efe4 ED |
3952 | /* It is necessary to ungate the pixclk gate prior to programming |
3953 | * the divisors, and gate it back when it is done. | |
3954 | */ | |
3955 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3956 | ||
3957 | /* Disable SSCCTL */ | |
3958 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3959 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3960 | SBI_SSCCTL_DISABLE, | |
3961 | SBI_ICLK); | |
e615efe4 ED |
3962 | |
3963 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3964 | if (clock == 20000) { |
e615efe4 ED |
3965 | auxdiv = 1; |
3966 | divsel = 0x41; | |
3967 | phaseinc = 0x20; | |
3968 | } else { | |
3969 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3970 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3971 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3972 | * convert the virtual clock precision to KHz here for higher |
3973 | * precision. | |
3974 | */ | |
3975 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3976 | u32 iclk_pi_range = 64; | |
3977 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3978 | ||
12d7ceed | 3979 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3980 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3981 | pi_value = desired_divisor % iclk_pi_range; | |
3982 | ||
3983 | auxdiv = 0; | |
3984 | divsel = msb_divisor_value - 2; | |
3985 | phaseinc = pi_value; | |
3986 | } | |
3987 | ||
3988 | /* This should not happen with any sane values */ | |
3989 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3990 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3991 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3992 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3993 | ||
3994 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3995 | clock, |
e615efe4 ED |
3996 | auxdiv, |
3997 | divsel, | |
3998 | phasedir, | |
3999 | phaseinc); | |
4000 | ||
4001 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 4002 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4003 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4004 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4005 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4006 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4007 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4008 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4009 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4010 | |
4011 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4012 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4013 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4014 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4015 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4016 | |
4017 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4018 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4019 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4020 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4021 | |
4022 | /* Wait for initialization time */ | |
4023 | udelay(24); | |
4024 | ||
4025 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
4026 | |
4027 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
4028 | } |
4029 | ||
275f01b2 DV |
4030 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4031 | enum pipe pch_transcoder) | |
4032 | { | |
4033 | struct drm_device *dev = crtc->base.dev; | |
4034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4035 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4036 | |
4037 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4038 | I915_READ(HTOTAL(cpu_transcoder))); | |
4039 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4040 | I915_READ(HBLANK(cpu_transcoder))); | |
4041 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4042 | I915_READ(HSYNC(cpu_transcoder))); | |
4043 | ||
4044 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4045 | I915_READ(VTOTAL(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4047 | I915_READ(VBLANK(cpu_transcoder))); | |
4048 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4049 | I915_READ(VSYNC(cpu_transcoder))); | |
4050 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4051 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4052 | } | |
4053 | ||
003632d9 | 4054 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4055 | { |
4056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4057 | uint32_t temp; | |
4058 | ||
4059 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4060 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4061 | return; |
4062 | ||
4063 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4064 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4065 | ||
003632d9 ACO |
4066 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4067 | if (enable) | |
4068 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4069 | ||
4070 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4071 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4072 | POSTING_READ(SOUTH_CHICKEN1); | |
4073 | } | |
4074 | ||
4075 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4076 | { | |
4077 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4078 | |
4079 | switch (intel_crtc->pipe) { | |
4080 | case PIPE_A: | |
4081 | break; | |
4082 | case PIPE_B: | |
6e3c9717 | 4083 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4084 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4085 | else |
003632d9 | 4086 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4087 | |
4088 | break; | |
4089 | case PIPE_C: | |
003632d9 | 4090 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4091 | |
4092 | break; | |
4093 | default: | |
4094 | BUG(); | |
4095 | } | |
4096 | } | |
4097 | ||
f67a559d JB |
4098 | /* |
4099 | * Enable PCH resources required for PCH ports: | |
4100 | * - PCH PLLs | |
4101 | * - FDI training & RX/TX | |
4102 | * - update transcoder timings | |
4103 | * - DP transcoding bits | |
4104 | * - transcoder | |
4105 | */ | |
4106 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4107 | { |
4108 | struct drm_device *dev = crtc->dev; | |
4109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4111 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4112 | u32 reg, temp; |
2c07245f | 4113 | |
ab9412ba | 4114 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4115 | |
1fbc0d78 DV |
4116 | if (IS_IVYBRIDGE(dev)) |
4117 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4118 | ||
cd986abb DV |
4119 | /* Write the TU size bits before fdi link training, so that error |
4120 | * detection works. */ | |
4121 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4122 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4123 | ||
c98e9dcf | 4124 | /* For PCH output, training FDI link */ |
674cf967 | 4125 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4126 | |
3ad8a208 DV |
4127 | /* We need to program the right clock selection before writing the pixel |
4128 | * mutliplier into the DPLL. */ | |
303b81e0 | 4129 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4130 | u32 sel; |
4b645f14 | 4131 | |
c98e9dcf | 4132 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4133 | temp |= TRANS_DPLL_ENABLE(pipe); |
4134 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4135 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4136 | temp |= sel; |
4137 | else | |
4138 | temp &= ~sel; | |
c98e9dcf | 4139 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4140 | } |
5eddb70b | 4141 | |
3ad8a208 DV |
4142 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4143 | * transcoder, and we actually should do this to not upset any PCH | |
4144 | * transcoder that already use the clock when we share it. | |
4145 | * | |
4146 | * Note that enable_shared_dpll tries to do the right thing, but | |
4147 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4148 | * the right LVDS enable sequence. */ | |
85b3894f | 4149 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4150 | |
d9b6cb56 JB |
4151 | /* set transcoder timing, panel must allow it */ |
4152 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4153 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4154 | |
303b81e0 | 4155 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4156 | |
c98e9dcf | 4157 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4158 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4159 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4160 | reg = TRANS_DP_CTL(pipe); |
4161 | temp = I915_READ(reg); | |
4162 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4163 | TRANS_DP_SYNC_MASK | |
4164 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4165 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4166 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4167 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4168 | |
4169 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4170 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4171 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4172 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4173 | |
4174 | switch (intel_trans_dp_port_sel(crtc)) { | |
4175 | case PCH_DP_B: | |
5eddb70b | 4176 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4177 | break; |
4178 | case PCH_DP_C: | |
5eddb70b | 4179 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4180 | break; |
4181 | case PCH_DP_D: | |
5eddb70b | 4182 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4183 | break; |
4184 | default: | |
e95d41e1 | 4185 | BUG(); |
32f9d658 | 4186 | } |
2c07245f | 4187 | |
5eddb70b | 4188 | I915_WRITE(reg, temp); |
6be4a607 | 4189 | } |
b52eb4dc | 4190 | |
b8a4f404 | 4191 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4192 | } |
4193 | ||
1507e5bd PZ |
4194 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4195 | { | |
4196 | struct drm_device *dev = crtc->dev; | |
4197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4199 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4200 | |
ab9412ba | 4201 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4202 | |
8c52b5e8 | 4203 | lpt_program_iclkip(crtc); |
1507e5bd | 4204 | |
0540e488 | 4205 | /* Set transcoder timing. */ |
275f01b2 | 4206 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4207 | |
937bb610 | 4208 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4209 | } |
4210 | ||
716c2e55 | 4211 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4212 | { |
e2b78267 | 4213 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4214 | |
4215 | if (pll == NULL) | |
4216 | return; | |
4217 | ||
3e369b76 | 4218 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4219 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4220 | return; |
4221 | } | |
4222 | ||
3e369b76 ACO |
4223 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4224 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4225 | WARN_ON(pll->on); |
4226 | WARN_ON(pll->active); | |
4227 | } | |
4228 | ||
6e3c9717 | 4229 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4230 | } |
4231 | ||
190f68c5 ACO |
4232 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4233 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4234 | { |
e2b78267 | 4235 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4236 | struct intel_shared_dpll *pll; |
e2b78267 | 4237 | enum intel_dpll_id i; |
ee7b9f93 | 4238 | |
98b6bd99 DV |
4239 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4240 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4241 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4242 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4243 | |
46edb027 DV |
4244 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4245 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4246 | |
8bd31e67 | 4247 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4248 | |
98b6bd99 DV |
4249 | goto found; |
4250 | } | |
4251 | ||
bcddf610 S |
4252 | if (IS_BROXTON(dev_priv->dev)) { |
4253 | /* PLL is attached to port in bxt */ | |
4254 | struct intel_encoder *encoder; | |
4255 | struct intel_digital_port *intel_dig_port; | |
4256 | ||
4257 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4258 | if (WARN_ON(!encoder)) | |
4259 | return NULL; | |
4260 | ||
4261 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4262 | /* 1:1 mapping between ports and PLLs */ | |
4263 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4264 | pll = &dev_priv->shared_dplls[i]; | |
4265 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4266 | crtc->base.base.id, pll->name); | |
4267 | WARN_ON(pll->new_config->crtc_mask); | |
4268 | ||
4269 | goto found; | |
4270 | } | |
4271 | ||
e72f9fbf DV |
4272 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4273 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4274 | |
4275 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4276 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4277 | continue; |
4278 | ||
190f68c5 | 4279 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4280 | &pll->new_config->hw_state, |
4281 | sizeof(pll->new_config->hw_state)) == 0) { | |
4282 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4283 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4284 | pll->new_config->crtc_mask, |
4285 | pll->active); | |
ee7b9f93 JB |
4286 | goto found; |
4287 | } | |
4288 | } | |
4289 | ||
4290 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4291 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4292 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4293 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4294 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4295 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4296 | goto found; |
4297 | } | |
4298 | } | |
4299 | ||
4300 | return NULL; | |
4301 | ||
4302 | found: | |
8bd31e67 | 4303 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4304 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4305 | |
190f68c5 | 4306 | crtc_state->shared_dpll = i; |
46edb027 DV |
4307 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4308 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4309 | |
8bd31e67 | 4310 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4311 | |
ee7b9f93 JB |
4312 | return pll; |
4313 | } | |
4314 | ||
8bd31e67 ACO |
4315 | /** |
4316 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4317 | * @dev_priv: DRM device | |
4318 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4319 | * | |
4320 | * Starts a new PLL staged config, copying the current config but | |
4321 | * releasing the references of pipes specified in clear_pipes. | |
4322 | */ | |
4323 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4324 | unsigned clear_pipes) | |
4325 | { | |
4326 | struct intel_shared_dpll *pll; | |
4327 | enum intel_dpll_id i; | |
4328 | ||
4329 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4330 | pll = &dev_priv->shared_dplls[i]; | |
4331 | ||
4332 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4333 | GFP_KERNEL); | |
4334 | if (!pll->new_config) | |
4335 | goto cleanup; | |
4336 | ||
4337 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4338 | } | |
4339 | ||
4340 | return 0; | |
4341 | ||
4342 | cleanup: | |
4343 | while (--i >= 0) { | |
4344 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4345 | kfree(pll->new_config); |
8bd31e67 ACO |
4346 | pll->new_config = NULL; |
4347 | } | |
4348 | ||
4349 | return -ENOMEM; | |
4350 | } | |
4351 | ||
4352 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4353 | { | |
4354 | struct intel_shared_dpll *pll; | |
4355 | enum intel_dpll_id i; | |
4356 | ||
4357 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4358 | pll = &dev_priv->shared_dplls[i]; | |
4359 | ||
4360 | WARN_ON(pll->new_config == &pll->config); | |
4361 | ||
4362 | pll->config = *pll->new_config; | |
4363 | kfree(pll->new_config); | |
4364 | pll->new_config = NULL; | |
4365 | } | |
4366 | } | |
4367 | ||
4368 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4369 | { | |
4370 | struct intel_shared_dpll *pll; | |
4371 | enum intel_dpll_id i; | |
4372 | ||
4373 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4374 | pll = &dev_priv->shared_dplls[i]; | |
4375 | ||
4376 | WARN_ON(pll->new_config == &pll->config); | |
4377 | ||
4378 | kfree(pll->new_config); | |
4379 | pll->new_config = NULL; | |
4380 | } | |
4381 | } | |
4382 | ||
a1520318 | 4383 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4384 | { |
4385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4386 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4387 | u32 temp; |
4388 | ||
4389 | temp = I915_READ(dslreg); | |
4390 | udelay(500); | |
4391 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4392 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4393 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4394 | } |
4395 | } | |
4396 | ||
a1b2278e CK |
4397 | /** |
4398 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4399 | * @intel_crtc: crtc | |
4400 | * @crtc_state: crtc_state | |
4401 | * @plane: plane (NULL indicates crtc is requesting update) | |
4402 | * @plane_state: plane's state | |
4403 | * @force_detach: request unconditional detachment of scaler | |
4404 | * | |
4405 | * This function updates scaler state for requested plane or crtc. | |
4406 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4407 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4408 | * as NULL. | |
4409 | * | |
4410 | * Return | |
4411 | * 0 - scaler_usage updated successfully | |
4412 | * error - requested scaling cannot be supported or other error condition | |
4413 | */ | |
4414 | int | |
4415 | skl_update_scaler_users( | |
4416 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4417 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4418 | int force_detach) | |
4419 | { | |
4420 | int need_scaling; | |
4421 | int idx; | |
4422 | int src_w, src_h, dst_w, dst_h; | |
4423 | int *scaler_id; | |
4424 | struct drm_framebuffer *fb; | |
4425 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4426 | unsigned int rotation; |
a1b2278e CK |
4427 | |
4428 | if (!intel_crtc || !crtc_state) | |
4429 | return 0; | |
4430 | ||
4431 | scaler_state = &crtc_state->scaler_state; | |
4432 | ||
4433 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4434 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4435 | ||
4436 | if (intel_plane) { | |
4437 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4438 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4439 | dst_w = drm_rect_width(&plane_state->dst); | |
4440 | dst_h = drm_rect_height(&plane_state->dst); | |
4441 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4442 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4443 | } else { |
4444 | struct drm_display_mode *adjusted_mode = | |
4445 | &crtc_state->base.adjusted_mode; | |
4446 | src_w = crtc_state->pipe_src_w; | |
4447 | src_h = crtc_state->pipe_src_h; | |
4448 | dst_w = adjusted_mode->hdisplay; | |
4449 | dst_h = adjusted_mode->vdisplay; | |
4450 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4451 | rotation = DRM_ROTATE_0; |
a1b2278e | 4452 | } |
6156a456 CK |
4453 | |
4454 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4455 | (src_h != dst_w || src_w != dst_h): | |
4456 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4457 | |
4458 | /* | |
4459 | * if plane is being disabled or scaler is no more required or force detach | |
4460 | * - free scaler binded to this plane/crtc | |
4461 | * - in order to do this, update crtc->scaler_usage | |
4462 | * | |
4463 | * Here scaler state in crtc_state is set free so that | |
4464 | * scaler can be assigned to other user. Actual register | |
4465 | * update to free the scaler is done in plane/panel-fit programming. | |
4466 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4467 | */ | |
4468 | if (force_detach || !need_scaling || (intel_plane && | |
4469 | (!fb || !plane_state->visible))) { | |
4470 | if (*scaler_id >= 0) { | |
4471 | scaler_state->scaler_users &= ~(1 << idx); | |
4472 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4473 | ||
4474 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4475 | "crtc_state = %p scaler_users = 0x%x\n", | |
4476 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4477 | intel_plane ? intel_plane->base.base.id : | |
4478 | intel_crtc->base.base.id, crtc_state, | |
4479 | scaler_state->scaler_users); | |
4480 | *scaler_id = -1; | |
4481 | } | |
4482 | return 0; | |
4483 | } | |
4484 | ||
4485 | /* range checks */ | |
4486 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4487 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4488 | ||
4489 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4490 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4491 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4492 | "size is out of scaler range\n", | |
4493 | intel_plane ? "PLANE" : "CRTC", | |
4494 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4495 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4496 | return -EINVAL; | |
4497 | } | |
4498 | ||
4499 | /* check colorkey */ | |
4500 | if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4501 | DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", | |
4502 | intel_plane->base.base.id); | |
4503 | return -EINVAL; | |
4504 | } | |
4505 | ||
4506 | /* Check src format */ | |
4507 | if (intel_plane) { | |
4508 | switch (fb->pixel_format) { | |
4509 | case DRM_FORMAT_RGB565: | |
4510 | case DRM_FORMAT_XBGR8888: | |
4511 | case DRM_FORMAT_XRGB8888: | |
4512 | case DRM_FORMAT_ABGR8888: | |
4513 | case DRM_FORMAT_ARGB8888: | |
4514 | case DRM_FORMAT_XRGB2101010: | |
a1b2278e | 4515 | case DRM_FORMAT_XBGR2101010: |
a1b2278e CK |
4516 | case DRM_FORMAT_YUYV: |
4517 | case DRM_FORMAT_YVYU: | |
4518 | case DRM_FORMAT_UYVY: | |
4519 | case DRM_FORMAT_VYUY: | |
4520 | break; | |
4521 | default: | |
4522 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4523 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4524 | return -EINVAL; | |
4525 | } | |
4526 | } | |
4527 | ||
4528 | /* mark this plane as a scaler user in crtc_state */ | |
4529 | scaler_state->scaler_users |= (1 << idx); | |
4530 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4531 | "crtc_state = %p scaler_users = 0x%x\n", | |
4532 | intel_plane ? "PLANE" : "CRTC", | |
4533 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4534 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4535 | return 0; | |
4536 | } | |
4537 | ||
4538 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4539 | { |
4540 | struct drm_device *dev = crtc->base.dev; | |
4541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4542 | int pipe = crtc->pipe; | |
a1b2278e CK |
4543 | struct intel_crtc_scaler_state *scaler_state = |
4544 | &crtc->config->scaler_state; | |
4545 | ||
4546 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4547 | ||
4548 | /* To update pfit, first update scaler state */ | |
4549 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4550 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4551 | skl_detach_scalers(crtc); | |
4552 | if (!enable) | |
4553 | return; | |
bd2e244f | 4554 | |
6e3c9717 | 4555 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4556 | int id; |
4557 | ||
4558 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4559 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4560 | return; | |
4561 | } | |
4562 | ||
4563 | id = scaler_state->scaler_id; | |
4564 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4565 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4566 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4567 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4568 | ||
4569 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4570 | } |
4571 | } | |
4572 | ||
b074cec8 JB |
4573 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4574 | { | |
4575 | struct drm_device *dev = crtc->base.dev; | |
4576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4577 | int pipe = crtc->pipe; | |
4578 | ||
6e3c9717 | 4579 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4580 | /* Force use of hard-coded filter coefficients |
4581 | * as some pre-programmed values are broken, | |
4582 | * e.g. x201. | |
4583 | */ | |
4584 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4585 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4586 | PF_PIPE_SEL_IVB(pipe)); | |
4587 | else | |
4588 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4589 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4590 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4591 | } |
4592 | } | |
4593 | ||
4a3b8769 | 4594 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4595 | { |
4596 | struct drm_device *dev = crtc->dev; | |
4597 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4598 | struct drm_plane *plane; |
bb53d4ae VS |
4599 | struct intel_plane *intel_plane; |
4600 | ||
af2b653b MR |
4601 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4602 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4603 | if (intel_plane->pipe == pipe) |
4604 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4605 | } |
bb53d4ae VS |
4606 | } |
4607 | ||
20bc8673 | 4608 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4609 | { |
cea165c3 VS |
4610 | struct drm_device *dev = crtc->base.dev; |
4611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4612 | |
6e3c9717 | 4613 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4614 | return; |
4615 | ||
cea165c3 VS |
4616 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4617 | intel_wait_for_vblank(dev, crtc->pipe); | |
4618 | ||
d77e4531 | 4619 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4620 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4621 | mutex_lock(&dev_priv->rps.hw_lock); |
4622 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4623 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4624 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4625 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4626 | * mailbox." Moreover, the mailbox may return a bogus state, |
4627 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4628 | */ |
4629 | } else { | |
4630 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4631 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4632 | * is essentially intel_wait_for_vblank. If we don't have this | |
4633 | * and don't wait for vblanks until the end of crtc_enable, then | |
4634 | * the HW state readout code will complain that the expected | |
4635 | * IPS_CTL value is not the one we read. */ | |
4636 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4637 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4638 | } | |
d77e4531 PZ |
4639 | } |
4640 | ||
20bc8673 | 4641 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4642 | { |
4643 | struct drm_device *dev = crtc->base.dev; | |
4644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4645 | ||
6e3c9717 | 4646 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4647 | return; |
4648 | ||
4649 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4650 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4651 | mutex_lock(&dev_priv->rps.hw_lock); |
4652 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4653 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4654 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4655 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4656 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4657 | } else { |
2a114cc1 | 4658 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4659 | POSTING_READ(IPS_CTL); |
4660 | } | |
d77e4531 PZ |
4661 | |
4662 | /* We need to wait for a vblank before we can disable the plane. */ | |
4663 | intel_wait_for_vblank(dev, crtc->pipe); | |
4664 | } | |
4665 | ||
4666 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4667 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4668 | { | |
4669 | struct drm_device *dev = crtc->dev; | |
4670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4672 | enum pipe pipe = intel_crtc->pipe; | |
4673 | int palreg = PALETTE(pipe); | |
4674 | int i; | |
4675 | bool reenable_ips = false; | |
4676 | ||
4677 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4678 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4679 | return; |
4680 | ||
50360403 | 4681 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4682 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4683 | assert_dsi_pll_enabled(dev_priv); |
4684 | else | |
4685 | assert_pll_enabled(dev_priv, pipe); | |
4686 | } | |
4687 | ||
4688 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4689 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4690 | palreg = LGC_PALETTE(pipe); |
4691 | ||
4692 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4693 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4694 | */ | |
6e3c9717 | 4695 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4696 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4697 | GAMMA_MODE_MODE_SPLIT)) { | |
4698 | hsw_disable_ips(intel_crtc); | |
4699 | reenable_ips = true; | |
4700 | } | |
4701 | ||
4702 | for (i = 0; i < 256; i++) { | |
4703 | I915_WRITE(palreg + 4 * i, | |
4704 | (intel_crtc->lut_r[i] << 16) | | |
4705 | (intel_crtc->lut_g[i] << 8) | | |
4706 | intel_crtc->lut_b[i]); | |
4707 | } | |
4708 | ||
4709 | if (reenable_ips) | |
4710 | hsw_enable_ips(intel_crtc); | |
4711 | } | |
4712 | ||
7cac945f | 4713 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4714 | { |
7cac945f | 4715 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4716 | struct drm_device *dev = intel_crtc->base.dev; |
4717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4718 | ||
4719 | mutex_lock(&dev->struct_mutex); | |
4720 | dev_priv->mm.interruptible = false; | |
4721 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4722 | dev_priv->mm.interruptible = true; | |
4723 | mutex_unlock(&dev->struct_mutex); | |
4724 | } | |
4725 | ||
4726 | /* Let userspace switch the overlay on again. In most cases userspace | |
4727 | * has to recompute where to put it anyway. | |
4728 | */ | |
4729 | } | |
4730 | ||
87d4300a ML |
4731 | /** |
4732 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4733 | * @crtc: the CRTC whose primary plane was just enabled | |
4734 | * | |
4735 | * Performs potentially sleeping operations that must be done after the primary | |
4736 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4737 | * called due to an explicit primary plane update, or due to an implicit | |
4738 | * re-enable that is caused when a sprite plane is updated to no longer | |
4739 | * completely hide the primary plane. | |
4740 | */ | |
4741 | static void | |
4742 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4743 | { |
4744 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4745 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4747 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4748 | |
87d4300a ML |
4749 | /* |
4750 | * BDW signals flip done immediately if the plane | |
4751 | * is disabled, even if the plane enable is already | |
4752 | * armed to occur at the next vblank :( | |
4753 | */ | |
4754 | if (IS_BROADWELL(dev)) | |
4755 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4756 | |
87d4300a ML |
4757 | /* |
4758 | * FIXME IPS should be fine as long as one plane is | |
4759 | * enabled, but in practice it seems to have problems | |
4760 | * when going from primary only to sprite only and vice | |
4761 | * versa. | |
4762 | */ | |
a5c4d7bc VS |
4763 | hsw_enable_ips(intel_crtc); |
4764 | ||
4765 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4766 | intel_fbc_update(dev); |
a5c4d7bc | 4767 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4768 | |
4769 | /* | |
87d4300a ML |
4770 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4771 | * So don't enable underrun reporting before at least some planes | |
4772 | * are enabled. | |
4773 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4774 | * but leave the pipe running. | |
f99d7069 | 4775 | */ |
87d4300a ML |
4776 | if (IS_GEN2(dev)) |
4777 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4778 | ||
4779 | /* Underruns don't raise interrupts, so check manually. */ | |
4780 | if (HAS_GMCH_DISPLAY(dev)) | |
4781 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4782 | } |
4783 | ||
87d4300a ML |
4784 | /** |
4785 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4786 | * @crtc: the CRTC whose primary plane is to be disabled | |
4787 | * | |
4788 | * Performs potentially sleeping operations that must be done before the | |
4789 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4790 | * be called due to an explicit primary plane update, or due to an implicit | |
4791 | * disable that is caused when a sprite plane completely hides the primary | |
4792 | * plane. | |
4793 | */ | |
4794 | static void | |
4795 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4796 | { |
4797 | struct drm_device *dev = crtc->dev; | |
4798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4799 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4800 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4801 | |
87d4300a ML |
4802 | /* |
4803 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4804 | * So diasble underrun reporting before all the planes get disabled. | |
4805 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4806 | * but leave the pipe running. | |
4807 | */ | |
4808 | if (IS_GEN2(dev)) | |
4809 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4810 | |
87d4300a ML |
4811 | /* |
4812 | * Vblank time updates from the shadow to live plane control register | |
4813 | * are blocked if the memory self-refresh mode is active at that | |
4814 | * moment. So to make sure the plane gets truly disabled, disable | |
4815 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4816 | * will be checked/applied by the HW only at the next frame start | |
4817 | * event which is after the vblank start event, so we need to have a | |
4818 | * wait-for-vblank between disabling the plane and the pipe. | |
4819 | */ | |
4820 | if (HAS_GMCH_DISPLAY(dev)) | |
4821 | intel_set_memory_cxsr(dev_priv, false); | |
4822 | ||
4823 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 4824 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4825 | intel_fbc_disable(dev); |
87d4300a | 4826 | mutex_unlock(&dev->struct_mutex); |
a5c4d7bc | 4827 | |
87d4300a ML |
4828 | /* |
4829 | * FIXME IPS should be fine as long as one plane is | |
4830 | * enabled, but in practice it seems to have problems | |
4831 | * when going from primary only to sprite only and vice | |
4832 | * versa. | |
4833 | */ | |
a5c4d7bc | 4834 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4835 | } |
4836 | ||
4837 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
4838 | { | |
87d4300a ML |
4839 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4840 | intel_enable_sprite_planes(crtc); | |
4841 | intel_crtc_update_cursor(crtc, true); | |
87d4300a ML |
4842 | |
4843 | intel_post_enable_primary(crtc); | |
4844 | } | |
4845 | ||
4846 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |
4847 | { | |
4848 | struct drm_device *dev = crtc->dev; | |
4849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4850 | struct intel_plane *intel_plane; | |
4851 | int pipe = intel_crtc->pipe; | |
4852 | ||
4853 | intel_crtc_wait_for_pending_flips(crtc); | |
4854 | ||
4855 | intel_pre_disable_primary(crtc); | |
a5c4d7bc | 4856 | |
7cac945f | 4857 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 ML |
4858 | for_each_intel_plane(dev, intel_plane) { |
4859 | if (intel_plane->pipe == pipe) { | |
4860 | struct drm_crtc *from = intel_plane->base.crtc; | |
4861 | ||
4862 | intel_plane->disable_plane(&intel_plane->base, | |
4863 | from ?: crtc, true); | |
4864 | } | |
4865 | } | |
f98551ae | 4866 | |
f99d7069 DV |
4867 | /* |
4868 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4869 | * to compute the mask of flip planes precisely. For the time being | |
4870 | * consider this a flip to a NULL plane. | |
4871 | */ | |
4872 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4873 | } |
4874 | ||
f67a559d JB |
4875 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4876 | { | |
4877 | struct drm_device *dev = crtc->dev; | |
4878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4880 | struct intel_encoder *encoder; |
f67a559d | 4881 | int pipe = intel_crtc->pipe; |
f67a559d | 4882 | |
83d65738 | 4883 | WARN_ON(!crtc->state->enable); |
08a48469 | 4884 | |
f67a559d JB |
4885 | if (intel_crtc->active) |
4886 | return; | |
4887 | ||
6e3c9717 | 4888 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4889 | intel_prepare_shared_dpll(intel_crtc); |
4890 | ||
6e3c9717 | 4891 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4892 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4893 | |
4894 | intel_set_pipe_timings(intel_crtc); | |
4895 | ||
6e3c9717 | 4896 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4897 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4898 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4899 | } |
4900 | ||
4901 | ironlake_set_pipeconf(crtc); | |
4902 | ||
f67a559d | 4903 | intel_crtc->active = true; |
8664281b | 4904 | |
a72e4c9f DV |
4905 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4906 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4907 | |
f6736a1a | 4908 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4909 | if (encoder->pre_enable) |
4910 | encoder->pre_enable(encoder); | |
f67a559d | 4911 | |
6e3c9717 | 4912 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4913 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4914 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4915 | * enabling. */ | |
88cefb6c | 4916 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4917 | } else { |
4918 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4919 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4920 | } | |
f67a559d | 4921 | |
b074cec8 | 4922 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4923 | |
9c54c0dd JB |
4924 | /* |
4925 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4926 | * clocks enabled | |
4927 | */ | |
4928 | intel_crtc_load_lut(crtc); | |
4929 | ||
f37fcc2a | 4930 | intel_update_watermarks(crtc); |
e1fdc473 | 4931 | intel_enable_pipe(intel_crtc); |
f67a559d | 4932 | |
6e3c9717 | 4933 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4934 | ironlake_pch_enable(crtc); |
c98e9dcf | 4935 | |
f9b61ff6 DV |
4936 | assert_vblank_disabled(crtc); |
4937 | drm_crtc_vblank_on(crtc); | |
4938 | ||
fa5c73b1 DV |
4939 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4940 | encoder->enable(encoder); | |
61b77ddd DV |
4941 | |
4942 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4943 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4944 | } |
4945 | ||
42db64ef PZ |
4946 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4947 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4948 | { | |
f5adf94e | 4949 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4950 | } |
4951 | ||
e4916946 PZ |
4952 | /* |
4953 | * This implements the workaround described in the "notes" section of the mode | |
4954 | * set sequence documentation. When going from no pipes or single pipe to | |
4955 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4956 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4957 | */ | |
4958 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4959 | { | |
4960 | struct drm_device *dev = crtc->base.dev; | |
4961 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4962 | ||
4963 | /* We want to get the other_active_crtc only if there's only 1 other | |
4964 | * active crtc. */ | |
d3fcc808 | 4965 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4966 | if (!crtc_it->active || crtc_it == crtc) |
4967 | continue; | |
4968 | ||
4969 | if (other_active_crtc) | |
4970 | return; | |
4971 | ||
4972 | other_active_crtc = crtc_it; | |
4973 | } | |
4974 | if (!other_active_crtc) | |
4975 | return; | |
4976 | ||
4977 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4978 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4979 | } | |
4980 | ||
4f771f10 PZ |
4981 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4982 | { | |
4983 | struct drm_device *dev = crtc->dev; | |
4984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4986 | struct intel_encoder *encoder; | |
4987 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4988 | |
83d65738 | 4989 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4990 | |
4991 | if (intel_crtc->active) | |
4992 | return; | |
4993 | ||
df8ad70c DV |
4994 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4995 | intel_enable_shared_dpll(intel_crtc); | |
4996 | ||
6e3c9717 | 4997 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4998 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4999 | |
5000 | intel_set_pipe_timings(intel_crtc); | |
5001 | ||
6e3c9717 ACO |
5002 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5003 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5004 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5005 | } |
5006 | ||
6e3c9717 | 5007 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5008 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5009 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5010 | } |
5011 | ||
5012 | haswell_set_pipeconf(crtc); | |
5013 | ||
5014 | intel_set_pipe_csc(crtc); | |
5015 | ||
4f771f10 | 5016 | intel_crtc->active = true; |
8664281b | 5017 | |
a72e4c9f | 5018 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
5019 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5020 | if (encoder->pre_enable) | |
5021 | encoder->pre_enable(encoder); | |
5022 | ||
6e3c9717 | 5023 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
5024 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5025 | true); | |
4fe9467d ID |
5026 | dev_priv->display.fdi_link_train(crtc); |
5027 | } | |
5028 | ||
1f544388 | 5029 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5030 | |
ff6d9f55 | 5031 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5032 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 5033 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5034 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
5035 | else |
5036 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
5037 | |
5038 | /* | |
5039 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5040 | * clocks enabled | |
5041 | */ | |
5042 | intel_crtc_load_lut(crtc); | |
5043 | ||
1f544388 | 5044 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 5045 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5046 | |
f37fcc2a | 5047 | intel_update_watermarks(crtc); |
e1fdc473 | 5048 | intel_enable_pipe(intel_crtc); |
42db64ef | 5049 | |
6e3c9717 | 5050 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5051 | lpt_pch_enable(crtc); |
4f771f10 | 5052 | |
6e3c9717 | 5053 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5054 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5055 | ||
f9b61ff6 DV |
5056 | assert_vblank_disabled(crtc); |
5057 | drm_crtc_vblank_on(crtc); | |
5058 | ||
8807e55b | 5059 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5060 | encoder->enable(encoder); |
8807e55b JN |
5061 | intel_opregion_notify_encoder(encoder, true); |
5062 | } | |
4f771f10 | 5063 | |
e4916946 PZ |
5064 | /* If we change the relative order between pipe/planes enabling, we need |
5065 | * to change the workaround. */ | |
5066 | haswell_mode_set_planes_workaround(intel_crtc); | |
4f771f10 PZ |
5067 | } |
5068 | ||
3f8dce3a DV |
5069 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5070 | { | |
5071 | struct drm_device *dev = crtc->base.dev; | |
5072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5073 | int pipe = crtc->pipe; | |
5074 | ||
5075 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5076 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5077 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5078 | I915_WRITE(PF_CTL(pipe), 0); |
5079 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5080 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5081 | } | |
5082 | } | |
5083 | ||
6be4a607 JB |
5084 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5085 | { | |
5086 | struct drm_device *dev = crtc->dev; | |
5087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5089 | struct intel_encoder *encoder; |
6be4a607 | 5090 | int pipe = intel_crtc->pipe; |
5eddb70b | 5091 | u32 reg, temp; |
b52eb4dc | 5092 | |
f7abfe8b CW |
5093 | if (!intel_crtc->active) |
5094 | return; | |
5095 | ||
ea9d758d DV |
5096 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5097 | encoder->disable(encoder); | |
5098 | ||
f9b61ff6 DV |
5099 | drm_crtc_vblank_off(crtc); |
5100 | assert_vblank_disabled(crtc); | |
5101 | ||
6e3c9717 | 5102 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5103 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5104 | |
575f7ab7 | 5105 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5106 | |
3f8dce3a | 5107 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5108 | |
bf49ec8c DV |
5109 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5110 | if (encoder->post_disable) | |
5111 | encoder->post_disable(encoder); | |
2c07245f | 5112 | |
6e3c9717 | 5113 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5114 | ironlake_fdi_disable(crtc); |
913d8d11 | 5115 | |
d925c59a | 5116 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5117 | |
d925c59a DV |
5118 | if (HAS_PCH_CPT(dev)) { |
5119 | /* disable TRANS_DP_CTL */ | |
5120 | reg = TRANS_DP_CTL(pipe); | |
5121 | temp = I915_READ(reg); | |
5122 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5123 | TRANS_DP_PORT_SEL_MASK); | |
5124 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5125 | I915_WRITE(reg, temp); | |
5126 | ||
5127 | /* disable DPLL_SEL */ | |
5128 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5129 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5130 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5131 | } |
e3421a18 | 5132 | |
d925c59a | 5133 | /* disable PCH DPLL */ |
e72f9fbf | 5134 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5135 | |
d925c59a DV |
5136 | ironlake_fdi_pll_disable(intel_crtc); |
5137 | } | |
6b383a7f | 5138 | |
f7abfe8b | 5139 | intel_crtc->active = false; |
46ba614c | 5140 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5141 | |
5142 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5143 | intel_fbc_update(dev); |
d1ebd816 | 5144 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5145 | } |
1b3c7a47 | 5146 | |
4f771f10 | 5147 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5148 | { |
4f771f10 PZ |
5149 | struct drm_device *dev = crtc->dev; |
5150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5151 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5152 | struct intel_encoder *encoder; |
6e3c9717 | 5153 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5154 | |
4f771f10 PZ |
5155 | if (!intel_crtc->active) |
5156 | return; | |
5157 | ||
8807e55b JN |
5158 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5159 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5160 | encoder->disable(encoder); |
8807e55b | 5161 | } |
4f771f10 | 5162 | |
f9b61ff6 DV |
5163 | drm_crtc_vblank_off(crtc); |
5164 | assert_vblank_disabled(crtc); | |
5165 | ||
6e3c9717 | 5166 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5167 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5168 | false); | |
575f7ab7 | 5169 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5170 | |
6e3c9717 | 5171 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5172 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5173 | ||
ad80a810 | 5174 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5175 | |
ff6d9f55 | 5176 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5177 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5178 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5179 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5180 | else |
5181 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5182 | |
1f544388 | 5183 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5184 | |
6e3c9717 | 5185 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5186 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5187 | intel_ddi_fdi_disable(crtc); |
83616634 | 5188 | } |
4f771f10 | 5189 | |
97b040aa ID |
5190 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5191 | if (encoder->post_disable) | |
5192 | encoder->post_disable(encoder); | |
5193 | ||
4f771f10 | 5194 | intel_crtc->active = false; |
46ba614c | 5195 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5196 | |
5197 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5198 | intel_fbc_update(dev); |
4f771f10 | 5199 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5200 | |
5201 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5202 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5203 | } |
5204 | ||
ee7b9f93 JB |
5205 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5206 | { | |
5207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5208 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5209 | } |
5210 | ||
6441ab5f | 5211 | |
2dd24552 JB |
5212 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5213 | { | |
5214 | struct drm_device *dev = crtc->base.dev; | |
5215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5216 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5217 | |
681a8504 | 5218 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5219 | return; |
5220 | ||
2dd24552 | 5221 | /* |
c0b03411 DV |
5222 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5223 | * according to register description and PRM. | |
2dd24552 | 5224 | */ |
c0b03411 DV |
5225 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5226 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5227 | |
b074cec8 JB |
5228 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5229 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5230 | |
5231 | /* Border color in case we don't scale up to the full screen. Black by | |
5232 | * default, change to something else for debugging. */ | |
5233 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5234 | } |
5235 | ||
d05410f9 DA |
5236 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5237 | { | |
5238 | switch (port) { | |
5239 | case PORT_A: | |
5240 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5241 | case PORT_B: | |
5242 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5243 | case PORT_C: | |
5244 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5245 | case PORT_D: | |
5246 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5247 | default: | |
5248 | WARN_ON_ONCE(1); | |
5249 | return POWER_DOMAIN_PORT_OTHER; | |
5250 | } | |
5251 | } | |
5252 | ||
77d22dca ID |
5253 | #define for_each_power_domain(domain, mask) \ |
5254 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5255 | if ((1 << (domain)) & (mask)) | |
5256 | ||
319be8ae ID |
5257 | enum intel_display_power_domain |
5258 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5259 | { | |
5260 | struct drm_device *dev = intel_encoder->base.dev; | |
5261 | struct intel_digital_port *intel_dig_port; | |
5262 | ||
5263 | switch (intel_encoder->type) { | |
5264 | case INTEL_OUTPUT_UNKNOWN: | |
5265 | /* Only DDI platforms should ever use this output type */ | |
5266 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5267 | case INTEL_OUTPUT_DISPLAYPORT: | |
5268 | case INTEL_OUTPUT_HDMI: | |
5269 | case INTEL_OUTPUT_EDP: | |
5270 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5271 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5272 | case INTEL_OUTPUT_DP_MST: |
5273 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5274 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5275 | case INTEL_OUTPUT_ANALOG: |
5276 | return POWER_DOMAIN_PORT_CRT; | |
5277 | case INTEL_OUTPUT_DSI: | |
5278 | return POWER_DOMAIN_PORT_DSI; | |
5279 | default: | |
5280 | return POWER_DOMAIN_PORT_OTHER; | |
5281 | } | |
5282 | } | |
5283 | ||
5284 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5285 | { |
319be8ae ID |
5286 | struct drm_device *dev = crtc->dev; |
5287 | struct intel_encoder *intel_encoder; | |
5288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5289 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5290 | unsigned long mask; |
5291 | enum transcoder transcoder; | |
5292 | ||
5293 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5294 | ||
5295 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5296 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5297 | if (intel_crtc->config->pch_pfit.enabled || |
5298 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5299 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5300 | ||
319be8ae ID |
5301 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5302 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5303 | ||
77d22dca ID |
5304 | return mask; |
5305 | } | |
5306 | ||
679dacd4 | 5307 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5308 | { |
679dacd4 | 5309 | struct drm_device *dev = state->dev; |
77d22dca ID |
5310 | struct drm_i915_private *dev_priv = dev->dev_private; |
5311 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5312 | struct intel_crtc *crtc; | |
5313 | ||
5314 | /* | |
5315 | * First get all needed power domains, then put all unneeded, to avoid | |
5316 | * any unnecessary toggling of the power wells. | |
5317 | */ | |
d3fcc808 | 5318 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5319 | enum intel_display_power_domain domain; |
5320 | ||
83d65738 | 5321 | if (!crtc->base.state->enable) |
77d22dca ID |
5322 | continue; |
5323 | ||
319be8ae | 5324 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5325 | |
5326 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5327 | intel_display_power_get(dev_priv, domain); | |
5328 | } | |
5329 | ||
50f6e502 | 5330 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5331 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5332 | |
d3fcc808 | 5333 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5334 | enum intel_display_power_domain domain; |
5335 | ||
5336 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5337 | intel_display_power_put(dev_priv, domain); | |
5338 | ||
5339 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5340 | } | |
5341 | ||
5342 | intel_display_set_init_power(dev_priv, false); | |
5343 | } | |
5344 | ||
f8437dd1 VK |
5345 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5346 | { | |
5347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5348 | uint32_t divider; | |
5349 | uint32_t ratio; | |
5350 | uint32_t current_freq; | |
5351 | int ret; | |
5352 | ||
5353 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5354 | switch (frequency) { | |
5355 | case 144000: | |
5356 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5357 | ratio = BXT_DE_PLL_RATIO(60); | |
5358 | break; | |
5359 | case 288000: | |
5360 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5361 | ratio = BXT_DE_PLL_RATIO(60); | |
5362 | break; | |
5363 | case 384000: | |
5364 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5365 | ratio = BXT_DE_PLL_RATIO(60); | |
5366 | break; | |
5367 | case 576000: | |
5368 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5369 | ratio = BXT_DE_PLL_RATIO(60); | |
5370 | break; | |
5371 | case 624000: | |
5372 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5373 | ratio = BXT_DE_PLL_RATIO(65); | |
5374 | break; | |
5375 | case 19200: | |
5376 | /* | |
5377 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5378 | * to suppress GCC warning. | |
5379 | */ | |
5380 | ratio = 0; | |
5381 | divider = 0; | |
5382 | break; | |
5383 | default: | |
5384 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5385 | ||
5386 | return; | |
5387 | } | |
5388 | ||
5389 | mutex_lock(&dev_priv->rps.hw_lock); | |
5390 | /* Inform power controller of upcoming frequency change */ | |
5391 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5392 | 0x80000000); | |
5393 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5394 | ||
5395 | if (ret) { | |
5396 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5397 | ret, frequency); | |
5398 | return; | |
5399 | } | |
5400 | ||
5401 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5402 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5403 | current_freq = current_freq * 500 + 1000; | |
5404 | ||
5405 | /* | |
5406 | * DE PLL has to be disabled when | |
5407 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5408 | * - before setting to 624MHz (PLL needs toggling) | |
5409 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5410 | */ | |
5411 | if (frequency == 19200 || frequency == 624000 || | |
5412 | current_freq == 624000) { | |
5413 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5414 | /* Timeout 200us */ | |
5415 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5416 | 1)) | |
5417 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5418 | } | |
5419 | ||
5420 | if (frequency != 19200) { | |
5421 | uint32_t val; | |
5422 | ||
5423 | val = I915_READ(BXT_DE_PLL_CTL); | |
5424 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5425 | val |= ratio; | |
5426 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5427 | ||
5428 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5429 | /* Timeout 200us */ | |
5430 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5431 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5432 | ||
5433 | val = I915_READ(CDCLK_CTL); | |
5434 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5435 | val |= divider; | |
5436 | /* | |
5437 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5438 | * enable otherwise. | |
5439 | */ | |
5440 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5441 | if (frequency >= 500000) | |
5442 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5443 | ||
5444 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5445 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5446 | val |= (frequency - 1000) / 500; | |
5447 | I915_WRITE(CDCLK_CTL, val); | |
5448 | } | |
5449 | ||
5450 | mutex_lock(&dev_priv->rps.hw_lock); | |
5451 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5452 | DIV_ROUND_UP(frequency, 25000)); | |
5453 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5454 | ||
5455 | if (ret) { | |
5456 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5457 | ret, frequency); | |
5458 | return; | |
5459 | } | |
5460 | ||
5461 | dev_priv->cdclk_freq = frequency; | |
5462 | } | |
5463 | ||
5464 | void broxton_init_cdclk(struct drm_device *dev) | |
5465 | { | |
5466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5467 | uint32_t val; | |
5468 | ||
5469 | /* | |
5470 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5471 | * or else the reset will hang because there is no PCH to respond. | |
5472 | * Move the handshake programming to initialization sequence. | |
5473 | * Previously was left up to BIOS. | |
5474 | */ | |
5475 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5476 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5477 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5478 | ||
5479 | /* Enable PG1 for cdclk */ | |
5480 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5481 | ||
5482 | /* check if cd clock is enabled */ | |
5483 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5484 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5485 | return; | |
5486 | } | |
5487 | ||
5488 | /* | |
5489 | * FIXME: | |
5490 | * - The initial CDCLK needs to be read from VBT. | |
5491 | * Need to make this change after VBT has changes for BXT. | |
5492 | * - check if setting the max (or any) cdclk freq is really necessary | |
5493 | * here, it belongs to modeset time | |
5494 | */ | |
5495 | broxton_set_cdclk(dev, 624000); | |
5496 | ||
5497 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5498 | POSTING_READ(DBUF_CTL); |
5499 | ||
f8437dd1 VK |
5500 | udelay(10); |
5501 | ||
5502 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5503 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5504 | } | |
5505 | ||
5506 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5507 | { | |
5508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5509 | ||
5510 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5511 | POSTING_READ(DBUF_CTL); |
5512 | ||
f8437dd1 VK |
5513 | udelay(10); |
5514 | ||
5515 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5516 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5517 | ||
5518 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5519 | broxton_set_cdclk(dev, 19200); | |
5520 | ||
5521 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5522 | } | |
5523 | ||
dfcab17e | 5524 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5525 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5526 | { |
586f49dc | 5527 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5528 | |
586f49dc JB |
5529 | /* Obtain SKU information */ |
5530 | mutex_lock(&dev_priv->dpio_lock); | |
5531 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5532 | CCK_FUSE_HPLL_FREQ_MASK; | |
5533 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5534 | |
dfcab17e | 5535 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5536 | } |
5537 | ||
f8bf63fd VS |
5538 | static void vlv_update_cdclk(struct drm_device *dev) |
5539 | { | |
5540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5541 | ||
164dfd28 | 5542 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5543 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5544 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5545 | |
5546 | /* | |
5547 | * Program the gmbus_freq based on the cdclk frequency. | |
5548 | * BSpec erroneously claims we should aim for 4MHz, but | |
5549 | * in fact 1MHz is the correct frequency. | |
5550 | */ | |
164dfd28 | 5551 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5552 | } |
5553 | ||
30a970c6 JB |
5554 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5555 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5556 | { | |
5557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5558 | u32 val, cmd; | |
5559 | ||
164dfd28 VK |
5560 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5561 | != dev_priv->cdclk_freq); | |
d60c4473 | 5562 | |
dfcab17e | 5563 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5564 | cmd = 2; |
dfcab17e | 5565 | else if (cdclk == 266667) |
30a970c6 JB |
5566 | cmd = 1; |
5567 | else | |
5568 | cmd = 0; | |
5569 | ||
5570 | mutex_lock(&dev_priv->rps.hw_lock); | |
5571 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5572 | val &= ~DSPFREQGUAR_MASK; | |
5573 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5574 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5575 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5576 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5577 | 50)) { | |
5578 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5579 | } | |
5580 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5581 | ||
dfcab17e | 5582 | if (cdclk == 400000) { |
6bcda4f0 | 5583 | u32 divider; |
30a970c6 | 5584 | |
6bcda4f0 | 5585 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5586 | |
5587 | mutex_lock(&dev_priv->dpio_lock); | |
5588 | /* adjust cdclk divider */ | |
5589 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5590 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5591 | val |= divider; |
5592 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5593 | |
5594 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5595 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5596 | 50)) | |
5597 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5598 | mutex_unlock(&dev_priv->dpio_lock); |
5599 | } | |
5600 | ||
5601 | mutex_lock(&dev_priv->dpio_lock); | |
5602 | /* adjust self-refresh exit latency value */ | |
5603 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5604 | val &= ~0x7f; | |
5605 | ||
5606 | /* | |
5607 | * For high bandwidth configs, we set a higher latency in the bunit | |
5608 | * so that the core display fetch happens in time to avoid underruns. | |
5609 | */ | |
dfcab17e | 5610 | if (cdclk == 400000) |
30a970c6 JB |
5611 | val |= 4500 / 250; /* 4.5 usec */ |
5612 | else | |
5613 | val |= 3000 / 250; /* 3.0 usec */ | |
5614 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5615 | mutex_unlock(&dev_priv->dpio_lock); | |
5616 | ||
f8bf63fd | 5617 | vlv_update_cdclk(dev); |
30a970c6 JB |
5618 | } |
5619 | ||
383c5a6a VS |
5620 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5621 | { | |
5622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5623 | u32 val, cmd; | |
5624 | ||
164dfd28 VK |
5625 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5626 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5627 | |
5628 | switch (cdclk) { | |
383c5a6a VS |
5629 | case 333333: |
5630 | case 320000: | |
383c5a6a | 5631 | case 266667: |
383c5a6a | 5632 | case 200000: |
383c5a6a VS |
5633 | break; |
5634 | default: | |
5f77eeb0 | 5635 | MISSING_CASE(cdclk); |
383c5a6a VS |
5636 | return; |
5637 | } | |
5638 | ||
9d0d3fda VS |
5639 | /* |
5640 | * Specs are full of misinformation, but testing on actual | |
5641 | * hardware has shown that we just need to write the desired | |
5642 | * CCK divider into the Punit register. | |
5643 | */ | |
5644 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5645 | ||
383c5a6a VS |
5646 | mutex_lock(&dev_priv->rps.hw_lock); |
5647 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5648 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5649 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5650 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5651 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5652 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5653 | 50)) { | |
5654 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5655 | } | |
5656 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5657 | ||
5658 | vlv_update_cdclk(dev); | |
5659 | } | |
5660 | ||
30a970c6 JB |
5661 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5662 | int max_pixclk) | |
5663 | { | |
6bcda4f0 | 5664 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5665 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5666 | |
30a970c6 JB |
5667 | /* |
5668 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5669 | * 200MHz | |
5670 | * 267MHz | |
29dc7ef3 | 5671 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5672 | * 400MHz (VLV only) |
5673 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5674 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5675 | * |
5676 | * We seem to get an unstable or solid color picture at 200MHz. | |
5677 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5678 | * are off. | |
30a970c6 | 5679 | */ |
6cca3195 VS |
5680 | if (!IS_CHERRYVIEW(dev_priv) && |
5681 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5682 | return 400000; |
6cca3195 | 5683 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5684 | return freq_320; |
e37c67a1 | 5685 | else if (max_pixclk > 0) |
dfcab17e | 5686 | return 266667; |
e37c67a1 VS |
5687 | else |
5688 | return 200000; | |
30a970c6 JB |
5689 | } |
5690 | ||
f8437dd1 VK |
5691 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5692 | int max_pixclk) | |
5693 | { | |
5694 | /* | |
5695 | * FIXME: | |
5696 | * - remove the guardband, it's not needed on BXT | |
5697 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5698 | */ | |
5699 | if (max_pixclk > 576000*9/10) | |
5700 | return 624000; | |
5701 | else if (max_pixclk > 384000*9/10) | |
5702 | return 576000; | |
5703 | else if (max_pixclk > 288000*9/10) | |
5704 | return 384000; | |
5705 | else if (max_pixclk > 144000*9/10) | |
5706 | return 288000; | |
5707 | else | |
5708 | return 144000; | |
5709 | } | |
5710 | ||
a821fc46 ACO |
5711 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5712 | * that's non-NULL, look at current state otherwise. */ | |
5713 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5714 | struct drm_atomic_state *state) | |
30a970c6 | 5715 | { |
30a970c6 | 5716 | struct intel_crtc *intel_crtc; |
304603f4 | 5717 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5718 | int max_pixclk = 0; |
5719 | ||
d3fcc808 | 5720 | for_each_intel_crtc(dev, intel_crtc) { |
a821fc46 ACO |
5721 | if (state) |
5722 | crtc_state = | |
5723 | intel_atomic_get_crtc_state(state, intel_crtc); | |
5724 | else | |
5725 | crtc_state = intel_crtc->config; | |
304603f4 ACO |
5726 | if (IS_ERR(crtc_state)) |
5727 | return PTR_ERR(crtc_state); | |
5728 | ||
5729 | if (!crtc_state->base.enable) | |
5730 | continue; | |
5731 | ||
5732 | max_pixclk = max(max_pixclk, | |
5733 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5734 | } |
5735 | ||
5736 | return max_pixclk; | |
5737 | } | |
5738 | ||
0a9ab303 | 5739 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) |
30a970c6 | 5740 | { |
304603f4 | 5741 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
0a9ab303 ACO |
5742 | struct drm_crtc *crtc; |
5743 | struct drm_crtc_state *crtc_state; | |
a821fc46 | 5744 | int max_pixclk = intel_mode_max_pixclk(state->dev, state); |
0a9ab303 | 5745 | int cdclk, i; |
30a970c6 | 5746 | |
304603f4 ACO |
5747 | if (max_pixclk < 0) |
5748 | return max_pixclk; | |
30a970c6 | 5749 | |
f8437dd1 VK |
5750 | if (IS_VALLEYVIEW(dev_priv)) |
5751 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5752 | else | |
5753 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5754 | ||
5755 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5756 | return 0; |
30a970c6 | 5757 | |
0a9ab303 ACO |
5758 | /* add all active pipes to the state */ |
5759 | for_each_crtc(state->dev, crtc) { | |
5760 | if (!crtc->state->enable) | |
5761 | continue; | |
5762 | ||
5763 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
5764 | if (IS_ERR(crtc_state)) | |
5765 | return PTR_ERR(crtc_state); | |
5766 | } | |
5767 | ||
2f2d7aa1 | 5768 | /* disable/enable all currently active pipes while we change cdclk */ |
0a9ab303 ACO |
5769 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
5770 | if (crtc_state->enable) | |
5771 | crtc_state->mode_changed = true; | |
304603f4 ACO |
5772 | |
5773 | return 0; | |
30a970c6 JB |
5774 | } |
5775 | ||
1e69cd74 VS |
5776 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5777 | { | |
5778 | unsigned int credits, default_credits; | |
5779 | ||
5780 | if (IS_CHERRYVIEW(dev_priv)) | |
5781 | default_credits = PFI_CREDIT(12); | |
5782 | else | |
5783 | default_credits = PFI_CREDIT(8); | |
5784 | ||
164dfd28 | 5785 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5786 | /* CHV suggested value is 31 or 63 */ |
5787 | if (IS_CHERRYVIEW(dev_priv)) | |
5788 | credits = PFI_CREDIT_31; | |
5789 | else | |
5790 | credits = PFI_CREDIT(15); | |
5791 | } else { | |
5792 | credits = default_credits; | |
5793 | } | |
5794 | ||
5795 | /* | |
5796 | * WA - write default credits before re-programming | |
5797 | * FIXME: should we also set the resend bit here? | |
5798 | */ | |
5799 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5800 | default_credits); | |
5801 | ||
5802 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5803 | credits | PFI_CREDIT_RESEND); | |
5804 | ||
5805 | /* | |
5806 | * FIXME is this guaranteed to clear | |
5807 | * immediately or should we poll for it? | |
5808 | */ | |
5809 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5810 | } | |
5811 | ||
a821fc46 | 5812 | static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state) |
30a970c6 | 5813 | { |
a821fc46 | 5814 | struct drm_device *dev = old_state->dev; |
30a970c6 | 5815 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 5816 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
304603f4 ACO |
5817 | int req_cdclk; |
5818 | ||
a821fc46 ACO |
5819 | /* The path in intel_mode_max_pixclk() with a NULL atomic state should |
5820 | * never fail. */ | |
304603f4 ACO |
5821 | if (WARN_ON(max_pixclk < 0)) |
5822 | return; | |
30a970c6 | 5823 | |
304603f4 | 5824 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 5825 | |
164dfd28 | 5826 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5827 | /* |
5828 | * FIXME: We can end up here with all power domains off, yet | |
5829 | * with a CDCLK frequency other than the minimum. To account | |
5830 | * for this take the PIPE-A power domain, which covers the HW | |
5831 | * blocks needed for the following programming. This can be | |
5832 | * removed once it's guaranteed that we get here either with | |
5833 | * the minimum CDCLK set, or the required power domains | |
5834 | * enabled. | |
5835 | */ | |
5836 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5837 | ||
383c5a6a VS |
5838 | if (IS_CHERRYVIEW(dev)) |
5839 | cherryview_set_cdclk(dev, req_cdclk); | |
5840 | else | |
5841 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5842 | |
1e69cd74 VS |
5843 | vlv_program_pfi_credits(dev_priv); |
5844 | ||
738c05c0 | 5845 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5846 | } |
30a970c6 JB |
5847 | } |
5848 | ||
89b667f8 JB |
5849 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5850 | { | |
5851 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5852 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5854 | struct intel_encoder *encoder; | |
5855 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5856 | bool is_dsi; |
89b667f8 | 5857 | |
83d65738 | 5858 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5859 | |
5860 | if (intel_crtc->active) | |
5861 | return; | |
5862 | ||
409ee761 | 5863 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5864 | |
1ae0d137 VS |
5865 | if (!is_dsi) { |
5866 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5867 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5868 | else |
6e3c9717 | 5869 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5870 | } |
5b18e57c | 5871 | |
6e3c9717 | 5872 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5873 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5874 | |
5875 | intel_set_pipe_timings(intel_crtc); | |
5876 | ||
c14b0485 VS |
5877 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5879 | ||
5880 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5881 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5882 | } | |
5883 | ||
5b18e57c DV |
5884 | i9xx_set_pipeconf(intel_crtc); |
5885 | ||
89b667f8 | 5886 | intel_crtc->active = true; |
89b667f8 | 5887 | |
a72e4c9f | 5888 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5889 | |
89b667f8 JB |
5890 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5891 | if (encoder->pre_pll_enable) | |
5892 | encoder->pre_pll_enable(encoder); | |
5893 | ||
9d556c99 CML |
5894 | if (!is_dsi) { |
5895 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5896 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5897 | else |
6e3c9717 | 5898 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5899 | } |
89b667f8 JB |
5900 | |
5901 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5902 | if (encoder->pre_enable) | |
5903 | encoder->pre_enable(encoder); | |
5904 | ||
2dd24552 JB |
5905 | i9xx_pfit_enable(intel_crtc); |
5906 | ||
63cbb074 VS |
5907 | intel_crtc_load_lut(crtc); |
5908 | ||
f37fcc2a | 5909 | intel_update_watermarks(crtc); |
e1fdc473 | 5910 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5911 | |
4b3a9526 VS |
5912 | assert_vblank_disabled(crtc); |
5913 | drm_crtc_vblank_on(crtc); | |
5914 | ||
f9b61ff6 DV |
5915 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5916 | encoder->enable(encoder); | |
89b667f8 JB |
5917 | } |
5918 | ||
f13c2ef3 DV |
5919 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5920 | { | |
5921 | struct drm_device *dev = crtc->base.dev; | |
5922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5923 | ||
6e3c9717 ACO |
5924 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5925 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5926 | } |
5927 | ||
0b8765c6 | 5928 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5929 | { |
5930 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5931 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5932 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5933 | struct intel_encoder *encoder; |
79e53945 | 5934 | int pipe = intel_crtc->pipe; |
79e53945 | 5935 | |
83d65738 | 5936 | WARN_ON(!crtc->state->enable); |
08a48469 | 5937 | |
f7abfe8b CW |
5938 | if (intel_crtc->active) |
5939 | return; | |
5940 | ||
f13c2ef3 DV |
5941 | i9xx_set_pll_dividers(intel_crtc); |
5942 | ||
6e3c9717 | 5943 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5944 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5945 | |
5946 | intel_set_pipe_timings(intel_crtc); | |
5947 | ||
5b18e57c DV |
5948 | i9xx_set_pipeconf(intel_crtc); |
5949 | ||
f7abfe8b | 5950 | intel_crtc->active = true; |
6b383a7f | 5951 | |
4a3436e8 | 5952 | if (!IS_GEN2(dev)) |
a72e4c9f | 5953 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5954 | |
9d6d9f19 MK |
5955 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5956 | if (encoder->pre_enable) | |
5957 | encoder->pre_enable(encoder); | |
5958 | ||
f6736a1a DV |
5959 | i9xx_enable_pll(intel_crtc); |
5960 | ||
2dd24552 JB |
5961 | i9xx_pfit_enable(intel_crtc); |
5962 | ||
63cbb074 VS |
5963 | intel_crtc_load_lut(crtc); |
5964 | ||
f37fcc2a | 5965 | intel_update_watermarks(crtc); |
e1fdc473 | 5966 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5967 | |
4b3a9526 VS |
5968 | assert_vblank_disabled(crtc); |
5969 | drm_crtc_vblank_on(crtc); | |
5970 | ||
f9b61ff6 DV |
5971 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5972 | encoder->enable(encoder); | |
0b8765c6 | 5973 | } |
79e53945 | 5974 | |
87476d63 DV |
5975 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5976 | { | |
5977 | struct drm_device *dev = crtc->base.dev; | |
5978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5979 | |
6e3c9717 | 5980 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5981 | return; |
87476d63 | 5982 | |
328d8e82 | 5983 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5984 | |
328d8e82 DV |
5985 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5986 | I915_READ(PFIT_CONTROL)); | |
5987 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5988 | } |
5989 | ||
0b8765c6 JB |
5990 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5991 | { | |
5992 | struct drm_device *dev = crtc->dev; | |
5993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5995 | struct intel_encoder *encoder; |
0b8765c6 | 5996 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5997 | |
f7abfe8b CW |
5998 | if (!intel_crtc->active) |
5999 | return; | |
6000 | ||
6304cd91 VS |
6001 | /* |
6002 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6003 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6004 | * We also need to wait on all gmch platforms because of the |
6005 | * self-refresh mode constraint explained above. | |
6304cd91 | 6006 | */ |
564ed191 | 6007 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6008 | |
4b3a9526 VS |
6009 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6010 | encoder->disable(encoder); | |
6011 | ||
f9b61ff6 DV |
6012 | drm_crtc_vblank_off(crtc); |
6013 | assert_vblank_disabled(crtc); | |
6014 | ||
575f7ab7 | 6015 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6016 | |
87476d63 | 6017 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6018 | |
89b667f8 JB |
6019 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6020 | if (encoder->post_disable) | |
6021 | encoder->post_disable(encoder); | |
6022 | ||
409ee761 | 6023 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6024 | if (IS_CHERRYVIEW(dev)) |
6025 | chv_disable_pll(dev_priv, pipe); | |
6026 | else if (IS_VALLEYVIEW(dev)) | |
6027 | vlv_disable_pll(dev_priv, pipe); | |
6028 | else | |
1c4e0274 | 6029 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6030 | } |
0b8765c6 | 6031 | |
4a3436e8 | 6032 | if (!IS_GEN2(dev)) |
a72e4c9f | 6033 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 6034 | |
f7abfe8b | 6035 | intel_crtc->active = false; |
46ba614c | 6036 | intel_update_watermarks(crtc); |
f37fcc2a | 6037 | |
efa9624e | 6038 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6039 | intel_fbc_update(dev); |
efa9624e | 6040 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6041 | } |
6042 | ||
ee7b9f93 JB |
6043 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
6044 | { | |
6045 | } | |
6046 | ||
b04c5bd6 BF |
6047 | /* Master function to enable/disable CRTC and corresponding power wells */ |
6048 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
6049 | { |
6050 | struct drm_device *dev = crtc->dev; | |
6051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 6052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
6053 | enum intel_display_power_domain domain; |
6054 | unsigned long domains; | |
976f8a20 | 6055 | |
0e572fe7 DV |
6056 | if (enable) { |
6057 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
6058 | domains = get_crtc_power_domains(crtc); |
6059 | for_each_power_domain(domain, domains) | |
6060 | intel_display_power_get(dev_priv, domain); | |
6061 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
6062 | |
6063 | dev_priv->display.crtc_enable(crtc); | |
ce22dba9 | 6064 | intel_crtc_enable_planes(crtc); |
0e572fe7 DV |
6065 | } |
6066 | } else { | |
6067 | if (intel_crtc->active) { | |
ce22dba9 | 6068 | intel_crtc_disable_planes(crtc); |
0e572fe7 DV |
6069 | dev_priv->display.crtc_disable(crtc); |
6070 | ||
e1e9fb84 DV |
6071 | domains = intel_crtc->enabled_power_domains; |
6072 | for_each_power_domain(domain, domains) | |
6073 | intel_display_power_put(dev_priv, domain); | |
6074 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6075 | } |
6076 | } | |
b04c5bd6 BF |
6077 | } |
6078 | ||
6079 | /** | |
6080 | * Sets the power management mode of the pipe and plane. | |
6081 | */ | |
6082 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6083 | { | |
6084 | struct drm_device *dev = crtc->dev; | |
6085 | struct intel_encoder *intel_encoder; | |
6086 | bool enable = false; | |
6087 | ||
6088 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6089 | enable |= intel_encoder->connectors_active; | |
6090 | ||
6091 | intel_crtc_control(crtc, enable); | |
0f63cca2 ACO |
6092 | |
6093 | crtc->state->active = enable; | |
976f8a20 DV |
6094 | } |
6095 | ||
cdd59983 CW |
6096 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6097 | { | |
cdd59983 | 6098 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6099 | struct drm_connector *connector; |
ee7b9f93 | 6100 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6101 | |
976f8a20 | 6102 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6103 | WARN_ON(!crtc->state->enable); |
976f8a20 | 6104 | |
ce22dba9 | 6105 | intel_crtc_disable_planes(crtc); |
976f8a20 | 6106 | dev_priv->display.crtc_disable(crtc); |
ee7b9f93 JB |
6107 | dev_priv->display.off(crtc); |
6108 | ||
70a101f8 | 6109 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6110 | |
6111 | /* Update computed state. */ | |
6112 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6113 | if (!connector->encoder || !connector->encoder->crtc) | |
6114 | continue; | |
6115 | ||
6116 | if (connector->encoder->crtc != crtc) | |
6117 | continue; | |
6118 | ||
6119 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6120 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6121 | } |
6122 | } | |
6123 | ||
ea5b213a | 6124 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6125 | { |
4ef69c7a | 6126 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6127 | |
ea5b213a CW |
6128 | drm_encoder_cleanup(encoder); |
6129 | kfree(intel_encoder); | |
7e7d76c3 JB |
6130 | } |
6131 | ||
9237329d | 6132 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6133 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6134 | * state of the entire output pipe. */ | |
9237329d | 6135 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6136 | { |
5ab432ef DV |
6137 | if (mode == DRM_MODE_DPMS_ON) { |
6138 | encoder->connectors_active = true; | |
6139 | ||
b2cabb0e | 6140 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6141 | } else { |
6142 | encoder->connectors_active = false; | |
6143 | ||
b2cabb0e | 6144 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6145 | } |
79e53945 JB |
6146 | } |
6147 | ||
0a91ca29 DV |
6148 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6149 | * internal consistency). */ | |
b980514c | 6150 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6151 | { |
0a91ca29 DV |
6152 | if (connector->get_hw_state(connector)) { |
6153 | struct intel_encoder *encoder = connector->encoder; | |
6154 | struct drm_crtc *crtc; | |
6155 | bool encoder_enabled; | |
6156 | enum pipe pipe; | |
6157 | ||
6158 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6159 | connector->base.base.id, | |
c23cc417 | 6160 | connector->base.name); |
0a91ca29 | 6161 | |
0e32b39c DA |
6162 | /* there is no real hw state for MST connectors */ |
6163 | if (connector->mst_port) | |
6164 | return; | |
6165 | ||
e2c719b7 | 6166 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6167 | "wrong connector dpms state\n"); |
e2c719b7 | 6168 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6169 | "active connector not linked to encoder\n"); |
0a91ca29 | 6170 | |
36cd7444 | 6171 | if (encoder) { |
e2c719b7 | 6172 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6173 | "encoder->connectors_active not set\n"); |
6174 | ||
6175 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6176 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6177 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6178 | return; |
0a91ca29 | 6179 | |
36cd7444 | 6180 | crtc = encoder->base.crtc; |
0a91ca29 | 6181 | |
83d65738 MR |
6182 | I915_STATE_WARN(!crtc->state->enable, |
6183 | "crtc not enabled\n"); | |
e2c719b7 RC |
6184 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6185 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6186 | "encoder active on the wrong pipe\n"); |
6187 | } | |
0a91ca29 | 6188 | } |
79e53945 JB |
6189 | } |
6190 | ||
08d9bc92 ACO |
6191 | int intel_connector_init(struct intel_connector *connector) |
6192 | { | |
6193 | struct drm_connector_state *connector_state; | |
6194 | ||
6195 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6196 | if (!connector_state) | |
6197 | return -ENOMEM; | |
6198 | ||
6199 | connector->base.state = connector_state; | |
6200 | return 0; | |
6201 | } | |
6202 | ||
6203 | struct intel_connector *intel_connector_alloc(void) | |
6204 | { | |
6205 | struct intel_connector *connector; | |
6206 | ||
6207 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6208 | if (!connector) | |
6209 | return NULL; | |
6210 | ||
6211 | if (intel_connector_init(connector) < 0) { | |
6212 | kfree(connector); | |
6213 | return NULL; | |
6214 | } | |
6215 | ||
6216 | return connector; | |
6217 | } | |
6218 | ||
5ab432ef DV |
6219 | /* Even simpler default implementation, if there's really no special case to |
6220 | * consider. */ | |
6221 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6222 | { |
5ab432ef DV |
6223 | /* All the simple cases only support two dpms states. */ |
6224 | if (mode != DRM_MODE_DPMS_ON) | |
6225 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6226 | |
5ab432ef DV |
6227 | if (mode == connector->dpms) |
6228 | return; | |
6229 | ||
6230 | connector->dpms = mode; | |
6231 | ||
6232 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6233 | if (connector->encoder) |
6234 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6235 | |
b980514c | 6236 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6237 | } |
6238 | ||
f0947c37 DV |
6239 | /* Simple connector->get_hw_state implementation for encoders that support only |
6240 | * one connector and no cloning and hence the encoder state determines the state | |
6241 | * of the connector. */ | |
6242 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6243 | { |
24929352 | 6244 | enum pipe pipe = 0; |
f0947c37 | 6245 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6246 | |
f0947c37 | 6247 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6248 | } |
6249 | ||
6d293983 | 6250 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6251 | { |
6d293983 ACO |
6252 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6253 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6254 | |
6255 | return 0; | |
6256 | } | |
6257 | ||
6d293983 | 6258 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6259 | struct intel_crtc_state *pipe_config) |
1857e1da | 6260 | { |
6d293983 ACO |
6261 | struct drm_atomic_state *state = pipe_config->base.state; |
6262 | struct intel_crtc *other_crtc; | |
6263 | struct intel_crtc_state *other_crtc_state; | |
6264 | ||
1857e1da DV |
6265 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6266 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6267 | if (pipe_config->fdi_lanes > 4) { | |
6268 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6269 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6270 | return -EINVAL; |
1857e1da DV |
6271 | } |
6272 | ||
bafb6553 | 6273 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6274 | if (pipe_config->fdi_lanes > 2) { |
6275 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6276 | pipe_config->fdi_lanes); | |
6d293983 | 6277 | return -EINVAL; |
1857e1da | 6278 | } else { |
6d293983 | 6279 | return 0; |
1857e1da DV |
6280 | } |
6281 | } | |
6282 | ||
6283 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6284 | return 0; |
1857e1da DV |
6285 | |
6286 | /* Ivybridge 3 pipe is really complicated */ | |
6287 | switch (pipe) { | |
6288 | case PIPE_A: | |
6d293983 | 6289 | return 0; |
1857e1da | 6290 | case PIPE_B: |
6d293983 ACO |
6291 | if (pipe_config->fdi_lanes <= 2) |
6292 | return 0; | |
6293 | ||
6294 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6295 | other_crtc_state = | |
6296 | intel_atomic_get_crtc_state(state, other_crtc); | |
6297 | if (IS_ERR(other_crtc_state)) | |
6298 | return PTR_ERR(other_crtc_state); | |
6299 | ||
6300 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6301 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6302 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6303 | return -EINVAL; |
1857e1da | 6304 | } |
6d293983 | 6305 | return 0; |
1857e1da | 6306 | case PIPE_C: |
251cc67c VS |
6307 | if (pipe_config->fdi_lanes > 2) { |
6308 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6309 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6310 | return -EINVAL; |
251cc67c | 6311 | } |
6d293983 ACO |
6312 | |
6313 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6314 | other_crtc_state = | |
6315 | intel_atomic_get_crtc_state(state, other_crtc); | |
6316 | if (IS_ERR(other_crtc_state)) | |
6317 | return PTR_ERR(other_crtc_state); | |
6318 | ||
6319 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6320 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6321 | return -EINVAL; |
1857e1da | 6322 | } |
6d293983 | 6323 | return 0; |
1857e1da DV |
6324 | default: |
6325 | BUG(); | |
6326 | } | |
6327 | } | |
6328 | ||
e29c22c0 DV |
6329 | #define RETRY 1 |
6330 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6331 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6332 | { |
1857e1da | 6333 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6334 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6335 | int lane, link_bw, fdi_dotclock, ret; |
6336 | bool needs_recompute = false; | |
877d48d5 | 6337 | |
e29c22c0 | 6338 | retry: |
877d48d5 DV |
6339 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6340 | * each output octet as 10 bits. The actual frequency | |
6341 | * is stored as a divider into a 100MHz clock, and the | |
6342 | * mode pixel clock is stored in units of 1KHz. | |
6343 | * Hence the bw of each lane in terms of the mode signal | |
6344 | * is: | |
6345 | */ | |
6346 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6347 | ||
241bfc38 | 6348 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6349 | |
2bd89a07 | 6350 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6351 | pipe_config->pipe_bpp); |
6352 | ||
6353 | pipe_config->fdi_lanes = lane; | |
6354 | ||
2bd89a07 | 6355 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6356 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6357 | |
6d293983 ACO |
6358 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6359 | intel_crtc->pipe, pipe_config); | |
6360 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6361 | pipe_config->pipe_bpp -= 2*3; |
6362 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6363 | pipe_config->pipe_bpp); | |
6364 | needs_recompute = true; | |
6365 | pipe_config->bw_constrained = true; | |
6366 | ||
6367 | goto retry; | |
6368 | } | |
6369 | ||
6370 | if (needs_recompute) | |
6371 | return RETRY; | |
6372 | ||
6d293983 | 6373 | return ret; |
877d48d5 DV |
6374 | } |
6375 | ||
42db64ef | 6376 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6377 | struct intel_crtc_state *pipe_config) |
42db64ef | 6378 | { |
d330a953 | 6379 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6380 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6381 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6382 | } |
6383 | ||
a43f6e0f | 6384 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6385 | struct intel_crtc_state *pipe_config) |
79e53945 | 6386 | { |
a43f6e0f | 6387 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6388 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6389 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6390 | int ret; |
89749350 | 6391 | |
ad3a4479 | 6392 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6393 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6394 | int clock_limit = |
6395 | dev_priv->display.get_display_clock_speed(dev); | |
6396 | ||
6397 | /* | |
6398 | * Enable pixel doubling when the dot clock | |
6399 | * is > 90% of the (display) core speed. | |
6400 | * | |
b397c96b VS |
6401 | * GDG double wide on either pipe, |
6402 | * otherwise pipe A only. | |
cf532bb2 | 6403 | */ |
b397c96b | 6404 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6405 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6406 | clock_limit *= 2; |
cf532bb2 | 6407 | pipe_config->double_wide = true; |
ad3a4479 VS |
6408 | } |
6409 | ||
241bfc38 | 6410 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6411 | return -EINVAL; |
2c07245f | 6412 | } |
89749350 | 6413 | |
1d1d0e27 VS |
6414 | /* |
6415 | * Pipe horizontal size must be even in: | |
6416 | * - DVO ganged mode | |
6417 | * - LVDS dual channel mode | |
6418 | * - Double wide pipe | |
6419 | */ | |
a93e255f | 6420 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6421 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6422 | pipe_config->pipe_src_w &= ~1; | |
6423 | ||
8693a824 DL |
6424 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6425 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6426 | */ |
6427 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6428 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6429 | return -EINVAL; |
44f46b42 | 6430 | |
f5adf94e | 6431 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6432 | hsw_compute_ips_config(crtc, pipe_config); |
6433 | ||
877d48d5 | 6434 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6435 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6436 | |
d03c93d4 CK |
6437 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6438 | * related checks called from atomic_crtc_check function */ | |
6439 | ret = 0; | |
6440 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6441 | crtc, pipe_config->base.state); | |
6442 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6443 | ||
6444 | return ret; | |
79e53945 JB |
6445 | } |
6446 | ||
1652d19e VS |
6447 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6448 | { | |
6449 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6450 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6451 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6452 | uint32_t linkrate; | |
6453 | ||
6454 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6455 | WARN(1, "LCPLL1 not enabled\n"); | |
6456 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6457 | } | |
6458 | ||
6459 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6460 | return 540000; | |
6461 | ||
6462 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6463 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6464 | |
71cd8423 DL |
6465 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6466 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6467 | /* vco 8640 */ |
6468 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6469 | case CDCLK_FREQ_450_432: | |
6470 | return 432000; | |
6471 | case CDCLK_FREQ_337_308: | |
6472 | return 308570; | |
6473 | case CDCLK_FREQ_675_617: | |
6474 | return 617140; | |
6475 | default: | |
6476 | WARN(1, "Unknown cd freq selection\n"); | |
6477 | } | |
6478 | } else { | |
6479 | /* vco 8100 */ | |
6480 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6481 | case CDCLK_FREQ_450_432: | |
6482 | return 450000; | |
6483 | case CDCLK_FREQ_337_308: | |
6484 | return 337500; | |
6485 | case CDCLK_FREQ_675_617: | |
6486 | return 675000; | |
6487 | default: | |
6488 | WARN(1, "Unknown cd freq selection\n"); | |
6489 | } | |
6490 | } | |
6491 | ||
6492 | /* error case, do as if DPLL0 isn't enabled */ | |
6493 | return 24000; | |
6494 | } | |
6495 | ||
6496 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6497 | { | |
6498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6499 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6500 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6501 | ||
6502 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6503 | return 800000; | |
6504 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6505 | return 450000; | |
6506 | else if (freq == LCPLL_CLK_FREQ_450) | |
6507 | return 450000; | |
6508 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6509 | return 540000; | |
6510 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6511 | return 337500; | |
6512 | else | |
6513 | return 675000; | |
6514 | } | |
6515 | ||
6516 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6517 | { | |
6518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6519 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6520 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6521 | ||
6522 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6523 | return 800000; | |
6524 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6525 | return 450000; | |
6526 | else if (freq == LCPLL_CLK_FREQ_450) | |
6527 | return 450000; | |
6528 | else if (IS_HSW_ULT(dev)) | |
6529 | return 337500; | |
6530 | else | |
6531 | return 540000; | |
79e53945 JB |
6532 | } |
6533 | ||
25eb05fc JB |
6534 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6535 | { | |
d197b7d3 | 6536 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6537 | u32 val; |
6538 | int divider; | |
6539 | ||
6bcda4f0 VS |
6540 | if (dev_priv->hpll_freq == 0) |
6541 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6542 | ||
d197b7d3 VS |
6543 | mutex_lock(&dev_priv->dpio_lock); |
6544 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6545 | mutex_unlock(&dev_priv->dpio_lock); | |
6546 | ||
6547 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6548 | ||
7d007f40 VS |
6549 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6550 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6551 | "cdclk change in progress\n"); | |
6552 | ||
6bcda4f0 | 6553 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6554 | } |
6555 | ||
b37a6434 VS |
6556 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6557 | { | |
6558 | return 450000; | |
6559 | } | |
6560 | ||
e70236a8 JB |
6561 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6562 | { | |
6563 | return 400000; | |
6564 | } | |
79e53945 | 6565 | |
e70236a8 | 6566 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6567 | { |
e907f170 | 6568 | return 333333; |
e70236a8 | 6569 | } |
79e53945 | 6570 | |
e70236a8 JB |
6571 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6572 | { | |
6573 | return 200000; | |
6574 | } | |
79e53945 | 6575 | |
257a7ffc DV |
6576 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6577 | { | |
6578 | u16 gcfgc = 0; | |
6579 | ||
6580 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6581 | ||
6582 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6583 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6584 | return 266667; |
257a7ffc | 6585 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6586 | return 333333; |
257a7ffc | 6587 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6588 | return 444444; |
257a7ffc DV |
6589 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6590 | return 200000; | |
6591 | default: | |
6592 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6593 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6594 | return 133333; |
257a7ffc | 6595 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6596 | return 166667; |
257a7ffc DV |
6597 | } |
6598 | } | |
6599 | ||
e70236a8 JB |
6600 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6601 | { | |
6602 | u16 gcfgc = 0; | |
79e53945 | 6603 | |
e70236a8 JB |
6604 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6605 | ||
6606 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6607 | return 133333; |
e70236a8 JB |
6608 | else { |
6609 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6610 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6611 | return 333333; |
e70236a8 JB |
6612 | default: |
6613 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6614 | return 190000; | |
79e53945 | 6615 | } |
e70236a8 JB |
6616 | } |
6617 | } | |
6618 | ||
6619 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6620 | { | |
e907f170 | 6621 | return 266667; |
e70236a8 JB |
6622 | } |
6623 | ||
6624 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6625 | { | |
6626 | u16 hpllcc = 0; | |
6627 | /* Assume that the hardware is in the high speed state. This | |
6628 | * should be the default. | |
6629 | */ | |
6630 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6631 | case GC_CLOCK_133_200: | |
6632 | case GC_CLOCK_100_200: | |
6633 | return 200000; | |
6634 | case GC_CLOCK_166_250: | |
6635 | return 250000; | |
6636 | case GC_CLOCK_100_133: | |
e907f170 | 6637 | return 133333; |
e70236a8 | 6638 | } |
79e53945 | 6639 | |
e70236a8 JB |
6640 | /* Shouldn't happen */ |
6641 | return 0; | |
6642 | } | |
79e53945 | 6643 | |
e70236a8 JB |
6644 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6645 | { | |
e907f170 | 6646 | return 133333; |
79e53945 JB |
6647 | } |
6648 | ||
2c07245f | 6649 | static void |
a65851af | 6650 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6651 | { |
a65851af VS |
6652 | while (*num > DATA_LINK_M_N_MASK || |
6653 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6654 | *num >>= 1; |
6655 | *den >>= 1; | |
6656 | } | |
6657 | } | |
6658 | ||
a65851af VS |
6659 | static void compute_m_n(unsigned int m, unsigned int n, |
6660 | uint32_t *ret_m, uint32_t *ret_n) | |
6661 | { | |
6662 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6663 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6664 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6665 | } | |
6666 | ||
e69d0bc1 DV |
6667 | void |
6668 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6669 | int pixel_clock, int link_clock, | |
6670 | struct intel_link_m_n *m_n) | |
2c07245f | 6671 | { |
e69d0bc1 | 6672 | m_n->tu = 64; |
a65851af VS |
6673 | |
6674 | compute_m_n(bits_per_pixel * pixel_clock, | |
6675 | link_clock * nlanes * 8, | |
6676 | &m_n->gmch_m, &m_n->gmch_n); | |
6677 | ||
6678 | compute_m_n(pixel_clock, link_clock, | |
6679 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6680 | } |
6681 | ||
a7615030 CW |
6682 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6683 | { | |
d330a953 JN |
6684 | if (i915.panel_use_ssc >= 0) |
6685 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6686 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6687 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6688 | } |
6689 | ||
a93e255f ACO |
6690 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6691 | int num_connectors) | |
c65d77d8 | 6692 | { |
a93e255f | 6693 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6694 | struct drm_i915_private *dev_priv = dev->dev_private; |
6695 | int refclk; | |
6696 | ||
a93e255f ACO |
6697 | WARN_ON(!crtc_state->base.state); |
6698 | ||
5ab7b0b7 | 6699 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 6700 | refclk = 100000; |
a93e255f | 6701 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6702 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6703 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6704 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6705 | } else if (!IS_GEN2(dev)) { |
6706 | refclk = 96000; | |
6707 | } else { | |
6708 | refclk = 48000; | |
6709 | } | |
6710 | ||
6711 | return refclk; | |
6712 | } | |
6713 | ||
7429e9d4 | 6714 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6715 | { |
7df00d7a | 6716 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6717 | } |
f47709a9 | 6718 | |
7429e9d4 DV |
6719 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6720 | { | |
6721 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6722 | } |
6723 | ||
f47709a9 | 6724 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6725 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6726 | intel_clock_t *reduced_clock) |
6727 | { | |
f47709a9 | 6728 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6729 | u32 fp, fp2 = 0; |
6730 | ||
6731 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6732 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6733 | if (reduced_clock) |
7429e9d4 | 6734 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6735 | } else { |
190f68c5 | 6736 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6737 | if (reduced_clock) |
7429e9d4 | 6738 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6739 | } |
6740 | ||
190f68c5 | 6741 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6742 | |
f47709a9 | 6743 | crtc->lowfreq_avail = false; |
a93e255f | 6744 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6745 | reduced_clock) { |
190f68c5 | 6746 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6747 | crtc->lowfreq_avail = true; |
a7516a05 | 6748 | } else { |
190f68c5 | 6749 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6750 | } |
6751 | } | |
6752 | ||
5e69f97f CML |
6753 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6754 | pipe) | |
89b667f8 JB |
6755 | { |
6756 | u32 reg_val; | |
6757 | ||
6758 | /* | |
6759 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6760 | * and set it to a reasonable value instead. | |
6761 | */ | |
ab3c759a | 6762 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6763 | reg_val &= 0xffffff00; |
6764 | reg_val |= 0x00000030; | |
ab3c759a | 6765 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6766 | |
ab3c759a | 6767 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6768 | reg_val &= 0x8cffffff; |
6769 | reg_val = 0x8c000000; | |
ab3c759a | 6770 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6771 | |
ab3c759a | 6772 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6773 | reg_val &= 0xffffff00; |
ab3c759a | 6774 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6775 | |
ab3c759a | 6776 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6777 | reg_val &= 0x00ffffff; |
6778 | reg_val |= 0xb0000000; | |
ab3c759a | 6779 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6780 | } |
6781 | ||
b551842d DV |
6782 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6783 | struct intel_link_m_n *m_n) | |
6784 | { | |
6785 | struct drm_device *dev = crtc->base.dev; | |
6786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6787 | int pipe = crtc->pipe; | |
6788 | ||
e3b95f1e DV |
6789 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6790 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6791 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6792 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6793 | } |
6794 | ||
6795 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6796 | struct intel_link_m_n *m_n, |
6797 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6798 | { |
6799 | struct drm_device *dev = crtc->base.dev; | |
6800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6801 | int pipe = crtc->pipe; | |
6e3c9717 | 6802 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6803 | |
6804 | if (INTEL_INFO(dev)->gen >= 5) { | |
6805 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6806 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6807 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6808 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6809 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6810 | * for gen < 8) and if DRRS is supported (to make sure the | |
6811 | * registers are not unnecessarily accessed). | |
6812 | */ | |
44395bfe | 6813 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6814 | crtc->config->has_drrs) { |
f769cd24 VK |
6815 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6816 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6817 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6818 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6819 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6820 | } | |
b551842d | 6821 | } else { |
e3b95f1e DV |
6822 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6823 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6824 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6825 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6826 | } |
6827 | } | |
6828 | ||
fe3cd48d | 6829 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6830 | { |
fe3cd48d R |
6831 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6832 | ||
6833 | if (m_n == M1_N1) { | |
6834 | dp_m_n = &crtc->config->dp_m_n; | |
6835 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6836 | } else if (m_n == M2_N2) { | |
6837 | ||
6838 | /* | |
6839 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6840 | * needs to be programmed into M1_N1. | |
6841 | */ | |
6842 | dp_m_n = &crtc->config->dp_m2_n2; | |
6843 | } else { | |
6844 | DRM_ERROR("Unsupported divider value\n"); | |
6845 | return; | |
6846 | } | |
6847 | ||
6e3c9717 ACO |
6848 | if (crtc->config->has_pch_encoder) |
6849 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6850 | else |
fe3cd48d | 6851 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6852 | } |
6853 | ||
d288f65f | 6854 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6855 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6856 | { |
6857 | u32 dpll, dpll_md; | |
6858 | ||
6859 | /* | |
6860 | * Enable DPIO clock input. We should never disable the reference | |
6861 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6862 | * on it. | |
6863 | */ | |
6864 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6865 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6866 | /* We should never disable this, set it here for state tracking */ | |
6867 | if (crtc->pipe == PIPE_B) | |
6868 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6869 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6870 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6871 | |
d288f65f | 6872 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6873 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6874 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6875 | } |
6876 | ||
d288f65f | 6877 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6878 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6879 | { |
f47709a9 | 6880 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6881 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6882 | int pipe = crtc->pipe; |
bdd4b6a6 | 6883 | u32 mdiv; |
a0c4da24 | 6884 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6885 | u32 coreclk, reg_val; |
a0c4da24 | 6886 | |
09153000 DV |
6887 | mutex_lock(&dev_priv->dpio_lock); |
6888 | ||
d288f65f VS |
6889 | bestn = pipe_config->dpll.n; |
6890 | bestm1 = pipe_config->dpll.m1; | |
6891 | bestm2 = pipe_config->dpll.m2; | |
6892 | bestp1 = pipe_config->dpll.p1; | |
6893 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6894 | |
89b667f8 JB |
6895 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6896 | ||
6897 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6898 | if (pipe == PIPE_B) |
5e69f97f | 6899 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6900 | |
6901 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6902 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6903 | |
6904 | /* Disable target IRef on PLL */ | |
ab3c759a | 6905 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6906 | reg_val &= 0x00ffffff; |
ab3c759a | 6907 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6908 | |
6909 | /* Disable fast lock */ | |
ab3c759a | 6910 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6911 | |
6912 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6913 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6914 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6915 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6916 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6917 | |
6918 | /* | |
6919 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6920 | * but we don't support that). | |
6921 | * Note: don't use the DAC post divider as it seems unstable. | |
6922 | */ | |
6923 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6924 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6925 | |
a0c4da24 | 6926 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6927 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6928 | |
89b667f8 | 6929 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6930 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6931 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6932 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6933 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6934 | 0x009f0003); |
89b667f8 | 6935 | else |
ab3c759a | 6936 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6937 | 0x00d0000f); |
6938 | ||
681a8504 | 6939 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6940 | /* Use SSC source */ |
bdd4b6a6 | 6941 | if (pipe == PIPE_A) |
ab3c759a | 6942 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6943 | 0x0df40000); |
6944 | else | |
ab3c759a | 6945 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6946 | 0x0df70000); |
6947 | } else { /* HDMI or VGA */ | |
6948 | /* Use bend source */ | |
bdd4b6a6 | 6949 | if (pipe == PIPE_A) |
ab3c759a | 6950 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6951 | 0x0df70000); |
6952 | else | |
ab3c759a | 6953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6954 | 0x0df40000); |
6955 | } | |
a0c4da24 | 6956 | |
ab3c759a | 6957 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6958 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6959 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6960 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6961 | coreclk |= 0x01000000; |
ab3c759a | 6962 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6963 | |
ab3c759a | 6964 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6965 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6966 | } |
6967 | ||
d288f65f | 6968 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6969 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6970 | { |
d288f65f | 6971 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6972 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6973 | DPLL_VCO_ENABLE; | |
6974 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6975 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6976 | |
d288f65f VS |
6977 | pipe_config->dpll_hw_state.dpll_md = |
6978 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6979 | } |
6980 | ||
d288f65f | 6981 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6982 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6983 | { |
6984 | struct drm_device *dev = crtc->base.dev; | |
6985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6986 | int pipe = crtc->pipe; | |
6987 | int dpll_reg = DPLL(crtc->pipe); | |
6988 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6989 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6990 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6991 | u32 dpio_val; |
9cbe40c1 | 6992 | int vco; |
9d556c99 | 6993 | |
d288f65f VS |
6994 | bestn = pipe_config->dpll.n; |
6995 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6996 | bestm1 = pipe_config->dpll.m1; | |
6997 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6998 | bestp1 = pipe_config->dpll.p1; | |
6999 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7000 | vco = pipe_config->dpll.vco; |
a945ce7e | 7001 | dpio_val = 0; |
9cbe40c1 | 7002 | loopfilter = 0; |
9d556c99 CML |
7003 | |
7004 | /* | |
7005 | * Enable Refclk and SSC | |
7006 | */ | |
a11b0703 | 7007 | I915_WRITE(dpll_reg, |
d288f65f | 7008 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
7009 | |
7010 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 7011 | |
9d556c99 CML |
7012 | /* p1 and p2 divider */ |
7013 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7014 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7015 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7016 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7017 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7018 | ||
7019 | /* Feedback post-divider - m2 */ | |
7020 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7021 | ||
7022 | /* Feedback refclk divider - n and m1 */ | |
7023 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7024 | DPIO_CHV_M1_DIV_BY_2 | | |
7025 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7026 | ||
7027 | /* M2 fraction division */ | |
a945ce7e VP |
7028 | if (bestm2_frac) |
7029 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7030 | |
7031 | /* M2 fraction division enable */ | |
a945ce7e VP |
7032 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7033 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7034 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7035 | if (bestm2_frac) | |
7036 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7037 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7038 | |
de3a0fde VP |
7039 | /* Program digital lock detect threshold */ |
7040 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7041 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7042 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7043 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7044 | if (!bestm2_frac) | |
7045 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7046 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7047 | ||
9d556c99 | 7048 | /* Loop filter */ |
9cbe40c1 VP |
7049 | if (vco == 5400000) { |
7050 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7051 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7052 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7053 | tribuf_calcntr = 0x9; | |
7054 | } else if (vco <= 6200000) { | |
7055 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7056 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7057 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7058 | tribuf_calcntr = 0x9; | |
7059 | } else if (vco <= 6480000) { | |
7060 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7061 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7062 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7063 | tribuf_calcntr = 0x8; | |
7064 | } else { | |
7065 | /* Not supported. Apply the same limits as in the max case */ | |
7066 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7067 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7068 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7069 | tribuf_calcntr = 0; | |
7070 | } | |
9d556c99 CML |
7071 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7072 | ||
968040b2 | 7073 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7074 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7075 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7076 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7077 | ||
9d556c99 CML |
7078 | /* AFC Recal */ |
7079 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7080 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7081 | DPIO_AFC_RECAL); | |
7082 | ||
7083 | mutex_unlock(&dev_priv->dpio_lock); | |
7084 | } | |
7085 | ||
d288f65f VS |
7086 | /** |
7087 | * vlv_force_pll_on - forcibly enable just the PLL | |
7088 | * @dev_priv: i915 private structure | |
7089 | * @pipe: pipe PLL to enable | |
7090 | * @dpll: PLL configuration | |
7091 | * | |
7092 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7093 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7094 | * be enabled. | |
7095 | */ | |
7096 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7097 | const struct dpll *dpll) | |
7098 | { | |
7099 | struct intel_crtc *crtc = | |
7100 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7101 | struct intel_crtc_state pipe_config = { |
a93e255f | 7102 | .base.crtc = &crtc->base, |
d288f65f VS |
7103 | .pixel_multiplier = 1, |
7104 | .dpll = *dpll, | |
7105 | }; | |
7106 | ||
7107 | if (IS_CHERRYVIEW(dev)) { | |
7108 | chv_update_pll(crtc, &pipe_config); | |
7109 | chv_prepare_pll(crtc, &pipe_config); | |
7110 | chv_enable_pll(crtc, &pipe_config); | |
7111 | } else { | |
7112 | vlv_update_pll(crtc, &pipe_config); | |
7113 | vlv_prepare_pll(crtc, &pipe_config); | |
7114 | vlv_enable_pll(crtc, &pipe_config); | |
7115 | } | |
7116 | } | |
7117 | ||
7118 | /** | |
7119 | * vlv_force_pll_off - forcibly disable just the PLL | |
7120 | * @dev_priv: i915 private structure | |
7121 | * @pipe: pipe PLL to disable | |
7122 | * | |
7123 | * Disable the PLL for @pipe. To be used in cases where we need | |
7124 | * the PLL enabled even when @pipe is not going to be enabled. | |
7125 | */ | |
7126 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7127 | { | |
7128 | if (IS_CHERRYVIEW(dev)) | |
7129 | chv_disable_pll(to_i915(dev), pipe); | |
7130 | else | |
7131 | vlv_disable_pll(to_i915(dev), pipe); | |
7132 | } | |
7133 | ||
f47709a9 | 7134 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7135 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7136 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7137 | int num_connectors) |
7138 | { | |
f47709a9 | 7139 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7140 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7141 | u32 dpll; |
7142 | bool is_sdvo; | |
190f68c5 | 7143 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7144 | |
190f68c5 | 7145 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7146 | |
a93e255f ACO |
7147 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7148 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7149 | |
7150 | dpll = DPLL_VGA_MODE_DIS; | |
7151 | ||
a93e255f | 7152 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7153 | dpll |= DPLLB_MODE_LVDS; |
7154 | else | |
7155 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7156 | |
ef1b460d | 7157 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7158 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7159 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7160 | } |
198a037f DV |
7161 | |
7162 | if (is_sdvo) | |
4a33e48d | 7163 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7164 | |
190f68c5 | 7165 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7166 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7167 | |
7168 | /* compute bitmask from p1 value */ | |
7169 | if (IS_PINEVIEW(dev)) | |
7170 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7171 | else { | |
7172 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7173 | if (IS_G4X(dev) && reduced_clock) | |
7174 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7175 | } | |
7176 | switch (clock->p2) { | |
7177 | case 5: | |
7178 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7179 | break; | |
7180 | case 7: | |
7181 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7182 | break; | |
7183 | case 10: | |
7184 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7185 | break; | |
7186 | case 14: | |
7187 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7188 | break; | |
7189 | } | |
7190 | if (INTEL_INFO(dev)->gen >= 4) | |
7191 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7192 | ||
190f68c5 | 7193 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7194 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7195 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7196 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7197 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7198 | else | |
7199 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7200 | ||
7201 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7202 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7203 | |
eb1cbe48 | 7204 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7205 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7206 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7207 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7208 | } |
7209 | } | |
7210 | ||
f47709a9 | 7211 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7212 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7213 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7214 | int num_connectors) |
7215 | { | |
f47709a9 | 7216 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7217 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7218 | u32 dpll; |
190f68c5 | 7219 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7220 | |
190f68c5 | 7221 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7222 | |
eb1cbe48 DV |
7223 | dpll = DPLL_VGA_MODE_DIS; |
7224 | ||
a93e255f | 7225 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7226 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7227 | } else { | |
7228 | if (clock->p1 == 2) | |
7229 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7230 | else | |
7231 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7232 | if (clock->p2 == 4) | |
7233 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7234 | } | |
7235 | ||
a93e255f | 7236 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7237 | dpll |= DPLL_DVO_2X_MODE; |
7238 | ||
a93e255f | 7239 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7240 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7241 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7242 | else | |
7243 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7244 | ||
7245 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7246 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7247 | } |
7248 | ||
8a654f3b | 7249 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7250 | { |
7251 | struct drm_device *dev = intel_crtc->base.dev; | |
7252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7253 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7254 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7255 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7256 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7257 | uint32_t crtc_vtotal, crtc_vblank_end; |
7258 | int vsyncshift = 0; | |
4d8a62ea DV |
7259 | |
7260 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7261 | * the hw state checker will get angry at the mismatch. */ | |
7262 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7263 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7264 | |
609aeaca | 7265 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7266 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7267 | crtc_vtotal -= 1; |
7268 | crtc_vblank_end -= 1; | |
609aeaca | 7269 | |
409ee761 | 7270 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7271 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7272 | else | |
7273 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7274 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7275 | if (vsyncshift < 0) |
7276 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7277 | } |
7278 | ||
7279 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7280 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7281 | |
fe2b8f9d | 7282 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7283 | (adjusted_mode->crtc_hdisplay - 1) | |
7284 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7285 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7286 | (adjusted_mode->crtc_hblank_start - 1) | |
7287 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7288 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7289 | (adjusted_mode->crtc_hsync_start - 1) | |
7290 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7291 | ||
fe2b8f9d | 7292 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7293 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7294 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7295 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7296 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7297 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7298 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7299 | (adjusted_mode->crtc_vsync_start - 1) | |
7300 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7301 | ||
b5e508d4 PZ |
7302 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7303 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7304 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7305 | * bits. */ | |
7306 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7307 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7308 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7309 | ||
b0e77b9c PZ |
7310 | /* pipesrc controls the size that is scaled from, which should |
7311 | * always be the user's requested size. | |
7312 | */ | |
7313 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7314 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7315 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7316 | } |
7317 | ||
1bd1bd80 | 7318 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7319 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7320 | { |
7321 | struct drm_device *dev = crtc->base.dev; | |
7322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7323 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7324 | uint32_t tmp; | |
7325 | ||
7326 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7327 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7328 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7329 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7330 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7331 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7332 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7333 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7334 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7335 | |
7336 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7337 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7338 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7339 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7340 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7341 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7342 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7343 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7344 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7345 | |
7346 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7347 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7348 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7349 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7350 | } |
7351 | ||
7352 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7353 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7354 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7355 | ||
2d112de7 ACO |
7356 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7357 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7358 | } |
7359 | ||
f6a83288 | 7360 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7361 | struct intel_crtc_state *pipe_config) |
babea61d | 7362 | { |
2d112de7 ACO |
7363 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7364 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7365 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7366 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7367 | |
2d112de7 ACO |
7368 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7369 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7370 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7371 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7372 | |
2d112de7 | 7373 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7374 | |
2d112de7 ACO |
7375 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7376 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7377 | } |
7378 | ||
84b046f3 DV |
7379 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7380 | { | |
7381 | struct drm_device *dev = intel_crtc->base.dev; | |
7382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7383 | uint32_t pipeconf; | |
7384 | ||
9f11a9e4 | 7385 | pipeconf = 0; |
84b046f3 | 7386 | |
b6b5d049 VS |
7387 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7388 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7389 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7390 | |
6e3c9717 | 7391 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7392 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7393 | |
ff9ce46e DV |
7394 | /* only g4x and later have fancy bpc/dither controls */ |
7395 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7396 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7397 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7398 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7399 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7400 | |
6e3c9717 | 7401 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7402 | case 18: |
7403 | pipeconf |= PIPECONF_6BPC; | |
7404 | break; | |
7405 | case 24: | |
7406 | pipeconf |= PIPECONF_8BPC; | |
7407 | break; | |
7408 | case 30: | |
7409 | pipeconf |= PIPECONF_10BPC; | |
7410 | break; | |
7411 | default: | |
7412 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7413 | BUG(); | |
84b046f3 DV |
7414 | } |
7415 | } | |
7416 | ||
7417 | if (HAS_PIPE_CXSR(dev)) { | |
7418 | if (intel_crtc->lowfreq_avail) { | |
7419 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7420 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7421 | } else { | |
7422 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7423 | } |
7424 | } | |
7425 | ||
6e3c9717 | 7426 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7427 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7428 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7429 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7430 | else | |
7431 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7432 | } else | |
84b046f3 DV |
7433 | pipeconf |= PIPECONF_PROGRESSIVE; |
7434 | ||
6e3c9717 | 7435 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7436 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7437 | |
84b046f3 DV |
7438 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7439 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7440 | } | |
7441 | ||
190f68c5 ACO |
7442 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7443 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7444 | { |
c7653199 | 7445 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7446 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7447 | int refclk, num_connectors = 0; |
652c393a | 7448 | intel_clock_t clock, reduced_clock; |
a16af721 | 7449 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7450 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7451 | struct intel_encoder *encoder; |
d4906093 | 7452 | const intel_limit_t *limit; |
55bb9992 | 7453 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7454 | struct drm_connector *connector; |
55bb9992 ACO |
7455 | struct drm_connector_state *connector_state; |
7456 | int i; | |
79e53945 | 7457 | |
dd3cd74a ACO |
7458 | memset(&crtc_state->dpll_hw_state, 0, |
7459 | sizeof(crtc_state->dpll_hw_state)); | |
7460 | ||
da3ced29 | 7461 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7462 | if (connector_state->crtc != &crtc->base) |
7463 | continue; | |
7464 | ||
7465 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7466 | ||
5eddb70b | 7467 | switch (encoder->type) { |
79e53945 JB |
7468 | case INTEL_OUTPUT_LVDS: |
7469 | is_lvds = true; | |
7470 | break; | |
e9fd1c02 JN |
7471 | case INTEL_OUTPUT_DSI: |
7472 | is_dsi = true; | |
7473 | break; | |
6847d71b PZ |
7474 | default: |
7475 | break; | |
79e53945 | 7476 | } |
43565a06 | 7477 | |
c751ce4f | 7478 | num_connectors++; |
79e53945 JB |
7479 | } |
7480 | ||
f2335330 | 7481 | if (is_dsi) |
5b18e57c | 7482 | return 0; |
f2335330 | 7483 | |
190f68c5 | 7484 | if (!crtc_state->clock_set) { |
a93e255f | 7485 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7486 | |
e9fd1c02 JN |
7487 | /* |
7488 | * Returns a set of divisors for the desired target clock with | |
7489 | * the given refclk, or FALSE. The returned values represent | |
7490 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7491 | * 2) / p1 / p2. | |
7492 | */ | |
a93e255f ACO |
7493 | limit = intel_limit(crtc_state, refclk); |
7494 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7495 | crtc_state->port_clock, |
e9fd1c02 | 7496 | refclk, NULL, &clock); |
f2335330 | 7497 | if (!ok) { |
e9fd1c02 JN |
7498 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7499 | return -EINVAL; | |
7500 | } | |
79e53945 | 7501 | |
f2335330 JN |
7502 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7503 | /* | |
7504 | * Ensure we match the reduced clock's P to the target | |
7505 | * clock. If the clocks don't match, we can't switch | |
7506 | * the display clock by using the FP0/FP1. In such case | |
7507 | * we will disable the LVDS downclock feature. | |
7508 | */ | |
7509 | has_reduced_clock = | |
a93e255f | 7510 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7511 | dev_priv->lvds_downclock, |
7512 | refclk, &clock, | |
7513 | &reduced_clock); | |
7514 | } | |
7515 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7516 | crtc_state->dpll.n = clock.n; |
7517 | crtc_state->dpll.m1 = clock.m1; | |
7518 | crtc_state->dpll.m2 = clock.m2; | |
7519 | crtc_state->dpll.p1 = clock.p1; | |
7520 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7521 | } |
7026d4ac | 7522 | |
e9fd1c02 | 7523 | if (IS_GEN2(dev)) { |
190f68c5 | 7524 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7525 | has_reduced_clock ? &reduced_clock : NULL, |
7526 | num_connectors); | |
9d556c99 | 7527 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7528 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7529 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7530 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7531 | } else { |
190f68c5 | 7532 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7533 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7534 | num_connectors); |
e9fd1c02 | 7535 | } |
79e53945 | 7536 | |
c8f7a0db | 7537 | return 0; |
f564048e EA |
7538 | } |
7539 | ||
2fa2fe9a | 7540 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7541 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7542 | { |
7543 | struct drm_device *dev = crtc->base.dev; | |
7544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7545 | uint32_t tmp; | |
7546 | ||
dc9e7dec VS |
7547 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7548 | return; | |
7549 | ||
2fa2fe9a | 7550 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7551 | if (!(tmp & PFIT_ENABLE)) |
7552 | return; | |
2fa2fe9a | 7553 | |
06922821 | 7554 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7555 | if (INTEL_INFO(dev)->gen < 4) { |
7556 | if (crtc->pipe != PIPE_B) | |
7557 | return; | |
2fa2fe9a DV |
7558 | } else { |
7559 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7560 | return; | |
7561 | } | |
7562 | ||
06922821 | 7563 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7564 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7565 | if (INTEL_INFO(dev)->gen < 5) | |
7566 | pipe_config->gmch_pfit.lvds_border_bits = | |
7567 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7568 | } | |
7569 | ||
acbec814 | 7570 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7571 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7572 | { |
7573 | struct drm_device *dev = crtc->base.dev; | |
7574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7575 | int pipe = pipe_config->cpu_transcoder; | |
7576 | intel_clock_t clock; | |
7577 | u32 mdiv; | |
662c6ecb | 7578 | int refclk = 100000; |
acbec814 | 7579 | |
f573de5a SK |
7580 | /* In case of MIPI DPLL will not even be used */ |
7581 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7582 | return; | |
7583 | ||
acbec814 | 7584 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7585 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7586 | mutex_unlock(&dev_priv->dpio_lock); |
7587 | ||
7588 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7589 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7590 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7591 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7592 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7593 | ||
f646628b | 7594 | vlv_clock(refclk, &clock); |
acbec814 | 7595 | |
f646628b VS |
7596 | /* clock.dot is the fast clock */ |
7597 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7598 | } |
7599 | ||
5724dbd1 DL |
7600 | static void |
7601 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7602 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7603 | { |
7604 | struct drm_device *dev = crtc->base.dev; | |
7605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7606 | u32 val, base, offset; | |
7607 | int pipe = crtc->pipe, plane = crtc->plane; | |
7608 | int fourcc, pixel_format; | |
6761dd31 | 7609 | unsigned int aligned_height; |
b113d5ee | 7610 | struct drm_framebuffer *fb; |
1b842c89 | 7611 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7612 | |
42a7b088 DL |
7613 | val = I915_READ(DSPCNTR(plane)); |
7614 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7615 | return; | |
7616 | ||
d9806c9f | 7617 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7618 | if (!intel_fb) { |
1ad292b5 JB |
7619 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7620 | return; | |
7621 | } | |
7622 | ||
1b842c89 DL |
7623 | fb = &intel_fb->base; |
7624 | ||
18c5247e DV |
7625 | if (INTEL_INFO(dev)->gen >= 4) { |
7626 | if (val & DISPPLANE_TILED) { | |
49af449b | 7627 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7628 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7629 | } | |
7630 | } | |
1ad292b5 JB |
7631 | |
7632 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7633 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7634 | fb->pixel_format = fourcc; |
7635 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7636 | |
7637 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7638 | if (plane_config->tiling) |
1ad292b5 JB |
7639 | offset = I915_READ(DSPTILEOFF(plane)); |
7640 | else | |
7641 | offset = I915_READ(DSPLINOFF(plane)); | |
7642 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7643 | } else { | |
7644 | base = I915_READ(DSPADDR(plane)); | |
7645 | } | |
7646 | plane_config->base = base; | |
7647 | ||
7648 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7649 | fb->width = ((val >> 16) & 0xfff) + 1; |
7650 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7651 | |
7652 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7653 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7654 | |
b113d5ee | 7655 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7656 | fb->pixel_format, |
7657 | fb->modifier[0]); | |
1ad292b5 | 7658 | |
f37b5c2b | 7659 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7660 | |
2844a921 DL |
7661 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7662 | pipe_name(pipe), plane, fb->width, fb->height, | |
7663 | fb->bits_per_pixel, base, fb->pitches[0], | |
7664 | plane_config->size); | |
1ad292b5 | 7665 | |
2d14030b | 7666 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7667 | } |
7668 | ||
70b23a98 | 7669 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7670 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7671 | { |
7672 | struct drm_device *dev = crtc->base.dev; | |
7673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7674 | int pipe = pipe_config->cpu_transcoder; | |
7675 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7676 | intel_clock_t clock; | |
7677 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7678 | int refclk = 100000; | |
7679 | ||
7680 | mutex_lock(&dev_priv->dpio_lock); | |
7681 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7682 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7683 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7684 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7685 | mutex_unlock(&dev_priv->dpio_lock); | |
7686 | ||
7687 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7688 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7689 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7690 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7691 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7692 | ||
7693 | chv_clock(refclk, &clock); | |
7694 | ||
7695 | /* clock.dot is the fast clock */ | |
7696 | pipe_config->port_clock = clock.dot / 5; | |
7697 | } | |
7698 | ||
0e8ffe1b | 7699 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7700 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7701 | { |
7702 | struct drm_device *dev = crtc->base.dev; | |
7703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7704 | uint32_t tmp; | |
7705 | ||
f458ebbc DV |
7706 | if (!intel_display_power_is_enabled(dev_priv, |
7707 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7708 | return false; |
7709 | ||
e143a21c | 7710 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7711 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7712 | |
0e8ffe1b DV |
7713 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7714 | if (!(tmp & PIPECONF_ENABLE)) | |
7715 | return false; | |
7716 | ||
42571aef VS |
7717 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7718 | switch (tmp & PIPECONF_BPC_MASK) { | |
7719 | case PIPECONF_6BPC: | |
7720 | pipe_config->pipe_bpp = 18; | |
7721 | break; | |
7722 | case PIPECONF_8BPC: | |
7723 | pipe_config->pipe_bpp = 24; | |
7724 | break; | |
7725 | case PIPECONF_10BPC: | |
7726 | pipe_config->pipe_bpp = 30; | |
7727 | break; | |
7728 | default: | |
7729 | break; | |
7730 | } | |
7731 | } | |
7732 | ||
b5a9fa09 DV |
7733 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7734 | pipe_config->limited_color_range = true; | |
7735 | ||
282740f7 VS |
7736 | if (INTEL_INFO(dev)->gen < 4) |
7737 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7738 | ||
1bd1bd80 DV |
7739 | intel_get_pipe_timings(crtc, pipe_config); |
7740 | ||
2fa2fe9a DV |
7741 | i9xx_get_pfit_config(crtc, pipe_config); |
7742 | ||
6c49f241 DV |
7743 | if (INTEL_INFO(dev)->gen >= 4) { |
7744 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7745 | pipe_config->pixel_multiplier = | |
7746 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7747 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7748 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7749 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7750 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7751 | pipe_config->pixel_multiplier = | |
7752 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7753 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7754 | } else { | |
7755 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7756 | * port and will be fixed up in the encoder->get_config | |
7757 | * function. */ | |
7758 | pipe_config->pixel_multiplier = 1; | |
7759 | } | |
8bcc2795 DV |
7760 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7761 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7762 | /* |
7763 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7764 | * on 830. Filter it out here so that we don't | |
7765 | * report errors due to that. | |
7766 | */ | |
7767 | if (IS_I830(dev)) | |
7768 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7769 | ||
8bcc2795 DV |
7770 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7771 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7772 | } else { |
7773 | /* Mask out read-only status bits. */ | |
7774 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7775 | DPLL_PORTC_READY_MASK | | |
7776 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7777 | } |
6c49f241 | 7778 | |
70b23a98 VS |
7779 | if (IS_CHERRYVIEW(dev)) |
7780 | chv_crtc_clock_get(crtc, pipe_config); | |
7781 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7782 | vlv_crtc_clock_get(crtc, pipe_config); |
7783 | else | |
7784 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7785 | |
0e8ffe1b DV |
7786 | return true; |
7787 | } | |
7788 | ||
dde86e2d | 7789 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7790 | { |
7791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7792 | struct intel_encoder *encoder; |
74cfd7ac | 7793 | u32 val, final; |
13d83a67 | 7794 | bool has_lvds = false; |
199e5d79 | 7795 | bool has_cpu_edp = false; |
199e5d79 | 7796 | bool has_panel = false; |
99eb6a01 KP |
7797 | bool has_ck505 = false; |
7798 | bool can_ssc = false; | |
13d83a67 JB |
7799 | |
7800 | /* We need to take the global config into account */ | |
b2784e15 | 7801 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7802 | switch (encoder->type) { |
7803 | case INTEL_OUTPUT_LVDS: | |
7804 | has_panel = true; | |
7805 | has_lvds = true; | |
7806 | break; | |
7807 | case INTEL_OUTPUT_EDP: | |
7808 | has_panel = true; | |
2de6905f | 7809 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7810 | has_cpu_edp = true; |
7811 | break; | |
6847d71b PZ |
7812 | default: |
7813 | break; | |
13d83a67 JB |
7814 | } |
7815 | } | |
7816 | ||
99eb6a01 | 7817 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7818 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7819 | can_ssc = has_ck505; |
7820 | } else { | |
7821 | has_ck505 = false; | |
7822 | can_ssc = true; | |
7823 | } | |
7824 | ||
2de6905f ID |
7825 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7826 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7827 | |
7828 | /* Ironlake: try to setup display ref clock before DPLL | |
7829 | * enabling. This is only under driver's control after | |
7830 | * PCH B stepping, previous chipset stepping should be | |
7831 | * ignoring this setting. | |
7832 | */ | |
74cfd7ac CW |
7833 | val = I915_READ(PCH_DREF_CONTROL); |
7834 | ||
7835 | /* As we must carefully and slowly disable/enable each source in turn, | |
7836 | * compute the final state we want first and check if we need to | |
7837 | * make any changes at all. | |
7838 | */ | |
7839 | final = val; | |
7840 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7841 | if (has_ck505) | |
7842 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7843 | else | |
7844 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7845 | ||
7846 | final &= ~DREF_SSC_SOURCE_MASK; | |
7847 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7848 | final &= ~DREF_SSC1_ENABLE; | |
7849 | ||
7850 | if (has_panel) { | |
7851 | final |= DREF_SSC_SOURCE_ENABLE; | |
7852 | ||
7853 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7854 | final |= DREF_SSC1_ENABLE; | |
7855 | ||
7856 | if (has_cpu_edp) { | |
7857 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7858 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7859 | else | |
7860 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7861 | } else | |
7862 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7863 | } else { | |
7864 | final |= DREF_SSC_SOURCE_DISABLE; | |
7865 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7866 | } | |
7867 | ||
7868 | if (final == val) | |
7869 | return; | |
7870 | ||
13d83a67 | 7871 | /* Always enable nonspread source */ |
74cfd7ac | 7872 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7873 | |
99eb6a01 | 7874 | if (has_ck505) |
74cfd7ac | 7875 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7876 | else |
74cfd7ac | 7877 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7878 | |
199e5d79 | 7879 | if (has_panel) { |
74cfd7ac CW |
7880 | val &= ~DREF_SSC_SOURCE_MASK; |
7881 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7882 | |
199e5d79 | 7883 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7884 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7885 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7886 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7887 | } else |
74cfd7ac | 7888 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7889 | |
7890 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7891 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7892 | POSTING_READ(PCH_DREF_CONTROL); |
7893 | udelay(200); | |
7894 | ||
74cfd7ac | 7895 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7896 | |
7897 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7898 | if (has_cpu_edp) { |
99eb6a01 | 7899 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7900 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7901 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7902 | } else |
74cfd7ac | 7903 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7904 | } else |
74cfd7ac | 7905 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7906 | |
74cfd7ac | 7907 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7908 | POSTING_READ(PCH_DREF_CONTROL); |
7909 | udelay(200); | |
7910 | } else { | |
7911 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7912 | ||
74cfd7ac | 7913 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7914 | |
7915 | /* Turn off CPU output */ | |
74cfd7ac | 7916 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7917 | |
74cfd7ac | 7918 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7919 | POSTING_READ(PCH_DREF_CONTROL); |
7920 | udelay(200); | |
7921 | ||
7922 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7923 | val &= ~DREF_SSC_SOURCE_MASK; |
7924 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7925 | |
7926 | /* Turn off SSC1 */ | |
74cfd7ac | 7927 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7928 | |
74cfd7ac | 7929 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7930 | POSTING_READ(PCH_DREF_CONTROL); |
7931 | udelay(200); | |
7932 | } | |
74cfd7ac CW |
7933 | |
7934 | BUG_ON(val != final); | |
13d83a67 JB |
7935 | } |
7936 | ||
f31f2d55 | 7937 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7938 | { |
f31f2d55 | 7939 | uint32_t tmp; |
dde86e2d | 7940 | |
0ff066a9 PZ |
7941 | tmp = I915_READ(SOUTH_CHICKEN2); |
7942 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7943 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7944 | |
0ff066a9 PZ |
7945 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7946 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7947 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7948 | |
0ff066a9 PZ |
7949 | tmp = I915_READ(SOUTH_CHICKEN2); |
7950 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7951 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7952 | |
0ff066a9 PZ |
7953 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7954 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7955 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7956 | } |
7957 | ||
7958 | /* WaMPhyProgramming:hsw */ | |
7959 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7960 | { | |
7961 | uint32_t tmp; | |
dde86e2d PZ |
7962 | |
7963 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7964 | tmp &= ~(0xFF << 24); | |
7965 | tmp |= (0x12 << 24); | |
7966 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7967 | ||
dde86e2d PZ |
7968 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7969 | tmp |= (1 << 11); | |
7970 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7971 | ||
7972 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7973 | tmp |= (1 << 11); | |
7974 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7975 | ||
dde86e2d PZ |
7976 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7977 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7978 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7979 | ||
7980 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7981 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7982 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7983 | ||
0ff066a9 PZ |
7984 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7985 | tmp &= ~(7 << 13); | |
7986 | tmp |= (5 << 13); | |
7987 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7988 | |
0ff066a9 PZ |
7989 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7990 | tmp &= ~(7 << 13); | |
7991 | tmp |= (5 << 13); | |
7992 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7993 | |
7994 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7995 | tmp &= ~0xFF; | |
7996 | tmp |= 0x1C; | |
7997 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7998 | ||
7999 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8000 | tmp &= ~0xFF; | |
8001 | tmp |= 0x1C; | |
8002 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8003 | ||
8004 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8005 | tmp &= ~(0xFF << 16); | |
8006 | tmp |= (0x1C << 16); | |
8007 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8008 | ||
8009 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8010 | tmp &= ~(0xFF << 16); | |
8011 | tmp |= (0x1C << 16); | |
8012 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8013 | ||
0ff066a9 PZ |
8014 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8015 | tmp |= (1 << 27); | |
8016 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8017 | |
0ff066a9 PZ |
8018 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8019 | tmp |= (1 << 27); | |
8020 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8021 | |
0ff066a9 PZ |
8022 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8023 | tmp &= ~(0xF << 28); | |
8024 | tmp |= (4 << 28); | |
8025 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8026 | |
0ff066a9 PZ |
8027 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8028 | tmp &= ~(0xF << 28); | |
8029 | tmp |= (4 << 28); | |
8030 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8031 | } |
8032 | ||
2fa86a1f PZ |
8033 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8034 | * Programming" based on the parameters passed: | |
8035 | * - Sequence to enable CLKOUT_DP | |
8036 | * - Sequence to enable CLKOUT_DP without spread | |
8037 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8038 | */ | |
8039 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8040 | bool with_fdi) | |
f31f2d55 PZ |
8041 | { |
8042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8043 | uint32_t reg, tmp; |
8044 | ||
8045 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8046 | with_spread = true; | |
8047 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8048 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8049 | with_fdi = false; | |
f31f2d55 PZ |
8050 | |
8051 | mutex_lock(&dev_priv->dpio_lock); | |
8052 | ||
8053 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8054 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8055 | tmp |= SBI_SSCCTL_PATHALT; | |
8056 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8057 | ||
8058 | udelay(24); | |
8059 | ||
2fa86a1f PZ |
8060 | if (with_spread) { |
8061 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8062 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8063 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8064 | |
2fa86a1f PZ |
8065 | if (with_fdi) { |
8066 | lpt_reset_fdi_mphy(dev_priv); | |
8067 | lpt_program_fdi_mphy(dev_priv); | |
8068 | } | |
8069 | } | |
dde86e2d | 8070 | |
2fa86a1f PZ |
8071 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8072 | SBI_GEN0 : SBI_DBUFF0; | |
8073 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8074 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8075 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
8076 | |
8077 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
8078 | } |
8079 | ||
47701c3b PZ |
8080 | /* Sequence to disable CLKOUT_DP */ |
8081 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8082 | { | |
8083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8084 | uint32_t reg, tmp; | |
8085 | ||
8086 | mutex_lock(&dev_priv->dpio_lock); | |
8087 | ||
8088 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8089 | SBI_GEN0 : SBI_DBUFF0; | |
8090 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8091 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8092 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8093 | ||
8094 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8095 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8096 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8097 | tmp |= SBI_SSCCTL_PATHALT; | |
8098 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8099 | udelay(32); | |
8100 | } | |
8101 | tmp |= SBI_SSCCTL_DISABLE; | |
8102 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8103 | } | |
8104 | ||
8105 | mutex_unlock(&dev_priv->dpio_lock); | |
8106 | } | |
8107 | ||
bf8fa3d3 PZ |
8108 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8109 | { | |
bf8fa3d3 PZ |
8110 | struct intel_encoder *encoder; |
8111 | bool has_vga = false; | |
8112 | ||
b2784e15 | 8113 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8114 | switch (encoder->type) { |
8115 | case INTEL_OUTPUT_ANALOG: | |
8116 | has_vga = true; | |
8117 | break; | |
6847d71b PZ |
8118 | default: |
8119 | break; | |
bf8fa3d3 PZ |
8120 | } |
8121 | } | |
8122 | ||
47701c3b PZ |
8123 | if (has_vga) |
8124 | lpt_enable_clkout_dp(dev, true, true); | |
8125 | else | |
8126 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8127 | } |
8128 | ||
dde86e2d PZ |
8129 | /* |
8130 | * Initialize reference clocks when the driver loads | |
8131 | */ | |
8132 | void intel_init_pch_refclk(struct drm_device *dev) | |
8133 | { | |
8134 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8135 | ironlake_init_pch_refclk(dev); | |
8136 | else if (HAS_PCH_LPT(dev)) | |
8137 | lpt_init_pch_refclk(dev); | |
8138 | } | |
8139 | ||
55bb9992 | 8140 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8141 | { |
55bb9992 | 8142 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8143 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8144 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8145 | struct drm_connector *connector; |
55bb9992 | 8146 | struct drm_connector_state *connector_state; |
d9d444cb | 8147 | struct intel_encoder *encoder; |
55bb9992 | 8148 | int num_connectors = 0, i; |
d9d444cb JB |
8149 | bool is_lvds = false; |
8150 | ||
da3ced29 | 8151 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8152 | if (connector_state->crtc != crtc_state->base.crtc) |
8153 | continue; | |
8154 | ||
8155 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8156 | ||
d9d444cb JB |
8157 | switch (encoder->type) { |
8158 | case INTEL_OUTPUT_LVDS: | |
8159 | is_lvds = true; | |
8160 | break; | |
6847d71b PZ |
8161 | default: |
8162 | break; | |
d9d444cb JB |
8163 | } |
8164 | num_connectors++; | |
8165 | } | |
8166 | ||
8167 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8168 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8169 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8170 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8171 | } |
8172 | ||
8173 | return 120000; | |
8174 | } | |
8175 | ||
6ff93609 | 8176 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8177 | { |
c8203565 | 8178 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8179 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8180 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8181 | uint32_t val; |
8182 | ||
78114071 | 8183 | val = 0; |
c8203565 | 8184 | |
6e3c9717 | 8185 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8186 | case 18: |
dfd07d72 | 8187 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8188 | break; |
8189 | case 24: | |
dfd07d72 | 8190 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8191 | break; |
8192 | case 30: | |
dfd07d72 | 8193 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8194 | break; |
8195 | case 36: | |
dfd07d72 | 8196 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8197 | break; |
8198 | default: | |
cc769b62 PZ |
8199 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8200 | BUG(); | |
c8203565 PZ |
8201 | } |
8202 | ||
6e3c9717 | 8203 | if (intel_crtc->config->dither) |
c8203565 PZ |
8204 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8205 | ||
6e3c9717 | 8206 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8207 | val |= PIPECONF_INTERLACED_ILK; |
8208 | else | |
8209 | val |= PIPECONF_PROGRESSIVE; | |
8210 | ||
6e3c9717 | 8211 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8212 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8213 | |
c8203565 PZ |
8214 | I915_WRITE(PIPECONF(pipe), val); |
8215 | POSTING_READ(PIPECONF(pipe)); | |
8216 | } | |
8217 | ||
86d3efce VS |
8218 | /* |
8219 | * Set up the pipe CSC unit. | |
8220 | * | |
8221 | * Currently only full range RGB to limited range RGB conversion | |
8222 | * is supported, but eventually this should handle various | |
8223 | * RGB<->YCbCr scenarios as well. | |
8224 | */ | |
50f3b016 | 8225 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8226 | { |
8227 | struct drm_device *dev = crtc->dev; | |
8228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8230 | int pipe = intel_crtc->pipe; | |
8231 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8232 | ||
8233 | /* | |
8234 | * TODO: Check what kind of values actually come out of the pipe | |
8235 | * with these coeff/postoff values and adjust to get the best | |
8236 | * accuracy. Perhaps we even need to take the bpc value into | |
8237 | * consideration. | |
8238 | */ | |
8239 | ||
6e3c9717 | 8240 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8241 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8242 | ||
8243 | /* | |
8244 | * GY/GU and RY/RU should be the other way around according | |
8245 | * to BSpec, but reality doesn't agree. Just set them up in | |
8246 | * a way that results in the correct picture. | |
8247 | */ | |
8248 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8249 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8250 | ||
8251 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8252 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8253 | ||
8254 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8255 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8256 | ||
8257 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8258 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8259 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8260 | ||
8261 | if (INTEL_INFO(dev)->gen > 6) { | |
8262 | uint16_t postoff = 0; | |
8263 | ||
6e3c9717 | 8264 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8265 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8266 | |
8267 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8268 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8269 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8270 | ||
8271 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8272 | } else { | |
8273 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8274 | ||
6e3c9717 | 8275 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8276 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8277 | ||
8278 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8279 | } | |
8280 | } | |
8281 | ||
6ff93609 | 8282 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8283 | { |
756f85cf PZ |
8284 | struct drm_device *dev = crtc->dev; |
8285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8287 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8288 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8289 | uint32_t val; |
8290 | ||
3eff4faa | 8291 | val = 0; |
ee2b0b38 | 8292 | |
6e3c9717 | 8293 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8294 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8295 | ||
6e3c9717 | 8296 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8297 | val |= PIPECONF_INTERLACED_ILK; |
8298 | else | |
8299 | val |= PIPECONF_PROGRESSIVE; | |
8300 | ||
702e7a56 PZ |
8301 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8302 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8303 | |
8304 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8305 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8306 | |
3cdf122c | 8307 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8308 | val = 0; |
8309 | ||
6e3c9717 | 8310 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8311 | case 18: |
8312 | val |= PIPEMISC_DITHER_6_BPC; | |
8313 | break; | |
8314 | case 24: | |
8315 | val |= PIPEMISC_DITHER_8_BPC; | |
8316 | break; | |
8317 | case 30: | |
8318 | val |= PIPEMISC_DITHER_10_BPC; | |
8319 | break; | |
8320 | case 36: | |
8321 | val |= PIPEMISC_DITHER_12_BPC; | |
8322 | break; | |
8323 | default: | |
8324 | /* Case prevented by pipe_config_set_bpp. */ | |
8325 | BUG(); | |
8326 | } | |
8327 | ||
6e3c9717 | 8328 | if (intel_crtc->config->dither) |
756f85cf PZ |
8329 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8330 | ||
8331 | I915_WRITE(PIPEMISC(pipe), val); | |
8332 | } | |
ee2b0b38 PZ |
8333 | } |
8334 | ||
6591c6e4 | 8335 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8336 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8337 | intel_clock_t *clock, |
8338 | bool *has_reduced_clock, | |
8339 | intel_clock_t *reduced_clock) | |
8340 | { | |
8341 | struct drm_device *dev = crtc->dev; | |
8342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8343 | int refclk; |
d4906093 | 8344 | const intel_limit_t *limit; |
a16af721 | 8345 | bool ret, is_lvds = false; |
79e53945 | 8346 | |
a93e255f | 8347 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8348 | |
55bb9992 | 8349 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8350 | |
d4906093 ML |
8351 | /* |
8352 | * Returns a set of divisors for the desired target clock with the given | |
8353 | * refclk, or FALSE. The returned values represent the clock equation: | |
8354 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8355 | */ | |
a93e255f ACO |
8356 | limit = intel_limit(crtc_state, refclk); |
8357 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8358 | crtc_state->port_clock, |
ee9300bb | 8359 | refclk, NULL, clock); |
6591c6e4 PZ |
8360 | if (!ret) |
8361 | return false; | |
cda4b7d3 | 8362 | |
ddc9003c | 8363 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8364 | /* |
8365 | * Ensure we match the reduced clock's P to the target clock. | |
8366 | * If the clocks don't match, we can't switch the display clock | |
8367 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8368 | * downclock feature. | |
8369 | */ | |
ee9300bb | 8370 | *has_reduced_clock = |
a93e255f | 8371 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8372 | dev_priv->lvds_downclock, |
8373 | refclk, clock, | |
8374 | reduced_clock); | |
652c393a | 8375 | } |
61e9653f | 8376 | |
6591c6e4 PZ |
8377 | return true; |
8378 | } | |
8379 | ||
d4b1931c PZ |
8380 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8381 | { | |
8382 | /* | |
8383 | * Account for spread spectrum to avoid | |
8384 | * oversubscribing the link. Max center spread | |
8385 | * is 2.5%; use 5% for safety's sake. | |
8386 | */ | |
8387 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8388 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8389 | } |
8390 | ||
7429e9d4 | 8391 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8392 | { |
7429e9d4 | 8393 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8394 | } |
8395 | ||
de13a2e3 | 8396 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8397 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8398 | u32 *fp, |
9a7c7890 | 8399 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8400 | { |
de13a2e3 | 8401 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8402 | struct drm_device *dev = crtc->dev; |
8403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8404 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8405 | struct drm_connector *connector; |
55bb9992 ACO |
8406 | struct drm_connector_state *connector_state; |
8407 | struct intel_encoder *encoder; | |
de13a2e3 | 8408 | uint32_t dpll; |
55bb9992 | 8409 | int factor, num_connectors = 0, i; |
09ede541 | 8410 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8411 | |
da3ced29 | 8412 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8413 | if (connector_state->crtc != crtc_state->base.crtc) |
8414 | continue; | |
8415 | ||
8416 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8417 | ||
8418 | switch (encoder->type) { | |
79e53945 JB |
8419 | case INTEL_OUTPUT_LVDS: |
8420 | is_lvds = true; | |
8421 | break; | |
8422 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8423 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8424 | is_sdvo = true; |
79e53945 | 8425 | break; |
6847d71b PZ |
8426 | default: |
8427 | break; | |
79e53945 | 8428 | } |
43565a06 | 8429 | |
c751ce4f | 8430 | num_connectors++; |
79e53945 | 8431 | } |
79e53945 | 8432 | |
c1858123 | 8433 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8434 | factor = 21; |
8435 | if (is_lvds) { | |
8436 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8437 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8438 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8439 | factor = 25; |
190f68c5 | 8440 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8441 | factor = 20; |
c1858123 | 8442 | |
190f68c5 | 8443 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8444 | *fp |= FP_CB_TUNE; |
2c07245f | 8445 | |
9a7c7890 DV |
8446 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8447 | *fp2 |= FP_CB_TUNE; | |
8448 | ||
5eddb70b | 8449 | dpll = 0; |
2c07245f | 8450 | |
a07d6787 EA |
8451 | if (is_lvds) |
8452 | dpll |= DPLLB_MODE_LVDS; | |
8453 | else | |
8454 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8455 | |
190f68c5 | 8456 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8457 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8458 | |
8459 | if (is_sdvo) | |
4a33e48d | 8460 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8461 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8462 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8463 | |
a07d6787 | 8464 | /* compute bitmask from p1 value */ |
190f68c5 | 8465 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8466 | /* also FPA1 */ |
190f68c5 | 8467 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8468 | |
190f68c5 | 8469 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8470 | case 5: |
8471 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8472 | break; | |
8473 | case 7: | |
8474 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8475 | break; | |
8476 | case 10: | |
8477 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8478 | break; | |
8479 | case 14: | |
8480 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8481 | break; | |
79e53945 JB |
8482 | } |
8483 | ||
b4c09f3b | 8484 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8485 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8486 | else |
8487 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8488 | ||
959e16d6 | 8489 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8490 | } |
8491 | ||
190f68c5 ACO |
8492 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8493 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8494 | { |
c7653199 | 8495 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8496 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8497 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8498 | bool ok, has_reduced_clock = false; |
8b47047b | 8499 | bool is_lvds = false; |
e2b78267 | 8500 | struct intel_shared_dpll *pll; |
de13a2e3 | 8501 | |
dd3cd74a ACO |
8502 | memset(&crtc_state->dpll_hw_state, 0, |
8503 | sizeof(crtc_state->dpll_hw_state)); | |
8504 | ||
409ee761 | 8505 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8506 | |
5dc5298b PZ |
8507 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8508 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8509 | |
190f68c5 | 8510 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8511 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8512 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8513 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8514 | return -EINVAL; | |
79e53945 | 8515 | } |
f47709a9 | 8516 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8517 | if (!crtc_state->clock_set) { |
8518 | crtc_state->dpll.n = clock.n; | |
8519 | crtc_state->dpll.m1 = clock.m1; | |
8520 | crtc_state->dpll.m2 = clock.m2; | |
8521 | crtc_state->dpll.p1 = clock.p1; | |
8522 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8523 | } |
79e53945 | 8524 | |
5dc5298b | 8525 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8526 | if (crtc_state->has_pch_encoder) { |
8527 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8528 | if (has_reduced_clock) |
7429e9d4 | 8529 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8530 | |
190f68c5 | 8531 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8532 | &fp, &reduced_clock, |
8533 | has_reduced_clock ? &fp2 : NULL); | |
8534 | ||
190f68c5 ACO |
8535 | crtc_state->dpll_hw_state.dpll = dpll; |
8536 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8537 | if (has_reduced_clock) |
190f68c5 | 8538 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8539 | else |
190f68c5 | 8540 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8541 | |
190f68c5 | 8542 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8543 | if (pll == NULL) { |
84f44ce7 | 8544 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8545 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8546 | return -EINVAL; |
8547 | } | |
3fb37703 | 8548 | } |
79e53945 | 8549 | |
ab585dea | 8550 | if (is_lvds && has_reduced_clock) |
c7653199 | 8551 | crtc->lowfreq_avail = true; |
bcd644e0 | 8552 | else |
c7653199 | 8553 | crtc->lowfreq_avail = false; |
e2b78267 | 8554 | |
c8f7a0db | 8555 | return 0; |
79e53945 JB |
8556 | } |
8557 | ||
eb14cb74 VS |
8558 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8559 | struct intel_link_m_n *m_n) | |
8560 | { | |
8561 | struct drm_device *dev = crtc->base.dev; | |
8562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8563 | enum pipe pipe = crtc->pipe; | |
8564 | ||
8565 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8566 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8567 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8568 | & ~TU_SIZE_MASK; | |
8569 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8570 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8571 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8572 | } | |
8573 | ||
8574 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8575 | enum transcoder transcoder, | |
b95af8be VK |
8576 | struct intel_link_m_n *m_n, |
8577 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8578 | { |
8579 | struct drm_device *dev = crtc->base.dev; | |
8580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8581 | enum pipe pipe = crtc->pipe; |
72419203 | 8582 | |
eb14cb74 VS |
8583 | if (INTEL_INFO(dev)->gen >= 5) { |
8584 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8585 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8586 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8587 | & ~TU_SIZE_MASK; | |
8588 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8589 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8590 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8591 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8592 | * gen < 8) and if DRRS is supported (to make sure the | |
8593 | * registers are not unnecessarily read). | |
8594 | */ | |
8595 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8596 | crtc->config->has_drrs) { |
b95af8be VK |
8597 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8598 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8599 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8600 | & ~TU_SIZE_MASK; | |
8601 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8602 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8603 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8604 | } | |
eb14cb74 VS |
8605 | } else { |
8606 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8607 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8608 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8609 | & ~TU_SIZE_MASK; | |
8610 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8611 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8612 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8613 | } | |
8614 | } | |
8615 | ||
8616 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8617 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8618 | { |
681a8504 | 8619 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8620 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8621 | else | |
8622 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8623 | &pipe_config->dp_m_n, |
8624 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8625 | } |
72419203 | 8626 | |
eb14cb74 | 8627 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8628 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8629 | { |
8630 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8631 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8632 | } |
8633 | ||
bd2e244f | 8634 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8635 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8636 | { |
8637 | struct drm_device *dev = crtc->base.dev; | |
8638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8639 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8640 | uint32_t ps_ctrl = 0; | |
8641 | int id = -1; | |
8642 | int i; | |
bd2e244f | 8643 | |
a1b2278e CK |
8644 | /* find scaler attached to this pipe */ |
8645 | for (i = 0; i < crtc->num_scalers; i++) { | |
8646 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8647 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8648 | id = i; | |
8649 | pipe_config->pch_pfit.enabled = true; | |
8650 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8651 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8652 | break; | |
8653 | } | |
8654 | } | |
bd2e244f | 8655 | |
a1b2278e CK |
8656 | scaler_state->scaler_id = id; |
8657 | if (id >= 0) { | |
8658 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8659 | } else { | |
8660 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8661 | } |
8662 | } | |
8663 | ||
5724dbd1 DL |
8664 | static void |
8665 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8666 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8667 | { |
8668 | struct drm_device *dev = crtc->base.dev; | |
8669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8670 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8671 | int pipe = crtc->pipe; |
8672 | int fourcc, pixel_format; | |
6761dd31 | 8673 | unsigned int aligned_height; |
bc8d7dff | 8674 | struct drm_framebuffer *fb; |
1b842c89 | 8675 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8676 | |
d9806c9f | 8677 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8678 | if (!intel_fb) { |
bc8d7dff DL |
8679 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8680 | return; | |
8681 | } | |
8682 | ||
1b842c89 DL |
8683 | fb = &intel_fb->base; |
8684 | ||
bc8d7dff | 8685 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8686 | if (!(val & PLANE_CTL_ENABLE)) |
8687 | goto error; | |
8688 | ||
bc8d7dff DL |
8689 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8690 | fourcc = skl_format_to_fourcc(pixel_format, | |
8691 | val & PLANE_CTL_ORDER_RGBX, | |
8692 | val & PLANE_CTL_ALPHA_MASK); | |
8693 | fb->pixel_format = fourcc; | |
8694 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8695 | ||
40f46283 DL |
8696 | tiling = val & PLANE_CTL_TILED_MASK; |
8697 | switch (tiling) { | |
8698 | case PLANE_CTL_TILED_LINEAR: | |
8699 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8700 | break; | |
8701 | case PLANE_CTL_TILED_X: | |
8702 | plane_config->tiling = I915_TILING_X; | |
8703 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8704 | break; | |
8705 | case PLANE_CTL_TILED_Y: | |
8706 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8707 | break; | |
8708 | case PLANE_CTL_TILED_YF: | |
8709 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8710 | break; | |
8711 | default: | |
8712 | MISSING_CASE(tiling); | |
8713 | goto error; | |
8714 | } | |
8715 | ||
bc8d7dff DL |
8716 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8717 | plane_config->base = base; | |
8718 | ||
8719 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8720 | ||
8721 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8722 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8723 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8724 | ||
8725 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8726 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8727 | fb->pixel_format); | |
bc8d7dff DL |
8728 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8729 | ||
8730 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8731 | fb->pixel_format, |
8732 | fb->modifier[0]); | |
bc8d7dff | 8733 | |
f37b5c2b | 8734 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8735 | |
8736 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8737 | pipe_name(pipe), fb->width, fb->height, | |
8738 | fb->bits_per_pixel, base, fb->pitches[0], | |
8739 | plane_config->size); | |
8740 | ||
2d14030b | 8741 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8742 | return; |
8743 | ||
8744 | error: | |
8745 | kfree(fb); | |
8746 | } | |
8747 | ||
2fa2fe9a | 8748 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8749 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8750 | { |
8751 | struct drm_device *dev = crtc->base.dev; | |
8752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8753 | uint32_t tmp; | |
8754 | ||
8755 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8756 | ||
8757 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8758 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8759 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8760 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8761 | |
8762 | /* We currently do not free assignements of panel fitters on | |
8763 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8764 | * differentiates them) so just WARN about this case for now. */ | |
8765 | if (IS_GEN7(dev)) { | |
8766 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8767 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8768 | } | |
2fa2fe9a | 8769 | } |
79e53945 JB |
8770 | } |
8771 | ||
5724dbd1 DL |
8772 | static void |
8773 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8774 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8775 | { |
8776 | struct drm_device *dev = crtc->base.dev; | |
8777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8778 | u32 val, base, offset; | |
aeee5a49 | 8779 | int pipe = crtc->pipe; |
4c6baa59 | 8780 | int fourcc, pixel_format; |
6761dd31 | 8781 | unsigned int aligned_height; |
b113d5ee | 8782 | struct drm_framebuffer *fb; |
1b842c89 | 8783 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8784 | |
42a7b088 DL |
8785 | val = I915_READ(DSPCNTR(pipe)); |
8786 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8787 | return; | |
8788 | ||
d9806c9f | 8789 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8790 | if (!intel_fb) { |
4c6baa59 JB |
8791 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8792 | return; | |
8793 | } | |
8794 | ||
1b842c89 DL |
8795 | fb = &intel_fb->base; |
8796 | ||
18c5247e DV |
8797 | if (INTEL_INFO(dev)->gen >= 4) { |
8798 | if (val & DISPPLANE_TILED) { | |
49af449b | 8799 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8800 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8801 | } | |
8802 | } | |
4c6baa59 JB |
8803 | |
8804 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8805 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8806 | fb->pixel_format = fourcc; |
8807 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8808 | |
aeee5a49 | 8809 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8810 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8811 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8812 | } else { |
49af449b | 8813 | if (plane_config->tiling) |
aeee5a49 | 8814 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8815 | else |
aeee5a49 | 8816 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8817 | } |
8818 | plane_config->base = base; | |
8819 | ||
8820 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8821 | fb->width = ((val >> 16) & 0xfff) + 1; |
8822 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8823 | |
8824 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8825 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8826 | |
b113d5ee | 8827 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8828 | fb->pixel_format, |
8829 | fb->modifier[0]); | |
4c6baa59 | 8830 | |
f37b5c2b | 8831 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8832 | |
2844a921 DL |
8833 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8834 | pipe_name(pipe), fb->width, fb->height, | |
8835 | fb->bits_per_pixel, base, fb->pitches[0], | |
8836 | plane_config->size); | |
b113d5ee | 8837 | |
2d14030b | 8838 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8839 | } |
8840 | ||
0e8ffe1b | 8841 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8842 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8843 | { |
8844 | struct drm_device *dev = crtc->base.dev; | |
8845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8846 | uint32_t tmp; | |
8847 | ||
f458ebbc DV |
8848 | if (!intel_display_power_is_enabled(dev_priv, |
8849 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8850 | return false; |
8851 | ||
e143a21c | 8852 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8853 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8854 | |
0e8ffe1b DV |
8855 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8856 | if (!(tmp & PIPECONF_ENABLE)) | |
8857 | return false; | |
8858 | ||
42571aef VS |
8859 | switch (tmp & PIPECONF_BPC_MASK) { |
8860 | case PIPECONF_6BPC: | |
8861 | pipe_config->pipe_bpp = 18; | |
8862 | break; | |
8863 | case PIPECONF_8BPC: | |
8864 | pipe_config->pipe_bpp = 24; | |
8865 | break; | |
8866 | case PIPECONF_10BPC: | |
8867 | pipe_config->pipe_bpp = 30; | |
8868 | break; | |
8869 | case PIPECONF_12BPC: | |
8870 | pipe_config->pipe_bpp = 36; | |
8871 | break; | |
8872 | default: | |
8873 | break; | |
8874 | } | |
8875 | ||
b5a9fa09 DV |
8876 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8877 | pipe_config->limited_color_range = true; | |
8878 | ||
ab9412ba | 8879 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8880 | struct intel_shared_dpll *pll; |
8881 | ||
88adfff1 DV |
8882 | pipe_config->has_pch_encoder = true; |
8883 | ||
627eb5a3 DV |
8884 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8885 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8886 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8887 | |
8888 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8889 | |
c0d43d62 | 8890 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8891 | pipe_config->shared_dpll = |
8892 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8893 | } else { |
8894 | tmp = I915_READ(PCH_DPLL_SEL); | |
8895 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8896 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8897 | else | |
8898 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8899 | } | |
66e985c0 DV |
8900 | |
8901 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8902 | ||
8903 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8904 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8905 | |
8906 | tmp = pipe_config->dpll_hw_state.dpll; | |
8907 | pipe_config->pixel_multiplier = | |
8908 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8909 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8910 | |
8911 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8912 | } else { |
8913 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8914 | } |
8915 | ||
1bd1bd80 DV |
8916 | intel_get_pipe_timings(crtc, pipe_config); |
8917 | ||
2fa2fe9a DV |
8918 | ironlake_get_pfit_config(crtc, pipe_config); |
8919 | ||
0e8ffe1b DV |
8920 | return true; |
8921 | } | |
8922 | ||
be256dc7 PZ |
8923 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8924 | { | |
8925 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8926 | struct intel_crtc *crtc; |
be256dc7 | 8927 | |
d3fcc808 | 8928 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8929 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8930 | pipe_name(crtc->pipe)); |
8931 | ||
e2c719b7 RC |
8932 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8933 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8934 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8935 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8936 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8937 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8938 | "CPU PWM1 enabled\n"); |
c5107b87 | 8939 | if (IS_HASWELL(dev)) |
e2c719b7 | 8940 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8941 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8942 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8943 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8944 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8945 | "Utility pin enabled\n"); |
e2c719b7 | 8946 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8947 | |
9926ada1 PZ |
8948 | /* |
8949 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8950 | * interrupts remain enabled. We used to check for that, but since it's | |
8951 | * gen-specific and since we only disable LCPLL after we fully disable | |
8952 | * the interrupts, the check below should be enough. | |
8953 | */ | |
e2c719b7 | 8954 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8955 | } |
8956 | ||
9ccd5aeb PZ |
8957 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8958 | { | |
8959 | struct drm_device *dev = dev_priv->dev; | |
8960 | ||
8961 | if (IS_HASWELL(dev)) | |
8962 | return I915_READ(D_COMP_HSW); | |
8963 | else | |
8964 | return I915_READ(D_COMP_BDW); | |
8965 | } | |
8966 | ||
3c4c9b81 PZ |
8967 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8968 | { | |
8969 | struct drm_device *dev = dev_priv->dev; | |
8970 | ||
8971 | if (IS_HASWELL(dev)) { | |
8972 | mutex_lock(&dev_priv->rps.hw_lock); | |
8973 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8974 | val)) | |
f475dadf | 8975 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8976 | mutex_unlock(&dev_priv->rps.hw_lock); |
8977 | } else { | |
9ccd5aeb PZ |
8978 | I915_WRITE(D_COMP_BDW, val); |
8979 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8980 | } |
be256dc7 PZ |
8981 | } |
8982 | ||
8983 | /* | |
8984 | * This function implements pieces of two sequences from BSpec: | |
8985 | * - Sequence for display software to disable LCPLL | |
8986 | * - Sequence for display software to allow package C8+ | |
8987 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8988 | * register. Callers should take care of disabling all the display engine | |
8989 | * functions, doing the mode unset, fixing interrupts, etc. | |
8990 | */ | |
6ff58d53 PZ |
8991 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8992 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8993 | { |
8994 | uint32_t val; | |
8995 | ||
8996 | assert_can_disable_lcpll(dev_priv); | |
8997 | ||
8998 | val = I915_READ(LCPLL_CTL); | |
8999 | ||
9000 | if (switch_to_fclk) { | |
9001 | val |= LCPLL_CD_SOURCE_FCLK; | |
9002 | I915_WRITE(LCPLL_CTL, val); | |
9003 | ||
9004 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9005 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9006 | DRM_ERROR("Switching to FCLK failed\n"); | |
9007 | ||
9008 | val = I915_READ(LCPLL_CTL); | |
9009 | } | |
9010 | ||
9011 | val |= LCPLL_PLL_DISABLE; | |
9012 | I915_WRITE(LCPLL_CTL, val); | |
9013 | POSTING_READ(LCPLL_CTL); | |
9014 | ||
9015 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9016 | DRM_ERROR("LCPLL still locked\n"); | |
9017 | ||
9ccd5aeb | 9018 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9019 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9020 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9021 | ndelay(100); |
9022 | ||
9ccd5aeb PZ |
9023 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9024 | 1)) | |
be256dc7 PZ |
9025 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9026 | ||
9027 | if (allow_power_down) { | |
9028 | val = I915_READ(LCPLL_CTL); | |
9029 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9030 | I915_WRITE(LCPLL_CTL, val); | |
9031 | POSTING_READ(LCPLL_CTL); | |
9032 | } | |
9033 | } | |
9034 | ||
9035 | /* | |
9036 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9037 | * source. | |
9038 | */ | |
6ff58d53 | 9039 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9040 | { |
9041 | uint32_t val; | |
9042 | ||
9043 | val = I915_READ(LCPLL_CTL); | |
9044 | ||
9045 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9046 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9047 | return; | |
9048 | ||
a8a8bd54 PZ |
9049 | /* |
9050 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9051 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9052 | */ |
59bad947 | 9053 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9054 | |
be256dc7 PZ |
9055 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9056 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9057 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9058 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9059 | } |
9060 | ||
9ccd5aeb | 9061 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9062 | val |= D_COMP_COMP_FORCE; |
9063 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9064 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9065 | |
9066 | val = I915_READ(LCPLL_CTL); | |
9067 | val &= ~LCPLL_PLL_DISABLE; | |
9068 | I915_WRITE(LCPLL_CTL, val); | |
9069 | ||
9070 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9071 | DRM_ERROR("LCPLL not locked yet\n"); | |
9072 | ||
9073 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9074 | val = I915_READ(LCPLL_CTL); | |
9075 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9076 | I915_WRITE(LCPLL_CTL, val); | |
9077 | ||
9078 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9079 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9080 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9081 | } | |
215733fa | 9082 | |
59bad947 | 9083 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
9084 | } |
9085 | ||
765dab67 PZ |
9086 | /* |
9087 | * Package states C8 and deeper are really deep PC states that can only be | |
9088 | * reached when all the devices on the system allow it, so even if the graphics | |
9089 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9090 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9091 | * | |
9092 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9093 | * well is disabled and most interrupts are disabled, and these are also | |
9094 | * requirements for runtime PM. When these conditions are met, we manually do | |
9095 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9096 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9097 | * hang the machine. | |
9098 | * | |
9099 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9100 | * the state of some registers, so when we come back from PC8+ we need to | |
9101 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9102 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9103 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9104 | * because of the runtime PM support). | |
9105 | * | |
9106 | * For more, read "Display Sequences for Package C8" on the hardware | |
9107 | * documentation. | |
9108 | */ | |
a14cb6fc | 9109 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9110 | { |
c67a470b PZ |
9111 | struct drm_device *dev = dev_priv->dev; |
9112 | uint32_t val; | |
9113 | ||
c67a470b PZ |
9114 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9115 | ||
c67a470b PZ |
9116 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9117 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9118 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9119 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9120 | } | |
9121 | ||
9122 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9123 | hsw_disable_lcpll(dev_priv, true, true); |
9124 | } | |
9125 | ||
a14cb6fc | 9126 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9127 | { |
9128 | struct drm_device *dev = dev_priv->dev; | |
9129 | uint32_t val; | |
9130 | ||
c67a470b PZ |
9131 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9132 | ||
9133 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9134 | lpt_init_pch_refclk(dev); |
9135 | ||
9136 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9137 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9138 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9139 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9140 | } | |
9141 | ||
9142 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9143 | } |
9144 | ||
a821fc46 | 9145 | static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) |
f8437dd1 | 9146 | { |
a821fc46 | 9147 | struct drm_device *dev = old_state->dev; |
f8437dd1 | 9148 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 9149 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
f8437dd1 VK |
9150 | int req_cdclk; |
9151 | ||
9152 | /* see the comment in valleyview_modeset_global_resources */ | |
9153 | if (WARN_ON(max_pixclk < 0)) | |
9154 | return; | |
9155 | ||
9156 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9157 | ||
9158 | if (req_cdclk != dev_priv->cdclk_freq) | |
9159 | broxton_set_cdclk(dev, req_cdclk); | |
9160 | } | |
9161 | ||
190f68c5 ACO |
9162 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9163 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9164 | { |
190f68c5 | 9165 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9166 | return -EINVAL; |
716c2e55 | 9167 | |
c7653199 | 9168 | crtc->lowfreq_avail = false; |
644cef34 | 9169 | |
c8f7a0db | 9170 | return 0; |
79e53945 JB |
9171 | } |
9172 | ||
3760b59c S |
9173 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9174 | enum port port, | |
9175 | struct intel_crtc_state *pipe_config) | |
9176 | { | |
9177 | switch (port) { | |
9178 | case PORT_A: | |
9179 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9180 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9181 | break; | |
9182 | case PORT_B: | |
9183 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9184 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9185 | break; | |
9186 | case PORT_C: | |
9187 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9188 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9189 | break; | |
9190 | default: | |
9191 | DRM_ERROR("Incorrect port type\n"); | |
9192 | } | |
9193 | } | |
9194 | ||
96b7dfb7 S |
9195 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9196 | enum port port, | |
5cec258b | 9197 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9198 | { |
3148ade7 | 9199 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9200 | |
9201 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9202 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9203 | ||
9204 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9205 | case SKL_DPLL0: |
9206 | /* | |
9207 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9208 | * of the shared DPLL framework and thus needs to be read out | |
9209 | * separately | |
9210 | */ | |
9211 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9212 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9213 | break; | |
96b7dfb7 S |
9214 | case SKL_DPLL1: |
9215 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9216 | break; | |
9217 | case SKL_DPLL2: | |
9218 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9219 | break; | |
9220 | case SKL_DPLL3: | |
9221 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9222 | break; | |
96b7dfb7 S |
9223 | } |
9224 | } | |
9225 | ||
7d2c8175 DL |
9226 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9227 | enum port port, | |
5cec258b | 9228 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9229 | { |
9230 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9231 | ||
9232 | switch (pipe_config->ddi_pll_sel) { | |
9233 | case PORT_CLK_SEL_WRPLL1: | |
9234 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9235 | break; | |
9236 | case PORT_CLK_SEL_WRPLL2: | |
9237 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9238 | break; | |
9239 | } | |
9240 | } | |
9241 | ||
26804afd | 9242 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9243 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9244 | { |
9245 | struct drm_device *dev = crtc->base.dev; | |
9246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9247 | struct intel_shared_dpll *pll; |
26804afd DV |
9248 | enum port port; |
9249 | uint32_t tmp; | |
9250 | ||
9251 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9252 | ||
9253 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9254 | ||
96b7dfb7 S |
9255 | if (IS_SKYLAKE(dev)) |
9256 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9257 | else if (IS_BROXTON(dev)) |
9258 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9259 | else |
9260 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9261 | |
d452c5b6 DV |
9262 | if (pipe_config->shared_dpll >= 0) { |
9263 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9264 | ||
9265 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9266 | &pipe_config->dpll_hw_state)); | |
9267 | } | |
9268 | ||
26804afd DV |
9269 | /* |
9270 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9271 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9272 | * the PCH transcoder is on. | |
9273 | */ | |
ca370455 DL |
9274 | if (INTEL_INFO(dev)->gen < 9 && |
9275 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9276 | pipe_config->has_pch_encoder = true; |
9277 | ||
9278 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9279 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9280 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9281 | ||
9282 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9283 | } | |
9284 | } | |
9285 | ||
0e8ffe1b | 9286 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9287 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9288 | { |
9289 | struct drm_device *dev = crtc->base.dev; | |
9290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9291 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9292 | uint32_t tmp; |
9293 | ||
f458ebbc | 9294 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9295 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9296 | return false; | |
9297 | ||
e143a21c | 9298 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9299 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9300 | ||
eccb140b DV |
9301 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9302 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9303 | enum pipe trans_edp_pipe; | |
9304 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9305 | default: | |
9306 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9307 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9308 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9309 | trans_edp_pipe = PIPE_A; | |
9310 | break; | |
9311 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9312 | trans_edp_pipe = PIPE_B; | |
9313 | break; | |
9314 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9315 | trans_edp_pipe = PIPE_C; | |
9316 | break; | |
9317 | } | |
9318 | ||
9319 | if (trans_edp_pipe == crtc->pipe) | |
9320 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9321 | } | |
9322 | ||
f458ebbc | 9323 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9324 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9325 | return false; |
9326 | ||
eccb140b | 9327 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9328 | if (!(tmp & PIPECONF_ENABLE)) |
9329 | return false; | |
9330 | ||
26804afd | 9331 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9332 | |
1bd1bd80 DV |
9333 | intel_get_pipe_timings(crtc, pipe_config); |
9334 | ||
a1b2278e CK |
9335 | if (INTEL_INFO(dev)->gen >= 9) { |
9336 | skl_init_scalers(dev, crtc, pipe_config); | |
9337 | } | |
9338 | ||
2fa2fe9a | 9339 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9340 | |
9341 | if (INTEL_INFO(dev)->gen >= 9) { | |
9342 | pipe_config->scaler_state.scaler_id = -1; | |
9343 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9344 | } | |
9345 | ||
bd2e244f | 9346 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9347 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9348 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9349 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9350 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9351 | else |
9352 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
bd2e244f | 9353 | } |
88adfff1 | 9354 | |
e59150dc JB |
9355 | if (IS_HASWELL(dev)) |
9356 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9357 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9358 | |
ebb69c95 CT |
9359 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9360 | pipe_config->pixel_multiplier = | |
9361 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9362 | } else { | |
9363 | pipe_config->pixel_multiplier = 1; | |
9364 | } | |
6c49f241 | 9365 | |
0e8ffe1b DV |
9366 | return true; |
9367 | } | |
9368 | ||
560b85bb CW |
9369 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9370 | { | |
9371 | struct drm_device *dev = crtc->dev; | |
9372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9374 | uint32_t cntl = 0, size = 0; |
560b85bb | 9375 | |
dc41c154 | 9376 | if (base) { |
3dd512fb MR |
9377 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9378 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9379 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9380 | ||
9381 | switch (stride) { | |
9382 | default: | |
9383 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9384 | width, stride); | |
9385 | stride = 256; | |
9386 | /* fallthrough */ | |
9387 | case 256: | |
9388 | case 512: | |
9389 | case 1024: | |
9390 | case 2048: | |
9391 | break; | |
4b0e333e CW |
9392 | } |
9393 | ||
dc41c154 VS |
9394 | cntl |= CURSOR_ENABLE | |
9395 | CURSOR_GAMMA_ENABLE | | |
9396 | CURSOR_FORMAT_ARGB | | |
9397 | CURSOR_STRIDE(stride); | |
9398 | ||
9399 | size = (height << 12) | width; | |
4b0e333e | 9400 | } |
560b85bb | 9401 | |
dc41c154 VS |
9402 | if (intel_crtc->cursor_cntl != 0 && |
9403 | (intel_crtc->cursor_base != base || | |
9404 | intel_crtc->cursor_size != size || | |
9405 | intel_crtc->cursor_cntl != cntl)) { | |
9406 | /* On these chipsets we can only modify the base/size/stride | |
9407 | * whilst the cursor is disabled. | |
9408 | */ | |
9409 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9410 | POSTING_READ(_CURACNTR); |
dc41c154 | 9411 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9412 | } |
560b85bb | 9413 | |
99d1f387 | 9414 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9415 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9416 | intel_crtc->cursor_base = base; |
9417 | } | |
4726e0b0 | 9418 | |
dc41c154 VS |
9419 | if (intel_crtc->cursor_size != size) { |
9420 | I915_WRITE(CURSIZE, size); | |
9421 | intel_crtc->cursor_size = size; | |
4b0e333e | 9422 | } |
560b85bb | 9423 | |
4b0e333e | 9424 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9425 | I915_WRITE(_CURACNTR, cntl); |
9426 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9427 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9428 | } |
560b85bb CW |
9429 | } |
9430 | ||
560b85bb | 9431 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9432 | { |
9433 | struct drm_device *dev = crtc->dev; | |
9434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9435 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9436 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9437 | uint32_t cntl; |
9438 | ||
9439 | cntl = 0; | |
9440 | if (base) { | |
9441 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9442 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9443 | case 64: |
9444 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9445 | break; | |
9446 | case 128: | |
9447 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9448 | break; | |
9449 | case 256: | |
9450 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9451 | break; | |
9452 | default: | |
3dd512fb | 9453 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9454 | return; |
65a21cd6 | 9455 | } |
4b0e333e | 9456 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9457 | |
9458 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9459 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9460 | } |
65a21cd6 | 9461 | |
8e7d688b | 9462 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9463 | cntl |= CURSOR_ROTATE_180; |
9464 | ||
4b0e333e CW |
9465 | if (intel_crtc->cursor_cntl != cntl) { |
9466 | I915_WRITE(CURCNTR(pipe), cntl); | |
9467 | POSTING_READ(CURCNTR(pipe)); | |
9468 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9469 | } |
4b0e333e | 9470 | |
65a21cd6 | 9471 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9472 | I915_WRITE(CURBASE(pipe), base); |
9473 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9474 | |
9475 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9476 | } |
9477 | ||
cda4b7d3 | 9478 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9479 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9480 | bool on) | |
cda4b7d3 CW |
9481 | { |
9482 | struct drm_device *dev = crtc->dev; | |
9483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9484 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9485 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9486 | int x = crtc->cursor_x; |
9487 | int y = crtc->cursor_y; | |
d6e4db15 | 9488 | u32 base = 0, pos = 0; |
cda4b7d3 | 9489 | |
d6e4db15 | 9490 | if (on) |
cda4b7d3 | 9491 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9492 | |
6e3c9717 | 9493 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9494 | base = 0; |
9495 | ||
6e3c9717 | 9496 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9497 | base = 0; |
9498 | ||
9499 | if (x < 0) { | |
3dd512fb | 9500 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9501 | base = 0; |
9502 | ||
9503 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9504 | x = -x; | |
9505 | } | |
9506 | pos |= x << CURSOR_X_SHIFT; | |
9507 | ||
9508 | if (y < 0) { | |
3dd512fb | 9509 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9510 | base = 0; |
9511 | ||
9512 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9513 | y = -y; | |
9514 | } | |
9515 | pos |= y << CURSOR_Y_SHIFT; | |
9516 | ||
4b0e333e | 9517 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9518 | return; |
9519 | ||
5efb3e28 VS |
9520 | I915_WRITE(CURPOS(pipe), pos); |
9521 | ||
4398ad45 VS |
9522 | /* ILK+ do this automagically */ |
9523 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9524 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9525 | base += (intel_crtc->base.cursor->state->crtc_h * |
9526 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9527 | } |
9528 | ||
8ac54669 | 9529 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9530 | i845_update_cursor(crtc, base); |
9531 | else | |
9532 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9533 | } |
9534 | ||
dc41c154 VS |
9535 | static bool cursor_size_ok(struct drm_device *dev, |
9536 | uint32_t width, uint32_t height) | |
9537 | { | |
9538 | if (width == 0 || height == 0) | |
9539 | return false; | |
9540 | ||
9541 | /* | |
9542 | * 845g/865g are special in that they are only limited by | |
9543 | * the width of their cursors, the height is arbitrary up to | |
9544 | * the precision of the register. Everything else requires | |
9545 | * square cursors, limited to a few power-of-two sizes. | |
9546 | */ | |
9547 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9548 | if ((width & 63) != 0) | |
9549 | return false; | |
9550 | ||
9551 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9552 | return false; | |
9553 | ||
9554 | if (height > 1023) | |
9555 | return false; | |
9556 | } else { | |
9557 | switch (width | height) { | |
9558 | case 256: | |
9559 | case 128: | |
9560 | if (IS_GEN2(dev)) | |
9561 | return false; | |
9562 | case 64: | |
9563 | break; | |
9564 | default: | |
9565 | return false; | |
9566 | } | |
9567 | } | |
9568 | ||
9569 | return true; | |
9570 | } | |
9571 | ||
79e53945 | 9572 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9573 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9574 | { |
7203425a | 9575 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9577 | |
7203425a | 9578 | for (i = start; i < end; i++) { |
79e53945 JB |
9579 | intel_crtc->lut_r[i] = red[i] >> 8; |
9580 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9581 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9582 | } | |
9583 | ||
9584 | intel_crtc_load_lut(crtc); | |
9585 | } | |
9586 | ||
79e53945 JB |
9587 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9588 | static struct drm_display_mode load_detect_mode = { | |
9589 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9590 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9591 | }; | |
9592 | ||
a8bb6818 DV |
9593 | struct drm_framebuffer * |
9594 | __intel_framebuffer_create(struct drm_device *dev, | |
9595 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9596 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9597 | { |
9598 | struct intel_framebuffer *intel_fb; | |
9599 | int ret; | |
9600 | ||
9601 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9602 | if (!intel_fb) { | |
6ccb81f2 | 9603 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9604 | return ERR_PTR(-ENOMEM); |
9605 | } | |
9606 | ||
9607 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9608 | if (ret) |
9609 | goto err; | |
d2dff872 CW |
9610 | |
9611 | return &intel_fb->base; | |
dd4916c5 | 9612 | err: |
6ccb81f2 | 9613 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9614 | kfree(intel_fb); |
9615 | ||
9616 | return ERR_PTR(ret); | |
d2dff872 CW |
9617 | } |
9618 | ||
b5ea642a | 9619 | static struct drm_framebuffer * |
a8bb6818 DV |
9620 | intel_framebuffer_create(struct drm_device *dev, |
9621 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9622 | struct drm_i915_gem_object *obj) | |
9623 | { | |
9624 | struct drm_framebuffer *fb; | |
9625 | int ret; | |
9626 | ||
9627 | ret = i915_mutex_lock_interruptible(dev); | |
9628 | if (ret) | |
9629 | return ERR_PTR(ret); | |
9630 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9631 | mutex_unlock(&dev->struct_mutex); | |
9632 | ||
9633 | return fb; | |
9634 | } | |
9635 | ||
d2dff872 CW |
9636 | static u32 |
9637 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9638 | { | |
9639 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9640 | return ALIGN(pitch, 64); | |
9641 | } | |
9642 | ||
9643 | static u32 | |
9644 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9645 | { | |
9646 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9647 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9648 | } |
9649 | ||
9650 | static struct drm_framebuffer * | |
9651 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9652 | struct drm_display_mode *mode, | |
9653 | int depth, int bpp) | |
9654 | { | |
9655 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9656 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9657 | |
9658 | obj = i915_gem_alloc_object(dev, | |
9659 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9660 | if (obj == NULL) | |
9661 | return ERR_PTR(-ENOMEM); | |
9662 | ||
9663 | mode_cmd.width = mode->hdisplay; | |
9664 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9665 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9666 | bpp); | |
5ca0c34a | 9667 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9668 | |
9669 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9670 | } | |
9671 | ||
9672 | static struct drm_framebuffer * | |
9673 | mode_fits_in_fbdev(struct drm_device *dev, | |
9674 | struct drm_display_mode *mode) | |
9675 | { | |
4520f53a | 9676 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9677 | struct drm_i915_private *dev_priv = dev->dev_private; |
9678 | struct drm_i915_gem_object *obj; | |
9679 | struct drm_framebuffer *fb; | |
9680 | ||
4c0e5528 | 9681 | if (!dev_priv->fbdev) |
d2dff872 CW |
9682 | return NULL; |
9683 | ||
4c0e5528 | 9684 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9685 | return NULL; |
9686 | ||
4c0e5528 DV |
9687 | obj = dev_priv->fbdev->fb->obj; |
9688 | BUG_ON(!obj); | |
9689 | ||
8bcd4553 | 9690 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9691 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9692 | fb->bits_per_pixel)) | |
d2dff872 CW |
9693 | return NULL; |
9694 | ||
01f2c773 | 9695 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9696 | return NULL; |
9697 | ||
9698 | return fb; | |
4520f53a DV |
9699 | #else |
9700 | return NULL; | |
9701 | #endif | |
d2dff872 CW |
9702 | } |
9703 | ||
d3a40d1b ACO |
9704 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9705 | struct drm_crtc *crtc, | |
9706 | struct drm_display_mode *mode, | |
9707 | struct drm_framebuffer *fb, | |
9708 | int x, int y) | |
9709 | { | |
9710 | struct drm_plane_state *plane_state; | |
9711 | int hdisplay, vdisplay; | |
9712 | int ret; | |
9713 | ||
9714 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9715 | if (IS_ERR(plane_state)) | |
9716 | return PTR_ERR(plane_state); | |
9717 | ||
9718 | if (mode) | |
9719 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
9720 | else | |
9721 | hdisplay = vdisplay = 0; | |
9722 | ||
9723 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9724 | if (ret) | |
9725 | return ret; | |
9726 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9727 | plane_state->crtc_x = 0; | |
9728 | plane_state->crtc_y = 0; | |
9729 | plane_state->crtc_w = hdisplay; | |
9730 | plane_state->crtc_h = vdisplay; | |
9731 | plane_state->src_x = x << 16; | |
9732 | plane_state->src_y = y << 16; | |
9733 | plane_state->src_w = hdisplay << 16; | |
9734 | plane_state->src_h = vdisplay << 16; | |
9735 | ||
9736 | return 0; | |
9737 | } | |
9738 | ||
d2434ab7 | 9739 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9740 | struct drm_display_mode *mode, |
51fd371b RC |
9741 | struct intel_load_detect_pipe *old, |
9742 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9743 | { |
9744 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9745 | struct intel_encoder *intel_encoder = |
9746 | intel_attached_encoder(connector); | |
79e53945 | 9747 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9748 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9749 | struct drm_crtc *crtc = NULL; |
9750 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9751 | struct drm_framebuffer *fb; |
51fd371b | 9752 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9753 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9754 | struct drm_connector_state *connector_state; |
4be07317 | 9755 | struct intel_crtc_state *crtc_state; |
51fd371b | 9756 | int ret, i = -1; |
79e53945 | 9757 | |
d2dff872 | 9758 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9759 | connector->base.id, connector->name, |
8e329a03 | 9760 | encoder->base.id, encoder->name); |
d2dff872 | 9761 | |
51fd371b RC |
9762 | retry: |
9763 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9764 | if (ret) | |
9765 | goto fail_unlock; | |
6e9f798d | 9766 | |
79e53945 JB |
9767 | /* |
9768 | * Algorithm gets a little messy: | |
7a5e4805 | 9769 | * |
79e53945 JB |
9770 | * - if the connector already has an assigned crtc, use it (but make |
9771 | * sure it's on first) | |
7a5e4805 | 9772 | * |
79e53945 JB |
9773 | * - try to find the first unused crtc that can drive this connector, |
9774 | * and use that if we find one | |
79e53945 JB |
9775 | */ |
9776 | ||
9777 | /* See if we already have a CRTC for this connector */ | |
9778 | if (encoder->crtc) { | |
9779 | crtc = encoder->crtc; | |
8261b191 | 9780 | |
51fd371b | 9781 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9782 | if (ret) |
9783 | goto fail_unlock; | |
9784 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9785 | if (ret) |
9786 | goto fail_unlock; | |
7b24056b | 9787 | |
24218aac | 9788 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9789 | old->load_detect_temp = false; |
9790 | ||
9791 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9792 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9793 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9794 | |
7173188d | 9795 | return true; |
79e53945 JB |
9796 | } |
9797 | ||
9798 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9799 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9800 | i++; |
9801 | if (!(encoder->possible_crtcs & (1 << i))) | |
9802 | continue; | |
83d65738 | 9803 | if (possible_crtc->state->enable) |
a459249c VS |
9804 | continue; |
9805 | /* This can occur when applying the pipe A quirk on resume. */ | |
9806 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9807 | continue; | |
9808 | ||
9809 | crtc = possible_crtc; | |
9810 | break; | |
79e53945 JB |
9811 | } |
9812 | ||
9813 | /* | |
9814 | * If we didn't find an unused CRTC, don't use any. | |
9815 | */ | |
9816 | if (!crtc) { | |
7173188d | 9817 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9818 | goto fail_unlock; |
79e53945 JB |
9819 | } |
9820 | ||
51fd371b RC |
9821 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9822 | if (ret) | |
4d02e2de DV |
9823 | goto fail_unlock; |
9824 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9825 | if (ret) | |
51fd371b | 9826 | goto fail_unlock; |
fc303101 DV |
9827 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9828 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9829 | |
9830 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9831 | intel_crtc->new_enabled = true; |
24218aac | 9832 | old->dpms_mode = connector->dpms; |
8261b191 | 9833 | old->load_detect_temp = true; |
d2dff872 | 9834 | old->release_fb = NULL; |
79e53945 | 9835 | |
83a57153 ACO |
9836 | state = drm_atomic_state_alloc(dev); |
9837 | if (!state) | |
9838 | return false; | |
9839 | ||
9840 | state->acquire_ctx = ctx; | |
9841 | ||
944b0c76 ACO |
9842 | connector_state = drm_atomic_get_connector_state(state, connector); |
9843 | if (IS_ERR(connector_state)) { | |
9844 | ret = PTR_ERR(connector_state); | |
9845 | goto fail; | |
9846 | } | |
9847 | ||
9848 | connector_state->crtc = crtc; | |
9849 | connector_state->best_encoder = &intel_encoder->base; | |
9850 | ||
4be07317 ACO |
9851 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9852 | if (IS_ERR(crtc_state)) { | |
9853 | ret = PTR_ERR(crtc_state); | |
9854 | goto fail; | |
9855 | } | |
9856 | ||
49d6fa21 | 9857 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9858 | |
6492711d CW |
9859 | if (!mode) |
9860 | mode = &load_detect_mode; | |
79e53945 | 9861 | |
d2dff872 CW |
9862 | /* We need a framebuffer large enough to accommodate all accesses |
9863 | * that the plane may generate whilst we perform load detection. | |
9864 | * We can not rely on the fbcon either being present (we get called | |
9865 | * during its initialisation to detect all boot displays, or it may | |
9866 | * not even exist) or that it is large enough to satisfy the | |
9867 | * requested mode. | |
9868 | */ | |
94352cf9 DV |
9869 | fb = mode_fits_in_fbdev(dev, mode); |
9870 | if (fb == NULL) { | |
d2dff872 | 9871 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9872 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9873 | old->release_fb = fb; | |
d2dff872 CW |
9874 | } else |
9875 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9876 | if (IS_ERR(fb)) { |
d2dff872 | 9877 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9878 | goto fail; |
79e53945 | 9879 | } |
79e53945 | 9880 | |
d3a40d1b ACO |
9881 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9882 | if (ret) | |
9883 | goto fail; | |
9884 | ||
8c7b5ccb ACO |
9885 | drm_mode_copy(&crtc_state->base.mode, mode); |
9886 | ||
9887 | if (intel_set_mode(crtc, state)) { | |
6492711d | 9888 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9889 | if (old->release_fb) |
9890 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9891 | goto fail; |
79e53945 | 9892 | } |
9128b040 | 9893 | crtc->primary->crtc = crtc; |
7173188d | 9894 | |
79e53945 | 9895 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9896 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9897 | return true; |
412b61d8 VS |
9898 | |
9899 | fail: | |
83d65738 | 9900 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9901 | fail_unlock: |
e5d958ef ACO |
9902 | drm_atomic_state_free(state); |
9903 | state = NULL; | |
83a57153 | 9904 | |
51fd371b RC |
9905 | if (ret == -EDEADLK) { |
9906 | drm_modeset_backoff(ctx); | |
9907 | goto retry; | |
9908 | } | |
9909 | ||
412b61d8 | 9910 | return false; |
79e53945 JB |
9911 | } |
9912 | ||
d2434ab7 | 9913 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9914 | struct intel_load_detect_pipe *old, |
9915 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9916 | { |
83a57153 | 9917 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9918 | struct intel_encoder *intel_encoder = |
9919 | intel_attached_encoder(connector); | |
4ef69c7a | 9920 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9921 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9923 | struct drm_atomic_state *state; |
944b0c76 | 9924 | struct drm_connector_state *connector_state; |
4be07317 | 9925 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 9926 | int ret; |
79e53945 | 9927 | |
d2dff872 | 9928 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9929 | connector->base.id, connector->name, |
8e329a03 | 9930 | encoder->base.id, encoder->name); |
d2dff872 | 9931 | |
8261b191 | 9932 | if (old->load_detect_temp) { |
83a57153 | 9933 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9934 | if (!state) |
9935 | goto fail; | |
83a57153 ACO |
9936 | |
9937 | state->acquire_ctx = ctx; | |
9938 | ||
944b0c76 ACO |
9939 | connector_state = drm_atomic_get_connector_state(state, connector); |
9940 | if (IS_ERR(connector_state)) | |
9941 | goto fail; | |
9942 | ||
4be07317 ACO |
9943 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9944 | if (IS_ERR(crtc_state)) | |
9945 | goto fail; | |
9946 | ||
fc303101 DV |
9947 | to_intel_connector(connector)->new_encoder = NULL; |
9948 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9949 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9950 | |
9951 | connector_state->best_encoder = NULL; | |
9952 | connector_state->crtc = NULL; | |
9953 | ||
49d6fa21 | 9954 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 9955 | |
d3a40d1b ACO |
9956 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
9957 | 0, 0); | |
9958 | if (ret) | |
9959 | goto fail; | |
9960 | ||
2bfb4627 ACO |
9961 | ret = intel_set_mode(crtc, state); |
9962 | if (ret) | |
9963 | goto fail; | |
d2dff872 | 9964 | |
36206361 DV |
9965 | if (old->release_fb) { |
9966 | drm_framebuffer_unregister_private(old->release_fb); | |
9967 | drm_framebuffer_unreference(old->release_fb); | |
9968 | } | |
d2dff872 | 9969 | |
0622a53c | 9970 | return; |
79e53945 JB |
9971 | } |
9972 | ||
c751ce4f | 9973 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9974 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9975 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9976 | |
9977 | return; | |
9978 | fail: | |
9979 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9980 | drm_atomic_state_free(state); | |
79e53945 JB |
9981 | } |
9982 | ||
da4a1efa | 9983 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9984 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9985 | { |
9986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9987 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9988 | ||
9989 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9990 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9991 | else if (HAS_PCH_SPLIT(dev)) |
9992 | return 120000; | |
9993 | else if (!IS_GEN2(dev)) | |
9994 | return 96000; | |
9995 | else | |
9996 | return 48000; | |
9997 | } | |
9998 | ||
79e53945 | 9999 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10000 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10001 | struct intel_crtc_state *pipe_config) |
79e53945 | 10002 | { |
f1f644dc | 10003 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10004 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10005 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10006 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10007 | u32 fp; |
10008 | intel_clock_t clock; | |
da4a1efa | 10009 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10010 | |
10011 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10012 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10013 | else |
293623f7 | 10014 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10015 | |
10016 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10017 | if (IS_PINEVIEW(dev)) { |
10018 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10019 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10020 | } else { |
10021 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10022 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10023 | } | |
10024 | ||
a6c45cf0 | 10025 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10026 | if (IS_PINEVIEW(dev)) |
10027 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10028 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10029 | else |
10030 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10031 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10032 | ||
10033 | switch (dpll & DPLL_MODE_MASK) { | |
10034 | case DPLLB_MODE_DAC_SERIAL: | |
10035 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10036 | 5 : 10; | |
10037 | break; | |
10038 | case DPLLB_MODE_LVDS: | |
10039 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10040 | 7 : 14; | |
10041 | break; | |
10042 | default: | |
28c97730 | 10043 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10044 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10045 | return; |
79e53945 JB |
10046 | } |
10047 | ||
ac58c3f0 | 10048 | if (IS_PINEVIEW(dev)) |
da4a1efa | 10049 | pineview_clock(refclk, &clock); |
ac58c3f0 | 10050 | else |
da4a1efa | 10051 | i9xx_clock(refclk, &clock); |
79e53945 | 10052 | } else { |
0fb58223 | 10053 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10054 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10055 | |
10056 | if (is_lvds) { | |
10057 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10058 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10059 | |
10060 | if (lvds & LVDS_CLKB_POWER_UP) | |
10061 | clock.p2 = 7; | |
10062 | else | |
10063 | clock.p2 = 14; | |
79e53945 JB |
10064 | } else { |
10065 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10066 | clock.p1 = 2; | |
10067 | else { | |
10068 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10069 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10070 | } | |
10071 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10072 | clock.p2 = 4; | |
10073 | else | |
10074 | clock.p2 = 2; | |
79e53945 | 10075 | } |
da4a1efa VS |
10076 | |
10077 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
10078 | } |
10079 | ||
18442d08 VS |
10080 | /* |
10081 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10082 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10083 | * encoder's get_config() function. |
10084 | */ | |
10085 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
10086 | } |
10087 | ||
6878da05 VS |
10088 | int intel_dotclock_calculate(int link_freq, |
10089 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10090 | { |
f1f644dc JB |
10091 | /* |
10092 | * The calculation for the data clock is: | |
1041a02f | 10093 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10094 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10095 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10096 | * |
10097 | * and the link clock is simpler: | |
1041a02f | 10098 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10099 | */ |
10100 | ||
6878da05 VS |
10101 | if (!m_n->link_n) |
10102 | return 0; | |
f1f644dc | 10103 | |
6878da05 VS |
10104 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10105 | } | |
f1f644dc | 10106 | |
18442d08 | 10107 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10108 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10109 | { |
10110 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10111 | |
18442d08 VS |
10112 | /* read out port_clock from the DPLL */ |
10113 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10114 | |
f1f644dc | 10115 | /* |
18442d08 | 10116 | * This value does not include pixel_multiplier. |
241bfc38 | 10117 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10118 | * agree once we know their relationship in the encoder's |
10119 | * get_config() function. | |
79e53945 | 10120 | */ |
2d112de7 | 10121 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10122 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10123 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10124 | } |
10125 | ||
10126 | /** Returns the currently programmed mode of the given pipe. */ | |
10127 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10128 | struct drm_crtc *crtc) | |
10129 | { | |
548f245b | 10130 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10132 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10133 | struct drm_display_mode *mode; |
5cec258b | 10134 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10135 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10136 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10137 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10138 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10139 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10140 | |
10141 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10142 | if (!mode) | |
10143 | return NULL; | |
10144 | ||
f1f644dc JB |
10145 | /* |
10146 | * Construct a pipe_config sufficient for getting the clock info | |
10147 | * back out of crtc_clock_get. | |
10148 | * | |
10149 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10150 | * to use a real value here instead. | |
10151 | */ | |
293623f7 | 10152 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10153 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10154 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10155 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10156 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10157 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10158 | ||
773ae034 | 10159 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10160 | mode->hdisplay = (htot & 0xffff) + 1; |
10161 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10162 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10163 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10164 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10165 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10166 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10167 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10168 | ||
10169 | drm_mode_set_name(mode); | |
79e53945 JB |
10170 | |
10171 | return mode; | |
10172 | } | |
10173 | ||
652c393a JB |
10174 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10175 | { | |
10176 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10177 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10179 | |
baff296c | 10180 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10181 | return; |
10182 | ||
10183 | if (!dev_priv->lvds_downclock_avail) | |
10184 | return; | |
10185 | ||
10186 | /* | |
10187 | * Since this is called by a timer, we should never get here in | |
10188 | * the manual case. | |
10189 | */ | |
10190 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10191 | int pipe = intel_crtc->pipe; |
10192 | int dpll_reg = DPLL(pipe); | |
10193 | int dpll; | |
f6e5b160 | 10194 | |
44d98a61 | 10195 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10196 | |
8ac5a6d5 | 10197 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10198 | |
dc257cf1 | 10199 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10200 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10201 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10202 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10203 | dpll = I915_READ(dpll_reg); |
10204 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10205 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10206 | } |
10207 | ||
10208 | } | |
10209 | ||
f047e395 CW |
10210 | void intel_mark_busy(struct drm_device *dev) |
10211 | { | |
c67a470b PZ |
10212 | struct drm_i915_private *dev_priv = dev->dev_private; |
10213 | ||
f62a0076 CW |
10214 | if (dev_priv->mm.busy) |
10215 | return; | |
10216 | ||
43694d69 | 10217 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10218 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10219 | if (INTEL_INFO(dev)->gen >= 6) |
10220 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10221 | dev_priv->mm.busy = true; |
f047e395 CW |
10222 | } |
10223 | ||
10224 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10225 | { |
c67a470b | 10226 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10227 | struct drm_crtc *crtc; |
652c393a | 10228 | |
f62a0076 CW |
10229 | if (!dev_priv->mm.busy) |
10230 | return; | |
10231 | ||
10232 | dev_priv->mm.busy = false; | |
10233 | ||
70e1e0ec | 10234 | for_each_crtc(dev, crtc) { |
f4510a27 | 10235 | if (!crtc->primary->fb) |
652c393a JB |
10236 | continue; |
10237 | ||
725a5b54 | 10238 | intel_decrease_pllclock(crtc); |
652c393a | 10239 | } |
b29c19b6 | 10240 | |
3d13ef2e | 10241 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10242 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10243 | |
43694d69 | 10244 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10245 | } |
10246 | ||
79e53945 JB |
10247 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10248 | { | |
10249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10250 | struct drm_device *dev = crtc->dev; |
10251 | struct intel_unpin_work *work; | |
67e77c5a | 10252 | |
5e2d7afc | 10253 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10254 | work = intel_crtc->unpin_work; |
10255 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10256 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10257 | |
10258 | if (work) { | |
10259 | cancel_work_sync(&work->work); | |
10260 | kfree(work); | |
10261 | } | |
79e53945 JB |
10262 | |
10263 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10264 | |
79e53945 JB |
10265 | kfree(intel_crtc); |
10266 | } | |
10267 | ||
6b95a207 KH |
10268 | static void intel_unpin_work_fn(struct work_struct *__work) |
10269 | { | |
10270 | struct intel_unpin_work *work = | |
10271 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10272 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10273 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10274 | |
b4a98e57 | 10275 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10276 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10277 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10278 | |
7ff0ebcc | 10279 | intel_fbc_update(dev); |
f06cc1b9 JH |
10280 | |
10281 | if (work->flip_queued_req) | |
146d84f0 | 10282 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10283 | mutex_unlock(&dev->struct_mutex); |
10284 | ||
f99d7069 | 10285 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10286 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10287 | |
b4a98e57 CW |
10288 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10289 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10290 | ||
6b95a207 KH |
10291 | kfree(work); |
10292 | } | |
10293 | ||
1afe3e9d | 10294 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10295 | struct drm_crtc *crtc) |
6b95a207 | 10296 | { |
6b95a207 KH |
10297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10298 | struct intel_unpin_work *work; | |
6b95a207 KH |
10299 | unsigned long flags; |
10300 | ||
10301 | /* Ignore early vblank irqs */ | |
10302 | if (intel_crtc == NULL) | |
10303 | return; | |
10304 | ||
f326038a DV |
10305 | /* |
10306 | * This is called both by irq handlers and the reset code (to complete | |
10307 | * lost pageflips) so needs the full irqsave spinlocks. | |
10308 | */ | |
6b95a207 KH |
10309 | spin_lock_irqsave(&dev->event_lock, flags); |
10310 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10311 | |
10312 | /* Ensure we don't miss a work->pending update ... */ | |
10313 | smp_rmb(); | |
10314 | ||
10315 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10316 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10317 | return; | |
10318 | } | |
10319 | ||
d6bbafa1 | 10320 | page_flip_completed(intel_crtc); |
0af7e4df | 10321 | |
6b95a207 | 10322 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10323 | } |
10324 | ||
1afe3e9d JB |
10325 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10326 | { | |
fbee40df | 10327 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10328 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10329 | ||
49b14a5c | 10330 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10331 | } |
10332 | ||
10333 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10334 | { | |
fbee40df | 10335 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10336 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10337 | ||
49b14a5c | 10338 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10339 | } |
10340 | ||
75f7f3ec VS |
10341 | /* Is 'a' after or equal to 'b'? */ |
10342 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10343 | { | |
10344 | return !((a - b) & 0x80000000); | |
10345 | } | |
10346 | ||
10347 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10348 | { | |
10349 | struct drm_device *dev = crtc->base.dev; | |
10350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10351 | ||
bdfa7542 VS |
10352 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10353 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10354 | return true; | |
10355 | ||
75f7f3ec VS |
10356 | /* |
10357 | * The relevant registers doen't exist on pre-ctg. | |
10358 | * As the flip done interrupt doesn't trigger for mmio | |
10359 | * flips on gmch platforms, a flip count check isn't | |
10360 | * really needed there. But since ctg has the registers, | |
10361 | * include it in the check anyway. | |
10362 | */ | |
10363 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10364 | return true; | |
10365 | ||
10366 | /* | |
10367 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10368 | * used the same base address. In that case the mmio flip might | |
10369 | * have completed, but the CS hasn't even executed the flip yet. | |
10370 | * | |
10371 | * A flip count check isn't enough as the CS might have updated | |
10372 | * the base address just after start of vblank, but before we | |
10373 | * managed to process the interrupt. This means we'd complete the | |
10374 | * CS flip too soon. | |
10375 | * | |
10376 | * Combining both checks should get us a good enough result. It may | |
10377 | * still happen that the CS flip has been executed, but has not | |
10378 | * yet actually completed. But in case the base address is the same | |
10379 | * anyway, we don't really care. | |
10380 | */ | |
10381 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10382 | crtc->unpin_work->gtt_offset && | |
10383 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10384 | crtc->unpin_work->flip_count); | |
10385 | } | |
10386 | ||
6b95a207 KH |
10387 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10388 | { | |
fbee40df | 10389 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10390 | struct intel_crtc *intel_crtc = |
10391 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10392 | unsigned long flags; | |
10393 | ||
f326038a DV |
10394 | |
10395 | /* | |
10396 | * This is called both by irq handlers and the reset code (to complete | |
10397 | * lost pageflips) so needs the full irqsave spinlocks. | |
10398 | * | |
10399 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10400 | * generate a page-flip completion irq, i.e. every modeset |
10401 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10402 | */ | |
6b95a207 | 10403 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10404 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10405 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10406 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10407 | } | |
10408 | ||
eba905b2 | 10409 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10410 | { |
10411 | /* Ensure that the work item is consistent when activating it ... */ | |
10412 | smp_wmb(); | |
10413 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10414 | /* and that it is marked active as soon as the irq could fire. */ | |
10415 | smp_wmb(); | |
10416 | } | |
10417 | ||
8c9f3aaf JB |
10418 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10419 | struct drm_crtc *crtc, | |
10420 | struct drm_framebuffer *fb, | |
ed8d1975 | 10421 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10422 | struct intel_engine_cs *ring, |
ed8d1975 | 10423 | uint32_t flags) |
8c9f3aaf | 10424 | { |
8c9f3aaf | 10425 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10426 | u32 flip_mask; |
10427 | int ret; | |
10428 | ||
6d90c952 | 10429 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10430 | if (ret) |
4fa62c89 | 10431 | return ret; |
8c9f3aaf JB |
10432 | |
10433 | /* Can't queue multiple flips, so wait for the previous | |
10434 | * one to finish before executing the next. | |
10435 | */ | |
10436 | if (intel_crtc->plane) | |
10437 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10438 | else | |
10439 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10440 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10441 | intel_ring_emit(ring, MI_NOOP); | |
10442 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10443 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10444 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10445 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10446 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10447 | |
10448 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10449 | __intel_ring_advance(ring); |
83d4092b | 10450 | return 0; |
8c9f3aaf JB |
10451 | } |
10452 | ||
10453 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10454 | struct drm_crtc *crtc, | |
10455 | struct drm_framebuffer *fb, | |
ed8d1975 | 10456 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10457 | struct intel_engine_cs *ring, |
ed8d1975 | 10458 | uint32_t flags) |
8c9f3aaf | 10459 | { |
8c9f3aaf | 10460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10461 | u32 flip_mask; |
10462 | int ret; | |
10463 | ||
6d90c952 | 10464 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10465 | if (ret) |
4fa62c89 | 10466 | return ret; |
8c9f3aaf JB |
10467 | |
10468 | if (intel_crtc->plane) | |
10469 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10470 | else | |
10471 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10472 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10473 | intel_ring_emit(ring, MI_NOOP); | |
10474 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10475 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10476 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10477 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10478 | intel_ring_emit(ring, MI_NOOP); |
10479 | ||
e7d841ca | 10480 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10481 | __intel_ring_advance(ring); |
83d4092b | 10482 | return 0; |
8c9f3aaf JB |
10483 | } |
10484 | ||
10485 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10486 | struct drm_crtc *crtc, | |
10487 | struct drm_framebuffer *fb, | |
ed8d1975 | 10488 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10489 | struct intel_engine_cs *ring, |
ed8d1975 | 10490 | uint32_t flags) |
8c9f3aaf JB |
10491 | { |
10492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10494 | uint32_t pf, pipesrc; | |
10495 | int ret; | |
10496 | ||
6d90c952 | 10497 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10498 | if (ret) |
4fa62c89 | 10499 | return ret; |
8c9f3aaf JB |
10500 | |
10501 | /* i965+ uses the linear or tiled offsets from the | |
10502 | * Display Registers (which do not change across a page-flip) | |
10503 | * so we need only reprogram the base address. | |
10504 | */ | |
6d90c952 DV |
10505 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10506 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10507 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10508 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10509 | obj->tiling_mode); |
8c9f3aaf JB |
10510 | |
10511 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10512 | * untested on non-native modes, so ignore it for now. | |
10513 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10514 | */ | |
10515 | pf = 0; | |
10516 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10517 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10518 | |
10519 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10520 | __intel_ring_advance(ring); |
83d4092b | 10521 | return 0; |
8c9f3aaf JB |
10522 | } |
10523 | ||
10524 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10525 | struct drm_crtc *crtc, | |
10526 | struct drm_framebuffer *fb, | |
ed8d1975 | 10527 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10528 | struct intel_engine_cs *ring, |
ed8d1975 | 10529 | uint32_t flags) |
8c9f3aaf JB |
10530 | { |
10531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10533 | uint32_t pf, pipesrc; | |
10534 | int ret; | |
10535 | ||
6d90c952 | 10536 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10537 | if (ret) |
4fa62c89 | 10538 | return ret; |
8c9f3aaf | 10539 | |
6d90c952 DV |
10540 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10541 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10542 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10543 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10544 | |
dc257cf1 DV |
10545 | /* Contrary to the suggestions in the documentation, |
10546 | * "Enable Panel Fitter" does not seem to be required when page | |
10547 | * flipping with a non-native mode, and worse causes a normal | |
10548 | * modeset to fail. | |
10549 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10550 | */ | |
10551 | pf = 0; | |
8c9f3aaf | 10552 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10553 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10554 | |
10555 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10556 | __intel_ring_advance(ring); |
83d4092b | 10557 | return 0; |
8c9f3aaf JB |
10558 | } |
10559 | ||
7c9017e5 JB |
10560 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10561 | struct drm_crtc *crtc, | |
10562 | struct drm_framebuffer *fb, | |
ed8d1975 | 10563 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10564 | struct intel_engine_cs *ring, |
ed8d1975 | 10565 | uint32_t flags) |
7c9017e5 | 10566 | { |
7c9017e5 | 10567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10568 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10569 | int len, ret; |
10570 | ||
eba905b2 | 10571 | switch (intel_crtc->plane) { |
cb05d8de DV |
10572 | case PLANE_A: |
10573 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10574 | break; | |
10575 | case PLANE_B: | |
10576 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10577 | break; | |
10578 | case PLANE_C: | |
10579 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10580 | break; | |
10581 | default: | |
10582 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10583 | return -ENODEV; |
cb05d8de DV |
10584 | } |
10585 | ||
ffe74d75 | 10586 | len = 4; |
f476828a | 10587 | if (ring->id == RCS) { |
ffe74d75 | 10588 | len += 6; |
f476828a DL |
10589 | /* |
10590 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10591 | * 48bits addresses, and we need a NOOP for the batch size to | |
10592 | * stay even. | |
10593 | */ | |
10594 | if (IS_GEN8(dev)) | |
10595 | len += 2; | |
10596 | } | |
ffe74d75 | 10597 | |
f66fab8e VS |
10598 | /* |
10599 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10600 | * "The full packet must be contained within the same cache line." | |
10601 | * | |
10602 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10603 | * cacheline, if we ever start emitting more commands before | |
10604 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10605 | * then do the cacheline alignment, and finally emit the | |
10606 | * MI_DISPLAY_FLIP. | |
10607 | */ | |
10608 | ret = intel_ring_cacheline_align(ring); | |
10609 | if (ret) | |
4fa62c89 | 10610 | return ret; |
f66fab8e | 10611 | |
ffe74d75 | 10612 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10613 | if (ret) |
4fa62c89 | 10614 | return ret; |
7c9017e5 | 10615 | |
ffe74d75 CW |
10616 | /* Unmask the flip-done completion message. Note that the bspec says that |
10617 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10618 | * more than one flip event at any time (or ensure that one flip message | |
10619 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10620 | * Experimentation says that BCS works despite DERRMR masking all | |
10621 | * flip-done completion events and that unmasking all planes at once | |
10622 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10623 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10624 | */ | |
10625 | if (ring->id == RCS) { | |
10626 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10627 | intel_ring_emit(ring, DERRMR); | |
10628 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10629 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10630 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10631 | if (IS_GEN8(dev)) |
10632 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10633 | MI_SRM_LRM_GLOBAL_GTT); | |
10634 | else | |
10635 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10636 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10637 | intel_ring_emit(ring, DERRMR); |
10638 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10639 | if (IS_GEN8(dev)) { |
10640 | intel_ring_emit(ring, 0); | |
10641 | intel_ring_emit(ring, MI_NOOP); | |
10642 | } | |
ffe74d75 CW |
10643 | } |
10644 | ||
cb05d8de | 10645 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10646 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10647 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10648 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10649 | |
10650 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10651 | __intel_ring_advance(ring); |
83d4092b | 10652 | return 0; |
7c9017e5 JB |
10653 | } |
10654 | ||
84c33a64 SG |
10655 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10656 | struct drm_i915_gem_object *obj) | |
10657 | { | |
10658 | /* | |
10659 | * This is not being used for older platforms, because | |
10660 | * non-availability of flip done interrupt forces us to use | |
10661 | * CS flips. Older platforms derive flip done using some clever | |
10662 | * tricks involving the flip_pending status bits and vblank irqs. | |
10663 | * So using MMIO flips there would disrupt this mechanism. | |
10664 | */ | |
10665 | ||
8e09bf83 CW |
10666 | if (ring == NULL) |
10667 | return true; | |
10668 | ||
84c33a64 SG |
10669 | if (INTEL_INFO(ring->dev)->gen < 5) |
10670 | return false; | |
10671 | ||
10672 | if (i915.use_mmio_flip < 0) | |
10673 | return false; | |
10674 | else if (i915.use_mmio_flip > 0) | |
10675 | return true; | |
14bf993e OM |
10676 | else if (i915.enable_execlists) |
10677 | return true; | |
84c33a64 | 10678 | else |
41c52415 | 10679 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10680 | } |
10681 | ||
ff944564 DL |
10682 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10683 | { | |
10684 | struct drm_device *dev = intel_crtc->base.dev; | |
10685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10686 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
10687 | const enum pipe pipe = intel_crtc->pipe; |
10688 | u32 ctl, stride; | |
10689 | ||
10690 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10691 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
10692 | switch (fb->modifier[0]) { |
10693 | case DRM_FORMAT_MOD_NONE: | |
10694 | break; | |
10695 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 10696 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
10697 | break; |
10698 | case I915_FORMAT_MOD_Y_TILED: | |
10699 | ctl |= PLANE_CTL_TILED_Y; | |
10700 | break; | |
10701 | case I915_FORMAT_MOD_Yf_TILED: | |
10702 | ctl |= PLANE_CTL_TILED_YF; | |
10703 | break; | |
10704 | default: | |
10705 | MISSING_CASE(fb->modifier[0]); | |
10706 | } | |
ff944564 DL |
10707 | |
10708 | /* | |
10709 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10710 | * linear buffers or in number of tiles for tiled buffers. | |
10711 | */ | |
2ebef630 TU |
10712 | stride = fb->pitches[0] / |
10713 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
10714 | fb->pixel_format); | |
ff944564 DL |
10715 | |
10716 | /* | |
10717 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10718 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10719 | */ | |
10720 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10721 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10722 | ||
10723 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10724 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10725 | } | |
10726 | ||
10727 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10728 | { |
10729 | struct drm_device *dev = intel_crtc->base.dev; | |
10730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10731 | struct intel_framebuffer *intel_fb = | |
10732 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10733 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10734 | u32 dspcntr; | |
10735 | u32 reg; | |
10736 | ||
84c33a64 SG |
10737 | reg = DSPCNTR(intel_crtc->plane); |
10738 | dspcntr = I915_READ(reg); | |
10739 | ||
c5d97472 DL |
10740 | if (obj->tiling_mode != I915_TILING_NONE) |
10741 | dspcntr |= DISPPLANE_TILED; | |
10742 | else | |
10743 | dspcntr &= ~DISPPLANE_TILED; | |
10744 | ||
84c33a64 SG |
10745 | I915_WRITE(reg, dspcntr); |
10746 | ||
10747 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10748 | intel_crtc->unpin_work->gtt_offset); | |
10749 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10750 | |
ff944564 DL |
10751 | } |
10752 | ||
10753 | /* | |
10754 | * XXX: This is the temporary way to update the plane registers until we get | |
10755 | * around to using the usual plane update functions for MMIO flips | |
10756 | */ | |
10757 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10758 | { | |
10759 | struct drm_device *dev = intel_crtc->base.dev; | |
10760 | bool atomic_update; | |
10761 | u32 start_vbl_count; | |
10762 | ||
10763 | intel_mark_page_flip_active(intel_crtc); | |
10764 | ||
10765 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10766 | ||
10767 | if (INTEL_INFO(dev)->gen >= 9) | |
10768 | skl_do_mmio_flip(intel_crtc); | |
10769 | else | |
10770 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10771 | ilk_do_mmio_flip(intel_crtc); | |
10772 | ||
9362c7c5 ACO |
10773 | if (atomic_update) |
10774 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10775 | } |
10776 | ||
9362c7c5 | 10777 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10778 | { |
b2cfe0ab CW |
10779 | struct intel_mmio_flip *mmio_flip = |
10780 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 10781 | |
b2cfe0ab CW |
10782 | if (mmio_flip->rq) |
10783 | WARN_ON(__i915_wait_request(mmio_flip->rq, | |
10784 | mmio_flip->crtc->reset_counter, | |
10785 | false, NULL, NULL)); | |
84c33a64 | 10786 | |
b2cfe0ab CW |
10787 | intel_do_mmio_flip(mmio_flip->crtc); |
10788 | ||
10789 | i915_gem_request_unreference__unlocked(mmio_flip->rq); | |
10790 | kfree(mmio_flip); | |
84c33a64 SG |
10791 | } |
10792 | ||
10793 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10794 | struct drm_crtc *crtc, | |
10795 | struct drm_framebuffer *fb, | |
10796 | struct drm_i915_gem_object *obj, | |
10797 | struct intel_engine_cs *ring, | |
10798 | uint32_t flags) | |
10799 | { | |
b2cfe0ab CW |
10800 | struct intel_mmio_flip *mmio_flip; |
10801 | ||
10802 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
10803 | if (mmio_flip == NULL) | |
10804 | return -ENOMEM; | |
84c33a64 | 10805 | |
b2cfe0ab CW |
10806 | mmio_flip->rq = i915_gem_request_reference(obj->last_write_req); |
10807 | mmio_flip->crtc = to_intel_crtc(crtc); | |
536f5b5e | 10808 | |
b2cfe0ab CW |
10809 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
10810 | schedule_work(&mmio_flip->work); | |
84c33a64 | 10811 | |
84c33a64 SG |
10812 | return 0; |
10813 | } | |
10814 | ||
8c9f3aaf JB |
10815 | static int intel_default_queue_flip(struct drm_device *dev, |
10816 | struct drm_crtc *crtc, | |
10817 | struct drm_framebuffer *fb, | |
ed8d1975 | 10818 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10819 | struct intel_engine_cs *ring, |
ed8d1975 | 10820 | uint32_t flags) |
8c9f3aaf JB |
10821 | { |
10822 | return -ENODEV; | |
10823 | } | |
10824 | ||
d6bbafa1 CW |
10825 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10826 | struct drm_crtc *crtc) | |
10827 | { | |
10828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10830 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10831 | u32 addr; | |
10832 | ||
10833 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10834 | return true; | |
10835 | ||
10836 | if (!work->enable_stall_check) | |
10837 | return false; | |
10838 | ||
10839 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10840 | if (work->flip_queued_req && |
10841 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10842 | return false; |
10843 | ||
1e3feefd | 10844 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10845 | } |
10846 | ||
1e3feefd | 10847 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10848 | return false; |
10849 | ||
10850 | /* Potential stall - if we see that the flip has happened, | |
10851 | * assume a missed interrupt. */ | |
10852 | if (INTEL_INFO(dev)->gen >= 4) | |
10853 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10854 | else | |
10855 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10856 | ||
10857 | /* There is a potential issue here with a false positive after a flip | |
10858 | * to the same address. We could address this by checking for a | |
10859 | * non-incrementing frame counter. | |
10860 | */ | |
10861 | return addr == work->gtt_offset; | |
10862 | } | |
10863 | ||
10864 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10865 | { | |
10866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10867 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10869 | struct intel_unpin_work *work; |
f326038a | 10870 | |
6c51d46f | 10871 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10872 | |
10873 | if (crtc == NULL) | |
10874 | return; | |
10875 | ||
f326038a | 10876 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10877 | work = intel_crtc->unpin_work; |
10878 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10879 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10880 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10881 | page_flip_completed(intel_crtc); |
6ad790c0 | 10882 | work = NULL; |
d6bbafa1 | 10883 | } |
6ad790c0 CW |
10884 | if (work != NULL && |
10885 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10886 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10887 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10888 | } |
10889 | ||
6b95a207 KH |
10890 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10891 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10892 | struct drm_pending_vblank_event *event, |
10893 | uint32_t page_flip_flags) | |
6b95a207 KH |
10894 | { |
10895 | struct drm_device *dev = crtc->dev; | |
10896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10897 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10898 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10900 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10901 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10902 | struct intel_unpin_work *work; |
a4872ba6 | 10903 | struct intel_engine_cs *ring; |
cf5d8a46 | 10904 | bool mmio_flip; |
52e68630 | 10905 | int ret; |
6b95a207 | 10906 | |
2ff8fde1 MR |
10907 | /* |
10908 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10909 | * check to be safe. In the future we may enable pageflipping from | |
10910 | * a disabled primary plane. | |
10911 | */ | |
10912 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10913 | return -EBUSY; | |
10914 | ||
e6a595d2 | 10915 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10916 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10917 | return -EINVAL; |
10918 | ||
10919 | /* | |
10920 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10921 | * Note that pitch changes could also affect these register. | |
10922 | */ | |
10923 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10924 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10925 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10926 | return -EINVAL; |
10927 | ||
f900db47 CW |
10928 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10929 | goto out_hang; | |
10930 | ||
b14c5679 | 10931 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10932 | if (work == NULL) |
10933 | return -ENOMEM; | |
10934 | ||
6b95a207 | 10935 | work->event = event; |
b4a98e57 | 10936 | work->crtc = crtc; |
ab8d6675 | 10937 | work->old_fb = old_fb; |
6b95a207 KH |
10938 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10939 | ||
87b6b101 | 10940 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10941 | if (ret) |
10942 | goto free_work; | |
10943 | ||
6b95a207 | 10944 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10945 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10946 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10947 | /* Before declaring the flip queue wedged, check if |
10948 | * the hardware completed the operation behind our backs. | |
10949 | */ | |
10950 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10951 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10952 | page_flip_completed(intel_crtc); | |
10953 | } else { | |
10954 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10955 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10956 | |
d6bbafa1 CW |
10957 | drm_crtc_vblank_put(crtc); |
10958 | kfree(work); | |
10959 | return -EBUSY; | |
10960 | } | |
6b95a207 KH |
10961 | } |
10962 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10963 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10964 | |
b4a98e57 CW |
10965 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10966 | flush_workqueue(dev_priv->wq); | |
10967 | ||
75dfca80 | 10968 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10969 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10970 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10971 | |
f4510a27 | 10972 | crtc->primary->fb = fb; |
afd65eb4 | 10973 | update_state_fb(crtc->primary); |
1ed1f968 | 10974 | |
e1f99ce6 | 10975 | work->pending_flip_obj = obj; |
e1f99ce6 | 10976 | |
89ed88ba CW |
10977 | ret = i915_mutex_lock_interruptible(dev); |
10978 | if (ret) | |
10979 | goto cleanup; | |
10980 | ||
b4a98e57 | 10981 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10982 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10983 | |
75f7f3ec | 10984 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10985 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10986 | |
4fa62c89 VS |
10987 | if (IS_VALLEYVIEW(dev)) { |
10988 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10989 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10990 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10991 | ring = NULL; | |
48bf5b2d | 10992 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10993 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10994 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10995 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10996 | if (ring == NULL || ring->id != RCS) |
10997 | ring = &dev_priv->ring[BCS]; | |
10998 | } else { | |
10999 | ring = &dev_priv->ring[RCS]; | |
11000 | } | |
11001 | ||
cf5d8a46 CW |
11002 | mmio_flip = use_mmio_flip(ring, obj); |
11003 | ||
11004 | /* When using CS flips, we want to emit semaphores between rings. | |
11005 | * However, when using mmio flips we will create a task to do the | |
11006 | * synchronisation, so all we want here is to pin the framebuffer | |
11007 | * into the display plane and skip any waits. | |
11008 | */ | |
82bc3b2d | 11009 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
11010 | crtc->primary->state, |
11011 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
11012 | if (ret) |
11013 | goto cleanup_pending; | |
6b95a207 | 11014 | |
121920fa TU |
11015 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11016 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11017 | |
cf5d8a46 | 11018 | if (mmio_flip) { |
84c33a64 SG |
11019 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11020 | page_flip_flags); | |
d6bbafa1 CW |
11021 | if (ret) |
11022 | goto cleanup_unpin; | |
11023 | ||
f06cc1b9 JH |
11024 | i915_gem_request_assign(&work->flip_queued_req, |
11025 | obj->last_write_req); | |
d6bbafa1 | 11026 | } else { |
d94b5030 CW |
11027 | if (obj->last_write_req) { |
11028 | ret = i915_gem_check_olr(obj->last_write_req); | |
11029 | if (ret) | |
11030 | goto cleanup_unpin; | |
11031 | } | |
11032 | ||
84c33a64 | 11033 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
11034 | page_flip_flags); |
11035 | if (ret) | |
11036 | goto cleanup_unpin; | |
11037 | ||
f06cc1b9 JH |
11038 | i915_gem_request_assign(&work->flip_queued_req, |
11039 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
11040 | } |
11041 | ||
1e3feefd | 11042 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11043 | work->enable_stall_check = true; |
4fa62c89 | 11044 | |
ab8d6675 | 11045 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
11046 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11047 | ||
7ff0ebcc | 11048 | intel_fbc_disable(dev); |
f99d7069 | 11049 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
11050 | mutex_unlock(&dev->struct_mutex); |
11051 | ||
e5510fac JB |
11052 | trace_i915_flip_request(intel_crtc->plane, obj); |
11053 | ||
6b95a207 | 11054 | return 0; |
96b099fd | 11055 | |
4fa62c89 | 11056 | cleanup_unpin: |
82bc3b2d | 11057 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11058 | cleanup_pending: |
b4a98e57 | 11059 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11060 | mutex_unlock(&dev->struct_mutex); |
11061 | cleanup: | |
f4510a27 | 11062 | crtc->primary->fb = old_fb; |
afd65eb4 | 11063 | update_state_fb(crtc->primary); |
89ed88ba CW |
11064 | |
11065 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11066 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11067 | |
5e2d7afc | 11068 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11069 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11070 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11071 | |
87b6b101 | 11072 | drm_crtc_vblank_put(crtc); |
7317c75e | 11073 | free_work: |
96b099fd CW |
11074 | kfree(work); |
11075 | ||
f900db47 CW |
11076 | if (ret == -EIO) { |
11077 | out_hang: | |
53a366b9 | 11078 | ret = intel_plane_restore(primary); |
f0d3dad3 | 11079 | if (ret == 0 && event) { |
5e2d7afc | 11080 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11081 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11082 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11083 | } |
f900db47 | 11084 | } |
96b099fd | 11085 | return ret; |
6b95a207 KH |
11086 | } |
11087 | ||
65b38e0d | 11088 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11089 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11090 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11091 | .atomic_begin = intel_begin_crtc_commit, |
11092 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
11093 | }; |
11094 | ||
9a935856 DV |
11095 | /** |
11096 | * intel_modeset_update_staged_output_state | |
11097 | * | |
11098 | * Updates the staged output configuration state, e.g. after we've read out the | |
11099 | * current hw state. | |
11100 | */ | |
11101 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 11102 | { |
7668851f | 11103 | struct intel_crtc *crtc; |
9a935856 DV |
11104 | struct intel_encoder *encoder; |
11105 | struct intel_connector *connector; | |
f6e5b160 | 11106 | |
3a3371ff | 11107 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11108 | connector->new_encoder = |
11109 | to_intel_encoder(connector->base.encoder); | |
11110 | } | |
f6e5b160 | 11111 | |
b2784e15 | 11112 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11113 | encoder->new_crtc = |
11114 | to_intel_crtc(encoder->base.crtc); | |
11115 | } | |
7668851f | 11116 | |
d3fcc808 | 11117 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11118 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 11119 | } |
f6e5b160 CW |
11120 | } |
11121 | ||
d29b2f9d ACO |
11122 | /* Transitional helper to copy current connector/encoder state to |
11123 | * connector->state. This is needed so that code that is partially | |
11124 | * converted to atomic does the right thing. | |
11125 | */ | |
11126 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11127 | { | |
11128 | struct intel_connector *connector; | |
11129 | ||
11130 | for_each_intel_connector(dev, connector) { | |
11131 | if (connector->base.encoder) { | |
11132 | connector->base.state->best_encoder = | |
11133 | connector->base.encoder; | |
11134 | connector->base.state->crtc = | |
11135 | connector->base.encoder->crtc; | |
11136 | } else { | |
11137 | connector->base.state->best_encoder = NULL; | |
11138 | connector->base.state->crtc = NULL; | |
11139 | } | |
11140 | } | |
11141 | } | |
11142 | ||
a821fc46 | 11143 | /* Fixup legacy state after an atomic state swap. |
9a935856 | 11144 | */ |
a821fc46 | 11145 | static void intel_modeset_fixup_state(struct drm_atomic_state *state) |
9a935856 | 11146 | { |
a821fc46 | 11147 | struct intel_crtc *crtc; |
9a935856 | 11148 | struct intel_encoder *encoder; |
a821fc46 | 11149 | struct intel_connector *connector; |
d5432a9d | 11150 | |
a821fc46 ACO |
11151 | for_each_intel_connector(state->dev, connector) { |
11152 | connector->base.encoder = connector->base.state->best_encoder; | |
11153 | if (connector->base.encoder) | |
11154 | connector->base.encoder->crtc = | |
11155 | connector->base.state->crtc; | |
9a935856 | 11156 | } |
f6e5b160 | 11157 | |
d5432a9d ACO |
11158 | /* Update crtc of disabled encoders */ |
11159 | for_each_intel_encoder(state->dev, encoder) { | |
11160 | int num_connectors = 0; | |
11161 | ||
a821fc46 ACO |
11162 | for_each_intel_connector(state->dev, connector) |
11163 | if (connector->base.encoder == &encoder->base) | |
d5432a9d ACO |
11164 | num_connectors++; |
11165 | ||
11166 | if (num_connectors == 0) | |
11167 | encoder->base.crtc = NULL; | |
9a935856 | 11168 | } |
7668851f | 11169 | |
a821fc46 ACO |
11170 | for_each_intel_crtc(state->dev, crtc) { |
11171 | crtc->base.enabled = crtc->base.state->enable; | |
11172 | crtc->config = to_intel_crtc_state(crtc->base.state); | |
7668851f | 11173 | } |
d29b2f9d | 11174 | |
d5432a9d ACO |
11175 | /* Copy the new configuration to the staged state, to keep the few |
11176 | * pieces of code that haven't been converted yet happy */ | |
11177 | intel_modeset_update_staged_output_state(state->dev); | |
9a935856 DV |
11178 | } |
11179 | ||
050f7aeb | 11180 | static void |
eba905b2 | 11181 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11182 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11183 | { |
11184 | int bpp = pipe_config->pipe_bpp; | |
11185 | ||
11186 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11187 | connector->base.base.id, | |
c23cc417 | 11188 | connector->base.name); |
050f7aeb DV |
11189 | |
11190 | /* Don't use an invalid EDID bpc value */ | |
11191 | if (connector->base.display_info.bpc && | |
11192 | connector->base.display_info.bpc * 3 < bpp) { | |
11193 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11194 | bpp, connector->base.display_info.bpc*3); | |
11195 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11196 | } | |
11197 | ||
11198 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11199 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11200 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11201 | bpp); | |
11202 | pipe_config->pipe_bpp = 24; | |
11203 | } | |
11204 | } | |
11205 | ||
4e53c2e0 | 11206 | static int |
050f7aeb | 11207 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11208 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11209 | { |
050f7aeb | 11210 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11211 | struct drm_atomic_state *state; |
da3ced29 ACO |
11212 | struct drm_connector *connector; |
11213 | struct drm_connector_state *connector_state; | |
1486017f | 11214 | int bpp, i; |
4e53c2e0 | 11215 | |
d328c9d7 | 11216 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11217 | bpp = 10*3; |
d328c9d7 DV |
11218 | else if (INTEL_INFO(dev)->gen >= 5) |
11219 | bpp = 12*3; | |
11220 | else | |
11221 | bpp = 8*3; | |
11222 | ||
4e53c2e0 | 11223 | |
4e53c2e0 DV |
11224 | pipe_config->pipe_bpp = bpp; |
11225 | ||
1486017f ACO |
11226 | state = pipe_config->base.state; |
11227 | ||
4e53c2e0 | 11228 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11229 | for_each_connector_in_state(state, connector, connector_state, i) { |
11230 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11231 | continue; |
11232 | ||
da3ced29 ACO |
11233 | connected_sink_compute_bpp(to_intel_connector(connector), |
11234 | pipe_config); | |
4e53c2e0 DV |
11235 | } |
11236 | ||
11237 | return bpp; | |
11238 | } | |
11239 | ||
644db711 DV |
11240 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11241 | { | |
11242 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11243 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11244 | mode->crtc_clock, |
644db711 DV |
11245 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11246 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11247 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11248 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11249 | } | |
11250 | ||
c0b03411 | 11251 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11252 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11253 | const char *context) |
11254 | { | |
6a60cd87 CK |
11255 | struct drm_device *dev = crtc->base.dev; |
11256 | struct drm_plane *plane; | |
11257 | struct intel_plane *intel_plane; | |
11258 | struct intel_plane_state *state; | |
11259 | struct drm_framebuffer *fb; | |
11260 | ||
11261 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11262 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11263 | |
11264 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11265 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11266 | pipe_config->pipe_bpp, pipe_config->dither); | |
11267 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11268 | pipe_config->has_pch_encoder, | |
11269 | pipe_config->fdi_lanes, | |
11270 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11271 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11272 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11273 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11274 | pipe_config->has_dp_encoder, | |
11275 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11276 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11277 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11278 | |
11279 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11280 | pipe_config->has_dp_encoder, | |
11281 | pipe_config->dp_m2_n2.gmch_m, | |
11282 | pipe_config->dp_m2_n2.gmch_n, | |
11283 | pipe_config->dp_m2_n2.link_m, | |
11284 | pipe_config->dp_m2_n2.link_n, | |
11285 | pipe_config->dp_m2_n2.tu); | |
11286 | ||
55072d19 DV |
11287 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11288 | pipe_config->has_audio, | |
11289 | pipe_config->has_infoframe); | |
11290 | ||
c0b03411 | 11291 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11292 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11293 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11294 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11295 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11296 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11297 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11298 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11299 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11300 | crtc->num_scalers, | |
11301 | pipe_config->scaler_state.scaler_users, | |
11302 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11303 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11304 | pipe_config->gmch_pfit.control, | |
11305 | pipe_config->gmch_pfit.pgm_ratios, | |
11306 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11307 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11308 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11309 | pipe_config->pch_pfit.size, |
11310 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11311 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11312 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11313 | |
415ff0f6 TU |
11314 | if (IS_BROXTON(dev)) { |
11315 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " | |
11316 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " | |
11317 | "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", | |
11318 | pipe_config->ddi_pll_sel, | |
11319 | pipe_config->dpll_hw_state.ebb0, | |
11320 | pipe_config->dpll_hw_state.pll0, | |
11321 | pipe_config->dpll_hw_state.pll1, | |
11322 | pipe_config->dpll_hw_state.pll2, | |
11323 | pipe_config->dpll_hw_state.pll3, | |
11324 | pipe_config->dpll_hw_state.pll6, | |
11325 | pipe_config->dpll_hw_state.pll8, | |
11326 | pipe_config->dpll_hw_state.pcsdw12); | |
11327 | } else if (IS_SKYLAKE(dev)) { | |
11328 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
11329 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11330 | pipe_config->ddi_pll_sel, | |
11331 | pipe_config->dpll_hw_state.ctrl1, | |
11332 | pipe_config->dpll_hw_state.cfgcr1, | |
11333 | pipe_config->dpll_hw_state.cfgcr2); | |
11334 | } else if (HAS_DDI(dev)) { | |
11335 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
11336 | pipe_config->ddi_pll_sel, | |
11337 | pipe_config->dpll_hw_state.wrpll); | |
11338 | } else { | |
11339 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
11340 | "fp0: 0x%x, fp1: 0x%x\n", | |
11341 | pipe_config->dpll_hw_state.dpll, | |
11342 | pipe_config->dpll_hw_state.dpll_md, | |
11343 | pipe_config->dpll_hw_state.fp0, | |
11344 | pipe_config->dpll_hw_state.fp1); | |
11345 | } | |
11346 | ||
6a60cd87 CK |
11347 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11348 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11349 | intel_plane = to_intel_plane(plane); | |
11350 | if (intel_plane->pipe != crtc->pipe) | |
11351 | continue; | |
11352 | ||
11353 | state = to_intel_plane_state(plane->state); | |
11354 | fb = state->base.fb; | |
11355 | if (!fb) { | |
11356 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11357 | "disabled, scaler_id = %d\n", | |
11358 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11359 | plane->base.id, intel_plane->pipe, | |
11360 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11361 | drm_plane_index(plane), state->scaler_id); | |
11362 | continue; | |
11363 | } | |
11364 | ||
11365 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11366 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11367 | plane->base.id, intel_plane->pipe, | |
11368 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11369 | drm_plane_index(plane)); | |
11370 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11371 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11372 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11373 | state->scaler_id, | |
11374 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11375 | drm_rect_width(&state->src) >> 16, | |
11376 | drm_rect_height(&state->src) >> 16, | |
11377 | state->dst.x1, state->dst.y1, | |
11378 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11379 | } | |
c0b03411 DV |
11380 | } |
11381 | ||
bc079e8b VS |
11382 | static bool encoders_cloneable(const struct intel_encoder *a, |
11383 | const struct intel_encoder *b) | |
accfc0c5 | 11384 | { |
bc079e8b VS |
11385 | /* masks could be asymmetric, so check both ways */ |
11386 | return a == b || (a->cloneable & (1 << b->type) && | |
11387 | b->cloneable & (1 << a->type)); | |
11388 | } | |
11389 | ||
98a221da ACO |
11390 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11391 | struct intel_crtc *crtc, | |
bc079e8b VS |
11392 | struct intel_encoder *encoder) |
11393 | { | |
bc079e8b | 11394 | struct intel_encoder *source_encoder; |
da3ced29 | 11395 | struct drm_connector *connector; |
98a221da ACO |
11396 | struct drm_connector_state *connector_state; |
11397 | int i; | |
bc079e8b | 11398 | |
da3ced29 | 11399 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da | 11400 | if (connector_state->crtc != &crtc->base) |
bc079e8b VS |
11401 | continue; |
11402 | ||
98a221da ACO |
11403 | source_encoder = |
11404 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11405 | if (!encoders_cloneable(encoder, source_encoder)) |
11406 | return false; | |
11407 | } | |
11408 | ||
11409 | return true; | |
11410 | } | |
11411 | ||
98a221da ACO |
11412 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11413 | struct intel_crtc *crtc) | |
bc079e8b | 11414 | { |
accfc0c5 | 11415 | struct intel_encoder *encoder; |
da3ced29 | 11416 | struct drm_connector *connector; |
98a221da ACO |
11417 | struct drm_connector_state *connector_state; |
11418 | int i; | |
accfc0c5 | 11419 | |
da3ced29 | 11420 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da ACO |
11421 | if (connector_state->crtc != &crtc->base) |
11422 | continue; | |
11423 | ||
11424 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11425 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11426 | return false; |
accfc0c5 DV |
11427 | } |
11428 | ||
bc079e8b | 11429 | return true; |
accfc0c5 DV |
11430 | } |
11431 | ||
5448a00d | 11432 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11433 | { |
5448a00d ACO |
11434 | struct drm_device *dev = state->dev; |
11435 | struct intel_encoder *encoder; | |
da3ced29 | 11436 | struct drm_connector *connector; |
5448a00d | 11437 | struct drm_connector_state *connector_state; |
00f0b378 | 11438 | unsigned int used_ports = 0; |
5448a00d | 11439 | int i; |
00f0b378 VS |
11440 | |
11441 | /* | |
11442 | * Walk the connector list instead of the encoder | |
11443 | * list to detect the problem on ddi platforms | |
11444 | * where there's just one encoder per digital port. | |
11445 | */ | |
da3ced29 | 11446 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 11447 | if (!connector_state->best_encoder) |
00f0b378 VS |
11448 | continue; |
11449 | ||
5448a00d ACO |
11450 | encoder = to_intel_encoder(connector_state->best_encoder); |
11451 | ||
11452 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11453 | |
11454 | switch (encoder->type) { | |
11455 | unsigned int port_mask; | |
11456 | case INTEL_OUTPUT_UNKNOWN: | |
11457 | if (WARN_ON(!HAS_DDI(dev))) | |
11458 | break; | |
11459 | case INTEL_OUTPUT_DISPLAYPORT: | |
11460 | case INTEL_OUTPUT_HDMI: | |
11461 | case INTEL_OUTPUT_EDP: | |
11462 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11463 | ||
11464 | /* the same port mustn't appear more than once */ | |
11465 | if (used_ports & port_mask) | |
11466 | return false; | |
11467 | ||
11468 | used_ports |= port_mask; | |
11469 | default: | |
11470 | break; | |
11471 | } | |
11472 | } | |
11473 | ||
11474 | return true; | |
11475 | } | |
11476 | ||
83a57153 ACO |
11477 | static void |
11478 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11479 | { | |
11480 | struct drm_crtc_state tmp_state; | |
663a3640 | 11481 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
11482 | struct intel_dpll_hw_state dpll_hw_state; |
11483 | enum intel_dpll_id shared_dpll; | |
8504c74c | 11484 | uint32_t ddi_pll_sel; |
83a57153 | 11485 | |
663a3640 | 11486 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 11487 | tmp_state = crtc_state->base; |
663a3640 | 11488 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11489 | shared_dpll = crtc_state->shared_dpll; |
11490 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 11491 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
4978cc93 | 11492 | |
83a57153 | 11493 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11494 | |
83a57153 | 11495 | crtc_state->base = tmp_state; |
663a3640 | 11496 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11497 | crtc_state->shared_dpll = shared_dpll; |
11498 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 11499 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
83a57153 ACO |
11500 | } |
11501 | ||
548ee15b | 11502 | static int |
b8cecdf5 | 11503 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
548ee15b ACO |
11504 | struct drm_atomic_state *state, |
11505 | struct intel_crtc_state *pipe_config) | |
ee7b9f93 | 11506 | { |
7758a113 | 11507 | struct intel_encoder *encoder; |
da3ced29 | 11508 | struct drm_connector *connector; |
0b901879 | 11509 | struct drm_connector_state *connector_state; |
d328c9d7 | 11510 | int base_bpp, ret = -EINVAL; |
0b901879 | 11511 | int i; |
e29c22c0 | 11512 | bool retry = true; |
ee7b9f93 | 11513 | |
98a221da | 11514 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 | 11515 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
548ee15b | 11516 | return -EINVAL; |
accfc0c5 DV |
11517 | } |
11518 | ||
5448a00d | 11519 | if (!check_digital_port_conflicts(state)) { |
00f0b378 | 11520 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
548ee15b | 11521 | return -EINVAL; |
00f0b378 VS |
11522 | } |
11523 | ||
83a57153 | 11524 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11525 | |
e143a21c DV |
11526 | pipe_config->cpu_transcoder = |
11527 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11528 | |
2960bc9c ID |
11529 | /* |
11530 | * Sanitize sync polarity flags based on requested ones. If neither | |
11531 | * positive or negative polarity is requested, treat this as meaning | |
11532 | * negative polarity. | |
11533 | */ | |
2d112de7 | 11534 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11535 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11536 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11537 | |
2d112de7 | 11538 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11539 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11540 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11541 | |
050f7aeb DV |
11542 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11543 | * plane pixel format and any sink constraints into account. Returns the | |
11544 | * source plane bpp so that dithering can be selected on mismatches | |
11545 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11546 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11547 | pipe_config); | |
11548 | if (base_bpp < 0) | |
4e53c2e0 DV |
11549 | goto fail; |
11550 | ||
e41a56be VS |
11551 | /* |
11552 | * Determine the real pipe dimensions. Note that stereo modes can | |
11553 | * increase the actual pipe size due to the frame doubling and | |
11554 | * insertion of additional space for blanks between the frame. This | |
11555 | * is stored in the crtc timings. We use the requested mode to do this | |
11556 | * computation to clearly distinguish it from the adjusted mode, which | |
11557 | * can be changed by the connectors in the below retry loop. | |
11558 | */ | |
2d112de7 | 11559 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11560 | &pipe_config->pipe_src_w, |
11561 | &pipe_config->pipe_src_h); | |
e41a56be | 11562 | |
e29c22c0 | 11563 | encoder_retry: |
ef1b460d | 11564 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11565 | pipe_config->port_clock = 0; |
ef1b460d | 11566 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11567 | |
135c81b8 | 11568 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11569 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11570 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11571 | |
7758a113 DV |
11572 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11573 | * adjust it according to limitations or connector properties, and also | |
11574 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11575 | */ |
da3ced29 | 11576 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11577 | if (connector_state->crtc != crtc) |
7758a113 | 11578 | continue; |
7ae89233 | 11579 | |
0b901879 ACO |
11580 | encoder = to_intel_encoder(connector_state->best_encoder); |
11581 | ||
efea6e8e DV |
11582 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11583 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11584 | goto fail; |
11585 | } | |
ee7b9f93 | 11586 | } |
47f1c6c9 | 11587 | |
ff9a6750 DV |
11588 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11589 | * done afterwards in case the encoder adjusts the mode. */ | |
11590 | if (!pipe_config->port_clock) | |
2d112de7 | 11591 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11592 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11593 | |
a43f6e0f | 11594 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11595 | if (ret < 0) { |
7758a113 DV |
11596 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11597 | goto fail; | |
ee7b9f93 | 11598 | } |
e29c22c0 DV |
11599 | |
11600 | if (ret == RETRY) { | |
11601 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11602 | ret = -EINVAL; | |
11603 | goto fail; | |
11604 | } | |
11605 | ||
11606 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11607 | retry = false; | |
11608 | goto encoder_retry; | |
11609 | } | |
11610 | ||
d328c9d7 | 11611 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11612 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11613 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11614 | |
548ee15b | 11615 | return 0; |
7758a113 | 11616 | fail: |
548ee15b | 11617 | return ret; |
ee7b9f93 | 11618 | } |
47f1c6c9 | 11619 | |
ea9d758d | 11620 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11621 | { |
ea9d758d | 11622 | struct drm_encoder *encoder; |
f6e5b160 | 11623 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11624 | |
ea9d758d DV |
11625 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11626 | if (encoder->crtc == crtc) | |
11627 | return true; | |
11628 | ||
11629 | return false; | |
11630 | } | |
11631 | ||
0a9ab303 ACO |
11632 | static bool |
11633 | needs_modeset(struct drm_crtc_state *state) | |
11634 | { | |
11635 | return state->mode_changed || state->active_changed; | |
11636 | } | |
11637 | ||
ea9d758d | 11638 | static void |
0a9ab303 | 11639 | intel_modeset_update_state(struct drm_atomic_state *state) |
ea9d758d | 11640 | { |
0a9ab303 | 11641 | struct drm_device *dev = state->dev; |
ba41c0de | 11642 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d | 11643 | struct intel_encoder *intel_encoder; |
0a9ab303 ACO |
11644 | struct drm_crtc *crtc; |
11645 | struct drm_crtc_state *crtc_state; | |
ea9d758d | 11646 | struct drm_connector *connector; |
0a9ab303 | 11647 | int i; |
ea9d758d | 11648 | |
ba41c0de DV |
11649 | intel_shared_dpll_commit(dev_priv); |
11650 | ||
b2784e15 | 11651 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11652 | if (!intel_encoder->base.crtc) |
11653 | continue; | |
11654 | ||
0a9ab303 ACO |
11655 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
11656 | if (crtc == intel_encoder->base.crtc) | |
11657 | break; | |
11658 | ||
11659 | if (crtc != intel_encoder->base.crtc) | |
11660 | continue; | |
ea9d758d | 11661 | |
0a9ab303 | 11662 | if (crtc_state->enable && needs_modeset(crtc_state)) |
ea9d758d DV |
11663 | intel_encoder->connectors_active = false; |
11664 | } | |
11665 | ||
a821fc46 ACO |
11666 | drm_atomic_helper_swap_state(state->dev, state); |
11667 | intel_modeset_fixup_state(state); | |
ea9d758d | 11668 | |
7668851f | 11669 | /* Double check state. */ |
0a9ab303 ACO |
11670 | for_each_crtc(dev, crtc) { |
11671 | WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); | |
ea9d758d DV |
11672 | } |
11673 | ||
11674 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11675 | if (!connector->encoder || !connector->encoder->crtc) | |
11676 | continue; | |
11677 | ||
0a9ab303 ACO |
11678 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
11679 | if (crtc == connector->encoder->crtc) | |
11680 | break; | |
11681 | ||
11682 | if (crtc != connector->encoder->crtc) | |
11683 | continue; | |
ea9d758d | 11684 | |
a821fc46 | 11685 | if (crtc->state->enable && needs_modeset(crtc->state)) { |
68d34720 DV |
11686 | struct drm_property *dpms_property = |
11687 | dev->mode_config.dpms_property; | |
11688 | ||
ea9d758d | 11689 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11690 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11691 | dpms_property, |
11692 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11693 | |
11694 | intel_encoder = to_intel_encoder(connector->encoder); | |
11695 | intel_encoder->connectors_active = true; | |
11696 | } | |
11697 | } | |
11698 | ||
11699 | } | |
11700 | ||
3bd26263 | 11701 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11702 | { |
3bd26263 | 11703 | int diff; |
f1f644dc JB |
11704 | |
11705 | if (clock1 == clock2) | |
11706 | return true; | |
11707 | ||
11708 | if (!clock1 || !clock2) | |
11709 | return false; | |
11710 | ||
11711 | diff = abs(clock1 - clock2); | |
11712 | ||
11713 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11714 | return true; | |
11715 | ||
11716 | return false; | |
11717 | } | |
11718 | ||
25c5b266 DV |
11719 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11720 | list_for_each_entry((intel_crtc), \ | |
11721 | &(dev)->mode_config.crtc_list, \ | |
11722 | base.head) \ | |
0973f18f | 11723 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11724 | |
0e8ffe1b | 11725 | static bool |
2fa2fe9a | 11726 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11727 | struct intel_crtc_state *current_config, |
11728 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11729 | { |
66e985c0 DV |
11730 | #define PIPE_CONF_CHECK_X(name) \ |
11731 | if (current_config->name != pipe_config->name) { \ | |
11732 | DRM_ERROR("mismatch in " #name " " \ | |
11733 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11734 | current_config->name, \ | |
11735 | pipe_config->name); \ | |
11736 | return false; \ | |
11737 | } | |
11738 | ||
08a24034 DV |
11739 | #define PIPE_CONF_CHECK_I(name) \ |
11740 | if (current_config->name != pipe_config->name) { \ | |
11741 | DRM_ERROR("mismatch in " #name " " \ | |
11742 | "(expected %i, found %i)\n", \ | |
11743 | current_config->name, \ | |
11744 | pipe_config->name); \ | |
11745 | return false; \ | |
88adfff1 DV |
11746 | } |
11747 | ||
b95af8be VK |
11748 | /* This is required for BDW+ where there is only one set of registers for |
11749 | * switching between high and low RR. | |
11750 | * This macro can be used whenever a comparison has to be made between one | |
11751 | * hw state and multiple sw state variables. | |
11752 | */ | |
11753 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11754 | if ((current_config->name != pipe_config->name) && \ | |
11755 | (current_config->alt_name != pipe_config->name)) { \ | |
11756 | DRM_ERROR("mismatch in " #name " " \ | |
11757 | "(expected %i or %i, found %i)\n", \ | |
11758 | current_config->name, \ | |
11759 | current_config->alt_name, \ | |
11760 | pipe_config->name); \ | |
11761 | return false; \ | |
11762 | } | |
11763 | ||
1bd1bd80 DV |
11764 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11765 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11766 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11767 | "(expected %i, found %i)\n", \ |
11768 | current_config->name & (mask), \ | |
11769 | pipe_config->name & (mask)); \ | |
11770 | return false; \ | |
11771 | } | |
11772 | ||
5e550656 VS |
11773 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11774 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11775 | DRM_ERROR("mismatch in " #name " " \ | |
11776 | "(expected %i, found %i)\n", \ | |
11777 | current_config->name, \ | |
11778 | pipe_config->name); \ | |
11779 | return false; \ | |
11780 | } | |
11781 | ||
bb760063 DV |
11782 | #define PIPE_CONF_QUIRK(quirk) \ |
11783 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11784 | ||
eccb140b DV |
11785 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11786 | ||
08a24034 DV |
11787 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11788 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11789 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11790 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11791 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11792 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11793 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11794 | |
eb14cb74 | 11795 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11796 | |
11797 | if (INTEL_INFO(dev)->gen < 8) { | |
11798 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11799 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11800 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11801 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11802 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11803 | ||
11804 | if (current_config->has_drrs) { | |
11805 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11806 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11807 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11808 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11809 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11810 | } | |
11811 | } else { | |
11812 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11813 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11814 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11815 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11816 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11817 | } | |
eb14cb74 | 11818 | |
2d112de7 ACO |
11819 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11820 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11821 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11822 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11823 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11824 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11825 | |
2d112de7 ACO |
11826 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11827 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11828 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11829 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11830 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11831 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11832 | |
c93f54cf | 11833 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11834 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11835 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11836 | IS_VALLEYVIEW(dev)) | |
11837 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11838 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11839 | |
9ed109a7 DV |
11840 | PIPE_CONF_CHECK_I(has_audio); |
11841 | ||
2d112de7 | 11842 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11843 | DRM_MODE_FLAG_INTERLACE); |
11844 | ||
bb760063 | 11845 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11846 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11847 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11848 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11849 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11850 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11851 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11852 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11853 | DRM_MODE_FLAG_NVSYNC); |
11854 | } | |
045ac3b5 | 11855 | |
37327abd VS |
11856 | PIPE_CONF_CHECK_I(pipe_src_w); |
11857 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11858 | |
9953599b DV |
11859 | /* |
11860 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11861 | * screen. Since we don't yet re-compute the pipe config when moving | |
11862 | * just the lvds port away to another pipe the sw tracking won't match. | |
11863 | * | |
11864 | * Proper atomic modesets with recomputed global state will fix this. | |
11865 | * Until then just don't check gmch state for inherited modes. | |
11866 | */ | |
11867 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11868 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11869 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11870 | if (INTEL_INFO(dev)->gen < 4) | |
11871 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11872 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11873 | } | |
11874 | ||
fd4daa9c CW |
11875 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11876 | if (current_config->pch_pfit.enabled) { | |
11877 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11878 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11879 | } | |
2fa2fe9a | 11880 | |
a1b2278e CK |
11881 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
11882 | ||
e59150dc JB |
11883 | /* BDW+ don't expose a synchronous way to read the state */ |
11884 | if (IS_HASWELL(dev)) | |
11885 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11886 | |
282740f7 VS |
11887 | PIPE_CONF_CHECK_I(double_wide); |
11888 | ||
26804afd DV |
11889 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11890 | ||
c0d43d62 | 11891 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11892 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11893 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11894 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11895 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11896 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11897 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11898 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11899 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11900 | |
42571aef VS |
11901 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11902 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11903 | ||
2d112de7 | 11904 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11905 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11906 | |
66e985c0 | 11907 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11908 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11909 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11910 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11911 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11912 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11913 | |
0e8ffe1b DV |
11914 | return true; |
11915 | } | |
11916 | ||
08db6652 DL |
11917 | static void check_wm_state(struct drm_device *dev) |
11918 | { | |
11919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11920 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11921 | struct intel_crtc *intel_crtc; | |
11922 | int plane; | |
11923 | ||
11924 | if (INTEL_INFO(dev)->gen < 9) | |
11925 | return; | |
11926 | ||
11927 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11928 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11929 | ||
11930 | for_each_intel_crtc(dev, intel_crtc) { | |
11931 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11932 | const enum pipe pipe = intel_crtc->pipe; | |
11933 | ||
11934 | if (!intel_crtc->active) | |
11935 | continue; | |
11936 | ||
11937 | /* planes */ | |
dd740780 | 11938 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11939 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11940 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11941 | ||
11942 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11943 | continue; | |
11944 | ||
11945 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11946 | "(expected (%u,%u), found (%u,%u))\n", | |
11947 | pipe_name(pipe), plane + 1, | |
11948 | sw_entry->start, sw_entry->end, | |
11949 | hw_entry->start, hw_entry->end); | |
11950 | } | |
11951 | ||
11952 | /* cursor */ | |
11953 | hw_entry = &hw_ddb.cursor[pipe]; | |
11954 | sw_entry = &sw_ddb->cursor[pipe]; | |
11955 | ||
11956 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11957 | continue; | |
11958 | ||
11959 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11960 | "(expected (%u,%u), found (%u,%u))\n", | |
11961 | pipe_name(pipe), | |
11962 | sw_entry->start, sw_entry->end, | |
11963 | hw_entry->start, hw_entry->end); | |
11964 | } | |
11965 | } | |
11966 | ||
91d1b4bd DV |
11967 | static void |
11968 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11969 | { |
8af6cf88 DV |
11970 | struct intel_connector *connector; |
11971 | ||
3a3371ff | 11972 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11973 | /* This also checks the encoder/connector hw state with the |
11974 | * ->get_hw_state callbacks. */ | |
11975 | intel_connector_check_state(connector); | |
11976 | ||
e2c719b7 | 11977 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11978 | "connector's staged encoder doesn't match current encoder\n"); |
11979 | } | |
91d1b4bd DV |
11980 | } |
11981 | ||
11982 | static void | |
11983 | check_encoder_state(struct drm_device *dev) | |
11984 | { | |
11985 | struct intel_encoder *encoder; | |
11986 | struct intel_connector *connector; | |
8af6cf88 | 11987 | |
b2784e15 | 11988 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11989 | bool enabled = false; |
11990 | bool active = false; | |
11991 | enum pipe pipe, tracked_pipe; | |
11992 | ||
11993 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11994 | encoder->base.base.id, | |
8e329a03 | 11995 | encoder->base.name); |
8af6cf88 | 11996 | |
e2c719b7 | 11997 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11998 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11999 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
12000 | "encoder's active_connectors set, but no crtc\n"); |
12001 | ||
3a3371ff | 12002 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12003 | if (connector->base.encoder != &encoder->base) |
12004 | continue; | |
12005 | enabled = true; | |
12006 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
12007 | active = true; | |
12008 | } | |
0e32b39c DA |
12009 | /* |
12010 | * for MST connectors if we unplug the connector is gone | |
12011 | * away but the encoder is still connected to a crtc | |
12012 | * until a modeset happens in response to the hotplug. | |
12013 | */ | |
12014 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
12015 | continue; | |
12016 | ||
e2c719b7 | 12017 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12018 | "encoder's enabled state mismatch " |
12019 | "(expected %i, found %i)\n", | |
12020 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 12021 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
12022 | "active encoder with no crtc\n"); |
12023 | ||
e2c719b7 | 12024 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
12025 | "encoder's computed active state doesn't match tracked active state " |
12026 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12027 | ||
12028 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12029 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12030 | "encoder's hw state doesn't match sw tracking " |
12031 | "(expected %i, found %i)\n", | |
12032 | encoder->connectors_active, active); | |
12033 | ||
12034 | if (!encoder->base.crtc) | |
12035 | continue; | |
12036 | ||
12037 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12038 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12039 | "active encoder's pipe doesn't match" |
12040 | "(expected %i, found %i)\n", | |
12041 | tracked_pipe, pipe); | |
12042 | ||
12043 | } | |
91d1b4bd DV |
12044 | } |
12045 | ||
12046 | static void | |
12047 | check_crtc_state(struct drm_device *dev) | |
12048 | { | |
fbee40df | 12049 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12050 | struct intel_crtc *crtc; |
12051 | struct intel_encoder *encoder; | |
5cec258b | 12052 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12053 | |
d3fcc808 | 12054 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12055 | bool enabled = false; |
12056 | bool active = false; | |
12057 | ||
045ac3b5 JB |
12058 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12059 | ||
8af6cf88 DV |
12060 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12061 | crtc->base.base.id); | |
12062 | ||
83d65738 | 12063 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12064 | "active crtc, but not enabled in sw tracking\n"); |
12065 | ||
b2784e15 | 12066 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12067 | if (encoder->base.crtc != &crtc->base) |
12068 | continue; | |
12069 | enabled = true; | |
12070 | if (encoder->connectors_active) | |
12071 | active = true; | |
12072 | } | |
6c49f241 | 12073 | |
e2c719b7 | 12074 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12075 | "crtc's computed active state doesn't match tracked active state " |
12076 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12077 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12078 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12079 | "(expected %i, found %i)\n", enabled, |
12080 | crtc->base.state->enable); | |
8af6cf88 | 12081 | |
0e8ffe1b DV |
12082 | active = dev_priv->display.get_pipe_config(crtc, |
12083 | &pipe_config); | |
d62cf62a | 12084 | |
b6b5d049 VS |
12085 | /* hw state is inconsistent with the pipe quirk */ |
12086 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12087 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12088 | active = crtc->active; |
12089 | ||
b2784e15 | 12090 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12091 | enum pipe pipe; |
6c49f241 DV |
12092 | if (encoder->base.crtc != &crtc->base) |
12093 | continue; | |
1d37b689 | 12094 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12095 | encoder->get_config(encoder, &pipe_config); |
12096 | } | |
12097 | ||
e2c719b7 | 12098 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12099 | "crtc active state doesn't match with hw state " |
12100 | "(expected %i, found %i)\n", crtc->active, active); | |
12101 | ||
c0b03411 | 12102 | if (active && |
6e3c9717 | 12103 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12104 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12105 | intel_dump_pipe_config(crtc, &pipe_config, |
12106 | "[hw state]"); | |
6e3c9717 | 12107 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12108 | "[sw state]"); |
12109 | } | |
8af6cf88 DV |
12110 | } |
12111 | } | |
12112 | ||
91d1b4bd DV |
12113 | static void |
12114 | check_shared_dpll_state(struct drm_device *dev) | |
12115 | { | |
fbee40df | 12116 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12117 | struct intel_crtc *crtc; |
12118 | struct intel_dpll_hw_state dpll_hw_state; | |
12119 | int i; | |
5358901f DV |
12120 | |
12121 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12122 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12123 | int enabled_crtcs = 0, active_crtcs = 0; | |
12124 | bool active; | |
12125 | ||
12126 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12127 | ||
12128 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12129 | ||
12130 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12131 | ||
e2c719b7 | 12132 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12133 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12134 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12135 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12136 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12137 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12138 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12139 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12140 | "pll on state mismatch (expected %i, found %i)\n", |
12141 | pll->on, active); | |
12142 | ||
d3fcc808 | 12143 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12144 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12145 | enabled_crtcs++; |
12146 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12147 | active_crtcs++; | |
12148 | } | |
e2c719b7 | 12149 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12150 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12151 | pll->active, active_crtcs); | |
e2c719b7 | 12152 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12153 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12154 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12155 | |
e2c719b7 | 12156 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12157 | sizeof(dpll_hw_state)), |
12158 | "pll hw state mismatch\n"); | |
5358901f | 12159 | } |
8af6cf88 DV |
12160 | } |
12161 | ||
91d1b4bd DV |
12162 | void |
12163 | intel_modeset_check_state(struct drm_device *dev) | |
12164 | { | |
08db6652 | 12165 | check_wm_state(dev); |
91d1b4bd DV |
12166 | check_connector_state(dev); |
12167 | check_encoder_state(dev); | |
12168 | check_crtc_state(dev); | |
12169 | check_shared_dpll_state(dev); | |
12170 | } | |
12171 | ||
5cec258b | 12172 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12173 | int dotclock) |
12174 | { | |
12175 | /* | |
12176 | * FDI already provided one idea for the dotclock. | |
12177 | * Yell if the encoder disagrees. | |
12178 | */ | |
2d112de7 | 12179 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12180 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12181 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12182 | } |
12183 | ||
80715b2f VS |
12184 | static void update_scanline_offset(struct intel_crtc *crtc) |
12185 | { | |
12186 | struct drm_device *dev = crtc->base.dev; | |
12187 | ||
12188 | /* | |
12189 | * The scanline counter increments at the leading edge of hsync. | |
12190 | * | |
12191 | * On most platforms it starts counting from vtotal-1 on the | |
12192 | * first active line. That means the scanline counter value is | |
12193 | * always one less than what we would expect. Ie. just after | |
12194 | * start of vblank, which also occurs at start of hsync (on the | |
12195 | * last active line), the scanline counter will read vblank_start-1. | |
12196 | * | |
12197 | * On gen2 the scanline counter starts counting from 1 instead | |
12198 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12199 | * to keep the value positive), instead of adding one. | |
12200 | * | |
12201 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12202 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12203 | * there's an extra 1 line difference. So we need to add two instead of | |
12204 | * one to the value. | |
12205 | */ | |
12206 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12207 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12208 | int vtotal; |
12209 | ||
12210 | vtotal = mode->crtc_vtotal; | |
12211 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12212 | vtotal /= 2; | |
12213 | ||
12214 | crtc->scanline_offset = vtotal - 1; | |
12215 | } else if (HAS_DDI(dev) && | |
409ee761 | 12216 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12217 | crtc->scanline_offset = 2; |
12218 | } else | |
12219 | crtc->scanline_offset = 1; | |
12220 | } | |
12221 | ||
5cec258b | 12222 | static struct intel_crtc_state * |
7f27126e | 12223 | intel_modeset_compute_config(struct drm_crtc *crtc, |
0a9ab303 | 12224 | struct drm_atomic_state *state) |
7f27126e | 12225 | { |
548ee15b | 12226 | struct intel_crtc_state *pipe_config; |
0b901879 ACO |
12227 | int ret = 0; |
12228 | ||
12229 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12230 | if (ret) | |
12231 | return ERR_PTR(ret); | |
7f27126e | 12232 | |
8c7b5ccb ACO |
12233 | ret = drm_atomic_helper_check_modeset(state->dev, state); |
12234 | if (ret) | |
12235 | return ERR_PTR(ret); | |
7f27126e | 12236 | |
7f27126e JB |
12237 | /* |
12238 | * Note this needs changes when we start tracking multiple modes | |
12239 | * and crtcs. At that point we'll need to compute the whole config | |
12240 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12241 | * for this crtc. | |
12242 | */ | |
548ee15b ACO |
12243 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
12244 | if (IS_ERR(pipe_config)) | |
12245 | return pipe_config; | |
83a57153 | 12246 | |
4fed33f6 | 12247 | if (!pipe_config->base.enable) |
548ee15b | 12248 | return pipe_config; |
7f27126e | 12249 | |
8c7b5ccb | 12250 | ret = intel_modeset_pipe_config(crtc, state, pipe_config); |
548ee15b ACO |
12251 | if (ret) |
12252 | return ERR_PTR(ret); | |
12253 | ||
8d8c9b51 ACO |
12254 | /* Check things that can only be changed through modeset */ |
12255 | if (pipe_config->has_audio != | |
12256 | to_intel_crtc(crtc)->config->has_audio) | |
12257 | pipe_config->base.mode_changed = true; | |
12258 | ||
12259 | /* | |
12260 | * Note we have an issue here with infoframes: current code | |
12261 | * only updates them on the full mode set path per hw | |
12262 | * requirements. So here we should be checking for any | |
12263 | * required changes and forcing a mode set. | |
12264 | */ | |
12265 | ||
548ee15b | 12266 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); |
db7542dd | 12267 | |
8c7b5ccb ACO |
12268 | ret = drm_atomic_helper_check_planes(state->dev, state); |
12269 | if (ret) | |
12270 | return ERR_PTR(ret); | |
12271 | ||
548ee15b | 12272 | return pipe_config; |
7f27126e JB |
12273 | } |
12274 | ||
0a9ab303 | 12275 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) |
ed6739ef | 12276 | { |
225da59b | 12277 | struct drm_device *dev = state->dev; |
ed6739ef | 12278 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12279 | unsigned clear_pipes = 0; |
ed6739ef | 12280 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12281 | struct intel_crtc_state *intel_crtc_state; |
12282 | struct drm_crtc *crtc; | |
12283 | struct drm_crtc_state *crtc_state; | |
ed6739ef | 12284 | int ret = 0; |
0a9ab303 | 12285 | int i; |
ed6739ef ACO |
12286 | |
12287 | if (!dev_priv->display.crtc_compute_clock) | |
12288 | return 0; | |
12289 | ||
0a9ab303 ACO |
12290 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12291 | intel_crtc = to_intel_crtc(crtc); | |
4978cc93 | 12292 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
0a9ab303 | 12293 | |
4978cc93 | 12294 | if (needs_modeset(crtc_state)) { |
0a9ab303 | 12295 | clear_pipes |= 1 << intel_crtc->pipe; |
4978cc93 | 12296 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
4978cc93 | 12297 | } |
0a9ab303 ACO |
12298 | } |
12299 | ||
ed6739ef ACO |
12300 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); |
12301 | if (ret) | |
12302 | goto done; | |
12303 | ||
0a9ab303 ACO |
12304 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12305 | if (!needs_modeset(crtc_state) || !crtc_state->enable) | |
225da59b ACO |
12306 | continue; |
12307 | ||
0a9ab303 ACO |
12308 | intel_crtc = to_intel_crtc(crtc); |
12309 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
12310 | ||
ed6739ef | 12311 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
0a9ab303 | 12312 | intel_crtc_state); |
ed6739ef ACO |
12313 | if (ret) { |
12314 | intel_shared_dpll_abort_config(dev_priv); | |
12315 | goto done; | |
12316 | } | |
12317 | } | |
12318 | ||
12319 | done: | |
12320 | return ret; | |
12321 | } | |
12322 | ||
054518dd ACO |
12323 | /* Code that should eventually be part of atomic_check() */ |
12324 | static int __intel_set_mode_checks(struct drm_atomic_state *state) | |
12325 | { | |
12326 | struct drm_device *dev = state->dev; | |
12327 | int ret; | |
12328 | ||
12329 | /* | |
12330 | * See if the config requires any additional preparation, e.g. | |
12331 | * to adjust global state with pipes off. We need to do this | |
12332 | * here so we can get the modeset_pipe updated config for the new | |
12333 | * mode set on this crtc. For other crtcs we need to use the | |
12334 | * adjusted_mode bits in the crtc directly. | |
12335 | */ | |
12336 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { | |
12337 | ret = valleyview_modeset_global_pipes(state); | |
12338 | if (ret) | |
12339 | return ret; | |
12340 | } | |
12341 | ||
12342 | ret = __intel_set_mode_setup_plls(state); | |
12343 | if (ret) | |
12344 | return ret; | |
12345 | ||
12346 | return 0; | |
12347 | } | |
12348 | ||
0a9ab303 | 12349 | static int __intel_set_mode(struct drm_crtc *modeset_crtc, |
0a9ab303 | 12350 | struct intel_crtc_state *pipe_config) |
a6778b3c | 12351 | { |
0a9ab303 | 12352 | struct drm_device *dev = modeset_crtc->dev; |
fbee40df | 12353 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 | 12354 | struct drm_atomic_state *state = pipe_config->base.state; |
0a9ab303 ACO |
12355 | struct drm_crtc *crtc; |
12356 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 12357 | int ret = 0; |
0a9ab303 | 12358 | int i; |
a6778b3c | 12359 | |
054518dd ACO |
12360 | ret = __intel_set_mode_checks(state); |
12361 | if (ret < 0) | |
12362 | return ret; | |
12363 | ||
d4afb8cc ACO |
12364 | ret = drm_atomic_helper_prepare_planes(dev, state); |
12365 | if (ret) | |
12366 | return ret; | |
12367 | ||
0a9ab303 ACO |
12368 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12369 | if (!needs_modeset(crtc_state)) | |
12370 | continue; | |
460da916 | 12371 | |
0a9ab303 ACO |
12372 | if (!crtc_state->enable) { |
12373 | intel_crtc_disable(crtc); | |
12374 | } else if (crtc->state->enable) { | |
12375 | intel_crtc_disable_planes(crtc); | |
12376 | dev_priv->display.crtc_disable(crtc); | |
ce22dba9 | 12377 | } |
ea9d758d | 12378 | } |
a6778b3c | 12379 | |
6c4c86f5 DV |
12380 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12381 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12382 | * |
12383 | * Note we'll need to fix this up when we start tracking multiple | |
12384 | * pipes; here we assume a single modeset_pipe and only track the | |
12385 | * single crtc and mode. | |
f6e5b160 | 12386 | */ |
0a9ab303 | 12387 | if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { |
8c7b5ccb | 12388 | modeset_crtc->mode = pipe_config->base.mode; |
c326c0a9 VS |
12389 | |
12390 | /* | |
12391 | * Calculate and store various constants which | |
12392 | * are later needed by vblank and swap-completion | |
12393 | * timestamping. They are derived from true hwmode. | |
12394 | */ | |
0a9ab303 | 12395 | drm_calc_timestamping_constants(modeset_crtc, |
2d112de7 | 12396 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12397 | } |
7758a113 | 12398 | |
ea9d758d DV |
12399 | /* Only after disabling all output pipelines that will be changed can we |
12400 | * update the the output configuration. */ | |
0a9ab303 | 12401 | intel_modeset_update_state(state); |
f6e5b160 | 12402 | |
a821fc46 ACO |
12403 | /* The state has been swaped above, so state actually contains the |
12404 | * old state now. */ | |
12405 | ||
304603f4 | 12406 | modeset_update_crtc_power_domains(state); |
47fab737 | 12407 | |
d4afb8cc | 12408 | drm_atomic_helper_commit_planes(dev, state); |
a6778b3c DV |
12409 | |
12410 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
0a9ab303 | 12411 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a821fc46 | 12412 | if (!needs_modeset(crtc->state) || !crtc->state->enable) |
0a9ab303 ACO |
12413 | continue; |
12414 | ||
12415 | update_scanline_offset(to_intel_crtc(crtc)); | |
80715b2f | 12416 | |
0a9ab303 ACO |
12417 | dev_priv->display.crtc_enable(crtc); |
12418 | intel_crtc_enable_planes(crtc); | |
80715b2f | 12419 | } |
a6778b3c | 12420 | |
a6778b3c | 12421 | /* FIXME: add subpixel order */ |
83a57153 | 12422 | |
d4afb8cc ACO |
12423 | drm_atomic_helper_cleanup_planes(dev, state); |
12424 | ||
2bfb4627 ACO |
12425 | drm_atomic_state_free(state); |
12426 | ||
9eb45f22 | 12427 | return 0; |
f6e5b160 CW |
12428 | } |
12429 | ||
0a9ab303 | 12430 | static int intel_set_mode_with_config(struct drm_crtc *crtc, |
0a9ab303 | 12431 | struct intel_crtc_state *pipe_config) |
f30da187 DV |
12432 | { |
12433 | int ret; | |
12434 | ||
8c7b5ccb | 12435 | ret = __intel_set_mode(crtc, pipe_config); |
f30da187 DV |
12436 | |
12437 | if (ret == 0) | |
12438 | intel_modeset_check_state(crtc->dev); | |
12439 | ||
12440 | return ret; | |
12441 | } | |
12442 | ||
7f27126e | 12443 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 12444 | struct drm_atomic_state *state) |
7f27126e | 12445 | { |
5cec258b | 12446 | struct intel_crtc_state *pipe_config; |
83a57153 | 12447 | int ret = 0; |
7f27126e | 12448 | |
8c7b5ccb | 12449 | pipe_config = intel_modeset_compute_config(crtc, state); |
83a57153 ACO |
12450 | if (IS_ERR(pipe_config)) { |
12451 | ret = PTR_ERR(pipe_config); | |
12452 | goto out; | |
12453 | } | |
12454 | ||
8c7b5ccb | 12455 | ret = intel_set_mode_with_config(crtc, pipe_config); |
83a57153 ACO |
12456 | if (ret) |
12457 | goto out; | |
7f27126e | 12458 | |
83a57153 ACO |
12459 | out: |
12460 | return ret; | |
7f27126e JB |
12461 | } |
12462 | ||
c0c36b94 CW |
12463 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12464 | { | |
83a57153 ACO |
12465 | struct drm_device *dev = crtc->dev; |
12466 | struct drm_atomic_state *state; | |
4be07317 | 12467 | struct intel_crtc *intel_crtc; |
83a57153 ACO |
12468 | struct intel_encoder *encoder; |
12469 | struct intel_connector *connector; | |
12470 | struct drm_connector_state *connector_state; | |
4be07317 | 12471 | struct intel_crtc_state *crtc_state; |
2bfb4627 | 12472 | int ret; |
83a57153 ACO |
12473 | |
12474 | state = drm_atomic_state_alloc(dev); | |
12475 | if (!state) { | |
12476 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12477 | crtc->base.id); | |
12478 | return; | |
12479 | } | |
12480 | ||
12481 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12482 | ||
12483 | /* The force restore path in the HW readout code relies on the staged | |
12484 | * config still keeping the user requested config while the actual | |
12485 | * state has been overwritten by the configuration read from HW. We | |
12486 | * need to copy the staged config to the atomic state, otherwise the | |
12487 | * mode set will just reapply the state the HW is already in. */ | |
12488 | for_each_intel_encoder(dev, encoder) { | |
12489 | if (&encoder->new_crtc->base != crtc) | |
12490 | continue; | |
12491 | ||
12492 | for_each_intel_connector(dev, connector) { | |
12493 | if (connector->new_encoder != encoder) | |
12494 | continue; | |
12495 | ||
12496 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12497 | if (IS_ERR(connector_state)) { | |
12498 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12499 | connector->base.base.id, | |
12500 | connector->base.name, | |
12501 | PTR_ERR(connector_state)); | |
12502 | continue; | |
12503 | } | |
12504 | ||
12505 | connector_state->crtc = crtc; | |
12506 | connector_state->best_encoder = &encoder->base; | |
12507 | } | |
12508 | } | |
12509 | ||
4be07317 ACO |
12510 | for_each_intel_crtc(dev, intel_crtc) { |
12511 | if (intel_crtc->new_enabled == intel_crtc->base.enabled) | |
12512 | continue; | |
12513 | ||
12514 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
12515 | if (IS_ERR(crtc_state)) { | |
12516 | DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", | |
12517 | intel_crtc->base.base.id, | |
12518 | PTR_ERR(crtc_state)); | |
12519 | continue; | |
12520 | } | |
12521 | ||
49d6fa21 ML |
12522 | crtc_state->base.active = crtc_state->base.enable = |
12523 | intel_crtc->new_enabled; | |
8c7b5ccb ACO |
12524 | |
12525 | if (&intel_crtc->base == crtc) | |
12526 | drm_mode_copy(&crtc_state->base.mode, &crtc->mode); | |
4be07317 ACO |
12527 | } |
12528 | ||
d3a40d1b ACO |
12529 | intel_modeset_setup_plane_state(state, crtc, &crtc->mode, |
12530 | crtc->primary->fb, crtc->x, crtc->y); | |
12531 | ||
2bfb4627 ACO |
12532 | ret = intel_set_mode(crtc, state); |
12533 | if (ret) | |
12534 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12535 | } |
12536 | ||
25c5b266 DV |
12537 | #undef for_each_intel_crtc_masked |
12538 | ||
b7885264 ACO |
12539 | static bool intel_connector_in_mode_set(struct intel_connector *connector, |
12540 | struct drm_mode_set *set) | |
12541 | { | |
12542 | int ro; | |
12543 | ||
12544 | for (ro = 0; ro < set->num_connectors; ro++) | |
12545 | if (set->connectors[ro] == &connector->base) | |
12546 | return true; | |
12547 | ||
12548 | return false; | |
12549 | } | |
12550 | ||
2e431051 | 12551 | static int |
9a935856 DV |
12552 | intel_modeset_stage_output_state(struct drm_device *dev, |
12553 | struct drm_mode_set *set, | |
944b0c76 | 12554 | struct drm_atomic_state *state) |
50f56119 | 12555 | { |
9a935856 | 12556 | struct intel_connector *connector; |
d5432a9d | 12557 | struct drm_connector *drm_connector; |
944b0c76 | 12558 | struct drm_connector_state *connector_state; |
d5432a9d ACO |
12559 | struct drm_crtc *crtc; |
12560 | struct drm_crtc_state *crtc_state; | |
12561 | int i, ret; | |
50f56119 | 12562 | |
9abdda74 | 12563 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12564 | * of connectors. For paranoia, double-check this. */ |
12565 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12566 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12567 | ||
3a3371ff | 12568 | for_each_intel_connector(dev, connector) { |
b7885264 ACO |
12569 | bool in_mode_set = intel_connector_in_mode_set(connector, set); |
12570 | ||
d5432a9d ACO |
12571 | if (!in_mode_set && connector->base.state->crtc != set->crtc) |
12572 | continue; | |
12573 | ||
12574 | connector_state = | |
12575 | drm_atomic_get_connector_state(state, &connector->base); | |
12576 | if (IS_ERR(connector_state)) | |
12577 | return PTR_ERR(connector_state); | |
12578 | ||
b7885264 ACO |
12579 | if (in_mode_set) { |
12580 | int pipe = to_intel_crtc(set->crtc)->pipe; | |
d5432a9d ACO |
12581 | connector_state->best_encoder = |
12582 | &intel_find_encoder(connector, pipe)->base; | |
50f56119 DV |
12583 | } |
12584 | ||
d5432a9d | 12585 | if (connector->base.state->crtc != set->crtc) |
b7885264 ACO |
12586 | continue; |
12587 | ||
9a935856 DV |
12588 | /* If we disable the crtc, disable all its connectors. Also, if |
12589 | * the connector is on the changing crtc but not on the new | |
12590 | * connector list, disable it. */ | |
b7885264 | 12591 | if (!set->fb || !in_mode_set) { |
d5432a9d | 12592 | connector_state->best_encoder = NULL; |
9a935856 DV |
12593 | |
12594 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12595 | connector->base.base.id, | |
c23cc417 | 12596 | connector->base.name); |
9a935856 | 12597 | } |
50f56119 | 12598 | } |
9a935856 | 12599 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12600 | |
d5432a9d ACO |
12601 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
12602 | connector = to_intel_connector(drm_connector); | |
12603 | ||
12604 | if (!connector_state->best_encoder) { | |
12605 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
12606 | NULL); | |
12607 | if (ret) | |
12608 | return ret; | |
7668851f | 12609 | |
50f56119 | 12610 | continue; |
d5432a9d | 12611 | } |
50f56119 | 12612 | |
d5432a9d ACO |
12613 | if (intel_connector_in_mode_set(connector, set)) { |
12614 | struct drm_crtc *crtc = connector->base.state->crtc; | |
12615 | ||
12616 | /* If this connector was in a previous crtc, add it | |
12617 | * to the state. We might need to disable it. */ | |
12618 | if (crtc) { | |
12619 | crtc_state = | |
12620 | drm_atomic_get_crtc_state(state, crtc); | |
12621 | if (IS_ERR(crtc_state)) | |
12622 | return PTR_ERR(crtc_state); | |
12623 | } | |
12624 | ||
12625 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
12626 | set->crtc); | |
12627 | if (ret) | |
12628 | return ret; | |
12629 | } | |
50f56119 DV |
12630 | |
12631 | /* Make sure the new CRTC will work with the encoder */ | |
d5432a9d ACO |
12632 | if (!drm_encoder_crtc_ok(connector_state->best_encoder, |
12633 | connector_state->crtc)) { | |
5e2b584e | 12634 | return -EINVAL; |
50f56119 | 12635 | } |
944b0c76 | 12636 | |
9a935856 DV |
12637 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12638 | connector->base.base.id, | |
c23cc417 | 12639 | connector->base.name, |
d5432a9d | 12640 | connector_state->crtc->base.id); |
944b0c76 | 12641 | |
d5432a9d ACO |
12642 | if (connector_state->best_encoder != &connector->encoder->base) |
12643 | connector->encoder = | |
12644 | to_intel_encoder(connector_state->best_encoder); | |
0e32b39c | 12645 | } |
7668851f | 12646 | |
d5432a9d | 12647 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
49d6fa21 ML |
12648 | bool has_connectors; |
12649 | ||
d5432a9d ACO |
12650 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12651 | if (ret) | |
12652 | return ret; | |
4be07317 | 12653 | |
49d6fa21 ML |
12654 | has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc); |
12655 | if (has_connectors != crtc_state->enable) | |
12656 | crtc_state->enable = | |
12657 | crtc_state->active = has_connectors; | |
7668851f VS |
12658 | } |
12659 | ||
8c7b5ccb ACO |
12660 | ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, |
12661 | set->fb, set->x, set->y); | |
12662 | if (ret) | |
12663 | return ret; | |
12664 | ||
12665 | crtc_state = drm_atomic_get_crtc_state(state, set->crtc); | |
12666 | if (IS_ERR(crtc_state)) | |
12667 | return PTR_ERR(crtc_state); | |
12668 | ||
12669 | if (set->mode) | |
12670 | drm_mode_copy(&crtc_state->mode, set->mode); | |
12671 | ||
12672 | if (set->num_connectors) | |
12673 | crtc_state->active = true; | |
12674 | ||
2e431051 DV |
12675 | return 0; |
12676 | } | |
12677 | ||
bb546623 ACO |
12678 | static bool primary_plane_visible(struct drm_crtc *crtc) |
12679 | { | |
12680 | struct intel_plane_state *plane_state = | |
12681 | to_intel_plane_state(crtc->primary->state); | |
12682 | ||
12683 | return plane_state->visible; | |
12684 | } | |
12685 | ||
2e431051 DV |
12686 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12687 | { | |
12688 | struct drm_device *dev; | |
83a57153 | 12689 | struct drm_atomic_state *state = NULL; |
5cec258b | 12690 | struct intel_crtc_state *pipe_config; |
bb546623 | 12691 | bool primary_plane_was_visible; |
2e431051 | 12692 | int ret; |
2e431051 | 12693 | |
8d3e375e DV |
12694 | BUG_ON(!set); |
12695 | BUG_ON(!set->crtc); | |
12696 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12697 | |
7e53f3a4 DV |
12698 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12699 | BUG_ON(!set->mode && set->fb); | |
12700 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12701 | |
2e431051 DV |
12702 | if (set->fb) { |
12703 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12704 | set->crtc->base.id, set->fb->base.id, | |
12705 | (int)set->num_connectors, set->x, set->y); | |
12706 | } else { | |
12707 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12708 | } |
12709 | ||
12710 | dev = set->crtc->dev; | |
12711 | ||
83a57153 | 12712 | state = drm_atomic_state_alloc(dev); |
7cbf41d6 ACO |
12713 | if (!state) |
12714 | return -ENOMEM; | |
83a57153 ACO |
12715 | |
12716 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12717 | ||
462a425a | 12718 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 | 12719 | if (ret) |
7cbf41d6 | 12720 | goto out; |
2e431051 | 12721 | |
8c7b5ccb | 12722 | pipe_config = intel_modeset_compute_config(set->crtc, state); |
20664591 | 12723 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12724 | ret = PTR_ERR(pipe_config); |
7cbf41d6 | 12725 | goto out; |
20664591 | 12726 | } |
50f52756 | 12727 | |
1f9954d0 JB |
12728 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12729 | ||
bb546623 ACO |
12730 | primary_plane_was_visible = primary_plane_visible(set->crtc); |
12731 | ||
8c7b5ccb | 12732 | ret = intel_set_mode_with_config(set->crtc, pipe_config); |
bb546623 ACO |
12733 | |
12734 | if (ret == 0 && | |
12735 | pipe_config->base.enable && | |
12736 | pipe_config->base.planes_changed && | |
12737 | !needs_modeset(&pipe_config->base)) { | |
3b150f08 | 12738 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
3b150f08 MR |
12739 | |
12740 | /* | |
12741 | * We need to make sure the primary plane is re-enabled if it | |
12742 | * has previously been turned off. | |
12743 | */ | |
bb546623 ACO |
12744 | if (ret == 0 && !primary_plane_was_visible && |
12745 | primary_plane_visible(set->crtc)) { | |
3b150f08 | 12746 | WARN_ON(!intel_crtc->active); |
87d4300a | 12747 | intel_post_enable_primary(set->crtc); |
3b150f08 MR |
12748 | } |
12749 | ||
7ca51a3a JB |
12750 | /* |
12751 | * In the fastboot case this may be our only check of the | |
12752 | * state after boot. It would be better to only do it on | |
12753 | * the first update, but we don't have a nice way of doing that | |
12754 | * (and really, set_config isn't used much for high freq page | |
12755 | * flipping, so increasing its cost here shouldn't be a big | |
12756 | * deal). | |
12757 | */ | |
d330a953 | 12758 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12759 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12760 | } |
12761 | ||
2d05eae1 | 12762 | if (ret) { |
bf67dfeb DV |
12763 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12764 | set->crtc->base.id, ret); | |
2d05eae1 | 12765 | } |
50f56119 | 12766 | |
7cbf41d6 | 12767 | out: |
2bfb4627 ACO |
12768 | if (ret) |
12769 | drm_atomic_state_free(state); | |
50f56119 DV |
12770 | return ret; |
12771 | } | |
f6e5b160 CW |
12772 | |
12773 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12774 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12775 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12776 | .destroy = intel_crtc_destroy, |
12777 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12778 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12779 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12780 | }; |
12781 | ||
5358901f DV |
12782 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12783 | struct intel_shared_dpll *pll, | |
12784 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12785 | { |
5358901f | 12786 | uint32_t val; |
ee7b9f93 | 12787 | |
f458ebbc | 12788 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12789 | return false; |
12790 | ||
5358901f | 12791 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12792 | hw_state->dpll = val; |
12793 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12794 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12795 | |
12796 | return val & DPLL_VCO_ENABLE; | |
12797 | } | |
12798 | ||
15bdd4cf DV |
12799 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12800 | struct intel_shared_dpll *pll) | |
12801 | { | |
3e369b76 ACO |
12802 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12803 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12804 | } |
12805 | ||
e7b903d2 DV |
12806 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12807 | struct intel_shared_dpll *pll) | |
12808 | { | |
e7b903d2 | 12809 | /* PCH refclock must be enabled first */ |
89eff4be | 12810 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12811 | |
3e369b76 | 12812 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12813 | |
12814 | /* Wait for the clocks to stabilize. */ | |
12815 | POSTING_READ(PCH_DPLL(pll->id)); | |
12816 | udelay(150); | |
12817 | ||
12818 | /* The pixel multiplier can only be updated once the | |
12819 | * DPLL is enabled and the clocks are stable. | |
12820 | * | |
12821 | * So write it again. | |
12822 | */ | |
3e369b76 | 12823 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12824 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12825 | udelay(200); |
12826 | } | |
12827 | ||
12828 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12829 | struct intel_shared_dpll *pll) | |
12830 | { | |
12831 | struct drm_device *dev = dev_priv->dev; | |
12832 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12833 | |
12834 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12835 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12836 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12837 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12838 | } |
12839 | ||
15bdd4cf DV |
12840 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12841 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12842 | udelay(200); |
12843 | } | |
12844 | ||
46edb027 DV |
12845 | static char *ibx_pch_dpll_names[] = { |
12846 | "PCH DPLL A", | |
12847 | "PCH DPLL B", | |
12848 | }; | |
12849 | ||
7c74ade1 | 12850 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12851 | { |
e7b903d2 | 12852 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12853 | int i; |
12854 | ||
7c74ade1 | 12855 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12856 | |
e72f9fbf | 12857 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12858 | dev_priv->shared_dplls[i].id = i; |
12859 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12860 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12861 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12862 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12863 | dev_priv->shared_dplls[i].get_hw_state = |
12864 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12865 | } |
12866 | } | |
12867 | ||
7c74ade1 DV |
12868 | static void intel_shared_dpll_init(struct drm_device *dev) |
12869 | { | |
e7b903d2 | 12870 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12871 | |
9cd86933 DV |
12872 | if (HAS_DDI(dev)) |
12873 | intel_ddi_pll_init(dev); | |
12874 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12875 | ibx_pch_dpll_init(dev); |
12876 | else | |
12877 | dev_priv->num_shared_dpll = 0; | |
12878 | ||
12879 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12880 | } |
12881 | ||
1fc0a8f7 TU |
12882 | /** |
12883 | * intel_wm_need_update - Check whether watermarks need updating | |
12884 | * @plane: drm plane | |
12885 | * @state: new plane state | |
12886 | * | |
12887 | * Check current plane state versus the new one to determine whether | |
12888 | * watermarks need to be recalculated. | |
12889 | * | |
12890 | * Returns true or false. | |
12891 | */ | |
12892 | bool intel_wm_need_update(struct drm_plane *plane, | |
12893 | struct drm_plane_state *state) | |
12894 | { | |
12895 | /* Update watermarks on tiling changes. */ | |
12896 | if (!plane->state->fb || !state->fb || | |
12897 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12898 | plane->state->rotation != state->rotation) | |
12899 | return true; | |
12900 | ||
12901 | return false; | |
12902 | } | |
12903 | ||
6beb8c23 MR |
12904 | /** |
12905 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12906 | * @plane: drm plane to prepare for | |
12907 | * @fb: framebuffer to prepare for presentation | |
12908 | * | |
12909 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12910 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12911 | * bits. Some older platforms need special physical address handling for | |
12912 | * cursor planes. | |
12913 | * | |
12914 | * Returns 0 on success, negative error code on failure. | |
12915 | */ | |
12916 | int | |
12917 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12918 | struct drm_framebuffer *fb, |
12919 | const struct drm_plane_state *new_state) | |
465c120c MR |
12920 | { |
12921 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12922 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12923 | enum pipe pipe = intel_plane->pipe; | |
12924 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12925 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12926 | unsigned frontbuffer_bits = 0; | |
12927 | int ret = 0; | |
465c120c | 12928 | |
ea2c67bb | 12929 | if (!obj) |
465c120c MR |
12930 | return 0; |
12931 | ||
6beb8c23 MR |
12932 | switch (plane->type) { |
12933 | case DRM_PLANE_TYPE_PRIMARY: | |
12934 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12935 | break; | |
12936 | case DRM_PLANE_TYPE_CURSOR: | |
12937 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12938 | break; | |
12939 | case DRM_PLANE_TYPE_OVERLAY: | |
12940 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12941 | break; | |
12942 | } | |
465c120c | 12943 | |
6beb8c23 | 12944 | mutex_lock(&dev->struct_mutex); |
465c120c | 12945 | |
6beb8c23 MR |
12946 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12947 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12948 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12949 | ret = i915_gem_object_attach_phys(obj, align); | |
12950 | if (ret) | |
12951 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12952 | } else { | |
82bc3b2d | 12953 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12954 | } |
465c120c | 12955 | |
6beb8c23 MR |
12956 | if (ret == 0) |
12957 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12958 | |
4c34574f | 12959 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12960 | |
6beb8c23 MR |
12961 | return ret; |
12962 | } | |
12963 | ||
38f3ce3a MR |
12964 | /** |
12965 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12966 | * @plane: drm plane to clean up for | |
12967 | * @fb: old framebuffer that was on plane | |
12968 | * | |
12969 | * Cleans up a framebuffer that has just been removed from a plane. | |
12970 | */ | |
12971 | void | |
12972 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12973 | struct drm_framebuffer *fb, |
12974 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12975 | { |
12976 | struct drm_device *dev = plane->dev; | |
12977 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12978 | ||
12979 | if (WARN_ON(!obj)) | |
12980 | return; | |
12981 | ||
12982 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12983 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12984 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12985 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12986 | mutex_unlock(&dev->struct_mutex); |
12987 | } | |
465c120c MR |
12988 | } |
12989 | ||
6156a456 CK |
12990 | int |
12991 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12992 | { | |
12993 | int max_scale; | |
12994 | struct drm_device *dev; | |
12995 | struct drm_i915_private *dev_priv; | |
12996 | int crtc_clock, cdclk; | |
12997 | ||
12998 | if (!intel_crtc || !crtc_state) | |
12999 | return DRM_PLANE_HELPER_NO_SCALING; | |
13000 | ||
13001 | dev = intel_crtc->base.dev; | |
13002 | dev_priv = dev->dev_private; | |
13003 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13004 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
13005 | ||
13006 | if (!crtc_clock || !cdclk) | |
13007 | return DRM_PLANE_HELPER_NO_SCALING; | |
13008 | ||
13009 | /* | |
13010 | * skl max scale is lower of: | |
13011 | * close to 3 but not 3, -1 is for that purpose | |
13012 | * or | |
13013 | * cdclk/crtc_clock | |
13014 | */ | |
13015 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13016 | ||
13017 | return max_scale; | |
13018 | } | |
13019 | ||
465c120c | 13020 | static int |
3c692a41 GP |
13021 | intel_check_primary_plane(struct drm_plane *plane, |
13022 | struct intel_plane_state *state) | |
13023 | { | |
32b7eeec MR |
13024 | struct drm_device *dev = plane->dev; |
13025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13026 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13027 | struct intel_crtc *intel_crtc; |
6156a456 | 13028 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13029 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13030 | struct drm_rect *dest = &state->dst; |
13031 | struct drm_rect *src = &state->src; | |
13032 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13033 | bool can_position = false; |
6156a456 CK |
13034 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13035 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13036 | int ret; |
13037 | ||
ea2c67bb MR |
13038 | crtc = crtc ? crtc : plane->crtc; |
13039 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13040 | crtc_state = state->base.state ? |
13041 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13042 | |
6156a456 CK |
13043 | if (INTEL_INFO(dev)->gen >= 9) { |
13044 | min_scale = 1; | |
13045 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
d8106366 | 13046 | can_position = true; |
6156a456 | 13047 | } |
d8106366 | 13048 | |
c59cb179 MR |
13049 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13050 | src, dest, clip, | |
6156a456 CK |
13051 | min_scale, |
13052 | max_scale, | |
d8106366 SJ |
13053 | can_position, true, |
13054 | &state->visible); | |
c59cb179 MR |
13055 | if (ret) |
13056 | return ret; | |
465c120c | 13057 | |
32b7eeec | 13058 | if (intel_crtc->active) { |
b70709a6 ML |
13059 | struct intel_plane_state *old_state = |
13060 | to_intel_plane_state(plane->state); | |
13061 | ||
32b7eeec MR |
13062 | intel_crtc->atomic.wait_for_flips = true; |
13063 | ||
13064 | /* | |
13065 | * FBC does not work on some platforms for rotated | |
13066 | * planes, so disable it when rotation is not 0 and | |
13067 | * update it when rotation is set back to 0. | |
13068 | * | |
13069 | * FIXME: This is redundant with the fbc update done in | |
13070 | * the primary plane enable function except that that | |
13071 | * one is done too late. We eventually need to unify | |
13072 | * this. | |
13073 | */ | |
b70709a6 | 13074 | if (state->visible && |
32b7eeec | 13075 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13076 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13077 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13078 | intel_crtc->atomic.disable_fbc = true; |
13079 | } | |
13080 | ||
b70709a6 | 13081 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13082 | /* |
13083 | * BDW signals flip done immediately if the plane | |
13084 | * is disabled, even if the plane enable is already | |
13085 | * armed to occur at the next vblank :( | |
13086 | */ | |
b70709a6 | 13087 | if (IS_BROADWELL(dev)) |
32b7eeec MR |
13088 | intel_crtc->atomic.wait_vblank = true; |
13089 | } | |
13090 | ||
13091 | intel_crtc->atomic.fb_bits |= | |
13092 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13093 | ||
13094 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13095 | |
1fc0a8f7 | 13096 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13097 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13098 | } |
13099 | ||
6156a456 CK |
13100 | if (INTEL_INFO(dev)->gen >= 9) { |
13101 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13102 | to_intel_plane(plane), state, 0); | |
13103 | if (ret) | |
13104 | return ret; | |
13105 | } | |
13106 | ||
14af293f GP |
13107 | return 0; |
13108 | } | |
13109 | ||
13110 | static void | |
13111 | intel_commit_primary_plane(struct drm_plane *plane, | |
13112 | struct intel_plane_state *state) | |
13113 | { | |
2b875c22 MR |
13114 | struct drm_crtc *crtc = state->base.crtc; |
13115 | struct drm_framebuffer *fb = state->base.fb; | |
13116 | struct drm_device *dev = plane->dev; | |
14af293f | 13117 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13118 | struct intel_crtc *intel_crtc; |
14af293f GP |
13119 | struct drm_rect *src = &state->src; |
13120 | ||
ea2c67bb MR |
13121 | crtc = crtc ? crtc : plane->crtc; |
13122 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13123 | |
13124 | plane->fb = fb; | |
9dc806fc MR |
13125 | crtc->x = src->x1 >> 16; |
13126 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13127 | |
ccc759dc | 13128 | if (intel_crtc->active) { |
27321ae8 | 13129 | if (state->visible) |
ccc759dc GP |
13130 | /* FIXME: kill this fastboot hack */ |
13131 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13132 | |
27321ae8 ML |
13133 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13134 | crtc->x, crtc->y); | |
ccc759dc | 13135 | } |
465c120c MR |
13136 | } |
13137 | ||
a8ad0d8e ML |
13138 | static void |
13139 | intel_disable_primary_plane(struct drm_plane *plane, | |
13140 | struct drm_crtc *crtc, | |
13141 | bool force) | |
13142 | { | |
13143 | struct drm_device *dev = plane->dev; | |
13144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13145 | ||
a8ad0d8e ML |
13146 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13147 | } | |
13148 | ||
32b7eeec | 13149 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13150 | { |
32b7eeec | 13151 | struct drm_device *dev = crtc->dev; |
140fd38d | 13152 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13154 | struct intel_plane *intel_plane; |
13155 | struct drm_plane *p; | |
13156 | unsigned fb_bits = 0; | |
13157 | ||
13158 | /* Track fb's for any planes being disabled */ | |
13159 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13160 | intel_plane = to_intel_plane(p); | |
13161 | ||
13162 | if (intel_crtc->atomic.disabled_planes & | |
13163 | (1 << drm_plane_index(p))) { | |
13164 | switch (p->type) { | |
13165 | case DRM_PLANE_TYPE_PRIMARY: | |
13166 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13167 | break; | |
13168 | case DRM_PLANE_TYPE_CURSOR: | |
13169 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13170 | break; | |
13171 | case DRM_PLANE_TYPE_OVERLAY: | |
13172 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13173 | break; | |
13174 | } | |
3c692a41 | 13175 | |
ea2c67bb MR |
13176 | mutex_lock(&dev->struct_mutex); |
13177 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13178 | mutex_unlock(&dev->struct_mutex); | |
13179 | } | |
13180 | } | |
3c692a41 | 13181 | |
32b7eeec MR |
13182 | if (intel_crtc->atomic.wait_for_flips) |
13183 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13184 | |
32b7eeec MR |
13185 | if (intel_crtc->atomic.disable_fbc) |
13186 | intel_fbc_disable(dev); | |
3c692a41 | 13187 | |
32b7eeec MR |
13188 | if (intel_crtc->atomic.pre_disable_primary) |
13189 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13190 | |
32b7eeec MR |
13191 | if (intel_crtc->atomic.update_wm) |
13192 | intel_update_watermarks(crtc); | |
3c692a41 | 13193 | |
32b7eeec | 13194 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13195 | |
c34c9ee4 MR |
13196 | /* Perform vblank evasion around commit operation */ |
13197 | if (intel_crtc->active) | |
13198 | intel_crtc->atomic.evade = | |
13199 | intel_pipe_update_start(intel_crtc, | |
13200 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13201 | } |
13202 | ||
13203 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13204 | { | |
13205 | struct drm_device *dev = crtc->dev; | |
13206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13208 | struct drm_plane *p; | |
13209 | ||
c34c9ee4 MR |
13210 | if (intel_crtc->atomic.evade) |
13211 | intel_pipe_update_end(intel_crtc, | |
13212 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13213 | |
140fd38d | 13214 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13215 | |
32b7eeec MR |
13216 | if (intel_crtc->atomic.wait_vblank) |
13217 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13218 | ||
13219 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13220 | ||
13221 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13222 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13223 | intel_fbc_update(dev); |
ccc759dc | 13224 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13225 | } |
3c692a41 | 13226 | |
32b7eeec MR |
13227 | if (intel_crtc->atomic.post_enable_primary) |
13228 | intel_post_enable_primary(crtc); | |
3c692a41 | 13229 | |
32b7eeec MR |
13230 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13231 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13232 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13233 | false, false); | |
13234 | ||
13235 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13236 | } |
13237 | ||
cf4c7c12 | 13238 | /** |
4a3b8769 MR |
13239 | * intel_plane_destroy - destroy a plane |
13240 | * @plane: plane to destroy | |
cf4c7c12 | 13241 | * |
4a3b8769 MR |
13242 | * Common destruction function for all types of planes (primary, cursor, |
13243 | * sprite). | |
cf4c7c12 | 13244 | */ |
4a3b8769 | 13245 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13246 | { |
13247 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13248 | drm_plane_cleanup(plane); | |
13249 | kfree(intel_plane); | |
13250 | } | |
13251 | ||
65a3fea0 | 13252 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13253 | .update_plane = drm_atomic_helper_update_plane, |
13254 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13255 | .destroy = intel_plane_destroy, |
c196e1d6 | 13256 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13257 | .atomic_get_property = intel_plane_atomic_get_property, |
13258 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13259 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13260 | .atomic_destroy_state = intel_plane_destroy_state, | |
13261 | ||
465c120c MR |
13262 | }; |
13263 | ||
13264 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13265 | int pipe) | |
13266 | { | |
13267 | struct intel_plane *primary; | |
8e7d688b | 13268 | struct intel_plane_state *state; |
465c120c MR |
13269 | const uint32_t *intel_primary_formats; |
13270 | int num_formats; | |
13271 | ||
13272 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13273 | if (primary == NULL) | |
13274 | return NULL; | |
13275 | ||
8e7d688b MR |
13276 | state = intel_create_plane_state(&primary->base); |
13277 | if (!state) { | |
ea2c67bb MR |
13278 | kfree(primary); |
13279 | return NULL; | |
13280 | } | |
8e7d688b | 13281 | primary->base.state = &state->base; |
ea2c67bb | 13282 | |
465c120c MR |
13283 | primary->can_scale = false; |
13284 | primary->max_downscale = 1; | |
6156a456 CK |
13285 | if (INTEL_INFO(dev)->gen >= 9) { |
13286 | primary->can_scale = true; | |
af99ceda | 13287 | state->scaler_id = -1; |
6156a456 | 13288 | } |
465c120c MR |
13289 | primary->pipe = pipe; |
13290 | primary->plane = pipe; | |
c59cb179 MR |
13291 | primary->check_plane = intel_check_primary_plane; |
13292 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13293 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13294 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13295 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13296 | primary->plane = !pipe; | |
13297 | ||
13298 | if (INTEL_INFO(dev)->gen <= 3) { | |
568db4f2 DL |
13299 | intel_primary_formats = i8xx_primary_formats; |
13300 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c | 13301 | } else { |
568db4f2 DL |
13302 | intel_primary_formats = i965_primary_formats; |
13303 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
465c120c MR |
13304 | } |
13305 | ||
13306 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13307 | &intel_plane_funcs, |
465c120c MR |
13308 | intel_primary_formats, num_formats, |
13309 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13310 | |
3b7a5119 SJ |
13311 | if (INTEL_INFO(dev)->gen >= 4) |
13312 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13313 | |
ea2c67bb MR |
13314 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13315 | ||
465c120c MR |
13316 | return &primary->base; |
13317 | } | |
13318 | ||
3b7a5119 SJ |
13319 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13320 | { | |
13321 | if (!dev->mode_config.rotation_property) { | |
13322 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13323 | BIT(DRM_ROTATE_180); | |
13324 | ||
13325 | if (INTEL_INFO(dev)->gen >= 9) | |
13326 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13327 | ||
13328 | dev->mode_config.rotation_property = | |
13329 | drm_mode_create_rotation_property(dev, flags); | |
13330 | } | |
13331 | if (dev->mode_config.rotation_property) | |
13332 | drm_object_attach_property(&plane->base.base, | |
13333 | dev->mode_config.rotation_property, | |
13334 | plane->base.state->rotation); | |
13335 | } | |
13336 | ||
3d7d6510 | 13337 | static int |
852e787c GP |
13338 | intel_check_cursor_plane(struct drm_plane *plane, |
13339 | struct intel_plane_state *state) | |
3d7d6510 | 13340 | { |
2b875c22 | 13341 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13342 | struct drm_device *dev = plane->dev; |
2b875c22 | 13343 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13344 | struct drm_rect *dest = &state->dst; |
13345 | struct drm_rect *src = &state->src; | |
13346 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13347 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13348 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13349 | unsigned stride; |
13350 | int ret; | |
3d7d6510 | 13351 | |
ea2c67bb MR |
13352 | crtc = crtc ? crtc : plane->crtc; |
13353 | intel_crtc = to_intel_crtc(crtc); | |
13354 | ||
757f9a3e | 13355 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13356 | src, dest, clip, |
3d7d6510 MR |
13357 | DRM_PLANE_HELPER_NO_SCALING, |
13358 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13359 | true, true, &state->visible); |
757f9a3e GP |
13360 | if (ret) |
13361 | return ret; | |
13362 | ||
13363 | ||
13364 | /* if we want to turn off the cursor ignore width and height */ | |
13365 | if (!obj) | |
32b7eeec | 13366 | goto finish; |
757f9a3e | 13367 | |
757f9a3e | 13368 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13369 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13370 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13371 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13372 | return -EINVAL; |
13373 | } | |
13374 | ||
ea2c67bb MR |
13375 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13376 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13377 | DRM_DEBUG_KMS("buffer is too small\n"); |
13378 | return -ENOMEM; | |
13379 | } | |
13380 | ||
3a656b54 | 13381 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13382 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13383 | ret = -EINVAL; | |
13384 | } | |
757f9a3e | 13385 | |
32b7eeec MR |
13386 | finish: |
13387 | if (intel_crtc->active) { | |
3749f463 | 13388 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13389 | intel_crtc->atomic.update_wm = true; |
13390 | ||
13391 | intel_crtc->atomic.fb_bits |= | |
13392 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13393 | } | |
13394 | ||
757f9a3e | 13395 | return ret; |
852e787c | 13396 | } |
3d7d6510 | 13397 | |
a8ad0d8e ML |
13398 | static void |
13399 | intel_disable_cursor_plane(struct drm_plane *plane, | |
13400 | struct drm_crtc *crtc, | |
13401 | bool force) | |
13402 | { | |
13403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13404 | ||
13405 | if (!force) { | |
13406 | plane->fb = NULL; | |
13407 | intel_crtc->cursor_bo = NULL; | |
13408 | intel_crtc->cursor_addr = 0; | |
13409 | } | |
13410 | ||
13411 | intel_crtc_update_cursor(crtc, false); | |
13412 | } | |
13413 | ||
f4a2cf29 | 13414 | static void |
852e787c GP |
13415 | intel_commit_cursor_plane(struct drm_plane *plane, |
13416 | struct intel_plane_state *state) | |
13417 | { | |
2b875c22 | 13418 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13419 | struct drm_device *dev = plane->dev; |
13420 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13421 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13422 | uint32_t addr; |
852e787c | 13423 | |
ea2c67bb MR |
13424 | crtc = crtc ? crtc : plane->crtc; |
13425 | intel_crtc = to_intel_crtc(crtc); | |
13426 | ||
2b875c22 | 13427 | plane->fb = state->base.fb; |
ea2c67bb MR |
13428 | crtc->cursor_x = state->base.crtc_x; |
13429 | crtc->cursor_y = state->base.crtc_y; | |
13430 | ||
a912f12f GP |
13431 | if (intel_crtc->cursor_bo == obj) |
13432 | goto update; | |
4ed91096 | 13433 | |
f4a2cf29 | 13434 | if (!obj) |
a912f12f | 13435 | addr = 0; |
f4a2cf29 | 13436 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13437 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13438 | else |
a912f12f | 13439 | addr = obj->phys_handle->busaddr; |
852e787c | 13440 | |
a912f12f GP |
13441 | intel_crtc->cursor_addr = addr; |
13442 | intel_crtc->cursor_bo = obj; | |
13443 | update: | |
852e787c | 13444 | |
32b7eeec | 13445 | if (intel_crtc->active) |
a912f12f | 13446 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13447 | } |
13448 | ||
3d7d6510 MR |
13449 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13450 | int pipe) | |
13451 | { | |
13452 | struct intel_plane *cursor; | |
8e7d688b | 13453 | struct intel_plane_state *state; |
3d7d6510 MR |
13454 | |
13455 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13456 | if (cursor == NULL) | |
13457 | return NULL; | |
13458 | ||
8e7d688b MR |
13459 | state = intel_create_plane_state(&cursor->base); |
13460 | if (!state) { | |
ea2c67bb MR |
13461 | kfree(cursor); |
13462 | return NULL; | |
13463 | } | |
8e7d688b | 13464 | cursor->base.state = &state->base; |
ea2c67bb | 13465 | |
3d7d6510 MR |
13466 | cursor->can_scale = false; |
13467 | cursor->max_downscale = 1; | |
13468 | cursor->pipe = pipe; | |
13469 | cursor->plane = pipe; | |
c59cb179 MR |
13470 | cursor->check_plane = intel_check_cursor_plane; |
13471 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13472 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13473 | |
13474 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13475 | &intel_plane_funcs, |
3d7d6510 MR |
13476 | intel_cursor_formats, |
13477 | ARRAY_SIZE(intel_cursor_formats), | |
13478 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13479 | |
13480 | if (INTEL_INFO(dev)->gen >= 4) { | |
13481 | if (!dev->mode_config.rotation_property) | |
13482 | dev->mode_config.rotation_property = | |
13483 | drm_mode_create_rotation_property(dev, | |
13484 | BIT(DRM_ROTATE_0) | | |
13485 | BIT(DRM_ROTATE_180)); | |
13486 | if (dev->mode_config.rotation_property) | |
13487 | drm_object_attach_property(&cursor->base.base, | |
13488 | dev->mode_config.rotation_property, | |
8e7d688b | 13489 | state->base.rotation); |
4398ad45 VS |
13490 | } |
13491 | ||
af99ceda CK |
13492 | if (INTEL_INFO(dev)->gen >=9) |
13493 | state->scaler_id = -1; | |
13494 | ||
ea2c67bb MR |
13495 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13496 | ||
3d7d6510 MR |
13497 | return &cursor->base; |
13498 | } | |
13499 | ||
549e2bfb CK |
13500 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13501 | struct intel_crtc_state *crtc_state) | |
13502 | { | |
13503 | int i; | |
13504 | struct intel_scaler *intel_scaler; | |
13505 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13506 | ||
13507 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13508 | intel_scaler = &scaler_state->scalers[i]; | |
13509 | intel_scaler->in_use = 0; | |
13510 | intel_scaler->id = i; | |
13511 | ||
13512 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13513 | } | |
13514 | ||
13515 | scaler_state->scaler_id = -1; | |
13516 | } | |
13517 | ||
b358d0a6 | 13518 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13519 | { |
fbee40df | 13520 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13521 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13522 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13523 | struct drm_plane *primary = NULL; |
13524 | struct drm_plane *cursor = NULL; | |
465c120c | 13525 | int i, ret; |
79e53945 | 13526 | |
955382f3 | 13527 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13528 | if (intel_crtc == NULL) |
13529 | return; | |
13530 | ||
f5de6e07 ACO |
13531 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13532 | if (!crtc_state) | |
13533 | goto fail; | |
550acefd ACO |
13534 | intel_crtc->config = crtc_state; |
13535 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13536 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13537 | |
549e2bfb CK |
13538 | /* initialize shared scalers */ |
13539 | if (INTEL_INFO(dev)->gen >= 9) { | |
13540 | if (pipe == PIPE_C) | |
13541 | intel_crtc->num_scalers = 1; | |
13542 | else | |
13543 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13544 | ||
13545 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13546 | } | |
13547 | ||
465c120c | 13548 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13549 | if (!primary) |
13550 | goto fail; | |
13551 | ||
13552 | cursor = intel_cursor_plane_create(dev, pipe); | |
13553 | if (!cursor) | |
13554 | goto fail; | |
13555 | ||
465c120c | 13556 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13557 | cursor, &intel_crtc_funcs); |
13558 | if (ret) | |
13559 | goto fail; | |
79e53945 JB |
13560 | |
13561 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13562 | for (i = 0; i < 256; i++) { |
13563 | intel_crtc->lut_r[i] = i; | |
13564 | intel_crtc->lut_g[i] = i; | |
13565 | intel_crtc->lut_b[i] = i; | |
13566 | } | |
13567 | ||
1f1c2e24 VS |
13568 | /* |
13569 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13570 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13571 | */ |
80824003 JB |
13572 | intel_crtc->pipe = pipe; |
13573 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13574 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13575 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13576 | intel_crtc->plane = !pipe; |
80824003 JB |
13577 | } |
13578 | ||
4b0e333e CW |
13579 | intel_crtc->cursor_base = ~0; |
13580 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13581 | intel_crtc->cursor_size = ~0; |
8d7849db | 13582 | |
22fd0fab JB |
13583 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13584 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13585 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13586 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13587 | ||
79e53945 | 13588 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13589 | |
13590 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13591 | return; |
13592 | ||
13593 | fail: | |
13594 | if (primary) | |
13595 | drm_plane_cleanup(primary); | |
13596 | if (cursor) | |
13597 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13598 | kfree(crtc_state); |
3d7d6510 | 13599 | kfree(intel_crtc); |
79e53945 JB |
13600 | } |
13601 | ||
752aa88a JB |
13602 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13603 | { | |
13604 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13605 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13606 | |
51fd371b | 13607 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13608 | |
d3babd3f | 13609 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13610 | return INVALID_PIPE; |
13611 | ||
13612 | return to_intel_crtc(encoder->crtc)->pipe; | |
13613 | } | |
13614 | ||
08d7b3d1 | 13615 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13616 | struct drm_file *file) |
08d7b3d1 | 13617 | { |
08d7b3d1 | 13618 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13619 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13620 | struct intel_crtc *crtc; |
08d7b3d1 | 13621 | |
7707e653 | 13622 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13623 | |
7707e653 | 13624 | if (!drmmode_crtc) { |
08d7b3d1 | 13625 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13626 | return -ENOENT; |
08d7b3d1 CW |
13627 | } |
13628 | ||
7707e653 | 13629 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13630 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13631 | |
c05422d5 | 13632 | return 0; |
08d7b3d1 CW |
13633 | } |
13634 | ||
66a9278e | 13635 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13636 | { |
66a9278e DV |
13637 | struct drm_device *dev = encoder->base.dev; |
13638 | struct intel_encoder *source_encoder; | |
79e53945 | 13639 | int index_mask = 0; |
79e53945 JB |
13640 | int entry = 0; |
13641 | ||
b2784e15 | 13642 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13643 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13644 | index_mask |= (1 << entry); |
13645 | ||
79e53945 JB |
13646 | entry++; |
13647 | } | |
4ef69c7a | 13648 | |
79e53945 JB |
13649 | return index_mask; |
13650 | } | |
13651 | ||
4d302442 CW |
13652 | static bool has_edp_a(struct drm_device *dev) |
13653 | { | |
13654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13655 | ||
13656 | if (!IS_MOBILE(dev)) | |
13657 | return false; | |
13658 | ||
13659 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13660 | return false; | |
13661 | ||
e3589908 | 13662 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13663 | return false; |
13664 | ||
13665 | return true; | |
13666 | } | |
13667 | ||
84b4e042 JB |
13668 | static bool intel_crt_present(struct drm_device *dev) |
13669 | { | |
13670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13671 | ||
884497ed DL |
13672 | if (INTEL_INFO(dev)->gen >= 9) |
13673 | return false; | |
13674 | ||
cf404ce4 | 13675 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13676 | return false; |
13677 | ||
13678 | if (IS_CHERRYVIEW(dev)) | |
13679 | return false; | |
13680 | ||
13681 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13682 | return false; | |
13683 | ||
13684 | return true; | |
13685 | } | |
13686 | ||
79e53945 JB |
13687 | static void intel_setup_outputs(struct drm_device *dev) |
13688 | { | |
725e30ad | 13689 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13690 | struct intel_encoder *encoder; |
cb0953d7 | 13691 | bool dpd_is_edp = false; |
79e53945 | 13692 | |
c9093354 | 13693 | intel_lvds_init(dev); |
79e53945 | 13694 | |
84b4e042 | 13695 | if (intel_crt_present(dev)) |
79935fca | 13696 | intel_crt_init(dev); |
cb0953d7 | 13697 | |
c776eb2e VK |
13698 | if (IS_BROXTON(dev)) { |
13699 | /* | |
13700 | * FIXME: Broxton doesn't support port detection via the | |
13701 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13702 | * detect the ports. | |
13703 | */ | |
13704 | intel_ddi_init(dev, PORT_A); | |
13705 | intel_ddi_init(dev, PORT_B); | |
13706 | intel_ddi_init(dev, PORT_C); | |
13707 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13708 | int found; |
13709 | ||
de31facd JB |
13710 | /* |
13711 | * Haswell uses DDI functions to detect digital outputs. | |
13712 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13713 | * it's there. | |
13714 | */ | |
0e72a5b5 | 13715 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13716 | /* WaIgnoreDDIAStrap: skl */ |
13717 | if (found || | |
13718 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13719 | intel_ddi_init(dev, PORT_A); |
13720 | ||
13721 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13722 | * register */ | |
13723 | found = I915_READ(SFUSE_STRAP); | |
13724 | ||
13725 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13726 | intel_ddi_init(dev, PORT_B); | |
13727 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13728 | intel_ddi_init(dev, PORT_C); | |
13729 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13730 | intel_ddi_init(dev, PORT_D); | |
13731 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13732 | int found; |
5d8a7752 | 13733 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13734 | |
13735 | if (has_edp_a(dev)) | |
13736 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13737 | |
dc0fa718 | 13738 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13739 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13740 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13741 | if (!found) |
e2debe91 | 13742 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13743 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13744 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13745 | } |
13746 | ||
dc0fa718 | 13747 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13748 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13749 | |
dc0fa718 | 13750 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13751 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13752 | |
5eb08b69 | 13753 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13754 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13755 | |
270b3042 | 13756 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13757 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13758 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13759 | /* |
13760 | * The DP_DETECTED bit is the latched state of the DDC | |
13761 | * SDA pin at boot. However since eDP doesn't require DDC | |
13762 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13763 | * eDP ports may have been muxed to an alternate function. | |
13764 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13765 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13766 | * detect eDP ports. | |
13767 | */ | |
d2182a66 VS |
13768 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13769 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13770 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13771 | PORT_B); | |
e17ac6db VS |
13772 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13773 | intel_dp_is_edp(dev, PORT_B)) | |
13774 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13775 | |
d2182a66 VS |
13776 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13777 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13778 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13779 | PORT_C); | |
e17ac6db VS |
13780 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13781 | intel_dp_is_edp(dev, PORT_C)) | |
13782 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13783 | |
9418c1f1 | 13784 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13785 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13786 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13787 | PORT_D); | |
e17ac6db VS |
13788 | /* eDP not supported on port D, so don't check VBT */ |
13789 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13790 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13791 | } |
13792 | ||
3cfca973 | 13793 | intel_dsi_init(dev); |
103a196f | 13794 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13795 | bool found = false; |
7d57382e | 13796 | |
e2debe91 | 13797 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13798 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13799 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13800 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13801 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13802 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13803 | } |
27185ae1 | 13804 | |
e7281eab | 13805 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13806 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13807 | } |
13520b05 KH |
13808 | |
13809 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13810 | |
e2debe91 | 13811 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13812 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13813 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13814 | } |
27185ae1 | 13815 | |
e2debe91 | 13816 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13817 | |
b01f2c3a JB |
13818 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13819 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13820 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13821 | } |
e7281eab | 13822 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13823 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13824 | } |
27185ae1 | 13825 | |
b01f2c3a | 13826 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13827 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13828 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13829 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13830 | intel_dvo_init(dev); |
13831 | ||
103a196f | 13832 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13833 | intel_tv_init(dev); |
13834 | ||
0bc12bcb | 13835 | intel_psr_init(dev); |
7c8f8a70 | 13836 | |
b2784e15 | 13837 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13838 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13839 | encoder->base.possible_clones = | |
66a9278e | 13840 | intel_encoder_clones(encoder); |
79e53945 | 13841 | } |
47356eb6 | 13842 | |
dde86e2d | 13843 | intel_init_pch_refclk(dev); |
270b3042 DV |
13844 | |
13845 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13846 | } |
13847 | ||
13848 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13849 | { | |
60a5ca01 | 13850 | struct drm_device *dev = fb->dev; |
79e53945 | 13851 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13852 | |
ef2d633e | 13853 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13854 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13855 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13856 | drm_gem_object_unreference(&intel_fb->obj->base); |
13857 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13858 | kfree(intel_fb); |
13859 | } | |
13860 | ||
13861 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13862 | struct drm_file *file, |
79e53945 JB |
13863 | unsigned int *handle) |
13864 | { | |
13865 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13866 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13867 | |
05394f39 | 13868 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13869 | } |
13870 | ||
13871 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13872 | .destroy = intel_user_framebuffer_destroy, | |
13873 | .create_handle = intel_user_framebuffer_create_handle, | |
13874 | }; | |
13875 | ||
b321803d DL |
13876 | static |
13877 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13878 | uint32_t pixel_format) | |
13879 | { | |
13880 | u32 gen = INTEL_INFO(dev)->gen; | |
13881 | ||
13882 | if (gen >= 9) { | |
13883 | /* "The stride in bytes must not exceed the of the size of 8K | |
13884 | * pixels and 32K bytes." | |
13885 | */ | |
13886 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13887 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13888 | return 32*1024; | |
13889 | } else if (gen >= 4) { | |
13890 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13891 | return 16*1024; | |
13892 | else | |
13893 | return 32*1024; | |
13894 | } else if (gen >= 3) { | |
13895 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13896 | return 8*1024; | |
13897 | else | |
13898 | return 16*1024; | |
13899 | } else { | |
13900 | /* XXX DSPC is limited to 4k tiled */ | |
13901 | return 8*1024; | |
13902 | } | |
13903 | } | |
13904 | ||
b5ea642a DV |
13905 | static int intel_framebuffer_init(struct drm_device *dev, |
13906 | struct intel_framebuffer *intel_fb, | |
13907 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13908 | struct drm_i915_gem_object *obj) | |
79e53945 | 13909 | { |
6761dd31 | 13910 | unsigned int aligned_height; |
79e53945 | 13911 | int ret; |
b321803d | 13912 | u32 pitch_limit, stride_alignment; |
79e53945 | 13913 | |
dd4916c5 DV |
13914 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13915 | ||
2a80eada DV |
13916 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13917 | /* Enforce that fb modifier and tiling mode match, but only for | |
13918 | * X-tiled. This is needed for FBC. */ | |
13919 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13920 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13921 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13922 | return -EINVAL; | |
13923 | } | |
13924 | } else { | |
13925 | if (obj->tiling_mode == I915_TILING_X) | |
13926 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13927 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13928 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13929 | return -EINVAL; | |
13930 | } | |
13931 | } | |
13932 | ||
9a8f0a12 TU |
13933 | /* Passed in modifier sanity checking. */ |
13934 | switch (mode_cmd->modifier[0]) { | |
13935 | case I915_FORMAT_MOD_Y_TILED: | |
13936 | case I915_FORMAT_MOD_Yf_TILED: | |
13937 | if (INTEL_INFO(dev)->gen < 9) { | |
13938 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13939 | mode_cmd->modifier[0]); | |
13940 | return -EINVAL; | |
13941 | } | |
13942 | case DRM_FORMAT_MOD_NONE: | |
13943 | case I915_FORMAT_MOD_X_TILED: | |
13944 | break; | |
13945 | default: | |
c0f40428 JB |
13946 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13947 | mode_cmd->modifier[0]); | |
57cd6508 | 13948 | return -EINVAL; |
c16ed4be | 13949 | } |
57cd6508 | 13950 | |
b321803d DL |
13951 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13952 | mode_cmd->pixel_format); | |
13953 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13954 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13955 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13956 | return -EINVAL; |
c16ed4be | 13957 | } |
57cd6508 | 13958 | |
b321803d DL |
13959 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13960 | mode_cmd->pixel_format); | |
a35cdaa0 | 13961 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13962 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13963 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13964 | "tiled" : "linear", |
a35cdaa0 | 13965 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13966 | return -EINVAL; |
c16ed4be | 13967 | } |
5d7bd705 | 13968 | |
2a80eada | 13969 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13970 | mode_cmd->pitches[0] != obj->stride) { |
13971 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13972 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13973 | return -EINVAL; |
c16ed4be | 13974 | } |
5d7bd705 | 13975 | |
57779d06 | 13976 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13977 | switch (mode_cmd->pixel_format) { |
57779d06 | 13978 | case DRM_FORMAT_C8: |
04b3924d VS |
13979 | case DRM_FORMAT_RGB565: |
13980 | case DRM_FORMAT_XRGB8888: | |
13981 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13982 | break; |
13983 | case DRM_FORMAT_XRGB1555: | |
13984 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13985 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13986 | DRM_DEBUG("unsupported pixel format: %s\n", |
13987 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13988 | return -EINVAL; |
c16ed4be | 13989 | } |
57779d06 VS |
13990 | break; |
13991 | case DRM_FORMAT_XBGR8888: | |
13992 | case DRM_FORMAT_ABGR8888: | |
04b3924d | 13993 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 13994 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 13995 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13996 | DRM_DEBUG("unsupported pixel format: %s\n", |
13997 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13998 | return -EINVAL; |
c16ed4be | 13999 | } |
b5626747 | 14000 | break; |
7531208b DL |
14001 | case DRM_FORMAT_ABGR2101010: |
14002 | if (!IS_VALLEYVIEW(dev)) { | |
14003 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14004 | drm_get_format_name(mode_cmd->pixel_format)); | |
14005 | return -EINVAL; | |
14006 | } | |
14007 | break; | |
04b3924d VS |
14008 | case DRM_FORMAT_YUYV: |
14009 | case DRM_FORMAT_UYVY: | |
14010 | case DRM_FORMAT_YVYU: | |
14011 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14012 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14013 | DRM_DEBUG("unsupported pixel format: %s\n", |
14014 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14015 | return -EINVAL; |
c16ed4be | 14016 | } |
57cd6508 CW |
14017 | break; |
14018 | default: | |
4ee62c76 VS |
14019 | DRM_DEBUG("unsupported pixel format: %s\n", |
14020 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14021 | return -EINVAL; |
14022 | } | |
14023 | ||
90f9a336 VS |
14024 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14025 | if (mode_cmd->offsets[0] != 0) | |
14026 | return -EINVAL; | |
14027 | ||
ec2c981e | 14028 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14029 | mode_cmd->pixel_format, |
14030 | mode_cmd->modifier[0]); | |
53155c0a DV |
14031 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14032 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14033 | return -EINVAL; | |
14034 | ||
c7d73f6a DV |
14035 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14036 | intel_fb->obj = obj; | |
80075d49 | 14037 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14038 | |
79e53945 JB |
14039 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14040 | if (ret) { | |
14041 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14042 | return ret; | |
14043 | } | |
14044 | ||
79e53945 JB |
14045 | return 0; |
14046 | } | |
14047 | ||
79e53945 JB |
14048 | static struct drm_framebuffer * |
14049 | intel_user_framebuffer_create(struct drm_device *dev, | |
14050 | struct drm_file *filp, | |
308e5bcb | 14051 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14052 | { |
05394f39 | 14053 | struct drm_i915_gem_object *obj; |
79e53945 | 14054 | |
308e5bcb JB |
14055 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14056 | mode_cmd->handles[0])); | |
c8725226 | 14057 | if (&obj->base == NULL) |
cce13ff7 | 14058 | return ERR_PTR(-ENOENT); |
79e53945 | 14059 | |
d2dff872 | 14060 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14061 | } |
14062 | ||
4520f53a | 14063 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14064 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14065 | { |
14066 | } | |
14067 | #endif | |
14068 | ||
79e53945 | 14069 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14070 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14071 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14072 | .atomic_check = intel_atomic_check, |
14073 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14074 | }; |
14075 | ||
e70236a8 JB |
14076 | /* Set up chip specific display functions */ |
14077 | static void intel_init_display(struct drm_device *dev) | |
14078 | { | |
14079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14080 | ||
ee9300bb DV |
14081 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14082 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14083 | else if (IS_CHERRYVIEW(dev)) |
14084 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14085 | else if (IS_VALLEYVIEW(dev)) |
14086 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14087 | else if (IS_PINEVIEW(dev)) | |
14088 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14089 | else | |
14090 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14091 | ||
bc8d7dff DL |
14092 | if (INTEL_INFO(dev)->gen >= 9) { |
14093 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14094 | dev_priv->display.get_initial_plane_config = |
14095 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14096 | dev_priv->display.crtc_compute_clock = |
14097 | haswell_crtc_compute_clock; | |
14098 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14099 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14100 | dev_priv->display.off = ironlake_crtc_off; | |
14101 | dev_priv->display.update_primary_plane = | |
14102 | skylake_update_primary_plane; | |
14103 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14104 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14105 | dev_priv->display.get_initial_plane_config = |
14106 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14107 | dev_priv->display.crtc_compute_clock = |
14108 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14109 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14110 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14111 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14112 | dev_priv->display.update_primary_plane = |
14113 | ironlake_update_primary_plane; | |
09b4ddf9 | 14114 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14115 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14116 | dev_priv->display.get_initial_plane_config = |
14117 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14118 | dev_priv->display.crtc_compute_clock = |
14119 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14120 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14121 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14122 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14123 | dev_priv->display.update_primary_plane = |
14124 | ironlake_update_primary_plane; | |
89b667f8 JB |
14125 | } else if (IS_VALLEYVIEW(dev)) { |
14126 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14127 | dev_priv->display.get_initial_plane_config = |
14128 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14129 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14130 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14131 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14132 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14133 | dev_priv->display.update_primary_plane = |
14134 | i9xx_update_primary_plane; | |
f564048e | 14135 | } else { |
0e8ffe1b | 14136 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14137 | dev_priv->display.get_initial_plane_config = |
14138 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14139 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14140 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14141 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14142 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14143 | dev_priv->display.update_primary_plane = |
14144 | i9xx_update_primary_plane; | |
f564048e | 14145 | } |
e70236a8 | 14146 | |
e70236a8 | 14147 | /* Returns the core display clock speed */ |
1652d19e VS |
14148 | if (IS_SKYLAKE(dev)) |
14149 | dev_priv->display.get_display_clock_speed = | |
14150 | skylake_get_display_clock_speed; | |
14151 | else if (IS_BROADWELL(dev)) | |
14152 | dev_priv->display.get_display_clock_speed = | |
14153 | broadwell_get_display_clock_speed; | |
14154 | else if (IS_HASWELL(dev)) | |
14155 | dev_priv->display.get_display_clock_speed = | |
14156 | haswell_get_display_clock_speed; | |
14157 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14158 | dev_priv->display.get_display_clock_speed = |
14159 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14160 | else if (IS_GEN5(dev)) |
14161 | dev_priv->display.get_display_clock_speed = | |
14162 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14163 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14164 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14165 | dev_priv->display.get_display_clock_speed = |
14166 | i945_get_display_clock_speed; | |
14167 | else if (IS_I915G(dev)) | |
14168 | dev_priv->display.get_display_clock_speed = | |
14169 | i915_get_display_clock_speed; | |
257a7ffc | 14170 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14171 | dev_priv->display.get_display_clock_speed = |
14172 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14173 | else if (IS_PINEVIEW(dev)) |
14174 | dev_priv->display.get_display_clock_speed = | |
14175 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14176 | else if (IS_I915GM(dev)) |
14177 | dev_priv->display.get_display_clock_speed = | |
14178 | i915gm_get_display_clock_speed; | |
14179 | else if (IS_I865G(dev)) | |
14180 | dev_priv->display.get_display_clock_speed = | |
14181 | i865_get_display_clock_speed; | |
f0f8a9ce | 14182 | else if (IS_I85X(dev)) |
e70236a8 JB |
14183 | dev_priv->display.get_display_clock_speed = |
14184 | i855_get_display_clock_speed; | |
14185 | else /* 852, 830 */ | |
14186 | dev_priv->display.get_display_clock_speed = | |
14187 | i830_get_display_clock_speed; | |
14188 | ||
7c10a2b5 | 14189 | if (IS_GEN5(dev)) { |
3bb11b53 | 14190 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14191 | } else if (IS_GEN6(dev)) { |
14192 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14193 | } else if (IS_IVYBRIDGE(dev)) { |
14194 | /* FIXME: detect B0+ stepping and use auto training */ | |
14195 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14196 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14197 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14198 | } else if (IS_VALLEYVIEW(dev)) { |
14199 | dev_priv->display.modeset_global_resources = | |
14200 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14201 | } else if (IS_BROXTON(dev)) { |
14202 | dev_priv->display.modeset_global_resources = | |
14203 | broxton_modeset_global_resources; | |
e70236a8 | 14204 | } |
8c9f3aaf | 14205 | |
8c9f3aaf JB |
14206 | switch (INTEL_INFO(dev)->gen) { |
14207 | case 2: | |
14208 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14209 | break; | |
14210 | ||
14211 | case 3: | |
14212 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14213 | break; | |
14214 | ||
14215 | case 4: | |
14216 | case 5: | |
14217 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14218 | break; | |
14219 | ||
14220 | case 6: | |
14221 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14222 | break; | |
7c9017e5 | 14223 | case 7: |
4e0bbc31 | 14224 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14225 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14226 | break; | |
830c81db | 14227 | case 9: |
ba343e02 TU |
14228 | /* Drop through - unsupported since execlist only. */ |
14229 | default: | |
14230 | /* Default just returns -ENODEV to indicate unsupported */ | |
14231 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14232 | } |
7bd688cd JN |
14233 | |
14234 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14235 | |
14236 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14237 | } |
14238 | ||
b690e96c JB |
14239 | /* |
14240 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14241 | * resume, or other times. This quirk makes sure that's the case for | |
14242 | * affected systems. | |
14243 | */ | |
0206e353 | 14244 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14245 | { |
14246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14247 | ||
14248 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14249 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14250 | } |
14251 | ||
b6b5d049 VS |
14252 | static void quirk_pipeb_force(struct drm_device *dev) |
14253 | { | |
14254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14255 | ||
14256 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14257 | DRM_INFO("applying pipe b force quirk\n"); | |
14258 | } | |
14259 | ||
435793df KP |
14260 | /* |
14261 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14262 | */ | |
14263 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14264 | { | |
14265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14266 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14267 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14268 | } |
14269 | ||
4dca20ef | 14270 | /* |
5a15ab5b CE |
14271 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14272 | * brightness value | |
4dca20ef CE |
14273 | */ |
14274 | static void quirk_invert_brightness(struct drm_device *dev) | |
14275 | { | |
14276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14277 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14278 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14279 | } |
14280 | ||
9c72cc6f SD |
14281 | /* Some VBT's incorrectly indicate no backlight is present */ |
14282 | static void quirk_backlight_present(struct drm_device *dev) | |
14283 | { | |
14284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14285 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14286 | DRM_INFO("applying backlight present quirk\n"); | |
14287 | } | |
14288 | ||
b690e96c JB |
14289 | struct intel_quirk { |
14290 | int device; | |
14291 | int subsystem_vendor; | |
14292 | int subsystem_device; | |
14293 | void (*hook)(struct drm_device *dev); | |
14294 | }; | |
14295 | ||
5f85f176 EE |
14296 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14297 | struct intel_dmi_quirk { | |
14298 | void (*hook)(struct drm_device *dev); | |
14299 | const struct dmi_system_id (*dmi_id_list)[]; | |
14300 | }; | |
14301 | ||
14302 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14303 | { | |
14304 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14305 | return 1; | |
14306 | } | |
14307 | ||
14308 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14309 | { | |
14310 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14311 | { | |
14312 | .callback = intel_dmi_reverse_brightness, | |
14313 | .ident = "NCR Corporation", | |
14314 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14315 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14316 | }, | |
14317 | }, | |
14318 | { } /* terminating entry */ | |
14319 | }, | |
14320 | .hook = quirk_invert_brightness, | |
14321 | }, | |
14322 | }; | |
14323 | ||
c43b5634 | 14324 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14325 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14326 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14327 | ||
b690e96c JB |
14328 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14329 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14330 | ||
5f080c0f VS |
14331 | /* 830 needs to leave pipe A & dpll A up */ |
14332 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14333 | ||
b6b5d049 VS |
14334 | /* 830 needs to leave pipe B & dpll B up */ |
14335 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14336 | ||
435793df KP |
14337 | /* Lenovo U160 cannot use SSC on LVDS */ |
14338 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14339 | |
14340 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14341 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14342 | |
be505f64 AH |
14343 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14344 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14345 | ||
14346 | /* Acer/eMachines G725 */ | |
14347 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14348 | ||
14349 | /* Acer/eMachines e725 */ | |
14350 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14351 | ||
14352 | /* Acer/Packard Bell NCL20 */ | |
14353 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14354 | ||
14355 | /* Acer Aspire 4736Z */ | |
14356 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14357 | |
14358 | /* Acer Aspire 5336 */ | |
14359 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14360 | |
14361 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14362 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14363 | |
dfb3d47b SD |
14364 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14365 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14366 | ||
b2a9601c | 14367 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14368 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14369 | ||
d4967d8c SD |
14370 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14371 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14372 | |
14373 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14374 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14375 | |
14376 | /* Dell Chromebook 11 */ | |
14377 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14378 | }; |
14379 | ||
14380 | static void intel_init_quirks(struct drm_device *dev) | |
14381 | { | |
14382 | struct pci_dev *d = dev->pdev; | |
14383 | int i; | |
14384 | ||
14385 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14386 | struct intel_quirk *q = &intel_quirks[i]; | |
14387 | ||
14388 | if (d->device == q->device && | |
14389 | (d->subsystem_vendor == q->subsystem_vendor || | |
14390 | q->subsystem_vendor == PCI_ANY_ID) && | |
14391 | (d->subsystem_device == q->subsystem_device || | |
14392 | q->subsystem_device == PCI_ANY_ID)) | |
14393 | q->hook(dev); | |
14394 | } | |
5f85f176 EE |
14395 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14396 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14397 | intel_dmi_quirks[i].hook(dev); | |
14398 | } | |
b690e96c JB |
14399 | } |
14400 | ||
9cce37f4 JB |
14401 | /* Disable the VGA plane that we never use */ |
14402 | static void i915_disable_vga(struct drm_device *dev) | |
14403 | { | |
14404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14405 | u8 sr1; | |
766aa1c4 | 14406 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14407 | |
2b37c616 | 14408 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14409 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14410 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14411 | sr1 = inb(VGA_SR_DATA); |
14412 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14413 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14414 | udelay(300); | |
14415 | ||
01f5a626 | 14416 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14417 | POSTING_READ(vga_reg); |
14418 | } | |
14419 | ||
f817586c DV |
14420 | void intel_modeset_init_hw(struct drm_device *dev) |
14421 | { | |
a8f78b58 ED |
14422 | intel_prepare_ddi(dev); |
14423 | ||
f8bf63fd VS |
14424 | if (IS_VALLEYVIEW(dev)) |
14425 | vlv_update_cdclk(dev); | |
14426 | ||
f817586c DV |
14427 | intel_init_clock_gating(dev); |
14428 | ||
8090c6b9 | 14429 | intel_enable_gt_powersave(dev); |
f817586c DV |
14430 | } |
14431 | ||
79e53945 JB |
14432 | void intel_modeset_init(struct drm_device *dev) |
14433 | { | |
652c393a | 14434 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14435 | int sprite, ret; |
8cc87b75 | 14436 | enum pipe pipe; |
46f297fb | 14437 | struct intel_crtc *crtc; |
79e53945 JB |
14438 | |
14439 | drm_mode_config_init(dev); | |
14440 | ||
14441 | dev->mode_config.min_width = 0; | |
14442 | dev->mode_config.min_height = 0; | |
14443 | ||
019d96cb DA |
14444 | dev->mode_config.preferred_depth = 24; |
14445 | dev->mode_config.prefer_shadow = 1; | |
14446 | ||
25bab385 TU |
14447 | dev->mode_config.allow_fb_modifiers = true; |
14448 | ||
e6ecefaa | 14449 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14450 | |
b690e96c JB |
14451 | intel_init_quirks(dev); |
14452 | ||
1fa61106 ED |
14453 | intel_init_pm(dev); |
14454 | ||
e3c74757 BW |
14455 | if (INTEL_INFO(dev)->num_pipes == 0) |
14456 | return; | |
14457 | ||
e70236a8 | 14458 | intel_init_display(dev); |
7c10a2b5 | 14459 | intel_init_audio(dev); |
e70236a8 | 14460 | |
a6c45cf0 CW |
14461 | if (IS_GEN2(dev)) { |
14462 | dev->mode_config.max_width = 2048; | |
14463 | dev->mode_config.max_height = 2048; | |
14464 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14465 | dev->mode_config.max_width = 4096; |
14466 | dev->mode_config.max_height = 4096; | |
79e53945 | 14467 | } else { |
a6c45cf0 CW |
14468 | dev->mode_config.max_width = 8192; |
14469 | dev->mode_config.max_height = 8192; | |
79e53945 | 14470 | } |
068be561 | 14471 | |
dc41c154 VS |
14472 | if (IS_845G(dev) || IS_I865G(dev)) { |
14473 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14474 | dev->mode_config.cursor_height = 1023; | |
14475 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14476 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14477 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14478 | } else { | |
14479 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14480 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14481 | } | |
14482 | ||
5d4545ae | 14483 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14484 | |
28c97730 | 14485 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14486 | INTEL_INFO(dev)->num_pipes, |
14487 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14488 | |
055e393f | 14489 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14490 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14491 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14492 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14493 | if (ret) |
06da8da2 | 14494 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14495 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14496 | } |
79e53945 JB |
14497 | } |
14498 | ||
f42bb70d JB |
14499 | intel_init_dpio(dev); |
14500 | ||
e72f9fbf | 14501 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14502 | |
9cce37f4 JB |
14503 | /* Just disable it once at startup */ |
14504 | i915_disable_vga(dev); | |
79e53945 | 14505 | intel_setup_outputs(dev); |
11be49eb CW |
14506 | |
14507 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14508 | intel_fbc_disable(dev); |
fa9fa083 | 14509 | |
6e9f798d | 14510 | drm_modeset_lock_all(dev); |
fa9fa083 | 14511 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14512 | drm_modeset_unlock_all(dev); |
46f297fb | 14513 | |
d3fcc808 | 14514 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14515 | if (!crtc->active) |
14516 | continue; | |
14517 | ||
46f297fb | 14518 | /* |
46f297fb JB |
14519 | * Note that reserving the BIOS fb up front prevents us |
14520 | * from stuffing other stolen allocations like the ring | |
14521 | * on top. This prevents some ugliness at boot time, and | |
14522 | * can even allow for smooth boot transitions if the BIOS | |
14523 | * fb is large enough for the active pipe configuration. | |
14524 | */ | |
5724dbd1 DL |
14525 | if (dev_priv->display.get_initial_plane_config) { |
14526 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14527 | &crtc->plane_config); |
14528 | /* | |
14529 | * If the fb is shared between multiple heads, we'll | |
14530 | * just get the first one. | |
14531 | */ | |
f6936e29 | 14532 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14533 | } |
46f297fb | 14534 | } |
2c7111db CW |
14535 | } |
14536 | ||
7fad798e DV |
14537 | static void intel_enable_pipe_a(struct drm_device *dev) |
14538 | { | |
14539 | struct intel_connector *connector; | |
14540 | struct drm_connector *crt = NULL; | |
14541 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14542 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14543 | |
14544 | /* We can't just switch on the pipe A, we need to set things up with a | |
14545 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14546 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14547 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14548 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14549 | crt = &connector->base; | |
14550 | break; | |
14551 | } | |
14552 | } | |
14553 | ||
14554 | if (!crt) | |
14555 | return; | |
14556 | ||
208bf9fd | 14557 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14558 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14559 | } |
14560 | ||
fa555837 DV |
14561 | static bool |
14562 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14563 | { | |
7eb552ae BW |
14564 | struct drm_device *dev = crtc->base.dev; |
14565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14566 | u32 reg, val; |
14567 | ||
7eb552ae | 14568 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14569 | return true; |
14570 | ||
14571 | reg = DSPCNTR(!crtc->plane); | |
14572 | val = I915_READ(reg); | |
14573 | ||
14574 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14575 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14576 | return false; | |
14577 | ||
14578 | return true; | |
14579 | } | |
14580 | ||
24929352 DV |
14581 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14582 | { | |
14583 | struct drm_device *dev = crtc->base.dev; | |
14584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14585 | u32 reg; |
24929352 | 14586 | |
24929352 | 14587 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14588 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14589 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14590 | ||
d3eaf884 | 14591 | /* restore vblank interrupts to correct state */ |
9625604c | 14592 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14593 | if (crtc->active) { |
14594 | update_scanline_offset(crtc); | |
9625604c DV |
14595 | drm_crtc_vblank_on(&crtc->base); |
14596 | } | |
d3eaf884 | 14597 | |
24929352 | 14598 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14599 | * disable the crtc (and hence change the state) if it is wrong. Note |
14600 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14601 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14602 | struct intel_connector *connector; |
14603 | bool plane; | |
14604 | ||
24929352 DV |
14605 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14606 | crtc->base.base.id); | |
14607 | ||
14608 | /* Pipe has the wrong plane attached and the plane is active. | |
14609 | * Temporarily change the plane mapping and disable everything | |
14610 | * ... */ | |
14611 | plane = crtc->plane; | |
b70709a6 | 14612 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 14613 | crtc->plane = !plane; |
ce22dba9 | 14614 | intel_crtc_disable_planes(&crtc->base); |
24929352 DV |
14615 | dev_priv->display.crtc_disable(&crtc->base); |
14616 | crtc->plane = plane; | |
14617 | ||
14618 | /* ... and break all links. */ | |
3a3371ff | 14619 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14620 | if (connector->encoder->base.crtc != &crtc->base) |
14621 | continue; | |
14622 | ||
7f1950fb EE |
14623 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14624 | connector->base.encoder = NULL; | |
24929352 | 14625 | } |
7f1950fb EE |
14626 | /* multiple connectors may have the same encoder: |
14627 | * handle them and break crtc link separately */ | |
3a3371ff | 14628 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14629 | if (connector->encoder->base.crtc == &crtc->base) { |
14630 | connector->encoder->base.crtc = NULL; | |
14631 | connector->encoder->connectors_active = false; | |
14632 | } | |
24929352 DV |
14633 | |
14634 | WARN_ON(crtc->active); | |
83d65738 | 14635 | crtc->base.state->enable = false; |
49d6fa21 | 14636 | crtc->base.state->active = false; |
24929352 DV |
14637 | crtc->base.enabled = false; |
14638 | } | |
24929352 | 14639 | |
7fad798e DV |
14640 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14641 | crtc->pipe == PIPE_A && !crtc->active) { | |
14642 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14643 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14644 | * call below we restore the pipe to the right state, but leave | |
14645 | * the required bits on. */ | |
14646 | intel_enable_pipe_a(dev); | |
14647 | } | |
14648 | ||
24929352 DV |
14649 | /* Adjust the state of the output pipe according to whether we |
14650 | * have active connectors/encoders. */ | |
14651 | intel_crtc_update_dpms(&crtc->base); | |
14652 | ||
83d65738 | 14653 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14654 | struct intel_encoder *encoder; |
14655 | ||
14656 | /* This can happen either due to bugs in the get_hw_state | |
14657 | * functions or because the pipe is force-enabled due to the | |
14658 | * pipe A quirk. */ | |
14659 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14660 | crtc->base.base.id, | |
83d65738 | 14661 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14662 | crtc->active ? "enabled" : "disabled"); |
14663 | ||
83d65738 | 14664 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 14665 | crtc->base.state->active = crtc->active; |
24929352 DV |
14666 | crtc->base.enabled = crtc->active; |
14667 | ||
14668 | /* Because we only establish the connector -> encoder -> | |
14669 | * crtc links if something is active, this means the | |
14670 | * crtc is now deactivated. Break the links. connector | |
14671 | * -> encoder links are only establish when things are | |
14672 | * actually up, hence no need to break them. */ | |
14673 | WARN_ON(crtc->active); | |
14674 | ||
14675 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14676 | WARN_ON(encoder->connectors_active); | |
14677 | encoder->base.crtc = NULL; | |
14678 | } | |
14679 | } | |
c5ab3bc0 | 14680 | |
a3ed6aad | 14681 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14682 | /* |
14683 | * We start out with underrun reporting disabled to avoid races. | |
14684 | * For correct bookkeeping mark this on active crtcs. | |
14685 | * | |
c5ab3bc0 DV |
14686 | * Also on gmch platforms we dont have any hardware bits to |
14687 | * disable the underrun reporting. Which means we need to start | |
14688 | * out with underrun reporting disabled also on inactive pipes, | |
14689 | * since otherwise we'll complain about the garbage we read when | |
14690 | * e.g. coming up after runtime pm. | |
14691 | * | |
4cc31489 DV |
14692 | * No protection against concurrent access is required - at |
14693 | * worst a fifo underrun happens which also sets this to false. | |
14694 | */ | |
14695 | crtc->cpu_fifo_underrun_disabled = true; | |
14696 | crtc->pch_fifo_underrun_disabled = true; | |
14697 | } | |
24929352 DV |
14698 | } |
14699 | ||
14700 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14701 | { | |
14702 | struct intel_connector *connector; | |
14703 | struct drm_device *dev = encoder->base.dev; | |
14704 | ||
14705 | /* We need to check both for a crtc link (meaning that the | |
14706 | * encoder is active and trying to read from a pipe) and the | |
14707 | * pipe itself being active. */ | |
14708 | bool has_active_crtc = encoder->base.crtc && | |
14709 | to_intel_crtc(encoder->base.crtc)->active; | |
14710 | ||
14711 | if (encoder->connectors_active && !has_active_crtc) { | |
14712 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14713 | encoder->base.base.id, | |
8e329a03 | 14714 | encoder->base.name); |
24929352 DV |
14715 | |
14716 | /* Connector is active, but has no active pipe. This is | |
14717 | * fallout from our resume register restoring. Disable | |
14718 | * the encoder manually again. */ | |
14719 | if (encoder->base.crtc) { | |
14720 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14721 | encoder->base.base.id, | |
8e329a03 | 14722 | encoder->base.name); |
24929352 | 14723 | encoder->disable(encoder); |
a62d1497 VS |
14724 | if (encoder->post_disable) |
14725 | encoder->post_disable(encoder); | |
24929352 | 14726 | } |
7f1950fb EE |
14727 | encoder->base.crtc = NULL; |
14728 | encoder->connectors_active = false; | |
24929352 DV |
14729 | |
14730 | /* Inconsistent output/port/pipe state happens presumably due to | |
14731 | * a bug in one of the get_hw_state functions. Or someplace else | |
14732 | * in our code, like the register restore mess on resume. Clamp | |
14733 | * things to off as a safer default. */ | |
3a3371ff | 14734 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14735 | if (connector->encoder != encoder) |
14736 | continue; | |
7f1950fb EE |
14737 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14738 | connector->base.encoder = NULL; | |
24929352 DV |
14739 | } |
14740 | } | |
14741 | /* Enabled encoders without active connectors will be fixed in | |
14742 | * the crtc fixup. */ | |
14743 | } | |
14744 | ||
04098753 | 14745 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14746 | { |
14747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14748 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14749 | |
04098753 ID |
14750 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14751 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14752 | i915_disable_vga(dev); | |
14753 | } | |
14754 | } | |
14755 | ||
14756 | void i915_redisable_vga(struct drm_device *dev) | |
14757 | { | |
14758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14759 | ||
8dc8a27c PZ |
14760 | /* This function can be called both from intel_modeset_setup_hw_state or |
14761 | * at a very early point in our resume sequence, where the power well | |
14762 | * structures are not yet restored. Since this function is at a very | |
14763 | * paranoid "someone might have enabled VGA while we were not looking" | |
14764 | * level, just check if the power well is enabled instead of trying to | |
14765 | * follow the "don't touch the power well if we don't need it" policy | |
14766 | * the rest of the driver uses. */ | |
f458ebbc | 14767 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14768 | return; |
14769 | ||
04098753 | 14770 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14771 | } |
14772 | ||
98ec7739 VS |
14773 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14774 | { | |
14775 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14776 | ||
14777 | if (!crtc->active) | |
14778 | return false; | |
14779 | ||
14780 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14781 | } | |
14782 | ||
30e984df | 14783 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14784 | { |
14785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14786 | enum pipe pipe; | |
24929352 DV |
14787 | struct intel_crtc *crtc; |
14788 | struct intel_encoder *encoder; | |
14789 | struct intel_connector *connector; | |
5358901f | 14790 | int i; |
24929352 | 14791 | |
d3fcc808 | 14792 | for_each_intel_crtc(dev, crtc) { |
b70709a6 ML |
14793 | struct drm_plane *primary = crtc->base.primary; |
14794 | struct intel_plane_state *plane_state; | |
14795 | ||
6e3c9717 | 14796 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14797 | |
6e3c9717 | 14798 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14799 | |
0e8ffe1b | 14800 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14801 | crtc->config); |
24929352 | 14802 | |
83d65738 | 14803 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 14804 | crtc->base.state->active = crtc->active; |
24929352 | 14805 | crtc->base.enabled = crtc->active; |
b70709a6 ML |
14806 | |
14807 | plane_state = to_intel_plane_state(primary->state); | |
14808 | plane_state->visible = primary_get_hw_state(crtc); | |
24929352 DV |
14809 | |
14810 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14811 | crtc->base.base.id, | |
14812 | crtc->active ? "enabled" : "disabled"); | |
14813 | } | |
14814 | ||
5358901f DV |
14815 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14816 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14817 | ||
3e369b76 ACO |
14818 | pll->on = pll->get_hw_state(dev_priv, pll, |
14819 | &pll->config.hw_state); | |
5358901f | 14820 | pll->active = 0; |
3e369b76 | 14821 | pll->config.crtc_mask = 0; |
d3fcc808 | 14822 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14823 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14824 | pll->active++; |
3e369b76 | 14825 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14826 | } |
5358901f | 14827 | } |
5358901f | 14828 | |
1e6f2ddc | 14829 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14830 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14831 | |
3e369b76 | 14832 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14833 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14834 | } |
14835 | ||
b2784e15 | 14836 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14837 | pipe = 0; |
14838 | ||
14839 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14840 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14841 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14842 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14843 | } else { |
14844 | encoder->base.crtc = NULL; | |
14845 | } | |
14846 | ||
14847 | encoder->connectors_active = false; | |
6f2bcceb | 14848 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14849 | encoder->base.base.id, |
8e329a03 | 14850 | encoder->base.name, |
24929352 | 14851 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14852 | pipe_name(pipe)); |
24929352 DV |
14853 | } |
14854 | ||
3a3371ff | 14855 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14856 | if (connector->get_hw_state(connector)) { |
14857 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14858 | connector->encoder->connectors_active = true; | |
14859 | connector->base.encoder = &connector->encoder->base; | |
14860 | } else { | |
14861 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14862 | connector->base.encoder = NULL; | |
14863 | } | |
14864 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14865 | connector->base.base.id, | |
c23cc417 | 14866 | connector->base.name, |
24929352 DV |
14867 | connector->base.encoder ? "enabled" : "disabled"); |
14868 | } | |
30e984df DV |
14869 | } |
14870 | ||
14871 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14872 | * and i915 state tracking structures. */ | |
14873 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14874 | bool force_restore) | |
14875 | { | |
14876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14877 | enum pipe pipe; | |
30e984df DV |
14878 | struct intel_crtc *crtc; |
14879 | struct intel_encoder *encoder; | |
35c95375 | 14880 | int i; |
30e984df DV |
14881 | |
14882 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14883 | |
babea61d JB |
14884 | /* |
14885 | * Now that we have the config, copy it to each CRTC struct | |
14886 | * Note that this could go away if we move to using crtc_config | |
14887 | * checking everywhere. | |
14888 | */ | |
d3fcc808 | 14889 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14890 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14891 | intel_mode_from_pipe_config(&crtc->base.mode, |
14892 | crtc->config); | |
babea61d JB |
14893 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14894 | crtc->base.base.id); | |
14895 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14896 | } | |
14897 | } | |
14898 | ||
24929352 | 14899 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14900 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14901 | intel_sanitize_encoder(encoder); |
14902 | } | |
14903 | ||
055e393f | 14904 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14905 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14906 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14907 | intel_dump_pipe_config(crtc, crtc->config, |
14908 | "[setup_hw_state]"); | |
24929352 | 14909 | } |
9a935856 | 14910 | |
d29b2f9d ACO |
14911 | intel_modeset_update_connector_atomic_state(dev); |
14912 | ||
35c95375 DV |
14913 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14914 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14915 | ||
14916 | if (!pll->on || pll->active) | |
14917 | continue; | |
14918 | ||
14919 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14920 | ||
14921 | pll->disable(dev_priv, pll); | |
14922 | pll->on = false; | |
14923 | } | |
14924 | ||
3078999f PB |
14925 | if (IS_GEN9(dev)) |
14926 | skl_wm_get_hw_state(dev); | |
14927 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14928 | ilk_wm_get_hw_state(dev); |
14929 | ||
45e2b5f6 | 14930 | if (force_restore) { |
7d0bc1ea VS |
14931 | i915_redisable_vga(dev); |
14932 | ||
f30da187 DV |
14933 | /* |
14934 | * We need to use raw interfaces for restoring state to avoid | |
14935 | * checking (bogus) intermediate states. | |
14936 | */ | |
055e393f | 14937 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14938 | struct drm_crtc *crtc = |
14939 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14940 | |
83a57153 | 14941 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14942 | } |
14943 | } else { | |
14944 | intel_modeset_update_staged_output_state(dev); | |
14945 | } | |
8af6cf88 DV |
14946 | |
14947 | intel_modeset_check_state(dev); | |
2c7111db CW |
14948 | } |
14949 | ||
14950 | void intel_modeset_gem_init(struct drm_device *dev) | |
14951 | { | |
92122789 | 14952 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14953 | struct drm_crtc *c; |
2ff8fde1 | 14954 | struct drm_i915_gem_object *obj; |
e0d6149b | 14955 | int ret; |
484b41dd | 14956 | |
ae48434c ID |
14957 | mutex_lock(&dev->struct_mutex); |
14958 | intel_init_gt_powersave(dev); | |
14959 | mutex_unlock(&dev->struct_mutex); | |
14960 | ||
92122789 JB |
14961 | /* |
14962 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14963 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14964 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14965 | * indicates as much. | |
14966 | */ | |
14967 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14968 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14969 | DREF_SSC1_ENABLE); | |
14970 | ||
1833b134 | 14971 | intel_modeset_init_hw(dev); |
02e792fb DV |
14972 | |
14973 | intel_setup_overlay(dev); | |
484b41dd JB |
14974 | |
14975 | /* | |
14976 | * Make sure any fbs we allocated at startup are properly | |
14977 | * pinned & fenced. When we do the allocation it's too early | |
14978 | * for this. | |
14979 | */ | |
70e1e0ec | 14980 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14981 | obj = intel_fb_obj(c->primary->fb); |
14982 | if (obj == NULL) | |
484b41dd JB |
14983 | continue; |
14984 | ||
e0d6149b TU |
14985 | mutex_lock(&dev->struct_mutex); |
14986 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
14987 | c->primary->fb, | |
14988 | c->primary->state, | |
14989 | NULL); | |
14990 | mutex_unlock(&dev->struct_mutex); | |
14991 | if (ret) { | |
484b41dd JB |
14992 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14993 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14994 | drm_framebuffer_unreference(c->primary->fb); |
14995 | c->primary->fb = NULL; | |
afd65eb4 | 14996 | update_state_fb(c->primary); |
484b41dd JB |
14997 | } |
14998 | } | |
0962c3c9 VS |
14999 | |
15000 | intel_backlight_register(dev); | |
79e53945 JB |
15001 | } |
15002 | ||
4932e2c3 ID |
15003 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15004 | { | |
15005 | struct drm_connector *connector = &intel_connector->base; | |
15006 | ||
15007 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15008 | drm_connector_unregister(connector); |
4932e2c3 ID |
15009 | } |
15010 | ||
79e53945 JB |
15011 | void intel_modeset_cleanup(struct drm_device *dev) |
15012 | { | |
652c393a | 15013 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15014 | struct drm_connector *connector; |
652c393a | 15015 | |
2eb5252e ID |
15016 | intel_disable_gt_powersave(dev); |
15017 | ||
0962c3c9 VS |
15018 | intel_backlight_unregister(dev); |
15019 | ||
fd0c0642 DV |
15020 | /* |
15021 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15022 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15023 | * experience fancy races otherwise. |
15024 | */ | |
2aeb7d3a | 15025 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15026 | |
fd0c0642 DV |
15027 | /* |
15028 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15029 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15030 | */ | |
f87ea761 | 15031 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15032 | |
652c393a JB |
15033 | mutex_lock(&dev->struct_mutex); |
15034 | ||
723bfd70 JB |
15035 | intel_unregister_dsm_handler(); |
15036 | ||
7ff0ebcc | 15037 | intel_fbc_disable(dev); |
e70236a8 | 15038 | |
69341a5e KH |
15039 | mutex_unlock(&dev->struct_mutex); |
15040 | ||
1630fe75 CW |
15041 | /* flush any delayed tasks or pending work */ |
15042 | flush_scheduled_work(); | |
15043 | ||
db31af1d JN |
15044 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15045 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15046 | struct intel_connector *intel_connector; |
15047 | ||
15048 | intel_connector = to_intel_connector(connector); | |
15049 | intel_connector->unregister(intel_connector); | |
db31af1d | 15050 | } |
d9255d57 | 15051 | |
79e53945 | 15052 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15053 | |
15054 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15055 | |
15056 | mutex_lock(&dev->struct_mutex); | |
15057 | intel_cleanup_gt_powersave(dev); | |
15058 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15059 | } |
15060 | ||
f1c79df3 ZW |
15061 | /* |
15062 | * Return which encoder is currently attached for connector. | |
15063 | */ | |
df0e9248 | 15064 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15065 | { |
df0e9248 CW |
15066 | return &intel_attached_encoder(connector)->base; |
15067 | } | |
f1c79df3 | 15068 | |
df0e9248 CW |
15069 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15070 | struct intel_encoder *encoder) | |
15071 | { | |
15072 | connector->encoder = encoder; | |
15073 | drm_mode_connector_attach_encoder(&connector->base, | |
15074 | &encoder->base); | |
79e53945 | 15075 | } |
28d52043 DA |
15076 | |
15077 | /* | |
15078 | * set vga decode state - true == enable VGA decode | |
15079 | */ | |
15080 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15081 | { | |
15082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15083 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15084 | u16 gmch_ctrl; |
15085 | ||
75fa041d CW |
15086 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15087 | DRM_ERROR("failed to read control word\n"); | |
15088 | return -EIO; | |
15089 | } | |
15090 | ||
c0cc8a55 CW |
15091 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15092 | return 0; | |
15093 | ||
28d52043 DA |
15094 | if (state) |
15095 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15096 | else | |
15097 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15098 | |
15099 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15100 | DRM_ERROR("failed to write control word\n"); | |
15101 | return -EIO; | |
15102 | } | |
15103 | ||
28d52043 DA |
15104 | return 0; |
15105 | } | |
c4a1d9e4 | 15106 | |
c4a1d9e4 | 15107 | struct intel_display_error_state { |
ff57f1b0 PZ |
15108 | |
15109 | u32 power_well_driver; | |
15110 | ||
63b66e5b CW |
15111 | int num_transcoders; |
15112 | ||
c4a1d9e4 CW |
15113 | struct intel_cursor_error_state { |
15114 | u32 control; | |
15115 | u32 position; | |
15116 | u32 base; | |
15117 | u32 size; | |
52331309 | 15118 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15119 | |
15120 | struct intel_pipe_error_state { | |
ddf9c536 | 15121 | bool power_domain_on; |
c4a1d9e4 | 15122 | u32 source; |
f301b1e1 | 15123 | u32 stat; |
52331309 | 15124 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15125 | |
15126 | struct intel_plane_error_state { | |
15127 | u32 control; | |
15128 | u32 stride; | |
15129 | u32 size; | |
15130 | u32 pos; | |
15131 | u32 addr; | |
15132 | u32 surface; | |
15133 | u32 tile_offset; | |
52331309 | 15134 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15135 | |
15136 | struct intel_transcoder_error_state { | |
ddf9c536 | 15137 | bool power_domain_on; |
63b66e5b CW |
15138 | enum transcoder cpu_transcoder; |
15139 | ||
15140 | u32 conf; | |
15141 | ||
15142 | u32 htotal; | |
15143 | u32 hblank; | |
15144 | u32 hsync; | |
15145 | u32 vtotal; | |
15146 | u32 vblank; | |
15147 | u32 vsync; | |
15148 | } transcoder[4]; | |
c4a1d9e4 CW |
15149 | }; |
15150 | ||
15151 | struct intel_display_error_state * | |
15152 | intel_display_capture_error_state(struct drm_device *dev) | |
15153 | { | |
fbee40df | 15154 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15155 | struct intel_display_error_state *error; |
63b66e5b CW |
15156 | int transcoders[] = { |
15157 | TRANSCODER_A, | |
15158 | TRANSCODER_B, | |
15159 | TRANSCODER_C, | |
15160 | TRANSCODER_EDP, | |
15161 | }; | |
c4a1d9e4 CW |
15162 | int i; |
15163 | ||
63b66e5b CW |
15164 | if (INTEL_INFO(dev)->num_pipes == 0) |
15165 | return NULL; | |
15166 | ||
9d1cb914 | 15167 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15168 | if (error == NULL) |
15169 | return NULL; | |
15170 | ||
190be112 | 15171 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15172 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15173 | ||
055e393f | 15174 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15175 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15176 | __intel_display_power_is_enabled(dev_priv, |
15177 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15178 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15179 | continue; |
15180 | ||
5efb3e28 VS |
15181 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15182 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15183 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15184 | |
15185 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15186 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15187 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15188 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15189 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15190 | } | |
ca291363 PZ |
15191 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15192 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15193 | if (INTEL_INFO(dev)->gen >= 4) { |
15194 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15195 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15196 | } | |
15197 | ||
c4a1d9e4 | 15198 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15199 | |
3abfce77 | 15200 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15201 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15202 | } |
15203 | ||
15204 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15205 | if (HAS_DDI(dev_priv->dev)) | |
15206 | error->num_transcoders++; /* Account for eDP. */ | |
15207 | ||
15208 | for (i = 0; i < error->num_transcoders; i++) { | |
15209 | enum transcoder cpu_transcoder = transcoders[i]; | |
15210 | ||
ddf9c536 | 15211 | error->transcoder[i].power_domain_on = |
f458ebbc | 15212 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15213 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15214 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15215 | continue; |
15216 | ||
63b66e5b CW |
15217 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15218 | ||
15219 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15220 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15221 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15222 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15223 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15224 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15225 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15226 | } |
15227 | ||
15228 | return error; | |
15229 | } | |
15230 | ||
edc3d884 MK |
15231 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15232 | ||
c4a1d9e4 | 15233 | void |
edc3d884 | 15234 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15235 | struct drm_device *dev, |
15236 | struct intel_display_error_state *error) | |
15237 | { | |
055e393f | 15238 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15239 | int i; |
15240 | ||
63b66e5b CW |
15241 | if (!error) |
15242 | return; | |
15243 | ||
edc3d884 | 15244 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15245 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15246 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15247 | error->power_well_driver); |
055e393f | 15248 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15249 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15250 | err_printf(m, " Power: %s\n", |
15251 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15252 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15253 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15254 | |
15255 | err_printf(m, "Plane [%d]:\n", i); | |
15256 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15257 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15258 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15259 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15260 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15261 | } |
4b71a570 | 15262 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15263 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15264 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15265 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15266 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15267 | } |
15268 | ||
edc3d884 MK |
15269 | err_printf(m, "Cursor [%d]:\n", i); |
15270 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15271 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15272 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15273 | } |
63b66e5b CW |
15274 | |
15275 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15276 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15277 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15278 | err_printf(m, " Power: %s\n", |
15279 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15280 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15281 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15282 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15283 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15284 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15285 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15286 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15287 | } | |
c4a1d9e4 | 15288 | } |
e2fcdaa9 VS |
15289 | |
15290 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15291 | { | |
15292 | struct intel_crtc *crtc; | |
15293 | ||
15294 | for_each_intel_crtc(dev, crtc) { | |
15295 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15296 | |
5e2d7afc | 15297 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15298 | |
15299 | work = crtc->unpin_work; | |
15300 | ||
15301 | if (work && work->event && | |
15302 | work->event->base.file_priv == file) { | |
15303 | kfree(work->event); | |
15304 | work->event = NULL; | |
15305 | } | |
15306 | ||
5e2d7afc | 15307 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15308 | } |
15309 | } |