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drm/i915: BDW clock change support
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS		 1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML		 1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS		 2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS		 2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS		 2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB		 2233}
2234
693db184
CW		 2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU		 2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU		 2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL		 2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL		 2266 tile_height = 64;
2267 break;
6761dd31
TU		 2268 case 2:
2269 case 4:
b5d0e9bf
DL		 2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL		 2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL		 2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU		 2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB		 2297}
2298
f64b98cd
TU		 2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU		 2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU		 2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU		 2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU		 2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH		 2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR		 2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU		 2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU		 2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH		 2367 }
2368
f64b98cd
TU		 2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW		 2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ		 2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH		 2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH		 2417}
2418
82bc3b2d
TU		 2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR		 2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU		 2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2433}
2434
c2c75131
DV		 2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW		 2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV		 2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL		 2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV		 2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV		 2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL		 2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL		 2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB		 2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB		 2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2558 return false;
2559}
2560
afd65eb4
MR		 2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV		 2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV		 2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB		 2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB		 2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB		 2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR		 2607 if (!i->active)
2608 continue;
2609
88595ac9
DV		 2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB		 2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB		 2618 }
2619 }
88595ac9
DV		 2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2633}
2634
29b9bde6
DV		 2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB		 2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS		 2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS		 2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS		 2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS		 2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV		 2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV		 2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO		 2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO		 2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB		 2759}
2760
29b9bde6
DV		 2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB		 2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS		 2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS		 2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS		 2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS		 2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB		 2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS		 2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB		 2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO		 2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB		 2859}
2860
b321803d
DL		 2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU		 2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU		 2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK		 2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK		 2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK		 2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ		 2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK		 3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK		 3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK		 3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK		 3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK		 3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL		 3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ		 3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK		 3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ		 3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB		 3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW		 3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV		 3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB		 3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS		 3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS		 3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS		 3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR		 3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3175 }
3176}
3177
ce22dba9
ML		 3178void intel_crtc_reset(struct intel_crtc *crtc)
3179{
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189}
3190
7514747d
VS		 3191void intel_prepare_reset(struct drm_device *dev)
3192{
f98ce92f
VS		 3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
7514747d
VS		 3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS		 3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3216 }
7514747d
VS		 3217}
3218
3219void intel_finish_reset(struct drm_device *dev)
3220{
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265}
3266
2e2f351d 3267static void
14667a4b
CW		 3268intel_finish_fb(struct drm_framebuffer *old_fb)
3269{
2ff8fde1 3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
14667a4b
CW		 3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
2e2f351d
CW		 3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
2e2f351d 3287 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3288 dev_priv->mm.interruptible = was_interruptible;
3289
2e2f351d 3290 WARN_ON(ret);
14667a4b
CW		 3291}
3292
7d5e3799
CW		 3293static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
5e2d7afc 3304 spin_lock_irq(&dev->event_lock);
7d5e3799 3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3306 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3307
3308 return pending;
3309}
3310
e30e8f75
GP		 3311static void intel_update_pipe_size(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
6e3c9717 3334 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3339 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
6e3c9717
ACO		 3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3348}
3349
5e84e1a4
ZW		 3350static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
61e499bf 3361 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3367 }
5e84e1a4
ZW		 3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
357555c0
JB		 3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3389}
3390
8db9d77b
ZW		 3391/* The FDI link training functions for ILK/Ibexpeak. */
3392static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
5eddb70b 3398 u32 reg, temp, tries;
8db9d77b 3399
1c8562f6 3400 /* FDI needs bits from pipe first */
0fc932b8 3401 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3402
e1a44743
AJ		 3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
5eddb70b
CW		 3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
e1a44743
AJ		 3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
e1a44743
AJ		 3411 udelay(150);
3412
8db9d77b 3413 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
627eb5a3 3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3421
5eddb70b
CW		 3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
8db9d77b
ZW		 3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
8db9d77b
ZW		 3429 udelay(150);
3430
5b2adf89 3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3435
5eddb70b 3436 reg = FDI_RX_IIR(pipe);
e1a44743 3437 for (tries = 0; tries < 5; tries++) {
5eddb70b 3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3444 break;
3445 }
8db9d77b 3446 }
e1a44743 3447 if (tries == 5)
5eddb70b 3448 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3449
3450 /* Train 2 */
5eddb70b
CW		 3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW		 3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3461 I915_WRITE(reg, temp);
8db9d77b 3462
5eddb70b
CW		 3463 POSTING_READ(reg);
3464 udelay(150);
8db9d77b 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3479
3480 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3481
8db9d77b
ZW		 3482}
3483
0206e353 3484static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489};
3490
3491/* The FDI link training functions for SNB/Cougarpoint. */
3492static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493{
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
fa37d39e 3498 u32 reg, temp, i, retry;
8db9d77b 3499
e1a44743
AJ		 3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
5eddb70b
CW		 3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
e1a44743
AJ		 3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
e1a44743
AJ		 3509 udelay(150);
3510
8db9d77b 3511 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
627eb5a3 3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3522
d74cf324
DV		 3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
5eddb70b
CW		 3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW		 3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
5eddb70b
CW		 3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
8db9d77b
ZW		 3538 udelay(150);
3539
0206e353 3540 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW		 3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW		 3548 udelay(500);
3549
fa37d39e
SP		 3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
8db9d77b 3560 }
fa37d39e
SP		 3561 if (retry < 5)
3562 break;
8db9d77b
ZW		 3563 }
3564 if (i == 4)
5eddb70b 3565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3566
3567 /* Train 2 */
5eddb70b
CW		 3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW		 3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
5eddb70b 3577 I915_WRITE(reg, temp);
8db9d77b 3578
5eddb70b
CW		 3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
8db9d77b
ZW		 3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
5eddb70b
CW		 3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
8db9d77b
ZW		 3591 udelay(150);
3592
0206e353 3593 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW		 3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
8db9d77b
ZW		 3601 udelay(500);
3602
fa37d39e
SP		 3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
8db9d77b 3613 }
fa37d39e
SP		 3614 if (retry < 5)
3615 break;
8db9d77b
ZW		 3616 }
3617 if (i == 4)
5eddb70b 3618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621}
3622
357555c0
JB		 3623/* Manual link training for Ivy Bridge A0 parts */
3624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
139ccd3f 3630 u32 reg, temp, i, j;
357555c0
JB		 3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
01a415fd
DV		 3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
139ccd3f
JB		 3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f
JB		 3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
357555c0 3661
139ccd3f 3662 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
139ccd3f 3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3672
139ccd3f
JB		 3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3675
139ccd3f 3676 reg = FDI_RX_CTL(pipe);
357555c0 3677 temp = I915_READ(reg);
139ccd3f
JB		 3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3681
139ccd3f
JB		 3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
357555c0 3684
139ccd3f
JB		 3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3689
139ccd3f
JB		 3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
357555c0 3703
139ccd3f 3704 /* Train 2 */
357555c0
JB		 3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
139ccd3f
JB		 3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
139ccd3f 3718 udelay(2); /* should be 1.5us */
357555c0 3719
139ccd3f
JB		 3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3724
139ccd3f
JB		 3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
357555c0 3733 }
139ccd3f
JB		 3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3736 }
357555c0 3737
139ccd3f 3738train_done:
357555c0
JB		 3739 DRM_DEBUG_KMS("FDI train done.\n");
3740}
3741
88cefb6c 3742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3743{
88cefb6c 3744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3746 int pipe = intel_crtc->pipe;
5eddb70b 3747 u32 reg, temp;
79e53945 3748
c64e311e 3749
c98e9dcf 3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
627eb5a3 3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB		 3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
c98e9dcf
JB		 3766 udelay(200);
3767
20749730
PZ		 3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3773
20749730
PZ		 3774 POSTING_READ(reg);
3775 udelay(100);
6be4a607 3776 }
0e23b99d
JB		 3777}
3778
88cefb6c
DV		 3779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780{
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806}
3807
0fc932b8
JB		 3808static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
dfd07d72 3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3832 if (HAS_PCH_IBX(dev))
6f06ce18 3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
dfd07d72 3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858}
3859
5dce5b93
CW		 3860bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861{
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
d3fcc808 3871 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882}
3883
d6bbafa1
CW		 3884static void page_flip_completed(struct intel_crtc *intel_crtc)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905}
3906
46a55d30 3907void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3908{
0f91128d 3909 struct drm_device *dev = crtc->dev;
5bb61643 3910 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3911
2c10d571 3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3917
5e2d7afc 3918 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
5e2d7afc 3923 spin_unlock_irq(&dev->event_lock);
9c787942 3924 }
5bb61643 3925
975d568a
CW		 3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
e6c3a2a6
CW		 3931}
3932
e615efe4
ED		 3933/* Program iCLKIP clock to the desired frequency */
3934static void lpt_program_iclkip(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
a580516d 3942 mutex_lock(&dev_priv->sb_lock);
09153000 3943
e615efe4
ED		 3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
e615efe4
ED		 3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3956 if (clock == 20000) {
e615efe4
ED		 3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
12d7ceed 3971 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3987 clock,
e615efe4
ED		 3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4002
4003 /* Program SSCAUXDIV */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4008
4009 /* Enable modulator and associated divider */
988d6ee8 4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4018
a580516d 4019 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4020}
4021
275f01b2
DV		 4022static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024{
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044}
4045
003632d9 4046static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4047{
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
003632d9
ACO		 4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065}
4066
4067static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068{
4069 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
6e3c9717 4075 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4077 else
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4079
4080 break;
4081 case PIPE_C:
003632d9 4082 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088}
4089
f67a559d
JB		 4090/*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4099{
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
ee7b9f93 4104 u32 reg, temp;
2c07245f 4105
ab9412ba 4106 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4107
1fbc0d78
DV		 4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
cd986abb
DV		 4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
c98e9dcf 4116 /* For PCH output, training FDI link */
674cf967 4117 dev_priv->display.fdi_link_train(crtc);
2c07245f 4118
3ad8a208
DV		 4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
303b81e0 4121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4122 u32 sel;
4b645f14 4123
c98e9dcf 4124 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4128 temp |= sel;
4129 else
4130 temp &= ~sel;
c98e9dcf 4131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4132 }
5eddb70b 4133
3ad8a208
DV		 4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
85b3894f 4141 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4142
d9b6cb56
JB		 4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4146
303b81e0 4147 intel_fdi_normal_train(crtc);
5e84e1a4 4148
c98e9dcf 4149 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
e3ef4479 4157 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4158 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4168 break;
4169 case PCH_DP_C:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4171 break;
4172 case PCH_DP_D:
5eddb70b 4173 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4174 break;
4175 default:
e95d41e1 4176 BUG();
32f9d658 4177 }
2c07245f 4178
5eddb70b 4179 I915_WRITE(reg, temp);
6be4a607 4180 }
b52eb4dc 4181
b8a4f404 4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4183}
4184
1507e5bd
PZ		 4185static void lpt_pch_enable(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4191
ab9412ba 4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4193
8c52b5e8 4194 lpt_program_iclkip(crtc);
1507e5bd 4195
0540e488 4196 /* Set transcoder timing. */
275f01b2 4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4198
937bb610 4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4200}
4201
716c2e55 4202void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4203{
e2b78267 4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4205
4206 if (pll == NULL)
4207 return;
4208
3e369b76 4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4210 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4211 return;
4212 }
4213
3e369b76
ACO		 4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
6e3c9717 4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4221}
4222
190f68c5
ACO		 4223struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
ee7b9f93 4225{
e2b78267 4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4227 struct intel_shared_dpll *pll;
e2b78267 4228 enum intel_dpll_id i;
ee7b9f93 4229
98b6bd99
DV		 4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4232 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4233 pll = &dev_priv->shared_dplls[i];
98b6bd99 4234
46edb027
DV		 4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
98b6bd99 4237
8bd31e67 4238 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4239
98b6bd99
DV		 4240 goto found;
4241 }
4242
bcddf610
S		 4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
e72f9fbf
DV		 4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4265
4266 /* Only want to check enabled timings first */
8bd31e67 4267 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4268 continue;
4269
190f68c5 4270 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4274 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4275 pll->new_config->crtc_mask,
4276 pll->active);
ee7b9f93
JB		 4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
8bd31e67 4284 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293found:
8bd31e67 4294 if (pll->new_config->crtc_mask == 0)
190f68c5 4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4296
190f68c5 4297 crtc_state->shared_dpll = i;
46edb027
DV		 4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
ee7b9f93 4300
8bd31e67 4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4302
ee7b9f93
JB		 4303 return pll;
4304}
4305
8bd31e67
ACO		 4306/**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316{
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
f354d733 4336 kfree(pll->new_config);
8bd31e67
ACO		 4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341}
4342
4343static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357}
4358
4359static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360{
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
a1520318 4374static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4377 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4383 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4385 }
4386}
4387
a1b2278e
CK		 4388/**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405int
4406skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410{
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
6156a456 4417 unsigned int rotation;
a1b2278e
CK		 4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
6156a456 4433 rotation = plane_state->base.rotation;
a1b2278e
CK		 4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
6156a456 4442 rotation = DRM_ROTATE_0;
a1b2278e 4443 }
6156a456
CK		 4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
225c228a
CK		 4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
a1b2278e 4507 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528}
4529
4530static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4531{
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
a1b2278e
CK		 4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
bd2e244f 4546
6e3c9717 4547 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4562 }
4563}
4564
b074cec8
JB		 4565static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566{
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
6e3c9717 4571 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4583 }
4584}
4585
4a3b8769 4586static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4587{
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4590 struct drm_plane *plane;
bb53d4ae
VS		 4591 struct intel_plane *intel_plane;
4592
af2b653b
MR		 4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
af2b653b 4597 }
bb53d4ae
VS		 4598}
4599
20bc8673 4600void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4601{
cea165c3
VS		 4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4604
6e3c9717 4605 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4606 return;
4607
cea165c3
VS		 4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
d77e4531 4611 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4612 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
2a114cc1
BW		 4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
d77e4531
PZ		 4631}
4632
20bc8673 4633void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4634{
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
6e3c9717 4638 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4642 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4649 } else {
2a114cc1 4650 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4651 POSTING_READ(IPS_CTL);
4652 }
d77e4531
PZ		 4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656}
4657
4658/** Loads the palette/gamma unit for the CRTC with the prepared values */
4659static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660{
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
83d65738 4670 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4671 return;
4672
50360403 4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
7a1db49a 4681 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
6e3c9717 4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703}
4704
7cac945f 4705static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4706{
7cac945f 4707 if (intel_crtc->overlay) {
d3eedb1a
VS		 4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721}
4722
87d4300a
ML		 4723/**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733static void
4734intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4735{
4736 struct drm_device *dev = crtc->dev;
87d4300a 4737 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
a5c4d7bc 4740
87d4300a
ML		 4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4748
87d4300a
ML		 4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
a5c4d7bc
VS		 4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4758 intel_fbc_update(dev);
a5c4d7bc 4759 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4760
4761 /*
87d4300a
ML		 4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
f99d7069 4767 */
87d4300a
ML		 4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4774}
4775
87d4300a
ML		 4776/**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786static void
4787intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
a5c4d7bc 4793
87d4300a
ML		 4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4802
87d4300a
ML		 4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
e35fef21 4816 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4817 intel_fbc_disable(dev);
87d4300a 4818 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4819
87d4300a
ML		 4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
a5c4d7bc 4826 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4827}
4828
4829static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830{
2d847d45
RV		 4831 struct drm_device *dev = crtc->dev;
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833 int pipe = intel_crtc->pipe;
4834
87d4300a
ML		 4835 intel_enable_primary_hw_plane(crtc->primary, crtc);
4836 intel_enable_sprite_planes(crtc);
4837 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4838
4839 intel_post_enable_primary(crtc);
2d847d45
RV		 4840
4841 /*
4842 * FIXME: Once we grow proper nuclear flip support out of this we need
4843 * to compute the mask of flip planes precisely. For the time being
4844 * consider this a flip to a NULL plane.
4845 */
4846 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4847}
4848
4849static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4850{
4851 struct drm_device *dev = crtc->dev;
4852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853 struct intel_plane *intel_plane;
4854 int pipe = intel_crtc->pipe;
4855
4856 intel_crtc_wait_for_pending_flips(crtc);
4857
4858 intel_pre_disable_primary(crtc);
a5c4d7bc 4859
7cac945f 4860 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4861 for_each_intel_plane(dev, intel_plane) {
4862 if (intel_plane->pipe == pipe) {
4863 struct drm_crtc *from = intel_plane->base.crtc;
4864
4865 intel_plane->disable_plane(&intel_plane->base,
4866 from ?: crtc, true);
4867 }
4868 }
f98551ae 4869
f99d7069
DV		 4870 /*
4871 * FIXME: Once we grow proper nuclear flip support out of this we need
4872 * to compute the mask of flip planes precisely. For the time being
4873 * consider this a flip to a NULL plane.
4874 */
4875 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4876}
4877
f67a559d
JB		 4878static void ironlake_crtc_enable(struct drm_crtc *crtc)
4879{
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4883 struct intel_encoder *encoder;
f67a559d 4884 int pipe = intel_crtc->pipe;
f67a559d 4885
83d65738 4886 WARN_ON(!crtc->state->enable);
08a48469 4887
f67a559d
JB		 4888 if (intel_crtc->active)
4889 return;
4890
6e3c9717 4891 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4892 intel_prepare_shared_dpll(intel_crtc);
4893
6e3c9717 4894 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4895 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4896
4897 intel_set_pipe_timings(intel_crtc);
4898
6e3c9717 4899 if (intel_crtc->config->has_pch_encoder) {
29407aab 4900 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4901 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4902 }
4903
4904 ironlake_set_pipeconf(crtc);
4905
f67a559d 4906 intel_crtc->active = true;
8664281b 4907
a72e4c9f
DV		 4908 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4909 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4910
f6736a1a 4911 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4912 if (encoder->pre_enable)
4913 encoder->pre_enable(encoder);
f67a559d 4914
6e3c9717 4915 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4916 /* Note: FDI PLL enabling _must_ be done before we enable the
4917 * cpu pipes, hence this is separate from all the other fdi/pch
4918 * enabling. */
88cefb6c 4919 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4920 } else {
4921 assert_fdi_tx_disabled(dev_priv, pipe);
4922 assert_fdi_rx_disabled(dev_priv, pipe);
4923 }
f67a559d 4924
b074cec8 4925 ironlake_pfit_enable(intel_crtc);
f67a559d 4926
9c54c0dd
JB		 4927 /*
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4929 * clocks enabled
4930 */
4931 intel_crtc_load_lut(crtc);
4932
f37fcc2a 4933 intel_update_watermarks(crtc);
e1fdc473 4934 intel_enable_pipe(intel_crtc);
f67a559d 4935
6e3c9717 4936 if (intel_crtc->config->has_pch_encoder)
f67a559d 4937 ironlake_pch_enable(crtc);
c98e9dcf 4938
f9b61ff6
DV		 4939 assert_vblank_disabled(crtc);
4940 drm_crtc_vblank_on(crtc);
4941
fa5c73b1
DV		 4942 for_each_encoder_on_crtc(dev, crtc, encoder)
4943 encoder->enable(encoder);
61b77ddd
DV		 4944
4945 if (HAS_PCH_CPT(dev))
a1520318 4946 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4947}
4948
42db64ef
PZ		 4949/* IPS only exists on ULT machines and is tied to pipe A. */
4950static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4951{
f5adf94e 4952 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4953}
4954
e4916946
PZ		 4955/*
4956 * This implements the workaround described in the "notes" section of the mode
4957 * set sequence documentation. When going from no pipes or single pipe to
4958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4960 */
4961static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4962{
4963 struct drm_device *dev = crtc->base.dev;
4964 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4965
4966 /* We want to get the other_active_crtc only if there's only 1 other
4967 * active crtc. */
d3fcc808 4968 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4969 if (!crtc_it->active || crtc_it == crtc)
4970 continue;
4971
4972 if (other_active_crtc)
4973 return;
4974
4975 other_active_crtc = crtc_it;
4976 }
4977 if (!other_active_crtc)
4978 return;
4979
4980 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4981 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4982}
4983
4f771f10
PZ		 4984static void haswell_crtc_enable(struct drm_crtc *crtc)
4985{
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989 struct intel_encoder *encoder;
4990 int pipe = intel_crtc->pipe;
4f771f10 4991
83d65738 4992 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4993
4994 if (intel_crtc->active)
4995 return;
4996
df8ad70c
DV		 4997 if (intel_crtc_to_shared_dpll(intel_crtc))
4998 intel_enable_shared_dpll(intel_crtc);
4999
6e3c9717 5000 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5001 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5002
5003 intel_set_pipe_timings(intel_crtc);
5004
6e3c9717
ACO		 5005 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5006 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5007 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5008 }
5009
6e3c9717 5010 if (intel_crtc->config->has_pch_encoder) {
229fca97 5011 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5012 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5013 }
5014
5015 haswell_set_pipeconf(crtc);
5016
5017 intel_set_pipe_csc(crtc);
5018
4f771f10 5019 intel_crtc->active = true;
8664281b 5020
a72e4c9f 5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->pre_enable)
5024 encoder->pre_enable(encoder);
5025
6e3c9717 5026 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5027 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5028 true);
4fe9467d
ID		 5029 dev_priv->display.fdi_link_train(crtc);
5030 }
5031
1f544388 5032 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5033
ff6d9f55 5034 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5035 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5036 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5037 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5038 else
5039 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5040
5041 /*
5042 * On ILK+ LUT must be loaded before the pipe is running but with
5043 * clocks enabled
5044 */
5045 intel_crtc_load_lut(crtc);
5046
1f544388 5047 intel_ddi_set_pipe_settings(crtc);
8228c251 5048 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5049
f37fcc2a 5050 intel_update_watermarks(crtc);
e1fdc473 5051 intel_enable_pipe(intel_crtc);
42db64ef 5052
6e3c9717 5053 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5054 lpt_pch_enable(crtc);
4f771f10 5055
6e3c9717 5056 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5057 intel_ddi_set_vc_payload_alloc(crtc, true);
5058
f9b61ff6
DV		 5059 assert_vblank_disabled(crtc);
5060 drm_crtc_vblank_on(crtc);
5061
8807e55b 5062 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5063 encoder->enable(encoder);
8807e55b
JN		 5064 intel_opregion_notify_encoder(encoder, true);
5065 }
4f771f10 5066
e4916946
PZ		 5067 /* If we change the relative order between pipe/planes enabling, we need
5068 * to change the workaround. */
5069 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5070}
5071
3f8dce3a
DV		 5072static void ironlake_pfit_disable(struct intel_crtc *crtc)
5073{
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 int pipe = crtc->pipe;
5077
5078 /* To avoid upsetting the power well on haswell only disable the pfit if
5079 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5080 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5081 I915_WRITE(PF_CTL(pipe), 0);
5082 I915_WRITE(PF_WIN_POS(pipe), 0);
5083 I915_WRITE(PF_WIN_SZ(pipe), 0);
5084 }
5085}
5086
6be4a607
JB		 5087static void ironlake_crtc_disable(struct drm_crtc *crtc)
5088{
5089 struct drm_device *dev = crtc->dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5092 struct intel_encoder *encoder;
6be4a607 5093 int pipe = intel_crtc->pipe;
5eddb70b 5094 u32 reg, temp;
b52eb4dc 5095
f7abfe8b
CW		 5096 if (!intel_crtc->active)
5097 return;
5098
ea9d758d
DV		 5099 for_each_encoder_on_crtc(dev, crtc, encoder)
5100 encoder->disable(encoder);
5101
f9b61ff6
DV		 5102 drm_crtc_vblank_off(crtc);
5103 assert_vblank_disabled(crtc);
5104
6e3c9717 5105 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5106 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5107
575f7ab7 5108 intel_disable_pipe(intel_crtc);
32f9d658 5109
3f8dce3a 5110 ironlake_pfit_disable(intel_crtc);
2c07245f 5111
5a74f70a
VS		 5112 if (intel_crtc->config->has_pch_encoder)
5113 ironlake_fdi_disable(crtc);
5114
bf49ec8c
DV		 5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
2c07245f 5118
6e3c9717 5119 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5121
d925c59a
DV		 5122 if (HAS_PCH_CPT(dev)) {
5123 /* disable TRANS_DP_CTL */
5124 reg = TRANS_DP_CTL(pipe);
5125 temp = I915_READ(reg);
5126 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5127 TRANS_DP_PORT_SEL_MASK);
5128 temp |= TRANS_DP_PORT_SEL_NONE;
5129 I915_WRITE(reg, temp);
5130
5131 /* disable DPLL_SEL */
5132 temp = I915_READ(PCH_DPLL_SEL);
11887397 5133 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5134 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5135 }
e3421a18 5136
d925c59a 5137 /* disable PCH DPLL */
e72f9fbf 5138 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5139
d925c59a
DV		 5140 ironlake_fdi_pll_disable(intel_crtc);
5141 }
6b383a7f 5142
f7abfe8b 5143 intel_crtc->active = false;
46ba614c 5144 intel_update_watermarks(crtc);
d1ebd816
BW		 5145
5146 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5147 intel_fbc_update(dev);
d1ebd816 5148 mutex_unlock(&dev->struct_mutex);
6be4a607 5149}
1b3c7a47 5150
4f771f10 5151static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5152{
4f771f10
PZ		 5153 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5156 struct intel_encoder *encoder;
6e3c9717 5157 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5158
4f771f10
PZ		 5159 if (!intel_crtc->active)
5160 return;
5161
8807e55b
JN		 5162 for_each_encoder_on_crtc(dev, crtc, encoder) {
5163 intel_opregion_notify_encoder(encoder, false);
4f771f10 5164 encoder->disable(encoder);
8807e55b 5165 }
4f771f10 5166
f9b61ff6
DV		 5167 drm_crtc_vblank_off(crtc);
5168 assert_vblank_disabled(crtc);
5169
6e3c9717 5170 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5171 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5172 false);
575f7ab7 5173 intel_disable_pipe(intel_crtc);
4f771f10 5174
6e3c9717 5175 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5176 intel_ddi_set_vc_payload_alloc(crtc, false);
5177
ad80a810 5178 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5179
ff6d9f55 5180 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5181 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5182 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5183 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5184 else
5185 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5186
1f544388 5187 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5188
6e3c9717 5189 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5190 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5191 intel_ddi_fdi_disable(crtc);
83616634 5192 }
4f771f10 5193
97b040aa
ID		 5194 for_each_encoder_on_crtc(dev, crtc, encoder)
5195 if (encoder->post_disable)
5196 encoder->post_disable(encoder);
5197
4f771f10 5198 intel_crtc->active = false;
46ba614c 5199 intel_update_watermarks(crtc);
4f771f10
PZ		 5200
5201 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5202 intel_fbc_update(dev);
4f771f10 5203 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5204
5205 if (intel_crtc_to_shared_dpll(intel_crtc))
5206 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5207}
5208
ee7b9f93
JB		 5209static void ironlake_crtc_off(struct drm_crtc *crtc)
5210{
5211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5212 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5213}
5214
6441ab5f 5215
2dd24552
JB		 5216static void i9xx_pfit_enable(struct intel_crtc *crtc)
5217{
5218 struct drm_device *dev = crtc->base.dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5220 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5221
681a8504 5222 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5223 return;
5224
2dd24552 5225 /*
c0b03411
DV		 5226 * The panel fitter should only be adjusted whilst the pipe is disabled,
5227 * according to register description and PRM.
2dd24552 5228 */
c0b03411
DV		 5229 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5230 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5231
b074cec8
JB		 5232 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5233 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5234
5235 /* Border color in case we don't scale up to the full screen. Black by
5236 * default, change to something else for debugging. */
5237 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5238}
5239
d05410f9
DA		 5240static enum intel_display_power_domain port_to_power_domain(enum port port)
5241{
5242 switch (port) {
5243 case PORT_A:
5244 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5245 case PORT_B:
5246 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5247 case PORT_C:
5248 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5249 case PORT_D:
5250 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5251 default:
5252 WARN_ON_ONCE(1);
5253 return POWER_DOMAIN_PORT_OTHER;
5254 }
5255}
5256
77d22dca
ID		 5257#define for_each_power_domain(domain, mask) \
5258 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5259 if ((1 << (domain)) & (mask))
5260
319be8ae
ID		 5261enum intel_display_power_domain
5262intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5263{
5264 struct drm_device *dev = intel_encoder->base.dev;
5265 struct intel_digital_port *intel_dig_port;
5266
5267 switch (intel_encoder->type) {
5268 case INTEL_OUTPUT_UNKNOWN:
5269 /* Only DDI platforms should ever use this output type */
5270 WARN_ON_ONCE(!HAS_DDI(dev));
5271 case INTEL_OUTPUT_DISPLAYPORT:
5272 case INTEL_OUTPUT_HDMI:
5273 case INTEL_OUTPUT_EDP:
5274 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5275 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5276 case INTEL_OUTPUT_DP_MST:
5277 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5278 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5279 case INTEL_OUTPUT_ANALOG:
5280 return POWER_DOMAIN_PORT_CRT;
5281 case INTEL_OUTPUT_DSI:
5282 return POWER_DOMAIN_PORT_DSI;
5283 default:
5284 return POWER_DOMAIN_PORT_OTHER;
5285 }
5286}
5287
5288static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5289{
319be8ae
ID		 5290 struct drm_device *dev = crtc->dev;
5291 struct intel_encoder *intel_encoder;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5294 unsigned long mask;
5295 enum transcoder transcoder;
5296
5297 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5298
5299 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5300 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5301 if (intel_crtc->config->pch_pfit.enabled ||
5302 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5303 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5304
319be8ae
ID		 5305 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5306 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5307
77d22dca
ID		 5308 return mask;
5309}
5310
679dacd4 5311static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5312{
679dacd4 5313 struct drm_device *dev = state->dev;
77d22dca
ID		 5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5316 struct intel_crtc *crtc;
5317
5318 /*
5319 * First get all needed power domains, then put all unneeded, to avoid
5320 * any unnecessary toggling of the power wells.
5321 */
d3fcc808 5322 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5323 enum intel_display_power_domain domain;
5324
83d65738 5325 if (!crtc->base.state->enable)
77d22dca
ID		 5326 continue;
5327
319be8ae 5328 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5329
5330 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5331 intel_display_power_get(dev_priv, domain);
5332 }
5333
50f6e502 5334 if (dev_priv->display.modeset_global_resources)
679dacd4 5335 dev_priv->display.modeset_global_resources(state);
50f6e502 5336
d3fcc808 5337 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5338 enum intel_display_power_domain domain;
5339
5340 for_each_power_domain(domain, crtc->enabled_power_domains)
5341 intel_display_power_put(dev_priv, domain);
5342
5343 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5344 }
5345
5346 intel_display_set_init_power(dev_priv, false);
5347}
5348
f8437dd1
VK		 5349void broxton_set_cdclk(struct drm_device *dev, int frequency)
5350{
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t divider;
5353 uint32_t ratio;
5354 uint32_t current_freq;
5355 int ret;
5356
5357 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358 switch (frequency) {
5359 case 144000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 288000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 384000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 576000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 624000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(65);
5378 break;
5379 case 19200:
5380 /*
5381 * Bypass frequency with DE PLL disabled. Init ratio, divider
5382 * to suppress GCC warning.
5383 */
5384 ratio = 0;
5385 divider = 0;
5386 break;
5387 default:
5388 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->rps.hw_lock);
5394 /* Inform power controller of upcoming frequency change */
5395 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 0x80000000);
5397 mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399 if (ret) {
5400 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401 ret, frequency);
5402 return;
5403 }
5404
5405 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407 current_freq = current_freq * 500 + 1000;
5408
5409 /*
5410 * DE PLL has to be disabled when
5411 * - setting to 19.2MHz (bypass, PLL isn't used)
5412 * - before setting to 624MHz (PLL needs toggling)
5413 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 */
5415 if (frequency == 19200 || frequency == 624000 ||
5416 current_freq == 624000) {
5417 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 /* Timeout 200us */
5419 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 1))
5421 DRM_ERROR("timout waiting for DE PLL unlock\n");
5422 }
5423
5424 if (frequency != 19200) {
5425 uint32_t val;
5426
5427 val = I915_READ(BXT_DE_PLL_CTL);
5428 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 val |= ratio;
5430 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 /* Timeout 200us */
5434 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437 val = I915_READ(CDCLK_CTL);
5438 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439 val |= divider;
5440 /*
5441 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442 * enable otherwise.
5443 */
5444 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 if (frequency >= 500000)
5446 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450 val |= (frequency - 1000) / 500;
5451 I915_WRITE(CDCLK_CTL, val);
5452 }
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456 DIV_ROUND_UP(frequency, 25000));
5457 mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459 if (ret) {
5460 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461 ret, frequency);
5462 return;
5463 }
5464
5465 dev_priv->cdclk_freq = frequency;
5466}
5467
5468void broxton_init_cdclk(struct drm_device *dev)
5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t val;
5472
5473 /*
5474 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475 * or else the reset will hang because there is no PCH to respond.
5476 * Move the handshake programming to initialization sequence.
5477 * Previously was left up to BIOS.
5478 */
5479 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483 /* Enable PG1 for cdclk */
5484 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486 /* check if cd clock is enabled */
5487 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488 DRM_DEBUG_KMS("Display already initialized\n");
5489 return;
5490 }
5491
5492 /*
5493 * FIXME:
5494 * - The initial CDCLK needs to be read from VBT.
5495 * Need to make this change after VBT has changes for BXT.
5496 * - check if setting the max (or any) cdclk freq is really necessary
5497 * here, it belongs to modeset time
5498 */
5499 broxton_set_cdclk(dev, 624000);
5500
5501 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5502 POSTING_READ(DBUF_CTL);
5503
f8437dd1
VK		 5504 udelay(10);
5505
5506 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507 DRM_ERROR("DBuf power enable timeout!\n");
5508}
5509
5510void broxton_uninit_cdclk(struct drm_device *dev)
5511{
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5515 POSTING_READ(DBUF_CTL);
5516
f8437dd1
VK		 5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev, 19200);
5524
5525 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526}
5527
5d96d8af
DL		 5528static const struct skl_cdclk_entry {
5529 unsigned int freq;
5530 unsigned int vco;
5531} skl_cdclk_frequencies[] = {
5532 { .freq = 308570, .vco = 8640 },
5533 { .freq = 337500, .vco = 8100 },
5534 { .freq = 432000, .vco = 8640 },
5535 { .freq = 450000, .vco = 8100 },
5536 { .freq = 540000, .vco = 8100 },
5537 { .freq = 617140, .vco = 8640 },
5538 { .freq = 675000, .vco = 8100 },
5539};
5540
5541static unsigned int skl_cdclk_decimal(unsigned int freq)
5542{
5543 return (freq - 1000) / 500;
5544}
5545
5546static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547{
5548 unsigned int i;
5549
5550 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553 if (e->freq == freq)
5554 return e->vco;
5555 }
5556
5557 return 8100;
5558}
5559
5560static void
5561skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562{
5563 unsigned int min_freq;
5564 u32 val;
5565
5566 /* select the minimum CDCLK before enabling DPLL 0 */
5567 val = I915_READ(CDCLK_CTL);
5568 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569 val |= CDCLK_FREQ_337_308;
5570
5571 if (required_vco == 8640)
5572 min_freq = 308570;
5573 else
5574 min_freq = 337500;
5575
5576 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578 I915_WRITE(CDCLK_CTL, val);
5579 POSTING_READ(CDCLK_CTL);
5580
5581 /*
5582 * We always enable DPLL0 with the lowest link rate possible, but still
5583 * taking into account the VCO required to operate the eDP panel at the
5584 * desired frequency. The usual DP link rates operate with a VCO of
5585 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586 * The modeset code is responsible for the selection of the exact link
5587 * rate later on, with the constraint of choosing a frequency that
5588 * works with required_vco.
5589 */
5590 val = I915_READ(DPLL_CTRL1);
5591
5592 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595 if (required_vco == 8640)
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597 SKL_DPLL0);
5598 else
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600 SKL_DPLL0);
5601
5602 I915_WRITE(DPLL_CTRL1, val);
5603 POSTING_READ(DPLL_CTRL1);
5604
5605 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608 DRM_ERROR("DPLL0 not locked\n");
5609}
5610
5611static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612{
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623}
5624
5625static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626{
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636}
5637
5638static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639{
5640 u32 freq_select, pcu_ack;
5641
5642 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5643
5644 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5645 DRM_ERROR("failed to inform PCU about cdclk change\n");
5646 return;
5647 }
5648
5649 /* set CDCLK_CTL */
5650 switch(freq) {
5651 case 450000:
5652 case 432000:
5653 freq_select = CDCLK_FREQ_450_432;
5654 pcu_ack = 1;
5655 break;
5656 case 540000:
5657 freq_select = CDCLK_FREQ_540;
5658 pcu_ack = 2;
5659 break;
5660 case 308570:
5661 case 337500:
5662 default:
5663 freq_select = CDCLK_FREQ_337_308;
5664 pcu_ack = 0;
5665 break;
5666 case 617140:
5667 case 675000:
5668 freq_select = CDCLK_FREQ_675_617;
5669 pcu_ack = 3;
5670 break;
5671 }
5672
5673 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5674 POSTING_READ(CDCLK_CTL);
5675
5676 /* inform PCU of the change */
5677 mutex_lock(&dev_priv->rps.hw_lock);
5678 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5679 mutex_unlock(&dev_priv->rps.hw_lock);
5680}
5681
5682void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5683{
5684 /* disable DBUF power */
5685 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5686 POSTING_READ(DBUF_CTL);
5687
5688 udelay(10);
5689
5690 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5691 DRM_ERROR("DBuf power disable timeout\n");
5692
5693 /* disable DPLL0 */
5694 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5695 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5696 DRM_ERROR("Couldn't disable DPLL0\n");
5697
5698 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5699}
5700
5701void skl_init_cdclk(struct drm_i915_private *dev_priv)
5702{
5703 u32 val;
5704 unsigned int required_vco;
5705
5706 /* enable PCH reset handshake */
5707 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5708 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5709
5710 /* enable PG1 and Misc I/O */
5711 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5712
5713 /* DPLL0 already enabed !? */
5714 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5715 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5716 return;
5717 }
5718
5719 /* enable DPLL0 */
5720 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5721 skl_dpll0_enable(dev_priv, required_vco);
5722
5723 /* set CDCLK to the frequency the BIOS chose */
5724 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726 /* enable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733 DRM_ERROR("DBuf power enable timeout\n");
5734}
5735
dfcab17e 5736/* returns HPLL frequency in kHz */
f8bf63fd 5737static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5738{
586f49dc 5739 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5740
586f49dc 5741 /* Obtain SKU information */
a580516d 5742 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5743 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5745 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5746
dfcab17e 5747 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5748}
5749
44913155
VS		 5750static void intel_update_max_cdclk(struct drm_device *dev)
5751{
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
b432e5cf
VS		 5754 if (IS_BROADWELL(dev)) {
5755 /*
5756 * FIXME with extra cooling we can allow
5757 * 540 MHz for ULX and 675 Mhz for ULT.
5758 * How can we know if extra cooling is
5759 * available? PCI ID, VTB, something else?
5760 */
5761 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5762 dev_priv->max_cdclk_freq = 450000;
5763 else if (IS_BDW_ULX(dev))
5764 dev_priv->max_cdclk_freq = 450000;
5765 else if (IS_BDW_ULT(dev))
5766 dev_priv->max_cdclk_freq = 540000;
5767 else
5768 dev_priv->max_cdclk_freq = 675000;
5769 } else if (IS_VALLEYVIEW(dev)) {
44913155
VS		 5770 dev_priv->max_cdclk_freq = 400000;
5771 } else {
5772 /* otherwise assume cdclk is fixed */
5773 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5774 }
5775
5776 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5777 dev_priv->max_cdclk_freq);
5778}
5779
b6283055 5780static void intel_update_cdclk(struct drm_device *dev)
f8bf63fd
VS		 5781{
5782 struct drm_i915_private *dev_priv = dev->dev_private;
5783
164dfd28 5784 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5785 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5786 dev_priv->cdclk_freq);
f8bf63fd
VS		 5787
5788 /*
5789 * Program the gmbus_freq based on the cdclk frequency.
5790 * BSpec erroneously claims we should aim for 4MHz, but
5791 * in fact 1MHz is the correct frequency.
5792 */
b6283055
VS		 5793 if (IS_VALLEYVIEW(dev)) {
5794 /*
5795 * Program the gmbus_freq based on the cdclk frequency.
5796 * BSpec erroneously claims we should aim for 4MHz, but
5797 * in fact 1MHz is the correct frequency.
5798 */
5799 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5800 }
44913155
VS		 5801
5802 if (dev_priv->max_cdclk_freq == 0)
5803 intel_update_max_cdclk(dev);
f8bf63fd
VS		 5804}
5805
30a970c6
JB		 5806/* Adjust CDclk dividers to allow high res or save power if possible */
5807static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5808{
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 u32 val, cmd;
5811
164dfd28
VK		 5812 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5813 != dev_priv->cdclk_freq);
d60c4473 5814
dfcab17e 5815 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5816 cmd = 2;
dfcab17e 5817 else if (cdclk == 266667)
30a970c6
JB		 5818 cmd = 1;
5819 else
5820 cmd = 0;
5821
5822 mutex_lock(&dev_priv->rps.hw_lock);
5823 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5824 val &= ~DSPFREQGUAR_MASK;
5825 val |= (cmd << DSPFREQGUAR_SHIFT);
5826 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5827 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5828 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5829 50)) {
5830 DRM_ERROR("timed out waiting for CDclk change\n");
5831 }
5832 mutex_unlock(&dev_priv->rps.hw_lock);
5833
54433e91
VS		 5834 mutex_lock(&dev_priv->sb_lock);
5835
dfcab17e 5836 if (cdclk == 400000) {
6bcda4f0 5837 u32 divider;
30a970c6 5838
6bcda4f0 5839 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5840
30a970c6
JB		 5841 /* adjust cdclk divider */
5842 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5843 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5844 val |= divider;
5845 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5846
5847 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5848 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5849 50))
5850 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5851 }
5852
30a970c6
JB		 5853 /* adjust self-refresh exit latency value */
5854 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5855 val &= ~0x7f;
5856
5857 /*
5858 * For high bandwidth configs, we set a higher latency in the bunit
5859 * so that the core display fetch happens in time to avoid underruns.
5860 */
dfcab17e 5861 if (cdclk == 400000)
30a970c6
JB		 5862 val |= 4500 / 250; /* 4.5 usec */
5863 else
5864 val |= 3000 / 250; /* 3.0 usec */
5865 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5866
a580516d 5867 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5868
b6283055 5869 intel_update_cdclk(dev);
30a970c6
JB		 5870}
5871
383c5a6a
VS		 5872static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5873{
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 u32 val, cmd;
5876
164dfd28
VK		 5877 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5878 != dev_priv->cdclk_freq);
383c5a6a
VS		 5879
5880 switch (cdclk) {
383c5a6a
VS		 5881 case 333333:
5882 case 320000:
383c5a6a 5883 case 266667:
383c5a6a 5884 case 200000:
383c5a6a
VS		 5885 break;
5886 default:
5f77eeb0 5887 MISSING_CASE(cdclk);
383c5a6a
VS		 5888 return;
5889 }
5890
9d0d3fda
VS		 5891 /*
5892 * Specs are full of misinformation, but testing on actual
5893 * hardware has shown that we just need to write the desired
5894 * CCK divider into the Punit register.
5895 */
5896 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5897
383c5a6a
VS		 5898 mutex_lock(&dev_priv->rps.hw_lock);
5899 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5900 val &= ~DSPFREQGUAR_MASK_CHV;
5901 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5902 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5903 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5904 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5905 50)) {
5906 DRM_ERROR("timed out waiting for CDclk change\n");
5907 }
5908 mutex_unlock(&dev_priv->rps.hw_lock);
5909
b6283055 5910 intel_update_cdclk(dev);
383c5a6a
VS		 5911}
5912
30a970c6
JB		 5913static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5914 int max_pixclk)
5915{
6bcda4f0 5916 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5917 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5918
30a970c6
JB		 5919 /*
5920 * Really only a few cases to deal with, as only 4 CDclks are supported:
5921 * 200MHz
5922 * 267MHz
29dc7ef3 5923 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5924 * 400MHz (VLV only)
5925 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5926 * of the lower bin and adjust if needed.
e37c67a1
VS		 5927 *
5928 * We seem to get an unstable or solid color picture at 200MHz.
5929 * Not sure what's wrong. For now use 200MHz only when all pipes
5930 * are off.
30a970c6 5931 */
6cca3195
VS		 5932 if (!IS_CHERRYVIEW(dev_priv) &&
5933 max_pixclk > freq_320*limit/100)
dfcab17e 5934 return 400000;
6cca3195 5935 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5936 return freq_320;
e37c67a1 5937 else if (max_pixclk > 0)
dfcab17e 5938 return 266667;
e37c67a1
VS		 5939 else
5940 return 200000;
30a970c6
JB		 5941}
5942
f8437dd1
VK		 5943static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5944 int max_pixclk)
5945{
5946 /*
5947 * FIXME:
5948 * - remove the guardband, it's not needed on BXT
5949 * - set 19.2MHz bypass frequency if there are no active pipes
5950 */
5951 if (max_pixclk > 576000*9/10)
5952 return 624000;
5953 else if (max_pixclk > 384000*9/10)
5954 return 576000;
5955 else if (max_pixclk > 288000*9/10)
5956 return 384000;
5957 else if (max_pixclk > 144000*9/10)
5958 return 288000;
5959 else
5960 return 144000;
5961}
5962
a821fc46
ACO		 5963/* Compute the max pixel clock for new configuration. Uses atomic state if
5964 * that's non-NULL, look at current state otherwise. */
5965static int intel_mode_max_pixclk(struct drm_device *dev,
5966 struct drm_atomic_state *state)
30a970c6 5967{
30a970c6 5968 struct intel_crtc *intel_crtc;
304603f4 5969 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5970 int max_pixclk = 0;
5971
d3fcc808 5972 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5973 if (state)
5974 crtc_state =
5975 intel_atomic_get_crtc_state(state, intel_crtc);
5976 else
5977 crtc_state = intel_crtc->config;
304603f4
ACO		 5978 if (IS_ERR(crtc_state))
5979 return PTR_ERR(crtc_state);
5980
5981 if (!crtc_state->base.enable)
5982 continue;
5983
5984 max_pixclk = max(max_pixclk,
5985 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5986 }
5987
5988 return max_pixclk;
5989}
5990
0a9ab303 5991static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5992{
304603f4 5993 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5994 struct drm_crtc *crtc;
5995 struct drm_crtc_state *crtc_state;
a821fc46 5996 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5997 int cdclk, i;
30a970c6 5998
304603f4
ACO		 5999 if (max_pixclk < 0)
6000 return max_pixclk;
30a970c6 6001
f8437dd1
VK		 6002 if (IS_VALLEYVIEW(dev_priv))
6003 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6004 else
6005 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
6006
6007 if (cdclk == dev_priv->cdclk_freq)
304603f4 6008 return 0;
30a970c6 6009
0a9ab303
ACO		 6010 /* add all active pipes to the state */
6011 for_each_crtc(state->dev, crtc) {
6012 if (!crtc->state->enable)
6013 continue;
6014
6015 crtc_state = drm_atomic_get_crtc_state(state, crtc);
6016 if (IS_ERR(crtc_state))
6017 return PTR_ERR(crtc_state);
6018 }
6019
2f2d7aa1 6020 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 6021 for_each_crtc_in_state(state, crtc, crtc_state, i)
6022 if (crtc_state->enable)
6023 crtc_state->mode_changed = true;
304603f4
ACO		 6024
6025 return 0;
30a970c6
JB		 6026}
6027
1e69cd74
VS		 6028static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6029{
6030 unsigned int credits, default_credits;
6031
6032 if (IS_CHERRYVIEW(dev_priv))
6033 default_credits = PFI_CREDIT(12);
6034 else
6035 default_credits = PFI_CREDIT(8);
6036
164dfd28 6037 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6038 /* CHV suggested value is 31 or 63 */
6039 if (IS_CHERRYVIEW(dev_priv))
6040 credits = PFI_CREDIT_31;
6041 else
6042 credits = PFI_CREDIT(15);
6043 } else {
6044 credits = default_credits;
6045 }
6046
6047 /*
6048 * WA - write default credits before re-programming
6049 * FIXME: should we also set the resend bit here?
6050 */
6051 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6052 default_credits);
6053
6054 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6055 credits | PFI_CREDIT_RESEND);
6056
6057 /*
6058 * FIXME is this guaranteed to clear
6059 * immediately or should we poll for it?
6060 */
6061 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6062}
6063
a821fc46 6064static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6065{
a821fc46 6066 struct drm_device *dev = old_state->dev;
30a970c6 6067 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6068 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6069 int req_cdclk;
6070
a821fc46
ACO		 6071 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6072 * never fail. */
304603f4
ACO		 6073 if (WARN_ON(max_pixclk < 0))
6074 return;
30a970c6 6075
304603f4 6076 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6077
164dfd28 6078 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6079 /*
6080 * FIXME: We can end up here with all power domains off, yet
6081 * with a CDCLK frequency other than the minimum. To account
6082 * for this take the PIPE-A power domain, which covers the HW
6083 * blocks needed for the following programming. This can be
6084 * removed once it's guaranteed that we get here either with
6085 * the minimum CDCLK set, or the required power domains
6086 * enabled.
6087 */
6088 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6089
383c5a6a
VS		 6090 if (IS_CHERRYVIEW(dev))
6091 cherryview_set_cdclk(dev, req_cdclk);
6092 else
6093 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6094
1e69cd74
VS		 6095 vlv_program_pfi_credits(dev_priv);
6096
738c05c0 6097 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6098 }
30a970c6
JB		 6099}
6100
89b667f8
JB		 6101static void valleyview_crtc_enable(struct drm_crtc *crtc)
6102{
6103 struct drm_device *dev = crtc->dev;
a72e4c9f 6104 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6106 struct intel_encoder *encoder;
6107 int pipe = intel_crtc->pipe;
23538ef1 6108 bool is_dsi;
89b667f8 6109
83d65738 6110 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6111
6112 if (intel_crtc->active)
6113 return;
6114
409ee761 6115 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6116
1ae0d137
VS		 6117 if (!is_dsi) {
6118 if (IS_CHERRYVIEW(dev))
6e3c9717 6119 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6120 else
6e3c9717 6121 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6122 }
5b18e57c 6123
6e3c9717 6124 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6125 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6126
6127 intel_set_pipe_timings(intel_crtc);
6128
c14b0485
VS		 6129 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6130 struct drm_i915_private *dev_priv = dev->dev_private;
6131
6132 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6133 I915_WRITE(CHV_CANVAS(pipe), 0);
6134 }
6135
5b18e57c
DV		 6136 i9xx_set_pipeconf(intel_crtc);
6137
89b667f8 6138 intel_crtc->active = true;
89b667f8 6139
a72e4c9f 6140 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6141
89b667f8
JB		 6142 for_each_encoder_on_crtc(dev, crtc, encoder)
6143 if (encoder->pre_pll_enable)
6144 encoder->pre_pll_enable(encoder);
6145
9d556c99
CML		 6146 if (!is_dsi) {
6147 if (IS_CHERRYVIEW(dev))
6e3c9717 6148 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6149 else
6e3c9717 6150 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6151 }
89b667f8
JB		 6152
6153 for_each_encoder_on_crtc(dev, crtc, encoder)
6154 if (encoder->pre_enable)
6155 encoder->pre_enable(encoder);
6156
2dd24552
JB		 6157 i9xx_pfit_enable(intel_crtc);
6158
63cbb074
VS		 6159 intel_crtc_load_lut(crtc);
6160
f37fcc2a 6161 intel_update_watermarks(crtc);
e1fdc473 6162 intel_enable_pipe(intel_crtc);
be6a6f8e 6163
4b3a9526
VS		 6164 assert_vblank_disabled(crtc);
6165 drm_crtc_vblank_on(crtc);
6166
f9b61ff6
DV		 6167 for_each_encoder_on_crtc(dev, crtc, encoder)
6168 encoder->enable(encoder);
89b667f8
JB		 6169}
6170
f13c2ef3
DV		 6171static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6172{
6173 struct drm_device *dev = crtc->base.dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175
6e3c9717
ACO		 6176 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6177 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6178}
6179
0b8765c6 6180static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6181{
6182 struct drm_device *dev = crtc->dev;
a72e4c9f 6183 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6185 struct intel_encoder *encoder;
79e53945 6186 int pipe = intel_crtc->pipe;
79e53945 6187
83d65738 6188 WARN_ON(!crtc->state->enable);
08a48469 6189
f7abfe8b
CW		 6190 if (intel_crtc->active)
6191 return;
6192
f13c2ef3
DV		 6193 i9xx_set_pll_dividers(intel_crtc);
6194
6e3c9717 6195 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6196 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6197
6198 intel_set_pipe_timings(intel_crtc);
6199
5b18e57c
DV		 6200 i9xx_set_pipeconf(intel_crtc);
6201
f7abfe8b 6202 intel_crtc->active = true;
6b383a7f 6203
4a3436e8 6204 if (!IS_GEN2(dev))
a72e4c9f 6205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6206
9d6d9f19
MK		 6207 for_each_encoder_on_crtc(dev, crtc, encoder)
6208 if (encoder->pre_enable)
6209 encoder->pre_enable(encoder);
6210
f6736a1a
DV		 6211 i9xx_enable_pll(intel_crtc);
6212
2dd24552
JB		 6213 i9xx_pfit_enable(intel_crtc);
6214
63cbb074
VS		 6215 intel_crtc_load_lut(crtc);
6216
f37fcc2a 6217 intel_update_watermarks(crtc);
e1fdc473 6218 intel_enable_pipe(intel_crtc);
be6a6f8e 6219
4b3a9526
VS		 6220 assert_vblank_disabled(crtc);
6221 drm_crtc_vblank_on(crtc);
6222
f9b61ff6
DV		 6223 for_each_encoder_on_crtc(dev, crtc, encoder)
6224 encoder->enable(encoder);
0b8765c6 6225}
79e53945 6226
87476d63
DV		 6227static void i9xx_pfit_disable(struct intel_crtc *crtc)
6228{
6229 struct drm_device *dev = crtc->base.dev;
6230 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6231
6e3c9717 6232 if (!crtc->config->gmch_pfit.control)
328d8e82 6233 return;
87476d63 6234
328d8e82 6235 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6236
328d8e82
DV		 6237 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6238 I915_READ(PFIT_CONTROL));
6239 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6240}
6241
0b8765c6
JB		 6242static void i9xx_crtc_disable(struct drm_crtc *crtc)
6243{
6244 struct drm_device *dev = crtc->dev;
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6247 struct intel_encoder *encoder;
0b8765c6 6248 int pipe = intel_crtc->pipe;
ef9c3aee 6249
f7abfe8b
CW		 6250 if (!intel_crtc->active)
6251 return;
6252
6304cd91
VS		 6253 /*
6254 * On gen2 planes are double buffered but the pipe isn't, so we must
6255 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6256 * We also need to wait on all gmch platforms because of the
6257 * self-refresh mode constraint explained above.
6304cd91 6258 */
564ed191 6259 intel_wait_for_vblank(dev, pipe);
6304cd91 6260
4b3a9526
VS		 6261 for_each_encoder_on_crtc(dev, crtc, encoder)
6262 encoder->disable(encoder);
6263
f9b61ff6
DV		 6264 drm_crtc_vblank_off(crtc);
6265 assert_vblank_disabled(crtc);
6266
575f7ab7 6267 intel_disable_pipe(intel_crtc);
24a1f16d 6268
87476d63 6269 i9xx_pfit_disable(intel_crtc);
24a1f16d 6270
89b667f8
JB		 6271 for_each_encoder_on_crtc(dev, crtc, encoder)
6272 if (encoder->post_disable)
6273 encoder->post_disable(encoder);
6274
409ee761 6275 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6276 if (IS_CHERRYVIEW(dev))
6277 chv_disable_pll(dev_priv, pipe);
6278 else if (IS_VALLEYVIEW(dev))
6279 vlv_disable_pll(dev_priv, pipe);
6280 else
1c4e0274 6281 i9xx_disable_pll(intel_crtc);
076ed3b2 6282 }
0b8765c6 6283
4a3436e8 6284 if (!IS_GEN2(dev))
a72e4c9f 6285 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6286
f7abfe8b 6287 intel_crtc->active = false;
46ba614c 6288 intel_update_watermarks(crtc);
f37fcc2a 6289
efa9624e 6290 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6291 intel_fbc_update(dev);
efa9624e 6292 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6293}
6294
ee7b9f93
JB		 6295static void i9xx_crtc_off(struct drm_crtc *crtc)
6296{
6297}
6298
b04c5bd6
BF		 6299/* Master function to enable/disable CRTC and corresponding power wells */
6300void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6301{
6302 struct drm_device *dev = crtc->dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6305 enum intel_display_power_domain domain;
6306 unsigned long domains;
976f8a20 6307
0e572fe7
DV		 6308 if (enable) {
6309 if (!intel_crtc->active) {
e1e9fb84
DV		 6310 domains = get_crtc_power_domains(crtc);
6311 for_each_power_domain(domain, domains)
6312 intel_display_power_get(dev_priv, domain);
6313 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6314
6315 dev_priv->display.crtc_enable(crtc);
ce22dba9 6316 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6317 }
6318 } else {
6319 if (intel_crtc->active) {
ce22dba9 6320 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6321 dev_priv->display.crtc_disable(crtc);
6322
e1e9fb84
DV		 6323 domains = intel_crtc->enabled_power_domains;
6324 for_each_power_domain(domain, domains)
6325 intel_display_power_put(dev_priv, domain);
6326 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6327 }
6328 }
b04c5bd6
BF		 6329}
6330
6331/**
6332 * Sets the power management mode of the pipe and plane.
6333 */
6334void intel_crtc_update_dpms(struct drm_crtc *crtc)
6335{
6336 struct drm_device *dev = crtc->dev;
6337 struct intel_encoder *intel_encoder;
6338 bool enable = false;
6339
6340 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6341 enable |= intel_encoder->connectors_active;
6342
6343 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6344
6345 crtc->state->active = enable;
976f8a20
DV		 6346}
6347
cdd59983
CW		 6348static void intel_crtc_disable(struct drm_crtc *crtc)
6349{
cdd59983 6350 struct drm_device *dev = crtc->dev;
976f8a20 6351 struct drm_connector *connector;
ee7b9f93 6352 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6353
976f8a20 6354 /* crtc should still be enabled when we disable it. */
83d65738 6355 WARN_ON(!crtc->state->enable);
976f8a20 6356
ce22dba9 6357 intel_crtc_disable_planes(crtc);
976f8a20 6358 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6359 dev_priv->display.off(crtc);
6360
70a101f8 6361 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6362
6363 /* Update computed state. */
6364 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6365 if (!connector->encoder || !connector->encoder->crtc)
6366 continue;
6367
6368 if (connector->encoder->crtc != crtc)
6369 continue;
6370
6371 connector->dpms = DRM_MODE_DPMS_OFF;
6372 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6373 }
6374}
6375
ea5b213a 6376void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6377{
4ef69c7a 6378 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6379
ea5b213a
CW		 6380 drm_encoder_cleanup(encoder);
6381 kfree(intel_encoder);
7e7d76c3
JB		 6382}
6383
9237329d 6384/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6385 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6386 * state of the entire output pipe. */
9237329d 6387static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6388{
5ab432ef
DV		 6389 if (mode == DRM_MODE_DPMS_ON) {
6390 encoder->connectors_active = true;
6391
b2cabb0e 6392 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6393 } else {
6394 encoder->connectors_active = false;
6395
b2cabb0e 6396 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6397 }
79e53945
JB		 6398}
6399
0a91ca29
DV		 6400/* Cross check the actual hw state with our own modeset state tracking (and it's
6401 * internal consistency). */
b980514c 6402static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6403{
0a91ca29
DV		 6404 if (connector->get_hw_state(connector)) {
6405 struct intel_encoder *encoder = connector->encoder;
6406 struct drm_crtc *crtc;
6407 bool encoder_enabled;
6408 enum pipe pipe;
6409
6410 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6411 connector->base.base.id,
c23cc417 6412 connector->base.name);
0a91ca29 6413
0e32b39c
DA		 6414 /* there is no real hw state for MST connectors */
6415 if (connector->mst_port)
6416 return;
6417
e2c719b7 6418 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6419 "wrong connector dpms state\n");
e2c719b7 6420 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6421 "active connector not linked to encoder\n");
0a91ca29 6422
36cd7444 6423 if (encoder) {
e2c719b7 6424 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6425 "encoder->connectors_active not set\n");
6426
6427 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6428 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6429 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6430 return;
0a91ca29 6431
36cd7444 6432 crtc = encoder->base.crtc;
0a91ca29 6433
83d65738
MR		 6434 I915_STATE_WARN(!crtc->state->enable,
6435 "crtc not enabled\n");
e2c719b7
RC		 6436 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6437 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6438 "encoder active on the wrong pipe\n");
6439 }
0a91ca29 6440 }
79e53945
JB		 6441}
6442
08d9bc92
ACO		 6443int intel_connector_init(struct intel_connector *connector)
6444{
6445 struct drm_connector_state *connector_state;
6446
6447 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6448 if (!connector_state)
6449 return -ENOMEM;
6450
6451 connector->base.state = connector_state;
6452 return 0;
6453}
6454
6455struct intel_connector *intel_connector_alloc(void)
6456{
6457 struct intel_connector *connector;
6458
6459 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6460 if (!connector)
6461 return NULL;
6462
6463 if (intel_connector_init(connector) < 0) {
6464 kfree(connector);
6465 return NULL;
6466 }
6467
6468 return connector;
6469}
6470
5ab432ef
DV		 6471/* Even simpler default implementation, if there's really no special case to
6472 * consider. */
6473void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6474{
5ab432ef
DV		 6475 /* All the simple cases only support two dpms states. */
6476 if (mode != DRM_MODE_DPMS_ON)
6477 mode = DRM_MODE_DPMS_OFF;
d4270e57 6478
5ab432ef
DV		 6479 if (mode == connector->dpms)
6480 return;
6481
6482 connector->dpms = mode;
6483
6484 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6485 if (connector->encoder)
6486 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6487
b980514c 6488 intel_modeset_check_state(connector->dev);
79e53945
JB		 6489}
6490
f0947c37
DV		 6491/* Simple connector->get_hw_state implementation for encoders that support only
6492 * one connector and no cloning and hence the encoder state determines the state
6493 * of the connector. */
6494bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6495{
24929352 6496 enum pipe pipe = 0;
f0947c37 6497 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6498
f0947c37 6499 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6500}
6501
6d293983 6502static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6503{
6d293983
ACO		 6504 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6505 return crtc_state->fdi_lanes;
d272ddfa
VS		 6506
6507 return 0;
6508}
6509
6d293983 6510static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6511 struct intel_crtc_state *pipe_config)
1857e1da 6512{
6d293983
ACO		 6513 struct drm_atomic_state *state = pipe_config->base.state;
6514 struct intel_crtc *other_crtc;
6515 struct intel_crtc_state *other_crtc_state;
6516
1857e1da
DV		 6517 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6518 pipe_name(pipe), pipe_config->fdi_lanes);
6519 if (pipe_config->fdi_lanes > 4) {
6520 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6521 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6522 return -EINVAL;
1857e1da
DV		 6523 }
6524
bafb6553 6525 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6526 if (pipe_config->fdi_lanes > 2) {
6527 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6528 pipe_config->fdi_lanes);
6d293983 6529 return -EINVAL;
1857e1da 6530 } else {
6d293983 6531 return 0;
1857e1da
DV		 6532 }
6533 }
6534
6535 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6536 return 0;
1857e1da
DV		 6537
6538 /* Ivybridge 3 pipe is really complicated */
6539 switch (pipe) {
6540 case PIPE_A:
6d293983 6541 return 0;
1857e1da 6542 case PIPE_B:
6d293983
ACO		 6543 if (pipe_config->fdi_lanes <= 2)
6544 return 0;
6545
6546 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6547 other_crtc_state =
6548 intel_atomic_get_crtc_state(state, other_crtc);
6549 if (IS_ERR(other_crtc_state))
6550 return PTR_ERR(other_crtc_state);
6551
6552 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6553 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6554 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6555 return -EINVAL;
1857e1da 6556 }
6d293983 6557 return 0;
1857e1da 6558 case PIPE_C:
251cc67c
VS		 6559 if (pipe_config->fdi_lanes > 2) {
6560 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6561 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6562 return -EINVAL;
251cc67c 6563 }
6d293983
ACO		 6564
6565 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6566 other_crtc_state =
6567 intel_atomic_get_crtc_state(state, other_crtc);
6568 if (IS_ERR(other_crtc_state))
6569 return PTR_ERR(other_crtc_state);
6570
6571 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6572 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6573 return -EINVAL;
1857e1da 6574 }
6d293983 6575 return 0;
1857e1da
DV		 6576 default:
6577 BUG();
6578 }
6579}
6580
e29c22c0
DV		 6581#define RETRY 1
6582static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6583 struct intel_crtc_state *pipe_config)
877d48d5 6584{
1857e1da 6585 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6586 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6587 int lane, link_bw, fdi_dotclock, ret;
6588 bool needs_recompute = false;
877d48d5 6589
e29c22c0 6590retry:
877d48d5
DV		 6591 /* FDI is a binary signal running at ~2.7GHz, encoding
6592 * each output octet as 10 bits. The actual frequency
6593 * is stored as a divider into a 100MHz clock, and the
6594 * mode pixel clock is stored in units of 1KHz.
6595 * Hence the bw of each lane in terms of the mode signal
6596 * is:
6597 */
6598 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6599
241bfc38 6600 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6601
2bd89a07 6602 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6603 pipe_config->pipe_bpp);
6604
6605 pipe_config->fdi_lanes = lane;
6606
2bd89a07 6607 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6608 link_bw, &pipe_config->fdi_m_n);
1857e1da 6609
6d293983
ACO		 6610 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6611 intel_crtc->pipe, pipe_config);
6612 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6613 pipe_config->pipe_bpp -= 2*3;
6614 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6615 pipe_config->pipe_bpp);
6616 needs_recompute = true;
6617 pipe_config->bw_constrained = true;
6618
6619 goto retry;
6620 }
6621
6622 if (needs_recompute)
6623 return RETRY;
6624
6d293983 6625 return ret;
877d48d5
DV		 6626}
6627
8cfb3407
VS		 6628static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6629 struct intel_crtc_state *pipe_config)
6630{
6631 if (pipe_config->pipe_bpp > 24)
6632 return false;
6633
6634 /* HSW can handle pixel rate up to cdclk? */
6635 if (IS_HASWELL(dev_priv->dev))
6636 return true;
6637
6638 /*
b432e5cf
VS		 6639 * We compare against max which means we must take
6640 * the increased cdclk requirement into account when
6641 * calculating the new cdclk.
6642 *
6643 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6644 */
6645 return ilk_pipe_pixel_rate(pipe_config) <=
6646 dev_priv->max_cdclk_freq * 95 / 100;
6647}
6648
42db64ef 6649static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6650 struct intel_crtc_state *pipe_config)
42db64ef 6651{
8cfb3407
VS		 6652 struct drm_device *dev = crtc->base.dev;
6653 struct drm_i915_private *dev_priv = dev->dev_private;
6654
d330a953 6655 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6656 hsw_crtc_supports_ips(crtc) &&
6657 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6658}
6659
a43f6e0f 6660static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6661 struct intel_crtc_state *pipe_config)
79e53945 6662{
a43f6e0f 6663 struct drm_device *dev = crtc->base.dev;
8bd31e67 6664 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6665 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6666 int ret;
89749350 6667
ad3a4479 6668 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6669 if (INTEL_INFO(dev)->gen < 4) {
44913155 6670 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6671
6672 /*
6673 * Enable pixel doubling when the dot clock
6674 * is > 90% of the (display) core speed.
6675 *
b397c96b
VS		 6676 * GDG double wide on either pipe,
6677 * otherwise pipe A only.
cf532bb2 6678 */
b397c96b 6679 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6680 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6681 clock_limit *= 2;
cf532bb2 6682 pipe_config->double_wide = true;
ad3a4479
VS		 6683 }
6684
241bfc38 6685 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6686 return -EINVAL;
2c07245f 6687 }
89749350 6688
1d1d0e27
VS		 6689 /*
6690 * Pipe horizontal size must be even in:
6691 * - DVO ganged mode
6692 * - LVDS dual channel mode
6693 * - Double wide pipe
6694 */
a93e255f 6695 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6696 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6697 pipe_config->pipe_src_w &= ~1;
6698
8693a824
DL		 6699 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6700 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6701 */
6702 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6703 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6704 return -EINVAL;
44f46b42 6705
f5adf94e 6706 if (HAS_IPS(dev))
a43f6e0f
DV		 6707 hsw_compute_ips_config(crtc, pipe_config);
6708
877d48d5 6709 if (pipe_config->has_pch_encoder)
a43f6e0f 6710 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6711
d03c93d4
CK		 6712 /* FIXME: remove below call once atomic mode set is place and all crtc
6713 * related checks called from atomic_crtc_check function */
6714 ret = 0;
6715 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6716 crtc, pipe_config->base.state);
6717 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6718
6719 return ret;
79e53945
JB		 6720}
6721
1652d19e
VS		 6722static int skylake_get_display_clock_speed(struct drm_device *dev)
6723{
6724 struct drm_i915_private *dev_priv = to_i915(dev);
6725 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6726 uint32_t cdctl = I915_READ(CDCLK_CTL);
6727 uint32_t linkrate;
6728
6729 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6730 WARN(1, "LCPLL1 not enabled\n");
6731 return 24000; /* 24MHz is the cd freq with NSSC ref */
6732 }
6733
6734 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6735 return 540000;
6736
6737 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6738 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6739
71cd8423
DL		 6740 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6741 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6742 /* vco 8640 */
6743 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6744 case CDCLK_FREQ_450_432:
6745 return 432000;
6746 case CDCLK_FREQ_337_308:
6747 return 308570;
6748 case CDCLK_FREQ_675_617:
6749 return 617140;
6750 default:
6751 WARN(1, "Unknown cd freq selection\n");
6752 }
6753 } else {
6754 /* vco 8100 */
6755 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6756 case CDCLK_FREQ_450_432:
6757 return 450000;
6758 case CDCLK_FREQ_337_308:
6759 return 337500;
6760 case CDCLK_FREQ_675_617:
6761 return 675000;
6762 default:
6763 WARN(1, "Unknown cd freq selection\n");
6764 }
6765 }
6766
6767 /* error case, do as if DPLL0 isn't enabled */
6768 return 24000;
6769}
6770
6771static int broadwell_get_display_clock_speed(struct drm_device *dev)
6772{
6773 struct drm_i915_private *dev_priv = dev->dev_private;
6774 uint32_t lcpll = I915_READ(LCPLL_CTL);
6775 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6776
6777 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6778 return 800000;
6779 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6780 return 450000;
6781 else if (freq == LCPLL_CLK_FREQ_450)
6782 return 450000;
6783 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6784 return 540000;
6785 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6786 return 337500;
6787 else
6788 return 675000;
6789}
6790
6791static int haswell_get_display_clock_speed(struct drm_device *dev)
6792{
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794 uint32_t lcpll = I915_READ(LCPLL_CTL);
6795 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6796
6797 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6798 return 800000;
6799 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6800 return 450000;
6801 else if (freq == LCPLL_CLK_FREQ_450)
6802 return 450000;
6803 else if (IS_HSW_ULT(dev))
6804 return 337500;
6805 else
6806 return 540000;
79e53945
JB		 6807}
6808
25eb05fc
JB		 6809static int valleyview_get_display_clock_speed(struct drm_device *dev)
6810{
d197b7d3 6811 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6812 u32 val;
6813 int divider;
6814
6bcda4f0
VS		 6815 if (dev_priv->hpll_freq == 0)
6816 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6817
a580516d 6818 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6819 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6820 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6821
6822 divider = val & DISPLAY_FREQUENCY_VALUES;
6823
7d007f40
VS		 6824 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6825 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6826 "cdclk change in progress\n");
6827
6bcda4f0 6828 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6829}
6830
b37a6434
VS		 6831static int ilk_get_display_clock_speed(struct drm_device *dev)
6832{
6833 return 450000;
6834}
6835
e70236a8
JB		 6836static int i945_get_display_clock_speed(struct drm_device *dev)
6837{
6838 return 400000;
6839}
79e53945 6840
e70236a8 6841static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6842{
e907f170 6843 return 333333;
e70236a8 6844}
79e53945 6845
e70236a8
JB		 6846static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6847{
6848 return 200000;
6849}
79e53945 6850
257a7ffc
DV		 6851static int pnv_get_display_clock_speed(struct drm_device *dev)
6852{
6853 u16 gcfgc = 0;
6854
6855 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6856
6857 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6858 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6859 return 266667;
257a7ffc 6860 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6861 return 333333;
257a7ffc 6862 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6863 return 444444;
257a7ffc
DV		 6864 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6865 return 200000;
6866 default:
6867 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6868 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6869 return 133333;
257a7ffc 6870 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6871 return 166667;
257a7ffc
DV		 6872 }
6873}
6874
e70236a8
JB		 6875static int i915gm_get_display_clock_speed(struct drm_device *dev)
6876{
6877 u16 gcfgc = 0;
79e53945 6878
e70236a8
JB		 6879 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6880
6881 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6882 return 133333;
e70236a8
JB		 6883 else {
6884 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6885 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6886 return 333333;
e70236a8
JB		 6887 default:
6888 case GC_DISPLAY_CLOCK_190_200_MHZ:
6889 return 190000;
79e53945 6890 }
e70236a8
JB		 6891 }
6892}
6893
6894static int i865_get_display_clock_speed(struct drm_device *dev)
6895{
e907f170 6896 return 266667;
e70236a8
JB		 6897}
6898
1b1d2716 6899static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6900{
6901 u16 hpllcc = 0;
1b1d2716 6902
65cd2b3f
VS		 6903 /*
6904 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6905 * encoding is different :(
6906 * FIXME is this the right way to detect 852GM/852GMV?
6907 */
6908 if (dev->pdev->revision == 0x1)
6909 return 133333;
6910
1b1d2716
VS		 6911 pci_bus_read_config_word(dev->pdev->bus,
6912 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6913
e70236a8
JB		 6914 /* Assume that the hardware is in the high speed state. This
6915 * should be the default.
6916 */
6917 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6918 case GC_CLOCK_133_200:
1b1d2716 6919 case GC_CLOCK_133_200_2:
e70236a8
JB		 6920 case GC_CLOCK_100_200:
6921 return 200000;
6922 case GC_CLOCK_166_250:
6923 return 250000;
6924 case GC_CLOCK_100_133:
e907f170 6925 return 133333;
1b1d2716
VS		 6926 case GC_CLOCK_133_266:
6927 case GC_CLOCK_133_266_2:
6928 case GC_CLOCK_166_266:
6929 return 266667;
e70236a8 6930 }
79e53945 6931
e70236a8
JB		 6932 /* Shouldn't happen */
6933 return 0;
6934}
79e53945 6935
e70236a8
JB		 6936static int i830_get_display_clock_speed(struct drm_device *dev)
6937{
e907f170 6938 return 133333;
79e53945
JB		 6939}
6940
34edce2f
VS		 6941static unsigned int intel_hpll_vco(struct drm_device *dev)
6942{
6943 struct drm_i915_private *dev_priv = dev->dev_private;
6944 static const unsigned int blb_vco[8] = {
6945 [0] = 3200000,
6946 [1] = 4000000,
6947 [2] = 5333333,
6948 [3] = 4800000,
6949 [4] = 6400000,
6950 };
6951 static const unsigned int pnv_vco[8] = {
6952 [0] = 3200000,
6953 [1] = 4000000,
6954 [2] = 5333333,
6955 [3] = 4800000,
6956 [4] = 2666667,
6957 };
6958 static const unsigned int cl_vco[8] = {
6959 [0] = 3200000,
6960 [1] = 4000000,
6961 [2] = 5333333,
6962 [3] = 6400000,
6963 [4] = 3333333,
6964 [5] = 3566667,
6965 [6] = 4266667,
6966 };
6967 static const unsigned int elk_vco[8] = {
6968 [0] = 3200000,
6969 [1] = 4000000,
6970 [2] = 5333333,
6971 [3] = 4800000,
6972 };
6973 static const unsigned int ctg_vco[8] = {
6974 [0] = 3200000,
6975 [1] = 4000000,
6976 [2] = 5333333,
6977 [3] = 6400000,
6978 [4] = 2666667,
6979 [5] = 4266667,
6980 };
6981 const unsigned int *vco_table;
6982 unsigned int vco;
6983 uint8_t tmp = 0;
6984
6985 /* FIXME other chipsets? */
6986 if (IS_GM45(dev))
6987 vco_table = ctg_vco;
6988 else if (IS_G4X(dev))
6989 vco_table = elk_vco;
6990 else if (IS_CRESTLINE(dev))
6991 vco_table = cl_vco;
6992 else if (IS_PINEVIEW(dev))
6993 vco_table = pnv_vco;
6994 else if (IS_G33(dev))
6995 vco_table = blb_vco;
6996 else
6997 return 0;
6998
6999 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7000
7001 vco = vco_table[tmp & 0x7];
7002 if (vco == 0)
7003 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7004 else
7005 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7006
7007 return vco;
7008}
7009
7010static int gm45_get_display_clock_speed(struct drm_device *dev)
7011{
7012 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7013 uint16_t tmp = 0;
7014
7015 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7016
7017 cdclk_sel = (tmp >> 12) & 0x1;
7018
7019 switch (vco) {
7020 case 2666667:
7021 case 4000000:
7022 case 5333333:
7023 return cdclk_sel ? 333333 : 222222;
7024 case 3200000:
7025 return cdclk_sel ? 320000 : 228571;
7026 default:
7027 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7028 return 222222;
7029 }
7030}
7031
7032static int i965gm_get_display_clock_speed(struct drm_device *dev)
7033{
7034 static const uint8_t div_3200[] = { 16, 10, 8 };
7035 static const uint8_t div_4000[] = { 20, 12, 10 };
7036 static const uint8_t div_5333[] = { 24, 16, 14 };
7037 const uint8_t *div_table;
7038 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7039 uint16_t tmp = 0;
7040
7041 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7042
7043 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7044
7045 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7046 goto fail;
7047
7048 switch (vco) {
7049 case 3200000:
7050 div_table = div_3200;
7051 break;
7052 case 4000000:
7053 div_table = div_4000;
7054 break;
7055 case 5333333:
7056 div_table = div_5333;
7057 break;
7058 default:
7059 goto fail;
7060 }
7061
7062 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7063
7064 fail:
7065 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7066 return 200000;
7067}
7068
7069static int g33_get_display_clock_speed(struct drm_device *dev)
7070{
7071 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7072 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7073 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7074 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7075 const uint8_t *div_table;
7076 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7077 uint16_t tmp = 0;
7078
7079 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7080
7081 cdclk_sel = (tmp >> 4) & 0x7;
7082
7083 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7084 goto fail;
7085
7086 switch (vco) {
7087 case 3200000:
7088 div_table = div_3200;
7089 break;
7090 case 4000000:
7091 div_table = div_4000;
7092 break;
7093 case 4800000:
7094 div_table = div_4800;
7095 break;
7096 case 5333333:
7097 div_table = div_5333;
7098 break;
7099 default:
7100 goto fail;
7101 }
7102
7103 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7104
7105 fail:
7106 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7107 return 190476;
7108}
7109
2c07245f 7110static void
a65851af 7111intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7112{
a65851af
VS		 7113 while (*num > DATA_LINK_M_N_MASK ||
7114 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7115 *num >>= 1;
7116 *den >>= 1;
7117 }
7118}
7119
a65851af
VS		 7120static void compute_m_n(unsigned int m, unsigned int n,
7121 uint32_t *ret_m, uint32_t *ret_n)
7122{
7123 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7124 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7125 intel_reduce_m_n_ratio(ret_m, ret_n);
7126}
7127
e69d0bc1
DV		 7128void
7129intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7130 int pixel_clock, int link_clock,
7131 struct intel_link_m_n *m_n)
2c07245f 7132{
e69d0bc1 7133 m_n->tu = 64;
a65851af
VS		 7134
7135 compute_m_n(bits_per_pixel * pixel_clock,
7136 link_clock * nlanes * 8,
7137 &m_n->gmch_m, &m_n->gmch_n);
7138
7139 compute_m_n(pixel_clock, link_clock,
7140 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7141}
7142
a7615030
CW		 7143static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7144{
d330a953
JN		 7145 if (i915.panel_use_ssc >= 0)
7146 return i915.panel_use_ssc != 0;
41aa3448 7147 return dev_priv->vbt.lvds_use_ssc
435793df 7148 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7149}
7150
a93e255f
ACO		 7151static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7152 int num_connectors)
c65d77d8 7153{
a93e255f 7154 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7155 struct drm_i915_private *dev_priv = dev->dev_private;
7156 int refclk;
7157
a93e255f
ACO		 7158 WARN_ON(!crtc_state->base.state);
7159
5ab7b0b7 7160 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7161 refclk = 100000;
a93e255f 7162 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7163 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7164 refclk = dev_priv->vbt.lvds_ssc_freq;
7165 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7166 } else if (!IS_GEN2(dev)) {
7167 refclk = 96000;
7168 } else {
7169 refclk = 48000;
7170 }
7171
7172 return refclk;
7173}
7174
7429e9d4 7175static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7176{
7df00d7a 7177 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7178}
f47709a9 7179
7429e9d4
DV		 7180static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7181{
7182 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7183}
7184
f47709a9 7185static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7186 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7187 intel_clock_t *reduced_clock)
7188{
f47709a9 7189 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7190 u32 fp, fp2 = 0;
7191
7192 if (IS_PINEVIEW(dev)) {
190f68c5 7193 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7194 if (reduced_clock)
7429e9d4 7195 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7196 } else {
190f68c5 7197 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7198 if (reduced_clock)
7429e9d4 7199 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7200 }
7201
190f68c5 7202 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7203
f47709a9 7204 crtc->lowfreq_avail = false;
a93e255f 7205 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7206 reduced_clock) {
190f68c5 7207 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7208 crtc->lowfreq_avail = true;
a7516a05 7209 } else {
190f68c5 7210 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7211 }
7212}
7213
5e69f97f
CML		 7214static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7215 pipe)
89b667f8
JB		 7216{
7217 u32 reg_val;
7218
7219 /*
7220 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7221 * and set it to a reasonable value instead.
7222 */
ab3c759a 7223 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7224 reg_val &= 0xffffff00;
7225 reg_val |= 0x00000030;
ab3c759a 7226 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7227
ab3c759a 7228 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7229 reg_val &= 0x8cffffff;
7230 reg_val = 0x8c000000;
ab3c759a 7231 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7232
ab3c759a 7233 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7234 reg_val &= 0xffffff00;
ab3c759a 7235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7236
ab3c759a 7237 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7238 reg_val &= 0x00ffffff;
7239 reg_val |= 0xb0000000;
ab3c759a 7240 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7241}
7242
b551842d
DV		 7243static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7244 struct intel_link_m_n *m_n)
7245{
7246 struct drm_device *dev = crtc->base.dev;
7247 struct drm_i915_private *dev_priv = dev->dev_private;
7248 int pipe = crtc->pipe;
7249
e3b95f1e
DV		 7250 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7251 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7252 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7253 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7254}
7255
7256static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7257 struct intel_link_m_n *m_n,
7258 struct intel_link_m_n *m2_n2)
b551842d
DV		 7259{
7260 struct drm_device *dev = crtc->base.dev;
7261 struct drm_i915_private *dev_priv = dev->dev_private;
7262 int pipe = crtc->pipe;
6e3c9717 7263 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7264
7265 if (INTEL_INFO(dev)->gen >= 5) {
7266 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7267 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7268 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7269 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7270 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7271 * for gen < 8) and if DRRS is supported (to make sure the
7272 * registers are not unnecessarily accessed).
7273 */
44395bfe 7274 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7275 crtc->config->has_drrs) {
f769cd24
VK		 7276 I915_WRITE(PIPE_DATA_M2(transcoder),
7277 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7278 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7279 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7280 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7281 }
b551842d 7282 } else {
e3b95f1e
DV		 7283 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7284 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7285 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7286 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7287 }
7288}
7289
fe3cd48d 7290void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7291{
fe3cd48d
R		 7292 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7293
7294 if (m_n == M1_N1) {
7295 dp_m_n = &crtc->config->dp_m_n;
7296 dp_m2_n2 = &crtc->config->dp_m2_n2;
7297 } else if (m_n == M2_N2) {
7298
7299 /*
7300 * M2_N2 registers are not supported. Hence m2_n2 divider value
7301 * needs to be programmed into M1_N1.
7302 */
7303 dp_m_n = &crtc->config->dp_m2_n2;
7304 } else {
7305 DRM_ERROR("Unsupported divider value\n");
7306 return;
7307 }
7308
6e3c9717
ACO		 7309 if (crtc->config->has_pch_encoder)
7310 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7311 else
fe3cd48d 7312 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7313}
7314
d288f65f 7315static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7316 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7317{
7318 u32 dpll, dpll_md;
7319
7320 /*
7321 * Enable DPIO clock input. We should never disable the reference
7322 * clock for pipe B, since VGA hotplug / manual detection depends
7323 * on it.
7324 */
7325 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7326 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7327 /* We should never disable this, set it here for state tracking */
7328 if (crtc->pipe == PIPE_B)
7329 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7330 dpll |= DPLL_VCO_ENABLE;
d288f65f 7331 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7332
d288f65f 7333 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7334 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7335 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7336}
7337
d288f65f 7338static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7339 const struct intel_crtc_state *pipe_config)
a0c4da24 7340{
f47709a9 7341 struct drm_device *dev = crtc->base.dev;
a0c4da24 7342 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7343 int pipe = crtc->pipe;
bdd4b6a6 7344 u32 mdiv;
a0c4da24 7345 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7346 u32 coreclk, reg_val;
a0c4da24 7347
a580516d 7348 mutex_lock(&dev_priv->sb_lock);
09153000 7349
d288f65f
VS		 7350 bestn = pipe_config->dpll.n;
7351 bestm1 = pipe_config->dpll.m1;
7352 bestm2 = pipe_config->dpll.m2;
7353 bestp1 = pipe_config->dpll.p1;
7354 bestp2 = pipe_config->dpll.p2;
a0c4da24 7355
89b667f8
JB		 7356 /* See eDP HDMI DPIO driver vbios notes doc */
7357
7358 /* PLL B needs special handling */
bdd4b6a6 7359 if (pipe == PIPE_B)
5e69f97f 7360 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7361
7362 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7364
7365 /* Disable target IRef on PLL */
ab3c759a 7366 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7367 reg_val &= 0x00ffffff;
ab3c759a 7368 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7369
7370 /* Disable fast lock */
ab3c759a 7371 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7372
7373 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7374 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7375 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7376 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7377 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7378
7379 /*
7380 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7381 * but we don't support that).
7382 * Note: don't use the DAC post divider as it seems unstable.
7383 */
7384 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7386
a0c4da24 7387 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7388 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7389
89b667f8 7390 /* Set HBR and RBR LPF coefficients */
d288f65f 7391 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7392 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7393 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7394 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7395 0x009f0003);
89b667f8 7396 else
ab3c759a 7397 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7398 0x00d0000f);
7399
681a8504 7400 if (pipe_config->has_dp_encoder) {
89b667f8 7401 /* Use SSC source */
bdd4b6a6 7402 if (pipe == PIPE_A)
ab3c759a 7403 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7404 0x0df40000);
7405 else
ab3c759a 7406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7407 0x0df70000);
7408 } else { /* HDMI or VGA */
7409 /* Use bend source */
bdd4b6a6 7410 if (pipe == PIPE_A)
ab3c759a 7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7412 0x0df70000);
7413 else
ab3c759a 7414 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7415 0x0df40000);
7416 }
a0c4da24 7417
ab3c759a 7418 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7419 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7421 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7422 coreclk |= 0x01000000;
ab3c759a 7423 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7424
ab3c759a 7425 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7426 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7427}
7428
d288f65f 7429static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7430 struct intel_crtc_state *pipe_config)
1ae0d137 7431{
d288f65f 7432 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7433 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7434 DPLL_VCO_ENABLE;
7435 if (crtc->pipe != PIPE_A)
d288f65f 7436 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7437
d288f65f
VS		 7438 pipe_config->dpll_hw_state.dpll_md =
7439 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7440}
7441
d288f65f 7442static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7443 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7444{
7445 struct drm_device *dev = crtc->base.dev;
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447 int pipe = crtc->pipe;
7448 int dpll_reg = DPLL(crtc->pipe);
7449 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7450 u32 loopfilter, tribuf_calcntr;
9d556c99 7451 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7452 u32 dpio_val;
9cbe40c1 7453 int vco;
9d556c99 7454
d288f65f
VS		 7455 bestn = pipe_config->dpll.n;
7456 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7457 bestm1 = pipe_config->dpll.m1;
7458 bestm2 = pipe_config->dpll.m2 >> 22;
7459 bestp1 = pipe_config->dpll.p1;
7460 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7461 vco = pipe_config->dpll.vco;
a945ce7e 7462 dpio_val = 0;
9cbe40c1 7463 loopfilter = 0;
9d556c99
CML		 7464
7465 /*
7466 * Enable Refclk and SSC
7467 */
a11b0703 7468 I915_WRITE(dpll_reg,
d288f65f 7469 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7470
a580516d 7471 mutex_lock(&dev_priv->sb_lock);
9d556c99 7472
9d556c99
CML		 7473 /* p1 and p2 divider */
7474 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7475 5 << DPIO_CHV_S1_DIV_SHIFT |
7476 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7477 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7478 1 << DPIO_CHV_K_DIV_SHIFT);
7479
7480 /* Feedback post-divider - m2 */
7481 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7482
7483 /* Feedback refclk divider - n and m1 */
7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7485 DPIO_CHV_M1_DIV_BY_2 |
7486 1 << DPIO_CHV_N_DIV_SHIFT);
7487
7488 /* M2 fraction division */
a945ce7e
VP		 7489 if (bestm2_frac)
7490 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7491
7492 /* M2 fraction division enable */
a945ce7e
VP		 7493 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7494 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7495 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7496 if (bestm2_frac)
7497 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7498 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7499
de3a0fde
VP		 7500 /* Program digital lock detect threshold */
7501 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7502 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7503 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7504 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7505 if (!bestm2_frac)
7506 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7507 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7508
9d556c99 7509 /* Loop filter */
9cbe40c1
VP		 7510 if (vco == 5400000) {
7511 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7512 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7513 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7514 tribuf_calcntr = 0x9;
7515 } else if (vco <= 6200000) {
7516 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7517 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7518 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7519 tribuf_calcntr = 0x9;
7520 } else if (vco <= 6480000) {
7521 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7522 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7523 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7524 tribuf_calcntr = 0x8;
7525 } else {
7526 /* Not supported. Apply the same limits as in the max case */
7527 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7528 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7529 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7530 tribuf_calcntr = 0;
7531 }
9d556c99
CML		 7532 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7533
968040b2 7534 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7535 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7536 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7537 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7538
9d556c99
CML		 7539 /* AFC Recal */
7540 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7541 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7542 DPIO_AFC_RECAL);
7543
a580516d 7544 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7545}
7546
d288f65f
VS		 7547/**
7548 * vlv_force_pll_on - forcibly enable just the PLL
7549 * @dev_priv: i915 private structure
7550 * @pipe: pipe PLL to enable
7551 * @dpll: PLL configuration
7552 *
7553 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7554 * in cases where we need the PLL enabled even when @pipe is not going to
7555 * be enabled.
7556 */
7557void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7558 const struct dpll *dpll)
7559{
7560 struct intel_crtc *crtc =
7561 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7562 struct intel_crtc_state pipe_config = {
a93e255f 7563 .base.crtc = &crtc->base,
d288f65f
VS		 7564 .pixel_multiplier = 1,
7565 .dpll = *dpll,
7566 };
7567
7568 if (IS_CHERRYVIEW(dev)) {
7569 chv_update_pll(crtc, &pipe_config);
7570 chv_prepare_pll(crtc, &pipe_config);
7571 chv_enable_pll(crtc, &pipe_config);
7572 } else {
7573 vlv_update_pll(crtc, &pipe_config);
7574 vlv_prepare_pll(crtc, &pipe_config);
7575 vlv_enable_pll(crtc, &pipe_config);
7576 }
7577}
7578
7579/**
7580 * vlv_force_pll_off - forcibly disable just the PLL
7581 * @dev_priv: i915 private structure
7582 * @pipe: pipe PLL to disable
7583 *
7584 * Disable the PLL for @pipe. To be used in cases where we need
7585 * the PLL enabled even when @pipe is not going to be enabled.
7586 */
7587void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7588{
7589 if (IS_CHERRYVIEW(dev))
7590 chv_disable_pll(to_i915(dev), pipe);
7591 else
7592 vlv_disable_pll(to_i915(dev), pipe);
7593}
7594
f47709a9 7595static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7596 struct intel_crtc_state *crtc_state,
f47709a9 7597 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7598 int num_connectors)
7599{
f47709a9 7600 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7601 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7602 u32 dpll;
7603 bool is_sdvo;
190f68c5 7604 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7605
190f68c5 7606 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7607
a93e255f
ACO		 7608 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7609 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7610
7611 dpll = DPLL_VGA_MODE_DIS;
7612
a93e255f 7613 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7614 dpll |= DPLLB_MODE_LVDS;
7615 else
7616 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7617
ef1b460d 7618 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7619 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7620 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7621 }
198a037f
DV		 7622
7623 if (is_sdvo)
4a33e48d 7624 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7625
190f68c5 7626 if (crtc_state->has_dp_encoder)
4a33e48d 7627 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7628
7629 /* compute bitmask from p1 value */
7630 if (IS_PINEVIEW(dev))
7631 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7632 else {
7633 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7634 if (IS_G4X(dev) && reduced_clock)
7635 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7636 }
7637 switch (clock->p2) {
7638 case 5:
7639 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7640 break;
7641 case 7:
7642 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7643 break;
7644 case 10:
7645 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7646 break;
7647 case 14:
7648 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7649 break;
7650 }
7651 if (INTEL_INFO(dev)->gen >= 4)
7652 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7653
190f68c5 7654 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7655 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7656 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7657 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7658 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7659 else
7660 dpll |= PLL_REF_INPUT_DREFCLK;
7661
7662 dpll |= DPLL_VCO_ENABLE;
190f68c5 7663 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7664
eb1cbe48 7665 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7666 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7667 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7668 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7669 }
7670}
7671
f47709a9 7672static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7673 struct intel_crtc_state *crtc_state,
f47709a9 7674 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7675 int num_connectors)
7676{
f47709a9 7677 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7678 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7679 u32 dpll;
190f68c5 7680 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7681
190f68c5 7682 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7683
eb1cbe48
DV		 7684 dpll = DPLL_VGA_MODE_DIS;
7685
a93e255f 7686 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7687 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7688 } else {
7689 if (clock->p1 == 2)
7690 dpll |= PLL_P1_DIVIDE_BY_TWO;
7691 else
7692 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7693 if (clock->p2 == 4)
7694 dpll |= PLL_P2_DIVIDE_BY_4;
7695 }
7696
a93e255f 7697 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7698 dpll |= DPLL_DVO_2X_MODE;
7699
a93e255f 7700 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7701 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7702 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7703 else
7704 dpll |= PLL_REF_INPUT_DREFCLK;
7705
7706 dpll |= DPLL_VCO_ENABLE;
190f68c5 7707 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7708}
7709
8a654f3b 7710static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7711{
7712 struct drm_device *dev = intel_crtc->base.dev;
7713 struct drm_i915_private *dev_priv = dev->dev_private;
7714 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7715 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7716 struct drm_display_mode *adjusted_mode =
6e3c9717 7717 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7718 uint32_t crtc_vtotal, crtc_vblank_end;
7719 int vsyncshift = 0;
4d8a62ea
DV		 7720
7721 /* We need to be careful not to changed the adjusted mode, for otherwise
7722 * the hw state checker will get angry at the mismatch. */
7723 crtc_vtotal = adjusted_mode->crtc_vtotal;
7724 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7725
609aeaca 7726 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7727 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7728 crtc_vtotal -= 1;
7729 crtc_vblank_end -= 1;
609aeaca 7730
409ee761 7731 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7732 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7733 else
7734 vsyncshift = adjusted_mode->crtc_hsync_start -
7735 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7736 if (vsyncshift < 0)
7737 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7738 }
7739
7740 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7741 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7742
fe2b8f9d 7743 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7744 (adjusted_mode->crtc_hdisplay - 1) |
7745 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7746 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7747 (adjusted_mode->crtc_hblank_start - 1) |
7748 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7749 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7750 (adjusted_mode->crtc_hsync_start - 1) |
7751 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7752
fe2b8f9d 7753 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7754 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7755 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7756 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7757 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7758 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7759 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7760 (adjusted_mode->crtc_vsync_start - 1) |
7761 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7762
b5e508d4
PZ		 7763 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7764 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7765 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7766 * bits. */
7767 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7768 (pipe == PIPE_B || pipe == PIPE_C))
7769 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7770
b0e77b9c
PZ		 7771 /* pipesrc controls the size that is scaled from, which should
7772 * always be the user's requested size.
7773 */
7774 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7775 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7776 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7777}
7778
1bd1bd80 7779static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7780 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7781{
7782 struct drm_device *dev = crtc->base.dev;
7783 struct drm_i915_private *dev_priv = dev->dev_private;
7784 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7785 uint32_t tmp;
7786
7787 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7788 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7789 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7790 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7791 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7792 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7793 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7794 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7795 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7796
7797 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7798 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7799 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7800 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7801 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7802 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7803 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7804 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7805 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7806
7807 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7808 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7809 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7810 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7811 }
7812
7813 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7814 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7815 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7816
2d112de7
ACO		 7817 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7818 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7819}
7820
f6a83288 7821void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7822 struct intel_crtc_state *pipe_config)
babea61d 7823{
2d112de7
ACO		 7824 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7825 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7826 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7827 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7828
2d112de7
ACO		 7829 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7830 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7831 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7832 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7833
2d112de7 7834 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7835
2d112de7
ACO		 7836 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7837 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7838}
7839
84b046f3
DV		 7840static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7841{
7842 struct drm_device *dev = intel_crtc->base.dev;
7843 struct drm_i915_private *dev_priv = dev->dev_private;
7844 uint32_t pipeconf;
7845
9f11a9e4 7846 pipeconf = 0;
84b046f3 7847
b6b5d049
VS		 7848 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7849 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7850 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7851
6e3c9717 7852 if (intel_crtc->config->double_wide)
cf532bb2 7853 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7854
ff9ce46e
DV		 7855 /* only g4x and later have fancy bpc/dither controls */
7856 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7857 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7858 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7859 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7860 PIPECONF_DITHER_TYPE_SP;
84b046f3 7861
6e3c9717 7862 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7863 case 18:
7864 pipeconf |= PIPECONF_6BPC;
7865 break;
7866 case 24:
7867 pipeconf |= PIPECONF_8BPC;
7868 break;
7869 case 30:
7870 pipeconf |= PIPECONF_10BPC;
7871 break;
7872 default:
7873 /* Case prevented by intel_choose_pipe_bpp_dither. */
7874 BUG();
84b046f3
DV		 7875 }
7876 }
7877
7878 if (HAS_PIPE_CXSR(dev)) {
7879 if (intel_crtc->lowfreq_avail) {
7880 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7881 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7882 } else {
7883 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7884 }
7885 }
7886
6e3c9717 7887 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7888 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7889 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7890 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7891 else
7892 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7893 } else
84b046f3
DV		 7894 pipeconf |= PIPECONF_PROGRESSIVE;
7895
6e3c9717 7896 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7897 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7898
84b046f3
DV		 7899 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7900 POSTING_READ(PIPECONF(intel_crtc->pipe));
7901}
7902
190f68c5
ACO		 7903static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7904 struct intel_crtc_state *crtc_state)
79e53945 7905{
c7653199 7906 struct drm_device *dev = crtc->base.dev;
79e53945 7907 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7908 int refclk, num_connectors = 0;
652c393a 7909 intel_clock_t clock, reduced_clock;
a16af721 7910 bool ok, has_reduced_clock = false;
e9fd1c02 7911 bool is_lvds = false, is_dsi = false;
5eddb70b 7912 struct intel_encoder *encoder;
d4906093 7913 const intel_limit_t *limit;
55bb9992 7914 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7915 struct drm_connector *connector;
55bb9992
ACO		 7916 struct drm_connector_state *connector_state;
7917 int i;
79e53945 7918
dd3cd74a
ACO		 7919 memset(&crtc_state->dpll_hw_state, 0,
7920 sizeof(crtc_state->dpll_hw_state));
7921
da3ced29 7922 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7923 if (connector_state->crtc != &crtc->base)
7924 continue;
7925
7926 encoder = to_intel_encoder(connector_state->best_encoder);
7927
5eddb70b 7928 switch (encoder->type) {
79e53945
JB		 7929 case INTEL_OUTPUT_LVDS:
7930 is_lvds = true;
7931 break;
e9fd1c02
JN		 7932 case INTEL_OUTPUT_DSI:
7933 is_dsi = true;
7934 break;
6847d71b
PZ		 7935 default:
7936 break;
79e53945 7937 }
43565a06 7938
c751ce4f 7939 num_connectors++;
79e53945
JB		 7940 }
7941
f2335330 7942 if (is_dsi)
5b18e57c 7943 return 0;
f2335330 7944
190f68c5 7945 if (!crtc_state->clock_set) {
a93e255f 7946 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7947
e9fd1c02
JN		 7948 /*
7949 * Returns a set of divisors for the desired target clock with
7950 * the given refclk, or FALSE. The returned values represent
7951 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7952 * 2) / p1 / p2.
7953 */
a93e255f
ACO		 7954 limit = intel_limit(crtc_state, refclk);
7955 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7956 crtc_state->port_clock,
e9fd1c02 7957 refclk, NULL, &clock);
f2335330 7958 if (!ok) {
e9fd1c02
JN		 7959 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7960 return -EINVAL;
7961 }
79e53945 7962
f2335330
JN		 7963 if (is_lvds && dev_priv->lvds_downclock_avail) {
7964 /*
7965 * Ensure we match the reduced clock's P to the target
7966 * clock. If the clocks don't match, we can't switch
7967 * the display clock by using the FP0/FP1. In such case
7968 * we will disable the LVDS downclock feature.
7969 */
7970 has_reduced_clock =
a93e255f 7971 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7972 dev_priv->lvds_downclock,
7973 refclk, &clock,
7974 &reduced_clock);
7975 }
7976 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7977 crtc_state->dpll.n = clock.n;
7978 crtc_state->dpll.m1 = clock.m1;
7979 crtc_state->dpll.m2 = clock.m2;
7980 crtc_state->dpll.p1 = clock.p1;
7981 crtc_state->dpll.p2 = clock.p2;
f47709a9 7982 }
7026d4ac 7983
e9fd1c02 7984 if (IS_GEN2(dev)) {
190f68c5 7985 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7986 has_reduced_clock ? &reduced_clock : NULL,
7987 num_connectors);
9d556c99 7988 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7989 chv_update_pll(crtc, crtc_state);
e9fd1c02 7990 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7991 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7992 } else {
190f68c5 7993 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7994 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7995 num_connectors);
e9fd1c02 7996 }
79e53945 7997
c8f7a0db 7998 return 0;
f564048e
EA		 7999}
8000
2fa2fe9a 8001static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8002 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8003{
8004 struct drm_device *dev = crtc->base.dev;
8005 struct drm_i915_private *dev_priv = dev->dev_private;
8006 uint32_t tmp;
8007
dc9e7dec
VS		 8008 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8009 return;
8010
2fa2fe9a 8011 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 8012 if (!(tmp & PFIT_ENABLE))
8013 return;
2fa2fe9a 8014
06922821 8015 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 8016 if (INTEL_INFO(dev)->gen < 4) {
8017 if (crtc->pipe != PIPE_B)
8018 return;
2fa2fe9a
DV		 8019 } else {
8020 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8021 return;
8022 }
8023
06922821 8024 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 8025 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8026 if (INTEL_INFO(dev)->gen < 5)
8027 pipe_config->gmch_pfit.lvds_border_bits =
8028 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8029}
8030
acbec814 8031static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8032 struct intel_crtc_state *pipe_config)
acbec814
JB		 8033{
8034 struct drm_device *dev = crtc->base.dev;
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 int pipe = pipe_config->cpu_transcoder;
8037 intel_clock_t clock;
8038 u32 mdiv;
662c6ecb 8039 int refclk = 100000;
acbec814 8040
f573de5a
SK		 8041 /* In case of MIPI DPLL will not even be used */
8042 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8043 return;
8044
a580516d 8045 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8046 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8047 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8048
8049 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8050 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8051 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8052 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8053 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8054
f646628b 8055 vlv_clock(refclk, &clock);
acbec814 8056
f646628b
VS		 8057 /* clock.dot is the fast clock */
8058 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8059}
8060
5724dbd1
DL		 8061static void
8062i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8063 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8064{
8065 struct drm_device *dev = crtc->base.dev;
8066 struct drm_i915_private *dev_priv = dev->dev_private;
8067 u32 val, base, offset;
8068 int pipe = crtc->pipe, plane = crtc->plane;
8069 int fourcc, pixel_format;
6761dd31 8070 unsigned int aligned_height;
b113d5ee 8071 struct drm_framebuffer *fb;
1b842c89 8072 struct intel_framebuffer *intel_fb;
1ad292b5 8073
42a7b088
DL		 8074 val = I915_READ(DSPCNTR(plane));
8075 if (!(val & DISPLAY_PLANE_ENABLE))
8076 return;
8077
d9806c9f 8078 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8079 if (!intel_fb) {
1ad292b5
JB		 8080 DRM_DEBUG_KMS("failed to alloc fb\n");
8081 return;
8082 }
8083
1b842c89
DL		 8084 fb = &intel_fb->base;
8085
18c5247e
DV		 8086 if (INTEL_INFO(dev)->gen >= 4) {
8087 if (val & DISPPLANE_TILED) {
49af449b 8088 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8089 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8090 }
8091 }
1ad292b5
JB		 8092
8093 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8094 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8095 fb->pixel_format = fourcc;
8096 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8097
8098 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8099 if (plane_config->tiling)
1ad292b5
JB		 8100 offset = I915_READ(DSPTILEOFF(plane));
8101 else
8102 offset = I915_READ(DSPLINOFF(plane));
8103 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8104 } else {
8105 base = I915_READ(DSPADDR(plane));
8106 }
8107 plane_config->base = base;
8108
8109 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8110 fb->width = ((val >> 16) & 0xfff) + 1;
8111 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8112
8113 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8114 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8115
b113d5ee 8116 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8117 fb->pixel_format,
8118 fb->modifier[0]);
1ad292b5 8119
f37b5c2b 8120 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8121
2844a921
DL		 8122 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8123 pipe_name(pipe), plane, fb->width, fb->height,
8124 fb->bits_per_pixel, base, fb->pitches[0],
8125 plane_config->size);
1ad292b5 8126
2d14030b 8127 plane_config->fb = intel_fb;
1ad292b5
JB		 8128}
8129
70b23a98 8130static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8131 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8132{
8133 struct drm_device *dev = crtc->base.dev;
8134 struct drm_i915_private *dev_priv = dev->dev_private;
8135 int pipe = pipe_config->cpu_transcoder;
8136 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8137 intel_clock_t clock;
8138 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8139 int refclk = 100000;
8140
a580516d 8141 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8142 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8143 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8144 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8145 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8146 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8147
8148 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8149 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8150 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8151 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8152 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8153
8154 chv_clock(refclk, &clock);
8155
8156 /* clock.dot is the fast clock */
8157 pipe_config->port_clock = clock.dot / 5;
8158}
8159
0e8ffe1b 8160static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8161 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8162{
8163 struct drm_device *dev = crtc->base.dev;
8164 struct drm_i915_private *dev_priv = dev->dev_private;
8165 uint32_t tmp;
8166
f458ebbc
DV		 8167 if (!intel_display_power_is_enabled(dev_priv,
8168 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8169 return false;
8170
e143a21c 8171 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8172 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8173
0e8ffe1b
DV		 8174 tmp = I915_READ(PIPECONF(crtc->pipe));
8175 if (!(tmp & PIPECONF_ENABLE))
8176 return false;
8177
42571aef
VS		 8178 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8179 switch (tmp & PIPECONF_BPC_MASK) {
8180 case PIPECONF_6BPC:
8181 pipe_config->pipe_bpp = 18;
8182 break;
8183 case PIPECONF_8BPC:
8184 pipe_config->pipe_bpp = 24;
8185 break;
8186 case PIPECONF_10BPC:
8187 pipe_config->pipe_bpp = 30;
8188 break;
8189 default:
8190 break;
8191 }
8192 }
8193
b5a9fa09
DV		 8194 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8195 pipe_config->limited_color_range = true;
8196
282740f7
VS		 8197 if (INTEL_INFO(dev)->gen < 4)
8198 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8199
1bd1bd80
DV		 8200 intel_get_pipe_timings(crtc, pipe_config);
8201
2fa2fe9a
DV		 8202 i9xx_get_pfit_config(crtc, pipe_config);
8203
6c49f241
DV		 8204 if (INTEL_INFO(dev)->gen >= 4) {
8205 tmp = I915_READ(DPLL_MD(crtc->pipe));
8206 pipe_config->pixel_multiplier =
8207 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8208 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8209 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8210 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8211 tmp = I915_READ(DPLL(crtc->pipe));
8212 pipe_config->pixel_multiplier =
8213 ((tmp & SDVO_MULTIPLIER_MASK)
8214 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8215 } else {
8216 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8217 * port and will be fixed up in the encoder->get_config
8218 * function. */
8219 pipe_config->pixel_multiplier = 1;
8220 }
8bcc2795
DV		 8221 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8222 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8223 /*
8224 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8225 * on 830. Filter it out here so that we don't
8226 * report errors due to that.
8227 */
8228 if (IS_I830(dev))
8229 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8230
8bcc2795
DV		 8231 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8232 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8233 } else {
8234 /* Mask out read-only status bits. */
8235 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8236 DPLL_PORTC_READY_MASK |
8237 DPLL_PORTB_READY_MASK);
8bcc2795 8238 }
6c49f241 8239
70b23a98
VS		 8240 if (IS_CHERRYVIEW(dev))
8241 chv_crtc_clock_get(crtc, pipe_config);
8242 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8243 vlv_crtc_clock_get(crtc, pipe_config);
8244 else
8245 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8246
0e8ffe1b
DV		 8247 return true;
8248}
8249
dde86e2d 8250static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8251{
8252 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8253 struct intel_encoder *encoder;
74cfd7ac 8254 u32 val, final;
13d83a67 8255 bool has_lvds = false;
199e5d79 8256 bool has_cpu_edp = false;
199e5d79 8257 bool has_panel = false;
99eb6a01
KP		 8258 bool has_ck505 = false;
8259 bool can_ssc = false;
13d83a67
JB		 8260
8261 /* We need to take the global config into account */
b2784e15 8262 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8263 switch (encoder->type) {
8264 case INTEL_OUTPUT_LVDS:
8265 has_panel = true;
8266 has_lvds = true;
8267 break;
8268 case INTEL_OUTPUT_EDP:
8269 has_panel = true;
2de6905f 8270 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8271 has_cpu_edp = true;
8272 break;
6847d71b
PZ		 8273 default:
8274 break;
13d83a67
JB		 8275 }
8276 }
8277
99eb6a01 8278 if (HAS_PCH_IBX(dev)) {
41aa3448 8279 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8280 can_ssc = has_ck505;
8281 } else {
8282 has_ck505 = false;
8283 can_ssc = true;
8284 }
8285
2de6905f
ID		 8286 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8287 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8288
8289 /* Ironlake: try to setup display ref clock before DPLL
8290 * enabling. This is only under driver's control after
8291 * PCH B stepping, previous chipset stepping should be
8292 * ignoring this setting.
8293 */
74cfd7ac
CW		 8294 val = I915_READ(PCH_DREF_CONTROL);
8295
8296 /* As we must carefully and slowly disable/enable each source in turn,
8297 * compute the final state we want first and check if we need to
8298 * make any changes at all.
8299 */
8300 final = val;
8301 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8302 if (has_ck505)
8303 final |= DREF_NONSPREAD_CK505_ENABLE;
8304 else
8305 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8306
8307 final &= ~DREF_SSC_SOURCE_MASK;
8308 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8309 final &= ~DREF_SSC1_ENABLE;
8310
8311 if (has_panel) {
8312 final |= DREF_SSC_SOURCE_ENABLE;
8313
8314 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8315 final |= DREF_SSC1_ENABLE;
8316
8317 if (has_cpu_edp) {
8318 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8319 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8320 else
8321 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8322 } else
8323 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8324 } else {
8325 final |= DREF_SSC_SOURCE_DISABLE;
8326 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8327 }
8328
8329 if (final == val)
8330 return;
8331
13d83a67 8332 /* Always enable nonspread source */
74cfd7ac 8333 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8334
99eb6a01 8335 if (has_ck505)
74cfd7ac 8336 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8337 else
74cfd7ac 8338 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8339
199e5d79 8340 if (has_panel) {
74cfd7ac
CW		 8341 val &= ~DREF_SSC_SOURCE_MASK;
8342 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8343
199e5d79 8344 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8345 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8346 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8347 val |= DREF_SSC1_ENABLE;
e77166b5 8348 } else
74cfd7ac 8349 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8350
8351 /* Get SSC going before enabling the outputs */
74cfd7ac 8352 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8353 POSTING_READ(PCH_DREF_CONTROL);
8354 udelay(200);
8355
74cfd7ac 8356 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8357
8358 /* Enable CPU source on CPU attached eDP */
199e5d79 8359 if (has_cpu_edp) {
99eb6a01 8360 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8361 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8362 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8363 } else
74cfd7ac 8364 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8365 } else
74cfd7ac 8366 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8367
74cfd7ac 8368 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8369 POSTING_READ(PCH_DREF_CONTROL);
8370 udelay(200);
8371 } else {
8372 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8373
74cfd7ac 8374 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8375
8376 /* Turn off CPU output */
74cfd7ac 8377 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8378
74cfd7ac 8379 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8380 POSTING_READ(PCH_DREF_CONTROL);
8381 udelay(200);
8382
8383 /* Turn off the SSC source */
74cfd7ac
CW		 8384 val &= ~DREF_SSC_SOURCE_MASK;
8385 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8386
8387 /* Turn off SSC1 */
74cfd7ac 8388 val &= ~DREF_SSC1_ENABLE;
199e5d79 8389
74cfd7ac 8390 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8391 POSTING_READ(PCH_DREF_CONTROL);
8392 udelay(200);
8393 }
74cfd7ac
CW		 8394
8395 BUG_ON(val != final);
13d83a67
JB		 8396}
8397
f31f2d55 8398static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8399{
f31f2d55 8400 uint32_t tmp;
dde86e2d 8401
0ff066a9
PZ		 8402 tmp = I915_READ(SOUTH_CHICKEN2);
8403 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8404 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8405
0ff066a9
PZ		 8406 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8407 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8408 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8409
0ff066a9
PZ		 8410 tmp = I915_READ(SOUTH_CHICKEN2);
8411 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8412 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8413
0ff066a9
PZ		 8414 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8415 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8416 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8417}
8418
8419/* WaMPhyProgramming:hsw */
8420static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8421{
8422 uint32_t tmp;
dde86e2d
PZ		 8423
8424 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8425 tmp &= ~(0xFF << 24);
8426 tmp |= (0x12 << 24);
8427 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8428
dde86e2d
PZ		 8429 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8430 tmp |= (1 << 11);
8431 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8432
8433 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8434 tmp |= (1 << 11);
8435 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8436
dde86e2d
PZ		 8437 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8438 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8439 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8440
8441 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8442 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8443 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8444
0ff066a9
PZ		 8445 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8446 tmp &= ~(7 << 13);
8447 tmp |= (5 << 13);
8448 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8449
0ff066a9
PZ		 8450 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8451 tmp &= ~(7 << 13);
8452 tmp |= (5 << 13);
8453 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8454
8455 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8456 tmp &= ~0xFF;
8457 tmp |= 0x1C;
8458 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8459
8460 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8461 tmp &= ~0xFF;
8462 tmp |= 0x1C;
8463 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8466 tmp &= ~(0xFF << 16);
8467 tmp |= (0x1C << 16);
8468 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8471 tmp &= ~(0xFF << 16);
8472 tmp |= (0x1C << 16);
8473 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8474
0ff066a9
PZ		 8475 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8476 tmp |= (1 << 27);
8477 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8478
0ff066a9
PZ		 8479 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8480 tmp |= (1 << 27);
8481 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8482
0ff066a9
PZ		 8483 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8484 tmp &= ~(0xF << 28);
8485 tmp |= (4 << 28);
8486 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8487
0ff066a9
PZ		 8488 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8489 tmp &= ~(0xF << 28);
8490 tmp |= (4 << 28);
8491 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8492}
8493
2fa86a1f
PZ		 8494/* Implements 3 different sequences from BSpec chapter "Display iCLK
8495 * Programming" based on the parameters passed:
8496 * - Sequence to enable CLKOUT_DP
8497 * - Sequence to enable CLKOUT_DP without spread
8498 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8499 */
8500static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8501 bool with_fdi)
f31f2d55
PZ		 8502{
8503 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8504 uint32_t reg, tmp;
8505
8506 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8507 with_spread = true;
8508 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8509 with_fdi, "LP PCH doesn't have FDI\n"))
8510 with_fdi = false;
f31f2d55 8511
a580516d 8512 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8513
8514 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8515 tmp &= ~SBI_SSCCTL_DISABLE;
8516 tmp |= SBI_SSCCTL_PATHALT;
8517 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8518
8519 udelay(24);
8520
2fa86a1f
PZ		 8521 if (with_spread) {
8522 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8523 tmp &= ~SBI_SSCCTL_PATHALT;
8524 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8525
2fa86a1f
PZ		 8526 if (with_fdi) {
8527 lpt_reset_fdi_mphy(dev_priv);
8528 lpt_program_fdi_mphy(dev_priv);
8529 }
8530 }
dde86e2d 8531
2fa86a1f
PZ		 8532 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8533 SBI_GEN0 : SBI_DBUFF0;
8534 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8535 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8536 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8537
a580516d 8538 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8539}
8540
47701c3b
PZ		 8541/* Sequence to disable CLKOUT_DP */
8542static void lpt_disable_clkout_dp(struct drm_device *dev)
8543{
8544 struct drm_i915_private *dev_priv = dev->dev_private;
8545 uint32_t reg, tmp;
8546
a580516d 8547 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8548
8549 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8550 SBI_GEN0 : SBI_DBUFF0;
8551 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8552 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8553 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8554
8555 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8556 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8557 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8558 tmp |= SBI_SSCCTL_PATHALT;
8559 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8560 udelay(32);
8561 }
8562 tmp |= SBI_SSCCTL_DISABLE;
8563 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8564 }
8565
a580516d 8566 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8567}
8568
bf8fa3d3
PZ		 8569static void lpt_init_pch_refclk(struct drm_device *dev)
8570{
bf8fa3d3
PZ		 8571 struct intel_encoder *encoder;
8572 bool has_vga = false;
8573
b2784e15 8574 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8575 switch (encoder->type) {
8576 case INTEL_OUTPUT_ANALOG:
8577 has_vga = true;
8578 break;
6847d71b
PZ		 8579 default:
8580 break;
bf8fa3d3
PZ		 8581 }
8582 }
8583
47701c3b
PZ		 8584 if (has_vga)
8585 lpt_enable_clkout_dp(dev, true, true);
8586 else
8587 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8588}
8589
dde86e2d
PZ		 8590/*
8591 * Initialize reference clocks when the driver loads
8592 */
8593void intel_init_pch_refclk(struct drm_device *dev)
8594{
8595 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8596 ironlake_init_pch_refclk(dev);
8597 else if (HAS_PCH_LPT(dev))
8598 lpt_init_pch_refclk(dev);
8599}
8600
55bb9992 8601static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8602{
55bb9992 8603 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8604 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8605 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8606 struct drm_connector *connector;
55bb9992 8607 struct drm_connector_state *connector_state;
d9d444cb 8608 struct intel_encoder *encoder;
55bb9992 8609 int num_connectors = 0, i;
d9d444cb
JB		 8610 bool is_lvds = false;
8611
da3ced29 8612 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8613 if (connector_state->crtc != crtc_state->base.crtc)
8614 continue;
8615
8616 encoder = to_intel_encoder(connector_state->best_encoder);
8617
d9d444cb
JB		 8618 switch (encoder->type) {
8619 case INTEL_OUTPUT_LVDS:
8620 is_lvds = true;
8621 break;
6847d71b
PZ		 8622 default:
8623 break;
d9d444cb
JB		 8624 }
8625 num_connectors++;
8626 }
8627
8628 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8629 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8630 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8631 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8632 }
8633
8634 return 120000;
8635}
8636
6ff93609 8637static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8638{
c8203565 8639 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8641 int pipe = intel_crtc->pipe;
c8203565
PZ		 8642 uint32_t val;
8643
78114071 8644 val = 0;
c8203565 8645
6e3c9717 8646 switch (intel_crtc->config->pipe_bpp) {
c8203565 8647 case 18:
dfd07d72 8648 val |= PIPECONF_6BPC;
c8203565
PZ		 8649 break;
8650 case 24:
dfd07d72 8651 val |= PIPECONF_8BPC;
c8203565
PZ		 8652 break;
8653 case 30:
dfd07d72 8654 val |= PIPECONF_10BPC;
c8203565
PZ		 8655 break;
8656 case 36:
dfd07d72 8657 val |= PIPECONF_12BPC;
c8203565
PZ		 8658 break;
8659 default:
cc769b62
PZ		 8660 /* Case prevented by intel_choose_pipe_bpp_dither. */
8661 BUG();
c8203565
PZ		 8662 }
8663
6e3c9717 8664 if (intel_crtc->config->dither)
c8203565
PZ		 8665 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8666
6e3c9717 8667 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8668 val |= PIPECONF_INTERLACED_ILK;
8669 else
8670 val |= PIPECONF_PROGRESSIVE;
8671
6e3c9717 8672 if (intel_crtc->config->limited_color_range)
3685a8f3 8673 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8674
c8203565
PZ		 8675 I915_WRITE(PIPECONF(pipe), val);
8676 POSTING_READ(PIPECONF(pipe));
8677}
8678
86d3efce
VS		 8679/*
8680 * Set up the pipe CSC unit.
8681 *
8682 * Currently only full range RGB to limited range RGB conversion
8683 * is supported, but eventually this should handle various
8684 * RGB<->YCbCr scenarios as well.
8685 */
50f3b016 8686static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8687{
8688 struct drm_device *dev = crtc->dev;
8689 struct drm_i915_private *dev_priv = dev->dev_private;
8690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8691 int pipe = intel_crtc->pipe;
8692 uint16_t coeff = 0x7800; /* 1.0 */
8693
8694 /*
8695 * TODO: Check what kind of values actually come out of the pipe
8696 * with these coeff/postoff values and adjust to get the best
8697 * accuracy. Perhaps we even need to take the bpc value into
8698 * consideration.
8699 */
8700
6e3c9717 8701 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8702 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8703
8704 /*
8705 * GY/GU and RY/RU should be the other way around according
8706 * to BSpec, but reality doesn't agree. Just set them up in
8707 * a way that results in the correct picture.
8708 */
8709 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8710 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8711
8712 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8713 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8714
8715 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8716 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8717
8718 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8719 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8720 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8721
8722 if (INTEL_INFO(dev)->gen > 6) {
8723 uint16_t postoff = 0;
8724
6e3c9717 8725 if (intel_crtc->config->limited_color_range)
32cf0cb0 8726 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8727
8728 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8729 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8730 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8731
8732 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8733 } else {
8734 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8735
6e3c9717 8736 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8737 mode |= CSC_BLACK_SCREEN_OFFSET;
8738
8739 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8740 }
8741}
8742
6ff93609 8743static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8744{
756f85cf
PZ		 8745 struct drm_device *dev = crtc->dev;
8746 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8748 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8749 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8750 uint32_t val;
8751
3eff4faa 8752 val = 0;
ee2b0b38 8753
6e3c9717 8754 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8755 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8756
6e3c9717 8757 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8758 val |= PIPECONF_INTERLACED_ILK;
8759 else
8760 val |= PIPECONF_PROGRESSIVE;
8761
702e7a56
PZ		 8762 I915_WRITE(PIPECONF(cpu_transcoder), val);
8763 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8764
8765 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8766 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8767
3cdf122c 8768 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8769 val = 0;
8770
6e3c9717 8771 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8772 case 18:
8773 val |= PIPEMISC_DITHER_6_BPC;
8774 break;
8775 case 24:
8776 val |= PIPEMISC_DITHER_8_BPC;
8777 break;
8778 case 30:
8779 val |= PIPEMISC_DITHER_10_BPC;
8780 break;
8781 case 36:
8782 val |= PIPEMISC_DITHER_12_BPC;
8783 break;
8784 default:
8785 /* Case prevented by pipe_config_set_bpp. */
8786 BUG();
8787 }
8788
6e3c9717 8789 if (intel_crtc->config->dither)
756f85cf
PZ		 8790 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8791
8792 I915_WRITE(PIPEMISC(pipe), val);
8793 }
ee2b0b38
PZ		 8794}
8795
6591c6e4 8796static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8797 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8798 intel_clock_t *clock,
8799 bool *has_reduced_clock,
8800 intel_clock_t *reduced_clock)
8801{
8802 struct drm_device *dev = crtc->dev;
8803 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8804 int refclk;
d4906093 8805 const intel_limit_t *limit;
a16af721 8806 bool ret, is_lvds = false;
79e53945 8807
a93e255f 8808 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8809
55bb9992 8810 refclk = ironlake_get_refclk(crtc_state);
79e53945 8811
d4906093
ML		 8812 /*
8813 * Returns a set of divisors for the desired target clock with the given
8814 * refclk, or FALSE. The returned values represent the clock equation:
8815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8816 */
a93e255f
ACO		 8817 limit = intel_limit(crtc_state, refclk);
8818 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8819 crtc_state->port_clock,
ee9300bb 8820 refclk, NULL, clock);
6591c6e4
PZ		 8821 if (!ret)
8822 return false;
cda4b7d3 8823
ddc9003c 8824 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8825 /*
8826 * Ensure we match the reduced clock's P to the target clock.
8827 * If the clocks don't match, we can't switch the display clock
8828 * by using the FP0/FP1. In such case we will disable the LVDS
8829 * downclock feature.
8830 */
ee9300bb 8831 *has_reduced_clock =
a93e255f 8832 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8833 dev_priv->lvds_downclock,
8834 refclk, clock,
8835 reduced_clock);
652c393a 8836 }
61e9653f 8837
6591c6e4
PZ		 8838 return true;
8839}
8840
d4b1931c
PZ		 8841int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8842{
8843 /*
8844 * Account for spread spectrum to avoid
8845 * oversubscribing the link. Max center spread
8846 * is 2.5%; use 5% for safety's sake.
8847 */
8848 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8849 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8850}
8851
7429e9d4 8852static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8853{
7429e9d4 8854 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8855}
8856
de13a2e3 8857static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8858 struct intel_crtc_state *crtc_state,
7429e9d4 8859 u32 *fp,
9a7c7890 8860 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8861{
de13a2e3 8862 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8863 struct drm_device *dev = crtc->dev;
8864 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8865 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8866 struct drm_connector *connector;
55bb9992
ACO		 8867 struct drm_connector_state *connector_state;
8868 struct intel_encoder *encoder;
de13a2e3 8869 uint32_t dpll;
55bb9992 8870 int factor, num_connectors = 0, i;
09ede541 8871 bool is_lvds = false, is_sdvo = false;
79e53945 8872
da3ced29 8873 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8874 if (connector_state->crtc != crtc_state->base.crtc)
8875 continue;
8876
8877 encoder = to_intel_encoder(connector_state->best_encoder);
8878
8879 switch (encoder->type) {
79e53945
JB		 8880 case INTEL_OUTPUT_LVDS:
8881 is_lvds = true;
8882 break;
8883 case INTEL_OUTPUT_SDVO:
7d57382e 8884 case INTEL_OUTPUT_HDMI:
79e53945 8885 is_sdvo = true;
79e53945 8886 break;
6847d71b
PZ		 8887 default:
8888 break;
79e53945 8889 }
43565a06 8890
c751ce4f 8891 num_connectors++;
79e53945 8892 }
79e53945 8893
c1858123 8894 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8895 factor = 21;
8896 if (is_lvds) {
8897 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8898 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8899 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8900 factor = 25;
190f68c5 8901 } else if (crtc_state->sdvo_tv_clock)
8febb297 8902 factor = 20;
c1858123 8903
190f68c5 8904 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8905 *fp |= FP_CB_TUNE;
2c07245f 8906
9a7c7890
DV		 8907 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8908 *fp2 |= FP_CB_TUNE;
8909
5eddb70b 8910 dpll = 0;
2c07245f 8911
a07d6787
EA		 8912 if (is_lvds)
8913 dpll |= DPLLB_MODE_LVDS;
8914 else
8915 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8916
190f68c5 8917 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8918 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8919
8920 if (is_sdvo)
4a33e48d 8921 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8922 if (crtc_state->has_dp_encoder)
4a33e48d 8923 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8924
a07d6787 8925 /* compute bitmask from p1 value */
190f68c5 8926 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8927 /* also FPA1 */
190f68c5 8928 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8929
190f68c5 8930 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8931 case 5:
8932 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8933 break;
8934 case 7:
8935 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8936 break;
8937 case 10:
8938 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8939 break;
8940 case 14:
8941 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8942 break;
79e53945
JB		 8943 }
8944
b4c09f3b 8945 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8946 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8947 else
8948 dpll |= PLL_REF_INPUT_DREFCLK;
8949
959e16d6 8950 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8951}
8952
190f68c5
ACO		 8953static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8954 struct intel_crtc_state *crtc_state)
de13a2e3 8955{
c7653199 8956 struct drm_device *dev = crtc->base.dev;
de13a2e3 8957 intel_clock_t clock, reduced_clock;
cbbab5bd 8958 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8959 bool ok, has_reduced_clock = false;
8b47047b 8960 bool is_lvds = false;
e2b78267 8961 struct intel_shared_dpll *pll;
de13a2e3 8962
dd3cd74a
ACO		 8963 memset(&crtc_state->dpll_hw_state, 0,
8964 sizeof(crtc_state->dpll_hw_state));
8965
409ee761 8966 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8967
5dc5298b
PZ		 8968 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8969 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8970
190f68c5 8971 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8972 &has_reduced_clock, &reduced_clock);
190f68c5 8973 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8974 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8975 return -EINVAL;
79e53945 8976 }
f47709a9 8977 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8978 if (!crtc_state->clock_set) {
8979 crtc_state->dpll.n = clock.n;
8980 crtc_state->dpll.m1 = clock.m1;
8981 crtc_state->dpll.m2 = clock.m2;
8982 crtc_state->dpll.p1 = clock.p1;
8983 crtc_state->dpll.p2 = clock.p2;
f47709a9 8984 }
79e53945 8985
5dc5298b 8986 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8987 if (crtc_state->has_pch_encoder) {
8988 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8989 if (has_reduced_clock)
7429e9d4 8990 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8991
190f68c5 8992 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8993 &fp, &reduced_clock,
8994 has_reduced_clock ? &fp2 : NULL);
8995
190f68c5
ACO		 8996 crtc_state->dpll_hw_state.dpll = dpll;
8997 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8998 if (has_reduced_clock)
190f68c5 8999 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 9000 else
190f68c5 9001 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 9002
190f68c5 9003 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 9004 if (pll == NULL) {
84f44ce7 9005 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 9006 pipe_name(crtc->pipe));
4b645f14
JB		 9007 return -EINVAL;
9008 }
3fb37703 9009 }
79e53945 9010
ab585dea 9011 if (is_lvds && has_reduced_clock)
c7653199 9012 crtc->lowfreq_avail = true;
bcd644e0 9013 else
c7653199 9014 crtc->lowfreq_avail = false;
e2b78267 9015
c8f7a0db 9016 return 0;
79e53945
JB		 9017}
9018
eb14cb74
VS		 9019static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9020 struct intel_link_m_n *m_n)
9021{
9022 struct drm_device *dev = crtc->base.dev;
9023 struct drm_i915_private *dev_priv = dev->dev_private;
9024 enum pipe pipe = crtc->pipe;
9025
9026 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9027 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9028 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9029 & ~TU_SIZE_MASK;
9030 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9031 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9032 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9033}
9034
9035static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9036 enum transcoder transcoder,
b95af8be
VK		 9037 struct intel_link_m_n *m_n,
9038 struct intel_link_m_n *m2_n2)
72419203
DV		 9039{
9040 struct drm_device *dev = crtc->base.dev;
9041 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 9042 enum pipe pipe = crtc->pipe;
72419203 9043
eb14cb74
VS		 9044 if (INTEL_INFO(dev)->gen >= 5) {
9045 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9046 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9047 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9048 & ~TU_SIZE_MASK;
9049 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9050 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9051 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9052 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9053 * gen < 8) and if DRRS is supported (to make sure the
9054 * registers are not unnecessarily read).
9055 */
9056 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9057 crtc->config->has_drrs) {
b95af8be
VK		 9058 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9059 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9060 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9061 & ~TU_SIZE_MASK;
9062 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9063 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9064 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9065 }
eb14cb74
VS		 9066 } else {
9067 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9068 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9069 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9070 & ~TU_SIZE_MASK;
9071 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9072 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9073 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9074 }
9075}
9076
9077void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9078 struct intel_crtc_state *pipe_config)
eb14cb74 9079{
681a8504 9080 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9081 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9082 else
9083 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9084 &pipe_config->dp_m_n,
9085 &pipe_config->dp_m2_n2);
eb14cb74 9086}
72419203 9087
eb14cb74 9088static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9089 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9090{
9091 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9092 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9093}
9094
bd2e244f 9095static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9096 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9097{
9098 struct drm_device *dev = crtc->base.dev;
9099 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9100 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9101 uint32_t ps_ctrl = 0;
9102 int id = -1;
9103 int i;
bd2e244f 9104
a1b2278e
CK		 9105 /* find scaler attached to this pipe */
9106 for (i = 0; i < crtc->num_scalers; i++) {
9107 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9108 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9109 id = i;
9110 pipe_config->pch_pfit.enabled = true;
9111 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9112 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9113 break;
9114 }
9115 }
bd2e244f 9116
a1b2278e
CK		 9117 scaler_state->scaler_id = id;
9118 if (id >= 0) {
9119 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9120 } else {
9121 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9122 }
9123}
9124
5724dbd1
DL		 9125static void
9126skylake_get_initial_plane_config(struct intel_crtc *crtc,
9127 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9128{
9129 struct drm_device *dev = crtc->base.dev;
9130 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9131 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9132 int pipe = crtc->pipe;
9133 int fourcc, pixel_format;
6761dd31 9134 unsigned int aligned_height;
bc8d7dff 9135 struct drm_framebuffer *fb;
1b842c89 9136 struct intel_framebuffer *intel_fb;
bc8d7dff 9137
d9806c9f 9138 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9139 if (!intel_fb) {
bc8d7dff
DL		 9140 DRM_DEBUG_KMS("failed to alloc fb\n");
9141 return;
9142 }
9143
1b842c89
DL		 9144 fb = &intel_fb->base;
9145
bc8d7dff 9146 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9147 if (!(val & PLANE_CTL_ENABLE))
9148 goto error;
9149
bc8d7dff
DL		 9150 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9151 fourcc = skl_format_to_fourcc(pixel_format,
9152 val & PLANE_CTL_ORDER_RGBX,
9153 val & PLANE_CTL_ALPHA_MASK);
9154 fb->pixel_format = fourcc;
9155 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9156
40f46283
DL		 9157 tiling = val & PLANE_CTL_TILED_MASK;
9158 switch (tiling) {
9159 case PLANE_CTL_TILED_LINEAR:
9160 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9161 break;
9162 case PLANE_CTL_TILED_X:
9163 plane_config->tiling = I915_TILING_X;
9164 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9165 break;
9166 case PLANE_CTL_TILED_Y:
9167 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9168 break;
9169 case PLANE_CTL_TILED_YF:
9170 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9171 break;
9172 default:
9173 MISSING_CASE(tiling);
9174 goto error;
9175 }
9176
bc8d7dff
DL		 9177 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9178 plane_config->base = base;
9179
9180 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9181
9182 val = I915_READ(PLANE_SIZE(pipe, 0));
9183 fb->height = ((val >> 16) & 0xfff) + 1;
9184 fb->width = ((val >> 0) & 0x1fff) + 1;
9185
9186 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9187 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9188 fb->pixel_format);
bc8d7dff
DL		 9189 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9190
9191 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9192 fb->pixel_format,
9193 fb->modifier[0]);
bc8d7dff 9194
f37b5c2b 9195 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9196
9197 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9198 pipe_name(pipe), fb->width, fb->height,
9199 fb->bits_per_pixel, base, fb->pitches[0],
9200 plane_config->size);
9201
2d14030b 9202 plane_config->fb = intel_fb;
bc8d7dff
DL		 9203 return;
9204
9205error:
9206 kfree(fb);
9207}
9208
2fa2fe9a 9209static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9210 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9211{
9212 struct drm_device *dev = crtc->base.dev;
9213 struct drm_i915_private *dev_priv = dev->dev_private;
9214 uint32_t tmp;
9215
9216 tmp = I915_READ(PF_CTL(crtc->pipe));
9217
9218 if (tmp & PF_ENABLE) {
fd4daa9c 9219 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9220 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9221 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9222
9223 /* We currently do not free assignements of panel fitters on
9224 * ivb/hsw (since we don't use the higher upscaling modes which
9225 * differentiates them) so just WARN about this case for now. */
9226 if (IS_GEN7(dev)) {
9227 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9228 PF_PIPE_SEL_IVB(crtc->pipe));
9229 }
2fa2fe9a 9230 }
79e53945
JB		 9231}
9232
5724dbd1
DL		 9233static void
9234ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9235 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9236{
9237 struct drm_device *dev = crtc->base.dev;
9238 struct drm_i915_private *dev_priv = dev->dev_private;
9239 u32 val, base, offset;
aeee5a49 9240 int pipe = crtc->pipe;
4c6baa59 9241 int fourcc, pixel_format;
6761dd31 9242 unsigned int aligned_height;
b113d5ee 9243 struct drm_framebuffer *fb;
1b842c89 9244 struct intel_framebuffer *intel_fb;
4c6baa59 9245
42a7b088
DL		 9246 val = I915_READ(DSPCNTR(pipe));
9247 if (!(val & DISPLAY_PLANE_ENABLE))
9248 return;
9249
d9806c9f 9250 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9251 if (!intel_fb) {
4c6baa59
JB		 9252 DRM_DEBUG_KMS("failed to alloc fb\n");
9253 return;
9254 }
9255
1b842c89
DL		 9256 fb = &intel_fb->base;
9257
18c5247e
DV		 9258 if (INTEL_INFO(dev)->gen >= 4) {
9259 if (val & DISPPLANE_TILED) {
49af449b 9260 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9261 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9262 }
9263 }
4c6baa59
JB		 9264
9265 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9266 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9267 fb->pixel_format = fourcc;
9268 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9269
aeee5a49 9270 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9271 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9272 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9273 } else {
49af449b 9274 if (plane_config->tiling)
aeee5a49 9275 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9276 else
aeee5a49 9277 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9278 }
9279 plane_config->base = base;
9280
9281 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9282 fb->width = ((val >> 16) & 0xfff) + 1;
9283 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9284
9285 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9286 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9287
b113d5ee 9288 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9289 fb->pixel_format,
9290 fb->modifier[0]);
4c6baa59 9291
f37b5c2b 9292 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9293
2844a921
DL		 9294 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9295 pipe_name(pipe), fb->width, fb->height,
9296 fb->bits_per_pixel, base, fb->pitches[0],
9297 plane_config->size);
b113d5ee 9298
2d14030b 9299 plane_config->fb = intel_fb;
4c6baa59
JB		 9300}
9301
0e8ffe1b 9302static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9303 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9304{
9305 struct drm_device *dev = crtc->base.dev;
9306 struct drm_i915_private *dev_priv = dev->dev_private;
9307 uint32_t tmp;
9308
f458ebbc
DV		 9309 if (!intel_display_power_is_enabled(dev_priv,
9310 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9311 return false;
9312
e143a21c 9313 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9314 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9315
0e8ffe1b
DV		 9316 tmp = I915_READ(PIPECONF(crtc->pipe));
9317 if (!(tmp & PIPECONF_ENABLE))
9318 return false;
9319
42571aef
VS		 9320 switch (tmp & PIPECONF_BPC_MASK) {
9321 case PIPECONF_6BPC:
9322 pipe_config->pipe_bpp = 18;
9323 break;
9324 case PIPECONF_8BPC:
9325 pipe_config->pipe_bpp = 24;
9326 break;
9327 case PIPECONF_10BPC:
9328 pipe_config->pipe_bpp = 30;
9329 break;
9330 case PIPECONF_12BPC:
9331 pipe_config->pipe_bpp = 36;
9332 break;
9333 default:
9334 break;
9335 }
9336
b5a9fa09
DV		 9337 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9338 pipe_config->limited_color_range = true;
9339
ab9412ba 9340 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9341 struct intel_shared_dpll *pll;
9342
88adfff1
DV		 9343 pipe_config->has_pch_encoder = true;
9344
627eb5a3
DV		 9345 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9346 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9347 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9348
9349 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9350
c0d43d62 9351 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9352 pipe_config->shared_dpll =
9353 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9354 } else {
9355 tmp = I915_READ(PCH_DPLL_SEL);
9356 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9357 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9358 else
9359 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9360 }
66e985c0
DV		 9361
9362 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9363
9364 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9365 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9366
9367 tmp = pipe_config->dpll_hw_state.dpll;
9368 pipe_config->pixel_multiplier =
9369 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9370 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9371
9372 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9373 } else {
9374 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9375 }
9376
1bd1bd80
DV		 9377 intel_get_pipe_timings(crtc, pipe_config);
9378
2fa2fe9a
DV		 9379 ironlake_get_pfit_config(crtc, pipe_config);
9380
0e8ffe1b
DV		 9381 return true;
9382}
9383
be256dc7
PZ		 9384static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9385{
9386 struct drm_device *dev = dev_priv->dev;
be256dc7 9387 struct intel_crtc *crtc;
be256dc7 9388
d3fcc808 9389 for_each_intel_crtc(dev, crtc)
e2c719b7 9390 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9391 pipe_name(crtc->pipe));
9392
e2c719b7
RC		 9393 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9394 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9395 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9396 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9397 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9398 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9399 "CPU PWM1 enabled\n");
c5107b87 9400 if (IS_HASWELL(dev))
e2c719b7 9401 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9402 "CPU PWM2 enabled\n");
e2c719b7 9403 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9404 "PCH PWM1 enabled\n");
e2c719b7 9405 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9406 "Utility pin enabled\n");
e2c719b7 9407 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9408
9926ada1
PZ		 9409 /*
9410 * In theory we can still leave IRQs enabled, as long as only the HPD
9411 * interrupts remain enabled. We used to check for that, but since it's
9412 * gen-specific and since we only disable LCPLL after we fully disable
9413 * the interrupts, the check below should be enough.
9414 */
e2c719b7 9415 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9416}
9417
9ccd5aeb
PZ		 9418static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9419{
9420 struct drm_device *dev = dev_priv->dev;
9421
9422 if (IS_HASWELL(dev))
9423 return I915_READ(D_COMP_HSW);
9424 else
9425 return I915_READ(D_COMP_BDW);
9426}
9427
3c4c9b81
PZ		 9428static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9429{
9430 struct drm_device *dev = dev_priv->dev;
9431
9432 if (IS_HASWELL(dev)) {
9433 mutex_lock(&dev_priv->rps.hw_lock);
9434 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9435 val))
f475dadf 9436 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9437 mutex_unlock(&dev_priv->rps.hw_lock);
9438 } else {
9ccd5aeb
PZ		 9439 I915_WRITE(D_COMP_BDW, val);
9440 POSTING_READ(D_COMP_BDW);
3c4c9b81 9441 }
be256dc7
PZ		 9442}
9443
9444/*
9445 * This function implements pieces of two sequences from BSpec:
9446 * - Sequence for display software to disable LCPLL
9447 * - Sequence for display software to allow package C8+
9448 * The steps implemented here are just the steps that actually touch the LCPLL
9449 * register. Callers should take care of disabling all the display engine
9450 * functions, doing the mode unset, fixing interrupts, etc.
9451 */
6ff58d53
PZ		 9452static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9453 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9454{
9455 uint32_t val;
9456
9457 assert_can_disable_lcpll(dev_priv);
9458
9459 val = I915_READ(LCPLL_CTL);
9460
9461 if (switch_to_fclk) {
9462 val |= LCPLL_CD_SOURCE_FCLK;
9463 I915_WRITE(LCPLL_CTL, val);
9464
9465 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9466 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9467 DRM_ERROR("Switching to FCLK failed\n");
9468
9469 val = I915_READ(LCPLL_CTL);
9470 }
9471
9472 val |= LCPLL_PLL_DISABLE;
9473 I915_WRITE(LCPLL_CTL, val);
9474 POSTING_READ(LCPLL_CTL);
9475
9476 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9477 DRM_ERROR("LCPLL still locked\n");
9478
9ccd5aeb 9479 val = hsw_read_dcomp(dev_priv);
be256dc7 9480 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9481 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9482 ndelay(100);
9483
9ccd5aeb
PZ		 9484 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9485 1))
be256dc7
PZ		 9486 DRM_ERROR("D_COMP RCOMP still in progress\n");
9487
9488 if (allow_power_down) {
9489 val = I915_READ(LCPLL_CTL);
9490 val |= LCPLL_POWER_DOWN_ALLOW;
9491 I915_WRITE(LCPLL_CTL, val);
9492 POSTING_READ(LCPLL_CTL);
9493 }
9494}
9495
9496/*
9497 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9498 * source.
9499 */
6ff58d53 9500static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9501{
9502 uint32_t val;
9503
9504 val = I915_READ(LCPLL_CTL);
9505
9506 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9507 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9508 return;
9509
a8a8bd54
PZ		 9510 /*
9511 * Make sure we're not on PC8 state before disabling PC8, otherwise
9512 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9513 */
59bad947 9514 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9515
be256dc7
PZ		 9516 if (val & LCPLL_POWER_DOWN_ALLOW) {
9517 val &= ~LCPLL_POWER_DOWN_ALLOW;
9518 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9519 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9520 }
9521
9ccd5aeb 9522 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9523 val |= D_COMP_COMP_FORCE;
9524 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9525 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9526
9527 val = I915_READ(LCPLL_CTL);
9528 val &= ~LCPLL_PLL_DISABLE;
9529 I915_WRITE(LCPLL_CTL, val);
9530
9531 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9532 DRM_ERROR("LCPLL not locked yet\n");
9533
9534 if (val & LCPLL_CD_SOURCE_FCLK) {
9535 val = I915_READ(LCPLL_CTL);
9536 val &= ~LCPLL_CD_SOURCE_FCLK;
9537 I915_WRITE(LCPLL_CTL, val);
9538
9539 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9540 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9541 DRM_ERROR("Switching back to LCPLL failed\n");
9542 }
215733fa 9543
59bad947 9544 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9545 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9546}
9547
765dab67
PZ		 9548/*
9549 * Package states C8 and deeper are really deep PC states that can only be
9550 * reached when all the devices on the system allow it, so even if the graphics
9551 * device allows PC8+, it doesn't mean the system will actually get to these
9552 * states. Our driver only allows PC8+ when going into runtime PM.
9553 *
9554 * The requirements for PC8+ are that all the outputs are disabled, the power
9555 * well is disabled and most interrupts are disabled, and these are also
9556 * requirements for runtime PM. When these conditions are met, we manually do
9557 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9558 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9559 * hang the machine.
9560 *
9561 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9562 * the state of some registers, so when we come back from PC8+ we need to
9563 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9564 * need to take care of the registers kept by RC6. Notice that this happens even
9565 * if we don't put the device in PCI D3 state (which is what currently happens
9566 * because of the runtime PM support).
9567 *
9568 * For more, read "Display Sequences for Package C8" on the hardware
9569 * documentation.
9570 */
a14cb6fc 9571void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9572{
c67a470b
PZ		 9573 struct drm_device *dev = dev_priv->dev;
9574 uint32_t val;
9575
c67a470b
PZ		 9576 DRM_DEBUG_KMS("Enabling package C8+\n");
9577
c67a470b
PZ		 9578 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9579 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9580 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9581 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9582 }
9583
9584 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9585 hsw_disable_lcpll(dev_priv, true, true);
9586}
9587
a14cb6fc 9588void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9589{
9590 struct drm_device *dev = dev_priv->dev;
9591 uint32_t val;
9592
c67a470b
PZ		 9593 DRM_DEBUG_KMS("Disabling package C8+\n");
9594
9595 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9596 lpt_init_pch_refclk(dev);
9597
9598 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9599 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9600 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9601 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9602 }
9603
9604 intel_prepare_ddi(dev);
c67a470b
PZ		 9605}
9606
a821fc46 9607static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9608{
a821fc46 9609 struct drm_device *dev = old_state->dev;
f8437dd1 9610 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9611 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9612 int req_cdclk;
9613
9614 /* see the comment in valleyview_modeset_global_resources */
9615 if (WARN_ON(max_pixclk < 0))
9616 return;
9617
9618 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9619
9620 if (req_cdclk != dev_priv->cdclk_freq)
9621 broxton_set_cdclk(dev, req_cdclk);
9622}
9623
b432e5cf
VS		 9624/* compute the max rate for new configuration */
9625static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9626{
9627 struct drm_device *dev = dev_priv->dev;
9628 struct intel_crtc *intel_crtc;
9629 struct drm_crtc *crtc;
9630 int max_pixel_rate = 0;
9631 int pixel_rate;
9632
9633 for_each_crtc(dev, crtc) {
9634 if (!crtc->state->enable)
9635 continue;
9636
9637 intel_crtc = to_intel_crtc(crtc);
9638 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9639
9640 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9641 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9642 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9643
9644 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9645 }
9646
9647 return max_pixel_rate;
9648}
9649
9650static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9651{
9652 struct drm_i915_private *dev_priv = dev->dev_private;
9653 uint32_t val, data;
9654 int ret;
9655
9656 if (WARN((I915_READ(LCPLL_CTL) &
9657 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9658 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9659 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9660 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9661 "trying to change cdclk frequency with cdclk not enabled\n"))
9662 return;
9663
9664 mutex_lock(&dev_priv->rps.hw_lock);
9665 ret = sandybridge_pcode_write(dev_priv,
9666 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9667 mutex_unlock(&dev_priv->rps.hw_lock);
9668 if (ret) {
9669 DRM_ERROR("failed to inform pcode about cdclk change\n");
9670 return;
9671 }
9672
9673 val = I915_READ(LCPLL_CTL);
9674 val |= LCPLL_CD_SOURCE_FCLK;
9675 I915_WRITE(LCPLL_CTL, val);
9676
9677 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9678 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9679 DRM_ERROR("Switching to FCLK failed\n");
9680
9681 val = I915_READ(LCPLL_CTL);
9682 val &= ~LCPLL_CLK_FREQ_MASK;
9683
9684 switch (cdclk) {
9685 case 450000:
9686 val |= LCPLL_CLK_FREQ_450;
9687 data = 0;
9688 break;
9689 case 540000:
9690 val |= LCPLL_CLK_FREQ_54O_BDW;
9691 data = 1;
9692 break;
9693 case 337500:
9694 val |= LCPLL_CLK_FREQ_337_5_BDW;
9695 data = 2;
9696 break;
9697 case 675000:
9698 val |= LCPLL_CLK_FREQ_675_BDW;
9699 data = 3;
9700 break;
9701 default:
9702 WARN(1, "invalid cdclk frequency\n");
9703 return;
9704 }
9705
9706 I915_WRITE(LCPLL_CTL, val);
9707
9708 val = I915_READ(LCPLL_CTL);
9709 val &= ~LCPLL_CD_SOURCE_FCLK;
9710 I915_WRITE(LCPLL_CTL, val);
9711
9712 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9713 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9714 DRM_ERROR("Switching back to LCPLL failed\n");
9715
9716 mutex_lock(&dev_priv->rps.hw_lock);
9717 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9718 mutex_unlock(&dev_priv->rps.hw_lock);
9719
9720 intel_update_cdclk(dev);
9721
9722 WARN(cdclk != dev_priv->cdclk_freq,
9723 "cdclk requested %d kHz but got %d kHz\n",
9724 cdclk, dev_priv->cdclk_freq);
9725}
9726
9727static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9728 int max_pixel_rate)
9729{
9730 int cdclk;
9731
9732 /*
9733 * FIXME should also account for plane ratio
9734 * once 64bpp pixel formats are supported.
9735 */
9736 if (max_pixel_rate > 540000)
9737 cdclk = 675000;
9738 else if (max_pixel_rate > 450000)
9739 cdclk = 540000;
9740 else if (max_pixel_rate > 337500)
9741 cdclk = 450000;
9742 else
9743 cdclk = 337500;
9744
9745 /*
9746 * FIXME move the cdclk caclulation to
9747 * compute_config() so we can fail gracegully.
9748 */
9749 if (cdclk > dev_priv->max_cdclk_freq) {
9750 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9751 cdclk, dev_priv->max_cdclk_freq);
9752 cdclk = dev_priv->max_cdclk_freq;
9753 }
9754
9755 return cdclk;
9756}
9757
9758static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9759{
9760 struct drm_i915_private *dev_priv = to_i915(state->dev);
9761 struct drm_crtc *crtc;
9762 struct drm_crtc_state *crtc_state;
9763 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9764 int cdclk, i;
9765
9766 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9767
9768 if (cdclk == dev_priv->cdclk_freq)
9769 return 0;
9770
9771 /* add all active pipes to the state */
9772 for_each_crtc(state->dev, crtc) {
9773 if (!crtc->state->enable)
9774 continue;
9775
9776 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9777 if (IS_ERR(crtc_state))
9778 return PTR_ERR(crtc_state);
9779 }
9780
9781 /* disable/enable all currently active pipes while we change cdclk */
9782 for_each_crtc_in_state(state, crtc, crtc_state, i)
9783 if (crtc_state->enable)
9784 crtc_state->mode_changed = true;
9785
9786 return 0;
9787}
9788
9789static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9790{
9791 struct drm_device *dev = state->dev;
9792 struct drm_i915_private *dev_priv = dev->dev_private;
9793 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9794 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9795
9796 if (req_cdclk != dev_priv->cdclk_freq)
9797 broadwell_set_cdclk(dev, req_cdclk);
9798}
9799
190f68c5
ACO		 9800static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9801 struct intel_crtc_state *crtc_state)
09b4ddf9 9802{
190f68c5 9803 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9804 return -EINVAL;
716c2e55 9805
c7653199 9806 crtc->lowfreq_avail = false;
644cef34 9807
c8f7a0db 9808 return 0;
79e53945
JB		 9809}
9810
3760b59c
S		 9811static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9812 enum port port,
9813 struct intel_crtc_state *pipe_config)
9814{
9815 switch (port) {
9816 case PORT_A:
9817 pipe_config->ddi_pll_sel = SKL_DPLL0;
9818 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9819 break;
9820 case PORT_B:
9821 pipe_config->ddi_pll_sel = SKL_DPLL1;
9822 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9823 break;
9824 case PORT_C:
9825 pipe_config->ddi_pll_sel = SKL_DPLL2;
9826 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9827 break;
9828 default:
9829 DRM_ERROR("Incorrect port type\n");
9830 }
9831}
9832
96b7dfb7
S		 9833static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9834 enum port port,
5cec258b 9835 struct intel_crtc_state *pipe_config)
96b7dfb7 9836{
3148ade7 9837 u32 temp, dpll_ctl1;
96b7dfb7
S		 9838
9839 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9840 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9841
9842 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9843 case SKL_DPLL0:
9844 /*
9845 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9846 * of the shared DPLL framework and thus needs to be read out
9847 * separately
9848 */
9849 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9850 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9851 break;
96b7dfb7
S		 9852 case SKL_DPLL1:
9853 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9854 break;
9855 case SKL_DPLL2:
9856 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9857 break;
9858 case SKL_DPLL3:
9859 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9860 break;
96b7dfb7
S		 9861 }
9862}
9863
7d2c8175
DL		 9864static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9865 enum port port,
5cec258b 9866 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9867{
9868 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9869
9870 switch (pipe_config->ddi_pll_sel) {
9871 case PORT_CLK_SEL_WRPLL1:
9872 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9873 break;
9874 case PORT_CLK_SEL_WRPLL2:
9875 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9876 break;
9877 }
9878}
9879
26804afd 9880static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9881 struct intel_crtc_state *pipe_config)
26804afd
DV		 9882{
9883 struct drm_device *dev = crtc->base.dev;
9884 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9885 struct intel_shared_dpll *pll;
26804afd
DV		 9886 enum port port;
9887 uint32_t tmp;
9888
9889 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9890
9891 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9892
96b7dfb7
S		 9893 if (IS_SKYLAKE(dev))
9894 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9895 else if (IS_BROXTON(dev))
9896 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9897 else
9898 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9899
d452c5b6
DV		 9900 if (pipe_config->shared_dpll >= 0) {
9901 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9902
9903 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9904 &pipe_config->dpll_hw_state));
9905 }
9906
26804afd
DV		 9907 /*
9908 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9909 * DDI E. So just check whether this pipe is wired to DDI E and whether
9910 * the PCH transcoder is on.
9911 */
ca370455
DL		 9912 if (INTEL_INFO(dev)->gen < 9 &&
9913 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9914 pipe_config->has_pch_encoder = true;
9915
9916 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9917 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9918 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9919
9920 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9921 }
9922}
9923
0e8ffe1b 9924static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9925 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9926{
9927 struct drm_device *dev = crtc->base.dev;
9928 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9929 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9930 uint32_t tmp;
9931
f458ebbc 9932 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9933 POWER_DOMAIN_PIPE(crtc->pipe)))
9934 return false;
9935
e143a21c 9936 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9937 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9938
eccb140b
DV		 9939 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9940 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9941 enum pipe trans_edp_pipe;
9942 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9943 default:
9944 WARN(1, "unknown pipe linked to edp transcoder\n");
9945 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9946 case TRANS_DDI_EDP_INPUT_A_ON:
9947 trans_edp_pipe = PIPE_A;
9948 break;
9949 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9950 trans_edp_pipe = PIPE_B;
9951 break;
9952 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9953 trans_edp_pipe = PIPE_C;
9954 break;
9955 }
9956
9957 if (trans_edp_pipe == crtc->pipe)
9958 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9959 }
9960
f458ebbc 9961 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9962 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9963 return false;
9964
eccb140b 9965 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9966 if (!(tmp & PIPECONF_ENABLE))
9967 return false;
9968
26804afd 9969 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9970
1bd1bd80
DV		 9971 intel_get_pipe_timings(crtc, pipe_config);
9972
a1b2278e
CK		 9973 if (INTEL_INFO(dev)->gen >= 9) {
9974 skl_init_scalers(dev, crtc, pipe_config);
9975 }
9976
2fa2fe9a 9977 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9978
9979 if (INTEL_INFO(dev)->gen >= 9) {
9980 pipe_config->scaler_state.scaler_id = -1;
9981 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9982 }
9983
bd2e244f 9984 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9985 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9986 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9987 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9988 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9989 else
9990 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9991 }
88adfff1 9992
e59150dc
JB		 9993 if (IS_HASWELL(dev))
9994 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9995 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9996
ebb69c95
CT		 9997 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9998 pipe_config->pixel_multiplier =
9999 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10000 } else {
10001 pipe_config->pixel_multiplier = 1;
10002 }
6c49f241 10003
0e8ffe1b
DV		 10004 return true;
10005}
10006
560b85bb
CW		 10007static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
10008{
10009 struct drm_device *dev = crtc->dev;
10010 struct drm_i915_private *dev_priv = dev->dev_private;
10011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 10012 uint32_t cntl = 0, size = 0;
560b85bb 10013
dc41c154 10014 if (base) {
3dd512fb
MR		 10015 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10016 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 10017 unsigned int stride = roundup_pow_of_two(width) * 4;
10018
10019 switch (stride) {
10020 default:
10021 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10022 width, stride);
10023 stride = 256;
10024 /* fallthrough */
10025 case 256:
10026 case 512:
10027 case 1024:
10028 case 2048:
10029 break;
4b0e333e
CW		 10030 }
10031
dc41c154
VS		 10032 cntl |= CURSOR_ENABLE |
10033 CURSOR_GAMMA_ENABLE |
10034 CURSOR_FORMAT_ARGB |
10035 CURSOR_STRIDE(stride);
10036
10037 size = (height << 12) | width;
4b0e333e 10038 }
560b85bb 10039
dc41c154
VS		 10040 if (intel_crtc->cursor_cntl != 0 &&
10041 (intel_crtc->cursor_base != base ||
10042 intel_crtc->cursor_size != size ||
10043 intel_crtc->cursor_cntl != cntl)) {
10044 /* On these chipsets we can only modify the base/size/stride
10045 * whilst the cursor is disabled.
10046 */
10047 I915_WRITE(_CURACNTR, 0);
4b0e333e 10048 POSTING_READ(_CURACNTR);
dc41c154 10049 intel_crtc->cursor_cntl = 0;
4b0e333e 10050 }
560b85bb 10051
99d1f387 10052 if (intel_crtc->cursor_base != base) {
9db4a9c7 10053 I915_WRITE(_CURABASE, base);
99d1f387
VS		 10054 intel_crtc->cursor_base = base;
10055 }
4726e0b0 10056
dc41c154
VS		 10057 if (intel_crtc->cursor_size != size) {
10058 I915_WRITE(CURSIZE, size);
10059 intel_crtc->cursor_size = size;
4b0e333e 10060 }
560b85bb 10061
4b0e333e 10062 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 10063 I915_WRITE(_CURACNTR, cntl);
10064 POSTING_READ(_CURACNTR);
4b0e333e 10065 intel_crtc->cursor_cntl = cntl;
560b85bb 10066 }
560b85bb
CW		 10067}
10068
560b85bb 10069static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 10070{
10071 struct drm_device *dev = crtc->dev;
10072 struct drm_i915_private *dev_priv = dev->dev_private;
10073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10074 int pipe = intel_crtc->pipe;
4b0e333e
CW		 10075 uint32_t cntl;
10076
10077 cntl = 0;
10078 if (base) {
10079 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10080 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10081 case 64:
10082 cntl |= CURSOR_MODE_64_ARGB_AX;
10083 break;
10084 case 128:
10085 cntl |= CURSOR_MODE_128_ARGB_AX;
10086 break;
10087 case 256:
10088 cntl |= CURSOR_MODE_256_ARGB_AX;
10089 break;
10090 default:
3dd512fb 10091 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10092 return;
65a21cd6 10093 }
4b0e333e 10094 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10095
10096 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10097 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10098 }
65a21cd6 10099
8e7d688b 10100 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10101 cntl |= CURSOR_ROTATE_180;
10102
4b0e333e
CW		 10103 if (intel_crtc->cursor_cntl != cntl) {
10104 I915_WRITE(CURCNTR(pipe), cntl);
10105 POSTING_READ(CURCNTR(pipe));
10106 intel_crtc->cursor_cntl = cntl;
65a21cd6 10107 }
4b0e333e 10108
65a21cd6 10109 /* and commit changes on next vblank */
5efb3e28
VS		 10110 I915_WRITE(CURBASE(pipe), base);
10111 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10112
10113 intel_crtc->cursor_base = base;
65a21cd6
JB		 10114}
10115
cda4b7d3 10116/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10117static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10118 bool on)
cda4b7d3
CW		 10119{
10120 struct drm_device *dev = crtc->dev;
10121 struct drm_i915_private *dev_priv = dev->dev_private;
10122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10123 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10124 int x = crtc->cursor_x;
10125 int y = crtc->cursor_y;
d6e4db15 10126 u32 base = 0, pos = 0;
cda4b7d3 10127
d6e4db15 10128 if (on)
cda4b7d3 10129 base = intel_crtc->cursor_addr;
cda4b7d3 10130
6e3c9717 10131 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10132 base = 0;
10133
6e3c9717 10134 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10135 base = 0;
10136
10137 if (x < 0) {
3dd512fb 10138 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10139 base = 0;
10140
10141 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10142 x = -x;
10143 }
10144 pos |= x << CURSOR_X_SHIFT;
10145
10146 if (y < 0) {
3dd512fb 10147 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10148 base = 0;
10149
10150 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10151 y = -y;
10152 }
10153 pos |= y << CURSOR_Y_SHIFT;
10154
4b0e333e 10155 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10156 return;
10157
5efb3e28
VS		 10158 I915_WRITE(CURPOS(pipe), pos);
10159
4398ad45
VS		 10160 /* ILK+ do this automagically */
10161 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10162 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10163 base += (intel_crtc->base.cursor->state->crtc_h *
10164 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10165 }
10166
8ac54669 10167 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10168 i845_update_cursor(crtc, base);
10169 else
10170 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10171}
10172
dc41c154
VS		 10173static bool cursor_size_ok(struct drm_device *dev,
10174 uint32_t width, uint32_t height)
10175{
10176 if (width == 0 || height == 0)
10177 return false;
10178
10179 /*
10180 * 845g/865g are special in that they are only limited by
10181 * the width of their cursors, the height is arbitrary up to
10182 * the precision of the register. Everything else requires
10183 * square cursors, limited to a few power-of-two sizes.
10184 */
10185 if (IS_845G(dev) || IS_I865G(dev)) {
10186 if ((width & 63) != 0)
10187 return false;
10188
10189 if (width > (IS_845G(dev) ? 64 : 512))
10190 return false;
10191
10192 if (height > 1023)
10193 return false;
10194 } else {
10195 switch (width | height) {
10196 case 256:
10197 case 128:
10198 if (IS_GEN2(dev))
10199 return false;
10200 case 64:
10201 break;
10202 default:
10203 return false;
10204 }
10205 }
10206
10207 return true;
10208}
10209
79e53945 10210static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10211 u16 *blue, uint32_t start, uint32_t size)
79e53945 10212{
7203425a 10213 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10215
7203425a 10216 for (i = start; i < end; i++) {
79e53945
JB		 10217 intel_crtc->lut_r[i] = red[i] >> 8;
10218 intel_crtc->lut_g[i] = green[i] >> 8;
10219 intel_crtc->lut_b[i] = blue[i] >> 8;
10220 }
10221
10222 intel_crtc_load_lut(crtc);
10223}
10224
79e53945
JB		 10225/* VESA 640x480x72Hz mode to set on the pipe */
10226static struct drm_display_mode load_detect_mode = {
10227 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10228 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10229};
10230
a8bb6818
DV		 10231struct drm_framebuffer *
10232__intel_framebuffer_create(struct drm_device *dev,
10233 struct drm_mode_fb_cmd2 *mode_cmd,
10234 struct drm_i915_gem_object *obj)
d2dff872
CW		 10235{
10236 struct intel_framebuffer *intel_fb;
10237 int ret;
10238
10239 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10240 if (!intel_fb) {
6ccb81f2 10241 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10242 return ERR_PTR(-ENOMEM);
10243 }
10244
10245 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10246 if (ret)
10247 goto err;
d2dff872
CW		 10248
10249 return &intel_fb->base;
dd4916c5 10250err:
6ccb81f2 10251 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10252 kfree(intel_fb);
10253
10254 return ERR_PTR(ret);
d2dff872
CW		 10255}
10256
b5ea642a 10257static struct drm_framebuffer *
a8bb6818
DV		 10258intel_framebuffer_create(struct drm_device *dev,
10259 struct drm_mode_fb_cmd2 *mode_cmd,
10260 struct drm_i915_gem_object *obj)
10261{
10262 struct drm_framebuffer *fb;
10263 int ret;
10264
10265 ret = i915_mutex_lock_interruptible(dev);
10266 if (ret)
10267 return ERR_PTR(ret);
10268 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10269 mutex_unlock(&dev->struct_mutex);
10270
10271 return fb;
10272}
10273
d2dff872
CW		 10274static u32
10275intel_framebuffer_pitch_for_width(int width, int bpp)
10276{
10277 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10278 return ALIGN(pitch, 64);
10279}
10280
10281static u32
10282intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10283{
10284 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10285 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10286}
10287
10288static struct drm_framebuffer *
10289intel_framebuffer_create_for_mode(struct drm_device *dev,
10290 struct drm_display_mode *mode,
10291 int depth, int bpp)
10292{
10293 struct drm_i915_gem_object *obj;
0fed39bd 10294 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10295
10296 obj = i915_gem_alloc_object(dev,
10297 intel_framebuffer_size_for_mode(mode, bpp));
10298 if (obj == NULL)
10299 return ERR_PTR(-ENOMEM);
10300
10301 mode_cmd.width = mode->hdisplay;
10302 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10303 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10304 bpp);
5ca0c34a 10305 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10306
10307 return intel_framebuffer_create(dev, &mode_cmd, obj);
10308}
10309
10310static struct drm_framebuffer *
10311mode_fits_in_fbdev(struct drm_device *dev,
10312 struct drm_display_mode *mode)
10313{
4520f53a 10314#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10315 struct drm_i915_private *dev_priv = dev->dev_private;
10316 struct drm_i915_gem_object *obj;
10317 struct drm_framebuffer *fb;
10318
4c0e5528 10319 if (!dev_priv->fbdev)
d2dff872
CW		 10320 return NULL;
10321
4c0e5528 10322 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10323 return NULL;
10324
4c0e5528
DV		 10325 obj = dev_priv->fbdev->fb->obj;
10326 BUG_ON(!obj);
10327
8bcd4553 10328 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10329 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10330 fb->bits_per_pixel))
d2dff872
CW		 10331 return NULL;
10332
01f2c773 10333 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10334 return NULL;
10335
10336 return fb;
4520f53a
DV		 10337#else
10338 return NULL;
10339#endif
d2dff872
CW		 10340}
10341
d3a40d1b
ACO		 10342static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10343 struct drm_crtc *crtc,
10344 struct drm_display_mode *mode,
10345 struct drm_framebuffer *fb,
10346 int x, int y)
10347{
10348 struct drm_plane_state *plane_state;
10349 int hdisplay, vdisplay;
10350 int ret;
10351
10352 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10353 if (IS_ERR(plane_state))
10354 return PTR_ERR(plane_state);
10355
10356 if (mode)
10357 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10358 else
10359 hdisplay = vdisplay = 0;
10360
10361 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10362 if (ret)
10363 return ret;
10364 drm_atomic_set_fb_for_plane(plane_state, fb);
10365 plane_state->crtc_x = 0;
10366 plane_state->crtc_y = 0;
10367 plane_state->crtc_w = hdisplay;
10368 plane_state->crtc_h = vdisplay;
10369 plane_state->src_x = x << 16;
10370 plane_state->src_y = y << 16;
10371 plane_state->src_w = hdisplay << 16;
10372 plane_state->src_h = vdisplay << 16;
10373
10374 return 0;
10375}
10376
d2434ab7 10377bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10378 struct drm_display_mode *mode,
51fd371b
RC		 10379 struct intel_load_detect_pipe *old,
10380 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10381{
10382 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10383 struct intel_encoder *intel_encoder =
10384 intel_attached_encoder(connector);
79e53945 10385 struct drm_crtc *possible_crtc;
4ef69c7a 10386 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10387 struct drm_crtc *crtc = NULL;
10388 struct drm_device *dev = encoder->dev;
94352cf9 10389 struct drm_framebuffer *fb;
51fd371b 10390 struct drm_mode_config *config = &dev->mode_config;
83a57153 10391 struct drm_atomic_state *state = NULL;
944b0c76 10392 struct drm_connector_state *connector_state;
4be07317 10393 struct intel_crtc_state *crtc_state;
51fd371b 10394 int ret, i = -1;
79e53945 10395
d2dff872 10396 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10397 connector->base.id, connector->name,
8e329a03 10398 encoder->base.id, encoder->name);
d2dff872 10399
51fd371b
RC		 10400retry:
10401 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10402 if (ret)
10403 goto fail_unlock;
6e9f798d 10404
79e53945
JB		 10405 /*
10406 * Algorithm gets a little messy:
7a5e4805 10407 *
79e53945
JB		 10408 * - if the connector already has an assigned crtc, use it (but make
10409 * sure it's on first)
7a5e4805 10410 *
79e53945
JB		 10411 * - try to find the first unused crtc that can drive this connector,
10412 * and use that if we find one
79e53945
JB		 10413 */
10414
10415 /* See if we already have a CRTC for this connector */
10416 if (encoder->crtc) {
10417 crtc = encoder->crtc;
8261b191 10418
51fd371b 10419 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10420 if (ret)
10421 goto fail_unlock;
10422 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10423 if (ret)
10424 goto fail_unlock;
7b24056b 10425
24218aac 10426 old->dpms_mode = connector->dpms;
8261b191
CW		 10427 old->load_detect_temp = false;
10428
10429 /* Make sure the crtc and connector are running */
24218aac
DV		 10430 if (connector->dpms != DRM_MODE_DPMS_ON)
10431 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10432
7173188d 10433 return true;
79e53945
JB		 10434 }
10435
10436 /* Find an unused one (if possible) */
70e1e0ec 10437 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10438 i++;
10439 if (!(encoder->possible_crtcs & (1 << i)))
10440 continue;
83d65738 10441 if (possible_crtc->state->enable)
a459249c
VS		 10442 continue;
10443 /* This can occur when applying the pipe A quirk on resume. */
10444 if (to_intel_crtc(possible_crtc)->new_enabled)
10445 continue;
10446
10447 crtc = possible_crtc;
10448 break;
79e53945
JB		 10449 }
10450
10451 /*
10452 * If we didn't find an unused CRTC, don't use any.
10453 */
10454 if (!crtc) {
7173188d 10455 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10456 goto fail_unlock;
79e53945
JB		 10457 }
10458
51fd371b
RC		 10459 ret = drm_modeset_lock(&crtc->mutex, ctx);
10460 if (ret)
4d02e2de
DV		 10461 goto fail_unlock;
10462 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10463 if (ret)
51fd371b 10464 goto fail_unlock;
fc303101
DV		 10465 intel_encoder->new_crtc = to_intel_crtc(crtc);
10466 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10467
10468 intel_crtc = to_intel_crtc(crtc);
412b61d8 10469 intel_crtc->new_enabled = true;
24218aac 10470 old->dpms_mode = connector->dpms;
8261b191 10471 old->load_detect_temp = true;
d2dff872 10472 old->release_fb = NULL;
79e53945 10473
83a57153
ACO		 10474 state = drm_atomic_state_alloc(dev);
10475 if (!state)
10476 return false;
10477
10478 state->acquire_ctx = ctx;
10479
944b0c76
ACO		 10480 connector_state = drm_atomic_get_connector_state(state, connector);
10481 if (IS_ERR(connector_state)) {
10482 ret = PTR_ERR(connector_state);
10483 goto fail;
10484 }
10485
10486 connector_state->crtc = crtc;
10487 connector_state->best_encoder = &intel_encoder->base;
10488
4be07317
ACO		 10489 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10490 if (IS_ERR(crtc_state)) {
10491 ret = PTR_ERR(crtc_state);
10492 goto fail;
10493 }
10494
49d6fa21 10495 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10496
6492711d
CW		 10497 if (!mode)
10498 mode = &load_detect_mode;
79e53945 10499
d2dff872
CW		 10500 /* We need a framebuffer large enough to accommodate all accesses
10501 * that the plane may generate whilst we perform load detection.
10502 * We can not rely on the fbcon either being present (we get called
10503 * during its initialisation to detect all boot displays, or it may
10504 * not even exist) or that it is large enough to satisfy the
10505 * requested mode.
10506 */
94352cf9
DV		 10507 fb = mode_fits_in_fbdev(dev, mode);
10508 if (fb == NULL) {
d2dff872 10509 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10510 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10511 old->release_fb = fb;
d2dff872
CW		 10512 } else
10513 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10514 if (IS_ERR(fb)) {
d2dff872 10515 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10516 goto fail;
79e53945 10517 }
79e53945 10518
d3a40d1b
ACO		 10519 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10520 if (ret)
10521 goto fail;
10522
8c7b5ccb
ACO		 10523 drm_mode_copy(&crtc_state->base.mode, mode);
10524
10525 if (intel_set_mode(crtc, state)) {
6492711d 10526 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10527 if (old->release_fb)
10528 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10529 goto fail;
79e53945 10530 }
9128b040 10531 crtc->primary->crtc = crtc;
7173188d 10532
79e53945 10533 /* let the connector get through one full cycle before testing */
9d0498a2 10534 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10535 return true;
412b61d8
VS		 10536
10537 fail:
83d65738 10538 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10539fail_unlock:
e5d958ef
ACO		 10540 drm_atomic_state_free(state);
10541 state = NULL;
83a57153 10542
51fd371b
RC		 10543 if (ret == -EDEADLK) {
10544 drm_modeset_backoff(ctx);
10545 goto retry;
10546 }
10547
412b61d8 10548 return false;
79e53945
JB		 10549}
10550
d2434ab7 10551void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10552 struct intel_load_detect_pipe *old,
10553 struct drm_modeset_acquire_ctx *ctx)
79e53945 10554{
83a57153 10555 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10556 struct intel_encoder *intel_encoder =
10557 intel_attached_encoder(connector);
4ef69c7a 10558 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10559 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10561 struct drm_atomic_state *state;
944b0c76 10562 struct drm_connector_state *connector_state;
4be07317 10563 struct intel_crtc_state *crtc_state;
d3a40d1b 10564 int ret;
79e53945 10565
d2dff872 10566 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10567 connector->base.id, connector->name,
8e329a03 10568 encoder->base.id, encoder->name);
d2dff872 10569
8261b191 10570 if (old->load_detect_temp) {
83a57153 10571 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10572 if (!state)
10573 goto fail;
83a57153
ACO		 10574
10575 state->acquire_ctx = ctx;
10576
944b0c76
ACO		 10577 connector_state = drm_atomic_get_connector_state(state, connector);
10578 if (IS_ERR(connector_state))
10579 goto fail;
10580
4be07317
ACO		 10581 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10582 if (IS_ERR(crtc_state))
10583 goto fail;
10584
fc303101
DV		 10585 to_intel_connector(connector)->new_encoder = NULL;
10586 intel_encoder->new_crtc = NULL;
412b61d8 10587 intel_crtc->new_enabled = false;
944b0c76
ACO		 10588
10589 connector_state->best_encoder = NULL;
10590 connector_state->crtc = NULL;
10591
49d6fa21 10592 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10593
d3a40d1b
ACO		 10594 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10595 0, 0);
10596 if (ret)
10597 goto fail;
10598
2bfb4627
ACO		 10599 ret = intel_set_mode(crtc, state);
10600 if (ret)
10601 goto fail;
d2dff872 10602
36206361
DV		 10603 if (old->release_fb) {
10604 drm_framebuffer_unregister_private(old->release_fb);
10605 drm_framebuffer_unreference(old->release_fb);
10606 }
d2dff872 10607
0622a53c 10608 return;
79e53945
JB		 10609 }
10610
c751ce4f 10611 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10612 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10613 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10614
10615 return;
10616fail:
10617 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10618 drm_atomic_state_free(state);
79e53945
JB		 10619}
10620
da4a1efa 10621static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10622 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10623{
10624 struct drm_i915_private *dev_priv = dev->dev_private;
10625 u32 dpll = pipe_config->dpll_hw_state.dpll;
10626
10627 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10628 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10629 else if (HAS_PCH_SPLIT(dev))
10630 return 120000;
10631 else if (!IS_GEN2(dev))
10632 return 96000;
10633 else
10634 return 48000;
10635}
10636
79e53945 10637/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10638static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10639 struct intel_crtc_state *pipe_config)
79e53945 10640{
f1f644dc 10641 struct drm_device *dev = crtc->base.dev;
79e53945 10642 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10643 int pipe = pipe_config->cpu_transcoder;
293623f7 10644 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10645 u32 fp;
10646 intel_clock_t clock;
da4a1efa 10647 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10648
10649 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10650 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10651 else
293623f7 10652 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10653
10654 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10655 if (IS_PINEVIEW(dev)) {
10656 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10657 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10658 } else {
10659 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10660 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10661 }
10662
a6c45cf0 10663 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10664 if (IS_PINEVIEW(dev))
10665 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10666 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10667 else
10668 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10669 DPLL_FPA01_P1_POST_DIV_SHIFT);
10670
10671 switch (dpll & DPLL_MODE_MASK) {
10672 case DPLLB_MODE_DAC_SERIAL:
10673 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10674 5 : 10;
10675 break;
10676 case DPLLB_MODE_LVDS:
10677 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10678 7 : 14;
10679 break;
10680 default:
28c97730 10681 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10682 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10683 return;
79e53945
JB		 10684 }
10685
ac58c3f0 10686 if (IS_PINEVIEW(dev))
da4a1efa 10687 pineview_clock(refclk, &clock);
ac58c3f0 10688 else
da4a1efa 10689 i9xx_clock(refclk, &clock);
79e53945 10690 } else {
0fb58223 10691 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10692 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10693
10694 if (is_lvds) {
10695 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10696 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10697
10698 if (lvds & LVDS_CLKB_POWER_UP)
10699 clock.p2 = 7;
10700 else
10701 clock.p2 = 14;
79e53945
JB		 10702 } else {
10703 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10704 clock.p1 = 2;
10705 else {
10706 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10707 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10708 }
10709 if (dpll & PLL_P2_DIVIDE_BY_4)
10710 clock.p2 = 4;
10711 else
10712 clock.p2 = 2;
79e53945 10713 }
da4a1efa
VS		 10714
10715 i9xx_clock(refclk, &clock);
79e53945
JB		 10716 }
10717
18442d08
VS		 10718 /*
10719 * This value includes pixel_multiplier. We will use
241bfc38 10720 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10721 * encoder's get_config() function.
10722 */
10723 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10724}
10725
6878da05
VS		 10726int intel_dotclock_calculate(int link_freq,
10727 const struct intel_link_m_n *m_n)
f1f644dc 10728{
f1f644dc
JB		 10729 /*
10730 * The calculation for the data clock is:
1041a02f 10731 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10732 * But we want to avoid losing precison if possible, so:
1041a02f 10733 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10734 *
10735 * and the link clock is simpler:
1041a02f 10736 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10737 */
10738
6878da05
VS		 10739 if (!m_n->link_n)
10740 return 0;
f1f644dc 10741
6878da05
VS		 10742 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10743}
f1f644dc 10744
18442d08 10745static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10746 struct intel_crtc_state *pipe_config)
6878da05
VS		 10747{
10748 struct drm_device *dev = crtc->base.dev;
79e53945 10749
18442d08
VS		 10750 /* read out port_clock from the DPLL */
10751 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10752
f1f644dc 10753 /*
18442d08 10754 * This value does not include pixel_multiplier.
241bfc38 10755 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10756 * agree once we know their relationship in the encoder's
10757 * get_config() function.
79e53945 10758 */
2d112de7 10759 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10760 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10761 &pipe_config->fdi_m_n);
79e53945
JB		 10762}
10763
10764/** Returns the currently programmed mode of the given pipe. */
10765struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10766 struct drm_crtc *crtc)
10767{
548f245b 10768 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10770 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10771 struct drm_display_mode *mode;
5cec258b 10772 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10773 int htot = I915_READ(HTOTAL(cpu_transcoder));
10774 int hsync = I915_READ(HSYNC(cpu_transcoder));
10775 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10776 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10777 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10778
10779 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10780 if (!mode)
10781 return NULL;
10782
f1f644dc
JB		 10783 /*
10784 * Construct a pipe_config sufficient for getting the clock info
10785 * back out of crtc_clock_get.
10786 *
10787 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10788 * to use a real value here instead.
10789 */
293623f7 10790 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10791 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10792 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10793 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10794 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10795 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10796
773ae034 10797 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10798 mode->hdisplay = (htot & 0xffff) + 1;
10799 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10800 mode->hsync_start = (hsync & 0xffff) + 1;
10801 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10802 mode->vdisplay = (vtot & 0xffff) + 1;
10803 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10804 mode->vsync_start = (vsync & 0xffff) + 1;
10805 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10806
10807 drm_mode_set_name(mode);
79e53945
JB		 10808
10809 return mode;
10810}
10811
652c393a
JB		 10812static void intel_decrease_pllclock(struct drm_crtc *crtc)
10813{
10814 struct drm_device *dev = crtc->dev;
fbee40df 10815 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10817
baff296c 10818 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10819 return;
10820
10821 if (!dev_priv->lvds_downclock_avail)
10822 return;
10823
10824 /*
10825 * Since this is called by a timer, we should never get here in
10826 * the manual case.
10827 */
10828 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10829 int pipe = intel_crtc->pipe;
10830 int dpll_reg = DPLL(pipe);
10831 int dpll;
f6e5b160 10832
44d98a61 10833 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10834
8ac5a6d5 10835 assert_panel_unlocked(dev_priv, pipe);
652c393a 10836
dc257cf1 10837 dpll = I915_READ(dpll_reg);
652c393a
JB		 10838 dpll |= DISPLAY_RATE_SELECT_FPA1;
10839 I915_WRITE(dpll_reg, dpll);
9d0498a2 10840 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10841 dpll = I915_READ(dpll_reg);
10842 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10843 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10844 }
10845
10846}
10847
f047e395
CW		 10848void intel_mark_busy(struct drm_device *dev)
10849{
c67a470b
PZ		 10850 struct drm_i915_private *dev_priv = dev->dev_private;
10851
f62a0076
CW		 10852 if (dev_priv->mm.busy)
10853 return;
10854
43694d69 10855 intel_runtime_pm_get(dev_priv);
c67a470b 10856 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10857 if (INTEL_INFO(dev)->gen >= 6)
10858 gen6_rps_busy(dev_priv);
f62a0076 10859 dev_priv->mm.busy = true;
f047e395
CW		 10860}
10861
10862void intel_mark_idle(struct drm_device *dev)
652c393a 10863{
c67a470b 10864 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10865 struct drm_crtc *crtc;
652c393a 10866
f62a0076
CW		 10867 if (!dev_priv->mm.busy)
10868 return;
10869
10870 dev_priv->mm.busy = false;
10871
70e1e0ec 10872 for_each_crtc(dev, crtc) {
f4510a27 10873 if (!crtc->primary->fb)
652c393a
JB		 10874 continue;
10875
725a5b54 10876 intel_decrease_pllclock(crtc);
652c393a 10877 }
b29c19b6 10878
3d13ef2e 10879 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10880 gen6_rps_idle(dev->dev_private);
bb4cdd53 10881
43694d69 10882 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10883}
10884
79e53945
JB		 10885static void intel_crtc_destroy(struct drm_crtc *crtc)
10886{
10887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10888 struct drm_device *dev = crtc->dev;
10889 struct intel_unpin_work *work;
67e77c5a 10890
5e2d7afc 10891 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10892 work = intel_crtc->unpin_work;
10893 intel_crtc->unpin_work = NULL;
5e2d7afc 10894 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10895
10896 if (work) {
10897 cancel_work_sync(&work->work);
10898 kfree(work);
10899 }
79e53945
JB		 10900
10901 drm_crtc_cleanup(crtc);
67e77c5a 10902
79e53945
JB		 10903 kfree(intel_crtc);
10904}
10905
6b95a207
KH		 10906static void intel_unpin_work_fn(struct work_struct *__work)
10907{
10908 struct intel_unpin_work *work =
10909 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10910 struct drm_device *dev = work->crtc->dev;
f99d7069 10911 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10912
b4a98e57 10913 mutex_lock(&dev->struct_mutex);
82bc3b2d 10914 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10915 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10916
7ff0ebcc 10917 intel_fbc_update(dev);
f06cc1b9
JH		 10918
10919 if (work->flip_queued_req)
146d84f0 10920 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10921 mutex_unlock(&dev->struct_mutex);
10922
f99d7069 10923 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10924 drm_framebuffer_unreference(work->old_fb);
f99d7069 10925
b4a98e57
CW		 10926 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10927 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10928
6b95a207
KH		 10929 kfree(work);
10930}
10931
1afe3e9d 10932static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10933 struct drm_crtc *crtc)
6b95a207 10934{
6b95a207
KH		 10935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10936 struct intel_unpin_work *work;
6b95a207
KH		 10937 unsigned long flags;
10938
10939 /* Ignore early vblank irqs */
10940 if (intel_crtc == NULL)
10941 return;
10942
f326038a
DV		 10943 /*
10944 * This is called both by irq handlers and the reset code (to complete
10945 * lost pageflips) so needs the full irqsave spinlocks.
10946 */
6b95a207
KH		 10947 spin_lock_irqsave(&dev->event_lock, flags);
10948 work = intel_crtc->unpin_work;
e7d841ca
CW		 10949
10950 /* Ensure we don't miss a work->pending update ... */
10951 smp_rmb();
10952
10953 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10954 spin_unlock_irqrestore(&dev->event_lock, flags);
10955 return;
10956 }
10957
d6bbafa1 10958 page_flip_completed(intel_crtc);
0af7e4df 10959
6b95a207 10960 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10961}
10962
1afe3e9d
JB		 10963void intel_finish_page_flip(struct drm_device *dev, int pipe)
10964{
fbee40df 10965 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10966 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10967
49b14a5c 10968 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10969}
10970
10971void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10972{
fbee40df 10973 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10974 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10975
49b14a5c 10976 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10977}
10978
75f7f3ec
VS		 10979/* Is 'a' after or equal to 'b'? */
10980static bool g4x_flip_count_after_eq(u32 a, u32 b)
10981{
10982 return !((a - b) & 0x80000000);
10983}
10984
10985static bool page_flip_finished(struct intel_crtc *crtc)
10986{
10987 struct drm_device *dev = crtc->base.dev;
10988 struct drm_i915_private *dev_priv = dev->dev_private;
10989
bdfa7542
VS		 10990 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10991 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10992 return true;
10993
75f7f3ec
VS		 10994 /*
10995 * The relevant registers doen't exist on pre-ctg.
10996 * As the flip done interrupt doesn't trigger for mmio
10997 * flips on gmch platforms, a flip count check isn't
10998 * really needed there. But since ctg has the registers,
10999 * include it in the check anyway.
11000 */
11001 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11002 return true;
11003
11004 /*
11005 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11006 * used the same base address. In that case the mmio flip might
11007 * have completed, but the CS hasn't even executed the flip yet.
11008 *
11009 * A flip count check isn't enough as the CS might have updated
11010 * the base address just after start of vblank, but before we
11011 * managed to process the interrupt. This means we'd complete the
11012 * CS flip too soon.
11013 *
11014 * Combining both checks should get us a good enough result. It may
11015 * still happen that the CS flip has been executed, but has not
11016 * yet actually completed. But in case the base address is the same
11017 * anyway, we don't really care.
11018 */
11019 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11020 crtc->unpin_work->gtt_offset &&
11021 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
11022 crtc->unpin_work->flip_count);
11023}
11024
6b95a207
KH		 11025void intel_prepare_page_flip(struct drm_device *dev, int plane)
11026{
fbee40df 11027 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 11028 struct intel_crtc *intel_crtc =
11029 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11030 unsigned long flags;
11031
f326038a
DV		 11032
11033 /*
11034 * This is called both by irq handlers and the reset code (to complete
11035 * lost pageflips) so needs the full irqsave spinlocks.
11036 *
11037 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 11038 * generate a page-flip completion irq, i.e. every modeset
11039 * is also accompanied by a spurious intel_prepare_page_flip().
11040 */
6b95a207 11041 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 11042 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 11043 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 11044 spin_unlock_irqrestore(&dev->event_lock, flags);
11045}
11046
eba905b2 11047static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 11048{
11049 /* Ensure that the work item is consistent when activating it ... */
11050 smp_wmb();
11051 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11052 /* and that it is marked active as soon as the irq could fire. */
11053 smp_wmb();
11054}
11055
8c9f3aaf
JB		 11056static int intel_gen2_queue_flip(struct drm_device *dev,
11057 struct drm_crtc *crtc,
11058 struct drm_framebuffer *fb,
ed8d1975 11059 struct drm_i915_gem_object *obj,
a4872ba6 11060 struct intel_engine_cs *ring,
ed8d1975 11061 uint32_t flags)
8c9f3aaf 11062{
8c9f3aaf 11063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11064 u32 flip_mask;
11065 int ret;
11066
6d90c952 11067 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11068 if (ret)
4fa62c89 11069 return ret;
8c9f3aaf
JB		 11070
11071 /* Can't queue multiple flips, so wait for the previous
11072 * one to finish before executing the next.
11073 */
11074 if (intel_crtc->plane)
11075 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11076 else
11077 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11078 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11079 intel_ring_emit(ring, MI_NOOP);
11080 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11081 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11082 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11083 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11084 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11085
11086 intel_mark_page_flip_active(intel_crtc);
09246732 11087 __intel_ring_advance(ring);
83d4092b 11088 return 0;
8c9f3aaf
JB		 11089}
11090
11091static int intel_gen3_queue_flip(struct drm_device *dev,
11092 struct drm_crtc *crtc,
11093 struct drm_framebuffer *fb,
ed8d1975 11094 struct drm_i915_gem_object *obj,
a4872ba6 11095 struct intel_engine_cs *ring,
ed8d1975 11096 uint32_t flags)
8c9f3aaf 11097{
8c9f3aaf 11098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11099 u32 flip_mask;
11100 int ret;
11101
6d90c952 11102 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11103 if (ret)
4fa62c89 11104 return ret;
8c9f3aaf
JB		 11105
11106 if (intel_crtc->plane)
11107 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11108 else
11109 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11110 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11111 intel_ring_emit(ring, MI_NOOP);
11112 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11113 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11114 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11115 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11116 intel_ring_emit(ring, MI_NOOP);
11117
e7d841ca 11118 intel_mark_page_flip_active(intel_crtc);
09246732 11119 __intel_ring_advance(ring);
83d4092b 11120 return 0;
8c9f3aaf
JB		 11121}
11122
11123static int intel_gen4_queue_flip(struct drm_device *dev,
11124 struct drm_crtc *crtc,
11125 struct drm_framebuffer *fb,
ed8d1975 11126 struct drm_i915_gem_object *obj,
a4872ba6 11127 struct intel_engine_cs *ring,
ed8d1975 11128 uint32_t flags)
8c9f3aaf
JB		 11129{
11130 struct drm_i915_private *dev_priv = dev->dev_private;
11131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11132 uint32_t pf, pipesrc;
11133 int ret;
11134
6d90c952 11135 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11136 if (ret)
4fa62c89 11137 return ret;
8c9f3aaf
JB		 11138
11139 /* i965+ uses the linear or tiled offsets from the
11140 * Display Registers (which do not change across a page-flip)
11141 * so we need only reprogram the base address.
11142 */
6d90c952
DV		 11143 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11144 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11145 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11146 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11147 obj->tiling_mode);
8c9f3aaf
JB		 11148
11149 /* XXX Enabling the panel-fitter across page-flip is so far
11150 * untested on non-native modes, so ignore it for now.
11151 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11152 */
11153 pf = 0;
11154 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11155 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11156
11157 intel_mark_page_flip_active(intel_crtc);
09246732 11158 __intel_ring_advance(ring);
83d4092b 11159 return 0;
8c9f3aaf
JB		 11160}
11161
11162static int intel_gen6_queue_flip(struct drm_device *dev,
11163 struct drm_crtc *crtc,
11164 struct drm_framebuffer *fb,
ed8d1975 11165 struct drm_i915_gem_object *obj,
a4872ba6 11166 struct intel_engine_cs *ring,
ed8d1975 11167 uint32_t flags)
8c9f3aaf
JB		 11168{
11169 struct drm_i915_private *dev_priv = dev->dev_private;
11170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11171 uint32_t pf, pipesrc;
11172 int ret;
11173
6d90c952 11174 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11175 if (ret)
4fa62c89 11176 return ret;
8c9f3aaf 11177
6d90c952
DV		 11178 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11179 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11180 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11181 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11182
dc257cf1
DV		 11183 /* Contrary to the suggestions in the documentation,
11184 * "Enable Panel Fitter" does not seem to be required when page
11185 * flipping with a non-native mode, and worse causes a normal
11186 * modeset to fail.
11187 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11188 */
11189 pf = 0;
8c9f3aaf 11190 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11191 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11192
11193 intel_mark_page_flip_active(intel_crtc);
09246732 11194 __intel_ring_advance(ring);
83d4092b 11195 return 0;
8c9f3aaf
JB		 11196}
11197
7c9017e5
JB		 11198static int intel_gen7_queue_flip(struct drm_device *dev,
11199 struct drm_crtc *crtc,
11200 struct drm_framebuffer *fb,
ed8d1975 11201 struct drm_i915_gem_object *obj,
a4872ba6 11202 struct intel_engine_cs *ring,
ed8d1975 11203 uint32_t flags)
7c9017e5 11204{
7c9017e5 11205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11206 uint32_t plane_bit = 0;
ffe74d75
CW		 11207 int len, ret;
11208
eba905b2 11209 switch (intel_crtc->plane) {
cb05d8de
DV		 11210 case PLANE_A:
11211 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11212 break;
11213 case PLANE_B:
11214 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11215 break;
11216 case PLANE_C:
11217 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11218 break;
11219 default:
11220 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11221 return -ENODEV;
cb05d8de
DV		 11222 }
11223
ffe74d75 11224 len = 4;
f476828a 11225 if (ring->id == RCS) {
ffe74d75 11226 len += 6;
f476828a
DL		 11227 /*
11228 * On Gen 8, SRM is now taking an extra dword to accommodate
11229 * 48bits addresses, and we need a NOOP for the batch size to
11230 * stay even.
11231 */
11232 if (IS_GEN8(dev))
11233 len += 2;
11234 }
ffe74d75 11235
f66fab8e
VS		 11236 /*
11237 * BSpec MI_DISPLAY_FLIP for IVB:
11238 * "The full packet must be contained within the same cache line."
11239 *
11240 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11241 * cacheline, if we ever start emitting more commands before
11242 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11243 * then do the cacheline alignment, and finally emit the
11244 * MI_DISPLAY_FLIP.
11245 */
11246 ret = intel_ring_cacheline_align(ring);
11247 if (ret)
4fa62c89 11248 return ret;
f66fab8e 11249
ffe74d75 11250 ret = intel_ring_begin(ring, len);
7c9017e5 11251 if (ret)
4fa62c89 11252 return ret;
7c9017e5 11253
ffe74d75
CW		 11254 /* Unmask the flip-done completion message. Note that the bspec says that
11255 * we should do this for both the BCS and RCS, and that we must not unmask
11256 * more than one flip event at any time (or ensure that one flip message
11257 * can be sent by waiting for flip-done prior to queueing new flips).
11258 * Experimentation says that BCS works despite DERRMR masking all
11259 * flip-done completion events and that unmasking all planes at once
11260 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11261 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11262 */
11263 if (ring->id == RCS) {
11264 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11265 intel_ring_emit(ring, DERRMR);
11266 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11267 DERRMR_PIPEB_PRI_FLIP_DONE |
11268 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11269 if (IS_GEN8(dev))
11270 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11271 MI_SRM_LRM_GLOBAL_GTT);
11272 else
11273 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11274 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11275 intel_ring_emit(ring, DERRMR);
11276 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11277 if (IS_GEN8(dev)) {
11278 intel_ring_emit(ring, 0);
11279 intel_ring_emit(ring, MI_NOOP);
11280 }
ffe74d75
CW		 11281 }
11282
cb05d8de 11283 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11284 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11285 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11286 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11287
11288 intel_mark_page_flip_active(intel_crtc);
09246732 11289 __intel_ring_advance(ring);
83d4092b 11290 return 0;
7c9017e5
JB		 11291}
11292
84c33a64
SG		 11293static bool use_mmio_flip(struct intel_engine_cs *ring,
11294 struct drm_i915_gem_object *obj)
11295{
11296 /*
11297 * This is not being used for older platforms, because
11298 * non-availability of flip done interrupt forces us to use
11299 * CS flips. Older platforms derive flip done using some clever
11300 * tricks involving the flip_pending status bits and vblank irqs.
11301 * So using MMIO flips there would disrupt this mechanism.
11302 */
11303
8e09bf83
CW		 11304 if (ring == NULL)
11305 return true;
11306
84c33a64
SG		 11307 if (INTEL_INFO(ring->dev)->gen < 5)
11308 return false;
11309
11310 if (i915.use_mmio_flip < 0)
11311 return false;
11312 else if (i915.use_mmio_flip > 0)
11313 return true;
14bf993e
OM		 11314 else if (i915.enable_execlists)
11315 return true;
84c33a64 11316 else
b4716185 11317 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11318}
11319
ff944564
DL		 11320static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11321{
11322 struct drm_device *dev = intel_crtc->base.dev;
11323 struct drm_i915_private *dev_priv = dev->dev_private;
11324 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11325 const enum pipe pipe = intel_crtc->pipe;
11326 u32 ctl, stride;
11327
11328 ctl = I915_READ(PLANE_CTL(pipe, 0));
11329 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11330 switch (fb->modifier[0]) {
11331 case DRM_FORMAT_MOD_NONE:
11332 break;
11333 case I915_FORMAT_MOD_X_TILED:
ff944564 11334 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11335 break;
11336 case I915_FORMAT_MOD_Y_TILED:
11337 ctl |= PLANE_CTL_TILED_Y;
11338 break;
11339 case I915_FORMAT_MOD_Yf_TILED:
11340 ctl |= PLANE_CTL_TILED_YF;
11341 break;
11342 default:
11343 MISSING_CASE(fb->modifier[0]);
11344 }
ff944564
DL		 11345
11346 /*
11347 * The stride is either expressed as a multiple of 64 bytes chunks for
11348 * linear buffers or in number of tiles for tiled buffers.
11349 */
2ebef630
TU		 11350 stride = fb->pitches[0] /
11351 intel_fb_stride_alignment(dev, fb->modifier[0],
11352 fb->pixel_format);
ff944564
DL		 11353
11354 /*
11355 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11356 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11357 */
11358 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11359 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11360
11361 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11362 POSTING_READ(PLANE_SURF(pipe, 0));
11363}
11364
11365static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11366{
11367 struct drm_device *dev = intel_crtc->base.dev;
11368 struct drm_i915_private *dev_priv = dev->dev_private;
11369 struct intel_framebuffer *intel_fb =
11370 to_intel_framebuffer(intel_crtc->base.primary->fb);
11371 struct drm_i915_gem_object *obj = intel_fb->obj;
11372 u32 dspcntr;
11373 u32 reg;
11374
84c33a64
SG		 11375 reg = DSPCNTR(intel_crtc->plane);
11376 dspcntr = I915_READ(reg);
11377
c5d97472
DL		 11378 if (obj->tiling_mode != I915_TILING_NONE)
11379 dspcntr |= DISPPLANE_TILED;
11380 else
11381 dspcntr &= ~DISPPLANE_TILED;
11382
84c33a64
SG		 11383 I915_WRITE(reg, dspcntr);
11384
11385 I915_WRITE(DSPSURF(intel_crtc->plane),
11386 intel_crtc->unpin_work->gtt_offset);
11387 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11388
ff944564
DL		 11389}
11390
11391/*
11392 * XXX: This is the temporary way to update the plane registers until we get
11393 * around to using the usual plane update functions for MMIO flips
11394 */
11395static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11396{
11397 struct drm_device *dev = intel_crtc->base.dev;
11398 bool atomic_update;
11399 u32 start_vbl_count;
11400
11401 intel_mark_page_flip_active(intel_crtc);
11402
11403 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11404
11405 if (INTEL_INFO(dev)->gen >= 9)
11406 skl_do_mmio_flip(intel_crtc);
11407 else
11408 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11409 ilk_do_mmio_flip(intel_crtc);
11410
9362c7c5
ACO		 11411 if (atomic_update)
11412 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11413}
11414
9362c7c5 11415static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11416{
b2cfe0ab
CW		 11417 struct intel_mmio_flip *mmio_flip =
11418 container_of(work, struct intel_mmio_flip, work);
84c33a64 11419
eed29a5b
DV		 11420 if (mmio_flip->req)
11421 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11422 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11423 false, NULL,
11424 &mmio_flip->i915->rps.mmioflips));
84c33a64 11425
b2cfe0ab
CW		 11426 intel_do_mmio_flip(mmio_flip->crtc);
11427
eed29a5b 11428 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11429 kfree(mmio_flip);
84c33a64
SG		 11430}
11431
11432static int intel_queue_mmio_flip(struct drm_device *dev,
11433 struct drm_crtc *crtc,
11434 struct drm_framebuffer *fb,
11435 struct drm_i915_gem_object *obj,
11436 struct intel_engine_cs *ring,
11437 uint32_t flags)
11438{
b2cfe0ab
CW		 11439 struct intel_mmio_flip *mmio_flip;
11440
11441 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11442 if (mmio_flip == NULL)
11443 return -ENOMEM;
84c33a64 11444
bcafc4e3 11445 mmio_flip->i915 = to_i915(dev);
eed29a5b 11446 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11447 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11448
b2cfe0ab
CW		 11449 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11450 schedule_work(&mmio_flip->work);
84c33a64 11451
84c33a64
SG		 11452 return 0;
11453}
11454
8c9f3aaf
JB		 11455static int intel_default_queue_flip(struct drm_device *dev,
11456 struct drm_crtc *crtc,
11457 struct drm_framebuffer *fb,
ed8d1975 11458 struct drm_i915_gem_object *obj,
a4872ba6 11459 struct intel_engine_cs *ring,
ed8d1975 11460 uint32_t flags)
8c9f3aaf
JB		 11461{
11462 return -ENODEV;
11463}
11464
d6bbafa1
CW		 11465static bool __intel_pageflip_stall_check(struct drm_device *dev,
11466 struct drm_crtc *crtc)
11467{
11468 struct drm_i915_private *dev_priv = dev->dev_private;
11469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11470 struct intel_unpin_work *work = intel_crtc->unpin_work;
11471 u32 addr;
11472
11473 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11474 return true;
11475
11476 if (!work->enable_stall_check)
11477 return false;
11478
11479 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11480 if (work->flip_queued_req &&
11481 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11482 return false;
11483
1e3feefd 11484 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11485 }
11486
1e3feefd 11487 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11488 return false;
11489
11490 /* Potential stall - if we see that the flip has happened,
11491 * assume a missed interrupt. */
11492 if (INTEL_INFO(dev)->gen >= 4)
11493 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11494 else
11495 addr = I915_READ(DSPADDR(intel_crtc->plane));
11496
11497 /* There is a potential issue here with a false positive after a flip
11498 * to the same address. We could address this by checking for a
11499 * non-incrementing frame counter.
11500 */
11501 return addr == work->gtt_offset;
11502}
11503
11504void intel_check_page_flip(struct drm_device *dev, int pipe)
11505{
11506 struct drm_i915_private *dev_priv = dev->dev_private;
11507 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11509 struct intel_unpin_work *work;
f326038a 11510
6c51d46f 11511 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11512
11513 if (crtc == NULL)
11514 return;
11515
f326038a 11516 spin_lock(&dev->event_lock);
6ad790c0
CW		 11517 work = intel_crtc->unpin_work;
11518 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11519 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11520 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11521 page_flip_completed(intel_crtc);
6ad790c0 11522 work = NULL;
d6bbafa1 11523 }
6ad790c0
CW		 11524 if (work != NULL &&
11525 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11526 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11527 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11528}
11529
6b95a207
KH		 11530static int intel_crtc_page_flip(struct drm_crtc *crtc,
11531 struct drm_framebuffer *fb,
ed8d1975
KP		 11532 struct drm_pending_vblank_event *event,
11533 uint32_t page_flip_flags)
6b95a207
KH		 11534{
11535 struct drm_device *dev = crtc->dev;
11536 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11537 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11538 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11540 struct drm_plane *primary = crtc->primary;
a071fa00 11541 enum pipe pipe = intel_crtc->pipe;
6b95a207 11542 struct intel_unpin_work *work;
a4872ba6 11543 struct intel_engine_cs *ring;
cf5d8a46 11544 bool mmio_flip;
52e68630 11545 int ret;
6b95a207 11546
2ff8fde1
MR		 11547 /*
11548 * drm_mode_page_flip_ioctl() should already catch this, but double
11549 * check to be safe. In the future we may enable pageflipping from
11550 * a disabled primary plane.
11551 */
11552 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11553 return -EBUSY;
11554
e6a595d2 11555 /* Can't change pixel format via MI display flips. */
f4510a27 11556 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11557 return -EINVAL;
11558
11559 /*
11560 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11561 * Note that pitch changes could also affect these register.
11562 */
11563 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11564 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11565 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11566 return -EINVAL;
11567
f900db47
CW		 11568 if (i915_terminally_wedged(&dev_priv->gpu_error))
11569 goto out_hang;
11570
b14c5679 11571 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11572 if (work == NULL)
11573 return -ENOMEM;
11574
6b95a207 11575 work->event = event;
b4a98e57 11576 work->crtc = crtc;
ab8d6675 11577 work->old_fb = old_fb;
6b95a207
KH		 11578 INIT_WORK(&work->work, intel_unpin_work_fn);
11579
87b6b101 11580 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11581 if (ret)
11582 goto free_work;
11583
6b95a207 11584 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11585 spin_lock_irq(&dev->event_lock);
6b95a207 11586 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11587 /* Before declaring the flip queue wedged, check if
11588 * the hardware completed the operation behind our backs.
11589 */
11590 if (__intel_pageflip_stall_check(dev, crtc)) {
11591 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11592 page_flip_completed(intel_crtc);
11593 } else {
11594 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11595 spin_unlock_irq(&dev->event_lock);
468f0b44 11596
d6bbafa1
CW		 11597 drm_crtc_vblank_put(crtc);
11598 kfree(work);
11599 return -EBUSY;
11600 }
6b95a207
KH		 11601 }
11602 intel_crtc->unpin_work = work;
5e2d7afc 11603 spin_unlock_irq(&dev->event_lock);
6b95a207 11604
b4a98e57
CW		 11605 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11606 flush_workqueue(dev_priv->wq);
11607
75dfca80 11608 /* Reference the objects for the scheduled work. */
ab8d6675 11609 drm_framebuffer_reference(work->old_fb);
05394f39 11610 drm_gem_object_reference(&obj->base);
6b95a207 11611
f4510a27 11612 crtc->primary->fb = fb;
afd65eb4 11613 update_state_fb(crtc->primary);
1ed1f968 11614
e1f99ce6 11615 work->pending_flip_obj = obj;
e1f99ce6 11616
89ed88ba
CW		 11617 ret = i915_mutex_lock_interruptible(dev);
11618 if (ret)
11619 goto cleanup;
11620
b4a98e57 11621 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11622 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11623
75f7f3ec 11624 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11625 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11626
4fa62c89
VS		 11627 if (IS_VALLEYVIEW(dev)) {
11628 ring = &dev_priv->ring[BCS];
ab8d6675 11629 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11630 /* vlv: DISPLAY_FLIP fails to change tiling */
11631 ring = NULL;
48bf5b2d 11632 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11633 ring = &dev_priv->ring[BCS];
4fa62c89 11634 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11635 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11636 if (ring == NULL || ring->id != RCS)
11637 ring = &dev_priv->ring[BCS];
11638 } else {
11639 ring = &dev_priv->ring[RCS];
11640 }
11641
cf5d8a46
CW		 11642 mmio_flip = use_mmio_flip(ring, obj);
11643
11644 /* When using CS flips, we want to emit semaphores between rings.
11645 * However, when using mmio flips we will create a task to do the
11646 * synchronisation, so all we want here is to pin the framebuffer
11647 * into the display plane and skip any waits.
11648 */
82bc3b2d 11649 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11650 crtc->primary->state,
b4716185 11651 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11652 if (ret)
11653 goto cleanup_pending;
6b95a207 11654
121920fa
TU		 11655 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11656 + intel_crtc->dspaddr_offset;
4fa62c89 11657
cf5d8a46 11658 if (mmio_flip) {
84c33a64
SG		 11659 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11660 page_flip_flags);
d6bbafa1
CW		 11661 if (ret)
11662 goto cleanup_unpin;
11663
f06cc1b9
JH		 11664 i915_gem_request_assign(&work->flip_queued_req,
11665 obj->last_write_req);
d6bbafa1 11666 } else {
d94b5030
CW		 11667 if (obj->last_write_req) {
11668 ret = i915_gem_check_olr(obj->last_write_req);
11669 if (ret)
11670 goto cleanup_unpin;
11671 }
11672
84c33a64 11673 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11674 page_flip_flags);
11675 if (ret)
11676 goto cleanup_unpin;
11677
f06cc1b9
JH		 11678 i915_gem_request_assign(&work->flip_queued_req,
11679 intel_ring_get_request(ring));
d6bbafa1
CW		 11680 }
11681
1e3feefd 11682 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11683 work->enable_stall_check = true;
4fa62c89 11684
ab8d6675 11685 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11686 INTEL_FRONTBUFFER_PRIMARY(pipe));
11687
7ff0ebcc 11688 intel_fbc_disable(dev);
f99d7069 11689 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11690 mutex_unlock(&dev->struct_mutex);
11691
e5510fac
JB		 11692 trace_i915_flip_request(intel_crtc->plane, obj);
11693
6b95a207 11694 return 0;
96b099fd 11695
4fa62c89 11696cleanup_unpin:
82bc3b2d 11697 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11698cleanup_pending:
b4a98e57 11699 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11700 mutex_unlock(&dev->struct_mutex);
11701cleanup:
f4510a27 11702 crtc->primary->fb = old_fb;
afd65eb4 11703 update_state_fb(crtc->primary);
89ed88ba
CW		 11704
11705 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11706 drm_framebuffer_unreference(work->old_fb);
96b099fd 11707
5e2d7afc 11708 spin_lock_irq(&dev->event_lock);
96b099fd 11709 intel_crtc->unpin_work = NULL;
5e2d7afc 11710 spin_unlock_irq(&dev->event_lock);
96b099fd 11711
87b6b101 11712 drm_crtc_vblank_put(crtc);
7317c75e 11713free_work:
96b099fd
CW		 11714 kfree(work);
11715
f900db47
CW		 11716 if (ret == -EIO) {
11717out_hang:
53a366b9 11718 ret = intel_plane_restore(primary);
f0d3dad3 11719 if (ret == 0 && event) {
5e2d7afc 11720 spin_lock_irq(&dev->event_lock);
a071fa00 11721 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11722 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11723 }
f900db47 11724 }
96b099fd 11725 return ret;
6b95a207
KH		 11726}
11727
65b38e0d 11728static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11729 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11730 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11731 .atomic_begin = intel_begin_crtc_commit,
11732 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11733};
11734
9a935856
DV		 11735/**
11736 * intel_modeset_update_staged_output_state
11737 *
11738 * Updates the staged output configuration state, e.g. after we've read out the
11739 * current hw state.
11740 */
11741static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11742{
7668851f 11743 struct intel_crtc *crtc;
9a935856
DV		 11744 struct intel_encoder *encoder;
11745 struct intel_connector *connector;
f6e5b160 11746
3a3371ff 11747 for_each_intel_connector(dev, connector) {
9a935856
DV		 11748 connector->new_encoder =
11749 to_intel_encoder(connector->base.encoder);
11750 }
f6e5b160 11751
b2784e15 11752 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11753 encoder->new_crtc =
11754 to_intel_crtc(encoder->base.crtc);
11755 }
7668851f 11756
d3fcc808 11757 for_each_intel_crtc(dev, crtc) {
83d65738 11758 crtc->new_enabled = crtc->base.state->enable;
7668851f 11759 }
f6e5b160
CW		 11760}
11761
d29b2f9d
ACO		 11762/* Transitional helper to copy current connector/encoder state to
11763 * connector->state. This is needed so that code that is partially
11764 * converted to atomic does the right thing.
11765 */
11766static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11767{
11768 struct intel_connector *connector;
11769
11770 for_each_intel_connector(dev, connector) {
11771 if (connector->base.encoder) {
11772 connector->base.state->best_encoder =
11773 connector->base.encoder;
11774 connector->base.state->crtc =
11775 connector->base.encoder->crtc;
11776 } else {
11777 connector->base.state->best_encoder = NULL;
11778 connector->base.state->crtc = NULL;
11779 }
11780 }
11781}
11782
a821fc46 11783/* Fixup legacy state after an atomic state swap.
9a935856 11784 */
a821fc46 11785static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11786{
a821fc46 11787 struct intel_crtc *crtc;
9a935856 11788 struct intel_encoder *encoder;
a821fc46 11789 struct intel_connector *connector;
d5432a9d 11790
a821fc46
ACO		 11791 for_each_intel_connector(state->dev, connector) {
11792 connector->base.encoder = connector->base.state->best_encoder;
11793 if (connector->base.encoder)
11794 connector->base.encoder->crtc =
11795 connector->base.state->crtc;
9a935856 11796 }
f6e5b160 11797
d5432a9d
ACO		 11798 /* Update crtc of disabled encoders */
11799 for_each_intel_encoder(state->dev, encoder) {
11800 int num_connectors = 0;
11801
a821fc46
ACO		 11802 for_each_intel_connector(state->dev, connector)
11803 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11804 num_connectors++;
11805
11806 if (num_connectors == 0)
11807 encoder->base.crtc = NULL;
9a935856 11808 }
7668851f 11809
a821fc46
ACO		 11810 for_each_intel_crtc(state->dev, crtc) {
11811 crtc->base.enabled = crtc->base.state->enable;
11812 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11813 }
d29b2f9d 11814
d5432a9d
ACO		 11815 /* Copy the new configuration to the staged state, to keep the few
11816 * pieces of code that haven't been converted yet happy */
11817 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11818}
11819
050f7aeb 11820static void
eba905b2 11821connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11822 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11823{
11824 int bpp = pipe_config->pipe_bpp;
11825
11826 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11827 connector->base.base.id,
c23cc417 11828 connector->base.name);
050f7aeb
DV		 11829
11830 /* Don't use an invalid EDID bpc value */
11831 if (connector->base.display_info.bpc &&
11832 connector->base.display_info.bpc * 3 < bpp) {
11833 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11834 bpp, connector->base.display_info.bpc*3);
11835 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11836 }
11837
11838 /* Clamp bpp to 8 on screens without EDID 1.4 */
11839 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11840 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11841 bpp);
11842 pipe_config->pipe_bpp = 24;
11843 }
11844}
11845
4e53c2e0 11846static int
050f7aeb 11847compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11848 struct intel_crtc_state *pipe_config)
4e53c2e0 11849{
050f7aeb 11850 struct drm_device *dev = crtc->base.dev;
1486017f 11851 struct drm_atomic_state *state;
da3ced29
ACO		 11852 struct drm_connector *connector;
11853 struct drm_connector_state *connector_state;
1486017f 11854 int bpp, i;
4e53c2e0 11855
d328c9d7 11856 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11857 bpp = 10*3;
d328c9d7
DV		 11858 else if (INTEL_INFO(dev)->gen >= 5)
11859 bpp = 12*3;
11860 else
11861 bpp = 8*3;
11862
4e53c2e0 11863
4e53c2e0
DV		 11864 pipe_config->pipe_bpp = bpp;
11865
1486017f
ACO		 11866 state = pipe_config->base.state;
11867
4e53c2e0 11868 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11869 for_each_connector_in_state(state, connector, connector_state, i) {
11870 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11871 continue;
11872
da3ced29
ACO		 11873 connected_sink_compute_bpp(to_intel_connector(connector),
11874 pipe_config);
4e53c2e0
DV		 11875 }
11876
11877 return bpp;
11878}
11879
644db711
DV		 11880static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11881{
11882 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11883 "type: 0x%x flags: 0x%x\n",
1342830c 11884 mode->crtc_clock,
644db711
DV		 11885 mode->crtc_hdisplay, mode->crtc_hsync_start,
11886 mode->crtc_hsync_end, mode->crtc_htotal,
11887 mode->crtc_vdisplay, mode->crtc_vsync_start,
11888 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11889}
11890
c0b03411 11891static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11892 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11893 const char *context)
11894{
6a60cd87
CK		 11895 struct drm_device *dev = crtc->base.dev;
11896 struct drm_plane *plane;
11897 struct intel_plane *intel_plane;
11898 struct intel_plane_state *state;
11899 struct drm_framebuffer *fb;
11900
11901 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11902 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11903
11904 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11905 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11906 pipe_config->pipe_bpp, pipe_config->dither);
11907 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11908 pipe_config->has_pch_encoder,
11909 pipe_config->fdi_lanes,
11910 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11911 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11912 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11913 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11914 pipe_config->has_dp_encoder,
11915 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11916 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11917 pipe_config->dp_m_n.tu);
b95af8be
VK		 11918
11919 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11920 pipe_config->has_dp_encoder,
11921 pipe_config->dp_m2_n2.gmch_m,
11922 pipe_config->dp_m2_n2.gmch_n,
11923 pipe_config->dp_m2_n2.link_m,
11924 pipe_config->dp_m2_n2.link_n,
11925 pipe_config->dp_m2_n2.tu);
11926
55072d19
DV		 11927 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11928 pipe_config->has_audio,
11929 pipe_config->has_infoframe);
11930
c0b03411 11931 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11932 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11933 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11934 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11935 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11936 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11937 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11938 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11939 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11940 crtc->num_scalers,
11941 pipe_config->scaler_state.scaler_users,
11942 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11943 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11944 pipe_config->gmch_pfit.control,
11945 pipe_config->gmch_pfit.pgm_ratios,
11946 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11947 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11948 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11949 pipe_config->pch_pfit.size,
11950 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11951 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11952 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11953
415ff0f6
TU		 11954 if (IS_BROXTON(dev)) {
11955 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11956 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11957 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11958 pipe_config->ddi_pll_sel,
11959 pipe_config->dpll_hw_state.ebb0,
11960 pipe_config->dpll_hw_state.pll0,
11961 pipe_config->dpll_hw_state.pll1,
11962 pipe_config->dpll_hw_state.pll2,
11963 pipe_config->dpll_hw_state.pll3,
11964 pipe_config->dpll_hw_state.pll6,
11965 pipe_config->dpll_hw_state.pll8,
11966 pipe_config->dpll_hw_state.pcsdw12);
11967 } else if (IS_SKYLAKE(dev)) {
11968 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11969 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11970 pipe_config->ddi_pll_sel,
11971 pipe_config->dpll_hw_state.ctrl1,
11972 pipe_config->dpll_hw_state.cfgcr1,
11973 pipe_config->dpll_hw_state.cfgcr2);
11974 } else if (HAS_DDI(dev)) {
11975 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11976 pipe_config->ddi_pll_sel,
11977 pipe_config->dpll_hw_state.wrpll);
11978 } else {
11979 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11980 "fp0: 0x%x, fp1: 0x%x\n",
11981 pipe_config->dpll_hw_state.dpll,
11982 pipe_config->dpll_hw_state.dpll_md,
11983 pipe_config->dpll_hw_state.fp0,
11984 pipe_config->dpll_hw_state.fp1);
11985 }
11986
6a60cd87
CK		 11987 DRM_DEBUG_KMS("planes on this crtc\n");
11988 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11989 intel_plane = to_intel_plane(plane);
11990 if (intel_plane->pipe != crtc->pipe)
11991 continue;
11992
11993 state = to_intel_plane_state(plane->state);
11994 fb = state->base.fb;
11995 if (!fb) {
11996 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11997 "disabled, scaler_id = %d\n",
11998 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11999 plane->base.id, intel_plane->pipe,
12000 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12001 drm_plane_index(plane), state->scaler_id);
12002 continue;
12003 }
12004
12005 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12006 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12007 plane->base.id, intel_plane->pipe,
12008 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12009 drm_plane_index(plane));
12010 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12011 fb->base.id, fb->width, fb->height, fb->pixel_format);
12012 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12013 state->scaler_id,
12014 state->src.x1 >> 16, state->src.y1 >> 16,
12015 drm_rect_width(&state->src) >> 16,
12016 drm_rect_height(&state->src) >> 16,
12017 state->dst.x1, state->dst.y1,
12018 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12019 }
c0b03411
DV		 12020}
12021
bc079e8b
VS		 12022static bool encoders_cloneable(const struct intel_encoder *a,
12023 const struct intel_encoder *b)
accfc0c5 12024{
bc079e8b
VS		 12025 /* masks could be asymmetric, so check both ways */
12026 return a == b || (a->cloneable & (1 << b->type) &&
12027 b->cloneable & (1 << a->type));
12028}
12029
98a221da
ACO		 12030static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12031 struct intel_crtc *crtc,
bc079e8b
VS		 12032 struct intel_encoder *encoder)
12033{
bc079e8b 12034 struct intel_encoder *source_encoder;
da3ced29 12035 struct drm_connector *connector;
98a221da
ACO		 12036 struct drm_connector_state *connector_state;
12037 int i;
bc079e8b 12038
da3ced29 12039 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 12040 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 12041 continue;
12042
98a221da
ACO		 12043 source_encoder =
12044 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 12045 if (!encoders_cloneable(encoder, source_encoder))
12046 return false;
12047 }
12048
12049 return true;
12050}
12051
98a221da
ACO		 12052static bool check_encoder_cloning(struct drm_atomic_state *state,
12053 struct intel_crtc *crtc)
bc079e8b 12054{
accfc0c5 12055 struct intel_encoder *encoder;
da3ced29 12056 struct drm_connector *connector;
98a221da
ACO		 12057 struct drm_connector_state *connector_state;
12058 int i;
accfc0c5 12059
da3ced29 12060 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 12061 if (connector_state->crtc != &crtc->base)
12062 continue;
12063
12064 encoder = to_intel_encoder(connector_state->best_encoder);
12065 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 12066 return false;
accfc0c5
DV		 12067 }
12068
bc079e8b 12069 return true;
accfc0c5
DV		 12070}
12071
5448a00d 12072static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12073{
5448a00d
ACO		 12074 struct drm_device *dev = state->dev;
12075 struct intel_encoder *encoder;
da3ced29 12076 struct drm_connector *connector;
5448a00d 12077 struct drm_connector_state *connector_state;
00f0b378 12078 unsigned int used_ports = 0;
5448a00d 12079 int i;
00f0b378
VS		 12080
12081 /*
12082 * Walk the connector list instead of the encoder
12083 * list to detect the problem on ddi platforms
12084 * where there's just one encoder per digital port.
12085 */
da3ced29 12086 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12087 if (!connector_state->best_encoder)
00f0b378
VS		 12088 continue;
12089
5448a00d
ACO		 12090 encoder = to_intel_encoder(connector_state->best_encoder);
12091
12092 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12093
12094 switch (encoder->type) {
12095 unsigned int port_mask;
12096 case INTEL_OUTPUT_UNKNOWN:
12097 if (WARN_ON(!HAS_DDI(dev)))
12098 break;
12099 case INTEL_OUTPUT_DISPLAYPORT:
12100 case INTEL_OUTPUT_HDMI:
12101 case INTEL_OUTPUT_EDP:
12102 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12103
12104 /* the same port mustn't appear more than once */
12105 if (used_ports & port_mask)
12106 return false;
12107
12108 used_ports |= port_mask;
12109 default:
12110 break;
12111 }
12112 }
12113
12114 return true;
12115}
12116
83a57153
ACO		 12117static void
12118clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12119{
12120 struct drm_crtc_state tmp_state;
663a3640 12121 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12122 struct intel_dpll_hw_state dpll_hw_state;
12123 enum intel_dpll_id shared_dpll;
8504c74c 12124 uint32_t ddi_pll_sel;
83a57153 12125
7546a384
ACO		 12126 /* FIXME: before the switch to atomic started, a new pipe_config was
12127 * kzalloc'd. Code that depends on any field being zero should be
12128 * fixed, so that the crtc_state can be safely duplicated. For now,
12129 * only fields that are know to not cause problems are preserved. */
12130
83a57153 12131 tmp_state = crtc_state->base;
663a3640 12132 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12133 shared_dpll = crtc_state->shared_dpll;
12134 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12135 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12136
83a57153 12137 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12138
83a57153 12139 crtc_state->base = tmp_state;
663a3640 12140 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12141 crtc_state->shared_dpll = shared_dpll;
12142 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12143 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12144}
12145
548ee15b 12146static int
b8cecdf5 12147intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 12148 struct drm_atomic_state *state,
12149 struct intel_crtc_state *pipe_config)
ee7b9f93 12150{
7758a113 12151 struct intel_encoder *encoder;
da3ced29 12152 struct drm_connector *connector;
0b901879 12153 struct drm_connector_state *connector_state;
d328c9d7 12154 int base_bpp, ret = -EINVAL;
0b901879 12155 int i;
e29c22c0 12156 bool retry = true;
ee7b9f93 12157
98a221da 12158 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 12159 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 12160 return -EINVAL;
accfc0c5
DV		 12161 }
12162
5448a00d 12163 if (!check_digital_port_conflicts(state)) {
00f0b378 12164 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 12165 return -EINVAL;
00f0b378
VS		 12166 }
12167
83a57153 12168 clear_intel_crtc_state(pipe_config);
7758a113 12169
e143a21c
DV		 12170 pipe_config->cpu_transcoder =
12171 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12172
2960bc9c
ID		 12173 /*
12174 * Sanitize sync polarity flags based on requested ones. If neither
12175 * positive or negative polarity is requested, treat this as meaning
12176 * negative polarity.
12177 */
2d112de7 12178 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12179 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12180 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12181
2d112de7 12182 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12183 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12184 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12185
050f7aeb
DV		 12186 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12187 * plane pixel format and any sink constraints into account. Returns the
12188 * source plane bpp so that dithering can be selected on mismatches
12189 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12190 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12191 pipe_config);
12192 if (base_bpp < 0)
4e53c2e0
DV		 12193 goto fail;
12194
e41a56be
VS		 12195 /*
12196 * Determine the real pipe dimensions. Note that stereo modes can
12197 * increase the actual pipe size due to the frame doubling and
12198 * insertion of additional space for blanks between the frame. This
12199 * is stored in the crtc timings. We use the requested mode to do this
12200 * computation to clearly distinguish it from the adjusted mode, which
12201 * can be changed by the connectors in the below retry loop.
12202 */
2d112de7 12203 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12204 &pipe_config->pipe_src_w,
12205 &pipe_config->pipe_src_h);
e41a56be 12206
e29c22c0 12207encoder_retry:
ef1b460d 12208 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12209 pipe_config->port_clock = 0;
ef1b460d 12210 pipe_config->pixel_multiplier = 1;
ff9a6750 12211
135c81b8 12212 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12213 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12214 CRTC_STEREO_DOUBLE);
135c81b8 12215
7758a113
DV		 12216 /* Pass our mode to the connectors and the CRTC to give them a chance to
12217 * adjust it according to limitations or connector properties, and also
12218 * a chance to reject the mode entirely.
47f1c6c9 12219 */
da3ced29 12220 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12221 if (connector_state->crtc != crtc)
7758a113 12222 continue;
7ae89233 12223
0b901879
ACO		 12224 encoder = to_intel_encoder(connector_state->best_encoder);
12225
efea6e8e
DV		 12226 if (!(encoder->compute_config(encoder, pipe_config))) {
12227 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12228 goto fail;
12229 }
ee7b9f93 12230 }
47f1c6c9 12231
ff9a6750
DV		 12232 /* Set default port clock if not overwritten by the encoder. Needs to be
12233 * done afterwards in case the encoder adjusts the mode. */
12234 if (!pipe_config->port_clock)
2d112de7 12235 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12236 * pipe_config->pixel_multiplier;
ff9a6750 12237
a43f6e0f 12238 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12239 if (ret < 0) {
7758a113
DV		 12240 DRM_DEBUG_KMS("CRTC fixup failed\n");
12241 goto fail;
ee7b9f93 12242 }
e29c22c0
DV		 12243
12244 if (ret == RETRY) {
12245 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12246 ret = -EINVAL;
12247 goto fail;
12248 }
12249
12250 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12251 retry = false;
12252 goto encoder_retry;
12253 }
12254
d328c9d7 12255 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12256 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12257 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12258
548ee15b 12259 return 0;
7758a113 12260fail:
548ee15b 12261 return ret;
ee7b9f93 12262}
47f1c6c9 12263
ea9d758d 12264static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12265{
ea9d758d 12266 struct drm_encoder *encoder;
f6e5b160 12267 struct drm_device *dev = crtc->dev;
f6e5b160 12268
ea9d758d
DV		 12269 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12270 if (encoder->crtc == crtc)
12271 return true;
12272
12273 return false;
12274}
12275
0a9ab303
ACO		 12276static bool
12277needs_modeset(struct drm_crtc_state *state)
12278{
12279 return state->mode_changed || state->active_changed;
12280}
12281
ea9d758d 12282static void
0a9ab303 12283intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12284{
0a9ab303 12285 struct drm_device *dev = state->dev;
ba41c0de 12286 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12287 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12288 struct drm_crtc *crtc;
12289 struct drm_crtc_state *crtc_state;
ea9d758d 12290 struct drm_connector *connector;
0a9ab303 12291 int i;
ea9d758d 12292
ba41c0de
DV		 12293 intel_shared_dpll_commit(dev_priv);
12294
b2784e15 12295 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12296 if (!intel_encoder->base.crtc)
12297 continue;
12298
bd4b4827
ACO		 12299 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12300 if (crtc != intel_encoder->base.crtc)
12301 continue;
0a9ab303 12302
bd4b4827
ACO		 12303 if (crtc_state->enable && needs_modeset(crtc_state))
12304 intel_encoder->connectors_active = false;
ea9d758d 12305
bd4b4827
ACO		 12306 break;
12307 }
ea9d758d
DV		 12308 }
12309
a821fc46
ACO		 12310 drm_atomic_helper_swap_state(state->dev, state);
12311 intel_modeset_fixup_state(state);
ea9d758d 12312
7668851f 12313 /* Double check state. */
0a9ab303
ACO		 12314 for_each_crtc(dev, crtc) {
12315 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 12316 }
12317
12318 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12319 if (!connector->encoder || !connector->encoder->crtc)
12320 continue;
12321
bd4b4827
ACO		 12322 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12323 if (crtc != connector->encoder->crtc)
12324 continue;
0a9ab303 12325
bd4b4827
ACO		 12326 if (crtc->state->enable && needs_modeset(crtc->state)) {
12327 struct drm_property *dpms_property =
12328 dev->mode_config.dpms_property;
ea9d758d 12329
bd4b4827
ACO		 12330 connector->dpms = DRM_MODE_DPMS_ON;
12331 drm_object_property_set_value(&connector->base,
12332 dpms_property,
12333 DRM_MODE_DPMS_ON);
68d34720 12334
bd4b4827
ACO		 12335 intel_encoder = to_intel_encoder(connector->encoder);
12336 intel_encoder->connectors_active = true;
12337 }
ea9d758d 12338
bd4b4827 12339 break;
ea9d758d
DV		 12340 }
12341 }
12342
12343}
12344
3bd26263 12345static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12346{
3bd26263 12347 int diff;
f1f644dc
JB		 12348
12349 if (clock1 == clock2)
12350 return true;
12351
12352 if (!clock1 || !clock2)
12353 return false;
12354
12355 diff = abs(clock1 - clock2);
12356
12357 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12358 return true;
12359
12360 return false;
12361}
12362
25c5b266
DV		 12363#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12364 list_for_each_entry((intel_crtc), \
12365 &(dev)->mode_config.crtc_list, \
12366 base.head) \
0973f18f 12367 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12368
0e8ffe1b 12369static bool
2fa2fe9a 12370intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12371 struct intel_crtc_state *current_config,
12372 struct intel_crtc_state *pipe_config)
0e8ffe1b 12373{
66e985c0
DV		 12374#define PIPE_CONF_CHECK_X(name) \
12375 if (current_config->name != pipe_config->name) { \
12376 DRM_ERROR("mismatch in " #name " " \
12377 "(expected 0x%08x, found 0x%08x)\n", \
12378 current_config->name, \
12379 pipe_config->name); \
12380 return false; \
12381 }
12382
08a24034
DV		 12383#define PIPE_CONF_CHECK_I(name) \
12384 if (current_config->name != pipe_config->name) { \
12385 DRM_ERROR("mismatch in " #name " " \
12386 "(expected %i, found %i)\n", \
12387 current_config->name, \
12388 pipe_config->name); \
12389 return false; \
88adfff1
DV		 12390 }
12391
b95af8be
VK		 12392/* This is required for BDW+ where there is only one set of registers for
12393 * switching between high and low RR.
12394 * This macro can be used whenever a comparison has to be made between one
12395 * hw state and multiple sw state variables.
12396 */
12397#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12398 if ((current_config->name != pipe_config->name) && \
12399 (current_config->alt_name != pipe_config->name)) { \
12400 DRM_ERROR("mismatch in " #name " " \
12401 "(expected %i or %i, found %i)\n", \
12402 current_config->name, \
12403 current_config->alt_name, \
12404 pipe_config->name); \
12405 return false; \
12406 }
12407
1bd1bd80
DV		 12408#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12409 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12410 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12411 "(expected %i, found %i)\n", \
12412 current_config->name & (mask), \
12413 pipe_config->name & (mask)); \
12414 return false; \
12415 }
12416
5e550656
VS		 12417#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12418 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12419 DRM_ERROR("mismatch in " #name " " \
12420 "(expected %i, found %i)\n", \
12421 current_config->name, \
12422 pipe_config->name); \
12423 return false; \
12424 }
12425
bb760063
DV		 12426#define PIPE_CONF_QUIRK(quirk) \
12427 ((current_config->quirks | pipe_config->quirks) & (quirk))
12428
eccb140b
DV		 12429 PIPE_CONF_CHECK_I(cpu_transcoder);
12430
08a24034
DV		 12431 PIPE_CONF_CHECK_I(has_pch_encoder);
12432 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12433 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12434 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12435 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12436 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12437 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12438
eb14cb74 12439 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12440
12441 if (INTEL_INFO(dev)->gen < 8) {
12442 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12443 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12444 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12445 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12446 PIPE_CONF_CHECK_I(dp_m_n.tu);
12447
12448 if (current_config->has_drrs) {
12449 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12450 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12451 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12452 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12453 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12454 }
12455 } else {
12456 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12457 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12458 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12459 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12460 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12461 }
eb14cb74 12462
2d112de7
ACO		 12463 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12464 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12465 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12466 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12467 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12468 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12469
2d112de7
ACO		 12470 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12471 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12472 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12473 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12474 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12475 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12476
c93f54cf 12477 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12478 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12479 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12480 IS_VALLEYVIEW(dev))
12481 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12482 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12483
9ed109a7
DV		 12484 PIPE_CONF_CHECK_I(has_audio);
12485
2d112de7 12486 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12487 DRM_MODE_FLAG_INTERLACE);
12488
bb760063 12489 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12490 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12491 DRM_MODE_FLAG_PHSYNC);
2d112de7 12492 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12493 DRM_MODE_FLAG_NHSYNC);
2d112de7 12494 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12495 DRM_MODE_FLAG_PVSYNC);
2d112de7 12496 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12497 DRM_MODE_FLAG_NVSYNC);
12498 }
045ac3b5 12499
37327abd
VS		 12500 PIPE_CONF_CHECK_I(pipe_src_w);
12501 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12502
9953599b
DV		 12503 /*
12504 * FIXME: BIOS likes to set up a cloned config with lvds+external
12505 * screen. Since we don't yet re-compute the pipe config when moving
12506 * just the lvds port away to another pipe the sw tracking won't match.
12507 *
12508 * Proper atomic modesets with recomputed global state will fix this.
12509 * Until then just don't check gmch state for inherited modes.
12510 */
12511 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12512 PIPE_CONF_CHECK_I(gmch_pfit.control);
12513 /* pfit ratios are autocomputed by the hw on gen4+ */
12514 if (INTEL_INFO(dev)->gen < 4)
12515 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12516 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12517 }
12518
fd4daa9c
CW		 12519 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12520 if (current_config->pch_pfit.enabled) {
12521 PIPE_CONF_CHECK_I(pch_pfit.pos);
12522 PIPE_CONF_CHECK_I(pch_pfit.size);
12523 }
2fa2fe9a 12524
a1b2278e
CK		 12525 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12526
e59150dc
JB		 12527 /* BDW+ don't expose a synchronous way to read the state */
12528 if (IS_HASWELL(dev))
12529 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12530
282740f7
VS		 12531 PIPE_CONF_CHECK_I(double_wide);
12532
26804afd
DV		 12533 PIPE_CONF_CHECK_X(ddi_pll_sel);
12534
c0d43d62 12535 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12536 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12537 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12538 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12539 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12540 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12541 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12542 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12543 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12544
42571aef
VS		 12545 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12546 PIPE_CONF_CHECK_I(pipe_bpp);
12547
2d112de7 12548 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12549 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12550
66e985c0 12551#undef PIPE_CONF_CHECK_X
08a24034 12552#undef PIPE_CONF_CHECK_I
b95af8be 12553#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12554#undef PIPE_CONF_CHECK_FLAGS
5e550656 12555#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12556#undef PIPE_CONF_QUIRK
88adfff1 12557
0e8ffe1b
DV		 12558 return true;
12559}
12560
08db6652
DL		 12561static void check_wm_state(struct drm_device *dev)
12562{
12563 struct drm_i915_private *dev_priv = dev->dev_private;
12564 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12565 struct intel_crtc *intel_crtc;
12566 int plane;
12567
12568 if (INTEL_INFO(dev)->gen < 9)
12569 return;
12570
12571 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12572 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12573
12574 for_each_intel_crtc(dev, intel_crtc) {
12575 struct skl_ddb_entry *hw_entry, *sw_entry;
12576 const enum pipe pipe = intel_crtc->pipe;
12577
12578 if (!intel_crtc->active)
12579 continue;
12580
12581 /* planes */
dd740780 12582 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12583 hw_entry = &hw_ddb.plane[pipe][plane];
12584 sw_entry = &sw_ddb->plane[pipe][plane];
12585
12586 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12587 continue;
12588
12589 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12590 "(expected (%u,%u), found (%u,%u))\n",
12591 pipe_name(pipe), plane + 1,
12592 sw_entry->start, sw_entry->end,
12593 hw_entry->start, hw_entry->end);
12594 }
12595
12596 /* cursor */
12597 hw_entry = &hw_ddb.cursor[pipe];
12598 sw_entry = &sw_ddb->cursor[pipe];
12599
12600 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12601 continue;
12602
12603 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12604 "(expected (%u,%u), found (%u,%u))\n",
12605 pipe_name(pipe),
12606 sw_entry->start, sw_entry->end,
12607 hw_entry->start, hw_entry->end);
12608 }
12609}
12610
91d1b4bd
DV		 12611static void
12612check_connector_state(struct drm_device *dev)
8af6cf88 12613{
8af6cf88
DV		 12614 struct intel_connector *connector;
12615
3a3371ff 12616 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12617 /* This also checks the encoder/connector hw state with the
12618 * ->get_hw_state callbacks. */
12619 intel_connector_check_state(connector);
12620
e2c719b7 12621 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12622 "connector's staged encoder doesn't match current encoder\n");
12623 }
91d1b4bd
DV		 12624}
12625
12626static void
12627check_encoder_state(struct drm_device *dev)
12628{
12629 struct intel_encoder *encoder;
12630 struct intel_connector *connector;
8af6cf88 12631
b2784e15 12632 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12633 bool enabled = false;
12634 bool active = false;
12635 enum pipe pipe, tracked_pipe;
12636
12637 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12638 encoder->base.base.id,
8e329a03 12639 encoder->base.name);
8af6cf88 12640
e2c719b7 12641 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12642 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12643 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12644 "encoder's active_connectors set, but no crtc\n");
12645
3a3371ff 12646 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12647 if (connector->base.encoder != &encoder->base)
12648 continue;
12649 enabled = true;
12650 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12651 active = true;
12652 }
0e32b39c
DA		 12653 /*
12654 * for MST connectors if we unplug the connector is gone
12655 * away but the encoder is still connected to a crtc
12656 * until a modeset happens in response to the hotplug.
12657 */
12658 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12659 continue;
12660
e2c719b7 12661 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12662 "encoder's enabled state mismatch "
12663 "(expected %i, found %i)\n",
12664 !!encoder->base.crtc, enabled);
e2c719b7 12665 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12666 "active encoder with no crtc\n");
12667
e2c719b7 12668 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12669 "encoder's computed active state doesn't match tracked active state "
12670 "(expected %i, found %i)\n", active, encoder->connectors_active);
12671
12672 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12673 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12674 "encoder's hw state doesn't match sw tracking "
12675 "(expected %i, found %i)\n",
12676 encoder->connectors_active, active);
12677
12678 if (!encoder->base.crtc)
12679 continue;
12680
12681 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12682 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12683 "active encoder's pipe doesn't match"
12684 "(expected %i, found %i)\n",
12685 tracked_pipe, pipe);
12686
12687 }
91d1b4bd
DV		 12688}
12689
12690static void
12691check_crtc_state(struct drm_device *dev)
12692{
fbee40df 12693 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12694 struct intel_crtc *crtc;
12695 struct intel_encoder *encoder;
5cec258b 12696 struct intel_crtc_state pipe_config;
8af6cf88 12697
d3fcc808 12698 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12699 bool enabled = false;
12700 bool active = false;
12701
045ac3b5
JB		 12702 memset(&pipe_config, 0, sizeof(pipe_config));
12703
8af6cf88
DV		 12704 DRM_DEBUG_KMS("[CRTC:%d]\n",
12705 crtc->base.base.id);
12706
83d65738 12707 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12708 "active crtc, but not enabled in sw tracking\n");
12709
b2784e15 12710 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12711 if (encoder->base.crtc != &crtc->base)
12712 continue;
12713 enabled = true;
12714 if (encoder->connectors_active)
12715 active = true;
12716 }
6c49f241 12717
e2c719b7 12718 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12719 "crtc's computed active state doesn't match tracked active state "
12720 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12721 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12722 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12723 "(expected %i, found %i)\n", enabled,
12724 crtc->base.state->enable);
8af6cf88 12725
0e8ffe1b
DV		 12726 active = dev_priv->display.get_pipe_config(crtc,
12727 &pipe_config);
d62cf62a 12728
b6b5d049
VS		 12729 /* hw state is inconsistent with the pipe quirk */
12730 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12731 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12732 active = crtc->active;
12733
b2784e15 12734 for_each_intel_encoder(dev, encoder) {
3eaba51c 12735 enum pipe pipe;
6c49f241
DV		 12736 if (encoder->base.crtc != &crtc->base)
12737 continue;
1d37b689 12738 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12739 encoder->get_config(encoder, &pipe_config);
12740 }
12741
e2c719b7 12742 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12743 "crtc active state doesn't match with hw state "
12744 "(expected %i, found %i)\n", crtc->active, active);
12745
c0b03411 12746 if (active &&
6e3c9717 12747 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12748 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12749 intel_dump_pipe_config(crtc, &pipe_config,
12750 "[hw state]");
6e3c9717 12751 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12752 "[sw state]");
12753 }
8af6cf88
DV		 12754 }
12755}
12756
91d1b4bd
DV		 12757static void
12758check_shared_dpll_state(struct drm_device *dev)
12759{
fbee40df 12760 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12761 struct intel_crtc *crtc;
12762 struct intel_dpll_hw_state dpll_hw_state;
12763 int i;
5358901f
DV		 12764
12765 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12766 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12767 int enabled_crtcs = 0, active_crtcs = 0;
12768 bool active;
12769
12770 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12771
12772 DRM_DEBUG_KMS("%s\n", pll->name);
12773
12774 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12775
e2c719b7 12776 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12777 "more active pll users than references: %i vs %i\n",
3e369b76 12778 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12779 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12780 "pll in active use but not on in sw tracking\n");
e2c719b7 12781 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12782 "pll in on but not on in use in sw tracking\n");
e2c719b7 12783 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12784 "pll on state mismatch (expected %i, found %i)\n",
12785 pll->on, active);
12786
d3fcc808 12787 for_each_intel_crtc(dev, crtc) {
83d65738 12788 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12789 enabled_crtcs++;
12790 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12791 active_crtcs++;
12792 }
e2c719b7 12793 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12794 "pll active crtcs mismatch (expected %i, found %i)\n",
12795 pll->active, active_crtcs);
e2c719b7 12796 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12797 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12798 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12799
e2c719b7 12800 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12801 sizeof(dpll_hw_state)),
12802 "pll hw state mismatch\n");
5358901f 12803 }
8af6cf88
DV		 12804}
12805
91d1b4bd
DV		 12806void
12807intel_modeset_check_state(struct drm_device *dev)
12808{
08db6652 12809 check_wm_state(dev);
91d1b4bd
DV		 12810 check_connector_state(dev);
12811 check_encoder_state(dev);
12812 check_crtc_state(dev);
12813 check_shared_dpll_state(dev);
12814}
12815
5cec258b 12816void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12817 int dotclock)
12818{
12819 /*
12820 * FDI already provided one idea for the dotclock.
12821 * Yell if the encoder disagrees.
12822 */
2d112de7 12823 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12824 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12825 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12826}
12827
80715b2f
VS		 12828static void update_scanline_offset(struct intel_crtc *crtc)
12829{
12830 struct drm_device *dev = crtc->base.dev;
12831
12832 /*
12833 * The scanline counter increments at the leading edge of hsync.
12834 *
12835 * On most platforms it starts counting from vtotal-1 on the
12836 * first active line. That means the scanline counter value is
12837 * always one less than what we would expect. Ie. just after
12838 * start of vblank, which also occurs at start of hsync (on the
12839 * last active line), the scanline counter will read vblank_start-1.
12840 *
12841 * On gen2 the scanline counter starts counting from 1 instead
12842 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12843 * to keep the value positive), instead of adding one.
12844 *
12845 * On HSW+ the behaviour of the scanline counter depends on the output
12846 * type. For DP ports it behaves like most other platforms, but on HDMI
12847 * there's an extra 1 line difference. So we need to add two instead of
12848 * one to the value.
12849 */
12850 if (IS_GEN2(dev)) {
6e3c9717 12851 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12852 int vtotal;
12853
12854 vtotal = mode->crtc_vtotal;
12855 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12856 vtotal /= 2;
12857
12858 crtc->scanline_offset = vtotal - 1;
12859 } else if (HAS_DDI(dev) &&
409ee761 12860 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12861 crtc->scanline_offset = 2;
12862 } else
12863 crtc->scanline_offset = 1;
12864}
12865
5cec258b 12866static struct intel_crtc_state *
7f27126e 12867intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12868 struct drm_atomic_state *state)
7f27126e 12869{
548ee15b 12870 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12871 int ret = 0;
12872
12873 ret = drm_atomic_add_affected_connectors(state, crtc);
12874 if (ret)
12875 return ERR_PTR(ret);
7f27126e 12876
8c7b5ccb
ACO		 12877 ret = drm_atomic_helper_check_modeset(state->dev, state);
12878 if (ret)
12879 return ERR_PTR(ret);
7f27126e 12880
7f27126e
JB		 12881 /*
12882 * Note this needs changes when we start tracking multiple modes
12883 * and crtcs. At that point we'll need to compute the whole config
12884 * (i.e. one pipe_config for each crtc) rather than just the one
12885 * for this crtc.
12886 */
548ee15b
ACO		 12887 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12888 if (IS_ERR(pipe_config))
12889 return pipe_config;
83a57153 12890
4fed33f6 12891 if (!pipe_config->base.enable)
548ee15b 12892 return pipe_config;
7f27126e 12893
8c7b5ccb 12894 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12895 if (ret)
12896 return ERR_PTR(ret);
12897
8d8c9b51
ACO		 12898 /* Check things that can only be changed through modeset */
12899 if (pipe_config->has_audio !=
12900 to_intel_crtc(crtc)->config->has_audio)
12901 pipe_config->base.mode_changed = true;
12902
12903 /*
12904 * Note we have an issue here with infoframes: current code
12905 * only updates them on the full mode set path per hw
12906 * requirements. So here we should be checking for any
12907 * required changes and forcing a mode set.
12908 */
12909
548ee15b 12910 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12911
8c7b5ccb
ACO		 12912 ret = drm_atomic_helper_check_planes(state->dev, state);
12913 if (ret)
12914 return ERR_PTR(ret);
12915
548ee15b 12916 return pipe_config;
7f27126e
JB		 12917}
12918
0a9ab303 12919static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12920{
225da59b 12921 struct drm_device *dev = state->dev;
ed6739ef 12922 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12923 unsigned clear_pipes = 0;
ed6739ef 12924 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12925 struct intel_crtc_state *intel_crtc_state;
12926 struct drm_crtc *crtc;
12927 struct drm_crtc_state *crtc_state;
ed6739ef 12928 int ret = 0;
0a9ab303 12929 int i;
ed6739ef
ACO		 12930
12931 if (!dev_priv->display.crtc_compute_clock)
12932 return 0;
12933
0a9ab303
ACO		 12934 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12935 intel_crtc = to_intel_crtc(crtc);
4978cc93 12936 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12937
4978cc93 12938 if (needs_modeset(crtc_state)) {
0a9ab303 12939 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12940 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12941 }
0a9ab303
ACO		 12942 }
12943
ed6739ef
ACO		 12944 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12945 if (ret)
12946 goto done;
12947
0a9ab303
ACO		 12948 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12949 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12950 continue;
12951
0a9ab303
ACO		 12952 intel_crtc = to_intel_crtc(crtc);
12953 intel_crtc_state = to_intel_crtc_state(crtc_state);
12954
ed6739ef 12955 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12956 intel_crtc_state);
ed6739ef
ACO		 12957 if (ret) {
12958 intel_shared_dpll_abort_config(dev_priv);
12959 goto done;
12960 }
12961 }
12962
12963done:
12964 return ret;
12965}
12966
054518dd
ACO		 12967/* Code that should eventually be part of atomic_check() */
12968static int __intel_set_mode_checks(struct drm_atomic_state *state)
12969{
12970 struct drm_device *dev = state->dev;
12971 int ret;
12972
12973 /*
12974 * See if the config requires any additional preparation, e.g.
12975 * to adjust global state with pipes off. We need to do this
12976 * here so we can get the modeset_pipe updated config for the new
12977 * mode set on this crtc. For other crtcs we need to use the
12978 * adjusted_mode bits in the crtc directly.
12979 */
b432e5cf
VS		 12980 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12981 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12982 ret = valleyview_modeset_global_pipes(state);
12983 else
12984 ret = broadwell_modeset_global_pipes(state);
12985
054518dd
ACO		 12986 if (ret)
12987 return ret;
12988 }
12989
12990 ret = __intel_set_mode_setup_plls(state);
12991 if (ret)
12992 return ret;
12993
12994 return 0;
12995}
12996
0a9ab303 12997static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12998 struct intel_crtc_state *pipe_config)
a6778b3c 12999{
0a9ab303 13000 struct drm_device *dev = modeset_crtc->dev;
fbee40df 13001 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 13002 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 13003 struct drm_crtc *crtc;
13004 struct drm_crtc_state *crtc_state;
c0c36b94 13005 int ret = 0;
0a9ab303 13006 int i;
a6778b3c 13007
054518dd
ACO		 13008 ret = __intel_set_mode_checks(state);
13009 if (ret < 0)
13010 return ret;
13011
d4afb8cc
ACO		 13012 ret = drm_atomic_helper_prepare_planes(dev, state);
13013 if (ret)
13014 return ret;
13015
0a9ab303
ACO		 13016 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13017 if (!needs_modeset(crtc_state))
13018 continue;
460da916 13019
0a9ab303
ACO		 13020 if (!crtc_state->enable) {
13021 intel_crtc_disable(crtc);
13022 } else if (crtc->state->enable) {
13023 intel_crtc_disable_planes(crtc);
13024 dev_priv->display.crtc_disable(crtc);
ce22dba9 13025 }
ea9d758d 13026 }
a6778b3c 13027
6c4c86f5
DV		 13028 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
13029 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 13030 *
13031 * Note we'll need to fix this up when we start tracking multiple
13032 * pipes; here we assume a single modeset_pipe and only track the
13033 * single crtc and mode.
f6e5b160 13034 */
0a9ab303 13035 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 13036 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 13037
13038 /*
13039 * Calculate and store various constants which
13040 * are later needed by vblank and swap-completion
13041 * timestamping. They are derived from true hwmode.
13042 */
0a9ab303 13043 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 13044 &pipe_config->base.adjusted_mode);
b8cecdf5 13045 }
7758a113 13046
ea9d758d
DV		 13047 /* Only after disabling all output pipelines that will be changed can we
13048 * update the the output configuration. */
0a9ab303 13049 intel_modeset_update_state(state);
f6e5b160 13050
a821fc46
ACO		 13051 /* The state has been swaped above, so state actually contains the
13052 * old state now. */
13053
304603f4 13054 modeset_update_crtc_power_domains(state);
47fab737 13055
d4afb8cc 13056 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 13057
13058 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13059 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 13060 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 13061 continue;
13062
13063 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 13064
0a9ab303
ACO		 13065 dev_priv->display.crtc_enable(crtc);
13066 intel_crtc_enable_planes(crtc);
80715b2f 13067 }
a6778b3c 13068
a6778b3c 13069 /* FIXME: add subpixel order */
83a57153 13070
d4afb8cc
ACO		 13071 drm_atomic_helper_cleanup_planes(dev, state);
13072
2bfb4627
ACO		 13073 drm_atomic_state_free(state);
13074
9eb45f22 13075 return 0;
f6e5b160
CW		 13076}
13077
0a9ab303 13078static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 13079 struct intel_crtc_state *pipe_config)
f30da187
DV		 13080{
13081 int ret;
13082
8c7b5ccb 13083 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 13084
13085 if (ret == 0)
13086 intel_modeset_check_state(crtc->dev);
13087
13088 return ret;
13089}
13090
7f27126e 13091static int intel_set_mode(struct drm_crtc *crtc,
83a57153 13092 struct drm_atomic_state *state)
7f27126e 13093{
5cec258b 13094 struct intel_crtc_state *pipe_config;
83a57153 13095 int ret = 0;
7f27126e 13096
8c7b5ccb 13097 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 13098 if (IS_ERR(pipe_config)) {
13099 ret = PTR_ERR(pipe_config);
13100 goto out;
13101 }
13102
8c7b5ccb 13103 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 13104 if (ret)
13105 goto out;
7f27126e 13106
83a57153
ACO		 13107out:
13108 return ret;
7f27126e
JB		 13109}
13110
c0c36b94
CW		 13111void intel_crtc_restore_mode(struct drm_crtc *crtc)
13112{
83a57153
ACO		 13113 struct drm_device *dev = crtc->dev;
13114 struct drm_atomic_state *state;
4be07317 13115 struct intel_crtc *intel_crtc;
83a57153
ACO		 13116 struct intel_encoder *encoder;
13117 struct intel_connector *connector;
13118 struct drm_connector_state *connector_state;
4be07317 13119 struct intel_crtc_state *crtc_state;
2bfb4627 13120 int ret;
83a57153
ACO		 13121
13122 state = drm_atomic_state_alloc(dev);
13123 if (!state) {
13124 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13125 crtc->base.id);
13126 return;
13127 }
13128
13129 state->acquire_ctx = dev->mode_config.acquire_ctx;
13130
13131 /* The force restore path in the HW readout code relies on the staged
13132 * config still keeping the user requested config while the actual
13133 * state has been overwritten by the configuration read from HW. We
13134 * need to copy the staged config to the atomic state, otherwise the
13135 * mode set will just reapply the state the HW is already in. */
13136 for_each_intel_encoder(dev, encoder) {
13137 if (&encoder->new_crtc->base != crtc)
13138 continue;
13139
13140 for_each_intel_connector(dev, connector) {
13141 if (connector->new_encoder != encoder)
13142 continue;
13143
13144 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13145 if (IS_ERR(connector_state)) {
13146 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13147 connector->base.base.id,
13148 connector->base.name,
13149 PTR_ERR(connector_state));
13150 continue;
13151 }
13152
13153 connector_state->crtc = crtc;
13154 connector_state->best_encoder = &encoder->base;
13155 }
13156 }
13157
4be07317
ACO		 13158 for_each_intel_crtc(dev, intel_crtc) {
13159 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13160 continue;
13161
13162 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13163 if (IS_ERR(crtc_state)) {
13164 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13165 intel_crtc->base.base.id,
13166 PTR_ERR(crtc_state));
13167 continue;
13168 }
13169
49d6fa21
ML		 13170 crtc_state->base.active = crtc_state->base.enable =
13171 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13172
13173 if (&intel_crtc->base == crtc)
13174 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13175 }
13176
d3a40d1b
ACO		 13177 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13178 crtc->primary->fb, crtc->x, crtc->y);
13179
2bfb4627
ACO		 13180 ret = intel_set_mode(crtc, state);
13181 if (ret)
13182 drm_atomic_state_free(state);
c0c36b94
CW		 13183}
13184
25c5b266
DV		 13185#undef for_each_intel_crtc_masked
13186
b7885264
ACO		 13187static bool intel_connector_in_mode_set(struct intel_connector *connector,
13188 struct drm_mode_set *set)
13189{
13190 int ro;
13191
13192 for (ro = 0; ro < set->num_connectors; ro++)
13193 if (set->connectors[ro] == &connector->base)
13194 return true;
13195
13196 return false;
13197}
13198
2e431051 13199static int
9a935856
DV		 13200intel_modeset_stage_output_state(struct drm_device *dev,
13201 struct drm_mode_set *set,
944b0c76 13202 struct drm_atomic_state *state)
50f56119 13203{
9a935856 13204 struct intel_connector *connector;
d5432a9d 13205 struct drm_connector *drm_connector;
944b0c76 13206 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13207 struct drm_crtc *crtc;
13208 struct drm_crtc_state *crtc_state;
13209 int i, ret;
50f56119 13210
9abdda74 13211 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13212 * of connectors. For paranoia, double-check this. */
13213 WARN_ON(!set->fb && (set->num_connectors != 0));
13214 WARN_ON(set->fb && (set->num_connectors == 0));
13215
3a3371ff 13216 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13217 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13218
d5432a9d
ACO		 13219 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13220 continue;
13221
13222 connector_state =
13223 drm_atomic_get_connector_state(state, &connector->base);
13224 if (IS_ERR(connector_state))
13225 return PTR_ERR(connector_state);
13226
b7885264
ACO		 13227 if (in_mode_set) {
13228 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13229 connector_state->best_encoder =
13230 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13231 }
13232
d5432a9d 13233 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13234 continue;
13235
9a935856
DV		 13236 /* If we disable the crtc, disable all its connectors. Also, if
13237 * the connector is on the changing crtc but not on the new
13238 * connector list, disable it. */
b7885264 13239 if (!set->fb || !in_mode_set) {
d5432a9d 13240 connector_state->best_encoder = NULL;
9a935856
DV		 13241
13242 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13243 connector->base.base.id,
c23cc417 13244 connector->base.name);
9a935856 13245 }
50f56119 13246 }
9a935856 13247 /* connector->new_encoder is now updated for all connectors. */
50f56119 13248
d5432a9d
ACO		 13249 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13250 connector = to_intel_connector(drm_connector);
13251
13252 if (!connector_state->best_encoder) {
13253 ret = drm_atomic_set_crtc_for_connector(connector_state,
13254 NULL);
13255 if (ret)
13256 return ret;
7668851f 13257
50f56119 13258 continue;
d5432a9d 13259 }
50f56119 13260
d5432a9d
ACO		 13261 if (intel_connector_in_mode_set(connector, set)) {
13262 struct drm_crtc *crtc = connector->base.state->crtc;
13263
13264 /* If this connector was in a previous crtc, add it
13265 * to the state. We might need to disable it. */
13266 if (crtc) {
13267 crtc_state =
13268 drm_atomic_get_crtc_state(state, crtc);
13269 if (IS_ERR(crtc_state))
13270 return PTR_ERR(crtc_state);
13271 }
13272
13273 ret = drm_atomic_set_crtc_for_connector(connector_state,
13274 set->crtc);
13275 if (ret)
13276 return ret;
13277 }
50f56119
DV		 13278
13279 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13280 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13281 connector_state->crtc)) {
5e2b584e 13282 return -EINVAL;
50f56119 13283 }
944b0c76 13284
9a935856
DV		 13285 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13286 connector->base.base.id,
c23cc417 13287 connector->base.name,
d5432a9d 13288 connector_state->crtc->base.id);
944b0c76 13289
d5432a9d
ACO		 13290 if (connector_state->best_encoder != &connector->encoder->base)
13291 connector->encoder =
13292 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13293 }
7668851f 13294
d5432a9d 13295 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13296 bool has_connectors;
13297
d5432a9d
ACO		 13298 ret = drm_atomic_add_affected_connectors(state, crtc);
13299 if (ret)
13300 return ret;
4be07317 13301
49d6fa21
ML		 13302 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13303 if (has_connectors != crtc_state->enable)
13304 crtc_state->enable =
13305 crtc_state->active = has_connectors;
7668851f
VS		 13306 }
13307
8c7b5ccb
ACO		 13308 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13309 set->fb, set->x, set->y);
13310 if (ret)
13311 return ret;
13312
13313 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13314 if (IS_ERR(crtc_state))
13315 return PTR_ERR(crtc_state);
13316
13317 if (set->mode)
13318 drm_mode_copy(&crtc_state->mode, set->mode);
13319
13320 if (set->num_connectors)
13321 crtc_state->active = true;
13322
2e431051
DV		 13323 return 0;
13324}
13325
bb546623
ACO		 13326static bool primary_plane_visible(struct drm_crtc *crtc)
13327{
13328 struct intel_plane_state *plane_state =
13329 to_intel_plane_state(crtc->primary->state);
13330
13331 return plane_state->visible;
13332}
13333
2e431051
DV		 13334static int intel_crtc_set_config(struct drm_mode_set *set)
13335{
13336 struct drm_device *dev;
83a57153 13337 struct drm_atomic_state *state = NULL;
5cec258b 13338 struct intel_crtc_state *pipe_config;
bb546623 13339 bool primary_plane_was_visible;
2e431051 13340 int ret;
2e431051 13341
8d3e375e
DV		 13342 BUG_ON(!set);
13343 BUG_ON(!set->crtc);
13344 BUG_ON(!set->crtc->helper_private);
2e431051 13345
7e53f3a4
DV		 13346 /* Enforce sane interface api - has been abused by the fb helper. */
13347 BUG_ON(!set->mode && set->fb);
13348 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13349
2e431051
DV		 13350 if (set->fb) {
13351 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13352 set->crtc->base.id, set->fb->base.id,
13353 (int)set->num_connectors, set->x, set->y);
13354 } else {
13355 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13356 }
13357
13358 dev = set->crtc->dev;
13359
83a57153 13360 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13361 if (!state)
13362 return -ENOMEM;
83a57153
ACO		 13363
13364 state->acquire_ctx = dev->mode_config.acquire_ctx;
13365
462a425a 13366 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13367 if (ret)
7cbf41d6 13368 goto out;
2e431051 13369
8c7b5ccb 13370 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13371 if (IS_ERR(pipe_config)) {
6ac0483b 13372 ret = PTR_ERR(pipe_config);
7cbf41d6 13373 goto out;
20664591 13374 }
50f52756 13375
1f9954d0
JB		 13376 intel_update_pipe_size(to_intel_crtc(set->crtc));
13377
bb546623
ACO		 13378 primary_plane_was_visible = primary_plane_visible(set->crtc);
13379
8c7b5ccb 13380 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13381
13382 if (ret == 0 &&
13383 pipe_config->base.enable &&
13384 pipe_config->base.planes_changed &&
13385 !needs_modeset(&pipe_config->base)) {
3b150f08 13386 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13387
13388 /*
13389 * We need to make sure the primary plane is re-enabled if it
13390 * has previously been turned off.
13391 */
bb546623
ACO		 13392 if (ret == 0 && !primary_plane_was_visible &&
13393 primary_plane_visible(set->crtc)) {
3b150f08 13394 WARN_ON(!intel_crtc->active);
87d4300a 13395 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13396 }
13397
7ca51a3a
JB		 13398 /*
13399 * In the fastboot case this may be our only check of the
13400 * state after boot. It would be better to only do it on
13401 * the first update, but we don't have a nice way of doing that
13402 * (and really, set_config isn't used much for high freq page
13403 * flipping, so increasing its cost here shouldn't be a big
13404 * deal).
13405 */
d330a953 13406 if (i915.fastboot && ret == 0)
7ca51a3a 13407 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13408 }
13409
2d05eae1 13410 if (ret) {
bf67dfeb
DV		 13411 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13412 set->crtc->base.id, ret);
2d05eae1 13413 }
50f56119 13414
7cbf41d6 13415out:
2bfb4627
ACO		 13416 if (ret)
13417 drm_atomic_state_free(state);
50f56119
DV		 13418 return ret;
13419}
f6e5b160
CW		 13420
13421static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13422 .gamma_set = intel_crtc_gamma_set,
50f56119 13423 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13424 .destroy = intel_crtc_destroy,
13425 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13426 .atomic_duplicate_state = intel_crtc_duplicate_state,
13427 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13428};
13429
5358901f
DV		 13430static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13431 struct intel_shared_dpll *pll,
13432 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13433{
5358901f 13434 uint32_t val;
ee7b9f93 13435
f458ebbc 13436 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13437 return false;
13438
5358901f 13439 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13440 hw_state->dpll = val;
13441 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13442 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13443
13444 return val & DPLL_VCO_ENABLE;
13445}
13446
15bdd4cf
DV		 13447static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13448 struct intel_shared_dpll *pll)
13449{
3e369b76
ACO		 13450 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13451 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13452}
13453
e7b903d2
DV		 13454static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13455 struct intel_shared_dpll *pll)
13456{
e7b903d2 13457 /* PCH refclock must be enabled first */
89eff4be 13458 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13459
3e369b76 13460 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13461
13462 /* Wait for the clocks to stabilize. */
13463 POSTING_READ(PCH_DPLL(pll->id));
13464 udelay(150);
13465
13466 /* The pixel multiplier can only be updated once the
13467 * DPLL is enabled and the clocks are stable.
13468 *
13469 * So write it again.
13470 */
3e369b76 13471 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13472 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13473 udelay(200);
13474}
13475
13476static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13477 struct intel_shared_dpll *pll)
13478{
13479 struct drm_device *dev = dev_priv->dev;
13480 struct intel_crtc *crtc;
e7b903d2
DV		 13481
13482 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13483 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13484 if (intel_crtc_to_shared_dpll(crtc) == pll)
13485 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13486 }
13487
15bdd4cf
DV		 13488 I915_WRITE(PCH_DPLL(pll->id), 0);
13489 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13490 udelay(200);
13491}
13492
46edb027
DV		 13493static char *ibx_pch_dpll_names[] = {
13494 "PCH DPLL A",
13495 "PCH DPLL B",
13496};
13497
7c74ade1 13498static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13499{
e7b903d2 13500 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13501 int i;
13502
7c74ade1 13503 dev_priv->num_shared_dpll = 2;
ee7b9f93 13504
e72f9fbf 13505 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13506 dev_priv->shared_dplls[i].id = i;
13507 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13508 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13509 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13510 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13511 dev_priv->shared_dplls[i].get_hw_state =
13512 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13513 }
13514}
13515
7c74ade1
DV		 13516static void intel_shared_dpll_init(struct drm_device *dev)
13517{
e7b903d2 13518 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13519
b6283055
VS		 13520 intel_update_cdclk(dev);
13521
9cd86933
DV		 13522 if (HAS_DDI(dev))
13523 intel_ddi_pll_init(dev);
13524 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13525 ibx_pch_dpll_init(dev);
13526 else
13527 dev_priv->num_shared_dpll = 0;
13528
13529 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13530}
13531
1fc0a8f7
TU		 13532/**
13533 * intel_wm_need_update - Check whether watermarks need updating
13534 * @plane: drm plane
13535 * @state: new plane state
13536 *
13537 * Check current plane state versus the new one to determine whether
13538 * watermarks need to be recalculated.
13539 *
13540 * Returns true or false.
13541 */
13542bool intel_wm_need_update(struct drm_plane *plane,
13543 struct drm_plane_state *state)
13544{
13545 /* Update watermarks on tiling changes. */
13546 if (!plane->state->fb || !state->fb ||
13547 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13548 plane->state->rotation != state->rotation)
13549 return true;
13550
13551 return false;
13552}
13553
6beb8c23
MR		 13554/**
13555 * intel_prepare_plane_fb - Prepare fb for usage on plane
13556 * @plane: drm plane to prepare for
13557 * @fb: framebuffer to prepare for presentation
13558 *
13559 * Prepares a framebuffer for usage on a display plane. Generally this
13560 * involves pinning the underlying object and updating the frontbuffer tracking
13561 * bits. Some older platforms need special physical address handling for
13562 * cursor planes.
13563 *
13564 * Returns 0 on success, negative error code on failure.
13565 */
13566int
13567intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13568 struct drm_framebuffer *fb,
13569 const struct drm_plane_state *new_state)
465c120c
MR		 13570{
13571 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13572 struct intel_plane *intel_plane = to_intel_plane(plane);
13573 enum pipe pipe = intel_plane->pipe;
13574 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13575 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13576 unsigned frontbuffer_bits = 0;
13577 int ret = 0;
465c120c 13578
ea2c67bb 13579 if (!obj)
465c120c
MR		 13580 return 0;
13581
6beb8c23
MR		 13582 switch (plane->type) {
13583 case DRM_PLANE_TYPE_PRIMARY:
13584 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13585 break;
13586 case DRM_PLANE_TYPE_CURSOR:
13587 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13588 break;
13589 case DRM_PLANE_TYPE_OVERLAY:
13590 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13591 break;
13592 }
465c120c 13593
6beb8c23 13594 mutex_lock(&dev->struct_mutex);
465c120c 13595
6beb8c23
MR		 13596 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13597 INTEL_INFO(dev)->cursor_needs_physical) {
13598 int align = IS_I830(dev) ? 16 * 1024 : 256;
13599 ret = i915_gem_object_attach_phys(obj, align);
13600 if (ret)
13601 DRM_DEBUG_KMS("failed to attach phys object\n");
13602 } else {
82bc3b2d 13603 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13604 }
465c120c 13605
6beb8c23
MR		 13606 if (ret == 0)
13607 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13608
4c34574f 13609 mutex_unlock(&dev->struct_mutex);
465c120c 13610
6beb8c23
MR		 13611 return ret;
13612}
13613
38f3ce3a
MR		 13614/**
13615 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13616 * @plane: drm plane to clean up for
13617 * @fb: old framebuffer that was on plane
13618 *
13619 * Cleans up a framebuffer that has just been removed from a plane.
13620 */
13621void
13622intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13623 struct drm_framebuffer *fb,
13624 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13625{
13626 struct drm_device *dev = plane->dev;
13627 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13628
13629 if (WARN_ON(!obj))
13630 return;
13631
13632 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13633 !INTEL_INFO(dev)->cursor_needs_physical) {
13634 mutex_lock(&dev->struct_mutex);
82bc3b2d 13635 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13636 mutex_unlock(&dev->struct_mutex);
13637 }
465c120c
MR		 13638}
13639
6156a456
CK		 13640int
13641skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13642{
13643 int max_scale;
13644 struct drm_device *dev;
13645 struct drm_i915_private *dev_priv;
13646 int crtc_clock, cdclk;
13647
13648 if (!intel_crtc || !crtc_state)
13649 return DRM_PLANE_HELPER_NO_SCALING;
13650
13651 dev = intel_crtc->base.dev;
13652 dev_priv = dev->dev_private;
13653 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13654 cdclk = dev_priv->display.get_display_clock_speed(dev);
13655
13656 if (!crtc_clock || !cdclk)
13657 return DRM_PLANE_HELPER_NO_SCALING;
13658
13659 /*
13660 * skl max scale is lower of:
13661 * close to 3 but not 3, -1 is for that purpose
13662 * or
13663 * cdclk/crtc_clock
13664 */
13665 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13666
13667 return max_scale;
13668}
13669
465c120c 13670static int
3c692a41
GP		 13671intel_check_primary_plane(struct drm_plane *plane,
13672 struct intel_plane_state *state)
13673{
32b7eeec
MR		 13674 struct drm_device *dev = plane->dev;
13675 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13676 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13677 struct intel_crtc *intel_crtc;
6156a456 13678 struct intel_crtc_state *crtc_state;
2b875c22 13679 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13680 struct drm_rect *dest = &state->dst;
13681 struct drm_rect *src = &state->src;
13682 const struct drm_rect *clip = &state->clip;
d8106366 13683 bool can_position = false;
6156a456
CK		 13684 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13685 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13686 int ret;
13687
ea2c67bb
MR		 13688 crtc = crtc ? crtc : plane->crtc;
13689 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13690 crtc_state = state->base.state ?
13691 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13692
6156a456 13693 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13694 /* use scaler when colorkey is not required */
13695 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13696 min_scale = 1;
13697 max_scale = skl_max_scale(intel_crtc, crtc_state);
13698 }
d8106366 13699 can_position = true;
6156a456 13700 }
d8106366 13701
c59cb179
MR		 13702 ret = drm_plane_helper_check_update(plane, crtc, fb,
13703 src, dest, clip,
6156a456
CK		 13704 min_scale,
13705 max_scale,
d8106366
SJ		 13706 can_position, true,
13707 &state->visible);
c59cb179
MR		 13708 if (ret)
13709 return ret;
465c120c 13710
32b7eeec 13711 if (intel_crtc->active) {
b70709a6
ML		 13712 struct intel_plane_state *old_state =
13713 to_intel_plane_state(plane->state);
13714
32b7eeec
MR		 13715 intel_crtc->atomic.wait_for_flips = true;
13716
13717 /*
13718 * FBC does not work on some platforms for rotated
13719 * planes, so disable it when rotation is not 0 and
13720 * update it when rotation is set back to 0.
13721 *
13722 * FIXME: This is redundant with the fbc update done in
13723 * the primary plane enable function except that that
13724 * one is done too late. We eventually need to unify
13725 * this.
13726 */
b70709a6 13727 if (state->visible &&
32b7eeec 13728 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13729 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13730 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13731 intel_crtc->atomic.disable_fbc = true;
13732 }
13733
b70709a6 13734 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13735 /*
13736 * BDW signals flip done immediately if the plane
13737 * is disabled, even if the plane enable is already
13738 * armed to occur at the next vblank :(
13739 */
b70709a6 13740 if (IS_BROADWELL(dev))
32b7eeec
MR		 13741 intel_crtc->atomic.wait_vblank = true;
13742 }
13743
13744 intel_crtc->atomic.fb_bits |=
13745 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13746
13747 intel_crtc->atomic.update_fbc = true;
0fda6568 13748
1fc0a8f7 13749 if (intel_wm_need_update(plane, &state->base))
0fda6568 13750 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13751 }
13752
6156a456
CK		 13753 if (INTEL_INFO(dev)->gen >= 9) {
13754 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13755 to_intel_plane(plane), state, 0);
13756 if (ret)
13757 return ret;
13758 }
13759
14af293f
GP		 13760 return 0;
13761}
13762
13763static void
13764intel_commit_primary_plane(struct drm_plane *plane,
13765 struct intel_plane_state *state)
13766{
2b875c22
MR		 13767 struct drm_crtc *crtc = state->base.crtc;
13768 struct drm_framebuffer *fb = state->base.fb;
13769 struct drm_device *dev = plane->dev;
14af293f 13770 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13771 struct intel_crtc *intel_crtc;
14af293f
GP		 13772 struct drm_rect *src = &state->src;
13773
ea2c67bb
MR		 13774 crtc = crtc ? crtc : plane->crtc;
13775 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13776
13777 plane->fb = fb;
9dc806fc
MR		 13778 crtc->x = src->x1 >> 16;
13779 crtc->y = src->y1 >> 16;
ccc759dc 13780
ccc759dc 13781 if (intel_crtc->active) {
27321ae8 13782 if (state->visible)
ccc759dc
GP		 13783 /* FIXME: kill this fastboot hack */
13784 intel_update_pipe_size(intel_crtc);
465c120c 13785
27321ae8
ML		 13786 dev_priv->display.update_primary_plane(crtc, plane->fb,
13787 crtc->x, crtc->y);
ccc759dc 13788 }
465c120c
MR		 13789}
13790
a8ad0d8e
ML		 13791static void
13792intel_disable_primary_plane(struct drm_plane *plane,
13793 struct drm_crtc *crtc,
13794 bool force)
13795{
13796 struct drm_device *dev = plane->dev;
13797 struct drm_i915_private *dev_priv = dev->dev_private;
13798
a8ad0d8e
ML		 13799 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13800}
13801
32b7eeec 13802static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13803{
32b7eeec 13804 struct drm_device *dev = crtc->dev;
140fd38d 13805 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13807 struct intel_plane *intel_plane;
13808 struct drm_plane *p;
13809 unsigned fb_bits = 0;
13810
13811 /* Track fb's for any planes being disabled */
13812 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13813 intel_plane = to_intel_plane(p);
13814
13815 if (intel_crtc->atomic.disabled_planes &
13816 (1 << drm_plane_index(p))) {
13817 switch (p->type) {
13818 case DRM_PLANE_TYPE_PRIMARY:
13819 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13820 break;
13821 case DRM_PLANE_TYPE_CURSOR:
13822 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13823 break;
13824 case DRM_PLANE_TYPE_OVERLAY:
13825 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13826 break;
13827 }
3c692a41 13828
ea2c67bb
MR		 13829 mutex_lock(&dev->struct_mutex);
13830 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13831 mutex_unlock(&dev->struct_mutex);
13832 }
13833 }
3c692a41 13834
32b7eeec
MR		 13835 if (intel_crtc->atomic.wait_for_flips)
13836 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13837
32b7eeec
MR		 13838 if (intel_crtc->atomic.disable_fbc)
13839 intel_fbc_disable(dev);
3c692a41 13840
32b7eeec
MR		 13841 if (intel_crtc->atomic.pre_disable_primary)
13842 intel_pre_disable_primary(crtc);
3c692a41 13843
32b7eeec
MR		 13844 if (intel_crtc->atomic.update_wm)
13845 intel_update_watermarks(crtc);
3c692a41 13846
32b7eeec 13847 intel_runtime_pm_get(dev_priv);
3c692a41 13848
c34c9ee4
MR		 13849 /* Perform vblank evasion around commit operation */
13850 if (intel_crtc->active)
13851 intel_crtc->atomic.evade =
13852 intel_pipe_update_start(intel_crtc,
13853 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13854}
13855
13856static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13857{
13858 struct drm_device *dev = crtc->dev;
13859 struct drm_i915_private *dev_priv = dev->dev_private;
13860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13861 struct drm_plane *p;
13862
c34c9ee4
MR		 13863 if (intel_crtc->atomic.evade)
13864 intel_pipe_update_end(intel_crtc,
13865 intel_crtc->atomic.start_vbl_count);
3c692a41 13866
140fd38d 13867 intel_runtime_pm_put(dev_priv);
3c692a41 13868
32b7eeec
MR		 13869 if (intel_crtc->atomic.wait_vblank)
13870 intel_wait_for_vblank(dev, intel_crtc->pipe);
13871
13872 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13873
13874 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13875 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13876 intel_fbc_update(dev);
ccc759dc 13877 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13878 }
3c692a41 13879
32b7eeec
MR		 13880 if (intel_crtc->atomic.post_enable_primary)
13881 intel_post_enable_primary(crtc);
3c692a41 13882
32b7eeec
MR		 13883 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13884 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13885 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13886 false, false);
13887
13888 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13889}
13890
cf4c7c12 13891/**
4a3b8769
MR		 13892 * intel_plane_destroy - destroy a plane
13893 * @plane: plane to destroy
cf4c7c12 13894 *
4a3b8769
MR		 13895 * Common destruction function for all types of planes (primary, cursor,
13896 * sprite).
cf4c7c12 13897 */
4a3b8769 13898void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13899{
13900 struct intel_plane *intel_plane = to_intel_plane(plane);
13901 drm_plane_cleanup(plane);
13902 kfree(intel_plane);
13903}
13904
65a3fea0 13905const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13906 .update_plane = drm_atomic_helper_update_plane,
13907 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13908 .destroy = intel_plane_destroy,
c196e1d6 13909 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13910 .atomic_get_property = intel_plane_atomic_get_property,
13911 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13912 .atomic_duplicate_state = intel_plane_duplicate_state,
13913 .atomic_destroy_state = intel_plane_destroy_state,
13914
465c120c
MR		 13915};
13916
13917static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13918 int pipe)
13919{
13920 struct intel_plane *primary;
8e7d688b 13921 struct intel_plane_state *state;
465c120c
MR		 13922 const uint32_t *intel_primary_formats;
13923 int num_formats;
13924
13925 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13926 if (primary == NULL)
13927 return NULL;
13928
8e7d688b
MR		 13929 state = intel_create_plane_state(&primary->base);
13930 if (!state) {
ea2c67bb
MR		 13931 kfree(primary);
13932 return NULL;
13933 }
8e7d688b 13934 primary->base.state = &state->base;
ea2c67bb 13935
465c120c
MR		 13936 primary->can_scale = false;
13937 primary->max_downscale = 1;
6156a456
CK		 13938 if (INTEL_INFO(dev)->gen >= 9) {
13939 primary->can_scale = true;
af99ceda 13940 state->scaler_id = -1;
6156a456 13941 }
465c120c
MR		 13942 primary->pipe = pipe;
13943 primary->plane = pipe;
c59cb179
MR		 13944 primary->check_plane = intel_check_primary_plane;
13945 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13946 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13947 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13948 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13949 primary->plane = !pipe;
13950
6c0fd451
DL		 13951 if (INTEL_INFO(dev)->gen >= 9) {
13952 intel_primary_formats = skl_primary_formats;
13953 num_formats = ARRAY_SIZE(skl_primary_formats);
13954 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13955 intel_primary_formats = i965_primary_formats;
13956 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13957 } else {
13958 intel_primary_formats = i8xx_primary_formats;
13959 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13960 }
13961
13962 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13963 &intel_plane_funcs,
465c120c
MR		 13964 intel_primary_formats, num_formats,
13965 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13966
3b7a5119
SJ		 13967 if (INTEL_INFO(dev)->gen >= 4)
13968 intel_create_rotation_property(dev, primary);
48404c1e 13969
ea2c67bb
MR		 13970 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13971
465c120c
MR		 13972 return &primary->base;
13973}
13974
3b7a5119
SJ		 13975void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13976{
13977 if (!dev->mode_config.rotation_property) {
13978 unsigned long flags = BIT(DRM_ROTATE_0) |
13979 BIT(DRM_ROTATE_180);
13980
13981 if (INTEL_INFO(dev)->gen >= 9)
13982 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13983
13984 dev->mode_config.rotation_property =
13985 drm_mode_create_rotation_property(dev, flags);
13986 }
13987 if (dev->mode_config.rotation_property)
13988 drm_object_attach_property(&plane->base.base,
13989 dev->mode_config.rotation_property,
13990 plane->base.state->rotation);
13991}
13992
3d7d6510 13993static int
852e787c
GP		 13994intel_check_cursor_plane(struct drm_plane *plane,
13995 struct intel_plane_state *state)
3d7d6510 13996{
2b875c22 13997 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13998 struct drm_device *dev = plane->dev;
2b875c22 13999 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 14000 struct drm_rect *dest = &state->dst;
14001 struct drm_rect *src = &state->src;
14002 const struct drm_rect *clip = &state->clip;
757f9a3e 14003 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 14004 struct intel_crtc *intel_crtc;
757f9a3e
GP		 14005 unsigned stride;
14006 int ret;
3d7d6510 14007
ea2c67bb
MR		 14008 crtc = crtc ? crtc : plane->crtc;
14009 intel_crtc = to_intel_crtc(crtc);
14010
757f9a3e 14011 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 14012 src, dest, clip,
3d7d6510
MR		 14013 DRM_PLANE_HELPER_NO_SCALING,
14014 DRM_PLANE_HELPER_NO_SCALING,
852e787c 14015 true, true, &state->visible);
757f9a3e
GP		 14016 if (ret)
14017 return ret;
14018
14019
14020 /* if we want to turn off the cursor ignore width and height */
14021 if (!obj)
32b7eeec 14022 goto finish;
757f9a3e 14023
757f9a3e 14024 /* Check for which cursor types we support */
ea2c67bb
MR		 14025 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
14026 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14027 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 14028 return -EINVAL;
14029 }
14030
ea2c67bb
MR		 14031 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14032 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 14033 DRM_DEBUG_KMS("buffer is too small\n");
14034 return -ENOMEM;
14035 }
14036
3a656b54 14037 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 14038 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14039 ret = -EINVAL;
14040 }
757f9a3e 14041
32b7eeec
MR		 14042finish:
14043 if (intel_crtc->active) {
3749f463 14044 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 14045 intel_crtc->atomic.update_wm = true;
14046
14047 intel_crtc->atomic.fb_bits |=
14048 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
14049 }
14050
757f9a3e 14051 return ret;
852e787c 14052}
3d7d6510 14053
a8ad0d8e
ML		 14054static void
14055intel_disable_cursor_plane(struct drm_plane *plane,
14056 struct drm_crtc *crtc,
14057 bool force)
14058{
14059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14060
14061 if (!force) {
14062 plane->fb = NULL;
14063 intel_crtc->cursor_bo = NULL;
14064 intel_crtc->cursor_addr = 0;
14065 }
14066
14067 intel_crtc_update_cursor(crtc, false);
14068}
14069
f4a2cf29 14070static void
852e787c
GP		 14071intel_commit_cursor_plane(struct drm_plane *plane,
14072 struct intel_plane_state *state)
14073{
2b875c22 14074 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 14075 struct drm_device *dev = plane->dev;
14076 struct intel_crtc *intel_crtc;
2b875c22 14077 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14078 uint32_t addr;
852e787c 14079
ea2c67bb
MR		 14080 crtc = crtc ? crtc : plane->crtc;
14081 intel_crtc = to_intel_crtc(crtc);
14082
2b875c22 14083 plane->fb = state->base.fb;
ea2c67bb
MR		 14084 crtc->cursor_x = state->base.crtc_x;
14085 crtc->cursor_y = state->base.crtc_y;
14086
a912f12f
GP		 14087 if (intel_crtc->cursor_bo == obj)
14088 goto update;
4ed91096 14089
f4a2cf29 14090 if (!obj)
a912f12f 14091 addr = 0;
f4a2cf29 14092 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14093 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14094 else
a912f12f 14095 addr = obj->phys_handle->busaddr;
852e787c 14096
a912f12f
GP		 14097 intel_crtc->cursor_addr = addr;
14098 intel_crtc->cursor_bo = obj;
14099update:
852e787c 14100
32b7eeec 14101 if (intel_crtc->active)
a912f12f 14102 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14103}
14104
3d7d6510
MR		 14105static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14106 int pipe)
14107{
14108 struct intel_plane *cursor;
8e7d688b 14109 struct intel_plane_state *state;
3d7d6510
MR		 14110
14111 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14112 if (cursor == NULL)
14113 return NULL;
14114
8e7d688b
MR		 14115 state = intel_create_plane_state(&cursor->base);
14116 if (!state) {
ea2c67bb
MR		 14117 kfree(cursor);
14118 return NULL;
14119 }
8e7d688b 14120 cursor->base.state = &state->base;
ea2c67bb 14121
3d7d6510
MR		 14122 cursor->can_scale = false;
14123 cursor->max_downscale = 1;
14124 cursor->pipe = pipe;
14125 cursor->plane = pipe;
c59cb179
MR		 14126 cursor->check_plane = intel_check_cursor_plane;
14127 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14128 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14129
14130 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14131 &intel_plane_funcs,
3d7d6510
MR		 14132 intel_cursor_formats,
14133 ARRAY_SIZE(intel_cursor_formats),
14134 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14135
14136 if (INTEL_INFO(dev)->gen >= 4) {
14137 if (!dev->mode_config.rotation_property)
14138 dev->mode_config.rotation_property =
14139 drm_mode_create_rotation_property(dev,
14140 BIT(DRM_ROTATE_0) |
14141 BIT(DRM_ROTATE_180));
14142 if (dev->mode_config.rotation_property)
14143 drm_object_attach_property(&cursor->base.base,
14144 dev->mode_config.rotation_property,
8e7d688b 14145 state->base.rotation);
4398ad45
VS		 14146 }
14147
af99ceda
CK		 14148 if (INTEL_INFO(dev)->gen >=9)
14149 state->scaler_id = -1;
14150
ea2c67bb
MR		 14151 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14152
3d7d6510
MR		 14153 return &cursor->base;
14154}
14155
549e2bfb
CK		 14156static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14157 struct intel_crtc_state *crtc_state)
14158{
14159 int i;
14160 struct intel_scaler *intel_scaler;
14161 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14162
14163 for (i = 0; i < intel_crtc->num_scalers; i++) {
14164 intel_scaler = &scaler_state->scalers[i];
14165 intel_scaler->in_use = 0;
14166 intel_scaler->id = i;
14167
14168 intel_scaler->mode = PS_SCALER_MODE_DYN;
14169 }
14170
14171 scaler_state->scaler_id = -1;
14172}
14173
b358d0a6 14174static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14175{
fbee40df 14176 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14177 struct intel_crtc *intel_crtc;
f5de6e07 14178 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14179 struct drm_plane *primary = NULL;
14180 struct drm_plane *cursor = NULL;
465c120c 14181 int i, ret;
79e53945 14182
955382f3 14183 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14184 if (intel_crtc == NULL)
14185 return;
14186
f5de6e07
ACO		 14187 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14188 if (!crtc_state)
14189 goto fail;
550acefd
ACO		 14190 intel_crtc->config = crtc_state;
14191 intel_crtc->base.state = &crtc_state->base;
07878248 14192 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14193
549e2bfb
CK		 14194 /* initialize shared scalers */
14195 if (INTEL_INFO(dev)->gen >= 9) {
14196 if (pipe == PIPE_C)
14197 intel_crtc->num_scalers = 1;
14198 else
14199 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14200
14201 skl_init_scalers(dev, intel_crtc, crtc_state);
14202 }
14203
465c120c 14204 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14205 if (!primary)
14206 goto fail;
14207
14208 cursor = intel_cursor_plane_create(dev, pipe);
14209 if (!cursor)
14210 goto fail;
14211
465c120c 14212 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14213 cursor, &intel_crtc_funcs);
14214 if (ret)
14215 goto fail;
79e53945
JB		 14216
14217 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14218 for (i = 0; i < 256; i++) {
14219 intel_crtc->lut_r[i] = i;
14220 intel_crtc->lut_g[i] = i;
14221 intel_crtc->lut_b[i] = i;
14222 }
14223
1f1c2e24
VS		 14224 /*
14225 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14226 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14227 */
80824003
JB		 14228 intel_crtc->pipe = pipe;
14229 intel_crtc->plane = pipe;
3a77c4c4 14230 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14231 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14232 intel_crtc->plane = !pipe;
80824003
JB		 14233 }
14234
4b0e333e
CW		 14235 intel_crtc->cursor_base = ~0;
14236 intel_crtc->cursor_cntl = ~0;
dc41c154 14237 intel_crtc->cursor_size = ~0;
8d7849db 14238
22fd0fab
JB		 14239 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14240 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14241 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14242 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14243
79e53945 14244 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14245
14246 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14247 return;
14248
14249fail:
14250 if (primary)
14251 drm_plane_cleanup(primary);
14252 if (cursor)
14253 drm_plane_cleanup(cursor);
f5de6e07 14254 kfree(crtc_state);
3d7d6510 14255 kfree(intel_crtc);
79e53945
JB		 14256}
14257
752aa88a
JB		 14258enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14259{
14260 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14261 struct drm_device *dev = connector->base.dev;
752aa88a 14262
51fd371b 14263 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14264
d3babd3f 14265 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14266 return INVALID_PIPE;
14267
14268 return to_intel_crtc(encoder->crtc)->pipe;
14269}
14270
08d7b3d1 14271int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14272 struct drm_file *file)
08d7b3d1 14273{
08d7b3d1 14274 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14275 struct drm_crtc *drmmode_crtc;
c05422d5 14276 struct intel_crtc *crtc;
08d7b3d1 14277
7707e653 14278 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14279
7707e653 14280 if (!drmmode_crtc) {
08d7b3d1 14281 DRM_ERROR("no such CRTC id\n");
3f2c2057 14282 return -ENOENT;
08d7b3d1
CW		 14283 }
14284
7707e653 14285 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14286 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14287
c05422d5 14288 return 0;
08d7b3d1
CW		 14289}
14290
66a9278e 14291static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14292{
66a9278e
DV		 14293 struct drm_device *dev = encoder->base.dev;
14294 struct intel_encoder *source_encoder;
79e53945 14295 int index_mask = 0;
79e53945
JB		 14296 int entry = 0;
14297
b2784e15 14298 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14299 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14300 index_mask |= (1 << entry);
14301
79e53945
JB		 14302 entry++;
14303 }
4ef69c7a 14304
79e53945
JB		 14305 return index_mask;
14306}
14307
4d302442
CW		 14308static bool has_edp_a(struct drm_device *dev)
14309{
14310 struct drm_i915_private *dev_priv = dev->dev_private;
14311
14312 if (!IS_MOBILE(dev))
14313 return false;
14314
14315 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14316 return false;
14317
e3589908 14318 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14319 return false;
14320
14321 return true;
14322}
14323
84b4e042
JB		 14324static bool intel_crt_present(struct drm_device *dev)
14325{
14326 struct drm_i915_private *dev_priv = dev->dev_private;
14327
884497ed
DL		 14328 if (INTEL_INFO(dev)->gen >= 9)
14329 return false;
14330
cf404ce4 14331 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14332 return false;
14333
14334 if (IS_CHERRYVIEW(dev))
14335 return false;
14336
14337 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14338 return false;
14339
14340 return true;
14341}
14342
79e53945
JB		 14343static void intel_setup_outputs(struct drm_device *dev)
14344{
725e30ad 14345 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14346 struct intel_encoder *encoder;
cb0953d7 14347 bool dpd_is_edp = false;
79e53945 14348
c9093354 14349 intel_lvds_init(dev);
79e53945 14350
84b4e042 14351 if (intel_crt_present(dev))
79935fca 14352 intel_crt_init(dev);
cb0953d7 14353
c776eb2e
VK		 14354 if (IS_BROXTON(dev)) {
14355 /*
14356 * FIXME: Broxton doesn't support port detection via the
14357 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14358 * detect the ports.
14359 */
14360 intel_ddi_init(dev, PORT_A);
14361 intel_ddi_init(dev, PORT_B);
14362 intel_ddi_init(dev, PORT_C);
14363 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14364 int found;
14365
de31facd
JB		 14366 /*
14367 * Haswell uses DDI functions to detect digital outputs.
14368 * On SKL pre-D0 the strap isn't connected, so we assume
14369 * it's there.
14370 */
0e72a5b5 14371 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14372 /* WaIgnoreDDIAStrap: skl */
14373 if (found ||
14374 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14375 intel_ddi_init(dev, PORT_A);
14376
14377 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14378 * register */
14379 found = I915_READ(SFUSE_STRAP);
14380
14381 if (found & SFUSE_STRAP_DDIB_DETECTED)
14382 intel_ddi_init(dev, PORT_B);
14383 if (found & SFUSE_STRAP_DDIC_DETECTED)
14384 intel_ddi_init(dev, PORT_C);
14385 if (found & SFUSE_STRAP_DDID_DETECTED)
14386 intel_ddi_init(dev, PORT_D);
14387 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14388 int found;
5d8a7752 14389 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14390
14391 if (has_edp_a(dev))
14392 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14393
dc0fa718 14394 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14395 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14396 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14397 if (!found)
e2debe91 14398 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14399 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14400 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14401 }
14402
dc0fa718 14403 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14404 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14405
dc0fa718 14406 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14407 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14408
5eb08b69 14409 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14410 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14411
270b3042 14412 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14413 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14414 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14415 /*
14416 * The DP_DETECTED bit is the latched state of the DDC
14417 * SDA pin at boot. However since eDP doesn't require DDC
14418 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14419 * eDP ports may have been muxed to an alternate function.
14420 * Thus we can't rely on the DP_DETECTED bit alone to detect
14421 * eDP ports. Consult the VBT as well as DP_DETECTED to
14422 * detect eDP ports.
14423 */
d2182a66
VS		 14424 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14425 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14426 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14427 PORT_B);
e17ac6db
VS		 14428 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14429 intel_dp_is_edp(dev, PORT_B))
14430 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14431
d2182a66
VS		 14432 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14433 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14434 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14435 PORT_C);
e17ac6db
VS		 14436 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14437 intel_dp_is_edp(dev, PORT_C))
14438 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14439
9418c1f1 14440 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14441 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14442 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14443 PORT_D);
e17ac6db
VS		 14444 /* eDP not supported on port D, so don't check VBT */
14445 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14446 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14447 }
14448
3cfca973 14449 intel_dsi_init(dev);
103a196f 14450 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14451 bool found = false;
7d57382e 14452
e2debe91 14453 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14454 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14455 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14456 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14457 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14458 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14459 }
27185ae1 14460
e7281eab 14461 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14462 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14463 }
13520b05
KH		 14464
14465 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14466
e2debe91 14467 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14468 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14469 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14470 }
27185ae1 14471
e2debe91 14472 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14473
b01f2c3a
JB		 14474 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14475 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14476 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14477 }
e7281eab 14478 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14479 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14480 }
27185ae1 14481
b01f2c3a 14482 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14483 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14484 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14485 } else if (IS_GEN2(dev))
79e53945
JB		 14486 intel_dvo_init(dev);
14487
103a196f 14488 if (SUPPORTS_TV(dev))
79e53945
JB		 14489 intel_tv_init(dev);
14490
0bc12bcb 14491 intel_psr_init(dev);
7c8f8a70 14492
b2784e15 14493 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14494 encoder->base.possible_crtcs = encoder->crtc_mask;
14495 encoder->base.possible_clones =
66a9278e 14496 intel_encoder_clones(encoder);
79e53945 14497 }
47356eb6 14498
dde86e2d 14499 intel_init_pch_refclk(dev);
270b3042
DV		 14500
14501 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14502}
14503
14504static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14505{
60a5ca01 14506 struct drm_device *dev = fb->dev;
79e53945 14507 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14508
ef2d633e 14509 drm_framebuffer_cleanup(fb);
60a5ca01 14510 mutex_lock(&dev->struct_mutex);
ef2d633e 14511 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14512 drm_gem_object_unreference(&intel_fb->obj->base);
14513 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14514 kfree(intel_fb);
14515}
14516
14517static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14518 struct drm_file *file,
79e53945
JB		 14519 unsigned int *handle)
14520{
14521 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14522 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14523
05394f39 14524 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14525}
14526
14527static const struct drm_framebuffer_funcs intel_fb_funcs = {
14528 .destroy = intel_user_framebuffer_destroy,
14529 .create_handle = intel_user_framebuffer_create_handle,
14530};
14531
b321803d
DL		 14532static
14533u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14534 uint32_t pixel_format)
14535{
14536 u32 gen = INTEL_INFO(dev)->gen;
14537
14538 if (gen >= 9) {
14539 /* "The stride in bytes must not exceed the of the size of 8K
14540 * pixels and 32K bytes."
14541 */
14542 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14543 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14544 return 32*1024;
14545 } else if (gen >= 4) {
14546 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14547 return 16*1024;
14548 else
14549 return 32*1024;
14550 } else if (gen >= 3) {
14551 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14552 return 8*1024;
14553 else
14554 return 16*1024;
14555 } else {
14556 /* XXX DSPC is limited to 4k tiled */
14557 return 8*1024;
14558 }
14559}
14560
b5ea642a
DV		 14561static int intel_framebuffer_init(struct drm_device *dev,
14562 struct intel_framebuffer *intel_fb,
14563 struct drm_mode_fb_cmd2 *mode_cmd,
14564 struct drm_i915_gem_object *obj)
79e53945 14565{
6761dd31 14566 unsigned int aligned_height;
79e53945 14567 int ret;
b321803d 14568 u32 pitch_limit, stride_alignment;
79e53945 14569
dd4916c5
DV		 14570 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14571
2a80eada
DV		 14572 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14573 /* Enforce that fb modifier and tiling mode match, but only for
14574 * X-tiled. This is needed for FBC. */
14575 if (!!(obj->tiling_mode == I915_TILING_X) !=
14576 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14577 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14578 return -EINVAL;
14579 }
14580 } else {
14581 if (obj->tiling_mode == I915_TILING_X)
14582 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14583 else if (obj->tiling_mode == I915_TILING_Y) {
14584 DRM_DEBUG("No Y tiling for legacy addfb\n");
14585 return -EINVAL;
14586 }
14587 }
14588
9a8f0a12
TU		 14589 /* Passed in modifier sanity checking. */
14590 switch (mode_cmd->modifier[0]) {
14591 case I915_FORMAT_MOD_Y_TILED:
14592 case I915_FORMAT_MOD_Yf_TILED:
14593 if (INTEL_INFO(dev)->gen < 9) {
14594 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14595 mode_cmd->modifier[0]);
14596 return -EINVAL;
14597 }
14598 case DRM_FORMAT_MOD_NONE:
14599 case I915_FORMAT_MOD_X_TILED:
14600 break;
14601 default:
c0f40428
JB		 14602 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14603 mode_cmd->modifier[0]);
57cd6508 14604 return -EINVAL;
c16ed4be 14605 }
57cd6508 14606
b321803d
DL		 14607 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14608 mode_cmd->pixel_format);
14609 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14610 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14611 mode_cmd->pitches[0], stride_alignment);
57cd6508 14612 return -EINVAL;
c16ed4be 14613 }
57cd6508 14614
b321803d
DL		 14615 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14616 mode_cmd->pixel_format);
a35cdaa0 14617 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14618 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14619 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14620 "tiled" : "linear",
a35cdaa0 14621 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14622 return -EINVAL;
c16ed4be 14623 }
5d7bd705 14624
2a80eada 14625 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14626 mode_cmd->pitches[0] != obj->stride) {
14627 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14628 mode_cmd->pitches[0], obj->stride);
5d7bd705 14629 return -EINVAL;
c16ed4be 14630 }
5d7bd705 14631
57779d06 14632 /* Reject formats not supported by any plane early. */
308e5bcb 14633 switch (mode_cmd->pixel_format) {
57779d06 14634 case DRM_FORMAT_C8:
04b3924d
VS		 14635 case DRM_FORMAT_RGB565:
14636 case DRM_FORMAT_XRGB8888:
14637 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14638 break;
14639 case DRM_FORMAT_XRGB1555:
c16ed4be 14640 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14641 DRM_DEBUG("unsupported pixel format: %s\n",
14642 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14643 return -EINVAL;
c16ed4be 14644 }
57779d06 14645 break;
57779d06 14646 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14647 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14648 DRM_DEBUG("unsupported pixel format: %s\n",
14649 drm_get_format_name(mode_cmd->pixel_format));
14650 return -EINVAL;
14651 }
14652 break;
14653 case DRM_FORMAT_XBGR8888:
04b3924d 14654 case DRM_FORMAT_XRGB2101010:
57779d06 14655 case DRM_FORMAT_XBGR2101010:
c16ed4be 14656 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14657 DRM_DEBUG("unsupported pixel format: %s\n",
14658 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14659 return -EINVAL;
c16ed4be 14660 }
b5626747 14661 break;
7531208b
DL		 14662 case DRM_FORMAT_ABGR2101010:
14663 if (!IS_VALLEYVIEW(dev)) {
14664 DRM_DEBUG("unsupported pixel format: %s\n",
14665 drm_get_format_name(mode_cmd->pixel_format));
14666 return -EINVAL;
14667 }
14668 break;
04b3924d
VS		 14669 case DRM_FORMAT_YUYV:
14670 case DRM_FORMAT_UYVY:
14671 case DRM_FORMAT_YVYU:
14672 case DRM_FORMAT_VYUY:
c16ed4be 14673 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14674 DRM_DEBUG("unsupported pixel format: %s\n",
14675 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14676 return -EINVAL;
c16ed4be 14677 }
57cd6508
CW		 14678 break;
14679 default:
4ee62c76
VS		 14680 DRM_DEBUG("unsupported pixel format: %s\n",
14681 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14682 return -EINVAL;
14683 }
14684
90f9a336
VS		 14685 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14686 if (mode_cmd->offsets[0] != 0)
14687 return -EINVAL;
14688
ec2c981e 14689 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14690 mode_cmd->pixel_format,
14691 mode_cmd->modifier[0]);
53155c0a
DV		 14692 /* FIXME drm helper for size checks (especially planar formats)? */
14693 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14694 return -EINVAL;
14695
c7d73f6a
DV		 14696 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14697 intel_fb->obj = obj;
80075d49 14698 intel_fb->obj->framebuffer_references++;
c7d73f6a 14699
79e53945
JB		 14700 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14701 if (ret) {
14702 DRM_ERROR("framebuffer init failed %d\n", ret);
14703 return ret;
14704 }
14705
79e53945
JB		 14706 return 0;
14707}
14708
79e53945
JB		 14709static struct drm_framebuffer *
14710intel_user_framebuffer_create(struct drm_device *dev,
14711 struct drm_file *filp,
308e5bcb 14712 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14713{
05394f39 14714 struct drm_i915_gem_object *obj;
79e53945 14715
308e5bcb
JB		 14716 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14717 mode_cmd->handles[0]));
c8725226 14718 if (&obj->base == NULL)
cce13ff7 14719 return ERR_PTR(-ENOENT);
79e53945 14720
d2dff872 14721 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14722}
14723
4520f53a 14724#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14725static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14726{
14727}
14728#endif
14729
79e53945 14730static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14731 .fb_create = intel_user_framebuffer_create,
0632fef6 14732 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14733 .atomic_check = intel_atomic_check,
14734 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14735};
14736
e70236a8
JB		 14737/* Set up chip specific display functions */
14738static void intel_init_display(struct drm_device *dev)
14739{
14740 struct drm_i915_private *dev_priv = dev->dev_private;
14741
ee9300bb
DV		 14742 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14743 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14744 else if (IS_CHERRYVIEW(dev))
14745 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14746 else if (IS_VALLEYVIEW(dev))
14747 dev_priv->display.find_dpll = vlv_find_best_dpll;
14748 else if (IS_PINEVIEW(dev))
14749 dev_priv->display.find_dpll = pnv_find_best_dpll;
14750 else
14751 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14752
bc8d7dff
DL		 14753 if (INTEL_INFO(dev)->gen >= 9) {
14754 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14755 dev_priv->display.get_initial_plane_config =
14756 skylake_get_initial_plane_config;
bc8d7dff
DL		 14757 dev_priv->display.crtc_compute_clock =
14758 haswell_crtc_compute_clock;
14759 dev_priv->display.crtc_enable = haswell_crtc_enable;
14760 dev_priv->display.crtc_disable = haswell_crtc_disable;
14761 dev_priv->display.off = ironlake_crtc_off;
14762 dev_priv->display.update_primary_plane =
14763 skylake_update_primary_plane;
14764 } else if (HAS_DDI(dev)) {
0e8ffe1b 14765 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14766 dev_priv->display.get_initial_plane_config =
14767 ironlake_get_initial_plane_config;
797d0259
ACO		 14768 dev_priv->display.crtc_compute_clock =
14769 haswell_crtc_compute_clock;
4f771f10
PZ		 14770 dev_priv->display.crtc_enable = haswell_crtc_enable;
14771 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14772 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14773 dev_priv->display.update_primary_plane =
14774 ironlake_update_primary_plane;
09b4ddf9 14775 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14776 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14777 dev_priv->display.get_initial_plane_config =
14778 ironlake_get_initial_plane_config;
3fb37703
ACO		 14779 dev_priv->display.crtc_compute_clock =
14780 ironlake_crtc_compute_clock;
76e5a89c
DV		 14781 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14782 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14783 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14784 dev_priv->display.update_primary_plane =
14785 ironlake_update_primary_plane;
89b667f8
JB		 14786 } else if (IS_VALLEYVIEW(dev)) {
14787 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14788 dev_priv->display.get_initial_plane_config =
14789 i9xx_get_initial_plane_config;
d6dfee7a 14790 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14791 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14792 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14793 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14794 dev_priv->display.update_primary_plane =
14795 i9xx_update_primary_plane;
f564048e 14796 } else {
0e8ffe1b 14797 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14798 dev_priv->display.get_initial_plane_config =
14799 i9xx_get_initial_plane_config;
d6dfee7a 14800 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14801 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14802 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14803 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14804 dev_priv->display.update_primary_plane =
14805 i9xx_update_primary_plane;
f564048e 14806 }
e70236a8 14807
e70236a8 14808 /* Returns the core display clock speed */
1652d19e
VS		 14809 if (IS_SKYLAKE(dev))
14810 dev_priv->display.get_display_clock_speed =
14811 skylake_get_display_clock_speed;
14812 else if (IS_BROADWELL(dev))
14813 dev_priv->display.get_display_clock_speed =
14814 broadwell_get_display_clock_speed;
14815 else if (IS_HASWELL(dev))
14816 dev_priv->display.get_display_clock_speed =
14817 haswell_get_display_clock_speed;
14818 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14819 dev_priv->display.get_display_clock_speed =
14820 valleyview_get_display_clock_speed;
b37a6434
VS		 14821 else if (IS_GEN5(dev))
14822 dev_priv->display.get_display_clock_speed =
14823 ilk_get_display_clock_speed;
a7c66cd8 14824 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14825 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14826 dev_priv->display.get_display_clock_speed =
14827 i945_get_display_clock_speed;
34edce2f
VS		 14828 else if (IS_GM45(dev))
14829 dev_priv->display.get_display_clock_speed =
14830 gm45_get_display_clock_speed;
14831 else if (IS_CRESTLINE(dev))
14832 dev_priv->display.get_display_clock_speed =
14833 i965gm_get_display_clock_speed;
14834 else if (IS_PINEVIEW(dev))
14835 dev_priv->display.get_display_clock_speed =
14836 pnv_get_display_clock_speed;
14837 else if (IS_G33(dev) || IS_G4X(dev))
14838 dev_priv->display.get_display_clock_speed =
14839 g33_get_display_clock_speed;
e70236a8
JB		 14840 else if (IS_I915G(dev))
14841 dev_priv->display.get_display_clock_speed =
14842 i915_get_display_clock_speed;
257a7ffc 14843 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14844 dev_priv->display.get_display_clock_speed =
14845 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14846 else if (IS_PINEVIEW(dev))
14847 dev_priv->display.get_display_clock_speed =
14848 pnv_get_display_clock_speed;
e70236a8
JB		 14849 else if (IS_I915GM(dev))
14850 dev_priv->display.get_display_clock_speed =
14851 i915gm_get_display_clock_speed;
14852 else if (IS_I865G(dev))
14853 dev_priv->display.get_display_clock_speed =
14854 i865_get_display_clock_speed;
f0f8a9ce 14855 else if (IS_I85X(dev))
e70236a8 14856 dev_priv->display.get_display_clock_speed =
1b1d2716 14857 i85x_get_display_clock_speed;
623e01e5
VS		 14858 else { /* 830 */
14859 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14860 dev_priv->display.get_display_clock_speed =
14861 i830_get_display_clock_speed;
623e01e5 14862 }
e70236a8 14863
7c10a2b5 14864 if (IS_GEN5(dev)) {
3bb11b53 14865 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14866 } else if (IS_GEN6(dev)) {
14867 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14868 } else if (IS_IVYBRIDGE(dev)) {
14869 /* FIXME: detect B0+ stepping and use auto training */
14870 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14871 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14872 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14873 if (IS_BROADWELL(dev))
14874 dev_priv->display.modeset_global_resources =
14875 broadwell_modeset_global_resources;
30a970c6
JB		 14876 } else if (IS_VALLEYVIEW(dev)) {
14877 dev_priv->display.modeset_global_resources =
14878 valleyview_modeset_global_resources;
f8437dd1
VK		 14879 } else if (IS_BROXTON(dev)) {
14880 dev_priv->display.modeset_global_resources =
14881 broxton_modeset_global_resources;
e70236a8 14882 }
8c9f3aaf 14883
8c9f3aaf
JB		 14884 switch (INTEL_INFO(dev)->gen) {
14885 case 2:
14886 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14887 break;
14888
14889 case 3:
14890 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14891 break;
14892
14893 case 4:
14894 case 5:
14895 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14896 break;
14897
14898 case 6:
14899 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14900 break;
7c9017e5 14901 case 7:
4e0bbc31 14902 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14903 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14904 break;
830c81db 14905 case 9:
ba343e02
TU		 14906 /* Drop through - unsupported since execlist only. */
14907 default:
14908 /* Default just returns -ENODEV to indicate unsupported */
14909 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14910 }
7bd688cd
JN		 14911
14912 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14913
14914 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14915}
14916
b690e96c
JB		 14917/*
14918 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14919 * resume, or other times. This quirk makes sure that's the case for
14920 * affected systems.
14921 */
0206e353 14922static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14923{
14924 struct drm_i915_private *dev_priv = dev->dev_private;
14925
14926 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14927 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14928}
14929
b6b5d049
VS		 14930static void quirk_pipeb_force(struct drm_device *dev)
14931{
14932 struct drm_i915_private *dev_priv = dev->dev_private;
14933
14934 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14935 DRM_INFO("applying pipe b force quirk\n");
14936}
14937
435793df
KP		 14938/*
14939 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14940 */
14941static void quirk_ssc_force_disable(struct drm_device *dev)
14942{
14943 struct drm_i915_private *dev_priv = dev->dev_private;
14944 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14945 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14946}
14947
4dca20ef 14948/*
5a15ab5b
CE		 14949 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14950 * brightness value
4dca20ef
CE		 14951 */
14952static void quirk_invert_brightness(struct drm_device *dev)
14953{
14954 struct drm_i915_private *dev_priv = dev->dev_private;
14955 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14956 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14957}
14958
9c72cc6f
SD		 14959/* Some VBT's incorrectly indicate no backlight is present */
14960static void quirk_backlight_present(struct drm_device *dev)
14961{
14962 struct drm_i915_private *dev_priv = dev->dev_private;
14963 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14964 DRM_INFO("applying backlight present quirk\n");
14965}
14966
b690e96c
JB		 14967struct intel_quirk {
14968 int device;
14969 int subsystem_vendor;
14970 int subsystem_device;
14971 void (*hook)(struct drm_device *dev);
14972};
14973
5f85f176
EE		 14974/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14975struct intel_dmi_quirk {
14976 void (*hook)(struct drm_device *dev);
14977 const struct dmi_system_id (*dmi_id_list)[];
14978};
14979
14980static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14981{
14982 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14983 return 1;
14984}
14985
14986static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14987 {
14988 .dmi_id_list = &(const struct dmi_system_id[]) {
14989 {
14990 .callback = intel_dmi_reverse_brightness,
14991 .ident = "NCR Corporation",
14992 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14993 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14994 },
14995 },
14996 { } /* terminating entry */
14997 },
14998 .hook = quirk_invert_brightness,
14999 },
15000};
15001
c43b5634 15002static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 15003 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15004 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15005
b690e96c
JB		 15006 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15007 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15008
5f080c0f
VS		 15009 /* 830 needs to leave pipe A & dpll A up */
15010 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15011
b6b5d049
VS		 15012 /* 830 needs to leave pipe B & dpll B up */
15013 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15014
435793df
KP		 15015 /* Lenovo U160 cannot use SSC on LVDS */
15016 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 15017
15018 /* Sony Vaio Y cannot use SSC on LVDS */
15019 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 15020
be505f64
AH		 15021 /* Acer Aspire 5734Z must invert backlight brightness */
15022 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15023
15024 /* Acer/eMachines G725 */
15025 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15026
15027 /* Acer/eMachines e725 */
15028 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15029
15030 /* Acer/Packard Bell NCL20 */
15031 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15032
15033 /* Acer Aspire 4736Z */
15034 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 15035
15036 /* Acer Aspire 5336 */
15037 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 15038
15039 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15040 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 15041
dfb3d47b
SD		 15042 /* Acer C720 Chromebook (Core i3 4005U) */
15043 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15044
b2a9601c 15045 /* Apple Macbook 2,1 (Core 2 T7400) */
15046 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15047
d4967d8c
SD		 15048 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15049 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 15050
15051 /* HP Chromebook 14 (Celeron 2955U) */
15052 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 15053
15054 /* Dell Chromebook 11 */
15055 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 15056};
15057
15058static void intel_init_quirks(struct drm_device *dev)
15059{
15060 struct pci_dev *d = dev->pdev;
15061 int i;
15062
15063 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15064 struct intel_quirk *q = &intel_quirks[i];
15065
15066 if (d->device == q->device &&
15067 (d->subsystem_vendor == q->subsystem_vendor ||
15068 q->subsystem_vendor == PCI_ANY_ID) &&
15069 (d->subsystem_device == q->subsystem_device ||
15070 q->subsystem_device == PCI_ANY_ID))
15071 q->hook(dev);
15072 }
5f85f176
EE		 15073 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15074 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15075 intel_dmi_quirks[i].hook(dev);
15076 }
b690e96c
JB		 15077}
15078
9cce37f4
JB		 15079/* Disable the VGA plane that we never use */
15080static void i915_disable_vga(struct drm_device *dev)
15081{
15082 struct drm_i915_private *dev_priv = dev->dev_private;
15083 u8 sr1;
766aa1c4 15084 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15085
2b37c616 15086 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15087 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15088 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15089 sr1 = inb(VGA_SR_DATA);
15090 outb(sr1 | 1<<5, VGA_SR_DATA);
15091 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15092 udelay(300);
15093
01f5a626 15094 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15095 POSTING_READ(vga_reg);
15096}
15097
f817586c
DV		 15098void intel_modeset_init_hw(struct drm_device *dev)
15099{
b6283055 15100 intel_update_cdclk(dev);
a8f78b58 15101 intel_prepare_ddi(dev);
f817586c 15102 intel_init_clock_gating(dev);
8090c6b9 15103 intel_enable_gt_powersave(dev);
f817586c
DV		 15104}
15105
79e53945
JB		 15106void intel_modeset_init(struct drm_device *dev)
15107{
652c393a 15108 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15109 int sprite, ret;
8cc87b75 15110 enum pipe pipe;
46f297fb 15111 struct intel_crtc *crtc;
79e53945
JB		 15112
15113 drm_mode_config_init(dev);
15114
15115 dev->mode_config.min_width = 0;
15116 dev->mode_config.min_height = 0;
15117
019d96cb
DA		 15118 dev->mode_config.preferred_depth = 24;
15119 dev->mode_config.prefer_shadow = 1;
15120
25bab385
TU		 15121 dev->mode_config.allow_fb_modifiers = true;
15122
e6ecefaa 15123 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15124
b690e96c
JB		 15125 intel_init_quirks(dev);
15126
1fa61106
ED		 15127 intel_init_pm(dev);
15128
e3c74757
BW		 15129 if (INTEL_INFO(dev)->num_pipes == 0)
15130 return;
15131
e70236a8 15132 intel_init_display(dev);
7c10a2b5 15133 intel_init_audio(dev);
e70236a8 15134
a6c45cf0
CW		 15135 if (IS_GEN2(dev)) {
15136 dev->mode_config.max_width = 2048;
15137 dev->mode_config.max_height = 2048;
15138 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15139 dev->mode_config.max_width = 4096;
15140 dev->mode_config.max_height = 4096;
79e53945 15141 } else {
a6c45cf0
CW		 15142 dev->mode_config.max_width = 8192;
15143 dev->mode_config.max_height = 8192;
79e53945 15144 }
068be561 15145
dc41c154
VS		 15146 if (IS_845G(dev) || IS_I865G(dev)) {
15147 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15148 dev->mode_config.cursor_height = 1023;
15149 } else if (IS_GEN2(dev)) {
068be561
DL		 15150 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15151 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15152 } else {
15153 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15154 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15155 }
15156
5d4545ae 15157 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15158
28c97730 15159 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15160 INTEL_INFO(dev)->num_pipes,
15161 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15162
055e393f 15163 for_each_pipe(dev_priv, pipe) {
8cc87b75 15164 intel_crtc_init(dev, pipe);
3bdcfc0c 15165 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15166 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15167 if (ret)
06da8da2 15168 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15169 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15170 }
79e53945
JB		 15171 }
15172
f42bb70d
JB		 15173 intel_init_dpio(dev);
15174
e72f9fbf 15175 intel_shared_dpll_init(dev);
ee7b9f93 15176
9cce37f4
JB		 15177 /* Just disable it once at startup */
15178 i915_disable_vga(dev);
79e53945 15179 intel_setup_outputs(dev);
11be49eb
CW		 15180
15181 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15182 intel_fbc_disable(dev);
fa9fa083 15183
6e9f798d 15184 drm_modeset_lock_all(dev);
fa9fa083 15185 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15186 drm_modeset_unlock_all(dev);
46f297fb 15187
d3fcc808 15188 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15189 if (!crtc->active)
15190 continue;
15191
46f297fb 15192 /*
46f297fb
JB		 15193 * Note that reserving the BIOS fb up front prevents us
15194 * from stuffing other stolen allocations like the ring
15195 * on top. This prevents some ugliness at boot time, and
15196 * can even allow for smooth boot transitions if the BIOS
15197 * fb is large enough for the active pipe configuration.
15198 */
5724dbd1
DL		 15199 if (dev_priv->display.get_initial_plane_config) {
15200 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15201 &crtc->plane_config);
15202 /*
15203 * If the fb is shared between multiple heads, we'll
15204 * just get the first one.
15205 */
f6936e29 15206 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15207 }
46f297fb 15208 }
2c7111db
CW		 15209}
15210
7fad798e
DV		 15211static void intel_enable_pipe_a(struct drm_device *dev)
15212{
15213 struct intel_connector *connector;
15214 struct drm_connector *crt = NULL;
15215 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15216 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15217
15218 /* We can't just switch on the pipe A, we need to set things up with a
15219 * proper mode and output configuration. As a gross hack, enable pipe A
15220 * by enabling the load detect pipe once. */
3a3371ff 15221 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15222 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15223 crt = &connector->base;
15224 break;
15225 }
15226 }
15227
15228 if (!crt)
15229 return;
15230
208bf9fd 15231 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15232 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15233}
15234
fa555837
DV		 15235static bool
15236intel_check_plane_mapping(struct intel_crtc *crtc)
15237{
7eb552ae
BW		 15238 struct drm_device *dev = crtc->base.dev;
15239 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15240 u32 reg, val;
15241
7eb552ae 15242 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15243 return true;
15244
15245 reg = DSPCNTR(!crtc->plane);
15246 val = I915_READ(reg);
15247
15248 if ((val & DISPLAY_PLANE_ENABLE) &&
15249 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15250 return false;
15251
15252 return true;
15253}
15254
24929352
DV		 15255static void intel_sanitize_crtc(struct intel_crtc *crtc)
15256{
15257 struct drm_device *dev = crtc->base.dev;
15258 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15259 u32 reg;
24929352 15260
24929352 15261 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15262 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15263 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15264
d3eaf884 15265 /* restore vblank interrupts to correct state */
9625604c 15266 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15267 if (crtc->active) {
15268 update_scanline_offset(crtc);
9625604c
DV		 15269 drm_crtc_vblank_on(&crtc->base);
15270 }
d3eaf884 15271
24929352 15272 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15273 * disable the crtc (and hence change the state) if it is wrong. Note
15274 * that gen4+ has a fixed plane -> pipe mapping. */
15275 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15276 struct intel_connector *connector;
15277 bool plane;
15278
24929352
DV		 15279 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15280 crtc->base.base.id);
15281
15282 /* Pipe has the wrong plane attached and the plane is active.
15283 * Temporarily change the plane mapping and disable everything
15284 * ... */
15285 plane = crtc->plane;
b70709a6 15286 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15287 crtc->plane = !plane;
ce22dba9 15288 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 15289 dev_priv->display.crtc_disable(&crtc->base);
15290 crtc->plane = plane;
15291
15292 /* ... and break all links. */
3a3371ff 15293 for_each_intel_connector(dev, connector) {
24929352
DV		 15294 if (connector->encoder->base.crtc != &crtc->base)
15295 continue;
15296
7f1950fb
EE		 15297 connector->base.dpms = DRM_MODE_DPMS_OFF;
15298 connector->base.encoder = NULL;
24929352 15299 }
7f1950fb
EE		 15300 /* multiple connectors may have the same encoder:
15301 * handle them and break crtc link separately */
3a3371ff 15302 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15303 if (connector->encoder->base.crtc == &crtc->base) {
15304 connector->encoder->base.crtc = NULL;
15305 connector->encoder->connectors_active = false;
15306 }
24929352
DV		 15307
15308 WARN_ON(crtc->active);
83d65738 15309 crtc->base.state->enable = false;
49d6fa21 15310 crtc->base.state->active = false;
24929352
DV		 15311 crtc->base.enabled = false;
15312 }
24929352 15313
7fad798e
DV		 15314 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15315 crtc->pipe == PIPE_A && !crtc->active) {
15316 /* BIOS forgot to enable pipe A, this mostly happens after
15317 * resume. Force-enable the pipe to fix this, the update_dpms
15318 * call below we restore the pipe to the right state, but leave
15319 * the required bits on. */
15320 intel_enable_pipe_a(dev);
15321 }
15322
24929352
DV		 15323 /* Adjust the state of the output pipe according to whether we
15324 * have active connectors/encoders. */
15325 intel_crtc_update_dpms(&crtc->base);
15326
83d65738 15327 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15328 struct intel_encoder *encoder;
15329
15330 /* This can happen either due to bugs in the get_hw_state
15331 * functions or because the pipe is force-enabled due to the
15332 * pipe A quirk. */
15333 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15334 crtc->base.base.id,
83d65738 15335 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15336 crtc->active ? "enabled" : "disabled");
15337
83d65738 15338 crtc->base.state->enable = crtc->active;
49d6fa21 15339 crtc->base.state->active = crtc->active;
24929352
DV		 15340 crtc->base.enabled = crtc->active;
15341
15342 /* Because we only establish the connector -> encoder ->
15343 * crtc links if something is active, this means the
15344 * crtc is now deactivated. Break the links. connector
15345 * -> encoder links are only establish when things are
15346 * actually up, hence no need to break them. */
15347 WARN_ON(crtc->active);
15348
15349 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15350 WARN_ON(encoder->connectors_active);
15351 encoder->base.crtc = NULL;
15352 }
15353 }
c5ab3bc0 15354
a3ed6aad 15355 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15356 /*
15357 * We start out with underrun reporting disabled to avoid races.
15358 * For correct bookkeeping mark this on active crtcs.
15359 *
c5ab3bc0
DV		 15360 * Also on gmch platforms we dont have any hardware bits to
15361 * disable the underrun reporting. Which means we need to start
15362 * out with underrun reporting disabled also on inactive pipes,
15363 * since otherwise we'll complain about the garbage we read when
15364 * e.g. coming up after runtime pm.
15365 *
4cc31489
DV		 15366 * No protection against concurrent access is required - at
15367 * worst a fifo underrun happens which also sets this to false.
15368 */
15369 crtc->cpu_fifo_underrun_disabled = true;
15370 crtc->pch_fifo_underrun_disabled = true;
15371 }
24929352
DV		 15372}
15373
15374static void intel_sanitize_encoder(struct intel_encoder *encoder)
15375{
15376 struct intel_connector *connector;
15377 struct drm_device *dev = encoder->base.dev;
15378
15379 /* We need to check both for a crtc link (meaning that the
15380 * encoder is active and trying to read from a pipe) and the
15381 * pipe itself being active. */
15382 bool has_active_crtc = encoder->base.crtc &&
15383 to_intel_crtc(encoder->base.crtc)->active;
15384
15385 if (encoder->connectors_active && !has_active_crtc) {
15386 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15387 encoder->base.base.id,
8e329a03 15388 encoder->base.name);
24929352
DV		 15389
15390 /* Connector is active, but has no active pipe. This is
15391 * fallout from our resume register restoring. Disable
15392 * the encoder manually again. */
15393 if (encoder->base.crtc) {
15394 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15395 encoder->base.base.id,
8e329a03 15396 encoder->base.name);
24929352 15397 encoder->disable(encoder);
a62d1497
VS		 15398 if (encoder->post_disable)
15399 encoder->post_disable(encoder);
24929352 15400 }
7f1950fb
EE		 15401 encoder->base.crtc = NULL;
15402 encoder->connectors_active = false;
24929352
DV		 15403
15404 /* Inconsistent output/port/pipe state happens presumably due to
15405 * a bug in one of the get_hw_state functions. Or someplace else
15406 * in our code, like the register restore mess on resume. Clamp
15407 * things to off as a safer default. */
3a3371ff 15408 for_each_intel_connector(dev, connector) {
24929352
DV		 15409 if (connector->encoder != encoder)
15410 continue;
7f1950fb
EE		 15411 connector->base.dpms = DRM_MODE_DPMS_OFF;
15412 connector->base.encoder = NULL;
24929352
DV		 15413 }
15414 }
15415 /* Enabled encoders without active connectors will be fixed in
15416 * the crtc fixup. */
15417}
15418
04098753 15419void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15420{
15421 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15422 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15423
04098753
ID		 15424 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15425 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15426 i915_disable_vga(dev);
15427 }
15428}
15429
15430void i915_redisable_vga(struct drm_device *dev)
15431{
15432 struct drm_i915_private *dev_priv = dev->dev_private;
15433
8dc8a27c
PZ		 15434 /* This function can be called both from intel_modeset_setup_hw_state or
15435 * at a very early point in our resume sequence, where the power well
15436 * structures are not yet restored. Since this function is at a very
15437 * paranoid "someone might have enabled VGA while we were not looking"
15438 * level, just check if the power well is enabled instead of trying to
15439 * follow the "don't touch the power well if we don't need it" policy
15440 * the rest of the driver uses. */
f458ebbc 15441 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15442 return;
15443
04098753 15444 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15445}
15446
98ec7739
VS		 15447static bool primary_get_hw_state(struct intel_crtc *crtc)
15448{
15449 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15450
15451 if (!crtc->active)
15452 return false;
15453
15454 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15455}
15456
30e984df 15457static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15458{
15459 struct drm_i915_private *dev_priv = dev->dev_private;
15460 enum pipe pipe;
24929352
DV		 15461 struct intel_crtc *crtc;
15462 struct intel_encoder *encoder;
15463 struct intel_connector *connector;
5358901f 15464 int i;
24929352 15465
d3fcc808 15466 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15467 struct drm_plane *primary = crtc->base.primary;
15468 struct intel_plane_state *plane_state;
15469
6e3c9717 15470 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15471
6e3c9717 15472 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15473
0e8ffe1b 15474 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15475 crtc->config);
24929352 15476
83d65738 15477 crtc->base.state->enable = crtc->active;
49d6fa21 15478 crtc->base.state->active = crtc->active;
24929352 15479 crtc->base.enabled = crtc->active;
b70709a6
ML		 15480
15481 plane_state = to_intel_plane_state(primary->state);
15482 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15483
15484 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15485 crtc->base.base.id,
15486 crtc->active ? "enabled" : "disabled");
15487 }
15488
5358901f
DV		 15489 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15490 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15491
3e369b76
ACO		 15492 pll->on = pll->get_hw_state(dev_priv, pll,
15493 &pll->config.hw_state);
5358901f 15494 pll->active = 0;
3e369b76 15495 pll->config.crtc_mask = 0;
d3fcc808 15496 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15497 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15498 pll->active++;
3e369b76 15499 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15500 }
5358901f 15501 }
5358901f 15502
1e6f2ddc 15503 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15504 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15505
3e369b76 15506 if (pll->config.crtc_mask)
bd2bb1b9 15507 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15508 }
15509
b2784e15 15510 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15511 pipe = 0;
15512
15513 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15514 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15515 encoder->base.crtc = &crtc->base;
6e3c9717 15516 encoder->get_config(encoder, crtc->config);
24929352
DV		 15517 } else {
15518 encoder->base.crtc = NULL;
15519 }
15520
15521 encoder->connectors_active = false;
6f2bcceb 15522 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15523 encoder->base.base.id,
8e329a03 15524 encoder->base.name,
24929352 15525 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15526 pipe_name(pipe));
24929352
DV		 15527 }
15528
3a3371ff 15529 for_each_intel_connector(dev, connector) {
24929352
DV		 15530 if (connector->get_hw_state(connector)) {
15531 connector->base.dpms = DRM_MODE_DPMS_ON;
15532 connector->encoder->connectors_active = true;
15533 connector->base.encoder = &connector->encoder->base;
15534 } else {
15535 connector->base.dpms = DRM_MODE_DPMS_OFF;
15536 connector->base.encoder = NULL;
15537 }
15538 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15539 connector->base.base.id,
c23cc417 15540 connector->base.name,
24929352
DV		 15541 connector->base.encoder ? "enabled" : "disabled");
15542 }
30e984df
DV		 15543}
15544
15545/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15546 * and i915 state tracking structures. */
15547void intel_modeset_setup_hw_state(struct drm_device *dev,
15548 bool force_restore)
15549{
15550 struct drm_i915_private *dev_priv = dev->dev_private;
15551 enum pipe pipe;
30e984df
DV		 15552 struct intel_crtc *crtc;
15553 struct intel_encoder *encoder;
35c95375 15554 int i;
30e984df
DV		 15555
15556 intel_modeset_readout_hw_state(dev);
24929352 15557
babea61d
JB		 15558 /*
15559 * Now that we have the config, copy it to each CRTC struct
15560 * Note that this could go away if we move to using crtc_config
15561 * checking everywhere.
15562 */
d3fcc808 15563 for_each_intel_crtc(dev, crtc) {
d330a953 15564 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15565 intel_mode_from_pipe_config(&crtc->base.mode,
15566 crtc->config);
babea61d
JB		 15567 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15568 crtc->base.base.id);
15569 drm_mode_debug_printmodeline(&crtc->base.mode);
15570 }
15571 }
15572
24929352 15573 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15574 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15575 intel_sanitize_encoder(encoder);
15576 }
15577
055e393f 15578 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15579 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15580 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15581 intel_dump_pipe_config(crtc, crtc->config,
15582 "[setup_hw_state]");
24929352 15583 }
9a935856 15584
d29b2f9d
ACO		 15585 intel_modeset_update_connector_atomic_state(dev);
15586
35c95375
DV		 15587 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15588 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15589
15590 if (!pll->on || pll->active)
15591 continue;
15592
15593 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15594
15595 pll->disable(dev_priv, pll);
15596 pll->on = false;
15597 }
15598
3078999f
PB		 15599 if (IS_GEN9(dev))
15600 skl_wm_get_hw_state(dev);
15601 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15602 ilk_wm_get_hw_state(dev);
15603
45e2b5f6 15604 if (force_restore) {
7d0bc1ea
VS		 15605 i915_redisable_vga(dev);
15606
f30da187
DV		 15607 /*
15608 * We need to use raw interfaces for restoring state to avoid
15609 * checking (bogus) intermediate states.
15610 */
055e393f 15611 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15612 struct drm_crtc *crtc =
15613 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15614
83a57153 15615 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15616 }
15617 } else {
15618 intel_modeset_update_staged_output_state(dev);
15619 }
8af6cf88
DV		 15620
15621 intel_modeset_check_state(dev);
2c7111db
CW		 15622}
15623
15624void intel_modeset_gem_init(struct drm_device *dev)
15625{
92122789 15626 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15627 struct drm_crtc *c;
2ff8fde1 15628 struct drm_i915_gem_object *obj;
e0d6149b 15629 int ret;
484b41dd 15630
ae48434c
ID		 15631 mutex_lock(&dev->struct_mutex);
15632 intel_init_gt_powersave(dev);
15633 mutex_unlock(&dev->struct_mutex);
15634
92122789
JB		 15635 /*
15636 * There may be no VBT; and if the BIOS enabled SSC we can
15637 * just keep using it to avoid unnecessary flicker. Whereas if the
15638 * BIOS isn't using it, don't assume it will work even if the VBT
15639 * indicates as much.
15640 */
15641 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15642 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15643 DREF_SSC1_ENABLE);
15644
1833b134 15645 intel_modeset_init_hw(dev);
02e792fb
DV		 15646
15647 intel_setup_overlay(dev);
484b41dd
JB		 15648
15649 /*
15650 * Make sure any fbs we allocated at startup are properly
15651 * pinned & fenced. When we do the allocation it's too early
15652 * for this.
15653 */
70e1e0ec 15654 for_each_crtc(dev, c) {
2ff8fde1
MR		 15655 obj = intel_fb_obj(c->primary->fb);
15656 if (obj == NULL)
484b41dd
JB		 15657 continue;
15658
e0d6149b
TU		 15659 mutex_lock(&dev->struct_mutex);
15660 ret = intel_pin_and_fence_fb_obj(c->primary,
15661 c->primary->fb,
15662 c->primary->state,
15663 NULL);
15664 mutex_unlock(&dev->struct_mutex);
15665 if (ret) {
484b41dd
JB		 15666 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15667 to_intel_crtc(c)->pipe);
66e514c1
DA		 15668 drm_framebuffer_unreference(c->primary->fb);
15669 c->primary->fb = NULL;
afd65eb4 15670 update_state_fb(c->primary);
484b41dd
JB		 15671 }
15672 }
0962c3c9
VS		 15673
15674 intel_backlight_register(dev);
79e53945
JB		 15675}
15676
4932e2c3
ID		 15677void intel_connector_unregister(struct intel_connector *intel_connector)
15678{
15679 struct drm_connector *connector = &intel_connector->base;
15680
15681 intel_panel_destroy_backlight(connector);
34ea3d38 15682 drm_connector_unregister(connector);
4932e2c3
ID		 15683}
15684
79e53945
JB		 15685void intel_modeset_cleanup(struct drm_device *dev)
15686{
652c393a 15687 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15688 struct drm_connector *connector;
652c393a 15689
2eb5252e
ID		 15690 intel_disable_gt_powersave(dev);
15691
0962c3c9
VS		 15692 intel_backlight_unregister(dev);
15693
fd0c0642
DV		 15694 /*
15695 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15696 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15697 * experience fancy races otherwise.
15698 */
2aeb7d3a 15699 intel_irq_uninstall(dev_priv);
eb21b92b 15700
fd0c0642
DV		 15701 /*
15702 * Due to the hpd irq storm handling the hotplug work can re-arm the
15703 * poll handlers. Hence disable polling after hpd handling is shut down.
15704 */
f87ea761 15705 drm_kms_helper_poll_fini(dev);
fd0c0642 15706
652c393a
JB		 15707 mutex_lock(&dev->struct_mutex);
15708
723bfd70
JB		 15709 intel_unregister_dsm_handler();
15710
7ff0ebcc 15711 intel_fbc_disable(dev);
e70236a8 15712
69341a5e
KH		 15713 mutex_unlock(&dev->struct_mutex);
15714
1630fe75
CW		 15715 /* flush any delayed tasks or pending work */
15716 flush_scheduled_work();
15717
db31af1d
JN		 15718 /* destroy the backlight and sysfs files before encoders/connectors */
15719 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15720 struct intel_connector *intel_connector;
15721
15722 intel_connector = to_intel_connector(connector);
15723 intel_connector->unregister(intel_connector);
db31af1d 15724 }
d9255d57 15725
79e53945 15726 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15727
15728 intel_cleanup_overlay(dev);
ae48434c
ID		 15729
15730 mutex_lock(&dev->struct_mutex);
15731 intel_cleanup_gt_powersave(dev);
15732 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15733}
15734
f1c79df3
ZW		 15735/*
15736 * Return which encoder is currently attached for connector.
15737 */
df0e9248 15738struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15739{
df0e9248
CW		 15740 return &intel_attached_encoder(connector)->base;
15741}
f1c79df3 15742
df0e9248
CW		 15743void intel_connector_attach_encoder(struct intel_connector *connector,
15744 struct intel_encoder *encoder)
15745{
15746 connector->encoder = encoder;
15747 drm_mode_connector_attach_encoder(&connector->base,
15748 &encoder->base);
79e53945 15749}
28d52043
DA		 15750
15751/*
15752 * set vga decode state - true == enable VGA decode
15753 */
15754int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15755{
15756 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15757 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15758 u16 gmch_ctrl;
15759
75fa041d
CW		 15760 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15761 DRM_ERROR("failed to read control word\n");
15762 return -EIO;
15763 }
15764
c0cc8a55
CW		 15765 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15766 return 0;
15767
28d52043
DA		 15768 if (state)
15769 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15770 else
15771 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15772
15773 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15774 DRM_ERROR("failed to write control word\n");
15775 return -EIO;
15776 }
15777
28d52043
DA		 15778 return 0;
15779}
c4a1d9e4 15780
c4a1d9e4 15781struct intel_display_error_state {
ff57f1b0
PZ		 15782
15783 u32 power_well_driver;
15784
63b66e5b
CW		 15785 int num_transcoders;
15786
c4a1d9e4
CW		 15787 struct intel_cursor_error_state {
15788 u32 control;
15789 u32 position;
15790 u32 base;
15791 u32 size;
52331309 15792 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15793
15794 struct intel_pipe_error_state {
ddf9c536 15795 bool power_domain_on;
c4a1d9e4 15796 u32 source;
f301b1e1 15797 u32 stat;
52331309 15798 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15799
15800 struct intel_plane_error_state {
15801 u32 control;
15802 u32 stride;
15803 u32 size;
15804 u32 pos;
15805 u32 addr;
15806 u32 surface;
15807 u32 tile_offset;
52331309 15808 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15809
15810 struct intel_transcoder_error_state {
ddf9c536 15811 bool power_domain_on;
63b66e5b
CW		 15812 enum transcoder cpu_transcoder;
15813
15814 u32 conf;
15815
15816 u32 htotal;
15817 u32 hblank;
15818 u32 hsync;
15819 u32 vtotal;
15820 u32 vblank;
15821 u32 vsync;
15822 } transcoder[4];
c4a1d9e4
CW		 15823};
15824
15825struct intel_display_error_state *
15826intel_display_capture_error_state(struct drm_device *dev)
15827{
fbee40df 15828 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15829 struct intel_display_error_state *error;
63b66e5b
CW		 15830 int transcoders[] = {
15831 TRANSCODER_A,
15832 TRANSCODER_B,
15833 TRANSCODER_C,
15834 TRANSCODER_EDP,
15835 };
c4a1d9e4
CW		 15836 int i;
15837
63b66e5b
CW		 15838 if (INTEL_INFO(dev)->num_pipes == 0)
15839 return NULL;
15840
9d1cb914 15841 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15842 if (error == NULL)
15843 return NULL;
15844
190be112 15845 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15846 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15847
055e393f 15848 for_each_pipe(dev_priv, i) {
ddf9c536 15849 error->pipe[i].power_domain_on =
f458ebbc
DV		 15850 __intel_display_power_is_enabled(dev_priv,
15851 POWER_DOMAIN_PIPE(i));
ddf9c536 15852 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15853 continue;
15854
5efb3e28
VS		 15855 error->cursor[i].control = I915_READ(CURCNTR(i));
15856 error->cursor[i].position = I915_READ(CURPOS(i));
15857 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15858
15859 error->plane[i].control = I915_READ(DSPCNTR(i));
15860 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15861 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15862 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15863 error->plane[i].pos = I915_READ(DSPPOS(i));
15864 }
ca291363
PZ		 15865 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15866 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15867 if (INTEL_INFO(dev)->gen >= 4) {
15868 error->plane[i].surface = I915_READ(DSPSURF(i));
15869 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15870 }
15871
c4a1d9e4 15872 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15873
3abfce77 15874 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15875 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15876 }
15877
15878 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15879 if (HAS_DDI(dev_priv->dev))
15880 error->num_transcoders++; /* Account for eDP. */
15881
15882 for (i = 0; i < error->num_transcoders; i++) {
15883 enum transcoder cpu_transcoder = transcoders[i];
15884
ddf9c536 15885 error->transcoder[i].power_domain_on =
f458ebbc 15886 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15887 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15888 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15889 continue;
15890
63b66e5b
CW		 15891 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15892
15893 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15894 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15895 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15896 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15897 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15898 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15899 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15900 }
15901
15902 return error;
15903}
15904
edc3d884
MK		 15905#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15906
c4a1d9e4 15907void
edc3d884 15908intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15909 struct drm_device *dev,
15910 struct intel_display_error_state *error)
15911{
055e393f 15912 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15913 int i;
15914
63b66e5b
CW		 15915 if (!error)
15916 return;
15917
edc3d884 15918 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15919 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15920 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15921 error->power_well_driver);
055e393f 15922 for_each_pipe(dev_priv, i) {
edc3d884 15923 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15924 err_printf(m, " Power: %s\n",
15925 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15926 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15927 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15928
15929 err_printf(m, "Plane [%d]:\n", i);
15930 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15931 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15932 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15933 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15934 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15935 }
4b71a570 15936 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15937 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15938 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15939 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15940 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15941 }
15942
edc3d884
MK		 15943 err_printf(m, "Cursor [%d]:\n", i);
15944 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15945 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15946 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15947 }
63b66e5b
CW		 15948
15949 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15950 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15951 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15952 err_printf(m, " Power: %s\n",
15953 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15954 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15955 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15956 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15957 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15958 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15959 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15960 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15961 }
c4a1d9e4 15962}
e2fcdaa9
VS		 15963
15964void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15965{
15966 struct intel_crtc *crtc;
15967
15968 for_each_intel_crtc(dev, crtc) {
15969 struct intel_unpin_work *work;
e2fcdaa9 15970
5e2d7afc 15971 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15972
15973 work = crtc->unpin_work;
15974
15975 if (work && work->event &&
15976 work->event->base.file_priv == file) {
15977 kfree(work->event);
15978 work->event = NULL;
15979 }
15980
5e2d7afc 15981 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15982 }
15983}
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