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drm/i915: Set mode_changed for audio in intel_modeset_pipe_config()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
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79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
cdba954e
ACO		 434static bool
435needs_modeset(struct drm_crtc_state *state)
436{
437 return state->mode_changed || state->active_changed;
438}
439
e0638cdf
PZ		 440/**
441 * Returns whether any output on the specified pipe is of the specified type
442 */
4093561b 443bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 444{
409ee761 445 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 446 struct intel_encoder *encoder;
447
409ee761 448 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 449 if (encoder->type == type)
450 return true;
451
452 return false;
453}
454
d0737e1d
ACO		 455/**
456 * Returns whether any output on the specified pipe will have the specified
457 * type after a staged modeset is complete, i.e., the same as
458 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
459 * encoder->crtc.
460 */
a93e255f
ACO		 461static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
462 int type)
d0737e1d 463{
a93e255f 464 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 465 struct drm_connector *connector;
a93e255f 466 struct drm_connector_state *connector_state;
d0737e1d 467 struct intel_encoder *encoder;
a93e255f
ACO		 468 int i, num_connectors = 0;
469
da3ced29 470 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 471 if (connector_state->crtc != crtc_state->base.crtc)
472 continue;
473
474 num_connectors++;
d0737e1d 475
a93e255f
ACO		 476 encoder = to_intel_encoder(connector_state->best_encoder);
477 if (encoder->type == type)
d0737e1d 478 return true;
a93e255f
ACO		 479 }
480
481 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 482
483 return false;
484}
485
a93e255f
ACO		 486static const intel_limit_t *
487intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 488{
a93e255f 489 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 490 const intel_limit_t *limit;
b91ad0ec 491
a93e255f 492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 493 if (intel_is_dual_link_lvds(dev)) {
1b894b59 494 if (refclk == 100000)
b91ad0ec
ZW		 495 limit = &intel_limits_ironlake_dual_lvds_100m;
496 else
497 limit = &intel_limits_ironlake_dual_lvds;
498 } else {
1b894b59 499 if (refclk == 100000)
b91ad0ec
ZW		 500 limit = &intel_limits_ironlake_single_lvds_100m;
501 else
502 limit = &intel_limits_ironlake_single_lvds;
503 }
c6bb3538 504 } else
b91ad0ec 505 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 506
507 return limit;
508}
509
a93e255f
ACO		 510static const intel_limit_t *
511intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 512{
a93e255f 513 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 514 const intel_limit_t *limit;
515
a93e255f 516 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 517 if (intel_is_dual_link_lvds(dev))
e4b36699 518 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 519 else
e4b36699 520 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
522 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 523 limit = &intel_limits_g4x_hdmi;
a93e255f 524 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 525 limit = &intel_limits_g4x_sdvo;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
a93e255f
ACO		 532static const intel_limit_t *
533intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 534{
a93e255f 535 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 536 const intel_limit_t *limit;
537
5ab7b0b7
ID		 538 if (IS_BROXTON(dev))
539 limit = &intel_limits_bxt;
540 else if (HAS_PCH_SPLIT(dev))
a93e255f 541 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 542 else if (IS_G4X(dev)) {
a93e255f 543 limit = intel_g4x_limit(crtc_state);
f2b115e6 544 } else if (IS_PINEVIEW(dev)) {
a93e255f 545 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 546 limit = &intel_limits_pineview_lvds;
2177832f 547 else
f2b115e6 548 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 549 } else if (IS_CHERRYVIEW(dev)) {
550 limit = &intel_limits_chv;
a0c4da24 551 } else if (IS_VALLEYVIEW(dev)) {
dc730512 552 limit = &intel_limits_vlv;
a6c45cf0 553 } else if (!IS_GEN2(dev)) {
a93e255f 554 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945 558 } else {
a93e255f 559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
a93e255f 561 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 562 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 563 else
564 limit = &intel_limits_i8xx_dac;
79e53945
JB		 565 }
566 return limit;
567}
568
f2b115e6
AJ		 569/* m1 is reserved as 0 in Pineview, n is a ring counter */
570static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 571{
2177832f
SL		 572 clock->m = clock->m2 + 2;
573 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 574 if (WARN_ON(clock->n == 0 || clock->p == 0))
575 return;
fb03ac01
VS		 576 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 578}
579
7429e9d4
DV		 580static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
581{
582 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
583}
584
ac58c3f0 585static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 586{
7429e9d4 587 clock->m = i9xx_dpll_compute_m(clock);
79e53945 588 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 589 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
590 return;
fb03ac01
VS		 591 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 593}
594
ef9348c8
CML		 595static void chv_clock(int refclk, intel_clock_t *clock)
596{
597 clock->m = clock->m1 * clock->m2;
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n == 0 || clock->p == 0))
600 return;
601 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
602 clock->n << 22);
603 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
604}
605
7c04d1d9 606#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 607/**
608 * Returns whether the given set of divisors are valid for a given refclk with
609 * the given connectors.
610 */
611
1b894b59
CW		 612static bool intel_PLL_is_valid(struct drm_device *dev,
613 const intel_limit_t *limit,
614 const intel_clock_t *clock)
79e53945 615{
f01b7962
VS		 616 if (clock->n < limit->n.min || limit->n.max < clock->n)
617 INTELPllInvalid("n out of range\n");
79e53945 618 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 619 INTELPllInvalid("p1 out of range\n");
79e53945 620 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 621 INTELPllInvalid("m2 out of range\n");
79e53945 622 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 623 INTELPllInvalid("m1 out of range\n");
f01b7962 624
5ab7b0b7 625 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 626 if (clock->m1 <= clock->m2)
627 INTELPllInvalid("m1 <= m2\n");
628
5ab7b0b7 629 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 630 if (clock->p < limit->p.min || limit->p.max < clock->p)
631 INTELPllInvalid("p out of range\n");
632 if (clock->m < limit->m.min || limit->m.max < clock->m)
633 INTELPllInvalid("m out of range\n");
634 }
635
79e53945 636 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 637 INTELPllInvalid("vco out of range\n");
79e53945
JB		 638 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
639 * connector, etc., rather than just a single range.
640 */
641 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 642 INTELPllInvalid("dot out of range\n");
79e53945
JB		 643
644 return true;
645}
646
d4906093 647static bool
a93e255f
ACO		 648i9xx_find_best_dpll(const intel_limit_t *limit,
649 struct intel_crtc_state *crtc_state,
cec2f356
SP		 650 int target, int refclk, intel_clock_t *match_clock,
651 intel_clock_t *best_clock)
79e53945 652{
a93e255f 653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 654 struct drm_device *dev = crtc->base.dev;
79e53945 655 intel_clock_t clock;
79e53945
JB		 656 int err = target;
657
a93e255f 658 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 659 /*
a210b028
DV		 660 * For LVDS just rely on its current settings for dual-channel.
661 * We haven't figured out how to reliably set up different
662 * single/dual channel state, if we even can.
79e53945 663 */
1974cad0 664 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 665 clock.p2 = limit->p2.p2_fast;
666 else
667 clock.p2 = limit->p2.p2_slow;
668 } else {
669 if (target < limit->p2.dot_limit)
670 clock.p2 = limit->p2.p2_slow;
671 else
672 clock.p2 = limit->p2.p2_fast;
673 }
674
0206e353 675 memset(best_clock, 0, sizeof(*best_clock));
79e53945 676
42158660
ZY		 677 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
678 clock.m1++) {
679 for (clock.m2 = limit->m2.min;
680 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 681 if (clock.m2 >= clock.m1)
42158660
ZY		 682 break;
683 for (clock.n = limit->n.min;
684 clock.n <= limit->n.max; clock.n++) {
685 for (clock.p1 = limit->p1.min;
686 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 687 int this_err;
688
ac58c3f0
DV		 689 i9xx_clock(refclk, &clock);
690 if (!intel_PLL_is_valid(dev, limit,
691 &clock))
692 continue;
693 if (match_clock &&
694 clock.p != match_clock->p)
695 continue;
696
697 this_err = abs(clock.dot - target);
698 if (this_err < err) {
699 *best_clock = clock;
700 err = this_err;
701 }
702 }
703 }
704 }
705 }
706
707 return (err != target);
708}
709
710static bool
a93e255f
ACO		 711pnv_find_best_dpll(const intel_limit_t *limit,
712 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 713 int target, int refclk, intel_clock_t *match_clock,
714 intel_clock_t *best_clock)
79e53945 715{
a93e255f 716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 717 struct drm_device *dev = crtc->base.dev;
79e53945 718 intel_clock_t clock;
79e53945
JB		 719 int err = target;
720
a93e255f 721 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 722 /*
a210b028
DV		 723 * For LVDS just rely on its current settings for dual-channel.
724 * We haven't figured out how to reliably set up different
725 * single/dual channel state, if we even can.
79e53945 726 */
1974cad0 727 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 728 clock.p2 = limit->p2.p2_fast;
729 else
730 clock.p2 = limit->p2.p2_slow;
731 } else {
732 if (target < limit->p2.dot_limit)
733 clock.p2 = limit->p2.p2_slow;
734 else
735 clock.p2 = limit->p2.p2_fast;
736 }
737
0206e353 738 memset(best_clock, 0, sizeof(*best_clock));
79e53945 739
42158660
ZY		 740 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
741 clock.m1++) {
742 for (clock.m2 = limit->m2.min;
743 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 744 for (clock.n = limit->n.min;
745 clock.n <= limit->n.max; clock.n++) {
746 for (clock.p1 = limit->p1.min;
747 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 748 int this_err;
749
ac58c3f0 750 pineview_clock(refclk, &clock);
1b894b59
CW		 751 if (!intel_PLL_is_valid(dev, limit,
752 &clock))
79e53945 753 continue;
cec2f356
SP		 754 if (match_clock &&
755 clock.p != match_clock->p)
756 continue;
79e53945
JB		 757
758 this_err = abs(clock.dot - target);
759 if (this_err < err) {
760 *best_clock = clock;
761 err = this_err;
762 }
763 }
764 }
765 }
766 }
767
768 return (err != target);
769}
770
d4906093 771static bool
a93e255f
ACO		 772g4x_find_best_dpll(const intel_limit_t *limit,
773 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 774 int target, int refclk, intel_clock_t *match_clock,
775 intel_clock_t *best_clock)
d4906093 776{
a93e255f 777 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 778 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 779 intel_clock_t clock;
780 int max_n;
781 bool found;
6ba770dc
AJ		 782 /* approximately equals target * 0.00585 */
783 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 784 found = false;
785
a93e255f 786 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 787 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 788 clock.p2 = limit->p2.p2_fast;
789 else
790 clock.p2 = limit->p2.p2_slow;
791 } else {
792 if (target < limit->p2.dot_limit)
793 clock.p2 = limit->p2.p2_slow;
794 else
795 clock.p2 = limit->p2.p2_fast;
796 }
797
798 memset(best_clock, 0, sizeof(*best_clock));
799 max_n = limit->n.max;
f77f13e2 800 /* based on hardware requirement, prefer smaller n to precision */
d4906093 801 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 802 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 803 for (clock.m1 = limit->m1.max;
804 clock.m1 >= limit->m1.min; clock.m1--) {
805 for (clock.m2 = limit->m2.max;
806 clock.m2 >= limit->m2.min; clock.m2--) {
807 for (clock.p1 = limit->p1.max;
808 clock.p1 >= limit->p1.min; clock.p1--) {
809 int this_err;
810
ac58c3f0 811 i9xx_clock(refclk, &clock);
1b894b59
CW		 812 if (!intel_PLL_is_valid(dev, limit,
813 &clock))
d4906093 814 continue;
1b894b59
CW		 815
816 this_err = abs(clock.dot - target);
d4906093
ML		 817 if (this_err < err_most) {
818 *best_clock = clock;
819 err_most = this_err;
820 max_n = clock.n;
821 found = true;
822 }
823 }
824 }
825 }
826 }
2c07245f
ZW		 827 return found;
828}
829
d5dd62bd
ID		 830/*
831 * Check if the calculated PLL configuration is more optimal compared to the
832 * best configuration and error found so far. Return the calculated error.
833 */
834static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
835 const intel_clock_t *calculated_clock,
836 const intel_clock_t *best_clock,
837 unsigned int best_error_ppm,
838 unsigned int *error_ppm)
839{
9ca3ba01
ID		 840 /*
841 * For CHV ignore the error and consider only the P value.
842 * Prefer a bigger P value based on HW requirements.
843 */
844 if (IS_CHERRYVIEW(dev)) {
845 *error_ppm = 0;
846
847 return calculated_clock->p > best_clock->p;
848 }
849
24be4e46
ID		 850 if (WARN_ON_ONCE(!target_freq))
851 return false;
852
d5dd62bd
ID		 853 *error_ppm = div_u64(1000000ULL *
854 abs(target_freq - calculated_clock->dot),
855 target_freq);
856 /*
857 * Prefer a better P value over a better (smaller) error if the error
858 * is small. Ensure this preference for future configurations too by
859 * setting the error to 0.
860 */
861 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
862 *error_ppm = 0;
863
864 return true;
865 }
866
867 return *error_ppm + 10 < best_error_ppm;
868}
869
a0c4da24 870static bool
a93e255f
ACO		 871vlv_find_best_dpll(const intel_limit_t *limit,
872 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
a0c4da24 875{
a93e255f 876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 877 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 878 intel_clock_t clock;
69e4f900 879 unsigned int bestppm = 1000000;
27e639bf
VS		 880 /* min update 19.2 MHz */
881 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 882 bool found = false;
a0c4da24 883
6b4bf1c4
VS		 884 target *= 5; /* fast clock */
885
886 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 887
888 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 889 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 890 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 891 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 892 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 893 clock.p = clock.p1 * clock.p2;
a0c4da24 894 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 895 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 896 unsigned int ppm;
69e4f900 897
6b4bf1c4
VS		 898 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
899 refclk * clock.m1);
900
901 vlv_clock(refclk, &clock);
43b0ac53 902
f01b7962
VS		 903 if (!intel_PLL_is_valid(dev, limit,
904 &clock))
43b0ac53
VS		 905 continue;
906
d5dd62bd
ID		 907 if (!vlv_PLL_is_optimal(dev, target,
908 &clock,
909 best_clock,
910 bestppm, &ppm))
911 continue;
6b4bf1c4 912
d5dd62bd
ID		 913 *best_clock = clock;
914 bestppm = ppm;
915 found = true;
a0c4da24
JB		 916 }
917 }
918 }
919 }
a0c4da24 920
49e497ef 921 return found;
a0c4da24 922}
a4fc5ed6 923
ef9348c8 924static bool
a93e255f
ACO		 925chv_find_best_dpll(const intel_limit_t *limit,
926 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 927 int target, int refclk, intel_clock_t *match_clock,
928 intel_clock_t *best_clock)
929{
a93e255f 930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 931 struct drm_device *dev = crtc->base.dev;
9ca3ba01 932 unsigned int best_error_ppm;
ef9348c8
CML		 933 intel_clock_t clock;
934 uint64_t m2;
935 int found = false;
936
937 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 938 best_error_ppm = 1000000;
ef9348c8
CML		 939
940 /*
941 * Based on hardware doc, the n always set to 1, and m1 always
942 * set to 2. If requires to support 200Mhz refclk, we need to
943 * revisit this because n may not 1 anymore.
944 */
945 clock.n = 1, clock.m1 = 2;
946 target *= 5; /* fast clock */
947
948 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
949 for (clock.p2 = limit->p2.p2_fast;
950 clock.p2 >= limit->p2.p2_slow;
951 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 952 unsigned int error_ppm;
ef9348c8
CML		 953
954 clock.p = clock.p1 * clock.p2;
955
956 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
957 clock.n) << 22, refclk * clock.m1);
958
959 if (m2 > INT_MAX/clock.m1)
960 continue;
961
962 clock.m2 = m2;
963
964 chv_clock(refclk, &clock);
965
966 if (!intel_PLL_is_valid(dev, limit, &clock))
967 continue;
968
9ca3ba01
ID		 969 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
970 best_error_ppm, &error_ppm))
971 continue;
972
973 *best_clock = clock;
974 best_error_ppm = error_ppm;
975 found = true;
ef9348c8
CML		 976 }
977 }
978
979 return found;
980}
981
5ab7b0b7
ID		 982bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
983 intel_clock_t *best_clock)
984{
985 int refclk = i9xx_get_refclk(crtc_state, 0);
986
987 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
988 target_clock, refclk, NULL, best_clock);
989}
990
20ddf665
VS		 991bool intel_crtc_active(struct drm_crtc *crtc)
992{
993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
994
995 /* Be paranoid as we can arrive here with only partial
996 * state retrieved from the hardware during setup.
997 *
241bfc38 998 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 999 * as Haswell has gained clock readout/fastboot support.
1000 *
66e514c1 1001 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1002 * properly reconstruct framebuffers.
c3d1f436
MR		 1003 *
1004 * FIXME: The intel_crtc->active here should be switched to
1005 * crtc->state->active once we have proper CRTC states wired up
1006 * for atomic.
20ddf665 1007 */
c3d1f436 1008 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1009 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1010}
1011
a5c961d1
PZ		 1012enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1013 enum pipe pipe)
1014{
1015 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1017
6e3c9717 1018 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1019}
1020
fbf49ea2
VS		 1021static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1022{
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 u32 reg = PIPEDSL(pipe);
1025 u32 line1, line2;
1026 u32 line_mask;
1027
1028 if (IS_GEN2(dev))
1029 line_mask = DSL_LINEMASK_GEN2;
1030 else
1031 line_mask = DSL_LINEMASK_GEN3;
1032
1033 line1 = I915_READ(reg) & line_mask;
1034 mdelay(5);
1035 line2 = I915_READ(reg) & line_mask;
1036
1037 return line1 == line2;
1038}
1039
ab7ad7f6
KP		 1040/*
1041 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1042 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1043 *
1044 * After disabling a pipe, we can't wait for vblank in the usual way,
1045 * spinning on the vblank interrupt status bit, since we won't actually
1046 * see an interrupt when the pipe is disabled.
1047 *
ab7ad7f6
KP		 1048 * On Gen4 and above:
1049 * wait for the pipe register state bit to turn off
1050 *
1051 * Otherwise:
1052 * wait for the display line value to settle (it usually
1053 * ends up stopping at the start of the next frame).
58e10eb9 1054 *
9d0498a2 1055 */
575f7ab7 1056static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1057{
575f7ab7 1058 struct drm_device *dev = crtc->base.dev;
9d0498a2 1059 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1060 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1061 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1062
1063 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1064 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1065
1066 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1067 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1068 100))
284637d9 1069 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1070 } else {
ab7ad7f6 1071 /* Wait for the display line to settle */
fbf49ea2 1072 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1073 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1074 }
79e53945
JB		 1075}
1076
b0ea7d37
DL		 1077/*
1078 * ibx_digital_port_connected - is the specified port connected?
1079 * @dev_priv: i915 private structure
1080 * @port: the port to test
1081 *
1082 * Returns true if @port is connected, false otherwise.
1083 */
1084bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1085 struct intel_digital_port *port)
1086{
1087 u32 bit;
1088
c36346e3 1089 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1090 switch (port->port) {
c36346e3
DL		 1091 case PORT_B:
1092 bit = SDE_PORTB_HOTPLUG;
1093 break;
1094 case PORT_C:
1095 bit = SDE_PORTC_HOTPLUG;
1096 break;
1097 case PORT_D:
1098 bit = SDE_PORTD_HOTPLUG;
1099 break;
1100 default:
1101 return true;
1102 }
1103 } else {
eba905b2 1104 switch (port->port) {
c36346e3
DL		 1105 case PORT_B:
1106 bit = SDE_PORTB_HOTPLUG_CPT;
1107 break;
1108 case PORT_C:
1109 bit = SDE_PORTC_HOTPLUG_CPT;
1110 break;
1111 case PORT_D:
1112 bit = SDE_PORTD_HOTPLUG_CPT;
1113 break;
1114 default:
1115 return true;
1116 }
b0ea7d37
DL		 1117 }
1118
1119 return I915_READ(SDEISR) & bit;
1120}
1121
b24e7179
JB		 1122static const char *state_string(bool enabled)
1123{
1124 return enabled ? "on" : "off";
1125}
1126
1127/* Only for pre-ILK configs */
55607e8a
DV		 1128void assert_pll(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
b24e7179
JB		 1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
1135 reg = DPLL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1138 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1139 "PLL state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
b24e7179 1142
23538ef1
JN		 1143/* XXX: the dsi pll is shared between MIPI DSI ports */
1144static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1145{
1146 u32 val;
1147 bool cur_state;
1148
a580516d 1149 mutex_lock(&dev_priv->sb_lock);
23538ef1 1150 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1151 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1152
1153 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1154 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1155 "DSI PLL state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157}
1158#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1159#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1160
55607e8a 1161struct intel_shared_dpll *
e2b78267
DV		 1162intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1163{
1164 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1165
6e3c9717 1166 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1167 return NULL;
1168
6e3c9717 1169 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1170}
1171
040484af 1172/* For ILK+ */
55607e8a
DV		 1173void assert_shared_dpll(struct drm_i915_private *dev_priv,
1174 struct intel_shared_dpll *pll,
1175 bool state)
040484af 1176{
040484af 1177 bool cur_state;
5358901f 1178 struct intel_dpll_hw_state hw_state;
040484af 1179
92b27b08 1180 if (WARN (!pll,
46edb027 1181 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1182 return;
ee7b9f93 1183
5358901f 1184 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1185 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1186 "%s assertion failure (expected %s, current %s)\n",
1187 pll->name, state_string(state), state_string(cur_state));
040484af 1188}
040484af
JB		 1189
1190static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1191 enum pipe pipe, bool state)
1192{
1193 int reg;
1194 u32 val;
1195 bool cur_state;
ad80a810
PZ		 1196 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1197 pipe);
040484af 1198
affa9354
PZ		 1199 if (HAS_DDI(dev_priv->dev)) {
1200 /* DDI does not have a specific FDI_TX register */
ad80a810 1201 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1202 val = I915_READ(reg);
ad80a810 1203 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1204 } else {
1205 reg = FDI_TX_CTL(pipe);
1206 val = I915_READ(reg);
1207 cur_state = !!(val & FDI_TX_ENABLE);
1208 }
e2c719b7 1209 I915_STATE_WARN(cur_state != state,
040484af
JB		 1210 "FDI TX state assertion failure (expected %s, current %s)\n",
1211 state_string(state), state_string(cur_state));
1212}
1213#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1214#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1215
1216static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218{
1219 int reg;
1220 u32 val;
1221 bool cur_state;
1222
d63fa0dc
PZ		 1223 reg = FDI_RX_CTL(pipe);
1224 val = I915_READ(reg);
1225 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1226 I915_STATE_WARN(cur_state != state,
040484af
JB		 1227 "FDI RX state assertion failure (expected %s, current %s)\n",
1228 state_string(state), state_string(cur_state));
1229}
1230#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1231#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1232
1233static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1234 enum pipe pipe)
1235{
1236 int reg;
1237 u32 val;
1238
1239 /* ILK FDI PLL is always enabled */
3d13ef2e 1240 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1241 return;
1242
bf507ef7 1243 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1244 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1245 return;
1246
040484af
JB		 1247 reg = FDI_TX_CTL(pipe);
1248 val = I915_READ(reg);
e2c719b7 1249 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1250}
1251
55607e8a
DV		 1252void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, bool state)
040484af
JB		 1254{
1255 int reg;
1256 u32 val;
55607e8a 1257 bool cur_state;
040484af
JB		 1258
1259 reg = FDI_RX_CTL(pipe);
1260 val = I915_READ(reg);
55607e8a 1261 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1262 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1263 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1264 state_string(state), state_string(cur_state));
040484af
JB		 1265}
1266
b680c37a
DV		 1267void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1268 enum pipe pipe)
ea0760cf 1269{
bedd4dba
JN		 1270 struct drm_device *dev = dev_priv->dev;
1271 int pp_reg;
ea0760cf
JB		 1272 u32 val;
1273 enum pipe panel_pipe = PIPE_A;
0de3b485 1274 bool locked = true;
ea0760cf 1275
bedd4dba
JN		 1276 if (WARN_ON(HAS_DDI(dev)))
1277 return;
1278
1279 if (HAS_PCH_SPLIT(dev)) {
1280 u32 port_sel;
1281
ea0760cf 1282 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1283 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284
1285 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1286 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1287 panel_pipe = PIPE_B;
1288 /* XXX: else fix for eDP */
1289 } else if (IS_VALLEYVIEW(dev)) {
1290 /* presumably write lock depends on pipe, not port select */
1291 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1292 panel_pipe = pipe;
ea0760cf
JB		 1293 } else {
1294 pp_reg = PP_CONTROL;
bedd4dba
JN		 1295 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1296 panel_pipe = PIPE_B;
ea0760cf
JB		 1297 }
1298
1299 val = I915_READ(pp_reg);
1300 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1301 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1302 locked = false;
1303
e2c719b7 1304 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1305 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1306 pipe_name(pipe));
ea0760cf
JB		 1307}
1308
93ce0ba6
JN		 1309static void assert_cursor(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, bool state)
1311{
1312 struct drm_device *dev = dev_priv->dev;
1313 bool cur_state;
1314
d9d82081 1315 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1316 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1317 else
5efb3e28 1318 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1319
e2c719b7 1320 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1321 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1322 pipe_name(pipe), state_string(state), state_string(cur_state));
1323}
1324#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1325#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326
b840d907
JB		 1327void assert_pipe(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, bool state)
b24e7179
JB		 1329{
1330 int reg;
1331 u32 val;
63d7bbe9 1332 bool cur_state;
702e7a56
PZ		 1333 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1334 pipe);
b24e7179 1335
b6b5d049
VS		 1336 /* if we need the pipe quirk it must be always on */
1337 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1338 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1339 state = true;
1340
f458ebbc 1341 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1342 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1343 cur_state = false;
1344 } else {
1345 reg = PIPECONF(cpu_transcoder);
1346 val = I915_READ(reg);
1347 cur_state = !!(val & PIPECONF_ENABLE);
1348 }
1349
e2c719b7 1350 I915_STATE_WARN(cur_state != state,
63d7bbe9 1351 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1352 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1353}
1354
931872fc
CW		 1355static void assert_plane(struct drm_i915_private *dev_priv,
1356 enum plane plane, bool state)
b24e7179
JB		 1357{
1358 int reg;
1359 u32 val;
931872fc 1360 bool cur_state;
b24e7179
JB		 1361
1362 reg = DSPCNTR(plane);
1363 val = I915_READ(reg);
931872fc 1364 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1365 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1366 "plane %c assertion failure (expected %s, current %s)\n",
1367 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1368}
1369
931872fc
CW		 1370#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1371#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1372
b24e7179
JB		 1373static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe)
1375{
653e1026 1376 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1377 int reg, i;
1378 u32 val;
1379 int cur_pipe;
1380
653e1026
VS		 1381 /* Primary planes are fixed to pipes on gen4+ */
1382 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1383 reg = DSPCNTR(pipe);
1384 val = I915_READ(reg);
e2c719b7 1385 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1386 "plane %c assertion failure, should be disabled but not\n",
1387 plane_name(pipe));
19ec1358 1388 return;
28c05794 1389 }
19ec1358 1390
b24e7179 1391 /* Need to check both planes against the pipe */
055e393f 1392 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1393 reg = DSPCNTR(i);
1394 val = I915_READ(reg);
1395 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1396 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1397 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1398 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1399 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1400 }
1401}
1402
19332d7a
JB		 1403static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405{
20674eef 1406 struct drm_device *dev = dev_priv->dev;
1fe47785 1407 int reg, sprite;
19332d7a
JB		 1408 u32 val;
1409
7feb8b88 1410 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1411 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1412 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1413 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1414 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1415 sprite, pipe_name(pipe));
1416 }
1417 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1419 reg = SPCNTR(pipe, sprite);
20674eef 1420 val = I915_READ(reg);
e2c719b7 1421 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1423 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1424 }
1425 } else if (INTEL_INFO(dev)->gen >= 7) {
1426 reg = SPRCTL(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1430 plane_name(pipe), pipe_name(pipe));
1431 } else if (INTEL_INFO(dev)->gen >= 5) {
1432 reg = DVSCNTR(pipe);
19332d7a 1433 val = I915_READ(reg);
e2c719b7 1434 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1435 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1436 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1437 }
1438}
1439
08c71e5e
VS		 1440static void assert_vblank_disabled(struct drm_crtc *crtc)
1441{
e2c719b7 1442 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1443 drm_crtc_vblank_put(crtc);
1444}
1445
89eff4be 1446static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1447{
1448 u32 val;
1449 bool enabled;
1450
e2c719b7 1451 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1452
92f2584a
JB		 1453 val = I915_READ(PCH_DREF_CONTROL);
1454 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1455 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1456 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1457}
1458
ab9412ba
DV		 1459static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
92f2584a
JB		 1461{
1462 int reg;
1463 u32 val;
1464 bool enabled;
1465
ab9412ba 1466 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1467 val = I915_READ(reg);
1468 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1469 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1470 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1471 pipe_name(pipe));
92f2584a
JB		 1472}
1473
4e634389
KP		 1474static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1476{
1477 if ((val & DP_PORT_EN) == 0)
1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
1481 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1482 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1483 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1484 return false;
44f37d1f
CML		 1485 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1486 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1487 return false;
f0575e92
KP		 1488 } else {
1489 if ((val & DP_PIPE_MASK) != (pipe << 30))
1490 return false;
1491 }
1492 return true;
1493}
1494
1519b995
KP		 1495static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497{
dc0fa718 1498 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1499 return false;
1500
1501 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1503 return false;
44f37d1f
CML		 1504 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1505 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1506 return false;
1519b995 1507 } else {
dc0fa718 1508 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1509 return false;
1510 }
1511 return true;
1512}
1513
1514static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1515 enum pipe pipe, u32 val)
1516{
1517 if ((val & LVDS_PORT_EN) == 0)
1518 return false;
1519
1520 if (HAS_PCH_CPT(dev_priv->dev)) {
1521 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1522 return false;
1523 } else {
1524 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1525 return false;
1526 }
1527 return true;
1528}
1529
1530static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1531 enum pipe pipe, u32 val)
1532{
1533 if ((val & ADPA_DAC_ENABLE) == 0)
1534 return false;
1535 if (HAS_PCH_CPT(dev_priv->dev)) {
1536 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1537 return false;
1538 } else {
1539 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1540 return false;
1541 }
1542 return true;
1543}
1544
291906f1 1545static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1546 enum pipe pipe, int reg, u32 port_sel)
291906f1 1547{
47a05eca 1548 u32 val = I915_READ(reg);
e2c719b7 1549 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1550 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1551 reg, pipe_name(pipe));
de9a35ab 1552
e2c719b7 1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1554 && (val & DP_PIPEB_SELECT),
de9a35ab 1555 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1556}
1557
1558static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe, int reg)
1560{
47a05eca 1561 u32 val = I915_READ(reg);
e2c719b7 1562 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1563 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1564 reg, pipe_name(pipe));
de9a35ab 1565
e2c719b7 1566 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1567 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1568 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1569}
1570
1571static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1572 enum pipe pipe)
1573{
1574 int reg;
1575 u32 val;
291906f1 1576
f0575e92
KP		 1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1580
1581 reg = PCH_ADPA;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1
JB		 1586
1587 reg = PCH_LVDS;
1588 val = I915_READ(reg);
e2c719b7 1589 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1590 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1591 pipe_name(pipe));
291906f1 1592
e2debe91
PZ		 1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1595 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1596}
1597
40e9cf64
JB		 1598static void intel_init_dpio(struct drm_device *dev)
1599{
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601
1602 if (!IS_VALLEYVIEW(dev))
1603 return;
1604
a09caddd
CML		 1605 /*
1606 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1607 * CHV x1 PHY (DP/HDMI D)
1608 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1609 */
1610 if (IS_CHERRYVIEW(dev)) {
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1612 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1613 } else {
1614 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1615 }
5382f5f3
JB		 1616}
1617
d288f65f 1618static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1619 const struct intel_crtc_state *pipe_config)
87442f73 1620{
426115cf
DV		 1621 struct drm_device *dev = crtc->base.dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 int reg = DPLL(crtc->pipe);
d288f65f 1624 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1625
426115cf 1626 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1627
1628 /* No really, not for ILK+ */
1629 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1630
1631 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1632 if (IS_MOBILE(dev_priv->dev))
426115cf 1633 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1634
426115cf
DV		 1635 I915_WRITE(reg, dpll);
1636 POSTING_READ(reg);
1637 udelay(150);
1638
1639 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1640 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1641
d288f65f 1642 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1643 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1644
1645 /* We do this three times for luck */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
426115cf 1649 I915_WRITE(reg, dpll);
87442f73
DV		 1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
426115cf 1652 I915_WRITE(reg, dpll);
87442f73
DV		 1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655}
1656
d288f65f 1657static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1658 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1659{
1660 struct drm_device *dev = crtc->base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 int pipe = crtc->pipe;
1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1664 u32 tmp;
1665
1666 assert_pipe_disabled(dev_priv, crtc->pipe);
1667
1668 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1669
a580516d 1670 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1671
1672 /* Enable back the 10bit clock to display controller */
1673 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1674 tmp |= DPIO_DCLKP_EN;
1675 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1676
54433e91
VS		 1677 mutex_unlock(&dev_priv->sb_lock);
1678
9d556c99
CML		 1679 /*
1680 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1681 */
1682 udelay(1);
1683
1684 /* Enable PLL */
d288f65f 1685 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1686
1687 /* Check PLL is locked */
a11b0703 1688 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1689 DRM_ERROR("PLL %d failed to lock\n", pipe);
1690
a11b0703 1691 /* not sure when this should be written */
d288f65f 1692 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1693 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1694}
1695
1c4e0274
VS		 1696static int intel_num_dvo_pipes(struct drm_device *dev)
1697{
1698 struct intel_crtc *crtc;
1699 int count = 0;
1700
1701 for_each_intel_crtc(dev, crtc)
1702 count += crtc->active &&
409ee761 1703 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1704
1705 return count;
1706}
1707
66e3d5c0 1708static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1709{
66e3d5c0
DV		 1710 struct drm_device *dev = crtc->base.dev;
1711 struct drm_i915_private *dev_priv = dev->dev_private;
1712 int reg = DPLL(crtc->pipe);
6e3c9717 1713 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1714
66e3d5c0 1715 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1716
63d7bbe9 1717 /* No really, not for ILK+ */
3d13ef2e 1718 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1719
1720 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1721 if (IS_MOBILE(dev) && !IS_I830(dev))
1722 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1723
1c4e0274
VS		 1724 /* Enable DVO 2x clock on both PLLs if necessary */
1725 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1726 /*
1727 * It appears to be important that we don't enable this
1728 * for the current pipe before otherwise configuring the
1729 * PLL. No idea how this should be handled if multiple
1730 * DVO outputs are enabled simultaneosly.
1731 */
1732 dpll |= DPLL_DVO_2X_MODE;
1733 I915_WRITE(DPLL(!crtc->pipe),
1734 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1735 }
66e3d5c0
DV		 1736
1737 /* Wait for the clocks to stabilize. */
1738 POSTING_READ(reg);
1739 udelay(150);
1740
1741 if (INTEL_INFO(dev)->gen >= 4) {
1742 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1743 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1744 } else {
1745 /* The pixel multiplier can only be updated once the
1746 * DPLL is enabled and the clocks are stable.
1747 *
1748 * So write it again.
1749 */
1750 I915_WRITE(reg, dpll);
1751 }
63d7bbe9
JB		 1752
1753 /* We do this three times for luck */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
66e3d5c0 1757 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1758 POSTING_READ(reg);
1759 udelay(150); /* wait for warmup */
66e3d5c0 1760 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1761 POSTING_READ(reg);
1762 udelay(150); /* wait for warmup */
1763}
1764
1765/**
50b44a44 1766 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe PLL to disable
1769 *
1770 * Disable the PLL for @pipe, making sure the pipe is off first.
1771 *
1772 * Note! This is for pre-ILK only.
1773 */
1c4e0274 1774static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1775{
1c4e0274
VS		 1776 struct drm_device *dev = crtc->base.dev;
1777 struct drm_i915_private *dev_priv = dev->dev_private;
1778 enum pipe pipe = crtc->pipe;
1779
1780 /* Disable DVO 2x clock on both PLLs if necessary */
1781 if (IS_I830(dev) &&
409ee761 1782 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1783 intel_num_dvo_pipes(dev) == 1) {
1784 I915_WRITE(DPLL(PIPE_B),
1785 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1786 I915_WRITE(DPLL(PIPE_A),
1787 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1788 }
1789
b6b5d049
VS		 1790 /* Don't disable pipe or pipe PLLs if needed */
1791 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1792 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1793 return;
1794
1795 /* Make sure the pipe isn't still relying on us */
1796 assert_pipe_disabled(dev_priv, pipe);
1797
50b44a44
DV		 1798 I915_WRITE(DPLL(pipe), 0);
1799 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1800}
1801
f6071166
JB		 1802static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1803{
1804 u32 val = 0;
1805
1806 /* Make sure the pipe isn't still relying on us */
1807 assert_pipe_disabled(dev_priv, pipe);
1808
e5cbfbfb
ID		 1809 /*
1810 * Leave integrated clock source and reference clock enabled for pipe B.
1811 * The latter is needed for VGA hotplug / manual detection.
1812 */
f6071166 1813 if (pipe == PIPE_B)
e5cbfbfb 1814 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1815 I915_WRITE(DPLL(pipe), val);
1816 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1817
1818}
1819
1820static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1821{
d752048d 1822 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1823 u32 val;
1824
a11b0703
VS		 1825 /* Make sure the pipe isn't still relying on us */
1826 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1827
a11b0703 1828 /* Set PLL en = 0 */
d17ec4ce 1829 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1830 if (pipe != PIPE_A)
1831 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1832 I915_WRITE(DPLL(pipe), val);
1833 POSTING_READ(DPLL(pipe));
d752048d 1834
a580516d 1835 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1836
1837 /* Disable 10bit clock to display controller */
1838 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1839 val &= ~DPIO_DCLKP_EN;
1840 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1841
61407f6d
VS		 1842 /* disable left/right clock distribution */
1843 if (pipe != PIPE_B) {
1844 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1845 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1846 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1847 } else {
1848 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1849 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1850 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1851 }
1852
a580516d 1853 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1854}
1855
e4607fcf 1856void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1857 struct intel_digital_port *dport,
1858 unsigned int expected_mask)
89b667f8
JB		 1859{
1860 u32 port_mask;
00fc31b7 1861 int dpll_reg;
89b667f8 1862
e4607fcf
CML		 1863 switch (dport->port) {
1864 case PORT_B:
89b667f8 1865 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1866 dpll_reg = DPLL(0);
e4607fcf
CML		 1867 break;
1868 case PORT_C:
89b667f8 1869 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1870 dpll_reg = DPLL(0);
9b6de0a1 1871 expected_mask <<= 4;
00fc31b7
CML		 1872 break;
1873 case PORT_D:
1874 port_mask = DPLL_PORTD_READY_MASK;
1875 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1876 break;
1877 default:
1878 BUG();
1879 }
89b667f8 1880
9b6de0a1
VS		 1881 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1884}
1885
b14b1055
DV		 1886static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887{
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
be19f0ff
CW		 1892 if (WARN_ON(pll == NULL))
1893 return;
1894
3e369b76 1895 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1896 if (pll->active == 0) {
1897 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898 WARN_ON(pll->on);
1899 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901 pll->mode_set(dev_priv, pll);
1902 }
1903}
1904
92f2584a 1905/**
85b3894f 1906 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1907 * @dev_priv: i915 private structure
1908 * @pipe: pipe PLL to enable
1909 *
1910 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911 * drives the transcoder clock.
1912 */
85b3894f 1913static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1918
87a875bb 1919 if (WARN_ON(pll == NULL))
48da64a8
CW		 1920 return;
1921
3e369b76 1922 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1923 return;
ee7b9f93 1924
74dd6928 1925 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1926 pll->name, pll->active, pll->on,
e2b78267 1927 crtc->base.base.id);
92f2584a 1928
cdbd2316
DV		 1929 if (pll->active++) {
1930 WARN_ON(!pll->on);
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1932 return;
1933 }
f4a091c7 1934 WARN_ON(pll->on);
ee7b9f93 1935
bd2bb1b9
PZ		 1936 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
46edb027 1938 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1939 pll->enable(dev_priv, pll);
ee7b9f93 1940 pll->on = true;
92f2584a
JB		 1941}
1942
f6daaec2 1943static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1944{
3d13ef2e
DL		 1945 struct drm_device *dev = crtc->base.dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1947 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1948
92f2584a 1949 /* PCH only available on ILK+ */
3d13ef2e 1950 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1951 if (WARN_ON(pll == NULL))
ee7b9f93 1952 return;
92f2584a 1953
3e369b76 1954 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1955 return;
7a419866 1956
46edb027
DV		 1957 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1958 pll->name, pll->active, pll->on,
e2b78267 1959 crtc->base.base.id);
7a419866 1960
48da64a8 1961 if (WARN_ON(pll->active == 0)) {
e9d6944e 1962 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1963 return;
1964 }
1965
e9d6944e 1966 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1967 WARN_ON(!pll->on);
cdbd2316 1968 if (--pll->active)
7a419866 1969 return;
ee7b9f93 1970
46edb027 1971 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1972 pll->disable(dev_priv, pll);
ee7b9f93 1973 pll->on = false;
bd2bb1b9
PZ		 1974
1975 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1976}
1977
b8a4f404
PZ		 1978static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1979 enum pipe pipe)
040484af 1980{
23670b32 1981 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1982 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1984 uint32_t reg, val, pipeconf_val;
040484af
JB		 1985
1986 /* PCH only available on ILK+ */
55522f37 1987 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1988
1989 /* Make sure PCH DPLL is enabled */
e72f9fbf 1990 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1991 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1992
1993 /* FDI must be feeding us bits for PCH ports */
1994 assert_fdi_tx_enabled(dev_priv, pipe);
1995 assert_fdi_rx_enabled(dev_priv, pipe);
1996
23670b32
DV		 1997 if (HAS_PCH_CPT(dev)) {
1998 /* Workaround: Set the timing override bit before enabling the
1999 * pch transcoder. */
2000 reg = TRANS_CHICKEN2(pipe);
2001 val = I915_READ(reg);
2002 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2003 I915_WRITE(reg, val);
59c859d6 2004 }
23670b32 2005
ab9412ba 2006 reg = PCH_TRANSCONF(pipe);
040484af 2007 val = I915_READ(reg);
5f7f726d 2008 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2009
2010 if (HAS_PCH_IBX(dev_priv->dev)) {
2011 /*
2012 * make the BPC in transcoder be consistent with
2013 * that in pipeconf reg.
2014 */
dfd07d72
DV		 2015 val &= ~PIPECONF_BPC_MASK;
2016 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2017 }
5f7f726d
PZ		 2018
2019 val &= ~TRANS_INTERLACE_MASK;
2020 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2021 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2022 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2023 val |= TRANS_LEGACY_INTERLACED_ILK;
2024 else
2025 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2026 else
2027 val |= TRANS_PROGRESSIVE;
2028
040484af
JB		 2029 I915_WRITE(reg, val | TRANS_ENABLE);
2030 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2031 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2032}
2033
8fb033d7 2034static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2035 enum transcoder cpu_transcoder)
040484af 2036{
8fb033d7 2037 u32 val, pipeconf_val;
8fb033d7
PZ		 2038
2039 /* PCH only available on ILK+ */
55522f37 2040 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2041
8fb033d7 2042 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2043 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2044 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2045
223a6fdf
PZ		 2046 /* Workaround: set timing override bit. */
2047 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2048 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2049 I915_WRITE(_TRANSA_CHICKEN2, val);
2050
25f3ef11 2051 val = TRANS_ENABLE;
937bb610 2052 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2053
9a76b1c6
PZ		 2054 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2055 PIPECONF_INTERLACED_ILK)
a35f2679 2056 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2057 else
2058 val |= TRANS_PROGRESSIVE;
2059
ab9412ba
DV		 2060 I915_WRITE(LPT_TRANSCONF, val);
2061 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2062 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2063}
2064
b8a4f404
PZ		 2065static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2066 enum pipe pipe)
040484af 2067{
23670b32
DV		 2068 struct drm_device *dev = dev_priv->dev;
2069 uint32_t reg, val;
040484af
JB		 2070
2071 /* FDI relies on the transcoder */
2072 assert_fdi_tx_disabled(dev_priv, pipe);
2073 assert_fdi_rx_disabled(dev_priv, pipe);
2074
291906f1
JB		 2075 /* Ports must be off as well */
2076 assert_pch_ports_disabled(dev_priv, pipe);
2077
ab9412ba 2078 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2079 val = I915_READ(reg);
2080 val &= ~TRANS_ENABLE;
2081 I915_WRITE(reg, val);
2082 /* wait for PCH transcoder off, transcoder state */
2083 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2084 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2085
2086 if (!HAS_PCH_IBX(dev)) {
2087 /* Workaround: Clear the timing override chicken bit again. */
2088 reg = TRANS_CHICKEN2(pipe);
2089 val = I915_READ(reg);
2090 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2091 I915_WRITE(reg, val);
2092 }
040484af
JB		 2093}
2094
ab4d966c 2095static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2096{
8fb033d7
PZ		 2097 u32 val;
2098
ab9412ba 2099 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2100 val &= ~TRANS_ENABLE;
ab9412ba 2101 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2102 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2103 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2104 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2105
2106 /* Workaround: clear timing override bit. */
2107 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2108 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2109 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2110}
2111
b24e7179 2112/**
309cfea8 2113 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2114 * @crtc: crtc responsible for the pipe
b24e7179 2115 *
0372264a 2116 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2117 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2118 */
e1fdc473 2119static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2120{
0372264a
PZ		 2121 struct drm_device *dev = crtc->base.dev;
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2125 pipe);
1a240d4d 2126 enum pipe pch_transcoder;
b24e7179
JB		 2127 int reg;
2128 u32 val;
2129
58c6eaa2 2130 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2131 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2132 assert_sprites_disabled(dev_priv, pipe);
2133
681e5811 2134 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2135 pch_transcoder = TRANSCODER_A;
2136 else
2137 pch_transcoder = pipe;
2138
b24e7179
JB		 2139 /*
2140 * A pipe without a PLL won't actually be able to drive bits from
2141 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2142 * need the check.
2143 */
50360403 2144 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2145 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2146 assert_dsi_pll_enabled(dev_priv);
2147 else
2148 assert_pll_enabled(dev_priv, pipe);
040484af 2149 else {
6e3c9717 2150 if (crtc->config->has_pch_encoder) {
040484af 2151 /* if driving the PCH, we need FDI enabled */
cc391bbb 2152 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2153 assert_fdi_tx_pll_enabled(dev_priv,
2154 (enum pipe) cpu_transcoder);
040484af
JB		 2155 }
2156 /* FIXME: assert CPU port conditions for SNB+ */
2157 }
b24e7179 2158
702e7a56 2159 reg = PIPECONF(cpu_transcoder);
b24e7179 2160 val = I915_READ(reg);
7ad25d48 2161 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2162 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2163 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2164 return;
7ad25d48 2165 }
00d70b15
CW		 2166
2167 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2168 POSTING_READ(reg);
b24e7179
JB		 2169}
2170
2171/**
309cfea8 2172 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2173 * @crtc: crtc whose pipes is to be disabled
b24e7179 2174 *
575f7ab7
VS		 2175 * Disable the pipe of @crtc, making sure that various hardware
2176 * specific requirements are met, if applicable, e.g. plane
2177 * disabled, panel fitter off, etc.
b24e7179
JB		 2178 *
2179 * Will wait until the pipe has shut down before returning.
2180 */
575f7ab7 2181static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2182{
575f7ab7 2183 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2184 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2185 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2186 int reg;
2187 u32 val;
2188
2189 /*
2190 * Make sure planes won't keep trying to pump pixels to us,
2191 * or we might hang the display.
2192 */
2193 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2194 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2195 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2196
702e7a56 2197 reg = PIPECONF(cpu_transcoder);
b24e7179 2198 val = I915_READ(reg);
00d70b15
CW		 2199 if ((val & PIPECONF_ENABLE) == 0)
2200 return;
2201
67adc644
VS		 2202 /*
2203 * Double wide has implications for planes
2204 * so best keep it disabled when not needed.
2205 */
6e3c9717 2206 if (crtc->config->double_wide)
67adc644
VS		 2207 val &= ~PIPECONF_DOUBLE_WIDE;
2208
2209 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2210 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2211 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2212 val &= ~PIPECONF_ENABLE;
2213
2214 I915_WRITE(reg, val);
2215 if ((val & PIPECONF_ENABLE) == 0)
2216 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2217}
2218
2219/**
262ca2b0 2220 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2221 * @plane: plane to be enabled
2222 * @crtc: crtc for the plane
b24e7179 2223 *
fdd508a6 2224 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2225 */
fdd508a6
VS		 2226static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2227 struct drm_crtc *crtc)
b24e7179 2228{
fdd508a6
VS		 2229 struct drm_device *dev = plane->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2232
2233 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2234 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2235 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2236
fdd508a6
VS		 2237 dev_priv->display.update_primary_plane(crtc, plane->fb,
2238 crtc->x, crtc->y);
b24e7179
JB		 2239}
2240
693db184
CW		 2241static bool need_vtd_wa(struct drm_device *dev)
2242{
2243#ifdef CONFIG_INTEL_IOMMU
2244 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2245 return true;
2246#endif
2247 return false;
2248}
2249
50470bb0 2250unsigned int
6761dd31
TU		 2251intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2252 uint64_t fb_format_modifier)
a57ce0b2 2253{
6761dd31
TU		 2254 unsigned int tile_height;
2255 uint32_t pixel_bytes;
a57ce0b2 2256
b5d0e9bf
DL		 2257 switch (fb_format_modifier) {
2258 case DRM_FORMAT_MOD_NONE:
2259 tile_height = 1;
2260 break;
2261 case I915_FORMAT_MOD_X_TILED:
2262 tile_height = IS_GEN2(dev) ? 16 : 8;
2263 break;
2264 case I915_FORMAT_MOD_Y_TILED:
2265 tile_height = 32;
2266 break;
2267 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2268 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2269 switch (pixel_bytes) {
b5d0e9bf 2270 default:
6761dd31 2271 case 1:
b5d0e9bf
DL		 2272 tile_height = 64;
2273 break;
6761dd31
TU		 2274 case 2:
2275 case 4:
b5d0e9bf
DL		 2276 tile_height = 32;
2277 break;
6761dd31 2278 case 8:
b5d0e9bf
DL		 2279 tile_height = 16;
2280 break;
6761dd31 2281 case 16:
b5d0e9bf
DL		 2282 WARN_ONCE(1,
2283 "128-bit pixels are not supported for display!");
2284 tile_height = 16;
2285 break;
2286 }
2287 break;
2288 default:
2289 MISSING_CASE(fb_format_modifier);
2290 tile_height = 1;
2291 break;
2292 }
091df6cb 2293
6761dd31
TU		 2294 return tile_height;
2295}
2296
2297unsigned int
2298intel_fb_align_height(struct drm_device *dev, unsigned int height,
2299 uint32_t pixel_format, uint64_t fb_format_modifier)
2300{
2301 return ALIGN(height, intel_tile_height(dev, pixel_format,
2302 fb_format_modifier));
a57ce0b2
JB		 2303}
2304
f64b98cd
TU		 2305static int
2306intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2307 const struct drm_plane_state *plane_state)
2308{
50470bb0 2309 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2310
f64b98cd
TU		 2311 *view = i915_ggtt_view_normal;
2312
50470bb0
TU		 2313 if (!plane_state)
2314 return 0;
2315
121920fa 2316 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2317 return 0;
2318
9abc4648 2319 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2320
2321 info->height = fb->height;
2322 info->pixel_format = fb->pixel_format;
2323 info->pitch = fb->pitches[0];
2324 info->fb_modifier = fb->modifier[0];
2325
f64b98cd
TU		 2326 return 0;
2327}
2328
127bd2ac 2329int
850c4cdc
TU		 2330intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331 struct drm_framebuffer *fb,
82bc3b2d 2332 const struct drm_plane_state *plane_state,
a4872ba6 2333 struct intel_engine_cs *pipelined)
6b95a207 2334{
850c4cdc 2335 struct drm_device *dev = fb->dev;
ce453d81 2336 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2337 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2338 struct i915_ggtt_view view;
6b95a207
KH		 2339 u32 alignment;
2340 int ret;
2341
ebcdd39e
MR		 2342 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343
7b911adc
TU		 2344 switch (fb->modifier[0]) {
2345 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2348 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2349 alignment = 128 * 1024;
a6c45cf0 2350 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2351 alignment = 4 * 1024;
2352 else
2353 alignment = 64 * 1024;
6b95a207 2354 break;
7b911adc 2355 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2356 if (INTEL_INFO(dev)->gen >= 9)
2357 alignment = 256 * 1024;
2358 else {
2359 /* pin() will align the object as required by fence */
2360 alignment = 0;
2361 }
6b95a207 2362 break;
7b911adc 2363 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2364 case I915_FORMAT_MOD_Yf_TILED:
2365 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2366 "Y tiling bo slipped through, driver bug!\n"))
2367 return -EINVAL;
2368 alignment = 1 * 1024 * 1024;
2369 break;
6b95a207 2370 default:
7b911adc
TU		 2371 MISSING_CASE(fb->modifier[0]);
2372 return -EINVAL;
6b95a207
KH		 2373 }
2374
f64b98cd
TU		 2375 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376 if (ret)
2377 return ret;
2378
693db184
CW		 2379 /* Note that the w/a also requires 64 PTE of padding following the
2380 * bo. We currently fill all unused PTE with the shadow page and so
2381 * we should always have valid PTE following the scanout preventing
2382 * the VT-d warning.
2383 */
2384 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2385 alignment = 256 * 1024;
2386
d6dd6843
PZ		 2387 /*
2388 * Global gtt pte registers are special registers which actually forward
2389 * writes to a chunk of system memory. Which means that there is no risk
2390 * that the register values disappear as soon as we call
2391 * intel_runtime_pm_put(), so it is correct to wrap only the
2392 * pin/unpin/fence and not more.
2393 */
2394 intel_runtime_pm_get(dev_priv);
2395
ce453d81 2396 dev_priv->mm.interruptible = false;
e6617330 2397 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2398 &view);
48b956c5 2399 if (ret)
ce453d81 2400 goto err_interruptible;
6b95a207
KH		 2401
2402 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2403 * fence, whereas 965+ only requires a fence if using
2404 * framebuffer compression. For simplicity, we always install
2405 * a fence as the cost is not that onerous.
2406 */
06d98131 2407 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2408 if (ret)
2409 goto err_unpin;
1690e1eb 2410
9a5a53b3 2411 i915_gem_object_pin_fence(obj);
6b95a207 2412
ce453d81 2413 dev_priv->mm.interruptible = true;
d6dd6843 2414 intel_runtime_pm_put(dev_priv);
6b95a207 2415 return 0;
48b956c5
CW		 2416
2417err_unpin:
f64b98cd 2418 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2419err_interruptible:
2420 dev_priv->mm.interruptible = true;
d6dd6843 2421 intel_runtime_pm_put(dev_priv);
48b956c5 2422 return ret;
6b95a207
KH		 2423}
2424
82bc3b2d
TU		 2425static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2426 const struct drm_plane_state *plane_state)
1690e1eb 2427{
82bc3b2d 2428 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2429 struct i915_ggtt_view view;
2430 int ret;
82bc3b2d 2431
ebcdd39e
MR		 2432 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433
f64b98cd
TU		 2434 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435 WARN_ONCE(ret, "Couldn't get view from plane state!");
2436
1690e1eb 2437 i915_gem_object_unpin_fence(obj);
f64b98cd 2438 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2439}
2440
c2c75131
DV		 2441/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2442 * is assumed to be a power-of-two. */
bc752862
CW		 2443unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2444 unsigned int tiling_mode,
2445 unsigned int cpp,
2446 unsigned int pitch)
c2c75131 2447{
bc752862
CW		 2448 if (tiling_mode != I915_TILING_NONE) {
2449 unsigned int tile_rows, tiles;
c2c75131 2450
bc752862
CW		 2451 tile_rows = *y / 8;
2452 *y %= 8;
c2c75131 2453
bc752862
CW		 2454 tiles = *x / (512/cpp);
2455 *x %= 512/cpp;
2456
2457 return tile_rows * pitch * 8 + tiles * 4096;
2458 } else {
2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
2462 *y = 0;
2463 *x = (offset & 4095) / cpp;
2464 return offset & -4096;
2465 }
c2c75131
DV		 2466}
2467
b35d63fa 2468static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2469{
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487}
2488
bc8d7dff
DL		 2489static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490{
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513}
2514
5724dbd1 2515static bool
f6936e29
DV		 2516intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2518{
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2522 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
46f297fb 2528
ff2652ea
CW		 2529 if (plane_config->size == 0)
2530 return false;
2531
f37b5c2b
DV		 2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
46f297fb 2536 if (!obj)
484b41dd 2537 return false;
46f297fb 2538
49af449b
DL		 2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2541 obj->stride = fb->pitches[0];
46f297fb 2542
6bf129df
DL		 2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2549
2550 mutex_lock(&dev->struct_mutex);
6bf129df 2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2552 &mode_cmd, obj)) {
46f297fb
JB		 2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
46f297fb 2556 mutex_unlock(&dev->struct_mutex);
484b41dd 2557
f6936e29 2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2559 return true;
46f297fb
JB		 2560
2561out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2564 return false;
2565}
2566
afd65eb4
MR		 2567/* Update plane->state->fb to match plane->fb after driver-internal updates */
2568static void
2569update_state_fb(struct drm_plane *plane)
2570{
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579}
2580
5724dbd1 2581static void
f6936e29
DV		 2582intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2584{
2585 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2586 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2ff8fde1 2589 struct drm_i915_gem_object *obj;
88595ac9
DV		 2590 struct drm_plane *primary = intel_crtc->base.primary;
2591 struct drm_framebuffer *fb;
484b41dd 2592
2d14030b 2593 if (!plane_config->fb)
484b41dd
JB		 2594 return;
2595
f6936e29 2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
f55548b5 2599 }
484b41dd 2600
2d14030b 2601 kfree(plane_config->fb);
484b41dd
JB		 2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
70e1e0ec 2607 for_each_crtc(dev, c) {
484b41dd
JB		 2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2ff8fde1
MR		 2613 if (!i->active)
2614 continue;
2615
88595ac9
DV		 2616 fb = c->primary->fb;
2617 if (!fb)
484b41dd
JB		 2618 continue;
2619
88595ac9 2620 obj = intel_fb_obj(fb);
2ff8fde1 2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
484b41dd
JB		 2624 }
2625 }
88595ac9
DV		 2626
2627 return;
2628
2629valid_fb:
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 primary->fb = fb;
2635 primary->state->crtc = &intel_crtc->base;
2636 primary->crtc = &intel_crtc->base;
2637 update_state_fb(primary);
2638 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2639}
2640
29b9bde6
DV		 2641static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2642 struct drm_framebuffer *fb,
2643 int x, int y)
81255565
JB		 2644{
2645 struct drm_device *dev = crtc->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2648 struct drm_plane *primary = crtc->primary;
2649 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2650 struct drm_i915_gem_object *obj;
81255565 2651 int plane = intel_crtc->plane;
e506a0c6 2652 unsigned long linear_offset;
81255565 2653 u32 dspcntr;
f45651ba 2654 u32 reg = DSPCNTR(plane);
48404c1e 2655 int pixel_size;
f45651ba 2656
b70709a6 2657 if (!visible || !fb) {
fdd508a6
VS		 2658 I915_WRITE(reg, 0);
2659 if (INTEL_INFO(dev)->gen >= 4)
2660 I915_WRITE(DSPSURF(plane), 0);
2661 else
2662 I915_WRITE(DSPADDR(plane), 0);
2663 POSTING_READ(reg);
2664 return;
2665 }
2666
c9ba6fad
VS		 2667 obj = intel_fb_obj(fb);
2668 if (WARN_ON(obj == NULL))
2669 return;
2670
2671 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2672
f45651ba
VS		 2673 dspcntr = DISPPLANE_GAMMA_ENABLE;
2674
fdd508a6 2675 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2676
2677 if (INTEL_INFO(dev)->gen < 4) {
2678 if (intel_crtc->pipe == PIPE_B)
2679 dspcntr |= DISPPLANE_SEL_PIPE_B;
2680
2681 /* pipesrc and dspsize control the size that is scaled from,
2682 * which should always be the user's requested size.
2683 */
2684 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2687 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2688 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2689 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2690 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2691 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2692 I915_WRITE(PRIMPOS(plane), 0);
2693 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2694 }
81255565 2695
57779d06
VS		 2696 switch (fb->pixel_format) {
2697 case DRM_FORMAT_C8:
81255565
JB		 2698 dspcntr |= DISPPLANE_8BPP;
2699 break;
57779d06 2700 case DRM_FORMAT_XRGB1555:
57779d06 2701 dspcntr |= DISPPLANE_BGRX555;
81255565 2702 break;
57779d06
VS		 2703 case DRM_FORMAT_RGB565:
2704 dspcntr |= DISPPLANE_BGRX565;
2705 break;
2706 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX888;
2708 break;
2709 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2710 dspcntr |= DISPPLANE_RGBX888;
2711 break;
2712 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2713 dspcntr |= DISPPLANE_BGRX101010;
2714 break;
2715 case DRM_FORMAT_XBGR2101010:
57779d06 2716 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2717 break;
2718 default:
baba133a 2719 BUG();
81255565 2720 }
57779d06 2721
f45651ba
VS		 2722 if (INTEL_INFO(dev)->gen >= 4 &&
2723 obj->tiling_mode != I915_TILING_NONE)
2724 dspcntr |= DISPPLANE_TILED;
81255565 2725
de1aa629
VS		 2726 if (IS_G4X(dev))
2727 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728
b9897127 2729 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2730
c2c75131
DV		 2731 if (INTEL_INFO(dev)->gen >= 4) {
2732 intel_crtc->dspaddr_offset =
bc752862 2733 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2734 pixel_size,
bc752862 2735 fb->pitches[0]);
c2c75131
DV		 2736 linear_offset -= intel_crtc->dspaddr_offset;
2737 } else {
e506a0c6 2738 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2739 }
e506a0c6 2740
8e7d688b 2741 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2742 dspcntr |= DISPPLANE_ROTATE_180;
2743
6e3c9717
ACO		 2744 x += (intel_crtc->config->pipe_src_w - 1);
2745 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2746
2747 /* Finding the last pixel of the last line of the display
2748 data and adding to linear_offset*/
2749 linear_offset +=
6e3c9717
ACO		 2750 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2751 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2752 }
2753
2754 I915_WRITE(reg, dspcntr);
2755
01f2c773 2756 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2757 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2758 I915_WRITE(DSPSURF(plane),
2759 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2760 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2761 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2762 } else
f343c5f6 2763 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2764 POSTING_READ(reg);
17638cd6
JB		 2765}
2766
29b9bde6
DV		 2767static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2768 struct drm_framebuffer *fb,
2769 int x, int y)
17638cd6
JB		 2770{
2771 struct drm_device *dev = crtc->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2774 struct drm_plane *primary = crtc->primary;
2775 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2776 struct drm_i915_gem_object *obj;
17638cd6 2777 int plane = intel_crtc->plane;
e506a0c6 2778 unsigned long linear_offset;
17638cd6 2779 u32 dspcntr;
f45651ba 2780 u32 reg = DSPCNTR(plane);
48404c1e 2781 int pixel_size;
f45651ba 2782
b70709a6 2783 if (!visible || !fb) {
fdd508a6
VS		 2784 I915_WRITE(reg, 0);
2785 I915_WRITE(DSPSURF(plane), 0);
2786 POSTING_READ(reg);
2787 return;
2788 }
2789
c9ba6fad
VS		 2790 obj = intel_fb_obj(fb);
2791 if (WARN_ON(obj == NULL))
2792 return;
2793
2794 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2795
f45651ba
VS		 2796 dspcntr = DISPPLANE_GAMMA_ENABLE;
2797
fdd508a6 2798 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2799
2800 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2801 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2802
57779d06
VS		 2803 switch (fb->pixel_format) {
2804 case DRM_FORMAT_C8:
17638cd6
JB		 2805 dspcntr |= DISPPLANE_8BPP;
2806 break;
57779d06
VS		 2807 case DRM_FORMAT_RGB565:
2808 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2809 break;
57779d06 2810 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX888;
2812 break;
2813 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2814 dspcntr |= DISPPLANE_RGBX888;
2815 break;
2816 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2817 dspcntr |= DISPPLANE_BGRX101010;
2818 break;
2819 case DRM_FORMAT_XBGR2101010:
57779d06 2820 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2821 break;
2822 default:
baba133a 2823 BUG();
17638cd6
JB		 2824 }
2825
2826 if (obj->tiling_mode != I915_TILING_NONE)
2827 dspcntr |= DISPPLANE_TILED;
17638cd6 2828
f45651ba 2829 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2830 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2831
b9897127 2832 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2833 intel_crtc->dspaddr_offset =
bc752862 2834 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2835 pixel_size,
bc752862 2836 fb->pitches[0]);
c2c75131 2837 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2838 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2839 dspcntr |= DISPPLANE_ROTATE_180;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2842 x += (intel_crtc->config->pipe_src_w - 1);
2843 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2844
2845 /* Finding the last pixel of the last line of the display
2846 data and adding to linear_offset*/
2847 linear_offset +=
6e3c9717
ACO		 2848 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2850 }
2851 }
2852
2853 I915_WRITE(reg, dspcntr);
17638cd6 2854
01f2c773 2855 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2856 I915_WRITE(DSPSURF(plane),
2857 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2858 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2859 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2860 } else {
2861 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862 I915_WRITE(DSPLINOFF(plane), linear_offset);
2863 }
17638cd6 2864 POSTING_READ(reg);
17638cd6
JB		 2865}
2866
b321803d
DL		 2867u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868 uint32_t pixel_format)
2869{
2870 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871
2872 /*
2873 * The stride is either expressed as a multiple of 64 bytes
2874 * chunks for linear buffers or in number of tiles for tiled
2875 * buffers.
2876 */
2877 switch (fb_modifier) {
2878 case DRM_FORMAT_MOD_NONE:
2879 return 64;
2880 case I915_FORMAT_MOD_X_TILED:
2881 if (INTEL_INFO(dev)->gen == 2)
2882 return 128;
2883 return 512;
2884 case I915_FORMAT_MOD_Y_TILED:
2885 /* No need to check for old gens and Y tiling since this is
2886 * about the display engine and those will be blocked before
2887 * we get here.
2888 */
2889 return 128;
2890 case I915_FORMAT_MOD_Yf_TILED:
2891 if (bits_per_pixel == 8)
2892 return 64;
2893 else
2894 return 128;
2895 default:
2896 MISSING_CASE(fb_modifier);
2897 return 64;
2898 }
2899}
2900
121920fa
TU		 2901unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902 struct drm_i915_gem_object *obj)
2903{
9abc4648 2904 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2905
2906 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2907 view = &i915_ggtt_view_rotated;
121920fa
TU		 2908
2909 return i915_gem_obj_ggtt_offset_view(obj, view);
2910}
2911
a1b2278e
CK		 2912/*
2913 * This function detaches (aka. unbinds) unused scalers in hardware
2914 */
2915void skl_detach_scalers(struct intel_crtc *intel_crtc)
2916{
2917 struct drm_device *dev;
2918 struct drm_i915_private *dev_priv;
2919 struct intel_crtc_scaler_state *scaler_state;
2920 int i;
2921
2922 if (!intel_crtc || !intel_crtc->config)
2923 return;
2924
2925 dev = intel_crtc->base.dev;
2926 dev_priv = dev->dev_private;
2927 scaler_state = &intel_crtc->config->scaler_state;
2928
2929 /* loop through and disable scalers that aren't in use */
2930 for (i = 0; i < intel_crtc->num_scalers; i++) {
2931 if (!scaler_state->scalers[i].in_use) {
2932 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2933 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2934 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2935 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2936 intel_crtc->base.base.id, intel_crtc->pipe, i);
2937 }
2938 }
2939}
2940
6156a456 2941u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2942{
6156a456 2943 switch (pixel_format) {
d161cf7a 2944 case DRM_FORMAT_C8:
c34ce3d1 2945 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2946 case DRM_FORMAT_RGB565:
c34ce3d1 2947 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2948 case DRM_FORMAT_XBGR8888:
c34ce3d1 2949 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2950 case DRM_FORMAT_XRGB8888:
c34ce3d1 2951 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2952 /*
2953 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2954 * to be already pre-multiplied. We need to add a knob (or a different
2955 * DRM_FORMAT) for user-space to configure that.
2956 */
f75fb42a 2957 case DRM_FORMAT_ABGR8888:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2959 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2960 case DRM_FORMAT_ARGB8888:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2962 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2963 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2964 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2965 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2966 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2967 case DRM_FORMAT_YUYV:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2969 case DRM_FORMAT_YVYU:
c34ce3d1 2970 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2971 case DRM_FORMAT_UYVY:
c34ce3d1 2972 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2973 case DRM_FORMAT_VYUY:
c34ce3d1 2974 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2975 default:
4249eeef 2976 MISSING_CASE(pixel_format);
70d21f0e 2977 }
8cfcba41 2978
c34ce3d1 2979 return 0;
6156a456 2980}
70d21f0e 2981
6156a456
CK		 2982u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2983{
6156a456 2984 switch (fb_modifier) {
30af77c4 2985 case DRM_FORMAT_MOD_NONE:
70d21f0e 2986 break;
30af77c4 2987 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2988 return PLANE_CTL_TILED_X;
b321803d 2989 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2990 return PLANE_CTL_TILED_Y;
b321803d 2991 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2992 return PLANE_CTL_TILED_YF;
70d21f0e 2993 default:
6156a456 2994 MISSING_CASE(fb_modifier);
70d21f0e 2995 }
8cfcba41 2996
c34ce3d1 2997 return 0;
6156a456 2998}
70d21f0e 2999
6156a456
CK		 3000u32 skl_plane_ctl_rotation(unsigned int rotation)
3001{
3b7a5119 3002 switch (rotation) {
6156a456
CK		 3003 case BIT(DRM_ROTATE_0):
3004 break;
1e8df167
SJ		 3005 /*
3006 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3007 * while i915 HW rotation is clockwise, thats why this swapping.
3008 */
3b7a5119 3009 case BIT(DRM_ROTATE_90):
1e8df167 3010 return PLANE_CTL_ROTATE_270;
3b7a5119 3011 case BIT(DRM_ROTATE_180):
c34ce3d1 3012 return PLANE_CTL_ROTATE_180;
3b7a5119 3013 case BIT(DRM_ROTATE_270):
1e8df167 3014 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3015 default:
3016 MISSING_CASE(rotation);
3017 }
3018
c34ce3d1 3019 return 0;
6156a456
CK		 3020}
3021
3022static void skylake_update_primary_plane(struct drm_crtc *crtc,
3023 struct drm_framebuffer *fb,
3024 int x, int y)
3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3029 struct drm_plane *plane = crtc->primary;
3030 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3031 struct drm_i915_gem_object *obj;
3032 int pipe = intel_crtc->pipe;
3033 u32 plane_ctl, stride_div, stride;
3034 u32 tile_height, plane_offset, plane_size;
3035 unsigned int rotation;
3036 int x_offset, y_offset;
3037 unsigned long surf_addr;
6156a456
CK		 3038 struct intel_crtc_state *crtc_state = intel_crtc->config;
3039 struct intel_plane_state *plane_state;
3040 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3041 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3042 int scaler_id = -1;
3043
6156a456
CK		 3044 plane_state = to_intel_plane_state(plane->state);
3045
b70709a6 3046 if (!visible || !fb) {
6156a456
CK		 3047 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3048 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3049 POSTING_READ(PLANE_CTL(pipe, 0));
3050 return;
3b7a5119 3051 }
70d21f0e 3052
6156a456
CK		 3053 plane_ctl = PLANE_CTL_ENABLE |
3054 PLANE_CTL_PIPE_GAMMA_ENABLE |
3055 PLANE_CTL_PIPE_CSC_ENABLE;
3056
3057 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3058 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3059 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3060
3061 rotation = plane->state->rotation;
3062 plane_ctl |= skl_plane_ctl_rotation(rotation);
3063
b321803d
DL		 3064 obj = intel_fb_obj(fb);
3065 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3066 fb->pixel_format);
3b7a5119
SJ		 3067 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3068
6156a456
CK		 3069 /*
3070 * FIXME: intel_plane_state->src, dst aren't set when transitional
3071 * update_plane helpers are called from legacy paths.
3072 * Once full atomic crtc is available, below check can be avoided.
3073 */
3074 if (drm_rect_width(&plane_state->src)) {
3075 scaler_id = plane_state->scaler_id;
3076 src_x = plane_state->src.x1 >> 16;
3077 src_y = plane_state->src.y1 >> 16;
3078 src_w = drm_rect_width(&plane_state->src) >> 16;
3079 src_h = drm_rect_height(&plane_state->src) >> 16;
3080 dst_x = plane_state->dst.x1;
3081 dst_y = plane_state->dst.y1;
3082 dst_w = drm_rect_width(&plane_state->dst);
3083 dst_h = drm_rect_height(&plane_state->dst);
3084
3085 WARN_ON(x != src_x || y != src_y);
3086 } else {
3087 src_w = intel_crtc->config->pipe_src_w;
3088 src_h = intel_crtc->config->pipe_src_h;
3089 }
3090
3b7a5119
SJ		 3091 if (intel_rotation_90_or_270(rotation)) {
3092 /* stride = Surface height in tiles */
2614f17d 3093 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3094 fb->modifier[0]);
3095 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3096 x_offset = stride * tile_height - y - src_h;
3b7a5119 3097 y_offset = x;
6156a456 3098 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3099 } else {
3100 stride = fb->pitches[0] / stride_div;
3101 x_offset = x;
3102 y_offset = y;
6156a456 3103 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3104 }
3105 plane_offset = y_offset << 16 | x_offset;
b321803d 3106
70d21f0e 3107 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3108 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3109 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3110 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3111
3112 if (scaler_id >= 0) {
3113 uint32_t ps_ctrl = 0;
3114
3115 WARN_ON(!dst_w || !dst_h);
3116 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3117 crtc_state->scaler_state.scalers[scaler_id].mode;
3118 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3119 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3120 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3121 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3122 I915_WRITE(PLANE_POS(pipe, 0), 0);
3123 } else {
3124 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3125 }
3126
121920fa 3127 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3128
3129 POSTING_READ(PLANE_SURF(pipe, 0));
3130}
3131
17638cd6
JB		 3132/* Assume fb object is pinned & idle & fenced and just update base pointers */
3133static int
3134intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3135 int x, int y, enum mode_set_atomic state)
3136{
3137 struct drm_device *dev = crtc->dev;
3138 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3139
6b8e6ed0
CW		 3140 if (dev_priv->display.disable_fbc)
3141 dev_priv->display.disable_fbc(dev);
81255565 3142
29b9bde6
DV		 3143 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3144
3145 return 0;
81255565
JB		 3146}
3147
7514747d 3148static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3149{
96a02917
VS		 3150 struct drm_crtc *crtc;
3151
70e1e0ec 3152 for_each_crtc(dev, crtc) {
96a02917
VS		 3153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154 enum plane plane = intel_crtc->plane;
3155
3156 intel_prepare_page_flip(dev, plane);
3157 intel_finish_page_flip_plane(dev, plane);
3158 }
7514747d
VS		 3159}
3160
3161static void intel_update_primary_planes(struct drm_device *dev)
3162{
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct drm_crtc *crtc;
96a02917 3165
70e1e0ec 3166 for_each_crtc(dev, crtc) {
96a02917
VS		 3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168
51fd371b 3169 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3170 /*
3171 * FIXME: Once we have proper support for primary planes (and
3172 * disabling them without disabling the entire crtc) allow again
66e514c1 3173 * a NULL crtc->primary->fb.
947fdaad 3174 */
f4510a27 3175 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3176 dev_priv->display.update_primary_plane(crtc,
66e514c1 3177 crtc->primary->fb,
262ca2b0
MR		 3178 crtc->x,
3179 crtc->y);
51fd371b 3180 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3181 }
3182}
3183
7514747d
VS		 3184void intel_prepare_reset(struct drm_device *dev)
3185{
3186 /* no reset support for gen2 */
3187 if (IS_GEN2(dev))
3188 return;
3189
3190 /* reset doesn't touch the display */
3191 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3192 return;
3193
3194 drm_modeset_lock_all(dev);
f98ce92f
VS		 3195 /*
3196 * Disabling the crtcs gracefully seems nicer. Also the
3197 * g33 docs say we should at least disable all the planes.
3198 */
6b72d486 3199 intel_display_suspend(dev);
7514747d
VS		 3200}
3201
3202void intel_finish_reset(struct drm_device *dev)
3203{
3204 struct drm_i915_private *dev_priv = to_i915(dev);
3205
3206 /*
3207 * Flips in the rings will be nuked by the reset,
3208 * so complete all pending flips so that user space
3209 * will get its events and not get stuck.
3210 */
3211 intel_complete_page_flips(dev);
3212
3213 /* no reset support for gen2 */
3214 if (IS_GEN2(dev))
3215 return;
3216
3217 /* reset doesn't touch the display */
3218 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3219 /*
3220 * Flips in the rings have been nuked by the reset,
3221 * so update the base address of all primary
3222 * planes to the the last fb to make sure we're
3223 * showing the correct fb after a reset.
3224 */
3225 intel_update_primary_planes(dev);
3226 return;
3227 }
3228
3229 /*
3230 * The display has been reset as well,
3231 * so need a full re-initialization.
3232 */
3233 intel_runtime_pm_disable_interrupts(dev_priv);
3234 intel_runtime_pm_enable_interrupts(dev_priv);
3235
3236 intel_modeset_init_hw(dev);
3237
3238 spin_lock_irq(&dev_priv->irq_lock);
3239 if (dev_priv->display.hpd_irq_setup)
3240 dev_priv->display.hpd_irq_setup(dev);
3241 spin_unlock_irq(&dev_priv->irq_lock);
3242
3243 intel_modeset_setup_hw_state(dev, true);
3244
3245 intel_hpd_init(dev_priv);
3246
3247 drm_modeset_unlock_all(dev);
3248}
3249
2e2f351d 3250static void
14667a4b
CW		 3251intel_finish_fb(struct drm_framebuffer *old_fb)
3252{
2ff8fde1 3253 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3254 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3255 bool was_interruptible = dev_priv->mm.interruptible;
3256 int ret;
3257
14667a4b
CW		 3258 /* Big Hammer, we also need to ensure that any pending
3259 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3260 * current scanout is retired before unpinning the old
2e2f351d
CW		 3261 * framebuffer. Note that we rely on userspace rendering
3262 * into the buffer attached to the pipe they are waiting
3263 * on. If not, userspace generates a GPU hang with IPEHR
3264 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3265 *
3266 * This should only fail upon a hung GPU, in which case we
3267 * can safely continue.
3268 */
3269 dev_priv->mm.interruptible = false;
2e2f351d 3270 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3271 dev_priv->mm.interruptible = was_interruptible;
3272
2e2f351d 3273 WARN_ON(ret);
14667a4b
CW		 3274}
3275
7d5e3799
CW		 3276static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3277{
3278 struct drm_device *dev = crtc->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3281 bool pending;
3282
3283 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3284 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3285 return false;
3286
5e2d7afc 3287 spin_lock_irq(&dev->event_lock);
7d5e3799 3288 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3289 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3290
3291 return pending;
3292}
3293
e30e8f75
GP		 3294static void intel_update_pipe_size(struct intel_crtc *crtc)
3295{
3296 struct drm_device *dev = crtc->base.dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 const struct drm_display_mode *adjusted_mode;
3299
3300 if (!i915.fastboot)
3301 return;
3302
3303 /*
3304 * Update pipe size and adjust fitter if needed: the reason for this is
3305 * that in compute_mode_changes we check the native mode (not the pfit
3306 * mode) to see if we can flip rather than do a full mode set. In the
3307 * fastboot case, we'll flip, but if we don't update the pipesrc and
3308 * pfit state, we'll end up with a big fb scanned out into the wrong
3309 * sized surface.
3310 *
3311 * To fix this properly, we need to hoist the checks up into
3312 * compute_mode_changes (or above), check the actual pfit state and
3313 * whether the platform allows pfit disable with pipe active, and only
3314 * then update the pipesrc and pfit state, even on the flip path.
3315 */
3316
6e3c9717 3317 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3318
3319 I915_WRITE(PIPESRC(crtc->pipe),
3320 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3321 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3322 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3323 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3324 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3325 I915_WRITE(PF_CTL(crtc->pipe), 0);
3326 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3327 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3328 }
6e3c9717
ACO		 3329 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3330 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3331}
3332
5e84e1a4
ZW		 3333static void intel_fdi_normal_train(struct drm_crtc *crtc)
3334{
3335 struct drm_device *dev = crtc->dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 int pipe = intel_crtc->pipe;
3339 u32 reg, temp;
3340
3341 /* enable normal train */
3342 reg = FDI_TX_CTL(pipe);
3343 temp = I915_READ(reg);
61e499bf 3344 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3347 } else {
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3350 }
5e84e1a4
ZW		 3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 if (HAS_PCH_CPT(dev)) {
3356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3358 } else {
3359 temp &= ~FDI_LINK_TRAIN_NONE;
3360 temp |= FDI_LINK_TRAIN_NONE;
3361 }
3362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3363
3364 /* wait one idle pattern time */
3365 POSTING_READ(reg);
3366 udelay(1000);
357555c0
JB		 3367
3368 /* IVB wants error correction enabled */
3369 if (IS_IVYBRIDGE(dev))
3370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3371 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3372}
3373
8db9d77b
ZW		 3374/* The FDI link training functions for ILK/Ibexpeak. */
3375static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3376{
3377 struct drm_device *dev = crtc->dev;
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3380 int pipe = intel_crtc->pipe;
5eddb70b 3381 u32 reg, temp, tries;
8db9d77b 3382
1c8562f6 3383 /* FDI needs bits from pipe first */
0fc932b8 3384 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3385
e1a44743
AJ		 3386 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3387 for train result */
5eddb70b
CW		 3388 reg = FDI_RX_IMR(pipe);
3389 temp = I915_READ(reg);
e1a44743
AJ		 3390 temp &= ~FDI_RX_SYMBOL_LOCK;
3391 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3392 I915_WRITE(reg, temp);
3393 I915_READ(reg);
e1a44743
AJ		 3394 udelay(150);
3395
8db9d77b 3396 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
627eb5a3 3399 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3400 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3403 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3404
5eddb70b
CW		 3405 reg = FDI_RX_CTL(pipe);
3406 temp = I915_READ(reg);
8db9d77b
ZW		 3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3409 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3410
3411 POSTING_READ(reg);
8db9d77b
ZW		 3412 udelay(150);
3413
5b2adf89 3414 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3417 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3418
5eddb70b 3419 reg = FDI_RX_IIR(pipe);
e1a44743 3420 for (tries = 0; tries < 5; tries++) {
5eddb70b 3421 temp = I915_READ(reg);
8db9d77b
ZW		 3422 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3423
3424 if ((temp & FDI_RX_BIT_LOCK)) {
3425 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3426 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3427 break;
3428 }
8db9d77b 3429 }
e1a44743 3430 if (tries == 5)
5eddb70b 3431 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3432
3433 /* Train 2 */
5eddb70b
CW		 3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
8db9d77b
ZW		 3436 temp &= ~FDI_LINK_TRAIN_NONE;
3437 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3438 I915_WRITE(reg, temp);
8db9d77b 3439
5eddb70b
CW		 3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
8db9d77b
ZW		 3442 temp &= ~FDI_LINK_TRAIN_NONE;
3443 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3444 I915_WRITE(reg, temp);
8db9d77b 3445
5eddb70b
CW		 3446 POSTING_READ(reg);
3447 udelay(150);
8db9d77b 3448
5eddb70b 3449 reg = FDI_RX_IIR(pipe);
e1a44743 3450 for (tries = 0; tries < 5; tries++) {
5eddb70b 3451 temp = I915_READ(reg);
8db9d77b
ZW		 3452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3453
3454 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3455 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3456 DRM_DEBUG_KMS("FDI train 2 done.\n");
3457 break;
3458 }
8db9d77b 3459 }
e1a44743 3460 if (tries == 5)
5eddb70b 3461 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3462
3463 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3464
8db9d77b
ZW		 3465}
3466
0206e353 3467static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3468 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3469 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3470 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3471 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3472};
3473
3474/* The FDI link training functions for SNB/Cougarpoint. */
3475static void gen6_fdi_link_train(struct drm_crtc *crtc)
3476{
3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 int pipe = intel_crtc->pipe;
fa37d39e 3481 u32 reg, temp, i, retry;
8db9d77b 3482
e1a44743
AJ		 3483 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3484 for train result */
5eddb70b
CW		 3485 reg = FDI_RX_IMR(pipe);
3486 temp = I915_READ(reg);
e1a44743
AJ		 3487 temp &= ~FDI_RX_SYMBOL_LOCK;
3488 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3489 I915_WRITE(reg, temp);
3490
3491 POSTING_READ(reg);
e1a44743
AJ		 3492 udelay(150);
3493
8db9d77b 3494 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3495 reg = FDI_TX_CTL(pipe);
3496 temp = I915_READ(reg);
627eb5a3 3497 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3498 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3499 temp &= ~FDI_LINK_TRAIN_NONE;
3500 temp |= FDI_LINK_TRAIN_PATTERN_1;
3501 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3502 /* SNB-B */
3503 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3504 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3505
d74cf324
DV		 3506 I915_WRITE(FDI_RX_MISC(pipe),
3507 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3508
5eddb70b
CW		 3509 reg = FDI_RX_CTL(pipe);
3510 temp = I915_READ(reg);
8db9d77b
ZW		 3511 if (HAS_PCH_CPT(dev)) {
3512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3514 } else {
3515 temp &= ~FDI_LINK_TRAIN_NONE;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1;
3517 }
5eddb70b
CW		 3518 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3519
3520 POSTING_READ(reg);
8db9d77b
ZW		 3521 udelay(150);
3522
0206e353 3523 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3524 reg = FDI_TX_CTL(pipe);
3525 temp = I915_READ(reg);
8db9d77b
ZW		 3526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3527 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3528 I915_WRITE(reg, temp);
3529
3530 POSTING_READ(reg);
8db9d77b
ZW		 3531 udelay(500);
3532
fa37d39e
SP		 3533 for (retry = 0; retry < 5; retry++) {
3534 reg = FDI_RX_IIR(pipe);
3535 temp = I915_READ(reg);
3536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3537 if (temp & FDI_RX_BIT_LOCK) {
3538 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3539 DRM_DEBUG_KMS("FDI train 1 done.\n");
3540 break;
3541 }
3542 udelay(50);
8db9d77b 3543 }
fa37d39e
SP		 3544 if (retry < 5)
3545 break;
8db9d77b
ZW		 3546 }
3547 if (i == 4)
5eddb70b 3548 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3549
3550 /* Train 2 */
5eddb70b
CW		 3551 reg = FDI_TX_CTL(pipe);
3552 temp = I915_READ(reg);
8db9d77b
ZW		 3553 temp &= ~FDI_LINK_TRAIN_NONE;
3554 temp |= FDI_LINK_TRAIN_PATTERN_2;
3555 if (IS_GEN6(dev)) {
3556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3557 /* SNB-B */
3558 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3559 }
5eddb70b 3560 I915_WRITE(reg, temp);
8db9d77b 3561
5eddb70b
CW		 3562 reg = FDI_RX_CTL(pipe);
3563 temp = I915_READ(reg);
8db9d77b
ZW		 3564 if (HAS_PCH_CPT(dev)) {
3565 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3566 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3567 } else {
3568 temp &= ~FDI_LINK_TRAIN_NONE;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2;
3570 }
5eddb70b
CW		 3571 I915_WRITE(reg, temp);
3572
3573 POSTING_READ(reg);
8db9d77b
ZW		 3574 udelay(150);
3575
0206e353 3576 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3577 reg = FDI_TX_CTL(pipe);
3578 temp = I915_READ(reg);
8db9d77b
ZW		 3579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3580 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
8db9d77b
ZW		 3584 udelay(500);
3585
fa37d39e
SP		 3586 for (retry = 0; retry < 5; retry++) {
3587 reg = FDI_RX_IIR(pipe);
3588 temp = I915_READ(reg);
3589 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3590 if (temp & FDI_RX_SYMBOL_LOCK) {
3591 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3592 DRM_DEBUG_KMS("FDI train 2 done.\n");
3593 break;
3594 }
3595 udelay(50);
8db9d77b 3596 }
fa37d39e
SP		 3597 if (retry < 5)
3598 break;
8db9d77b
ZW		 3599 }
3600 if (i == 4)
5eddb70b 3601 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3602
3603 DRM_DEBUG_KMS("FDI train done.\n");
3604}
3605
357555c0
JB		 3606/* Manual link training for Ivy Bridge A0 parts */
3607static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3608{
3609 struct drm_device *dev = crtc->dev;
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 int pipe = intel_crtc->pipe;
139ccd3f 3613 u32 reg, temp, i, j;
357555c0
JB		 3614
3615 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3616 for train result */
3617 reg = FDI_RX_IMR(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~FDI_RX_SYMBOL_LOCK;
3620 temp &= ~FDI_RX_BIT_LOCK;
3621 I915_WRITE(reg, temp);
3622
3623 POSTING_READ(reg);
3624 udelay(150);
3625
01a415fd
DV		 3626 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3627 I915_READ(FDI_RX_IIR(pipe)));
3628
139ccd3f
JB		 3629 /* Try each vswing and preemphasis setting twice before moving on */
3630 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3631 /* disable first in case we need to retry */
3632 reg = FDI_TX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3635 temp &= ~FDI_TX_ENABLE;
3636 I915_WRITE(reg, temp);
357555c0 3637
139ccd3f
JB		 3638 reg = FDI_RX_CTL(pipe);
3639 temp = I915_READ(reg);
3640 temp &= ~FDI_LINK_TRAIN_AUTO;
3641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3642 temp &= ~FDI_RX_ENABLE;
3643 I915_WRITE(reg, temp);
357555c0 3644
139ccd3f 3645 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3646 reg = FDI_TX_CTL(pipe);
3647 temp = I915_READ(reg);
139ccd3f 3648 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3649 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3650 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3652 temp |= snb_b_fdi_train_param[j/2];
3653 temp |= FDI_COMPOSITE_SYNC;
3654 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3655
139ccd3f
JB		 3656 I915_WRITE(FDI_RX_MISC(pipe),
3657 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3658
139ccd3f 3659 reg = FDI_RX_CTL(pipe);
357555c0 3660 temp = I915_READ(reg);
139ccd3f
JB		 3661 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3662 temp |= FDI_COMPOSITE_SYNC;
3663 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3664
139ccd3f
JB		 3665 POSTING_READ(reg);
3666 udelay(1); /* should be 0.5us */
357555c0 3667
139ccd3f
JB		 3668 for (i = 0; i < 4; i++) {
3669 reg = FDI_RX_IIR(pipe);
3670 temp = I915_READ(reg);
3671 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3672
139ccd3f
JB		 3673 if (temp & FDI_RX_BIT_LOCK ||
3674 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3675 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3676 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3677 i);
3678 break;
3679 }
3680 udelay(1); /* should be 0.5us */
3681 }
3682 if (i == 4) {
3683 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3684 continue;
3685 }
357555c0 3686
139ccd3f 3687 /* Train 2 */
357555c0
JB		 3688 reg = FDI_TX_CTL(pipe);
3689 temp = I915_READ(reg);
139ccd3f
JB		 3690 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3691 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3692 I915_WRITE(reg, temp);
3693
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3697 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3698 I915_WRITE(reg, temp);
3699
3700 POSTING_READ(reg);
139ccd3f 3701 udelay(2); /* should be 1.5us */
357555c0 3702
139ccd3f
JB		 3703 for (i = 0; i < 4; i++) {
3704 reg = FDI_RX_IIR(pipe);
3705 temp = I915_READ(reg);
3706 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3707
139ccd3f
JB		 3708 if (temp & FDI_RX_SYMBOL_LOCK ||
3709 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3711 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3712 i);
3713 goto train_done;
3714 }
3715 udelay(2); /* should be 1.5us */
357555c0 3716 }
139ccd3f
JB		 3717 if (i == 4)
3718 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3719 }
357555c0 3720
139ccd3f 3721train_done:
357555c0
JB		 3722 DRM_DEBUG_KMS("FDI train done.\n");
3723}
3724
88cefb6c 3725static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3726{
88cefb6c 3727 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3728 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3729 int pipe = intel_crtc->pipe;
5eddb70b 3730 u32 reg, temp;
79e53945 3731
c64e311e 3732
c98e9dcf 3733 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3734 reg = FDI_RX_CTL(pipe);
3735 temp = I915_READ(reg);
627eb5a3 3736 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3737 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3738 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3739 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3740
3741 POSTING_READ(reg);
c98e9dcf
JB		 3742 udelay(200);
3743
3744 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3745 temp = I915_READ(reg);
3746 I915_WRITE(reg, temp | FDI_PCDCLK);
3747
3748 POSTING_READ(reg);
c98e9dcf
JB		 3749 udelay(200);
3750
20749730
PZ		 3751 /* Enable CPU FDI TX PLL, always on for Ironlake */
3752 reg = FDI_TX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3755 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3756
20749730
PZ		 3757 POSTING_READ(reg);
3758 udelay(100);
6be4a607 3759 }
0e23b99d
JB		 3760}
3761
88cefb6c
DV		 3762static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3763{
3764 struct drm_device *dev = intel_crtc->base.dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 int pipe = intel_crtc->pipe;
3767 u32 reg, temp;
3768
3769 /* Switch from PCDclk to Rawclk */
3770 reg = FDI_RX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3773
3774 /* Disable CPU FDI TX PLL */
3775 reg = FDI_TX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3778
3779 POSTING_READ(reg);
3780 udelay(100);
3781
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3785
3786 /* Wait for the clocks to turn off. */
3787 POSTING_READ(reg);
3788 udelay(100);
3789}
3790
0fc932b8
JB		 3791static void ironlake_fdi_disable(struct drm_crtc *crtc)
3792{
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796 int pipe = intel_crtc->pipe;
3797 u32 reg, temp;
3798
3799 /* disable CPU FDI tx and PCH FDI rx */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3803 POSTING_READ(reg);
3804
3805 reg = FDI_RX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 temp &= ~(0x7 << 16);
dfd07d72 3808 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3809 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3810
3811 POSTING_READ(reg);
3812 udelay(100);
3813
3814 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3815 if (HAS_PCH_IBX(dev))
6f06ce18 3816 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3817
3818 /* still set train pattern 1 */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 temp &= ~FDI_LINK_TRAIN_NONE;
3822 temp |= FDI_LINK_TRAIN_PATTERN_1;
3823 I915_WRITE(reg, temp);
3824
3825 reg = FDI_RX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 if (HAS_PCH_CPT(dev)) {
3828 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3829 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3830 } else {
3831 temp &= ~FDI_LINK_TRAIN_NONE;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1;
3833 }
3834 /* BPC in FDI rx is consistent with that in PIPECONF */
3835 temp &= ~(0x07 << 16);
dfd07d72 3836 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3837 I915_WRITE(reg, temp);
3838
3839 POSTING_READ(reg);
3840 udelay(100);
3841}
3842
5dce5b93
CW		 3843bool intel_has_pending_fb_unpin(struct drm_device *dev)
3844{
3845 struct intel_crtc *crtc;
3846
3847 /* Note that we don't need to be called with mode_config.lock here
3848 * as our list of CRTC objects is static for the lifetime of the
3849 * device and so cannot disappear as we iterate. Similarly, we can
3850 * happily treat the predicates as racy, atomic checks as userspace
3851 * cannot claim and pin a new fb without at least acquring the
3852 * struct_mutex and so serialising with us.
3853 */
d3fcc808 3854 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3855 if (atomic_read(&crtc->unpin_work_count) == 0)
3856 continue;
3857
3858 if (crtc->unpin_work)
3859 intel_wait_for_vblank(dev, crtc->pipe);
3860
3861 return true;
3862 }
3863
3864 return false;
3865}
3866
d6bbafa1
CW		 3867static void page_flip_completed(struct intel_crtc *intel_crtc)
3868{
3869 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3870 struct intel_unpin_work *work = intel_crtc->unpin_work;
3871
3872 /* ensure that the unpin work is consistent wrt ->pending. */
3873 smp_rmb();
3874 intel_crtc->unpin_work = NULL;
3875
3876 if (work->event)
3877 drm_send_vblank_event(intel_crtc->base.dev,
3878 intel_crtc->pipe,
3879 work->event);
3880
3881 drm_crtc_vblank_put(&intel_crtc->base);
3882
3883 wake_up_all(&dev_priv->pending_flip_queue);
3884 queue_work(dev_priv->wq, &work->work);
3885
3886 trace_i915_flip_complete(intel_crtc->plane,
3887 work->pending_flip_obj);
3888}
3889
46a55d30 3890void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3891{
0f91128d 3892 struct drm_device *dev = crtc->dev;
5bb61643 3893 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3894
2c10d571 3895 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3896 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3897 !intel_crtc_has_pending_flip(crtc),
3898 60*HZ) == 0)) {
3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3900
5e2d7afc 3901 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3902 if (intel_crtc->unpin_work) {
3903 WARN_ONCE(1, "Removing stuck page flip\n");
3904 page_flip_completed(intel_crtc);
3905 }
5e2d7afc 3906 spin_unlock_irq(&dev->event_lock);
9c787942 3907 }
5bb61643 3908
975d568a
CW		 3909 if (crtc->primary->fb) {
3910 mutex_lock(&dev->struct_mutex);
3911 intel_finish_fb(crtc->primary->fb);
3912 mutex_unlock(&dev->struct_mutex);
3913 }
e6c3a2a6
CW		 3914}
3915
e615efe4
ED		 3916/* Program iCLKIP clock to the desired frequency */
3917static void lpt_program_iclkip(struct drm_crtc *crtc)
3918{
3919 struct drm_device *dev = crtc->dev;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3921 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3922 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3923 u32 temp;
3924
a580516d 3925 mutex_lock(&dev_priv->sb_lock);
09153000 3926
e615efe4
ED		 3927 /* It is necessary to ungate the pixclk gate prior to programming
3928 * the divisors, and gate it back when it is done.
3929 */
3930 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3931
3932 /* Disable SSCCTL */
3933 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3934 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3935 SBI_SSCCTL_DISABLE,
3936 SBI_ICLK);
e615efe4
ED		 3937
3938 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3939 if (clock == 20000) {
e615efe4
ED		 3940 auxdiv = 1;
3941 divsel = 0x41;
3942 phaseinc = 0x20;
3943 } else {
3944 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3945 * but the adjusted_mode->crtc_clock in in KHz. To get the
3946 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3947 * convert the virtual clock precision to KHz here for higher
3948 * precision.
3949 */
3950 u32 iclk_virtual_root_freq = 172800 * 1000;
3951 u32 iclk_pi_range = 64;
3952 u32 desired_divisor, msb_divisor_value, pi_value;
3953
12d7ceed 3954 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3955 msb_divisor_value = desired_divisor / iclk_pi_range;
3956 pi_value = desired_divisor % iclk_pi_range;
3957
3958 auxdiv = 0;
3959 divsel = msb_divisor_value - 2;
3960 phaseinc = pi_value;
3961 }
3962
3963 /* This should not happen with any sane values */
3964 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3965 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3966 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3967 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3968
3969 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3970 clock,
e615efe4
ED		 3971 auxdiv,
3972 divsel,
3973 phasedir,
3974 phaseinc);
3975
3976 /* Program SSCDIVINTPHASE6 */
988d6ee8 3977 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3978 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3979 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3980 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3981 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3982 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3983 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3984 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3985
3986 /* Program SSCAUXDIV */
988d6ee8 3987 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3988 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3989 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3990 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3991
3992 /* Enable modulator and associated divider */
988d6ee8 3993 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3994 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3995 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3996
3997 /* Wait for initialization time */
3998 udelay(24);
3999
4000 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4001
a580516d 4002 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4003}
4004
275f01b2
DV		 4005static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4006 enum pipe pch_transcoder)
4007{
4008 struct drm_device *dev = crtc->base.dev;
4009 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4010 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4011
4012 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4013 I915_READ(HTOTAL(cpu_transcoder)));
4014 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4015 I915_READ(HBLANK(cpu_transcoder)));
4016 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4017 I915_READ(HSYNC(cpu_transcoder)));
4018
4019 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4020 I915_READ(VTOTAL(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4022 I915_READ(VBLANK(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4024 I915_READ(VSYNC(cpu_transcoder)));
4025 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4026 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4027}
4028
003632d9 4029static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4030{
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 uint32_t temp;
4033
4034 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4035 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4036 return;
4037
4038 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4039 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4040
003632d9
ACO		 4041 temp &= ~FDI_BC_BIFURCATION_SELECT;
4042 if (enable)
4043 temp |= FDI_BC_BIFURCATION_SELECT;
4044
4045 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4046 I915_WRITE(SOUTH_CHICKEN1, temp);
4047 POSTING_READ(SOUTH_CHICKEN1);
4048}
4049
4050static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4051{
4052 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4053
4054 switch (intel_crtc->pipe) {
4055 case PIPE_A:
4056 break;
4057 case PIPE_B:
6e3c9717 4058 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4059 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4060 else
003632d9 4061 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4062
4063 break;
4064 case PIPE_C:
003632d9 4065 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4066
4067 break;
4068 default:
4069 BUG();
4070 }
4071}
4072
f67a559d
JB		 4073/*
4074 * Enable PCH resources required for PCH ports:
4075 * - PCH PLLs
4076 * - FDI training & RX/TX
4077 * - update transcoder timings
4078 * - DP transcoding bits
4079 * - transcoder
4080 */
4081static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4082{
4083 struct drm_device *dev = crtc->dev;
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4086 int pipe = intel_crtc->pipe;
ee7b9f93 4087 u32 reg, temp;
2c07245f 4088
ab9412ba 4089 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4090
1fbc0d78
DV		 4091 if (IS_IVYBRIDGE(dev))
4092 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4093
cd986abb
DV		 4094 /* Write the TU size bits before fdi link training, so that error
4095 * detection works. */
4096 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4097 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4098
c98e9dcf 4099 /* For PCH output, training FDI link */
674cf967 4100 dev_priv->display.fdi_link_train(crtc);
2c07245f 4101
3ad8a208
DV		 4102 /* We need to program the right clock selection before writing the pixel
4103 * mutliplier into the DPLL. */
303b81e0 4104 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4105 u32 sel;
4b645f14 4106
c98e9dcf 4107 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4108 temp |= TRANS_DPLL_ENABLE(pipe);
4109 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4110 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4111 temp |= sel;
4112 else
4113 temp &= ~sel;
c98e9dcf 4114 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4115 }
5eddb70b 4116
3ad8a208
DV		 4117 /* XXX: pch pll's can be enabled any time before we enable the PCH
4118 * transcoder, and we actually should do this to not upset any PCH
4119 * transcoder that already use the clock when we share it.
4120 *
4121 * Note that enable_shared_dpll tries to do the right thing, but
4122 * get_shared_dpll unconditionally resets the pll - we need that to have
4123 * the right LVDS enable sequence. */
85b3894f 4124 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4125
d9b6cb56
JB		 4126 /* set transcoder timing, panel must allow it */
4127 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4128 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4129
303b81e0 4130 intel_fdi_normal_train(crtc);
5e84e1a4 4131
c98e9dcf 4132 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4133 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4134 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4135 reg = TRANS_DP_CTL(pipe);
4136 temp = I915_READ(reg);
4137 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4138 TRANS_DP_SYNC_MASK |
4139 TRANS_DP_BPC_MASK);
e3ef4479 4140 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4141 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4142
4143 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4144 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4145 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4146 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4147
4148 switch (intel_trans_dp_port_sel(crtc)) {
4149 case PCH_DP_B:
5eddb70b 4150 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4151 break;
4152 case PCH_DP_C:
5eddb70b 4153 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4154 break;
4155 case PCH_DP_D:
5eddb70b 4156 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4157 break;
4158 default:
e95d41e1 4159 BUG();
32f9d658 4160 }
2c07245f 4161
5eddb70b 4162 I915_WRITE(reg, temp);
6be4a607 4163 }
b52eb4dc 4164
b8a4f404 4165 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4166}
4167
1507e5bd
PZ		 4168static void lpt_pch_enable(struct drm_crtc *crtc)
4169{
4170 struct drm_device *dev = crtc->dev;
4171 struct drm_i915_private *dev_priv = dev->dev_private;
4172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4173 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4174
ab9412ba 4175 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4176
8c52b5e8 4177 lpt_program_iclkip(crtc);
1507e5bd 4178
0540e488 4179 /* Set transcoder timing. */
275f01b2 4180 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4181
937bb610 4182 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4183}
4184
190f68c5
ACO		 4185struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4186 struct intel_crtc_state *crtc_state)
ee7b9f93 4187{
e2b78267 4188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4189 struct intel_shared_dpll *pll;
e2b78267 4190 enum intel_dpll_id i;
ee7b9f93 4191
98b6bd99
DV		 4192 if (HAS_PCH_IBX(dev_priv->dev)) {
4193 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4194 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4195 pll = &dev_priv->shared_dplls[i];
98b6bd99 4196
46edb027
DV		 4197 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4198 crtc->base.base.id, pll->name);
98b6bd99 4199
8bd31e67 4200 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4201
98b6bd99
DV		 4202 goto found;
4203 }
4204
bcddf610
S		 4205 if (IS_BROXTON(dev_priv->dev)) {
4206 /* PLL is attached to port in bxt */
4207 struct intel_encoder *encoder;
4208 struct intel_digital_port *intel_dig_port;
4209
4210 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4211 if (WARN_ON(!encoder))
4212 return NULL;
4213
4214 intel_dig_port = enc_to_dig_port(&encoder->base);
4215 /* 1:1 mapping between ports and PLLs */
4216 i = (enum intel_dpll_id)intel_dig_port->port;
4217 pll = &dev_priv->shared_dplls[i];
4218 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4219 crtc->base.base.id, pll->name);
4220 WARN_ON(pll->new_config->crtc_mask);
4221
4222 goto found;
4223 }
4224
e72f9fbf
DV		 4225 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4226 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4227
4228 /* Only want to check enabled timings first */
8bd31e67 4229 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4230 continue;
4231
190f68c5 4232 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4233 &pll->new_config->hw_state,
4234 sizeof(pll->new_config->hw_state)) == 0) {
4235 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4236 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4237 pll->new_config->crtc_mask,
4238 pll->active);
ee7b9f93
JB		 4239 goto found;
4240 }
4241 }
4242
4243 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
8bd31e67 4246 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4247 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4248 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4249 goto found;
4250 }
4251 }
4252
4253 return NULL;
4254
4255found:
8bd31e67 4256 if (pll->new_config->crtc_mask == 0)
190f68c5 4257 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4258
190f68c5 4259 crtc_state->shared_dpll = i;
46edb027
DV		 4260 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4261 pipe_name(crtc->pipe));
ee7b9f93 4262
8bd31e67 4263 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4264
ee7b9f93
JB		 4265 return pll;
4266}
4267
8bd31e67
ACO		 4268/**
4269 * intel_shared_dpll_start_config - start a new PLL staged config
4270 * @dev_priv: DRM device
4271 * @clear_pipes: mask of pipes that will have their PLLs freed
4272 *
4273 * Starts a new PLL staged config, copying the current config but
4274 * releasing the references of pipes specified in clear_pipes.
4275 */
4276static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4277 unsigned clear_pipes)
4278{
4279 struct intel_shared_dpll *pll;
4280 enum intel_dpll_id i;
4281
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284
4285 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4286 GFP_KERNEL);
4287 if (!pll->new_config)
4288 goto cleanup;
4289
4290 pll->new_config->crtc_mask &= ~clear_pipes;
4291 }
4292
4293 return 0;
4294
4295cleanup:
4296 while (--i >= 0) {
4297 pll = &dev_priv->shared_dplls[i];
f354d733 4298 kfree(pll->new_config);
8bd31e67
ACO		 4299 pll->new_config = NULL;
4300 }
4301
4302 return -ENOMEM;
4303}
4304
4305static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4306{
4307 struct intel_shared_dpll *pll;
4308 enum intel_dpll_id i;
4309
4310 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4311 pll = &dev_priv->shared_dplls[i];
4312
4313 WARN_ON(pll->new_config == &pll->config);
4314
4315 pll->config = *pll->new_config;
4316 kfree(pll->new_config);
4317 pll->new_config = NULL;
4318 }
4319}
4320
4321static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4322{
4323 struct intel_shared_dpll *pll;
4324 enum intel_dpll_id i;
4325
4326 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4327 pll = &dev_priv->shared_dplls[i];
4328
4329 WARN_ON(pll->new_config == &pll->config);
4330
4331 kfree(pll->new_config);
4332 pll->new_config = NULL;
4333 }
4334}
4335
a1520318 4336static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4337{
4338 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4339 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4340 u32 temp;
4341
4342 temp = I915_READ(dslreg);
4343 udelay(500);
4344 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4345 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4346 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4347 }
4348}
4349
a1b2278e
CK		 4350/**
4351 * skl_update_scaler_users - Stages update to crtc's scaler state
4352 * @intel_crtc: crtc
4353 * @crtc_state: crtc_state
4354 * @plane: plane (NULL indicates crtc is requesting update)
4355 * @plane_state: plane's state
4356 * @force_detach: request unconditional detachment of scaler
4357 *
4358 * This function updates scaler state for requested plane or crtc.
4359 * To request scaler usage update for a plane, caller shall pass plane pointer.
4360 * To request scaler usage update for crtc, caller shall pass plane pointer
4361 * as NULL.
4362 *
4363 * Return
4364 * 0 - scaler_usage updated successfully
4365 * error - requested scaling cannot be supported or other error condition
4366 */
4367int
4368skl_update_scaler_users(
4369 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4370 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4371 int force_detach)
4372{
4373 int need_scaling;
4374 int idx;
4375 int src_w, src_h, dst_w, dst_h;
4376 int *scaler_id;
4377 struct drm_framebuffer *fb;
4378 struct intel_crtc_scaler_state *scaler_state;
6156a456 4379 unsigned int rotation;
a1b2278e
CK		 4380
4381 if (!intel_crtc || !crtc_state)
4382 return 0;
4383
4384 scaler_state = &crtc_state->scaler_state;
4385
4386 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4387 fb = intel_plane ? plane_state->base.fb : NULL;
4388
4389 if (intel_plane) {
4390 src_w = drm_rect_width(&plane_state->src) >> 16;
4391 src_h = drm_rect_height(&plane_state->src) >> 16;
4392 dst_w = drm_rect_width(&plane_state->dst);
4393 dst_h = drm_rect_height(&plane_state->dst);
4394 scaler_id = &plane_state->scaler_id;
6156a456 4395 rotation = plane_state->base.rotation;
a1b2278e
CK		 4396 } else {
4397 struct drm_display_mode *adjusted_mode =
4398 &crtc_state->base.adjusted_mode;
4399 src_w = crtc_state->pipe_src_w;
4400 src_h = crtc_state->pipe_src_h;
4401 dst_w = adjusted_mode->hdisplay;
4402 dst_h = adjusted_mode->vdisplay;
4403 scaler_id = &scaler_state->scaler_id;
6156a456 4404 rotation = DRM_ROTATE_0;
a1b2278e 4405 }
6156a456
CK		 4406
4407 need_scaling = intel_rotation_90_or_270(rotation) ?
4408 (src_h != dst_w || src_w != dst_h):
4409 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4410
4411 /*
4412 * if plane is being disabled or scaler is no more required or force detach
4413 * - free scaler binded to this plane/crtc
4414 * - in order to do this, update crtc->scaler_usage
4415 *
4416 * Here scaler state in crtc_state is set free so that
4417 * scaler can be assigned to other user. Actual register
4418 * update to free the scaler is done in plane/panel-fit programming.
4419 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4420 */
4421 if (force_detach || !need_scaling || (intel_plane &&
4422 (!fb || !plane_state->visible))) {
4423 if (*scaler_id >= 0) {
4424 scaler_state->scaler_users &= ~(1 << idx);
4425 scaler_state->scalers[*scaler_id].in_use = 0;
4426
4427 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4428 "crtc_state = %p scaler_users = 0x%x\n",
4429 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4430 intel_plane ? intel_plane->base.base.id :
4431 intel_crtc->base.base.id, crtc_state,
4432 scaler_state->scaler_users);
4433 *scaler_id = -1;
4434 }
4435 return 0;
4436 }
4437
4438 /* range checks */
4439 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4440 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4441
4442 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4443 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4444 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4445 "size is out of scaler range\n",
4446 intel_plane ? "PLANE" : "CRTC",
4447 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4448 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4449 return -EINVAL;
4450 }
4451
4452 /* check colorkey */
225c228a
CK		 4453 if (WARN_ON(intel_plane &&
4454 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4455 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4456 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4457 return -EINVAL;
4458 }
4459
4460 /* Check src format */
4461 if (intel_plane) {
4462 switch (fb->pixel_format) {
4463 case DRM_FORMAT_RGB565:
4464 case DRM_FORMAT_XBGR8888:
4465 case DRM_FORMAT_XRGB8888:
4466 case DRM_FORMAT_ABGR8888:
4467 case DRM_FORMAT_ARGB8888:
4468 case DRM_FORMAT_XRGB2101010:
a1b2278e 4469 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4470 case DRM_FORMAT_YUYV:
4471 case DRM_FORMAT_YVYU:
4472 case DRM_FORMAT_UYVY:
4473 case DRM_FORMAT_VYUY:
4474 break;
4475 default:
4476 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4477 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4478 return -EINVAL;
4479 }
4480 }
4481
4482 /* mark this plane as a scaler user in crtc_state */
4483 scaler_state->scaler_users |= (1 << idx);
4484 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4485 "crtc_state = %p scaler_users = 0x%x\n",
4486 intel_plane ? "PLANE" : "CRTC",
4487 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4488 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4489 return 0;
4490}
4491
4492static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4493{
4494 struct drm_device *dev = crtc->base.dev;
4495 struct drm_i915_private *dev_priv = dev->dev_private;
4496 int pipe = crtc->pipe;
a1b2278e
CK		 4497 struct intel_crtc_scaler_state *scaler_state =
4498 &crtc->config->scaler_state;
4499
4500 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4501
4502 /* To update pfit, first update scaler state */
4503 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4504 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4505 skl_detach_scalers(crtc);
4506 if (!enable)
4507 return;
bd2e244f 4508
6e3c9717 4509 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4510 int id;
4511
4512 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4513 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4514 return;
4515 }
4516
4517 id = scaler_state->scaler_id;
4518 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4519 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4520 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4521 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4522
4523 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4524 }
4525}
4526
b074cec8
JB		 4527static void ironlake_pfit_enable(struct intel_crtc *crtc)
4528{
4529 struct drm_device *dev = crtc->base.dev;
4530 struct drm_i915_private *dev_priv = dev->dev_private;
4531 int pipe = crtc->pipe;
4532
6e3c9717 4533 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4534 /* Force use of hard-coded filter coefficients
4535 * as some pre-programmed values are broken,
4536 * e.g. x201.
4537 */
4538 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4539 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4540 PF_PIPE_SEL_IVB(pipe));
4541 else
4542 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4543 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4544 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4545 }
4546}
4547
4a3b8769 4548static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4549{
4550 struct drm_device *dev = crtc->dev;
4551 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4552 struct drm_plane *plane;
bb53d4ae
VS		 4553 struct intel_plane *intel_plane;
4554
af2b653b
MR		 4555 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4556 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4557 if (intel_plane->pipe == pipe)
4558 intel_plane_restore(&intel_plane->base);
af2b653b 4559 }
bb53d4ae
VS		 4560}
4561
20bc8673 4562void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4563{
cea165c3
VS		 4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4566
6e3c9717 4567 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4568 return;
4569
cea165c3
VS		 4570 /* We can only enable IPS after we enable a plane and wait for a vblank */
4571 intel_wait_for_vblank(dev, crtc->pipe);
4572
d77e4531 4573 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4574 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4575 mutex_lock(&dev_priv->rps.hw_lock);
4576 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578 /* Quoting Art Runyan: "its not safe to expect any particular
4579 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4580 * mailbox." Moreover, the mailbox may return a bogus state,
4581 * so we need to just enable it and continue on.
2a114cc1
BW		 4582 */
4583 } else {
4584 I915_WRITE(IPS_CTL, IPS_ENABLE);
4585 /* The bit only becomes 1 in the next vblank, so this wait here
4586 * is essentially intel_wait_for_vblank. If we don't have this
4587 * and don't wait for vblanks until the end of crtc_enable, then
4588 * the HW state readout code will complain that the expected
4589 * IPS_CTL value is not the one we read. */
4590 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4591 DRM_ERROR("Timed out waiting for IPS enable\n");
4592 }
d77e4531
PZ		 4593}
4594
20bc8673 4595void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4596{
4597 struct drm_device *dev = crtc->base.dev;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599
6e3c9717 4600 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4601 return;
4602
4603 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4604 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4605 mutex_lock(&dev_priv->rps.hw_lock);
4606 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4607 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4608 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4609 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4610 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4611 } else {
2a114cc1 4612 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4613 POSTING_READ(IPS_CTL);
4614 }
d77e4531
PZ		 4615
4616 /* We need to wait for a vblank before we can disable the plane. */
4617 intel_wait_for_vblank(dev, crtc->pipe);
4618}
4619
4620/** Loads the palette/gamma unit for the CRTC with the prepared values */
4621static void intel_crtc_load_lut(struct drm_crtc *crtc)
4622{
4623 struct drm_device *dev = crtc->dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 enum pipe pipe = intel_crtc->pipe;
4627 int palreg = PALETTE(pipe);
4628 int i;
4629 bool reenable_ips = false;
4630
4631 /* The clocks have to be on to load the palette. */
83d65738 4632 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4633 return;
4634
50360403 4635 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4636 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4637 assert_dsi_pll_enabled(dev_priv);
4638 else
4639 assert_pll_enabled(dev_priv, pipe);
4640 }
4641
4642 /* use legacy palette for Ironlake */
7a1db49a 4643 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4644 palreg = LGC_PALETTE(pipe);
4645
4646 /* Workaround : Do not read or write the pipe palette/gamma data while
4647 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4648 */
6e3c9717 4649 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4650 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4651 GAMMA_MODE_MODE_SPLIT)) {
4652 hsw_disable_ips(intel_crtc);
4653 reenable_ips = true;
4654 }
4655
4656 for (i = 0; i < 256; i++) {
4657 I915_WRITE(palreg + 4 * i,
4658 (intel_crtc->lut_r[i] << 16) |
4659 (intel_crtc->lut_g[i] << 8) |
4660 intel_crtc->lut_b[i]);
4661 }
4662
4663 if (reenable_ips)
4664 hsw_enable_ips(intel_crtc);
4665}
4666
7cac945f 4667static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4668{
7cac945f 4669 if (intel_crtc->overlay) {
d3eedb1a
VS		 4670 struct drm_device *dev = intel_crtc->base.dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672
4673 mutex_lock(&dev->struct_mutex);
4674 dev_priv->mm.interruptible = false;
4675 (void) intel_overlay_switch_off(intel_crtc->overlay);
4676 dev_priv->mm.interruptible = true;
4677 mutex_unlock(&dev->struct_mutex);
4678 }
4679
4680 /* Let userspace switch the overlay on again. In most cases userspace
4681 * has to recompute where to put it anyway.
4682 */
4683}
4684
87d4300a
ML		 4685/**
4686 * intel_post_enable_primary - Perform operations after enabling primary plane
4687 * @crtc: the CRTC whose primary plane was just enabled
4688 *
4689 * Performs potentially sleeping operations that must be done after the primary
4690 * plane is enabled, such as updating FBC and IPS. Note that this may be
4691 * called due to an explicit primary plane update, or due to an implicit
4692 * re-enable that is caused when a sprite plane is updated to no longer
4693 * completely hide the primary plane.
4694 */
4695static void
4696intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4697{
4698 struct drm_device *dev = crtc->dev;
87d4300a 4699 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701 int pipe = intel_crtc->pipe;
a5c4d7bc 4702
87d4300a
ML		 4703 /*
4704 * BDW signals flip done immediately if the plane
4705 * is disabled, even if the plane enable is already
4706 * armed to occur at the next vblank :(
4707 */
4708 if (IS_BROADWELL(dev))
4709 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4710
87d4300a
ML		 4711 /*
4712 * FIXME IPS should be fine as long as one plane is
4713 * enabled, but in practice it seems to have problems
4714 * when going from primary only to sprite only and vice
4715 * versa.
4716 */
a5c4d7bc
VS		 4717 hsw_enable_ips(intel_crtc);
4718
4719 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4720 intel_fbc_update(dev);
a5c4d7bc 4721 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4722
4723 /*
87d4300a
ML		 4724 * Gen2 reports pipe underruns whenever all planes are disabled.
4725 * So don't enable underrun reporting before at least some planes
4726 * are enabled.
4727 * FIXME: Need to fix the logic to work when we turn off all planes
4728 * but leave the pipe running.
f99d7069 4729 */
87d4300a
ML		 4730 if (IS_GEN2(dev))
4731 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4732
4733 /* Underruns don't raise interrupts, so check manually. */
4734 if (HAS_GMCH_DISPLAY(dev))
4735 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4736}
4737
87d4300a
ML		 4738/**
4739 * intel_pre_disable_primary - Perform operations before disabling primary plane
4740 * @crtc: the CRTC whose primary plane is to be disabled
4741 *
4742 * Performs potentially sleeping operations that must be done before the
4743 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4744 * be called due to an explicit primary plane update, or due to an implicit
4745 * disable that is caused when a sprite plane completely hides the primary
4746 * plane.
4747 */
4748static void
4749intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4750{
4751 struct drm_device *dev = crtc->dev;
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4754 int pipe = intel_crtc->pipe;
a5c4d7bc 4755
87d4300a
ML		 4756 /*
4757 * Gen2 reports pipe underruns whenever all planes are disabled.
4758 * So diasble underrun reporting before all the planes get disabled.
4759 * FIXME: Need to fix the logic to work when we turn off all planes
4760 * but leave the pipe running.
4761 */
4762 if (IS_GEN2(dev))
4763 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4764
87d4300a
ML		 4765 /*
4766 * Vblank time updates from the shadow to live plane control register
4767 * are blocked if the memory self-refresh mode is active at that
4768 * moment. So to make sure the plane gets truly disabled, disable
4769 * first the self-refresh mode. The self-refresh enable bit in turn
4770 * will be checked/applied by the HW only at the next frame start
4771 * event which is after the vblank start event, so we need to have a
4772 * wait-for-vblank between disabling the plane and the pipe.
4773 */
4774 if (HAS_GMCH_DISPLAY(dev))
4775 intel_set_memory_cxsr(dev_priv, false);
4776
4777 mutex_lock(&dev->struct_mutex);
e35fef21 4778 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4779 intel_fbc_disable(dev);
87d4300a 4780 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4781
87d4300a
ML		 4782 /*
4783 * FIXME IPS should be fine as long as one plane is
4784 * enabled, but in practice it seems to have problems
4785 * when going from primary only to sprite only and vice
4786 * versa.
4787 */
a5c4d7bc 4788 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4789}
4790
4791static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4792{
2d847d45
RV		 4793 struct drm_device *dev = crtc->dev;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4795 int pipe = intel_crtc->pipe;
4796
87d4300a
ML		 4797 intel_enable_primary_hw_plane(crtc->primary, crtc);
4798 intel_enable_sprite_planes(crtc);
4799 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4800
4801 intel_post_enable_primary(crtc);
2d847d45
RV		 4802
4803 /*
4804 * FIXME: Once we grow proper nuclear flip support out of this we need
4805 * to compute the mask of flip planes precisely. For the time being
4806 * consider this a flip to a NULL plane.
4807 */
4808 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4809}
4810
4811static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4812{
4813 struct drm_device *dev = crtc->dev;
4814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815 struct intel_plane *intel_plane;
4816 int pipe = intel_crtc->pipe;
4817
4818 intel_crtc_wait_for_pending_flips(crtc);
4819
4820 intel_pre_disable_primary(crtc);
a5c4d7bc 4821
7cac945f 4822 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4823 for_each_intel_plane(dev, intel_plane) {
4824 if (intel_plane->pipe == pipe) {
4825 struct drm_crtc *from = intel_plane->base.crtc;
4826
4827 intel_plane->disable_plane(&intel_plane->base,
4828 from ?: crtc, true);
4829 }
4830 }
f98551ae 4831
f99d7069
DV		 4832 /*
4833 * FIXME: Once we grow proper nuclear flip support out of this we need
4834 * to compute the mask of flip planes precisely. For the time being
4835 * consider this a flip to a NULL plane.
4836 */
4837 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4838}
4839
f67a559d
JB		 4840static void ironlake_crtc_enable(struct drm_crtc *crtc)
4841{
4842 struct drm_device *dev = crtc->dev;
4843 struct drm_i915_private *dev_priv = dev->dev_private;
4844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4845 struct intel_encoder *encoder;
f67a559d 4846 int pipe = intel_crtc->pipe;
f67a559d 4847
83d65738 4848 WARN_ON(!crtc->state->enable);
08a48469 4849
f67a559d
JB		 4850 if (intel_crtc->active)
4851 return;
4852
6e3c9717 4853 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4854 intel_prepare_shared_dpll(intel_crtc);
4855
6e3c9717 4856 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4857 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4858
4859 intel_set_pipe_timings(intel_crtc);
4860
6e3c9717 4861 if (intel_crtc->config->has_pch_encoder) {
29407aab 4862 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4863 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4864 }
4865
4866 ironlake_set_pipeconf(crtc);
4867
f67a559d 4868 intel_crtc->active = true;
8664281b 4869
a72e4c9f
DV		 4870 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4871 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4872
f6736a1a 4873 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4874 if (encoder->pre_enable)
4875 encoder->pre_enable(encoder);
f67a559d 4876
6e3c9717 4877 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4878 /* Note: FDI PLL enabling _must_ be done before we enable the
4879 * cpu pipes, hence this is separate from all the other fdi/pch
4880 * enabling. */
88cefb6c 4881 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4882 } else {
4883 assert_fdi_tx_disabled(dev_priv, pipe);
4884 assert_fdi_rx_disabled(dev_priv, pipe);
4885 }
f67a559d 4886
b074cec8 4887 ironlake_pfit_enable(intel_crtc);
f67a559d 4888
9c54c0dd
JB		 4889 /*
4890 * On ILK+ LUT must be loaded before the pipe is running but with
4891 * clocks enabled
4892 */
4893 intel_crtc_load_lut(crtc);
4894
f37fcc2a 4895 intel_update_watermarks(crtc);
e1fdc473 4896 intel_enable_pipe(intel_crtc);
f67a559d 4897
6e3c9717 4898 if (intel_crtc->config->has_pch_encoder)
f67a559d 4899 ironlake_pch_enable(crtc);
c98e9dcf 4900
f9b61ff6
DV		 4901 assert_vblank_disabled(crtc);
4902 drm_crtc_vblank_on(crtc);
4903
fa5c73b1
DV		 4904 for_each_encoder_on_crtc(dev, crtc, encoder)
4905 encoder->enable(encoder);
61b77ddd
DV		 4906
4907 if (HAS_PCH_CPT(dev))
a1520318 4908 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4909}
4910
42db64ef
PZ		 4911/* IPS only exists on ULT machines and is tied to pipe A. */
4912static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4913{
f5adf94e 4914 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4915}
4916
e4916946
PZ		 4917/*
4918 * This implements the workaround described in the "notes" section of the mode
4919 * set sequence documentation. When going from no pipes or single pipe to
4920 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4921 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4922 */
4923static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4924{
4925 struct drm_device *dev = crtc->base.dev;
4926 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4927
4928 /* We want to get the other_active_crtc only if there's only 1 other
4929 * active crtc. */
d3fcc808 4930 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4931 if (!crtc_it->active || crtc_it == crtc)
4932 continue;
4933
4934 if (other_active_crtc)
4935 return;
4936
4937 other_active_crtc = crtc_it;
4938 }
4939 if (!other_active_crtc)
4940 return;
4941
4942 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4943 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4944}
4945
4f771f10
PZ		 4946static void haswell_crtc_enable(struct drm_crtc *crtc)
4947{
4948 struct drm_device *dev = crtc->dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951 struct intel_encoder *encoder;
4952 int pipe = intel_crtc->pipe;
4f771f10 4953
83d65738 4954 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4955
4956 if (intel_crtc->active)
4957 return;
4958
df8ad70c
DV		 4959 if (intel_crtc_to_shared_dpll(intel_crtc))
4960 intel_enable_shared_dpll(intel_crtc);
4961
6e3c9717 4962 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4963 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4964
4965 intel_set_pipe_timings(intel_crtc);
4966
6e3c9717
ACO		 4967 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4968 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4969 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4970 }
4971
6e3c9717 4972 if (intel_crtc->config->has_pch_encoder) {
229fca97 4973 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4974 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4975 }
4976
4977 haswell_set_pipeconf(crtc);
4978
4979 intel_set_pipe_csc(crtc);
4980
4f771f10 4981 intel_crtc->active = true;
8664281b 4982
a72e4c9f 4983 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4984 for_each_encoder_on_crtc(dev, crtc, encoder)
4985 if (encoder->pre_enable)
4986 encoder->pre_enable(encoder);
4987
6e3c9717 4988 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4989 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4990 true);
4fe9467d
ID		 4991 dev_priv->display.fdi_link_train(crtc);
4992 }
4993
1f544388 4994 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4995
ff6d9f55 4996 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4997 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4998 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4999 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5000 else
5001 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5002
5003 /*
5004 * On ILK+ LUT must be loaded before the pipe is running but with
5005 * clocks enabled
5006 */
5007 intel_crtc_load_lut(crtc);
5008
1f544388 5009 intel_ddi_set_pipe_settings(crtc);
8228c251 5010 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5011
f37fcc2a 5012 intel_update_watermarks(crtc);
e1fdc473 5013 intel_enable_pipe(intel_crtc);
42db64ef 5014
6e3c9717 5015 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5016 lpt_pch_enable(crtc);
4f771f10 5017
6e3c9717 5018 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5019 intel_ddi_set_vc_payload_alloc(crtc, true);
5020
f9b61ff6
DV		 5021 assert_vblank_disabled(crtc);
5022 drm_crtc_vblank_on(crtc);
5023
8807e55b 5024 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5025 encoder->enable(encoder);
8807e55b
JN		 5026 intel_opregion_notify_encoder(encoder, true);
5027 }
4f771f10 5028
e4916946
PZ		 5029 /* If we change the relative order between pipe/planes enabling, we need
5030 * to change the workaround. */
5031 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5032}
5033
3f8dce3a
DV		 5034static void ironlake_pfit_disable(struct intel_crtc *crtc)
5035{
5036 struct drm_device *dev = crtc->base.dev;
5037 struct drm_i915_private *dev_priv = dev->dev_private;
5038 int pipe = crtc->pipe;
5039
5040 /* To avoid upsetting the power well on haswell only disable the pfit if
5041 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5042 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5043 I915_WRITE(PF_CTL(pipe), 0);
5044 I915_WRITE(PF_WIN_POS(pipe), 0);
5045 I915_WRITE(PF_WIN_SZ(pipe), 0);
5046 }
5047}
5048
6be4a607
JB		 5049static void ironlake_crtc_disable(struct drm_crtc *crtc)
5050{
5051 struct drm_device *dev = crtc->dev;
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5054 struct intel_encoder *encoder;
6be4a607 5055 int pipe = intel_crtc->pipe;
5eddb70b 5056 u32 reg, temp;
b52eb4dc 5057
f7abfe8b
CW		 5058 if (!intel_crtc->active)
5059 return;
5060
ea9d758d
DV		 5061 for_each_encoder_on_crtc(dev, crtc, encoder)
5062 encoder->disable(encoder);
5063
f9b61ff6
DV		 5064 drm_crtc_vblank_off(crtc);
5065 assert_vblank_disabled(crtc);
5066
6e3c9717 5067 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5068 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5069
575f7ab7 5070 intel_disable_pipe(intel_crtc);
32f9d658 5071
3f8dce3a 5072 ironlake_pfit_disable(intel_crtc);
2c07245f 5073
5a74f70a
VS		 5074 if (intel_crtc->config->has_pch_encoder)
5075 ironlake_fdi_disable(crtc);
5076
bf49ec8c
DV		 5077 for_each_encoder_on_crtc(dev, crtc, encoder)
5078 if (encoder->post_disable)
5079 encoder->post_disable(encoder);
2c07245f 5080
6e3c9717 5081 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5082 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5083
d925c59a
DV		 5084 if (HAS_PCH_CPT(dev)) {
5085 /* disable TRANS_DP_CTL */
5086 reg = TRANS_DP_CTL(pipe);
5087 temp = I915_READ(reg);
5088 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5089 TRANS_DP_PORT_SEL_MASK);
5090 temp |= TRANS_DP_PORT_SEL_NONE;
5091 I915_WRITE(reg, temp);
5092
5093 /* disable DPLL_SEL */
5094 temp = I915_READ(PCH_DPLL_SEL);
11887397 5095 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5096 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5097 }
e3421a18 5098
d925c59a 5099 /* disable PCH DPLL */
e72f9fbf 5100 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5101
d925c59a
DV		 5102 ironlake_fdi_pll_disable(intel_crtc);
5103 }
6b383a7f 5104
f7abfe8b 5105 intel_crtc->active = false;
46ba614c 5106 intel_update_watermarks(crtc);
d1ebd816
BW		 5107
5108 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5109 intel_fbc_update(dev);
d1ebd816 5110 mutex_unlock(&dev->struct_mutex);
6be4a607 5111}
1b3c7a47 5112
4f771f10 5113static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5114{
4f771f10
PZ		 5115 struct drm_device *dev = crtc->dev;
5116 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5118 struct intel_encoder *encoder;
6e3c9717 5119 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5120
4f771f10
PZ		 5121 if (!intel_crtc->active)
5122 return;
5123
8807e55b
JN		 5124 for_each_encoder_on_crtc(dev, crtc, encoder) {
5125 intel_opregion_notify_encoder(encoder, false);
4f771f10 5126 encoder->disable(encoder);
8807e55b 5127 }
4f771f10 5128
f9b61ff6
DV		 5129 drm_crtc_vblank_off(crtc);
5130 assert_vblank_disabled(crtc);
5131
6e3c9717 5132 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5133 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5134 false);
575f7ab7 5135 intel_disable_pipe(intel_crtc);
4f771f10 5136
6e3c9717 5137 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5138 intel_ddi_set_vc_payload_alloc(crtc, false);
5139
ad80a810 5140 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5141
ff6d9f55 5142 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5143 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5144 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5145 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5146 else
5147 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5148
1f544388 5149 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5150
6e3c9717 5151 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5152 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5153 intel_ddi_fdi_disable(crtc);
83616634 5154 }
4f771f10 5155
97b040aa
ID		 5156 for_each_encoder_on_crtc(dev, crtc, encoder)
5157 if (encoder->post_disable)
5158 encoder->post_disable(encoder);
5159
4f771f10 5160 intel_crtc->active = false;
46ba614c 5161 intel_update_watermarks(crtc);
4f771f10
PZ		 5162
5163 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5164 intel_fbc_update(dev);
4f771f10 5165 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5166
5167 if (intel_crtc_to_shared_dpll(intel_crtc))
5168 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5169}
5170
2dd24552
JB		 5171static void i9xx_pfit_enable(struct intel_crtc *crtc)
5172{
5173 struct drm_device *dev = crtc->base.dev;
5174 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5175 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5176
681a8504 5177 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5178 return;
5179
2dd24552 5180 /*
c0b03411
DV		 5181 * The panel fitter should only be adjusted whilst the pipe is disabled,
5182 * according to register description and PRM.
2dd24552 5183 */
c0b03411
DV		 5184 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5185 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5186
b074cec8
JB		 5187 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5188 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5189
5190 /* Border color in case we don't scale up to the full screen. Black by
5191 * default, change to something else for debugging. */
5192 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5193}
5194
d05410f9
DA		 5195static enum intel_display_power_domain port_to_power_domain(enum port port)
5196{
5197 switch (port) {
5198 case PORT_A:
5199 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5200 case PORT_B:
5201 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5202 case PORT_C:
5203 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5204 case PORT_D:
5205 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5206 default:
5207 WARN_ON_ONCE(1);
5208 return POWER_DOMAIN_PORT_OTHER;
5209 }
5210}
5211
77d22dca
ID		 5212#define for_each_power_domain(domain, mask) \
5213 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5214 if ((1 << (domain)) & (mask))
5215
319be8ae
ID		 5216enum intel_display_power_domain
5217intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5218{
5219 struct drm_device *dev = intel_encoder->base.dev;
5220 struct intel_digital_port *intel_dig_port;
5221
5222 switch (intel_encoder->type) {
5223 case INTEL_OUTPUT_UNKNOWN:
5224 /* Only DDI platforms should ever use this output type */
5225 WARN_ON_ONCE(!HAS_DDI(dev));
5226 case INTEL_OUTPUT_DISPLAYPORT:
5227 case INTEL_OUTPUT_HDMI:
5228 case INTEL_OUTPUT_EDP:
5229 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5230 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5231 case INTEL_OUTPUT_DP_MST:
5232 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5233 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5234 case INTEL_OUTPUT_ANALOG:
5235 return POWER_DOMAIN_PORT_CRT;
5236 case INTEL_OUTPUT_DSI:
5237 return POWER_DOMAIN_PORT_DSI;
5238 default:
5239 return POWER_DOMAIN_PORT_OTHER;
5240 }
5241}
5242
5243static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5244{
319be8ae
ID		 5245 struct drm_device *dev = crtc->dev;
5246 struct intel_encoder *intel_encoder;
5247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5248 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5249 unsigned long mask;
5250 enum transcoder transcoder;
5251
5252 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5253
5254 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5255 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5256 if (intel_crtc->config->pch_pfit.enabled ||
5257 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5258 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5259
319be8ae
ID		 5260 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5261 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5262
77d22dca
ID		 5263 return mask;
5264}
5265
679dacd4 5266static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5267{
679dacd4 5268 struct drm_device *dev = state->dev;
77d22dca
ID		 5269 struct drm_i915_private *dev_priv = dev->dev_private;
5270 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5271 struct intel_crtc *crtc;
5272
5273 /*
5274 * First get all needed power domains, then put all unneeded, to avoid
5275 * any unnecessary toggling of the power wells.
5276 */
d3fcc808 5277 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5278 enum intel_display_power_domain domain;
5279
83d65738 5280 if (!crtc->base.state->enable)
77d22dca
ID		 5281 continue;
5282
319be8ae 5283 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5284
5285 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5286 intel_display_power_get(dev_priv, domain);
5287 }
5288
50f6e502 5289 if (dev_priv->display.modeset_global_resources)
679dacd4 5290 dev_priv->display.modeset_global_resources(state);
50f6e502 5291
d3fcc808 5292 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5293 enum intel_display_power_domain domain;
5294
5295 for_each_power_domain(domain, crtc->enabled_power_domains)
5296 intel_display_power_put(dev_priv, domain);
5297
5298 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5299 }
5300
5301 intel_display_set_init_power(dev_priv, false);
5302}
5303
560a7ae4
DL		 5304static void intel_update_max_cdclk(struct drm_device *dev)
5305{
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307
5308 if (IS_SKYLAKE(dev)) {
5309 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5310
5311 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5312 dev_priv->max_cdclk_freq = 675000;
5313 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5314 dev_priv->max_cdclk_freq = 540000;
5315 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5316 dev_priv->max_cdclk_freq = 450000;
5317 else
5318 dev_priv->max_cdclk_freq = 337500;
5319 } else if (IS_BROADWELL(dev)) {
5320 /*
5321 * FIXME with extra cooling we can allow
5322 * 540 MHz for ULX and 675 Mhz for ULT.
5323 * How can we know if extra cooling is
5324 * available? PCI ID, VTB, something else?
5325 */
5326 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5327 dev_priv->max_cdclk_freq = 450000;
5328 else if (IS_BDW_ULX(dev))
5329 dev_priv->max_cdclk_freq = 450000;
5330 else if (IS_BDW_ULT(dev))
5331 dev_priv->max_cdclk_freq = 540000;
5332 else
5333 dev_priv->max_cdclk_freq = 675000;
5334 } else if (IS_VALLEYVIEW(dev)) {
5335 dev_priv->max_cdclk_freq = 400000;
5336 } else {
5337 /* otherwise assume cdclk is fixed */
5338 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5339 }
5340
5341 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5342 dev_priv->max_cdclk_freq);
5343}
5344
5345static void intel_update_cdclk(struct drm_device *dev)
5346{
5347 struct drm_i915_private *dev_priv = dev->dev_private;
5348
5349 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5350 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5351 dev_priv->cdclk_freq);
5352
5353 /*
5354 * Program the gmbus_freq based on the cdclk frequency.
5355 * BSpec erroneously claims we should aim for 4MHz, but
5356 * in fact 1MHz is the correct frequency.
5357 */
5358 if (IS_VALLEYVIEW(dev)) {
5359 /*
5360 * Program the gmbus_freq based on the cdclk frequency.
5361 * BSpec erroneously claims we should aim for 4MHz, but
5362 * in fact 1MHz is the correct frequency.
5363 */
5364 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5365 }
5366
5367 if (dev_priv->max_cdclk_freq == 0)
5368 intel_update_max_cdclk(dev);
5369}
5370
70d0c574 5371static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5372{
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 uint32_t divider;
5375 uint32_t ratio;
5376 uint32_t current_freq;
5377 int ret;
5378
5379 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5380 switch (frequency) {
5381 case 144000:
5382 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5383 ratio = BXT_DE_PLL_RATIO(60);
5384 break;
5385 case 288000:
5386 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5387 ratio = BXT_DE_PLL_RATIO(60);
5388 break;
5389 case 384000:
5390 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5391 ratio = BXT_DE_PLL_RATIO(60);
5392 break;
5393 case 576000:
5394 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5395 ratio = BXT_DE_PLL_RATIO(60);
5396 break;
5397 case 624000:
5398 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5399 ratio = BXT_DE_PLL_RATIO(65);
5400 break;
5401 case 19200:
5402 /*
5403 * Bypass frequency with DE PLL disabled. Init ratio, divider
5404 * to suppress GCC warning.
5405 */
5406 ratio = 0;
5407 divider = 0;
5408 break;
5409 default:
5410 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5411
5412 return;
5413 }
5414
5415 mutex_lock(&dev_priv->rps.hw_lock);
5416 /* Inform power controller of upcoming frequency change */
5417 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5418 0x80000000);
5419 mutex_unlock(&dev_priv->rps.hw_lock);
5420
5421 if (ret) {
5422 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5423 ret, frequency);
5424 return;
5425 }
5426
5427 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5428 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5429 current_freq = current_freq * 500 + 1000;
5430
5431 /*
5432 * DE PLL has to be disabled when
5433 * - setting to 19.2MHz (bypass, PLL isn't used)
5434 * - before setting to 624MHz (PLL needs toggling)
5435 * - before setting to any frequency from 624MHz (PLL needs toggling)
5436 */
5437 if (frequency == 19200 || frequency == 624000 ||
5438 current_freq == 624000) {
5439 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5440 /* Timeout 200us */
5441 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5442 1))
5443 DRM_ERROR("timout waiting for DE PLL unlock\n");
5444 }
5445
5446 if (frequency != 19200) {
5447 uint32_t val;
5448
5449 val = I915_READ(BXT_DE_PLL_CTL);
5450 val &= ~BXT_DE_PLL_RATIO_MASK;
5451 val |= ratio;
5452 I915_WRITE(BXT_DE_PLL_CTL, val);
5453
5454 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5455 /* Timeout 200us */
5456 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5457 DRM_ERROR("timeout waiting for DE PLL lock\n");
5458
5459 val = I915_READ(CDCLK_CTL);
5460 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5461 val |= divider;
5462 /*
5463 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5464 * enable otherwise.
5465 */
5466 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5467 if (frequency >= 500000)
5468 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5469
5470 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5471 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5472 val |= (frequency - 1000) / 500;
5473 I915_WRITE(CDCLK_CTL, val);
5474 }
5475
5476 mutex_lock(&dev_priv->rps.hw_lock);
5477 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5478 DIV_ROUND_UP(frequency, 25000));
5479 mutex_unlock(&dev_priv->rps.hw_lock);
5480
5481 if (ret) {
5482 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5483 ret, frequency);
5484 return;
5485 }
5486
a47871bd 5487 intel_update_cdclk(dev);
f8437dd1
VK		 5488}
5489
5490void broxton_init_cdclk(struct drm_device *dev)
5491{
5492 struct drm_i915_private *dev_priv = dev->dev_private;
5493 uint32_t val;
5494
5495 /*
5496 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5497 * or else the reset will hang because there is no PCH to respond.
5498 * Move the handshake programming to initialization sequence.
5499 * Previously was left up to BIOS.
5500 */
5501 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5502 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5503 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5504
5505 /* Enable PG1 for cdclk */
5506 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5507
5508 /* check if cd clock is enabled */
5509 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5510 DRM_DEBUG_KMS("Display already initialized\n");
5511 return;
5512 }
5513
5514 /*
5515 * FIXME:
5516 * - The initial CDCLK needs to be read from VBT.
5517 * Need to make this change after VBT has changes for BXT.
5518 * - check if setting the max (or any) cdclk freq is really necessary
5519 * here, it belongs to modeset time
5520 */
5521 broxton_set_cdclk(dev, 624000);
5522
5523 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5524 POSTING_READ(DBUF_CTL);
5525
f8437dd1
VK		 5526 udelay(10);
5527
5528 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5529 DRM_ERROR("DBuf power enable timeout!\n");
5530}
5531
5532void broxton_uninit_cdclk(struct drm_device *dev)
5533{
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535
5536 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5537 POSTING_READ(DBUF_CTL);
5538
f8437dd1
VK		 5539 udelay(10);
5540
5541 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5542 DRM_ERROR("DBuf power disable timeout!\n");
5543
5544 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5545 broxton_set_cdclk(dev, 19200);
5546
5547 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5548}
5549
5d96d8af
DL		 5550static const struct skl_cdclk_entry {
5551 unsigned int freq;
5552 unsigned int vco;
5553} skl_cdclk_frequencies[] = {
5554 { .freq = 308570, .vco = 8640 },
5555 { .freq = 337500, .vco = 8100 },
5556 { .freq = 432000, .vco = 8640 },
5557 { .freq = 450000, .vco = 8100 },
5558 { .freq = 540000, .vco = 8100 },
5559 { .freq = 617140, .vco = 8640 },
5560 { .freq = 675000, .vco = 8100 },
5561};
5562
5563static unsigned int skl_cdclk_decimal(unsigned int freq)
5564{
5565 return (freq - 1000) / 500;
5566}
5567
5568static unsigned int skl_cdclk_get_vco(unsigned int freq)
5569{
5570 unsigned int i;
5571
5572 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5573 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5574
5575 if (e->freq == freq)
5576 return e->vco;
5577 }
5578
5579 return 8100;
5580}
5581
5582static void
5583skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5584{
5585 unsigned int min_freq;
5586 u32 val;
5587
5588 /* select the minimum CDCLK before enabling DPLL 0 */
5589 val = I915_READ(CDCLK_CTL);
5590 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5591 val |= CDCLK_FREQ_337_308;
5592
5593 if (required_vco == 8640)
5594 min_freq = 308570;
5595 else
5596 min_freq = 337500;
5597
5598 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5599
5600 I915_WRITE(CDCLK_CTL, val);
5601 POSTING_READ(CDCLK_CTL);
5602
5603 /*
5604 * We always enable DPLL0 with the lowest link rate possible, but still
5605 * taking into account the VCO required to operate the eDP panel at the
5606 * desired frequency. The usual DP link rates operate with a VCO of
5607 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5608 * The modeset code is responsible for the selection of the exact link
5609 * rate later on, with the constraint of choosing a frequency that
5610 * works with required_vco.
5611 */
5612 val = I915_READ(DPLL_CTRL1);
5613
5614 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5615 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5616 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5617 if (required_vco == 8640)
5618 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5619 SKL_DPLL0);
5620 else
5621 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5622 SKL_DPLL0);
5623
5624 I915_WRITE(DPLL_CTRL1, val);
5625 POSTING_READ(DPLL_CTRL1);
5626
5627 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5628
5629 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5630 DRM_ERROR("DPLL0 not locked\n");
5631}
5632
5633static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5634{
5635 int ret;
5636 u32 val;
5637
5638 /* inform PCU we want to change CDCLK */
5639 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5640 mutex_lock(&dev_priv->rps.hw_lock);
5641 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5642 mutex_unlock(&dev_priv->rps.hw_lock);
5643
5644 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5645}
5646
5647static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5648{
5649 unsigned int i;
5650
5651 for (i = 0; i < 15; i++) {
5652 if (skl_cdclk_pcu_ready(dev_priv))
5653 return true;
5654 udelay(10);
5655 }
5656
5657 return false;
5658}
5659
5660static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5661{
560a7ae4 5662 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5663 u32 freq_select, pcu_ack;
5664
5665 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5666
5667 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5668 DRM_ERROR("failed to inform PCU about cdclk change\n");
5669 return;
5670 }
5671
5672 /* set CDCLK_CTL */
5673 switch(freq) {
5674 case 450000:
5675 case 432000:
5676 freq_select = CDCLK_FREQ_450_432;
5677 pcu_ack = 1;
5678 break;
5679 case 540000:
5680 freq_select = CDCLK_FREQ_540;
5681 pcu_ack = 2;
5682 break;
5683 case 308570:
5684 case 337500:
5685 default:
5686 freq_select = CDCLK_FREQ_337_308;
5687 pcu_ack = 0;
5688 break;
5689 case 617140:
5690 case 675000:
5691 freq_select = CDCLK_FREQ_675_617;
5692 pcu_ack = 3;
5693 break;
5694 }
5695
5696 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5697 POSTING_READ(CDCLK_CTL);
5698
5699 /* inform PCU of the change */
5700 mutex_lock(&dev_priv->rps.hw_lock);
5701 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5702 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5703
5704 intel_update_cdclk(dev);
5d96d8af
DL		 5705}
5706
5707void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5708{
5709 /* disable DBUF power */
5710 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5711 POSTING_READ(DBUF_CTL);
5712
5713 udelay(10);
5714
5715 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5716 DRM_ERROR("DBuf power disable timeout\n");
5717
5718 /* disable DPLL0 */
5719 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5720 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5721 DRM_ERROR("Couldn't disable DPLL0\n");
5722
5723 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5724}
5725
5726void skl_init_cdclk(struct drm_i915_private *dev_priv)
5727{
5728 u32 val;
5729 unsigned int required_vco;
5730
5731 /* enable PCH reset handshake */
5732 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5733 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5734
5735 /* enable PG1 and Misc I/O */
5736 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5737
5738 /* DPLL0 already enabed !? */
5739 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5740 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5741 return;
5742 }
5743
5744 /* enable DPLL0 */
5745 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5746 skl_dpll0_enable(dev_priv, required_vco);
5747
5748 /* set CDCLK to the frequency the BIOS chose */
5749 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5750
5751 /* enable DBUF power */
5752 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5753 POSTING_READ(DBUF_CTL);
5754
5755 udelay(10);
5756
5757 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5758 DRM_ERROR("DBuf power enable timeout\n");
5759}
5760
dfcab17e 5761/* returns HPLL frequency in kHz */
f8bf63fd 5762static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5763{
586f49dc 5764 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5765
586f49dc 5766 /* Obtain SKU information */
a580516d 5767 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5768 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5769 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5770 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5771
dfcab17e 5772 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5773}
5774
5775/* Adjust CDclk dividers to allow high res or save power if possible */
5776static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5777{
5778 struct drm_i915_private *dev_priv = dev->dev_private;
5779 u32 val, cmd;
5780
164dfd28
VK		 5781 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5782 != dev_priv->cdclk_freq);
d60c4473 5783
dfcab17e 5784 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5785 cmd = 2;
dfcab17e 5786 else if (cdclk == 266667)
30a970c6
JB		 5787 cmd = 1;
5788 else
5789 cmd = 0;
5790
5791 mutex_lock(&dev_priv->rps.hw_lock);
5792 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5793 val &= ~DSPFREQGUAR_MASK;
5794 val |= (cmd << DSPFREQGUAR_SHIFT);
5795 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5796 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5797 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5798 50)) {
5799 DRM_ERROR("timed out waiting for CDclk change\n");
5800 }
5801 mutex_unlock(&dev_priv->rps.hw_lock);
5802
54433e91
VS		 5803 mutex_lock(&dev_priv->sb_lock);
5804
dfcab17e 5805 if (cdclk == 400000) {
6bcda4f0 5806 u32 divider;
30a970c6 5807
6bcda4f0 5808 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5809
30a970c6
JB		 5810 /* adjust cdclk divider */
5811 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5812 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5813 val |= divider;
5814 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5815
5816 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5817 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5818 50))
5819 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5820 }
5821
30a970c6
JB		 5822 /* adjust self-refresh exit latency value */
5823 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5824 val &= ~0x7f;
5825
5826 /*
5827 * For high bandwidth configs, we set a higher latency in the bunit
5828 * so that the core display fetch happens in time to avoid underruns.
5829 */
dfcab17e 5830 if (cdclk == 400000)
30a970c6
JB		 5831 val |= 4500 / 250; /* 4.5 usec */
5832 else
5833 val |= 3000 / 250; /* 3.0 usec */
5834 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5835
a580516d 5836 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5837
b6283055 5838 intel_update_cdclk(dev);
30a970c6
JB		 5839}
5840
383c5a6a
VS		 5841static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5842{
5843 struct drm_i915_private *dev_priv = dev->dev_private;
5844 u32 val, cmd;
5845
164dfd28
VK		 5846 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5847 != dev_priv->cdclk_freq);
383c5a6a
VS		 5848
5849 switch (cdclk) {
383c5a6a
VS		 5850 case 333333:
5851 case 320000:
383c5a6a 5852 case 266667:
383c5a6a 5853 case 200000:
383c5a6a
VS		 5854 break;
5855 default:
5f77eeb0 5856 MISSING_CASE(cdclk);
383c5a6a
VS		 5857 return;
5858 }
5859
9d0d3fda
VS		 5860 /*
5861 * Specs are full of misinformation, but testing on actual
5862 * hardware has shown that we just need to write the desired
5863 * CCK divider into the Punit register.
5864 */
5865 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5866
383c5a6a
VS		 5867 mutex_lock(&dev_priv->rps.hw_lock);
5868 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5869 val &= ~DSPFREQGUAR_MASK_CHV;
5870 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5871 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5872 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5873 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5874 50)) {
5875 DRM_ERROR("timed out waiting for CDclk change\n");
5876 }
5877 mutex_unlock(&dev_priv->rps.hw_lock);
5878
b6283055 5879 intel_update_cdclk(dev);
383c5a6a
VS		 5880}
5881
30a970c6
JB		 5882static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5883 int max_pixclk)
5884{
6bcda4f0 5885 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5886 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5887
30a970c6
JB		 5888 /*
5889 * Really only a few cases to deal with, as only 4 CDclks are supported:
5890 * 200MHz
5891 * 267MHz
29dc7ef3 5892 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5893 * 400MHz (VLV only)
5894 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5895 * of the lower bin and adjust if needed.
e37c67a1
VS		 5896 *
5897 * We seem to get an unstable or solid color picture at 200MHz.
5898 * Not sure what's wrong. For now use 200MHz only when all pipes
5899 * are off.
30a970c6 5900 */
6cca3195
VS		 5901 if (!IS_CHERRYVIEW(dev_priv) &&
5902 max_pixclk > freq_320*limit/100)
dfcab17e 5903 return 400000;
6cca3195 5904 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5905 return freq_320;
e37c67a1 5906 else if (max_pixclk > 0)
dfcab17e 5907 return 266667;
e37c67a1
VS		 5908 else
5909 return 200000;
30a970c6
JB		 5910}
5911
f8437dd1
VK		 5912static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5913 int max_pixclk)
5914{
5915 /*
5916 * FIXME:
5917 * - remove the guardband, it's not needed on BXT
5918 * - set 19.2MHz bypass frequency if there are no active pipes
5919 */
5920 if (max_pixclk > 576000*9/10)
5921 return 624000;
5922 else if (max_pixclk > 384000*9/10)
5923 return 576000;
5924 else if (max_pixclk > 288000*9/10)
5925 return 384000;
5926 else if (max_pixclk > 144000*9/10)
5927 return 288000;
5928 else
5929 return 144000;
5930}
5931
a821fc46
ACO		 5932/* Compute the max pixel clock for new configuration. Uses atomic state if
5933 * that's non-NULL, look at current state otherwise. */
5934static int intel_mode_max_pixclk(struct drm_device *dev,
5935 struct drm_atomic_state *state)
30a970c6 5936{
30a970c6 5937 struct intel_crtc *intel_crtc;
304603f4 5938 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5939 int max_pixclk = 0;
5940
d3fcc808 5941 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5942 if (state)
5943 crtc_state =
5944 intel_atomic_get_crtc_state(state, intel_crtc);
5945 else
5946 crtc_state = intel_crtc->config;
304603f4
ACO		 5947 if (IS_ERR(crtc_state))
5948 return PTR_ERR(crtc_state);
5949
5950 if (!crtc_state->base.enable)
5951 continue;
5952
5953 max_pixclk = max(max_pixclk,
5954 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5955 }
5956
5957 return max_pixclk;
5958}
5959
0a9ab303 5960static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5961{
304603f4 5962 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5963 struct drm_crtc *crtc;
5964 struct drm_crtc_state *crtc_state;
a821fc46 5965 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5966 int cdclk, i;
30a970c6 5967
304603f4
ACO		 5968 if (max_pixclk < 0)
5969 return max_pixclk;
30a970c6 5970
f8437dd1
VK		 5971 if (IS_VALLEYVIEW(dev_priv))
5972 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5973 else
5974 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5975
5976 if (cdclk == dev_priv->cdclk_freq)
304603f4 5977 return 0;
30a970c6 5978
0a9ab303
ACO		 5979 /* add all active pipes to the state */
5980 for_each_crtc(state->dev, crtc) {
5981 if (!crtc->state->enable)
5982 continue;
5983
5984 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5985 if (IS_ERR(crtc_state))
5986 return PTR_ERR(crtc_state);
5987 }
5988
2f2d7aa1 5989 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5990 for_each_crtc_in_state(state, crtc, crtc_state, i)
5991 if (crtc_state->enable)
5992 crtc_state->mode_changed = true;
304603f4
ACO		 5993
5994 return 0;
30a970c6
JB		 5995}
5996
1e69cd74
VS		 5997static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5998{
5999 unsigned int credits, default_credits;
6000
6001 if (IS_CHERRYVIEW(dev_priv))
6002 default_credits = PFI_CREDIT(12);
6003 else
6004 default_credits = PFI_CREDIT(8);
6005
164dfd28 6006 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6007 /* CHV suggested value is 31 or 63 */
6008 if (IS_CHERRYVIEW(dev_priv))
6009 credits = PFI_CREDIT_31;
6010 else
6011 credits = PFI_CREDIT(15);
6012 } else {
6013 credits = default_credits;
6014 }
6015
6016 /*
6017 * WA - write default credits before re-programming
6018 * FIXME: should we also set the resend bit here?
6019 */
6020 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6021 default_credits);
6022
6023 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6024 credits | PFI_CREDIT_RESEND);
6025
6026 /*
6027 * FIXME is this guaranteed to clear
6028 * immediately or should we poll for it?
6029 */
6030 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6031}
6032
a821fc46 6033static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6034{
a821fc46 6035 struct drm_device *dev = old_state->dev;
30a970c6 6036 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6037 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6038 int req_cdclk;
6039
a821fc46
ACO		 6040 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6041 * never fail. */
304603f4
ACO		 6042 if (WARN_ON(max_pixclk < 0))
6043 return;
30a970c6 6044
304603f4 6045 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6046
164dfd28 6047 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6048 /*
6049 * FIXME: We can end up here with all power domains off, yet
6050 * with a CDCLK frequency other than the minimum. To account
6051 * for this take the PIPE-A power domain, which covers the HW
6052 * blocks needed for the following programming. This can be
6053 * removed once it's guaranteed that we get here either with
6054 * the minimum CDCLK set, or the required power domains
6055 * enabled.
6056 */
6057 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6058
383c5a6a
VS		 6059 if (IS_CHERRYVIEW(dev))
6060 cherryview_set_cdclk(dev, req_cdclk);
6061 else
6062 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6063
1e69cd74
VS		 6064 vlv_program_pfi_credits(dev_priv);
6065
738c05c0 6066 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6067 }
30a970c6
JB		 6068}
6069
89b667f8
JB		 6070static void valleyview_crtc_enable(struct drm_crtc *crtc)
6071{
6072 struct drm_device *dev = crtc->dev;
a72e4c9f 6073 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075 struct intel_encoder *encoder;
6076 int pipe = intel_crtc->pipe;
23538ef1 6077 bool is_dsi;
89b667f8 6078
83d65738 6079 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6080
6081 if (intel_crtc->active)
6082 return;
6083
409ee761 6084 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6085
1ae0d137
VS		 6086 if (!is_dsi) {
6087 if (IS_CHERRYVIEW(dev))
6e3c9717 6088 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6089 else
6e3c9717 6090 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6091 }
5b18e57c 6092
6e3c9717 6093 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6094 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6095
6096 intel_set_pipe_timings(intel_crtc);
6097
c14b0485
VS		 6098 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100
6101 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6102 I915_WRITE(CHV_CANVAS(pipe), 0);
6103 }
6104
5b18e57c
DV		 6105 i9xx_set_pipeconf(intel_crtc);
6106
89b667f8 6107 intel_crtc->active = true;
89b667f8 6108
a72e4c9f 6109 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6110
89b667f8
JB		 6111 for_each_encoder_on_crtc(dev, crtc, encoder)
6112 if (encoder->pre_pll_enable)
6113 encoder->pre_pll_enable(encoder);
6114
9d556c99
CML		 6115 if (!is_dsi) {
6116 if (IS_CHERRYVIEW(dev))
6e3c9717 6117 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6118 else
6e3c9717 6119 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6120 }
89b667f8
JB		 6121
6122 for_each_encoder_on_crtc(dev, crtc, encoder)
6123 if (encoder->pre_enable)
6124 encoder->pre_enable(encoder);
6125
2dd24552
JB		 6126 i9xx_pfit_enable(intel_crtc);
6127
63cbb074
VS		 6128 intel_crtc_load_lut(crtc);
6129
f37fcc2a 6130 intel_update_watermarks(crtc);
e1fdc473 6131 intel_enable_pipe(intel_crtc);
be6a6f8e 6132
4b3a9526
VS		 6133 assert_vblank_disabled(crtc);
6134 drm_crtc_vblank_on(crtc);
6135
f9b61ff6
DV		 6136 for_each_encoder_on_crtc(dev, crtc, encoder)
6137 encoder->enable(encoder);
89b667f8
JB		 6138}
6139
f13c2ef3
DV		 6140static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6141{
6142 struct drm_device *dev = crtc->base.dev;
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144
6e3c9717
ACO		 6145 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6146 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6147}
6148
0b8765c6 6149static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6150{
6151 struct drm_device *dev = crtc->dev;
a72e4c9f 6152 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6154 struct intel_encoder *encoder;
79e53945 6155 int pipe = intel_crtc->pipe;
79e53945 6156
83d65738 6157 WARN_ON(!crtc->state->enable);
08a48469 6158
f7abfe8b
CW		 6159 if (intel_crtc->active)
6160 return;
6161
f13c2ef3
DV		 6162 i9xx_set_pll_dividers(intel_crtc);
6163
6e3c9717 6164 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6165 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6166
6167 intel_set_pipe_timings(intel_crtc);
6168
5b18e57c
DV		 6169 i9xx_set_pipeconf(intel_crtc);
6170
f7abfe8b 6171 intel_crtc->active = true;
6b383a7f 6172
4a3436e8 6173 if (!IS_GEN2(dev))
a72e4c9f 6174 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6175
9d6d9f19
MK		 6176 for_each_encoder_on_crtc(dev, crtc, encoder)
6177 if (encoder->pre_enable)
6178 encoder->pre_enable(encoder);
6179
f6736a1a
DV		 6180 i9xx_enable_pll(intel_crtc);
6181
2dd24552
JB		 6182 i9xx_pfit_enable(intel_crtc);
6183
63cbb074
VS		 6184 intel_crtc_load_lut(crtc);
6185
f37fcc2a 6186 intel_update_watermarks(crtc);
e1fdc473 6187 intel_enable_pipe(intel_crtc);
be6a6f8e 6188
4b3a9526
VS		 6189 assert_vblank_disabled(crtc);
6190 drm_crtc_vblank_on(crtc);
6191
f9b61ff6
DV		 6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 encoder->enable(encoder);
0b8765c6 6194}
79e53945 6195
87476d63
DV		 6196static void i9xx_pfit_disable(struct intel_crtc *crtc)
6197{
6198 struct drm_device *dev = crtc->base.dev;
6199 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6200
6e3c9717 6201 if (!crtc->config->gmch_pfit.control)
328d8e82 6202 return;
87476d63 6203
328d8e82 6204 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6205
328d8e82
DV		 6206 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6207 I915_READ(PFIT_CONTROL));
6208 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6209}
6210
0b8765c6
JB		 6211static void i9xx_crtc_disable(struct drm_crtc *crtc)
6212{
6213 struct drm_device *dev = crtc->dev;
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6216 struct intel_encoder *encoder;
0b8765c6 6217 int pipe = intel_crtc->pipe;
ef9c3aee 6218
f7abfe8b
CW		 6219 if (!intel_crtc->active)
6220 return;
6221
6304cd91
VS		 6222 /*
6223 * On gen2 planes are double buffered but the pipe isn't, so we must
6224 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6225 * We also need to wait on all gmch platforms because of the
6226 * self-refresh mode constraint explained above.
6304cd91 6227 */
564ed191 6228 intel_wait_for_vblank(dev, pipe);
6304cd91 6229
4b3a9526
VS		 6230 for_each_encoder_on_crtc(dev, crtc, encoder)
6231 encoder->disable(encoder);
6232
f9b61ff6
DV		 6233 drm_crtc_vblank_off(crtc);
6234 assert_vblank_disabled(crtc);
6235
575f7ab7 6236 intel_disable_pipe(intel_crtc);
24a1f16d 6237
87476d63 6238 i9xx_pfit_disable(intel_crtc);
24a1f16d 6239
89b667f8
JB		 6240 for_each_encoder_on_crtc(dev, crtc, encoder)
6241 if (encoder->post_disable)
6242 encoder->post_disable(encoder);
6243
409ee761 6244 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6245 if (IS_CHERRYVIEW(dev))
6246 chv_disable_pll(dev_priv, pipe);
6247 else if (IS_VALLEYVIEW(dev))
6248 vlv_disable_pll(dev_priv, pipe);
6249 else
1c4e0274 6250 i9xx_disable_pll(intel_crtc);
076ed3b2 6251 }
0b8765c6 6252
4a3436e8 6253 if (!IS_GEN2(dev))
a72e4c9f 6254 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6255
f7abfe8b 6256 intel_crtc->active = false;
46ba614c 6257 intel_update_watermarks(crtc);
f37fcc2a 6258
efa9624e 6259 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6260 intel_fbc_update(dev);
efa9624e 6261 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6262}
6263
6b72d486
ML		 6264/*
6265 * turn all crtc's off, but do not adjust state
6266 * This has to be paired with a call to intel_modeset_setup_hw_state.
6267 */
6268void intel_display_suspend(struct drm_device *dev)
6269{
6270 struct drm_i915_private *dev_priv = to_i915(dev);
6271 struct drm_crtc *crtc;
6272
6273 for_each_crtc(dev, crtc) {
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6275 enum intel_display_power_domain domain;
6276 unsigned long domains;
6277
6278 if (!intel_crtc->active)
6279 continue;
6280
6281 intel_crtc_disable_planes(crtc);
6282 dev_priv->display.crtc_disable(crtc);
6283
6284 domains = intel_crtc->enabled_power_domains;
6285 for_each_power_domain(domain, domains)
6286 intel_display_power_put(dev_priv, domain);
6287 intel_crtc->enabled_power_domains = 0;
6288 }
6289}
6290
b04c5bd6
BF		 6291/* Master function to enable/disable CRTC and corresponding power wells */
6292void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6293{
6294 struct drm_device *dev = crtc->dev;
6295 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6297 enum intel_display_power_domain domain;
6298 unsigned long domains;
976f8a20 6299
1b509259
ML		 6300 if (enable == intel_crtc->active)
6301 return;
6302
6303 if (enable && !crtc->state->enable)
6304 return;
6305
6306 crtc->state->active = enable;
0e572fe7 6307 if (enable) {
1b509259
ML		 6308 domains = get_crtc_power_domains(crtc);
6309 for_each_power_domain(domain, domains)
6310 intel_display_power_get(dev_priv, domain);
6311 intel_crtc->enabled_power_domains = domains;
6312
6313 dev_priv->display.crtc_enable(crtc);
6314 intel_crtc_enable_planes(crtc);
0e572fe7 6315 } else {
1b509259
ML		 6316 intel_crtc_disable_planes(crtc);
6317 dev_priv->display.crtc_disable(crtc);
6318
6319 domains = intel_crtc->enabled_power_domains;
6320 for_each_power_domain(domain, domains)
6321 intel_display_power_put(dev_priv, domain);
6322 intel_crtc->enabled_power_domains = 0;
0e572fe7 6323 }
b04c5bd6
BF		 6324}
6325
6326/**
6327 * Sets the power management mode of the pipe and plane.
6328 */
6329void intel_crtc_update_dpms(struct drm_crtc *crtc)
6330{
6331 struct drm_device *dev = crtc->dev;
6332 struct intel_encoder *intel_encoder;
6333 bool enable = false;
6334
6335 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6336 enable |= intel_encoder->connectors_active;
6337
6338 intel_crtc_control(crtc, enable);
976f8a20
DV		 6339}
6340
ea5b213a 6341void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6342{
4ef69c7a 6343 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6344
ea5b213a
CW		 6345 drm_encoder_cleanup(encoder);
6346 kfree(intel_encoder);
7e7d76c3
JB		 6347}
6348
9237329d 6349/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6350 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6351 * state of the entire output pipe. */
9237329d 6352static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6353{
5ab432ef
DV		 6354 if (mode == DRM_MODE_DPMS_ON) {
6355 encoder->connectors_active = true;
6356
b2cabb0e 6357 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6358 } else {
6359 encoder->connectors_active = false;
6360
b2cabb0e 6361 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6362 }
79e53945
JB		 6363}
6364
0a91ca29
DV		 6365/* Cross check the actual hw state with our own modeset state tracking (and it's
6366 * internal consistency). */
b980514c 6367static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6368{
0a91ca29
DV		 6369 if (connector->get_hw_state(connector)) {
6370 struct intel_encoder *encoder = connector->encoder;
6371 struct drm_crtc *crtc;
6372 bool encoder_enabled;
6373 enum pipe pipe;
6374
6375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6376 connector->base.base.id,
c23cc417 6377 connector->base.name);
0a91ca29 6378
0e32b39c
DA		 6379 /* there is no real hw state for MST connectors */
6380 if (connector->mst_port)
6381 return;
6382
e2c719b7 6383 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6384 "wrong connector dpms state\n");
e2c719b7 6385 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6386 "active connector not linked to encoder\n");
0a91ca29 6387
36cd7444 6388 if (encoder) {
e2c719b7 6389 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6390 "encoder->connectors_active not set\n");
6391
6392 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6393 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6394 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6395 return;
0a91ca29 6396
36cd7444 6397 crtc = encoder->base.crtc;
0a91ca29 6398
83d65738
MR		 6399 I915_STATE_WARN(!crtc->state->enable,
6400 "crtc not enabled\n");
e2c719b7
RC		 6401 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6402 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6403 "encoder active on the wrong pipe\n");
6404 }
0a91ca29 6405 }
79e53945
JB		 6406}
6407
08d9bc92
ACO		 6408int intel_connector_init(struct intel_connector *connector)
6409{
6410 struct drm_connector_state *connector_state;
6411
6412 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6413 if (!connector_state)
6414 return -ENOMEM;
6415
6416 connector->base.state = connector_state;
6417 return 0;
6418}
6419
6420struct intel_connector *intel_connector_alloc(void)
6421{
6422 struct intel_connector *connector;
6423
6424 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6425 if (!connector)
6426 return NULL;
6427
6428 if (intel_connector_init(connector) < 0) {
6429 kfree(connector);
6430 return NULL;
6431 }
6432
6433 return connector;
6434}
6435
5ab432ef
DV		 6436/* Even simpler default implementation, if there's really no special case to
6437 * consider. */
6438void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6439{
5ab432ef
DV		 6440 /* All the simple cases only support two dpms states. */
6441 if (mode != DRM_MODE_DPMS_ON)
6442 mode = DRM_MODE_DPMS_OFF;
d4270e57 6443
5ab432ef
DV		 6444 if (mode == connector->dpms)
6445 return;
6446
6447 connector->dpms = mode;
6448
6449 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6450 if (connector->encoder)
6451 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6452
b980514c 6453 intel_modeset_check_state(connector->dev);
79e53945
JB		 6454}
6455
f0947c37
DV		 6456/* Simple connector->get_hw_state implementation for encoders that support only
6457 * one connector and no cloning and hence the encoder state determines the state
6458 * of the connector. */
6459bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6460{
24929352 6461 enum pipe pipe = 0;
f0947c37 6462 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6463
f0947c37 6464 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6465}
6466
6d293983 6467static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6468{
6d293983
ACO		 6469 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6470 return crtc_state->fdi_lanes;
d272ddfa
VS		 6471
6472 return 0;
6473}
6474
6d293983 6475static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6476 struct intel_crtc_state *pipe_config)
1857e1da 6477{
6d293983
ACO		 6478 struct drm_atomic_state *state = pipe_config->base.state;
6479 struct intel_crtc *other_crtc;
6480 struct intel_crtc_state *other_crtc_state;
6481
1857e1da
DV		 6482 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6483 pipe_name(pipe), pipe_config->fdi_lanes);
6484 if (pipe_config->fdi_lanes > 4) {
6485 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6486 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6487 return -EINVAL;
1857e1da
DV		 6488 }
6489
bafb6553 6490 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6491 if (pipe_config->fdi_lanes > 2) {
6492 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6493 pipe_config->fdi_lanes);
6d293983 6494 return -EINVAL;
1857e1da 6495 } else {
6d293983 6496 return 0;
1857e1da
DV		 6497 }
6498 }
6499
6500 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6501 return 0;
1857e1da
DV		 6502
6503 /* Ivybridge 3 pipe is really complicated */
6504 switch (pipe) {
6505 case PIPE_A:
6d293983 6506 return 0;
1857e1da 6507 case PIPE_B:
6d293983
ACO		 6508 if (pipe_config->fdi_lanes <= 2)
6509 return 0;
6510
6511 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6512 other_crtc_state =
6513 intel_atomic_get_crtc_state(state, other_crtc);
6514 if (IS_ERR(other_crtc_state))
6515 return PTR_ERR(other_crtc_state);
6516
6517 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6518 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6519 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6520 return -EINVAL;
1857e1da 6521 }
6d293983 6522 return 0;
1857e1da 6523 case PIPE_C:
251cc67c
VS		 6524 if (pipe_config->fdi_lanes > 2) {
6525 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6526 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6527 return -EINVAL;
251cc67c 6528 }
6d293983
ACO		 6529
6530 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6531 other_crtc_state =
6532 intel_atomic_get_crtc_state(state, other_crtc);
6533 if (IS_ERR(other_crtc_state))
6534 return PTR_ERR(other_crtc_state);
6535
6536 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6537 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6538 return -EINVAL;
1857e1da 6539 }
6d293983 6540 return 0;
1857e1da
DV		 6541 default:
6542 BUG();
6543 }
6544}
6545
e29c22c0
DV		 6546#define RETRY 1
6547static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6548 struct intel_crtc_state *pipe_config)
877d48d5 6549{
1857e1da 6550 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6551 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6552 int lane, link_bw, fdi_dotclock, ret;
6553 bool needs_recompute = false;
877d48d5 6554
e29c22c0 6555retry:
877d48d5
DV		 6556 /* FDI is a binary signal running at ~2.7GHz, encoding
6557 * each output octet as 10 bits. The actual frequency
6558 * is stored as a divider into a 100MHz clock, and the
6559 * mode pixel clock is stored in units of 1KHz.
6560 * Hence the bw of each lane in terms of the mode signal
6561 * is:
6562 */
6563 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6564
241bfc38 6565 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6566
2bd89a07 6567 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6568 pipe_config->pipe_bpp);
6569
6570 pipe_config->fdi_lanes = lane;
6571
2bd89a07 6572 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6573 link_bw, &pipe_config->fdi_m_n);
1857e1da 6574
6d293983
ACO		 6575 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6576 intel_crtc->pipe, pipe_config);
6577 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6578 pipe_config->pipe_bpp -= 2*3;
6579 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6580 pipe_config->pipe_bpp);
6581 needs_recompute = true;
6582 pipe_config->bw_constrained = true;
6583
6584 goto retry;
6585 }
6586
6587 if (needs_recompute)
6588 return RETRY;
6589
6d293983 6590 return ret;
877d48d5
DV		 6591}
6592
8cfb3407
VS		 6593static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6594 struct intel_crtc_state *pipe_config)
6595{
6596 if (pipe_config->pipe_bpp > 24)
6597 return false;
6598
6599 /* HSW can handle pixel rate up to cdclk? */
6600 if (IS_HASWELL(dev_priv->dev))
6601 return true;
6602
6603 /*
b432e5cf
VS		 6604 * We compare against max which means we must take
6605 * the increased cdclk requirement into account when
6606 * calculating the new cdclk.
6607 *
6608 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6609 */
6610 return ilk_pipe_pixel_rate(pipe_config) <=
6611 dev_priv->max_cdclk_freq * 95 / 100;
6612}
6613
42db64ef 6614static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6615 struct intel_crtc_state *pipe_config)
42db64ef 6616{
8cfb3407
VS		 6617 struct drm_device *dev = crtc->base.dev;
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619
d330a953 6620 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6621 hsw_crtc_supports_ips(crtc) &&
6622 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6623}
6624
a43f6e0f 6625static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6626 struct intel_crtc_state *pipe_config)
79e53945 6627{
a43f6e0f 6628 struct drm_device *dev = crtc->base.dev;
8bd31e67 6629 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6630 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6631 int ret;
89749350 6632
ad3a4479 6633 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6634 if (INTEL_INFO(dev)->gen < 4) {
44913155 6635 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6636
6637 /*
6638 * Enable pixel doubling when the dot clock
6639 * is > 90% of the (display) core speed.
6640 *
b397c96b
VS		 6641 * GDG double wide on either pipe,
6642 * otherwise pipe A only.
cf532bb2 6643 */
b397c96b 6644 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6645 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6646 clock_limit *= 2;
cf532bb2 6647 pipe_config->double_wide = true;
ad3a4479
VS		 6648 }
6649
241bfc38 6650 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6651 return -EINVAL;
2c07245f 6652 }
89749350 6653
1d1d0e27
VS		 6654 /*
6655 * Pipe horizontal size must be even in:
6656 * - DVO ganged mode
6657 * - LVDS dual channel mode
6658 * - Double wide pipe
6659 */
a93e255f 6660 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6661 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6662 pipe_config->pipe_src_w &= ~1;
6663
8693a824
DL		 6664 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6665 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6666 */
6667 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6668 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6669 return -EINVAL;
44f46b42 6670
f5adf94e 6671 if (HAS_IPS(dev))
a43f6e0f
DV		 6672 hsw_compute_ips_config(crtc, pipe_config);
6673
877d48d5 6674 if (pipe_config->has_pch_encoder)
a43f6e0f 6675 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6676
d03c93d4
CK		 6677 /* FIXME: remove below call once atomic mode set is place and all crtc
6678 * related checks called from atomic_crtc_check function */
6679 ret = 0;
6680 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6681 crtc, pipe_config->base.state);
6682 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6683
6684 return ret;
79e53945
JB		 6685}
6686
1652d19e
VS		 6687static int skylake_get_display_clock_speed(struct drm_device *dev)
6688{
6689 struct drm_i915_private *dev_priv = to_i915(dev);
6690 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6691 uint32_t cdctl = I915_READ(CDCLK_CTL);
6692 uint32_t linkrate;
6693
414355a7 6694 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6695 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6696
6697 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6698 return 540000;
6699
6700 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6701 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6702
71cd8423
DL		 6703 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6704 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6705 /* vco 8640 */
6706 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6707 case CDCLK_FREQ_450_432:
6708 return 432000;
6709 case CDCLK_FREQ_337_308:
6710 return 308570;
6711 case CDCLK_FREQ_675_617:
6712 return 617140;
6713 default:
6714 WARN(1, "Unknown cd freq selection\n");
6715 }
6716 } else {
6717 /* vco 8100 */
6718 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6719 case CDCLK_FREQ_450_432:
6720 return 450000;
6721 case CDCLK_FREQ_337_308:
6722 return 337500;
6723 case CDCLK_FREQ_675_617:
6724 return 675000;
6725 default:
6726 WARN(1, "Unknown cd freq selection\n");
6727 }
6728 }
6729
6730 /* error case, do as if DPLL0 isn't enabled */
6731 return 24000;
6732}
6733
6734static int broadwell_get_display_clock_speed(struct drm_device *dev)
6735{
6736 struct drm_i915_private *dev_priv = dev->dev_private;
6737 uint32_t lcpll = I915_READ(LCPLL_CTL);
6738 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6739
6740 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6741 return 800000;
6742 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6743 return 450000;
6744 else if (freq == LCPLL_CLK_FREQ_450)
6745 return 450000;
6746 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6747 return 540000;
6748 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6749 return 337500;
6750 else
6751 return 675000;
6752}
6753
6754static int haswell_get_display_clock_speed(struct drm_device *dev)
6755{
6756 struct drm_i915_private *dev_priv = dev->dev_private;
6757 uint32_t lcpll = I915_READ(LCPLL_CTL);
6758 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6759
6760 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6761 return 800000;
6762 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6763 return 450000;
6764 else if (freq == LCPLL_CLK_FREQ_450)
6765 return 450000;
6766 else if (IS_HSW_ULT(dev))
6767 return 337500;
6768 else
6769 return 540000;
79e53945
JB		 6770}
6771
25eb05fc
JB		 6772static int valleyview_get_display_clock_speed(struct drm_device *dev)
6773{
d197b7d3 6774 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6775 u32 val;
6776 int divider;
6777
6bcda4f0
VS		 6778 if (dev_priv->hpll_freq == 0)
6779 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6780
a580516d 6781 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6782 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6783 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6784
6785 divider = val & DISPLAY_FREQUENCY_VALUES;
6786
7d007f40
VS		 6787 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6788 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6789 "cdclk change in progress\n");
6790
6bcda4f0 6791 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6792}
6793
b37a6434
VS		 6794static int ilk_get_display_clock_speed(struct drm_device *dev)
6795{
6796 return 450000;
6797}
6798
e70236a8
JB		 6799static int i945_get_display_clock_speed(struct drm_device *dev)
6800{
6801 return 400000;
6802}
79e53945 6803
e70236a8 6804static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6805{
e907f170 6806 return 333333;
e70236a8 6807}
79e53945 6808
e70236a8
JB		 6809static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6810{
6811 return 200000;
6812}
79e53945 6813
257a7ffc
DV		 6814static int pnv_get_display_clock_speed(struct drm_device *dev)
6815{
6816 u16 gcfgc = 0;
6817
6818 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6819
6820 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6821 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6822 return 266667;
257a7ffc 6823 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6824 return 333333;
257a7ffc 6825 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6826 return 444444;
257a7ffc
DV		 6827 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6828 return 200000;
6829 default:
6830 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6831 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6832 return 133333;
257a7ffc 6833 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6834 return 166667;
257a7ffc
DV		 6835 }
6836}
6837
e70236a8
JB		 6838static int i915gm_get_display_clock_speed(struct drm_device *dev)
6839{
6840 u16 gcfgc = 0;
79e53945 6841
e70236a8
JB		 6842 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6843
6844 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6845 return 133333;
e70236a8
JB		 6846 else {
6847 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6848 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6849 return 333333;
e70236a8
JB		 6850 default:
6851 case GC_DISPLAY_CLOCK_190_200_MHZ:
6852 return 190000;
79e53945 6853 }
e70236a8
JB		 6854 }
6855}
6856
6857static int i865_get_display_clock_speed(struct drm_device *dev)
6858{
e907f170 6859 return 266667;
e70236a8
JB		 6860}
6861
1b1d2716 6862static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6863{
6864 u16 hpllcc = 0;
1b1d2716 6865
65cd2b3f
VS		 6866 /*
6867 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6868 * encoding is different :(
6869 * FIXME is this the right way to detect 852GM/852GMV?
6870 */
6871 if (dev->pdev->revision == 0x1)
6872 return 133333;
6873
1b1d2716
VS		 6874 pci_bus_read_config_word(dev->pdev->bus,
6875 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6876
e70236a8
JB		 6877 /* Assume that the hardware is in the high speed state. This
6878 * should be the default.
6879 */
6880 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6881 case GC_CLOCK_133_200:
1b1d2716 6882 case GC_CLOCK_133_200_2:
e70236a8
JB		 6883 case GC_CLOCK_100_200:
6884 return 200000;
6885 case GC_CLOCK_166_250:
6886 return 250000;
6887 case GC_CLOCK_100_133:
e907f170 6888 return 133333;
1b1d2716
VS		 6889 case GC_CLOCK_133_266:
6890 case GC_CLOCK_133_266_2:
6891 case GC_CLOCK_166_266:
6892 return 266667;
e70236a8 6893 }
79e53945 6894
e70236a8
JB		 6895 /* Shouldn't happen */
6896 return 0;
6897}
79e53945 6898
e70236a8
JB		 6899static int i830_get_display_clock_speed(struct drm_device *dev)
6900{
e907f170 6901 return 133333;
79e53945
JB		 6902}
6903
34edce2f
VS		 6904static unsigned int intel_hpll_vco(struct drm_device *dev)
6905{
6906 struct drm_i915_private *dev_priv = dev->dev_private;
6907 static const unsigned int blb_vco[8] = {
6908 [0] = 3200000,
6909 [1] = 4000000,
6910 [2] = 5333333,
6911 [3] = 4800000,
6912 [4] = 6400000,
6913 };
6914 static const unsigned int pnv_vco[8] = {
6915 [0] = 3200000,
6916 [1] = 4000000,
6917 [2] = 5333333,
6918 [3] = 4800000,
6919 [4] = 2666667,
6920 };
6921 static const unsigned int cl_vco[8] = {
6922 [0] = 3200000,
6923 [1] = 4000000,
6924 [2] = 5333333,
6925 [3] = 6400000,
6926 [4] = 3333333,
6927 [5] = 3566667,
6928 [6] = 4266667,
6929 };
6930 static const unsigned int elk_vco[8] = {
6931 [0] = 3200000,
6932 [1] = 4000000,
6933 [2] = 5333333,
6934 [3] = 4800000,
6935 };
6936 static const unsigned int ctg_vco[8] = {
6937 [0] = 3200000,
6938 [1] = 4000000,
6939 [2] = 5333333,
6940 [3] = 6400000,
6941 [4] = 2666667,
6942 [5] = 4266667,
6943 };
6944 const unsigned int *vco_table;
6945 unsigned int vco;
6946 uint8_t tmp = 0;
6947
6948 /* FIXME other chipsets? */
6949 if (IS_GM45(dev))
6950 vco_table = ctg_vco;
6951 else if (IS_G4X(dev))
6952 vco_table = elk_vco;
6953 else if (IS_CRESTLINE(dev))
6954 vco_table = cl_vco;
6955 else if (IS_PINEVIEW(dev))
6956 vco_table = pnv_vco;
6957 else if (IS_G33(dev))
6958 vco_table = blb_vco;
6959 else
6960 return 0;
6961
6962 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6963
6964 vco = vco_table[tmp & 0x7];
6965 if (vco == 0)
6966 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6967 else
6968 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6969
6970 return vco;
6971}
6972
6973static int gm45_get_display_clock_speed(struct drm_device *dev)
6974{
6975 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6976 uint16_t tmp = 0;
6977
6978 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6979
6980 cdclk_sel = (tmp >> 12) & 0x1;
6981
6982 switch (vco) {
6983 case 2666667:
6984 case 4000000:
6985 case 5333333:
6986 return cdclk_sel ? 333333 : 222222;
6987 case 3200000:
6988 return cdclk_sel ? 320000 : 228571;
6989 default:
6990 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6991 return 222222;
6992 }
6993}
6994
6995static int i965gm_get_display_clock_speed(struct drm_device *dev)
6996{
6997 static const uint8_t div_3200[] = { 16, 10, 8 };
6998 static const uint8_t div_4000[] = { 20, 12, 10 };
6999 static const uint8_t div_5333[] = { 24, 16, 14 };
7000 const uint8_t *div_table;
7001 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7002 uint16_t tmp = 0;
7003
7004 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7005
7006 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7007
7008 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7009 goto fail;
7010
7011 switch (vco) {
7012 case 3200000:
7013 div_table = div_3200;
7014 break;
7015 case 4000000:
7016 div_table = div_4000;
7017 break;
7018 case 5333333:
7019 div_table = div_5333;
7020 break;
7021 default:
7022 goto fail;
7023 }
7024
7025 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7026
7027 fail:
7028 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7029 return 200000;
7030}
7031
7032static int g33_get_display_clock_speed(struct drm_device *dev)
7033{
7034 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7035 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7036 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7037 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7038 const uint8_t *div_table;
7039 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7040 uint16_t tmp = 0;
7041
7042 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7043
7044 cdclk_sel = (tmp >> 4) & 0x7;
7045
7046 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7047 goto fail;
7048
7049 switch (vco) {
7050 case 3200000:
7051 div_table = div_3200;
7052 break;
7053 case 4000000:
7054 div_table = div_4000;
7055 break;
7056 case 4800000:
7057 div_table = div_4800;
7058 break;
7059 case 5333333:
7060 div_table = div_5333;
7061 break;
7062 default:
7063 goto fail;
7064 }
7065
7066 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7067
7068 fail:
7069 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7070 return 190476;
7071}
7072
2c07245f 7073static void
a65851af 7074intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7075{
a65851af
VS		 7076 while (*num > DATA_LINK_M_N_MASK ||
7077 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7078 *num >>= 1;
7079 *den >>= 1;
7080 }
7081}
7082
a65851af
VS		 7083static void compute_m_n(unsigned int m, unsigned int n,
7084 uint32_t *ret_m, uint32_t *ret_n)
7085{
7086 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7087 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7088 intel_reduce_m_n_ratio(ret_m, ret_n);
7089}
7090
e69d0bc1
DV		 7091void
7092intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7093 int pixel_clock, int link_clock,
7094 struct intel_link_m_n *m_n)
2c07245f 7095{
e69d0bc1 7096 m_n->tu = 64;
a65851af
VS		 7097
7098 compute_m_n(bits_per_pixel * pixel_clock,
7099 link_clock * nlanes * 8,
7100 &m_n->gmch_m, &m_n->gmch_n);
7101
7102 compute_m_n(pixel_clock, link_clock,
7103 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7104}
7105
a7615030
CW		 7106static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7107{
d330a953
JN		 7108 if (i915.panel_use_ssc >= 0)
7109 return i915.panel_use_ssc != 0;
41aa3448 7110 return dev_priv->vbt.lvds_use_ssc
435793df 7111 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7112}
7113
a93e255f
ACO		 7114static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7115 int num_connectors)
c65d77d8 7116{
a93e255f 7117 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7118 struct drm_i915_private *dev_priv = dev->dev_private;
7119 int refclk;
7120
a93e255f
ACO		 7121 WARN_ON(!crtc_state->base.state);
7122
5ab7b0b7 7123 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7124 refclk = 100000;
a93e255f 7125 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7126 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7127 refclk = dev_priv->vbt.lvds_ssc_freq;
7128 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7129 } else if (!IS_GEN2(dev)) {
7130 refclk = 96000;
7131 } else {
7132 refclk = 48000;
7133 }
7134
7135 return refclk;
7136}
7137
7429e9d4 7138static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7139{
7df00d7a 7140 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7141}
f47709a9 7142
7429e9d4
DV		 7143static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7144{
7145 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7146}
7147
f47709a9 7148static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7149 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7150 intel_clock_t *reduced_clock)
7151{
f47709a9 7152 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7153 u32 fp, fp2 = 0;
7154
7155 if (IS_PINEVIEW(dev)) {
190f68c5 7156 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7157 if (reduced_clock)
7429e9d4 7158 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7159 } else {
190f68c5 7160 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7161 if (reduced_clock)
7429e9d4 7162 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7163 }
7164
190f68c5 7165 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7166
f47709a9 7167 crtc->lowfreq_avail = false;
a93e255f 7168 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7169 reduced_clock) {
190f68c5 7170 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7171 crtc->lowfreq_avail = true;
a7516a05 7172 } else {
190f68c5 7173 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7174 }
7175}
7176
5e69f97f
CML		 7177static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7178 pipe)
89b667f8
JB		 7179{
7180 u32 reg_val;
7181
7182 /*
7183 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7184 * and set it to a reasonable value instead.
7185 */
ab3c759a 7186 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7187 reg_val &= 0xffffff00;
7188 reg_val |= 0x00000030;
ab3c759a 7189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7190
ab3c759a 7191 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7192 reg_val &= 0x8cffffff;
7193 reg_val = 0x8c000000;
ab3c759a 7194 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7195
ab3c759a 7196 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7197 reg_val &= 0xffffff00;
ab3c759a 7198 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7199
ab3c759a 7200 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7201 reg_val &= 0x00ffffff;
7202 reg_val |= 0xb0000000;
ab3c759a 7203 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7204}
7205
b551842d
DV		 7206static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7207 struct intel_link_m_n *m_n)
7208{
7209 struct drm_device *dev = crtc->base.dev;
7210 struct drm_i915_private *dev_priv = dev->dev_private;
7211 int pipe = crtc->pipe;
7212
e3b95f1e
DV		 7213 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7214 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7215 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7216 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7217}
7218
7219static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7220 struct intel_link_m_n *m_n,
7221 struct intel_link_m_n *m2_n2)
b551842d
DV		 7222{
7223 struct drm_device *dev = crtc->base.dev;
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 int pipe = crtc->pipe;
6e3c9717 7226 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7227
7228 if (INTEL_INFO(dev)->gen >= 5) {
7229 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7230 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7231 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7232 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7233 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7234 * for gen < 8) and if DRRS is supported (to make sure the
7235 * registers are not unnecessarily accessed).
7236 */
44395bfe 7237 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7238 crtc->config->has_drrs) {
f769cd24
VK		 7239 I915_WRITE(PIPE_DATA_M2(transcoder),
7240 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7241 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7242 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7243 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7244 }
b551842d 7245 } else {
e3b95f1e
DV		 7246 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7247 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7248 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7249 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7250 }
7251}
7252
fe3cd48d 7253void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7254{
fe3cd48d
R		 7255 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7256
7257 if (m_n == M1_N1) {
7258 dp_m_n = &crtc->config->dp_m_n;
7259 dp_m2_n2 = &crtc->config->dp_m2_n2;
7260 } else if (m_n == M2_N2) {
7261
7262 /*
7263 * M2_N2 registers are not supported. Hence m2_n2 divider value
7264 * needs to be programmed into M1_N1.
7265 */
7266 dp_m_n = &crtc->config->dp_m2_n2;
7267 } else {
7268 DRM_ERROR("Unsupported divider value\n");
7269 return;
7270 }
7271
6e3c9717
ACO		 7272 if (crtc->config->has_pch_encoder)
7273 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7274 else
fe3cd48d 7275 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7276}
7277
d288f65f 7278static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7279 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7280{
7281 u32 dpll, dpll_md;
7282
7283 /*
7284 * Enable DPIO clock input. We should never disable the reference
7285 * clock for pipe B, since VGA hotplug / manual detection depends
7286 * on it.
7287 */
7288 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7289 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7290 /* We should never disable this, set it here for state tracking */
7291 if (crtc->pipe == PIPE_B)
7292 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7293 dpll |= DPLL_VCO_ENABLE;
d288f65f 7294 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7295
d288f65f 7296 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7297 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7298 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7299}
7300
d288f65f 7301static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7302 const struct intel_crtc_state *pipe_config)
a0c4da24 7303{
f47709a9 7304 struct drm_device *dev = crtc->base.dev;
a0c4da24 7305 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7306 int pipe = crtc->pipe;
bdd4b6a6 7307 u32 mdiv;
a0c4da24 7308 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7309 u32 coreclk, reg_val;
a0c4da24 7310
a580516d 7311 mutex_lock(&dev_priv->sb_lock);
09153000 7312
d288f65f
VS		 7313 bestn = pipe_config->dpll.n;
7314 bestm1 = pipe_config->dpll.m1;
7315 bestm2 = pipe_config->dpll.m2;
7316 bestp1 = pipe_config->dpll.p1;
7317 bestp2 = pipe_config->dpll.p2;
a0c4da24 7318
89b667f8
JB		 7319 /* See eDP HDMI DPIO driver vbios notes doc */
7320
7321 /* PLL B needs special handling */
bdd4b6a6 7322 if (pipe == PIPE_B)
5e69f97f 7323 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7324
7325 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7326 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7327
7328 /* Disable target IRef on PLL */
ab3c759a 7329 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7330 reg_val &= 0x00ffffff;
ab3c759a 7331 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7332
7333 /* Disable fast lock */
ab3c759a 7334 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7335
7336 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7337 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7338 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7339 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7340 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7341
7342 /*
7343 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7344 * but we don't support that).
7345 * Note: don't use the DAC post divider as it seems unstable.
7346 */
7347 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7349
a0c4da24 7350 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7352
89b667f8 7353 /* Set HBR and RBR LPF coefficients */
d288f65f 7354 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7355 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7356 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7357 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7358 0x009f0003);
89b667f8 7359 else
ab3c759a 7360 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7361 0x00d0000f);
7362
681a8504 7363 if (pipe_config->has_dp_encoder) {
89b667f8 7364 /* Use SSC source */
bdd4b6a6 7365 if (pipe == PIPE_A)
ab3c759a 7366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7367 0x0df40000);
7368 else
ab3c759a 7369 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7370 0x0df70000);
7371 } else { /* HDMI or VGA */
7372 /* Use bend source */
bdd4b6a6 7373 if (pipe == PIPE_A)
ab3c759a 7374 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7375 0x0df70000);
7376 else
ab3c759a 7377 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7378 0x0df40000);
7379 }
a0c4da24 7380
ab3c759a 7381 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7382 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7383 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7384 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7385 coreclk |= 0x01000000;
ab3c759a 7386 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7387
ab3c759a 7388 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7389 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7390}
7391
d288f65f 7392static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7393 struct intel_crtc_state *pipe_config)
1ae0d137 7394{
d288f65f 7395 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7396 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7397 DPLL_VCO_ENABLE;
7398 if (crtc->pipe != PIPE_A)
d288f65f 7399 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7400
d288f65f
VS		 7401 pipe_config->dpll_hw_state.dpll_md =
7402 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7403}
7404
d288f65f 7405static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7406 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7407{
7408 struct drm_device *dev = crtc->base.dev;
7409 struct drm_i915_private *dev_priv = dev->dev_private;
7410 int pipe = crtc->pipe;
7411 int dpll_reg = DPLL(crtc->pipe);
7412 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7413 u32 loopfilter, tribuf_calcntr;
9d556c99 7414 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7415 u32 dpio_val;
9cbe40c1 7416 int vco;
9d556c99 7417
d288f65f
VS		 7418 bestn = pipe_config->dpll.n;
7419 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7420 bestm1 = pipe_config->dpll.m1;
7421 bestm2 = pipe_config->dpll.m2 >> 22;
7422 bestp1 = pipe_config->dpll.p1;
7423 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7424 vco = pipe_config->dpll.vco;
a945ce7e 7425 dpio_val = 0;
9cbe40c1 7426 loopfilter = 0;
9d556c99
CML		 7427
7428 /*
7429 * Enable Refclk and SSC
7430 */
a11b0703 7431 I915_WRITE(dpll_reg,
d288f65f 7432 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7433
a580516d 7434 mutex_lock(&dev_priv->sb_lock);
9d556c99 7435
9d556c99
CML		 7436 /* p1 and p2 divider */
7437 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7438 5 << DPIO_CHV_S1_DIV_SHIFT |
7439 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7440 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7441 1 << DPIO_CHV_K_DIV_SHIFT);
7442
7443 /* Feedback post-divider - m2 */
7444 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7445
7446 /* Feedback refclk divider - n and m1 */
7447 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7448 DPIO_CHV_M1_DIV_BY_2 |
7449 1 << DPIO_CHV_N_DIV_SHIFT);
7450
7451 /* M2 fraction division */
a945ce7e
VP		 7452 if (bestm2_frac)
7453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7454
7455 /* M2 fraction division enable */
a945ce7e
VP		 7456 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7457 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7458 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7459 if (bestm2_frac)
7460 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7461 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7462
de3a0fde
VP		 7463 /* Program digital lock detect threshold */
7464 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7465 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7466 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7467 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7468 if (!bestm2_frac)
7469 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7470 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7471
9d556c99 7472 /* Loop filter */
9cbe40c1
VP		 7473 if (vco == 5400000) {
7474 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7475 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7476 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7477 tribuf_calcntr = 0x9;
7478 } else if (vco <= 6200000) {
7479 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7480 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7481 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7482 tribuf_calcntr = 0x9;
7483 } else if (vco <= 6480000) {
7484 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7485 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7486 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7487 tribuf_calcntr = 0x8;
7488 } else {
7489 /* Not supported. Apply the same limits as in the max case */
7490 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7491 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7492 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7493 tribuf_calcntr = 0;
7494 }
9d556c99
CML		 7495 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7496
968040b2 7497 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7498 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7499 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7500 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7501
9d556c99
CML		 7502 /* AFC Recal */
7503 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7504 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7505 DPIO_AFC_RECAL);
7506
a580516d 7507 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7508}
7509
d288f65f
VS		 7510/**
7511 * vlv_force_pll_on - forcibly enable just the PLL
7512 * @dev_priv: i915 private structure
7513 * @pipe: pipe PLL to enable
7514 * @dpll: PLL configuration
7515 *
7516 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7517 * in cases where we need the PLL enabled even when @pipe is not going to
7518 * be enabled.
7519 */
7520void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7521 const struct dpll *dpll)
7522{
7523 struct intel_crtc *crtc =
7524 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7525 struct intel_crtc_state pipe_config = {
a93e255f 7526 .base.crtc = &crtc->base,
d288f65f
VS		 7527 .pixel_multiplier = 1,
7528 .dpll = *dpll,
7529 };
7530
7531 if (IS_CHERRYVIEW(dev)) {
7532 chv_update_pll(crtc, &pipe_config);
7533 chv_prepare_pll(crtc, &pipe_config);
7534 chv_enable_pll(crtc, &pipe_config);
7535 } else {
7536 vlv_update_pll(crtc, &pipe_config);
7537 vlv_prepare_pll(crtc, &pipe_config);
7538 vlv_enable_pll(crtc, &pipe_config);
7539 }
7540}
7541
7542/**
7543 * vlv_force_pll_off - forcibly disable just the PLL
7544 * @dev_priv: i915 private structure
7545 * @pipe: pipe PLL to disable
7546 *
7547 * Disable the PLL for @pipe. To be used in cases where we need
7548 * the PLL enabled even when @pipe is not going to be enabled.
7549 */
7550void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7551{
7552 if (IS_CHERRYVIEW(dev))
7553 chv_disable_pll(to_i915(dev), pipe);
7554 else
7555 vlv_disable_pll(to_i915(dev), pipe);
7556}
7557
f47709a9 7558static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7559 struct intel_crtc_state *crtc_state,
f47709a9 7560 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7561 int num_connectors)
7562{
f47709a9 7563 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7564 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7565 u32 dpll;
7566 bool is_sdvo;
190f68c5 7567 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7568
190f68c5 7569 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7570
a93e255f
ACO		 7571 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7572 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7573
7574 dpll = DPLL_VGA_MODE_DIS;
7575
a93e255f 7576 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7577 dpll |= DPLLB_MODE_LVDS;
7578 else
7579 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7580
ef1b460d 7581 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7582 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7583 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7584 }
198a037f
DV		 7585
7586 if (is_sdvo)
4a33e48d 7587 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7588
190f68c5 7589 if (crtc_state->has_dp_encoder)
4a33e48d 7590 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7591
7592 /* compute bitmask from p1 value */
7593 if (IS_PINEVIEW(dev))
7594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7595 else {
7596 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7597 if (IS_G4X(dev) && reduced_clock)
7598 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7599 }
7600 switch (clock->p2) {
7601 case 5:
7602 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7603 break;
7604 case 7:
7605 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7606 break;
7607 case 10:
7608 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7609 break;
7610 case 14:
7611 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7612 break;
7613 }
7614 if (INTEL_INFO(dev)->gen >= 4)
7615 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7616
190f68c5 7617 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7618 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7619 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7620 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7621 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7622 else
7623 dpll |= PLL_REF_INPUT_DREFCLK;
7624
7625 dpll |= DPLL_VCO_ENABLE;
190f68c5 7626 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7627
eb1cbe48 7628 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7629 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7630 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7631 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7632 }
7633}
7634
f47709a9 7635static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7636 struct intel_crtc_state *crtc_state,
f47709a9 7637 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7638 int num_connectors)
7639{
f47709a9 7640 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7641 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7642 u32 dpll;
190f68c5 7643 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7644
190f68c5 7645 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7646
eb1cbe48
DV		 7647 dpll = DPLL_VGA_MODE_DIS;
7648
a93e255f 7649 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7650 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7651 } else {
7652 if (clock->p1 == 2)
7653 dpll |= PLL_P1_DIVIDE_BY_TWO;
7654 else
7655 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7656 if (clock->p2 == 4)
7657 dpll |= PLL_P2_DIVIDE_BY_4;
7658 }
7659
a93e255f 7660 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7661 dpll |= DPLL_DVO_2X_MODE;
7662
a93e255f 7663 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7664 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7665 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7666 else
7667 dpll |= PLL_REF_INPUT_DREFCLK;
7668
7669 dpll |= DPLL_VCO_ENABLE;
190f68c5 7670 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7671}
7672
8a654f3b 7673static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7674{
7675 struct drm_device *dev = intel_crtc->base.dev;
7676 struct drm_i915_private *dev_priv = dev->dev_private;
7677 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7678 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7679 struct drm_display_mode *adjusted_mode =
6e3c9717 7680 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7681 uint32_t crtc_vtotal, crtc_vblank_end;
7682 int vsyncshift = 0;
4d8a62ea
DV		 7683
7684 /* We need to be careful not to changed the adjusted mode, for otherwise
7685 * the hw state checker will get angry at the mismatch. */
7686 crtc_vtotal = adjusted_mode->crtc_vtotal;
7687 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7688
609aeaca 7689 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7690 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7691 crtc_vtotal -= 1;
7692 crtc_vblank_end -= 1;
609aeaca 7693
409ee761 7694 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7695 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7696 else
7697 vsyncshift = adjusted_mode->crtc_hsync_start -
7698 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7699 if (vsyncshift < 0)
7700 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7701 }
7702
7703 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7704 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7705
fe2b8f9d 7706 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7707 (adjusted_mode->crtc_hdisplay - 1) |
7708 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7709 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7710 (adjusted_mode->crtc_hblank_start - 1) |
7711 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7712 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7713 (adjusted_mode->crtc_hsync_start - 1) |
7714 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7715
fe2b8f9d 7716 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7717 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7718 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7719 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7720 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7721 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7722 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7723 (adjusted_mode->crtc_vsync_start - 1) |
7724 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7725
b5e508d4
PZ		 7726 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7727 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7728 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7729 * bits. */
7730 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7731 (pipe == PIPE_B || pipe == PIPE_C))
7732 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7733
b0e77b9c
PZ		 7734 /* pipesrc controls the size that is scaled from, which should
7735 * always be the user's requested size.
7736 */
7737 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7738 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7739 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7740}
7741
1bd1bd80 7742static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7743 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7744{
7745 struct drm_device *dev = crtc->base.dev;
7746 struct drm_i915_private *dev_priv = dev->dev_private;
7747 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7748 uint32_t tmp;
7749
7750 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7751 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7752 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7753 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7754 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7755 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7756 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7757 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7758 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7759
7760 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7761 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7762 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7763 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7764 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7765 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7766 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7767 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7768 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7769
7770 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7771 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7772 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7773 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7774 }
7775
7776 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7777 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7778 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7779
2d112de7
ACO		 7780 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7781 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7782}
7783
f6a83288 7784void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7785 struct intel_crtc_state *pipe_config)
babea61d 7786{
2d112de7
ACO		 7787 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7788 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7789 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7790 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7791
2d112de7
ACO		 7792 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7793 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7794 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7795 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7796
2d112de7 7797 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7798
2d112de7
ACO		 7799 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7800 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7801}
7802
84b046f3
DV		 7803static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7804{
7805 struct drm_device *dev = intel_crtc->base.dev;
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 uint32_t pipeconf;
7808
9f11a9e4 7809 pipeconf = 0;
84b046f3 7810
b6b5d049
VS		 7811 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7812 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7813 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7814
6e3c9717 7815 if (intel_crtc->config->double_wide)
cf532bb2 7816 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7817
ff9ce46e
DV		 7818 /* only g4x and later have fancy bpc/dither controls */
7819 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7820 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7821 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7822 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7823 PIPECONF_DITHER_TYPE_SP;
84b046f3 7824
6e3c9717 7825 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7826 case 18:
7827 pipeconf |= PIPECONF_6BPC;
7828 break;
7829 case 24:
7830 pipeconf |= PIPECONF_8BPC;
7831 break;
7832 case 30:
7833 pipeconf |= PIPECONF_10BPC;
7834 break;
7835 default:
7836 /* Case prevented by intel_choose_pipe_bpp_dither. */
7837 BUG();
84b046f3
DV		 7838 }
7839 }
7840
7841 if (HAS_PIPE_CXSR(dev)) {
7842 if (intel_crtc->lowfreq_avail) {
7843 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7844 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7845 } else {
7846 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7847 }
7848 }
7849
6e3c9717 7850 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7851 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7852 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7853 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7854 else
7855 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7856 } else
84b046f3
DV		 7857 pipeconf |= PIPECONF_PROGRESSIVE;
7858
6e3c9717 7859 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7860 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7861
84b046f3
DV		 7862 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7863 POSTING_READ(PIPECONF(intel_crtc->pipe));
7864}
7865
190f68c5
ACO		 7866static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7867 struct intel_crtc_state *crtc_state)
79e53945 7868{
c7653199 7869 struct drm_device *dev = crtc->base.dev;
79e53945 7870 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7871 int refclk, num_connectors = 0;
652c393a 7872 intel_clock_t clock, reduced_clock;
a16af721 7873 bool ok, has_reduced_clock = false;
e9fd1c02 7874 bool is_lvds = false, is_dsi = false;
5eddb70b 7875 struct intel_encoder *encoder;
d4906093 7876 const intel_limit_t *limit;
55bb9992 7877 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7878 struct drm_connector *connector;
55bb9992
ACO		 7879 struct drm_connector_state *connector_state;
7880 int i;
79e53945 7881
dd3cd74a
ACO		 7882 memset(&crtc_state->dpll_hw_state, 0,
7883 sizeof(crtc_state->dpll_hw_state));
7884
da3ced29 7885 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7886 if (connector_state->crtc != &crtc->base)
7887 continue;
7888
7889 encoder = to_intel_encoder(connector_state->best_encoder);
7890
5eddb70b 7891 switch (encoder->type) {
79e53945
JB		 7892 case INTEL_OUTPUT_LVDS:
7893 is_lvds = true;
7894 break;
e9fd1c02
JN		 7895 case INTEL_OUTPUT_DSI:
7896 is_dsi = true;
7897 break;
6847d71b
PZ		 7898 default:
7899 break;
79e53945 7900 }
43565a06 7901
c751ce4f 7902 num_connectors++;
79e53945
JB		 7903 }
7904
f2335330 7905 if (is_dsi)
5b18e57c 7906 return 0;
f2335330 7907
190f68c5 7908 if (!crtc_state->clock_set) {
a93e255f 7909 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7910
e9fd1c02
JN		 7911 /*
7912 * Returns a set of divisors for the desired target clock with
7913 * the given refclk, or FALSE. The returned values represent
7914 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7915 * 2) / p1 / p2.
7916 */
a93e255f
ACO		 7917 limit = intel_limit(crtc_state, refclk);
7918 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7919 crtc_state->port_clock,
e9fd1c02 7920 refclk, NULL, &clock);
f2335330 7921 if (!ok) {
e9fd1c02
JN		 7922 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7923 return -EINVAL;
7924 }
79e53945 7925
f2335330
JN		 7926 if (is_lvds && dev_priv->lvds_downclock_avail) {
7927 /*
7928 * Ensure we match the reduced clock's P to the target
7929 * clock. If the clocks don't match, we can't switch
7930 * the display clock by using the FP0/FP1. In such case
7931 * we will disable the LVDS downclock feature.
7932 */
7933 has_reduced_clock =
a93e255f 7934 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7935 dev_priv->lvds_downclock,
7936 refclk, &clock,
7937 &reduced_clock);
7938 }
7939 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7940 crtc_state->dpll.n = clock.n;
7941 crtc_state->dpll.m1 = clock.m1;
7942 crtc_state->dpll.m2 = clock.m2;
7943 crtc_state->dpll.p1 = clock.p1;
7944 crtc_state->dpll.p2 = clock.p2;
f47709a9 7945 }
7026d4ac 7946
e9fd1c02 7947 if (IS_GEN2(dev)) {
190f68c5 7948 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7949 has_reduced_clock ? &reduced_clock : NULL,
7950 num_connectors);
9d556c99 7951 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7952 chv_update_pll(crtc, crtc_state);
e9fd1c02 7953 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7954 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7955 } else {
190f68c5 7956 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7957 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7958 num_connectors);
e9fd1c02 7959 }
79e53945 7960
c8f7a0db 7961 return 0;
f564048e
EA		 7962}
7963
2fa2fe9a 7964static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7965 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7966{
7967 struct drm_device *dev = crtc->base.dev;
7968 struct drm_i915_private *dev_priv = dev->dev_private;
7969 uint32_t tmp;
7970
dc9e7dec
VS		 7971 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7972 return;
7973
2fa2fe9a 7974 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7975 if (!(tmp & PFIT_ENABLE))
7976 return;
2fa2fe9a 7977
06922821 7978 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7979 if (INTEL_INFO(dev)->gen < 4) {
7980 if (crtc->pipe != PIPE_B)
7981 return;
2fa2fe9a
DV		 7982 } else {
7983 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7984 return;
7985 }
7986
06922821 7987 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7988 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7989 if (INTEL_INFO(dev)->gen < 5)
7990 pipe_config->gmch_pfit.lvds_border_bits =
7991 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7992}
7993
acbec814 7994static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7995 struct intel_crtc_state *pipe_config)
acbec814
JB		 7996{
7997 struct drm_device *dev = crtc->base.dev;
7998 struct drm_i915_private *dev_priv = dev->dev_private;
7999 int pipe = pipe_config->cpu_transcoder;
8000 intel_clock_t clock;
8001 u32 mdiv;
662c6ecb 8002 int refclk = 100000;
acbec814 8003
f573de5a
SK		 8004 /* In case of MIPI DPLL will not even be used */
8005 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8006 return;
8007
a580516d 8008 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8009 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8010 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8011
8012 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8013 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8014 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8015 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8016 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8017
f646628b 8018 vlv_clock(refclk, &clock);
acbec814 8019
f646628b
VS		 8020 /* clock.dot is the fast clock */
8021 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8022}
8023
5724dbd1
DL		 8024static void
8025i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8026 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8027{
8028 struct drm_device *dev = crtc->base.dev;
8029 struct drm_i915_private *dev_priv = dev->dev_private;
8030 u32 val, base, offset;
8031 int pipe = crtc->pipe, plane = crtc->plane;
8032 int fourcc, pixel_format;
6761dd31 8033 unsigned int aligned_height;
b113d5ee 8034 struct drm_framebuffer *fb;
1b842c89 8035 struct intel_framebuffer *intel_fb;
1ad292b5 8036
42a7b088
DL		 8037 val = I915_READ(DSPCNTR(plane));
8038 if (!(val & DISPLAY_PLANE_ENABLE))
8039 return;
8040
d9806c9f 8041 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8042 if (!intel_fb) {
1ad292b5
JB		 8043 DRM_DEBUG_KMS("failed to alloc fb\n");
8044 return;
8045 }
8046
1b842c89
DL		 8047 fb = &intel_fb->base;
8048
18c5247e
DV		 8049 if (INTEL_INFO(dev)->gen >= 4) {
8050 if (val & DISPPLANE_TILED) {
49af449b 8051 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8052 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8053 }
8054 }
1ad292b5
JB		 8055
8056 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8057 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8058 fb->pixel_format = fourcc;
8059 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8060
8061 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8062 if (plane_config->tiling)
1ad292b5
JB		 8063 offset = I915_READ(DSPTILEOFF(plane));
8064 else
8065 offset = I915_READ(DSPLINOFF(plane));
8066 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8067 } else {
8068 base = I915_READ(DSPADDR(plane));
8069 }
8070 plane_config->base = base;
8071
8072 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8073 fb->width = ((val >> 16) & 0xfff) + 1;
8074 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8075
8076 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8077 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8078
b113d5ee 8079 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8080 fb->pixel_format,
8081 fb->modifier[0]);
1ad292b5 8082
f37b5c2b 8083 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8084
2844a921
DL		 8085 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8086 pipe_name(pipe), plane, fb->width, fb->height,
8087 fb->bits_per_pixel, base, fb->pitches[0],
8088 plane_config->size);
1ad292b5 8089
2d14030b 8090 plane_config->fb = intel_fb;
1ad292b5
JB		 8091}
8092
70b23a98 8093static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8094 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8095{
8096 struct drm_device *dev = crtc->base.dev;
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 int pipe = pipe_config->cpu_transcoder;
8099 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8100 intel_clock_t clock;
8101 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8102 int refclk = 100000;
8103
a580516d 8104 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8105 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8106 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8107 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8108 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8109 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8110
8111 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8112 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8113 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8114 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8115 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8116
8117 chv_clock(refclk, &clock);
8118
8119 /* clock.dot is the fast clock */
8120 pipe_config->port_clock = clock.dot / 5;
8121}
8122
0e8ffe1b 8123static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8124 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8125{
8126 struct drm_device *dev = crtc->base.dev;
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8128 uint32_t tmp;
8129
f458ebbc
DV		 8130 if (!intel_display_power_is_enabled(dev_priv,
8131 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8132 return false;
8133
e143a21c 8134 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8135 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8136
0e8ffe1b
DV		 8137 tmp = I915_READ(PIPECONF(crtc->pipe));
8138 if (!(tmp & PIPECONF_ENABLE))
8139 return false;
8140
42571aef
VS		 8141 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8142 switch (tmp & PIPECONF_BPC_MASK) {
8143 case PIPECONF_6BPC:
8144 pipe_config->pipe_bpp = 18;
8145 break;
8146 case PIPECONF_8BPC:
8147 pipe_config->pipe_bpp = 24;
8148 break;
8149 case PIPECONF_10BPC:
8150 pipe_config->pipe_bpp = 30;
8151 break;
8152 default:
8153 break;
8154 }
8155 }
8156
b5a9fa09
DV		 8157 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8158 pipe_config->limited_color_range = true;
8159
282740f7
VS		 8160 if (INTEL_INFO(dev)->gen < 4)
8161 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8162
1bd1bd80
DV		 8163 intel_get_pipe_timings(crtc, pipe_config);
8164
2fa2fe9a
DV		 8165 i9xx_get_pfit_config(crtc, pipe_config);
8166
6c49f241
DV		 8167 if (INTEL_INFO(dev)->gen >= 4) {
8168 tmp = I915_READ(DPLL_MD(crtc->pipe));
8169 pipe_config->pixel_multiplier =
8170 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8171 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8172 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8173 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8174 tmp = I915_READ(DPLL(crtc->pipe));
8175 pipe_config->pixel_multiplier =
8176 ((tmp & SDVO_MULTIPLIER_MASK)
8177 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8178 } else {
8179 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8180 * port and will be fixed up in the encoder->get_config
8181 * function. */
8182 pipe_config->pixel_multiplier = 1;
8183 }
8bcc2795
DV		 8184 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8185 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8186 /*
8187 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8188 * on 830. Filter it out here so that we don't
8189 * report errors due to that.
8190 */
8191 if (IS_I830(dev))
8192 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8193
8bcc2795
DV		 8194 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8195 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8196 } else {
8197 /* Mask out read-only status bits. */
8198 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8199 DPLL_PORTC_READY_MASK |
8200 DPLL_PORTB_READY_MASK);
8bcc2795 8201 }
6c49f241 8202
70b23a98
VS		 8203 if (IS_CHERRYVIEW(dev))
8204 chv_crtc_clock_get(crtc, pipe_config);
8205 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8206 vlv_crtc_clock_get(crtc, pipe_config);
8207 else
8208 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8209
0e8ffe1b
DV		 8210 return true;
8211}
8212
dde86e2d 8213static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8214{
8215 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8216 struct intel_encoder *encoder;
74cfd7ac 8217 u32 val, final;
13d83a67 8218 bool has_lvds = false;
199e5d79 8219 bool has_cpu_edp = false;
199e5d79 8220 bool has_panel = false;
99eb6a01
KP		 8221 bool has_ck505 = false;
8222 bool can_ssc = false;
13d83a67
JB		 8223
8224 /* We need to take the global config into account */
b2784e15 8225 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8226 switch (encoder->type) {
8227 case INTEL_OUTPUT_LVDS:
8228 has_panel = true;
8229 has_lvds = true;
8230 break;
8231 case INTEL_OUTPUT_EDP:
8232 has_panel = true;
2de6905f 8233 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8234 has_cpu_edp = true;
8235 break;
6847d71b
PZ		 8236 default:
8237 break;
13d83a67
JB		 8238 }
8239 }
8240
99eb6a01 8241 if (HAS_PCH_IBX(dev)) {
41aa3448 8242 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8243 can_ssc = has_ck505;
8244 } else {
8245 has_ck505 = false;
8246 can_ssc = true;
8247 }
8248
2de6905f
ID		 8249 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8250 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8251
8252 /* Ironlake: try to setup display ref clock before DPLL
8253 * enabling. This is only under driver's control after
8254 * PCH B stepping, previous chipset stepping should be
8255 * ignoring this setting.
8256 */
74cfd7ac
CW		 8257 val = I915_READ(PCH_DREF_CONTROL);
8258
8259 /* As we must carefully and slowly disable/enable each source in turn,
8260 * compute the final state we want first and check if we need to
8261 * make any changes at all.
8262 */
8263 final = val;
8264 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8265 if (has_ck505)
8266 final |= DREF_NONSPREAD_CK505_ENABLE;
8267 else
8268 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8269
8270 final &= ~DREF_SSC_SOURCE_MASK;
8271 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8272 final &= ~DREF_SSC1_ENABLE;
8273
8274 if (has_panel) {
8275 final |= DREF_SSC_SOURCE_ENABLE;
8276
8277 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8278 final |= DREF_SSC1_ENABLE;
8279
8280 if (has_cpu_edp) {
8281 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8282 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8283 else
8284 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8285 } else
8286 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8287 } else {
8288 final |= DREF_SSC_SOURCE_DISABLE;
8289 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8290 }
8291
8292 if (final == val)
8293 return;
8294
13d83a67 8295 /* Always enable nonspread source */
74cfd7ac 8296 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8297
99eb6a01 8298 if (has_ck505)
74cfd7ac 8299 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8300 else
74cfd7ac 8301 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8302
199e5d79 8303 if (has_panel) {
74cfd7ac
CW		 8304 val &= ~DREF_SSC_SOURCE_MASK;
8305 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8306
199e5d79 8307 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8308 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8309 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8310 val |= DREF_SSC1_ENABLE;
e77166b5 8311 } else
74cfd7ac 8312 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8313
8314 /* Get SSC going before enabling the outputs */
74cfd7ac 8315 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8316 POSTING_READ(PCH_DREF_CONTROL);
8317 udelay(200);
8318
74cfd7ac 8319 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8320
8321 /* Enable CPU source on CPU attached eDP */
199e5d79 8322 if (has_cpu_edp) {
99eb6a01 8323 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8324 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8325 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8326 } else
74cfd7ac 8327 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8328 } else
74cfd7ac 8329 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8330
74cfd7ac 8331 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8332 POSTING_READ(PCH_DREF_CONTROL);
8333 udelay(200);
8334 } else {
8335 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8336
74cfd7ac 8337 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8338
8339 /* Turn off CPU output */
74cfd7ac 8340 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8341
74cfd7ac 8342 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8343 POSTING_READ(PCH_DREF_CONTROL);
8344 udelay(200);
8345
8346 /* Turn off the SSC source */
74cfd7ac
CW		 8347 val &= ~DREF_SSC_SOURCE_MASK;
8348 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8349
8350 /* Turn off SSC1 */
74cfd7ac 8351 val &= ~DREF_SSC1_ENABLE;
199e5d79 8352
74cfd7ac 8353 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8354 POSTING_READ(PCH_DREF_CONTROL);
8355 udelay(200);
8356 }
74cfd7ac
CW		 8357
8358 BUG_ON(val != final);
13d83a67
JB		 8359}
8360
f31f2d55 8361static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8362{
f31f2d55 8363 uint32_t tmp;
dde86e2d 8364
0ff066a9
PZ		 8365 tmp = I915_READ(SOUTH_CHICKEN2);
8366 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8367 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8368
0ff066a9
PZ		 8369 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8370 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8371 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8372
0ff066a9
PZ		 8373 tmp = I915_READ(SOUTH_CHICKEN2);
8374 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8375 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8376
0ff066a9
PZ		 8377 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8378 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8379 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8380}
8381
8382/* WaMPhyProgramming:hsw */
8383static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8384{
8385 uint32_t tmp;
dde86e2d
PZ		 8386
8387 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8388 tmp &= ~(0xFF << 24);
8389 tmp |= (0x12 << 24);
8390 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8391
dde86e2d
PZ		 8392 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8393 tmp |= (1 << 11);
8394 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8395
8396 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8397 tmp |= (1 << 11);
8398 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8399
dde86e2d
PZ		 8400 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8401 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8402 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8403
8404 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8405 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8406 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8407
0ff066a9
PZ		 8408 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8409 tmp &= ~(7 << 13);
8410 tmp |= (5 << 13);
8411 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8412
0ff066a9
PZ		 8413 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8414 tmp &= ~(7 << 13);
8415 tmp |= (5 << 13);
8416 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8417
8418 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8419 tmp &= ~0xFF;
8420 tmp |= 0x1C;
8421 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8422
8423 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8424 tmp &= ~0xFF;
8425 tmp |= 0x1C;
8426 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8427
8428 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8429 tmp &= ~(0xFF << 16);
8430 tmp |= (0x1C << 16);
8431 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8432
8433 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8434 tmp &= ~(0xFF << 16);
8435 tmp |= (0x1C << 16);
8436 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8437
0ff066a9
PZ		 8438 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8439 tmp |= (1 << 27);
8440 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8441
0ff066a9
PZ		 8442 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8443 tmp |= (1 << 27);
8444 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8445
0ff066a9
PZ		 8446 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8447 tmp &= ~(0xF << 28);
8448 tmp |= (4 << 28);
8449 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8450
0ff066a9
PZ		 8451 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8452 tmp &= ~(0xF << 28);
8453 tmp |= (4 << 28);
8454 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8455}
8456
2fa86a1f
PZ		 8457/* Implements 3 different sequences from BSpec chapter "Display iCLK
8458 * Programming" based on the parameters passed:
8459 * - Sequence to enable CLKOUT_DP
8460 * - Sequence to enable CLKOUT_DP without spread
8461 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8462 */
8463static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8464 bool with_fdi)
f31f2d55
PZ		 8465{
8466 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8467 uint32_t reg, tmp;
8468
8469 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8470 with_spread = true;
8471 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8472 with_fdi, "LP PCH doesn't have FDI\n"))
8473 with_fdi = false;
f31f2d55 8474
a580516d 8475 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8476
8477 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8478 tmp &= ~SBI_SSCCTL_DISABLE;
8479 tmp |= SBI_SSCCTL_PATHALT;
8480 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8481
8482 udelay(24);
8483
2fa86a1f
PZ		 8484 if (with_spread) {
8485 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8486 tmp &= ~SBI_SSCCTL_PATHALT;
8487 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8488
2fa86a1f
PZ		 8489 if (with_fdi) {
8490 lpt_reset_fdi_mphy(dev_priv);
8491 lpt_program_fdi_mphy(dev_priv);
8492 }
8493 }
dde86e2d 8494
2fa86a1f
PZ		 8495 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8496 SBI_GEN0 : SBI_DBUFF0;
8497 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8498 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8499 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8500
a580516d 8501 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8502}
8503
47701c3b
PZ		 8504/* Sequence to disable CLKOUT_DP */
8505static void lpt_disable_clkout_dp(struct drm_device *dev)
8506{
8507 struct drm_i915_private *dev_priv = dev->dev_private;
8508 uint32_t reg, tmp;
8509
a580516d 8510 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8511
8512 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8513 SBI_GEN0 : SBI_DBUFF0;
8514 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8515 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8516 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8517
8518 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8519 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8520 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8521 tmp |= SBI_SSCCTL_PATHALT;
8522 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8523 udelay(32);
8524 }
8525 tmp |= SBI_SSCCTL_DISABLE;
8526 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8527 }
8528
a580516d 8529 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8530}
8531
bf8fa3d3
PZ		 8532static void lpt_init_pch_refclk(struct drm_device *dev)
8533{
bf8fa3d3
PZ		 8534 struct intel_encoder *encoder;
8535 bool has_vga = false;
8536
b2784e15 8537 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8538 switch (encoder->type) {
8539 case INTEL_OUTPUT_ANALOG:
8540 has_vga = true;
8541 break;
6847d71b
PZ		 8542 default:
8543 break;
bf8fa3d3
PZ		 8544 }
8545 }
8546
47701c3b
PZ		 8547 if (has_vga)
8548 lpt_enable_clkout_dp(dev, true, true);
8549 else
8550 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8551}
8552
dde86e2d
PZ		 8553/*
8554 * Initialize reference clocks when the driver loads
8555 */
8556void intel_init_pch_refclk(struct drm_device *dev)
8557{
8558 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8559 ironlake_init_pch_refclk(dev);
8560 else if (HAS_PCH_LPT(dev))
8561 lpt_init_pch_refclk(dev);
8562}
8563
55bb9992 8564static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8565{
55bb9992 8566 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8567 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8568 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8569 struct drm_connector *connector;
55bb9992 8570 struct drm_connector_state *connector_state;
d9d444cb 8571 struct intel_encoder *encoder;
55bb9992 8572 int num_connectors = 0, i;
d9d444cb
JB		 8573 bool is_lvds = false;
8574
da3ced29 8575 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8576 if (connector_state->crtc != crtc_state->base.crtc)
8577 continue;
8578
8579 encoder = to_intel_encoder(connector_state->best_encoder);
8580
d9d444cb
JB		 8581 switch (encoder->type) {
8582 case INTEL_OUTPUT_LVDS:
8583 is_lvds = true;
8584 break;
6847d71b
PZ		 8585 default:
8586 break;
d9d444cb
JB		 8587 }
8588 num_connectors++;
8589 }
8590
8591 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8592 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8593 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8594 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8595 }
8596
8597 return 120000;
8598}
8599
6ff93609 8600static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8601{
c8203565 8602 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8604 int pipe = intel_crtc->pipe;
c8203565
PZ		 8605 uint32_t val;
8606
78114071 8607 val = 0;
c8203565 8608
6e3c9717 8609 switch (intel_crtc->config->pipe_bpp) {
c8203565 8610 case 18:
dfd07d72 8611 val |= PIPECONF_6BPC;
c8203565
PZ		 8612 break;
8613 case 24:
dfd07d72 8614 val |= PIPECONF_8BPC;
c8203565
PZ		 8615 break;
8616 case 30:
dfd07d72 8617 val |= PIPECONF_10BPC;
c8203565
PZ		 8618 break;
8619 case 36:
dfd07d72 8620 val |= PIPECONF_12BPC;
c8203565
PZ		 8621 break;
8622 default:
cc769b62
PZ		 8623 /* Case prevented by intel_choose_pipe_bpp_dither. */
8624 BUG();
c8203565
PZ		 8625 }
8626
6e3c9717 8627 if (intel_crtc->config->dither)
c8203565
PZ		 8628 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8629
6e3c9717 8630 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8631 val |= PIPECONF_INTERLACED_ILK;
8632 else
8633 val |= PIPECONF_PROGRESSIVE;
8634
6e3c9717 8635 if (intel_crtc->config->limited_color_range)
3685a8f3 8636 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8637
c8203565
PZ		 8638 I915_WRITE(PIPECONF(pipe), val);
8639 POSTING_READ(PIPECONF(pipe));
8640}
8641
86d3efce
VS		 8642/*
8643 * Set up the pipe CSC unit.
8644 *
8645 * Currently only full range RGB to limited range RGB conversion
8646 * is supported, but eventually this should handle various
8647 * RGB<->YCbCr scenarios as well.
8648 */
50f3b016 8649static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8650{
8651 struct drm_device *dev = crtc->dev;
8652 struct drm_i915_private *dev_priv = dev->dev_private;
8653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8654 int pipe = intel_crtc->pipe;
8655 uint16_t coeff = 0x7800; /* 1.0 */
8656
8657 /*
8658 * TODO: Check what kind of values actually come out of the pipe
8659 * with these coeff/postoff values and adjust to get the best
8660 * accuracy. Perhaps we even need to take the bpc value into
8661 * consideration.
8662 */
8663
6e3c9717 8664 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8665 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8666
8667 /*
8668 * GY/GU and RY/RU should be the other way around according
8669 * to BSpec, but reality doesn't agree. Just set them up in
8670 * a way that results in the correct picture.
8671 */
8672 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8673 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8674
8675 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8676 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8677
8678 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8679 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8680
8681 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8682 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8683 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8684
8685 if (INTEL_INFO(dev)->gen > 6) {
8686 uint16_t postoff = 0;
8687
6e3c9717 8688 if (intel_crtc->config->limited_color_range)
32cf0cb0 8689 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8690
8691 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8692 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8693 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8694
8695 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8696 } else {
8697 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8698
6e3c9717 8699 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8700 mode |= CSC_BLACK_SCREEN_OFFSET;
8701
8702 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8703 }
8704}
8705
6ff93609 8706static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8707{
756f85cf
PZ		 8708 struct drm_device *dev = crtc->dev;
8709 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8711 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8712 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8713 uint32_t val;
8714
3eff4faa 8715 val = 0;
ee2b0b38 8716
6e3c9717 8717 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8718 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8719
6e3c9717 8720 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8721 val |= PIPECONF_INTERLACED_ILK;
8722 else
8723 val |= PIPECONF_PROGRESSIVE;
8724
702e7a56
PZ		 8725 I915_WRITE(PIPECONF(cpu_transcoder), val);
8726 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8727
8728 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8729 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8730
3cdf122c 8731 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8732 val = 0;
8733
6e3c9717 8734 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8735 case 18:
8736 val |= PIPEMISC_DITHER_6_BPC;
8737 break;
8738 case 24:
8739 val |= PIPEMISC_DITHER_8_BPC;
8740 break;
8741 case 30:
8742 val |= PIPEMISC_DITHER_10_BPC;
8743 break;
8744 case 36:
8745 val |= PIPEMISC_DITHER_12_BPC;
8746 break;
8747 default:
8748 /* Case prevented by pipe_config_set_bpp. */
8749 BUG();
8750 }
8751
6e3c9717 8752 if (intel_crtc->config->dither)
756f85cf
PZ		 8753 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8754
8755 I915_WRITE(PIPEMISC(pipe), val);
8756 }
ee2b0b38
PZ		 8757}
8758
6591c6e4 8759static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8760 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8761 intel_clock_t *clock,
8762 bool *has_reduced_clock,
8763 intel_clock_t *reduced_clock)
8764{
8765 struct drm_device *dev = crtc->dev;
8766 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8767 int refclk;
d4906093 8768 const intel_limit_t *limit;
a16af721 8769 bool ret, is_lvds = false;
79e53945 8770
a93e255f 8771 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8772
55bb9992 8773 refclk = ironlake_get_refclk(crtc_state);
79e53945 8774
d4906093
ML		 8775 /*
8776 * Returns a set of divisors for the desired target clock with the given
8777 * refclk, or FALSE. The returned values represent the clock equation:
8778 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8779 */
a93e255f
ACO		 8780 limit = intel_limit(crtc_state, refclk);
8781 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8782 crtc_state->port_clock,
ee9300bb 8783 refclk, NULL, clock);
6591c6e4
PZ		 8784 if (!ret)
8785 return false;
cda4b7d3 8786
ddc9003c 8787 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8788 /*
8789 * Ensure we match the reduced clock's P to the target clock.
8790 * If the clocks don't match, we can't switch the display clock
8791 * by using the FP0/FP1. In such case we will disable the LVDS
8792 * downclock feature.
8793 */
ee9300bb 8794 *has_reduced_clock =
a93e255f 8795 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8796 dev_priv->lvds_downclock,
8797 refclk, clock,
8798 reduced_clock);
652c393a 8799 }
61e9653f 8800
6591c6e4
PZ		 8801 return true;
8802}
8803
d4b1931c
PZ		 8804int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8805{
8806 /*
8807 * Account for spread spectrum to avoid
8808 * oversubscribing the link. Max center spread
8809 * is 2.5%; use 5% for safety's sake.
8810 */
8811 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8812 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8813}
8814
7429e9d4 8815static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8816{
7429e9d4 8817 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8818}
8819
de13a2e3 8820static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8821 struct intel_crtc_state *crtc_state,
7429e9d4 8822 u32 *fp,
9a7c7890 8823 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8824{
de13a2e3 8825 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8826 struct drm_device *dev = crtc->dev;
8827 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8828 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8829 struct drm_connector *connector;
55bb9992
ACO		 8830 struct drm_connector_state *connector_state;
8831 struct intel_encoder *encoder;
de13a2e3 8832 uint32_t dpll;
55bb9992 8833 int factor, num_connectors = 0, i;
09ede541 8834 bool is_lvds = false, is_sdvo = false;
79e53945 8835
da3ced29 8836 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8837 if (connector_state->crtc != crtc_state->base.crtc)
8838 continue;
8839
8840 encoder = to_intel_encoder(connector_state->best_encoder);
8841
8842 switch (encoder->type) {
79e53945
JB		 8843 case INTEL_OUTPUT_LVDS:
8844 is_lvds = true;
8845 break;
8846 case INTEL_OUTPUT_SDVO:
7d57382e 8847 case INTEL_OUTPUT_HDMI:
79e53945 8848 is_sdvo = true;
79e53945 8849 break;
6847d71b
PZ		 8850 default:
8851 break;
79e53945 8852 }
43565a06 8853
c751ce4f 8854 num_connectors++;
79e53945 8855 }
79e53945 8856
c1858123 8857 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8858 factor = 21;
8859 if (is_lvds) {
8860 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8861 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8862 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8863 factor = 25;
190f68c5 8864 } else if (crtc_state->sdvo_tv_clock)
8febb297 8865 factor = 20;
c1858123 8866
190f68c5 8867 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8868 *fp |= FP_CB_TUNE;
2c07245f 8869
9a7c7890
DV		 8870 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8871 *fp2 |= FP_CB_TUNE;
8872
5eddb70b 8873 dpll = 0;
2c07245f 8874
a07d6787
EA		 8875 if (is_lvds)
8876 dpll |= DPLLB_MODE_LVDS;
8877 else
8878 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8879
190f68c5 8880 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8881 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8882
8883 if (is_sdvo)
4a33e48d 8884 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8885 if (crtc_state->has_dp_encoder)
4a33e48d 8886 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8887
a07d6787 8888 /* compute bitmask from p1 value */
190f68c5 8889 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8890 /* also FPA1 */
190f68c5 8891 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8892
190f68c5 8893 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8894 case 5:
8895 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8896 break;
8897 case 7:
8898 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8899 break;
8900 case 10:
8901 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8902 break;
8903 case 14:
8904 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8905 break;
79e53945
JB		 8906 }
8907
b4c09f3b 8908 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8909 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8910 else
8911 dpll |= PLL_REF_INPUT_DREFCLK;
8912
959e16d6 8913 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8914}
8915
190f68c5
ACO		 8916static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8917 struct intel_crtc_state *crtc_state)
de13a2e3 8918{
c7653199 8919 struct drm_device *dev = crtc->base.dev;
de13a2e3 8920 intel_clock_t clock, reduced_clock;
cbbab5bd 8921 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8922 bool ok, has_reduced_clock = false;
8b47047b 8923 bool is_lvds = false;
e2b78267 8924 struct intel_shared_dpll *pll;
de13a2e3 8925
dd3cd74a
ACO		 8926 memset(&crtc_state->dpll_hw_state, 0,
8927 sizeof(crtc_state->dpll_hw_state));
8928
409ee761 8929 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8930
5dc5298b
PZ		 8931 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8932 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8933
190f68c5 8934 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8935 &has_reduced_clock, &reduced_clock);
190f68c5 8936 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8937 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8938 return -EINVAL;
79e53945 8939 }
f47709a9 8940 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8941 if (!crtc_state->clock_set) {
8942 crtc_state->dpll.n = clock.n;
8943 crtc_state->dpll.m1 = clock.m1;
8944 crtc_state->dpll.m2 = clock.m2;
8945 crtc_state->dpll.p1 = clock.p1;
8946 crtc_state->dpll.p2 = clock.p2;
f47709a9 8947 }
79e53945 8948
5dc5298b 8949 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8950 if (crtc_state->has_pch_encoder) {
8951 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8952 if (has_reduced_clock)
7429e9d4 8953 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8954
190f68c5 8955 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8956 &fp, &reduced_clock,
8957 has_reduced_clock ? &fp2 : NULL);
8958
190f68c5
ACO		 8959 crtc_state->dpll_hw_state.dpll = dpll;
8960 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8961 if (has_reduced_clock)
190f68c5 8962 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8963 else
190f68c5 8964 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8965
190f68c5 8966 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8967 if (pll == NULL) {
84f44ce7 8968 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8969 pipe_name(crtc->pipe));
4b645f14
JB		 8970 return -EINVAL;
8971 }
3fb37703 8972 }
79e53945 8973
ab585dea 8974 if (is_lvds && has_reduced_clock)
c7653199 8975 crtc->lowfreq_avail = true;
bcd644e0 8976 else
c7653199 8977 crtc->lowfreq_avail = false;
e2b78267 8978
c8f7a0db 8979 return 0;
79e53945
JB		 8980}
8981
eb14cb74
VS		 8982static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8983 struct intel_link_m_n *m_n)
8984{
8985 struct drm_device *dev = crtc->base.dev;
8986 struct drm_i915_private *dev_priv = dev->dev_private;
8987 enum pipe pipe = crtc->pipe;
8988
8989 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8990 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8991 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8992 & ~TU_SIZE_MASK;
8993 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8994 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8995 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8996}
8997
8998static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8999 enum transcoder transcoder,
b95af8be
VK		 9000 struct intel_link_m_n *m_n,
9001 struct intel_link_m_n *m2_n2)
72419203
DV		 9002{
9003 struct drm_device *dev = crtc->base.dev;
9004 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 9005 enum pipe pipe = crtc->pipe;
72419203 9006
eb14cb74
VS		 9007 if (INTEL_INFO(dev)->gen >= 5) {
9008 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9009 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9010 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9011 & ~TU_SIZE_MASK;
9012 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9013 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9014 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9015 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9016 * gen < 8) and if DRRS is supported (to make sure the
9017 * registers are not unnecessarily read).
9018 */
9019 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9020 crtc->config->has_drrs) {
b95af8be
VK		 9021 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9022 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9023 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9024 & ~TU_SIZE_MASK;
9025 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9026 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9027 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9028 }
eb14cb74
VS		 9029 } else {
9030 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9031 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9032 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9033 & ~TU_SIZE_MASK;
9034 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9035 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9036 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9037 }
9038}
9039
9040void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9041 struct intel_crtc_state *pipe_config)
eb14cb74 9042{
681a8504 9043 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9044 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9045 else
9046 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9047 &pipe_config->dp_m_n,
9048 &pipe_config->dp_m2_n2);
eb14cb74 9049}
72419203 9050
eb14cb74 9051static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9052 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9053{
9054 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9055 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9056}
9057
bd2e244f 9058static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9059 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9060{
9061 struct drm_device *dev = crtc->base.dev;
9062 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9063 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9064 uint32_t ps_ctrl = 0;
9065 int id = -1;
9066 int i;
bd2e244f 9067
a1b2278e
CK		 9068 /* find scaler attached to this pipe */
9069 for (i = 0; i < crtc->num_scalers; i++) {
9070 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9071 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9072 id = i;
9073 pipe_config->pch_pfit.enabled = true;
9074 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9075 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9076 break;
9077 }
9078 }
bd2e244f 9079
a1b2278e
CK		 9080 scaler_state->scaler_id = id;
9081 if (id >= 0) {
9082 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9083 } else {
9084 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9085 }
9086}
9087
5724dbd1
DL		 9088static void
9089skylake_get_initial_plane_config(struct intel_crtc *crtc,
9090 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9091{
9092 struct drm_device *dev = crtc->base.dev;
9093 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9094 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9095 int pipe = crtc->pipe;
9096 int fourcc, pixel_format;
6761dd31 9097 unsigned int aligned_height;
bc8d7dff 9098 struct drm_framebuffer *fb;
1b842c89 9099 struct intel_framebuffer *intel_fb;
bc8d7dff 9100
d9806c9f 9101 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9102 if (!intel_fb) {
bc8d7dff
DL		 9103 DRM_DEBUG_KMS("failed to alloc fb\n");
9104 return;
9105 }
9106
1b842c89
DL		 9107 fb = &intel_fb->base;
9108
bc8d7dff 9109 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9110 if (!(val & PLANE_CTL_ENABLE))
9111 goto error;
9112
bc8d7dff
DL		 9113 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9114 fourcc = skl_format_to_fourcc(pixel_format,
9115 val & PLANE_CTL_ORDER_RGBX,
9116 val & PLANE_CTL_ALPHA_MASK);
9117 fb->pixel_format = fourcc;
9118 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9119
40f46283
DL		 9120 tiling = val & PLANE_CTL_TILED_MASK;
9121 switch (tiling) {
9122 case PLANE_CTL_TILED_LINEAR:
9123 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9124 break;
9125 case PLANE_CTL_TILED_X:
9126 plane_config->tiling = I915_TILING_X;
9127 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9128 break;
9129 case PLANE_CTL_TILED_Y:
9130 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9131 break;
9132 case PLANE_CTL_TILED_YF:
9133 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9134 break;
9135 default:
9136 MISSING_CASE(tiling);
9137 goto error;
9138 }
9139
bc8d7dff
DL		 9140 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9141 plane_config->base = base;
9142
9143 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9144
9145 val = I915_READ(PLANE_SIZE(pipe, 0));
9146 fb->height = ((val >> 16) & 0xfff) + 1;
9147 fb->width = ((val >> 0) & 0x1fff) + 1;
9148
9149 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9150 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9151 fb->pixel_format);
bc8d7dff
DL		 9152 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9153
9154 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9155 fb->pixel_format,
9156 fb->modifier[0]);
bc8d7dff 9157
f37b5c2b 9158 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9159
9160 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9161 pipe_name(pipe), fb->width, fb->height,
9162 fb->bits_per_pixel, base, fb->pitches[0],
9163 plane_config->size);
9164
2d14030b 9165 plane_config->fb = intel_fb;
bc8d7dff
DL		 9166 return;
9167
9168error:
9169 kfree(fb);
9170}
9171
2fa2fe9a 9172static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9173 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9174{
9175 struct drm_device *dev = crtc->base.dev;
9176 struct drm_i915_private *dev_priv = dev->dev_private;
9177 uint32_t tmp;
9178
9179 tmp = I915_READ(PF_CTL(crtc->pipe));
9180
9181 if (tmp & PF_ENABLE) {
fd4daa9c 9182 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9183 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9184 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9185
9186 /* We currently do not free assignements of panel fitters on
9187 * ivb/hsw (since we don't use the higher upscaling modes which
9188 * differentiates them) so just WARN about this case for now. */
9189 if (IS_GEN7(dev)) {
9190 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9191 PF_PIPE_SEL_IVB(crtc->pipe));
9192 }
2fa2fe9a 9193 }
79e53945
JB		 9194}
9195
5724dbd1
DL		 9196static void
9197ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9198 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9199{
9200 struct drm_device *dev = crtc->base.dev;
9201 struct drm_i915_private *dev_priv = dev->dev_private;
9202 u32 val, base, offset;
aeee5a49 9203 int pipe = crtc->pipe;
4c6baa59 9204 int fourcc, pixel_format;
6761dd31 9205 unsigned int aligned_height;
b113d5ee 9206 struct drm_framebuffer *fb;
1b842c89 9207 struct intel_framebuffer *intel_fb;
4c6baa59 9208
42a7b088
DL		 9209 val = I915_READ(DSPCNTR(pipe));
9210 if (!(val & DISPLAY_PLANE_ENABLE))
9211 return;
9212
d9806c9f 9213 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9214 if (!intel_fb) {
4c6baa59
JB		 9215 DRM_DEBUG_KMS("failed to alloc fb\n");
9216 return;
9217 }
9218
1b842c89
DL		 9219 fb = &intel_fb->base;
9220
18c5247e
DV		 9221 if (INTEL_INFO(dev)->gen >= 4) {
9222 if (val & DISPPLANE_TILED) {
49af449b 9223 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9224 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9225 }
9226 }
4c6baa59
JB		 9227
9228 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9229 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9230 fb->pixel_format = fourcc;
9231 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9232
aeee5a49 9233 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9234 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9235 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9236 } else {
49af449b 9237 if (plane_config->tiling)
aeee5a49 9238 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9239 else
aeee5a49 9240 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9241 }
9242 plane_config->base = base;
9243
9244 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9245 fb->width = ((val >> 16) & 0xfff) + 1;
9246 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9247
9248 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9249 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9250
b113d5ee 9251 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9252 fb->pixel_format,
9253 fb->modifier[0]);
4c6baa59 9254
f37b5c2b 9255 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9256
2844a921
DL		 9257 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9258 pipe_name(pipe), fb->width, fb->height,
9259 fb->bits_per_pixel, base, fb->pitches[0],
9260 plane_config->size);
b113d5ee 9261
2d14030b 9262 plane_config->fb = intel_fb;
4c6baa59
JB		 9263}
9264
0e8ffe1b 9265static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9266 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9267{
9268 struct drm_device *dev = crtc->base.dev;
9269 struct drm_i915_private *dev_priv = dev->dev_private;
9270 uint32_t tmp;
9271
f458ebbc
DV		 9272 if (!intel_display_power_is_enabled(dev_priv,
9273 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9274 return false;
9275
e143a21c 9276 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9277 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9278
0e8ffe1b
DV		 9279 tmp = I915_READ(PIPECONF(crtc->pipe));
9280 if (!(tmp & PIPECONF_ENABLE))
9281 return false;
9282
42571aef
VS		 9283 switch (tmp & PIPECONF_BPC_MASK) {
9284 case PIPECONF_6BPC:
9285 pipe_config->pipe_bpp = 18;
9286 break;
9287 case PIPECONF_8BPC:
9288 pipe_config->pipe_bpp = 24;
9289 break;
9290 case PIPECONF_10BPC:
9291 pipe_config->pipe_bpp = 30;
9292 break;
9293 case PIPECONF_12BPC:
9294 pipe_config->pipe_bpp = 36;
9295 break;
9296 default:
9297 break;
9298 }
9299
b5a9fa09
DV		 9300 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9301 pipe_config->limited_color_range = true;
9302
ab9412ba 9303 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9304 struct intel_shared_dpll *pll;
9305
88adfff1
DV		 9306 pipe_config->has_pch_encoder = true;
9307
627eb5a3
DV		 9308 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9309 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9310 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9311
9312 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9313
c0d43d62 9314 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9315 pipe_config->shared_dpll =
9316 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9317 } else {
9318 tmp = I915_READ(PCH_DPLL_SEL);
9319 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9320 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9321 else
9322 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9323 }
66e985c0
DV		 9324
9325 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9326
9327 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9328 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9329
9330 tmp = pipe_config->dpll_hw_state.dpll;
9331 pipe_config->pixel_multiplier =
9332 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9333 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9334
9335 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9336 } else {
9337 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9338 }
9339
1bd1bd80
DV		 9340 intel_get_pipe_timings(crtc, pipe_config);
9341
2fa2fe9a
DV		 9342 ironlake_get_pfit_config(crtc, pipe_config);
9343
0e8ffe1b
DV		 9344 return true;
9345}
9346
be256dc7
PZ		 9347static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9348{
9349 struct drm_device *dev = dev_priv->dev;
be256dc7 9350 struct intel_crtc *crtc;
be256dc7 9351
d3fcc808 9352 for_each_intel_crtc(dev, crtc)
e2c719b7 9353 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9354 pipe_name(crtc->pipe));
9355
e2c719b7
RC		 9356 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9357 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9358 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9359 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9360 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9361 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9362 "CPU PWM1 enabled\n");
c5107b87 9363 if (IS_HASWELL(dev))
e2c719b7 9364 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9365 "CPU PWM2 enabled\n");
e2c719b7 9366 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9367 "PCH PWM1 enabled\n");
e2c719b7 9368 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9369 "Utility pin enabled\n");
e2c719b7 9370 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9371
9926ada1
PZ		 9372 /*
9373 * In theory we can still leave IRQs enabled, as long as only the HPD
9374 * interrupts remain enabled. We used to check for that, but since it's
9375 * gen-specific and since we only disable LCPLL after we fully disable
9376 * the interrupts, the check below should be enough.
9377 */
e2c719b7 9378 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9379}
9380
9ccd5aeb
PZ		 9381static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9382{
9383 struct drm_device *dev = dev_priv->dev;
9384
9385 if (IS_HASWELL(dev))
9386 return I915_READ(D_COMP_HSW);
9387 else
9388 return I915_READ(D_COMP_BDW);
9389}
9390
3c4c9b81
PZ		 9391static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9392{
9393 struct drm_device *dev = dev_priv->dev;
9394
9395 if (IS_HASWELL(dev)) {
9396 mutex_lock(&dev_priv->rps.hw_lock);
9397 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9398 val))
f475dadf 9399 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9400 mutex_unlock(&dev_priv->rps.hw_lock);
9401 } else {
9ccd5aeb
PZ		 9402 I915_WRITE(D_COMP_BDW, val);
9403 POSTING_READ(D_COMP_BDW);
3c4c9b81 9404 }
be256dc7
PZ		 9405}
9406
9407/*
9408 * This function implements pieces of two sequences from BSpec:
9409 * - Sequence for display software to disable LCPLL
9410 * - Sequence for display software to allow package C8+
9411 * The steps implemented here are just the steps that actually touch the LCPLL
9412 * register. Callers should take care of disabling all the display engine
9413 * functions, doing the mode unset, fixing interrupts, etc.
9414 */
6ff58d53
PZ		 9415static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9416 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9417{
9418 uint32_t val;
9419
9420 assert_can_disable_lcpll(dev_priv);
9421
9422 val = I915_READ(LCPLL_CTL);
9423
9424 if (switch_to_fclk) {
9425 val |= LCPLL_CD_SOURCE_FCLK;
9426 I915_WRITE(LCPLL_CTL, val);
9427
9428 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9429 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9430 DRM_ERROR("Switching to FCLK failed\n");
9431
9432 val = I915_READ(LCPLL_CTL);
9433 }
9434
9435 val |= LCPLL_PLL_DISABLE;
9436 I915_WRITE(LCPLL_CTL, val);
9437 POSTING_READ(LCPLL_CTL);
9438
9439 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9440 DRM_ERROR("LCPLL still locked\n");
9441
9ccd5aeb 9442 val = hsw_read_dcomp(dev_priv);
be256dc7 9443 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9444 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9445 ndelay(100);
9446
9ccd5aeb
PZ		 9447 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9448 1))
be256dc7
PZ		 9449 DRM_ERROR("D_COMP RCOMP still in progress\n");
9450
9451 if (allow_power_down) {
9452 val = I915_READ(LCPLL_CTL);
9453 val |= LCPLL_POWER_DOWN_ALLOW;
9454 I915_WRITE(LCPLL_CTL, val);
9455 POSTING_READ(LCPLL_CTL);
9456 }
9457}
9458
9459/*
9460 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9461 * source.
9462 */
6ff58d53 9463static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9464{
9465 uint32_t val;
9466
9467 val = I915_READ(LCPLL_CTL);
9468
9469 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9470 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9471 return;
9472
a8a8bd54
PZ		 9473 /*
9474 * Make sure we're not on PC8 state before disabling PC8, otherwise
9475 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9476 */
59bad947 9477 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9478
be256dc7
PZ		 9479 if (val & LCPLL_POWER_DOWN_ALLOW) {
9480 val &= ~LCPLL_POWER_DOWN_ALLOW;
9481 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9482 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9483 }
9484
9ccd5aeb 9485 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9486 val |= D_COMP_COMP_FORCE;
9487 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9488 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9489
9490 val = I915_READ(LCPLL_CTL);
9491 val &= ~LCPLL_PLL_DISABLE;
9492 I915_WRITE(LCPLL_CTL, val);
9493
9494 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9495 DRM_ERROR("LCPLL not locked yet\n");
9496
9497 if (val & LCPLL_CD_SOURCE_FCLK) {
9498 val = I915_READ(LCPLL_CTL);
9499 val &= ~LCPLL_CD_SOURCE_FCLK;
9500 I915_WRITE(LCPLL_CTL, val);
9501
9502 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9503 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9504 DRM_ERROR("Switching back to LCPLL failed\n");
9505 }
215733fa 9506
59bad947 9507 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9508 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9509}
9510
765dab67
PZ		 9511/*
9512 * Package states C8 and deeper are really deep PC states that can only be
9513 * reached when all the devices on the system allow it, so even if the graphics
9514 * device allows PC8+, it doesn't mean the system will actually get to these
9515 * states. Our driver only allows PC8+ when going into runtime PM.
9516 *
9517 * The requirements for PC8+ are that all the outputs are disabled, the power
9518 * well is disabled and most interrupts are disabled, and these are also
9519 * requirements for runtime PM. When these conditions are met, we manually do
9520 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9521 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9522 * hang the machine.
9523 *
9524 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9525 * the state of some registers, so when we come back from PC8+ we need to
9526 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9527 * need to take care of the registers kept by RC6. Notice that this happens even
9528 * if we don't put the device in PCI D3 state (which is what currently happens
9529 * because of the runtime PM support).
9530 *
9531 * For more, read "Display Sequences for Package C8" on the hardware
9532 * documentation.
9533 */
a14cb6fc 9534void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9535{
c67a470b
PZ		 9536 struct drm_device *dev = dev_priv->dev;
9537 uint32_t val;
9538
c67a470b
PZ		 9539 DRM_DEBUG_KMS("Enabling package C8+\n");
9540
c67a470b
PZ		 9541 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9542 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9543 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9544 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9545 }
9546
9547 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9548 hsw_disable_lcpll(dev_priv, true, true);
9549}
9550
a14cb6fc 9551void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9552{
9553 struct drm_device *dev = dev_priv->dev;
9554 uint32_t val;
9555
c67a470b
PZ		 9556 DRM_DEBUG_KMS("Disabling package C8+\n");
9557
9558 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9559 lpt_init_pch_refclk(dev);
9560
9561 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9562 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9563 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9564 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9565 }
9566
9567 intel_prepare_ddi(dev);
c67a470b
PZ		 9568}
9569
a821fc46 9570static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9571{
a821fc46 9572 struct drm_device *dev = old_state->dev;
f8437dd1 9573 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9574 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9575 int req_cdclk;
9576
9577 /* see the comment in valleyview_modeset_global_resources */
9578 if (WARN_ON(max_pixclk < 0))
9579 return;
9580
9581 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9582
9583 if (req_cdclk != dev_priv->cdclk_freq)
9584 broxton_set_cdclk(dev, req_cdclk);
9585}
9586
b432e5cf
VS		 9587/* compute the max rate for new configuration */
9588static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9589{
9590 struct drm_device *dev = dev_priv->dev;
9591 struct intel_crtc *intel_crtc;
9592 struct drm_crtc *crtc;
9593 int max_pixel_rate = 0;
9594 int pixel_rate;
9595
9596 for_each_crtc(dev, crtc) {
9597 if (!crtc->state->enable)
9598 continue;
9599
9600 intel_crtc = to_intel_crtc(crtc);
9601 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9602
9603 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9604 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9605 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9606
9607 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9608 }
9609
9610 return max_pixel_rate;
9611}
9612
9613static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9614{
9615 struct drm_i915_private *dev_priv = dev->dev_private;
9616 uint32_t val, data;
9617 int ret;
9618
9619 if (WARN((I915_READ(LCPLL_CTL) &
9620 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9621 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9622 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9623 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9624 "trying to change cdclk frequency with cdclk not enabled\n"))
9625 return;
9626
9627 mutex_lock(&dev_priv->rps.hw_lock);
9628 ret = sandybridge_pcode_write(dev_priv,
9629 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9630 mutex_unlock(&dev_priv->rps.hw_lock);
9631 if (ret) {
9632 DRM_ERROR("failed to inform pcode about cdclk change\n");
9633 return;
9634 }
9635
9636 val = I915_READ(LCPLL_CTL);
9637 val |= LCPLL_CD_SOURCE_FCLK;
9638 I915_WRITE(LCPLL_CTL, val);
9639
9640 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9641 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9642 DRM_ERROR("Switching to FCLK failed\n");
9643
9644 val = I915_READ(LCPLL_CTL);
9645 val &= ~LCPLL_CLK_FREQ_MASK;
9646
9647 switch (cdclk) {
9648 case 450000:
9649 val |= LCPLL_CLK_FREQ_450;
9650 data = 0;
9651 break;
9652 case 540000:
9653 val |= LCPLL_CLK_FREQ_54O_BDW;
9654 data = 1;
9655 break;
9656 case 337500:
9657 val |= LCPLL_CLK_FREQ_337_5_BDW;
9658 data = 2;
9659 break;
9660 case 675000:
9661 val |= LCPLL_CLK_FREQ_675_BDW;
9662 data = 3;
9663 break;
9664 default:
9665 WARN(1, "invalid cdclk frequency\n");
9666 return;
9667 }
9668
9669 I915_WRITE(LCPLL_CTL, val);
9670
9671 val = I915_READ(LCPLL_CTL);
9672 val &= ~LCPLL_CD_SOURCE_FCLK;
9673 I915_WRITE(LCPLL_CTL, val);
9674
9675 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9676 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9677 DRM_ERROR("Switching back to LCPLL failed\n");
9678
9679 mutex_lock(&dev_priv->rps.hw_lock);
9680 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9681 mutex_unlock(&dev_priv->rps.hw_lock);
9682
9683 intel_update_cdclk(dev);
9684
9685 WARN(cdclk != dev_priv->cdclk_freq,
9686 "cdclk requested %d kHz but got %d kHz\n",
9687 cdclk, dev_priv->cdclk_freq);
9688}
9689
9690static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9691 int max_pixel_rate)
9692{
9693 int cdclk;
9694
9695 /*
9696 * FIXME should also account for plane ratio
9697 * once 64bpp pixel formats are supported.
9698 */
9699 if (max_pixel_rate > 540000)
9700 cdclk = 675000;
9701 else if (max_pixel_rate > 450000)
9702 cdclk = 540000;
9703 else if (max_pixel_rate > 337500)
9704 cdclk = 450000;
9705 else
9706 cdclk = 337500;
9707
9708 /*
9709 * FIXME move the cdclk caclulation to
9710 * compute_config() so we can fail gracegully.
9711 */
9712 if (cdclk > dev_priv->max_cdclk_freq) {
9713 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9714 cdclk, dev_priv->max_cdclk_freq);
9715 cdclk = dev_priv->max_cdclk_freq;
9716 }
9717
9718 return cdclk;
9719}
9720
9721static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9722{
9723 struct drm_i915_private *dev_priv = to_i915(state->dev);
9724 struct drm_crtc *crtc;
9725 struct drm_crtc_state *crtc_state;
9726 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9727 int cdclk, i;
9728
9729 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9730
9731 if (cdclk == dev_priv->cdclk_freq)
9732 return 0;
9733
9734 /* add all active pipes to the state */
9735 for_each_crtc(state->dev, crtc) {
9736 if (!crtc->state->enable)
9737 continue;
9738
9739 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9740 if (IS_ERR(crtc_state))
9741 return PTR_ERR(crtc_state);
9742 }
9743
9744 /* disable/enable all currently active pipes while we change cdclk */
9745 for_each_crtc_in_state(state, crtc, crtc_state, i)
9746 if (crtc_state->enable)
9747 crtc_state->mode_changed = true;
9748
9749 return 0;
9750}
9751
9752static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9753{
9754 struct drm_device *dev = state->dev;
9755 struct drm_i915_private *dev_priv = dev->dev_private;
9756 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9757 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9758
9759 if (req_cdclk != dev_priv->cdclk_freq)
9760 broadwell_set_cdclk(dev, req_cdclk);
9761}
9762
190f68c5
ACO		 9763static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9764 struct intel_crtc_state *crtc_state)
09b4ddf9 9765{
190f68c5 9766 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9767 return -EINVAL;
716c2e55 9768
c7653199 9769 crtc->lowfreq_avail = false;
644cef34 9770
c8f7a0db 9771 return 0;
79e53945
JB		 9772}
9773
3760b59c
S		 9774static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9775 enum port port,
9776 struct intel_crtc_state *pipe_config)
9777{
9778 switch (port) {
9779 case PORT_A:
9780 pipe_config->ddi_pll_sel = SKL_DPLL0;
9781 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9782 break;
9783 case PORT_B:
9784 pipe_config->ddi_pll_sel = SKL_DPLL1;
9785 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9786 break;
9787 case PORT_C:
9788 pipe_config->ddi_pll_sel = SKL_DPLL2;
9789 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9790 break;
9791 default:
9792 DRM_ERROR("Incorrect port type\n");
9793 }
9794}
9795
96b7dfb7
S		 9796static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9797 enum port port,
5cec258b 9798 struct intel_crtc_state *pipe_config)
96b7dfb7 9799{
3148ade7 9800 u32 temp, dpll_ctl1;
96b7dfb7
S		 9801
9802 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9803 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9804
9805 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9806 case SKL_DPLL0:
9807 /*
9808 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9809 * of the shared DPLL framework and thus needs to be read out
9810 * separately
9811 */
9812 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9813 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9814 break;
96b7dfb7
S		 9815 case SKL_DPLL1:
9816 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9817 break;
9818 case SKL_DPLL2:
9819 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9820 break;
9821 case SKL_DPLL3:
9822 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9823 break;
96b7dfb7
S		 9824 }
9825}
9826
7d2c8175
DL		 9827static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9828 enum port port,
5cec258b 9829 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9830{
9831 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9832
9833 switch (pipe_config->ddi_pll_sel) {
9834 case PORT_CLK_SEL_WRPLL1:
9835 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9836 break;
9837 case PORT_CLK_SEL_WRPLL2:
9838 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9839 break;
9840 }
9841}
9842
26804afd 9843static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9844 struct intel_crtc_state *pipe_config)
26804afd
DV		 9845{
9846 struct drm_device *dev = crtc->base.dev;
9847 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9848 struct intel_shared_dpll *pll;
26804afd
DV		 9849 enum port port;
9850 uint32_t tmp;
9851
9852 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9853
9854 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9855
96b7dfb7
S		 9856 if (IS_SKYLAKE(dev))
9857 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9858 else if (IS_BROXTON(dev))
9859 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9860 else
9861 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9862
d452c5b6
DV		 9863 if (pipe_config->shared_dpll >= 0) {
9864 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9865
9866 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9867 &pipe_config->dpll_hw_state));
9868 }
9869
26804afd
DV		 9870 /*
9871 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9872 * DDI E. So just check whether this pipe is wired to DDI E and whether
9873 * the PCH transcoder is on.
9874 */
ca370455
DL		 9875 if (INTEL_INFO(dev)->gen < 9 &&
9876 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9877 pipe_config->has_pch_encoder = true;
9878
9879 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9880 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9881 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9882
9883 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9884 }
9885}
9886
0e8ffe1b 9887static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9888 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9889{
9890 struct drm_device *dev = crtc->base.dev;
9891 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9892 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9893 uint32_t tmp;
9894
f458ebbc 9895 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9896 POWER_DOMAIN_PIPE(crtc->pipe)))
9897 return false;
9898
e143a21c 9899 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9900 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9901
eccb140b
DV		 9902 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9903 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9904 enum pipe trans_edp_pipe;
9905 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9906 default:
9907 WARN(1, "unknown pipe linked to edp transcoder\n");
9908 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9909 case TRANS_DDI_EDP_INPUT_A_ON:
9910 trans_edp_pipe = PIPE_A;
9911 break;
9912 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9913 trans_edp_pipe = PIPE_B;
9914 break;
9915 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9916 trans_edp_pipe = PIPE_C;
9917 break;
9918 }
9919
9920 if (trans_edp_pipe == crtc->pipe)
9921 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9922 }
9923
f458ebbc 9924 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9925 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9926 return false;
9927
eccb140b 9928 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9929 if (!(tmp & PIPECONF_ENABLE))
9930 return false;
9931
26804afd 9932 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9933
1bd1bd80
DV		 9934 intel_get_pipe_timings(crtc, pipe_config);
9935
a1b2278e
CK		 9936 if (INTEL_INFO(dev)->gen >= 9) {
9937 skl_init_scalers(dev, crtc, pipe_config);
9938 }
9939
2fa2fe9a 9940 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9941
9942 if (INTEL_INFO(dev)->gen >= 9) {
9943 pipe_config->scaler_state.scaler_id = -1;
9944 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9945 }
9946
bd2e244f 9947 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9948 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9949 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9950 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9951 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9952 else
9953 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9954 }
88adfff1 9955
e59150dc
JB		 9956 if (IS_HASWELL(dev))
9957 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9958 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9959
ebb69c95
CT		 9960 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9961 pipe_config->pixel_multiplier =
9962 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9963 } else {
9964 pipe_config->pixel_multiplier = 1;
9965 }
6c49f241 9966
0e8ffe1b
DV		 9967 return true;
9968}
9969
560b85bb
CW		 9970static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9971{
9972 struct drm_device *dev = crtc->dev;
9973 struct drm_i915_private *dev_priv = dev->dev_private;
9974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9975 uint32_t cntl = 0, size = 0;
560b85bb 9976
dc41c154 9977 if (base) {
3dd512fb
MR		 9978 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9979 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9980 unsigned int stride = roundup_pow_of_two(width) * 4;
9981
9982 switch (stride) {
9983 default:
9984 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9985 width, stride);
9986 stride = 256;
9987 /* fallthrough */
9988 case 256:
9989 case 512:
9990 case 1024:
9991 case 2048:
9992 break;
4b0e333e
CW		 9993 }
9994
dc41c154
VS		 9995 cntl |= CURSOR_ENABLE |
9996 CURSOR_GAMMA_ENABLE |
9997 CURSOR_FORMAT_ARGB |
9998 CURSOR_STRIDE(stride);
9999
10000 size = (height << 12) | width;
4b0e333e 10001 }
560b85bb 10002
dc41c154
VS		 10003 if (intel_crtc->cursor_cntl != 0 &&
10004 (intel_crtc->cursor_base != base ||
10005 intel_crtc->cursor_size != size ||
10006 intel_crtc->cursor_cntl != cntl)) {
10007 /* On these chipsets we can only modify the base/size/stride
10008 * whilst the cursor is disabled.
10009 */
10010 I915_WRITE(_CURACNTR, 0);
4b0e333e 10011 POSTING_READ(_CURACNTR);
dc41c154 10012 intel_crtc->cursor_cntl = 0;
4b0e333e 10013 }
560b85bb 10014
99d1f387 10015 if (intel_crtc->cursor_base != base) {
9db4a9c7 10016 I915_WRITE(_CURABASE, base);
99d1f387
VS		 10017 intel_crtc->cursor_base = base;
10018 }
4726e0b0 10019
dc41c154
VS		 10020 if (intel_crtc->cursor_size != size) {
10021 I915_WRITE(CURSIZE, size);
10022 intel_crtc->cursor_size = size;
4b0e333e 10023 }
560b85bb 10024
4b0e333e 10025 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 10026 I915_WRITE(_CURACNTR, cntl);
10027 POSTING_READ(_CURACNTR);
4b0e333e 10028 intel_crtc->cursor_cntl = cntl;
560b85bb 10029 }
560b85bb
CW		 10030}
10031
560b85bb 10032static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 10033{
10034 struct drm_device *dev = crtc->dev;
10035 struct drm_i915_private *dev_priv = dev->dev_private;
10036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10037 int pipe = intel_crtc->pipe;
4b0e333e
CW		 10038 uint32_t cntl;
10039
10040 cntl = 0;
10041 if (base) {
10042 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10043 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10044 case 64:
10045 cntl |= CURSOR_MODE_64_ARGB_AX;
10046 break;
10047 case 128:
10048 cntl |= CURSOR_MODE_128_ARGB_AX;
10049 break;
10050 case 256:
10051 cntl |= CURSOR_MODE_256_ARGB_AX;
10052 break;
10053 default:
3dd512fb 10054 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10055 return;
65a21cd6 10056 }
4b0e333e 10057 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10058
10059 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10060 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10061 }
65a21cd6 10062
8e7d688b 10063 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10064 cntl |= CURSOR_ROTATE_180;
10065
4b0e333e
CW		 10066 if (intel_crtc->cursor_cntl != cntl) {
10067 I915_WRITE(CURCNTR(pipe), cntl);
10068 POSTING_READ(CURCNTR(pipe));
10069 intel_crtc->cursor_cntl = cntl;
65a21cd6 10070 }
4b0e333e 10071
65a21cd6 10072 /* and commit changes on next vblank */
5efb3e28
VS		 10073 I915_WRITE(CURBASE(pipe), base);
10074 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10075
10076 intel_crtc->cursor_base = base;
65a21cd6
JB		 10077}
10078
cda4b7d3 10079/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10080static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10081 bool on)
cda4b7d3
CW		 10082{
10083 struct drm_device *dev = crtc->dev;
10084 struct drm_i915_private *dev_priv = dev->dev_private;
10085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10086 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10087 int x = crtc->cursor_x;
10088 int y = crtc->cursor_y;
d6e4db15 10089 u32 base = 0, pos = 0;
cda4b7d3 10090
d6e4db15 10091 if (on)
cda4b7d3 10092 base = intel_crtc->cursor_addr;
cda4b7d3 10093
6e3c9717 10094 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10095 base = 0;
10096
6e3c9717 10097 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10098 base = 0;
10099
10100 if (x < 0) {
3dd512fb 10101 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10102 base = 0;
10103
10104 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10105 x = -x;
10106 }
10107 pos |= x << CURSOR_X_SHIFT;
10108
10109 if (y < 0) {
3dd512fb 10110 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10111 base = 0;
10112
10113 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10114 y = -y;
10115 }
10116 pos |= y << CURSOR_Y_SHIFT;
10117
4b0e333e 10118 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10119 return;
10120
5efb3e28
VS		 10121 I915_WRITE(CURPOS(pipe), pos);
10122
4398ad45
VS		 10123 /* ILK+ do this automagically */
10124 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10125 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10126 base += (intel_crtc->base.cursor->state->crtc_h *
10127 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10128 }
10129
8ac54669 10130 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10131 i845_update_cursor(crtc, base);
10132 else
10133 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10134}
10135
dc41c154
VS		 10136static bool cursor_size_ok(struct drm_device *dev,
10137 uint32_t width, uint32_t height)
10138{
10139 if (width == 0 || height == 0)
10140 return false;
10141
10142 /*
10143 * 845g/865g are special in that they are only limited by
10144 * the width of their cursors, the height is arbitrary up to
10145 * the precision of the register. Everything else requires
10146 * square cursors, limited to a few power-of-two sizes.
10147 */
10148 if (IS_845G(dev) || IS_I865G(dev)) {
10149 if ((width & 63) != 0)
10150 return false;
10151
10152 if (width > (IS_845G(dev) ? 64 : 512))
10153 return false;
10154
10155 if (height > 1023)
10156 return false;
10157 } else {
10158 switch (width | height) {
10159 case 256:
10160 case 128:
10161 if (IS_GEN2(dev))
10162 return false;
10163 case 64:
10164 break;
10165 default:
10166 return false;
10167 }
10168 }
10169
10170 return true;
10171}
10172
79e53945 10173static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10174 u16 *blue, uint32_t start, uint32_t size)
79e53945 10175{
7203425a 10176 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10178
7203425a 10179 for (i = start; i < end; i++) {
79e53945
JB		 10180 intel_crtc->lut_r[i] = red[i] >> 8;
10181 intel_crtc->lut_g[i] = green[i] >> 8;
10182 intel_crtc->lut_b[i] = blue[i] >> 8;
10183 }
10184
10185 intel_crtc_load_lut(crtc);
10186}
10187
79e53945
JB		 10188/* VESA 640x480x72Hz mode to set on the pipe */
10189static struct drm_display_mode load_detect_mode = {
10190 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10191 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10192};
10193
a8bb6818
DV		 10194struct drm_framebuffer *
10195__intel_framebuffer_create(struct drm_device *dev,
10196 struct drm_mode_fb_cmd2 *mode_cmd,
10197 struct drm_i915_gem_object *obj)
d2dff872
CW		 10198{
10199 struct intel_framebuffer *intel_fb;
10200 int ret;
10201
10202 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10203 if (!intel_fb) {
6ccb81f2 10204 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10205 return ERR_PTR(-ENOMEM);
10206 }
10207
10208 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10209 if (ret)
10210 goto err;
d2dff872
CW		 10211
10212 return &intel_fb->base;
dd4916c5 10213err:
6ccb81f2 10214 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10215 kfree(intel_fb);
10216
10217 return ERR_PTR(ret);
d2dff872
CW		 10218}
10219
b5ea642a 10220static struct drm_framebuffer *
a8bb6818
DV		 10221intel_framebuffer_create(struct drm_device *dev,
10222 struct drm_mode_fb_cmd2 *mode_cmd,
10223 struct drm_i915_gem_object *obj)
10224{
10225 struct drm_framebuffer *fb;
10226 int ret;
10227
10228 ret = i915_mutex_lock_interruptible(dev);
10229 if (ret)
10230 return ERR_PTR(ret);
10231 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10232 mutex_unlock(&dev->struct_mutex);
10233
10234 return fb;
10235}
10236
d2dff872
CW		 10237static u32
10238intel_framebuffer_pitch_for_width(int width, int bpp)
10239{
10240 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10241 return ALIGN(pitch, 64);
10242}
10243
10244static u32
10245intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10246{
10247 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10248 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10249}
10250
10251static struct drm_framebuffer *
10252intel_framebuffer_create_for_mode(struct drm_device *dev,
10253 struct drm_display_mode *mode,
10254 int depth, int bpp)
10255{
10256 struct drm_i915_gem_object *obj;
0fed39bd 10257 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10258
10259 obj = i915_gem_alloc_object(dev,
10260 intel_framebuffer_size_for_mode(mode, bpp));
10261 if (obj == NULL)
10262 return ERR_PTR(-ENOMEM);
10263
10264 mode_cmd.width = mode->hdisplay;
10265 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10266 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10267 bpp);
5ca0c34a 10268 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10269
10270 return intel_framebuffer_create(dev, &mode_cmd, obj);
10271}
10272
10273static struct drm_framebuffer *
10274mode_fits_in_fbdev(struct drm_device *dev,
10275 struct drm_display_mode *mode)
10276{
4520f53a 10277#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10278 struct drm_i915_private *dev_priv = dev->dev_private;
10279 struct drm_i915_gem_object *obj;
10280 struct drm_framebuffer *fb;
10281
4c0e5528 10282 if (!dev_priv->fbdev)
d2dff872
CW		 10283 return NULL;
10284
4c0e5528 10285 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10286 return NULL;
10287
4c0e5528
DV		 10288 obj = dev_priv->fbdev->fb->obj;
10289 BUG_ON(!obj);
10290
8bcd4553 10291 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10292 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10293 fb->bits_per_pixel))
d2dff872
CW		 10294 return NULL;
10295
01f2c773 10296 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10297 return NULL;
10298
10299 return fb;
4520f53a
DV		 10300#else
10301 return NULL;
10302#endif
d2dff872
CW		 10303}
10304
d3a40d1b
ACO		 10305static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10306 struct drm_crtc *crtc,
10307 struct drm_display_mode *mode,
10308 struct drm_framebuffer *fb,
10309 int x, int y)
10310{
10311 struct drm_plane_state *plane_state;
10312 int hdisplay, vdisplay;
10313 int ret;
10314
10315 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10316 if (IS_ERR(plane_state))
10317 return PTR_ERR(plane_state);
10318
10319 if (mode)
10320 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10321 else
10322 hdisplay = vdisplay = 0;
10323
10324 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10325 if (ret)
10326 return ret;
10327 drm_atomic_set_fb_for_plane(plane_state, fb);
10328 plane_state->crtc_x = 0;
10329 plane_state->crtc_y = 0;
10330 plane_state->crtc_w = hdisplay;
10331 plane_state->crtc_h = vdisplay;
10332 plane_state->src_x = x << 16;
10333 plane_state->src_y = y << 16;
10334 plane_state->src_w = hdisplay << 16;
10335 plane_state->src_h = vdisplay << 16;
10336
10337 return 0;
10338}
10339
d2434ab7 10340bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10341 struct drm_display_mode *mode,
51fd371b
RC		 10342 struct intel_load_detect_pipe *old,
10343 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10344{
10345 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10346 struct intel_encoder *intel_encoder =
10347 intel_attached_encoder(connector);
79e53945 10348 struct drm_crtc *possible_crtc;
4ef69c7a 10349 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10350 struct drm_crtc *crtc = NULL;
10351 struct drm_device *dev = encoder->dev;
94352cf9 10352 struct drm_framebuffer *fb;
51fd371b 10353 struct drm_mode_config *config = &dev->mode_config;
83a57153 10354 struct drm_atomic_state *state = NULL;
944b0c76 10355 struct drm_connector_state *connector_state;
4be07317 10356 struct intel_crtc_state *crtc_state;
51fd371b 10357 int ret, i = -1;
79e53945 10358
d2dff872 10359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10360 connector->base.id, connector->name,
8e329a03 10361 encoder->base.id, encoder->name);
d2dff872 10362
51fd371b
RC		 10363retry:
10364 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10365 if (ret)
10366 goto fail_unlock;
6e9f798d 10367
79e53945
JB		 10368 /*
10369 * Algorithm gets a little messy:
7a5e4805 10370 *
79e53945
JB		 10371 * - if the connector already has an assigned crtc, use it (but make
10372 * sure it's on first)
7a5e4805 10373 *
79e53945
JB		 10374 * - try to find the first unused crtc that can drive this connector,
10375 * and use that if we find one
79e53945
JB		 10376 */
10377
10378 /* See if we already have a CRTC for this connector */
10379 if (encoder->crtc) {
10380 crtc = encoder->crtc;
8261b191 10381
51fd371b 10382 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10383 if (ret)
10384 goto fail_unlock;
10385 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10386 if (ret)
10387 goto fail_unlock;
7b24056b 10388
24218aac 10389 old->dpms_mode = connector->dpms;
8261b191
CW		 10390 old->load_detect_temp = false;
10391
10392 /* Make sure the crtc and connector are running */
24218aac
DV		 10393 if (connector->dpms != DRM_MODE_DPMS_ON)
10394 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10395
7173188d 10396 return true;
79e53945
JB		 10397 }
10398
10399 /* Find an unused one (if possible) */
70e1e0ec 10400 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10401 i++;
10402 if (!(encoder->possible_crtcs & (1 << i)))
10403 continue;
83d65738 10404 if (possible_crtc->state->enable)
a459249c
VS		 10405 continue;
10406 /* This can occur when applying the pipe A quirk on resume. */
10407 if (to_intel_crtc(possible_crtc)->new_enabled)
10408 continue;
10409
10410 crtc = possible_crtc;
10411 break;
79e53945
JB		 10412 }
10413
10414 /*
10415 * If we didn't find an unused CRTC, don't use any.
10416 */
10417 if (!crtc) {
7173188d 10418 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10419 goto fail_unlock;
79e53945
JB		 10420 }
10421
51fd371b
RC		 10422 ret = drm_modeset_lock(&crtc->mutex, ctx);
10423 if (ret)
4d02e2de
DV		 10424 goto fail_unlock;
10425 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10426 if (ret)
51fd371b 10427 goto fail_unlock;
fc303101
DV		 10428 intel_encoder->new_crtc = to_intel_crtc(crtc);
10429 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10430
10431 intel_crtc = to_intel_crtc(crtc);
412b61d8 10432 intel_crtc->new_enabled = true;
24218aac 10433 old->dpms_mode = connector->dpms;
8261b191 10434 old->load_detect_temp = true;
d2dff872 10435 old->release_fb = NULL;
79e53945 10436
83a57153
ACO		 10437 state = drm_atomic_state_alloc(dev);
10438 if (!state)
10439 return false;
10440
10441 state->acquire_ctx = ctx;
10442
944b0c76
ACO		 10443 connector_state = drm_atomic_get_connector_state(state, connector);
10444 if (IS_ERR(connector_state)) {
10445 ret = PTR_ERR(connector_state);
10446 goto fail;
10447 }
10448
10449 connector_state->crtc = crtc;
10450 connector_state->best_encoder = &intel_encoder->base;
10451
4be07317
ACO		 10452 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10453 if (IS_ERR(crtc_state)) {
10454 ret = PTR_ERR(crtc_state);
10455 goto fail;
10456 }
10457
49d6fa21 10458 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10459
6492711d
CW		 10460 if (!mode)
10461 mode = &load_detect_mode;
79e53945 10462
d2dff872
CW		 10463 /* We need a framebuffer large enough to accommodate all accesses
10464 * that the plane may generate whilst we perform load detection.
10465 * We can not rely on the fbcon either being present (we get called
10466 * during its initialisation to detect all boot displays, or it may
10467 * not even exist) or that it is large enough to satisfy the
10468 * requested mode.
10469 */
94352cf9
DV		 10470 fb = mode_fits_in_fbdev(dev, mode);
10471 if (fb == NULL) {
d2dff872 10472 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10473 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10474 old->release_fb = fb;
d2dff872
CW		 10475 } else
10476 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10477 if (IS_ERR(fb)) {
d2dff872 10478 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10479 goto fail;
79e53945 10480 }
79e53945 10481
d3a40d1b
ACO		 10482 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10483 if (ret)
10484 goto fail;
10485
8c7b5ccb
ACO		 10486 drm_mode_copy(&crtc_state->base.mode, mode);
10487
10488 if (intel_set_mode(crtc, state)) {
6492711d 10489 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10490 if (old->release_fb)
10491 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10492 goto fail;
79e53945 10493 }
9128b040 10494 crtc->primary->crtc = crtc;
7173188d 10495
79e53945 10496 /* let the connector get through one full cycle before testing */
9d0498a2 10497 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10498 return true;
412b61d8
VS		 10499
10500 fail:
83d65738 10501 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10502fail_unlock:
e5d958ef
ACO		 10503 drm_atomic_state_free(state);
10504 state = NULL;
83a57153 10505
51fd371b
RC		 10506 if (ret == -EDEADLK) {
10507 drm_modeset_backoff(ctx);
10508 goto retry;
10509 }
10510
412b61d8 10511 return false;
79e53945
JB		 10512}
10513
d2434ab7 10514void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10515 struct intel_load_detect_pipe *old,
10516 struct drm_modeset_acquire_ctx *ctx)
79e53945 10517{
83a57153 10518 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10519 struct intel_encoder *intel_encoder =
10520 intel_attached_encoder(connector);
4ef69c7a 10521 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10522 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10524 struct drm_atomic_state *state;
944b0c76 10525 struct drm_connector_state *connector_state;
4be07317 10526 struct intel_crtc_state *crtc_state;
d3a40d1b 10527 int ret;
79e53945 10528
d2dff872 10529 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10530 connector->base.id, connector->name,
8e329a03 10531 encoder->base.id, encoder->name);
d2dff872 10532
8261b191 10533 if (old->load_detect_temp) {
83a57153 10534 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10535 if (!state)
10536 goto fail;
83a57153
ACO		 10537
10538 state->acquire_ctx = ctx;
10539
944b0c76
ACO		 10540 connector_state = drm_atomic_get_connector_state(state, connector);
10541 if (IS_ERR(connector_state))
10542 goto fail;
10543
4be07317
ACO		 10544 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10545 if (IS_ERR(crtc_state))
10546 goto fail;
10547
fc303101
DV		 10548 to_intel_connector(connector)->new_encoder = NULL;
10549 intel_encoder->new_crtc = NULL;
412b61d8 10550 intel_crtc->new_enabled = false;
944b0c76
ACO		 10551
10552 connector_state->best_encoder = NULL;
10553 connector_state->crtc = NULL;
10554
49d6fa21 10555 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10556
d3a40d1b
ACO		 10557 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10558 0, 0);
10559 if (ret)
10560 goto fail;
10561
2bfb4627
ACO		 10562 ret = intel_set_mode(crtc, state);
10563 if (ret)
10564 goto fail;
d2dff872 10565
36206361
DV		 10566 if (old->release_fb) {
10567 drm_framebuffer_unregister_private(old->release_fb);
10568 drm_framebuffer_unreference(old->release_fb);
10569 }
d2dff872 10570
0622a53c 10571 return;
79e53945
JB		 10572 }
10573
c751ce4f 10574 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10575 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10576 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10577
10578 return;
10579fail:
10580 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10581 drm_atomic_state_free(state);
79e53945
JB		 10582}
10583
da4a1efa 10584static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10585 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10586{
10587 struct drm_i915_private *dev_priv = dev->dev_private;
10588 u32 dpll = pipe_config->dpll_hw_state.dpll;
10589
10590 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10591 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10592 else if (HAS_PCH_SPLIT(dev))
10593 return 120000;
10594 else if (!IS_GEN2(dev))
10595 return 96000;
10596 else
10597 return 48000;
10598}
10599
79e53945 10600/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10601static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10602 struct intel_crtc_state *pipe_config)
79e53945 10603{
f1f644dc 10604 struct drm_device *dev = crtc->base.dev;
79e53945 10605 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10606 int pipe = pipe_config->cpu_transcoder;
293623f7 10607 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10608 u32 fp;
10609 intel_clock_t clock;
da4a1efa 10610 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10611
10612 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10613 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10614 else
293623f7 10615 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10616
10617 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10618 if (IS_PINEVIEW(dev)) {
10619 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10620 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10621 } else {
10622 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10623 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10624 }
10625
a6c45cf0 10626 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10627 if (IS_PINEVIEW(dev))
10628 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10629 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10630 else
10631 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10632 DPLL_FPA01_P1_POST_DIV_SHIFT);
10633
10634 switch (dpll & DPLL_MODE_MASK) {
10635 case DPLLB_MODE_DAC_SERIAL:
10636 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10637 5 : 10;
10638 break;
10639 case DPLLB_MODE_LVDS:
10640 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10641 7 : 14;
10642 break;
10643 default:
28c97730 10644 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10645 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10646 return;
79e53945
JB		 10647 }
10648
ac58c3f0 10649 if (IS_PINEVIEW(dev))
da4a1efa 10650 pineview_clock(refclk, &clock);
ac58c3f0 10651 else
da4a1efa 10652 i9xx_clock(refclk, &clock);
79e53945 10653 } else {
0fb58223 10654 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10655 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10656
10657 if (is_lvds) {
10658 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10659 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10660
10661 if (lvds & LVDS_CLKB_POWER_UP)
10662 clock.p2 = 7;
10663 else
10664 clock.p2 = 14;
79e53945
JB		 10665 } else {
10666 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10667 clock.p1 = 2;
10668 else {
10669 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10670 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10671 }
10672 if (dpll & PLL_P2_DIVIDE_BY_4)
10673 clock.p2 = 4;
10674 else
10675 clock.p2 = 2;
79e53945 10676 }
da4a1efa
VS		 10677
10678 i9xx_clock(refclk, &clock);
79e53945
JB		 10679 }
10680
18442d08
VS		 10681 /*
10682 * This value includes pixel_multiplier. We will use
241bfc38 10683 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10684 * encoder's get_config() function.
10685 */
10686 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10687}
10688
6878da05
VS		 10689int intel_dotclock_calculate(int link_freq,
10690 const struct intel_link_m_n *m_n)
f1f644dc 10691{
f1f644dc
JB		 10692 /*
10693 * The calculation for the data clock is:
1041a02f 10694 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10695 * But we want to avoid losing precison if possible, so:
1041a02f 10696 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10697 *
10698 * and the link clock is simpler:
1041a02f 10699 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10700 */
10701
6878da05
VS		 10702 if (!m_n->link_n)
10703 return 0;
f1f644dc 10704
6878da05
VS		 10705 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10706}
f1f644dc 10707
18442d08 10708static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10709 struct intel_crtc_state *pipe_config)
6878da05
VS		 10710{
10711 struct drm_device *dev = crtc->base.dev;
79e53945 10712
18442d08
VS		 10713 /* read out port_clock from the DPLL */
10714 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10715
f1f644dc 10716 /*
18442d08 10717 * This value does not include pixel_multiplier.
241bfc38 10718 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10719 * agree once we know their relationship in the encoder's
10720 * get_config() function.
79e53945 10721 */
2d112de7 10722 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10723 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10724 &pipe_config->fdi_m_n);
79e53945
JB		 10725}
10726
10727/** Returns the currently programmed mode of the given pipe. */
10728struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10729 struct drm_crtc *crtc)
10730{
548f245b 10731 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10733 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10734 struct drm_display_mode *mode;
5cec258b 10735 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10736 int htot = I915_READ(HTOTAL(cpu_transcoder));
10737 int hsync = I915_READ(HSYNC(cpu_transcoder));
10738 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10739 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10740 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10741
10742 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10743 if (!mode)
10744 return NULL;
10745
f1f644dc
JB		 10746 /*
10747 * Construct a pipe_config sufficient for getting the clock info
10748 * back out of crtc_clock_get.
10749 *
10750 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10751 * to use a real value here instead.
10752 */
293623f7 10753 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10754 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10755 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10756 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10757 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10758 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10759
773ae034 10760 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10761 mode->hdisplay = (htot & 0xffff) + 1;
10762 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10763 mode->hsync_start = (hsync & 0xffff) + 1;
10764 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10765 mode->vdisplay = (vtot & 0xffff) + 1;
10766 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10767 mode->vsync_start = (vsync & 0xffff) + 1;
10768 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10769
10770 drm_mode_set_name(mode);
79e53945
JB		 10771
10772 return mode;
10773}
10774
652c393a
JB		 10775static void intel_decrease_pllclock(struct drm_crtc *crtc)
10776{
10777 struct drm_device *dev = crtc->dev;
fbee40df 10778 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10780
baff296c 10781 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10782 return;
10783
10784 if (!dev_priv->lvds_downclock_avail)
10785 return;
10786
10787 /*
10788 * Since this is called by a timer, we should never get here in
10789 * the manual case.
10790 */
10791 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10792 int pipe = intel_crtc->pipe;
10793 int dpll_reg = DPLL(pipe);
10794 int dpll;
f6e5b160 10795
44d98a61 10796 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10797
8ac5a6d5 10798 assert_panel_unlocked(dev_priv, pipe);
652c393a 10799
dc257cf1 10800 dpll = I915_READ(dpll_reg);
652c393a
JB		 10801 dpll |= DISPLAY_RATE_SELECT_FPA1;
10802 I915_WRITE(dpll_reg, dpll);
9d0498a2 10803 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10804 dpll = I915_READ(dpll_reg);
10805 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10806 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10807 }
10808
10809}
10810
f047e395
CW		 10811void intel_mark_busy(struct drm_device *dev)
10812{
c67a470b
PZ		 10813 struct drm_i915_private *dev_priv = dev->dev_private;
10814
f62a0076
CW		 10815 if (dev_priv->mm.busy)
10816 return;
10817
43694d69 10818 intel_runtime_pm_get(dev_priv);
c67a470b 10819 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10820 if (INTEL_INFO(dev)->gen >= 6)
10821 gen6_rps_busy(dev_priv);
f62a0076 10822 dev_priv->mm.busy = true;
f047e395
CW		 10823}
10824
10825void intel_mark_idle(struct drm_device *dev)
652c393a 10826{
c67a470b 10827 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10828 struct drm_crtc *crtc;
652c393a 10829
f62a0076
CW		 10830 if (!dev_priv->mm.busy)
10831 return;
10832
10833 dev_priv->mm.busy = false;
10834
70e1e0ec 10835 for_each_crtc(dev, crtc) {
f4510a27 10836 if (!crtc->primary->fb)
652c393a
JB		 10837 continue;
10838
725a5b54 10839 intel_decrease_pllclock(crtc);
652c393a 10840 }
b29c19b6 10841
3d13ef2e 10842 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10843 gen6_rps_idle(dev->dev_private);
bb4cdd53 10844
43694d69 10845 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10846}
10847
79e53945
JB		 10848static void intel_crtc_destroy(struct drm_crtc *crtc)
10849{
10850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10851 struct drm_device *dev = crtc->dev;
10852 struct intel_unpin_work *work;
67e77c5a 10853
5e2d7afc 10854 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10855 work = intel_crtc->unpin_work;
10856 intel_crtc->unpin_work = NULL;
5e2d7afc 10857 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10858
10859 if (work) {
10860 cancel_work_sync(&work->work);
10861 kfree(work);
10862 }
79e53945
JB		 10863
10864 drm_crtc_cleanup(crtc);
67e77c5a 10865
79e53945
JB		 10866 kfree(intel_crtc);
10867}
10868
6b95a207
KH		 10869static void intel_unpin_work_fn(struct work_struct *__work)
10870{
10871 struct intel_unpin_work *work =
10872 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10873 struct drm_device *dev = work->crtc->dev;
f99d7069 10874 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10875
b4a98e57 10876 mutex_lock(&dev->struct_mutex);
82bc3b2d 10877 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10878 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10879
7ff0ebcc 10880 intel_fbc_update(dev);
f06cc1b9
JH		 10881
10882 if (work->flip_queued_req)
146d84f0 10883 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10884 mutex_unlock(&dev->struct_mutex);
10885
f99d7069 10886 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10887 drm_framebuffer_unreference(work->old_fb);
f99d7069 10888
b4a98e57
CW		 10889 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10890 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10891
6b95a207
KH		 10892 kfree(work);
10893}
10894
1afe3e9d 10895static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10896 struct drm_crtc *crtc)
6b95a207 10897{
6b95a207
KH		 10898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10899 struct intel_unpin_work *work;
6b95a207
KH		 10900 unsigned long flags;
10901
10902 /* Ignore early vblank irqs */
10903 if (intel_crtc == NULL)
10904 return;
10905
f326038a
DV		 10906 /*
10907 * This is called both by irq handlers and the reset code (to complete
10908 * lost pageflips) so needs the full irqsave spinlocks.
10909 */
6b95a207
KH		 10910 spin_lock_irqsave(&dev->event_lock, flags);
10911 work = intel_crtc->unpin_work;
e7d841ca
CW		 10912
10913 /* Ensure we don't miss a work->pending update ... */
10914 smp_rmb();
10915
10916 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10917 spin_unlock_irqrestore(&dev->event_lock, flags);
10918 return;
10919 }
10920
d6bbafa1 10921 page_flip_completed(intel_crtc);
0af7e4df 10922
6b95a207 10923 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10924}
10925
1afe3e9d
JB		 10926void intel_finish_page_flip(struct drm_device *dev, int pipe)
10927{
fbee40df 10928 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10929 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10930
49b14a5c 10931 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10932}
10933
10934void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10935{
fbee40df 10936 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10937 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10938
49b14a5c 10939 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10940}
10941
75f7f3ec
VS		 10942/* Is 'a' after or equal to 'b'? */
10943static bool g4x_flip_count_after_eq(u32 a, u32 b)
10944{
10945 return !((a - b) & 0x80000000);
10946}
10947
10948static bool page_flip_finished(struct intel_crtc *crtc)
10949{
10950 struct drm_device *dev = crtc->base.dev;
10951 struct drm_i915_private *dev_priv = dev->dev_private;
10952
bdfa7542
VS		 10953 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10954 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10955 return true;
10956
75f7f3ec
VS		 10957 /*
10958 * The relevant registers doen't exist on pre-ctg.
10959 * As the flip done interrupt doesn't trigger for mmio
10960 * flips on gmch platforms, a flip count check isn't
10961 * really needed there. But since ctg has the registers,
10962 * include it in the check anyway.
10963 */
10964 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10965 return true;
10966
10967 /*
10968 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10969 * used the same base address. In that case the mmio flip might
10970 * have completed, but the CS hasn't even executed the flip yet.
10971 *
10972 * A flip count check isn't enough as the CS might have updated
10973 * the base address just after start of vblank, but before we
10974 * managed to process the interrupt. This means we'd complete the
10975 * CS flip too soon.
10976 *
10977 * Combining both checks should get us a good enough result. It may
10978 * still happen that the CS flip has been executed, but has not
10979 * yet actually completed. But in case the base address is the same
10980 * anyway, we don't really care.
10981 */
10982 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10983 crtc->unpin_work->gtt_offset &&
10984 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10985 crtc->unpin_work->flip_count);
10986}
10987
6b95a207
KH		 10988void intel_prepare_page_flip(struct drm_device *dev, int plane)
10989{
fbee40df 10990 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10991 struct intel_crtc *intel_crtc =
10992 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10993 unsigned long flags;
10994
f326038a
DV		 10995
10996 /*
10997 * This is called both by irq handlers and the reset code (to complete
10998 * lost pageflips) so needs the full irqsave spinlocks.
10999 *
11000 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 11001 * generate a page-flip completion irq, i.e. every modeset
11002 * is also accompanied by a spurious intel_prepare_page_flip().
11003 */
6b95a207 11004 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 11005 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 11006 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 11007 spin_unlock_irqrestore(&dev->event_lock, flags);
11008}
11009
eba905b2 11010static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 11011{
11012 /* Ensure that the work item is consistent when activating it ... */
11013 smp_wmb();
11014 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11015 /* and that it is marked active as soon as the irq could fire. */
11016 smp_wmb();
11017}
11018
8c9f3aaf
JB		 11019static int intel_gen2_queue_flip(struct drm_device *dev,
11020 struct drm_crtc *crtc,
11021 struct drm_framebuffer *fb,
ed8d1975 11022 struct drm_i915_gem_object *obj,
a4872ba6 11023 struct intel_engine_cs *ring,
ed8d1975 11024 uint32_t flags)
8c9f3aaf 11025{
8c9f3aaf 11026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11027 u32 flip_mask;
11028 int ret;
11029
6d90c952 11030 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11031 if (ret)
4fa62c89 11032 return ret;
8c9f3aaf
JB		 11033
11034 /* Can't queue multiple flips, so wait for the previous
11035 * one to finish before executing the next.
11036 */
11037 if (intel_crtc->plane)
11038 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11039 else
11040 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11041 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11042 intel_ring_emit(ring, MI_NOOP);
11043 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11044 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11045 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11046 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11047 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11048
11049 intel_mark_page_flip_active(intel_crtc);
09246732 11050 __intel_ring_advance(ring);
83d4092b 11051 return 0;
8c9f3aaf
JB		 11052}
11053
11054static int intel_gen3_queue_flip(struct drm_device *dev,
11055 struct drm_crtc *crtc,
11056 struct drm_framebuffer *fb,
ed8d1975 11057 struct drm_i915_gem_object *obj,
a4872ba6 11058 struct intel_engine_cs *ring,
ed8d1975 11059 uint32_t flags)
8c9f3aaf 11060{
8c9f3aaf 11061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11062 u32 flip_mask;
11063 int ret;
11064
6d90c952 11065 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11066 if (ret)
4fa62c89 11067 return ret;
8c9f3aaf
JB		 11068
11069 if (intel_crtc->plane)
11070 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11071 else
11072 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11073 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11074 intel_ring_emit(ring, MI_NOOP);
11075 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11076 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11077 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11078 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11079 intel_ring_emit(ring, MI_NOOP);
11080
e7d841ca 11081 intel_mark_page_flip_active(intel_crtc);
09246732 11082 __intel_ring_advance(ring);
83d4092b 11083 return 0;
8c9f3aaf
JB		 11084}
11085
11086static int intel_gen4_queue_flip(struct drm_device *dev,
11087 struct drm_crtc *crtc,
11088 struct drm_framebuffer *fb,
ed8d1975 11089 struct drm_i915_gem_object *obj,
a4872ba6 11090 struct intel_engine_cs *ring,
ed8d1975 11091 uint32_t flags)
8c9f3aaf
JB		 11092{
11093 struct drm_i915_private *dev_priv = dev->dev_private;
11094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11095 uint32_t pf, pipesrc;
11096 int ret;
11097
6d90c952 11098 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11099 if (ret)
4fa62c89 11100 return ret;
8c9f3aaf
JB		 11101
11102 /* i965+ uses the linear or tiled offsets from the
11103 * Display Registers (which do not change across a page-flip)
11104 * so we need only reprogram the base address.
11105 */
6d90c952
DV		 11106 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11107 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11108 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11109 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11110 obj->tiling_mode);
8c9f3aaf
JB		 11111
11112 /* XXX Enabling the panel-fitter across page-flip is so far
11113 * untested on non-native modes, so ignore it for now.
11114 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11115 */
11116 pf = 0;
11117 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11118 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11119
11120 intel_mark_page_flip_active(intel_crtc);
09246732 11121 __intel_ring_advance(ring);
83d4092b 11122 return 0;
8c9f3aaf
JB		 11123}
11124
11125static int intel_gen6_queue_flip(struct drm_device *dev,
11126 struct drm_crtc *crtc,
11127 struct drm_framebuffer *fb,
ed8d1975 11128 struct drm_i915_gem_object *obj,
a4872ba6 11129 struct intel_engine_cs *ring,
ed8d1975 11130 uint32_t flags)
8c9f3aaf
JB		 11131{
11132 struct drm_i915_private *dev_priv = dev->dev_private;
11133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11134 uint32_t pf, pipesrc;
11135 int ret;
11136
6d90c952 11137 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11138 if (ret)
4fa62c89 11139 return ret;
8c9f3aaf 11140
6d90c952
DV		 11141 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11142 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11143 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11144 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11145
dc257cf1
DV		 11146 /* Contrary to the suggestions in the documentation,
11147 * "Enable Panel Fitter" does not seem to be required when page
11148 * flipping with a non-native mode, and worse causes a normal
11149 * modeset to fail.
11150 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11151 */
11152 pf = 0;
8c9f3aaf 11153 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11154 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11155
11156 intel_mark_page_flip_active(intel_crtc);
09246732 11157 __intel_ring_advance(ring);
83d4092b 11158 return 0;
8c9f3aaf
JB		 11159}
11160
7c9017e5
JB		 11161static int intel_gen7_queue_flip(struct drm_device *dev,
11162 struct drm_crtc *crtc,
11163 struct drm_framebuffer *fb,
ed8d1975 11164 struct drm_i915_gem_object *obj,
a4872ba6 11165 struct intel_engine_cs *ring,
ed8d1975 11166 uint32_t flags)
7c9017e5 11167{
7c9017e5 11168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11169 uint32_t plane_bit = 0;
ffe74d75
CW		 11170 int len, ret;
11171
eba905b2 11172 switch (intel_crtc->plane) {
cb05d8de
DV		 11173 case PLANE_A:
11174 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11175 break;
11176 case PLANE_B:
11177 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11178 break;
11179 case PLANE_C:
11180 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11181 break;
11182 default:
11183 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11184 return -ENODEV;
cb05d8de
DV		 11185 }
11186
ffe74d75 11187 len = 4;
f476828a 11188 if (ring->id == RCS) {
ffe74d75 11189 len += 6;
f476828a
DL		 11190 /*
11191 * On Gen 8, SRM is now taking an extra dword to accommodate
11192 * 48bits addresses, and we need a NOOP for the batch size to
11193 * stay even.
11194 */
11195 if (IS_GEN8(dev))
11196 len += 2;
11197 }
ffe74d75 11198
f66fab8e
VS		 11199 /*
11200 * BSpec MI_DISPLAY_FLIP for IVB:
11201 * "The full packet must be contained within the same cache line."
11202 *
11203 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11204 * cacheline, if we ever start emitting more commands before
11205 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11206 * then do the cacheline alignment, and finally emit the
11207 * MI_DISPLAY_FLIP.
11208 */
11209 ret = intel_ring_cacheline_align(ring);
11210 if (ret)
4fa62c89 11211 return ret;
f66fab8e 11212
ffe74d75 11213 ret = intel_ring_begin(ring, len);
7c9017e5 11214 if (ret)
4fa62c89 11215 return ret;
7c9017e5 11216
ffe74d75
CW		 11217 /* Unmask the flip-done completion message. Note that the bspec says that
11218 * we should do this for both the BCS and RCS, and that we must not unmask
11219 * more than one flip event at any time (or ensure that one flip message
11220 * can be sent by waiting for flip-done prior to queueing new flips).
11221 * Experimentation says that BCS works despite DERRMR masking all
11222 * flip-done completion events and that unmasking all planes at once
11223 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11224 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11225 */
11226 if (ring->id == RCS) {
11227 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11228 intel_ring_emit(ring, DERRMR);
11229 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11230 DERRMR_PIPEB_PRI_FLIP_DONE |
11231 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11232 if (IS_GEN8(dev))
11233 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11234 MI_SRM_LRM_GLOBAL_GTT);
11235 else
11236 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11237 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11238 intel_ring_emit(ring, DERRMR);
11239 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11240 if (IS_GEN8(dev)) {
11241 intel_ring_emit(ring, 0);
11242 intel_ring_emit(ring, MI_NOOP);
11243 }
ffe74d75
CW		 11244 }
11245
cb05d8de 11246 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11247 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11248 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11249 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11250
11251 intel_mark_page_flip_active(intel_crtc);
09246732 11252 __intel_ring_advance(ring);
83d4092b 11253 return 0;
7c9017e5
JB		 11254}
11255
84c33a64
SG		 11256static bool use_mmio_flip(struct intel_engine_cs *ring,
11257 struct drm_i915_gem_object *obj)
11258{
11259 /*
11260 * This is not being used for older platforms, because
11261 * non-availability of flip done interrupt forces us to use
11262 * CS flips. Older platforms derive flip done using some clever
11263 * tricks involving the flip_pending status bits and vblank irqs.
11264 * So using MMIO flips there would disrupt this mechanism.
11265 */
11266
8e09bf83
CW		 11267 if (ring == NULL)
11268 return true;
11269
84c33a64
SG		 11270 if (INTEL_INFO(ring->dev)->gen < 5)
11271 return false;
11272
11273 if (i915.use_mmio_flip < 0)
11274 return false;
11275 else if (i915.use_mmio_flip > 0)
11276 return true;
14bf993e
OM		 11277 else if (i915.enable_execlists)
11278 return true;
84c33a64 11279 else
b4716185 11280 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11281}
11282
ff944564
DL		 11283static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11284{
11285 struct drm_device *dev = intel_crtc->base.dev;
11286 struct drm_i915_private *dev_priv = dev->dev_private;
11287 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11288 const enum pipe pipe = intel_crtc->pipe;
11289 u32 ctl, stride;
11290
11291 ctl = I915_READ(PLANE_CTL(pipe, 0));
11292 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11293 switch (fb->modifier[0]) {
11294 case DRM_FORMAT_MOD_NONE:
11295 break;
11296 case I915_FORMAT_MOD_X_TILED:
ff944564 11297 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11298 break;
11299 case I915_FORMAT_MOD_Y_TILED:
11300 ctl |= PLANE_CTL_TILED_Y;
11301 break;
11302 case I915_FORMAT_MOD_Yf_TILED:
11303 ctl |= PLANE_CTL_TILED_YF;
11304 break;
11305 default:
11306 MISSING_CASE(fb->modifier[0]);
11307 }
ff944564
DL		 11308
11309 /*
11310 * The stride is either expressed as a multiple of 64 bytes chunks for
11311 * linear buffers or in number of tiles for tiled buffers.
11312 */
2ebef630
TU		 11313 stride = fb->pitches[0] /
11314 intel_fb_stride_alignment(dev, fb->modifier[0],
11315 fb->pixel_format);
ff944564
DL		 11316
11317 /*
11318 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11319 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11320 */
11321 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11322 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11323
11324 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11325 POSTING_READ(PLANE_SURF(pipe, 0));
11326}
11327
11328static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11329{
11330 struct drm_device *dev = intel_crtc->base.dev;
11331 struct drm_i915_private *dev_priv = dev->dev_private;
11332 struct intel_framebuffer *intel_fb =
11333 to_intel_framebuffer(intel_crtc->base.primary->fb);
11334 struct drm_i915_gem_object *obj = intel_fb->obj;
11335 u32 dspcntr;
11336 u32 reg;
11337
84c33a64
SG		 11338 reg = DSPCNTR(intel_crtc->plane);
11339 dspcntr = I915_READ(reg);
11340
c5d97472
DL		 11341 if (obj->tiling_mode != I915_TILING_NONE)
11342 dspcntr |= DISPPLANE_TILED;
11343 else
11344 dspcntr &= ~DISPPLANE_TILED;
11345
84c33a64
SG		 11346 I915_WRITE(reg, dspcntr);
11347
11348 I915_WRITE(DSPSURF(intel_crtc->plane),
11349 intel_crtc->unpin_work->gtt_offset);
11350 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11351
ff944564
DL		 11352}
11353
11354/*
11355 * XXX: This is the temporary way to update the plane registers until we get
11356 * around to using the usual plane update functions for MMIO flips
11357 */
11358static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11359{
11360 struct drm_device *dev = intel_crtc->base.dev;
11361 bool atomic_update;
11362 u32 start_vbl_count;
11363
11364 intel_mark_page_flip_active(intel_crtc);
11365
11366 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11367
11368 if (INTEL_INFO(dev)->gen >= 9)
11369 skl_do_mmio_flip(intel_crtc);
11370 else
11371 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11372 ilk_do_mmio_flip(intel_crtc);
11373
9362c7c5
ACO		 11374 if (atomic_update)
11375 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11376}
11377
9362c7c5 11378static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11379{
b2cfe0ab
CW		 11380 struct intel_mmio_flip *mmio_flip =
11381 container_of(work, struct intel_mmio_flip, work);
84c33a64 11382
eed29a5b
DV		 11383 if (mmio_flip->req)
11384 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11385 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11386 false, NULL,
11387 &mmio_flip->i915->rps.mmioflips));
84c33a64 11388
b2cfe0ab
CW		 11389 intel_do_mmio_flip(mmio_flip->crtc);
11390
eed29a5b 11391 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11392 kfree(mmio_flip);
84c33a64
SG		 11393}
11394
11395static int intel_queue_mmio_flip(struct drm_device *dev,
11396 struct drm_crtc *crtc,
11397 struct drm_framebuffer *fb,
11398 struct drm_i915_gem_object *obj,
11399 struct intel_engine_cs *ring,
11400 uint32_t flags)
11401{
b2cfe0ab
CW		 11402 struct intel_mmio_flip *mmio_flip;
11403
11404 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11405 if (mmio_flip == NULL)
11406 return -ENOMEM;
84c33a64 11407
bcafc4e3 11408 mmio_flip->i915 = to_i915(dev);
eed29a5b 11409 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11410 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11411
b2cfe0ab
CW		 11412 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11413 schedule_work(&mmio_flip->work);
84c33a64 11414
84c33a64
SG		 11415 return 0;
11416}
11417
8c9f3aaf
JB		 11418static int intel_default_queue_flip(struct drm_device *dev,
11419 struct drm_crtc *crtc,
11420 struct drm_framebuffer *fb,
ed8d1975 11421 struct drm_i915_gem_object *obj,
a4872ba6 11422 struct intel_engine_cs *ring,
ed8d1975 11423 uint32_t flags)
8c9f3aaf
JB		 11424{
11425 return -ENODEV;
11426}
11427
d6bbafa1
CW		 11428static bool __intel_pageflip_stall_check(struct drm_device *dev,
11429 struct drm_crtc *crtc)
11430{
11431 struct drm_i915_private *dev_priv = dev->dev_private;
11432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11433 struct intel_unpin_work *work = intel_crtc->unpin_work;
11434 u32 addr;
11435
11436 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11437 return true;
11438
11439 if (!work->enable_stall_check)
11440 return false;
11441
11442 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11443 if (work->flip_queued_req &&
11444 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11445 return false;
11446
1e3feefd 11447 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11448 }
11449
1e3feefd 11450 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11451 return false;
11452
11453 /* Potential stall - if we see that the flip has happened,
11454 * assume a missed interrupt. */
11455 if (INTEL_INFO(dev)->gen >= 4)
11456 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11457 else
11458 addr = I915_READ(DSPADDR(intel_crtc->plane));
11459
11460 /* There is a potential issue here with a false positive after a flip
11461 * to the same address. We could address this by checking for a
11462 * non-incrementing frame counter.
11463 */
11464 return addr == work->gtt_offset;
11465}
11466
11467void intel_check_page_flip(struct drm_device *dev, int pipe)
11468{
11469 struct drm_i915_private *dev_priv = dev->dev_private;
11470 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11472 struct intel_unpin_work *work;
f326038a 11473
6c51d46f 11474 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11475
11476 if (crtc == NULL)
11477 return;
11478
f326038a 11479 spin_lock(&dev->event_lock);
6ad790c0
CW		 11480 work = intel_crtc->unpin_work;
11481 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11482 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11483 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11484 page_flip_completed(intel_crtc);
6ad790c0 11485 work = NULL;
d6bbafa1 11486 }
6ad790c0
CW		 11487 if (work != NULL &&
11488 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11489 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11490 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11491}
11492
6b95a207
KH		 11493static int intel_crtc_page_flip(struct drm_crtc *crtc,
11494 struct drm_framebuffer *fb,
ed8d1975
KP		 11495 struct drm_pending_vblank_event *event,
11496 uint32_t page_flip_flags)
6b95a207
KH		 11497{
11498 struct drm_device *dev = crtc->dev;
11499 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11500 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11501 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11503 struct drm_plane *primary = crtc->primary;
a071fa00 11504 enum pipe pipe = intel_crtc->pipe;
6b95a207 11505 struct intel_unpin_work *work;
a4872ba6 11506 struct intel_engine_cs *ring;
cf5d8a46 11507 bool mmio_flip;
52e68630 11508 int ret;
6b95a207 11509
2ff8fde1
MR		 11510 /*
11511 * drm_mode_page_flip_ioctl() should already catch this, but double
11512 * check to be safe. In the future we may enable pageflipping from
11513 * a disabled primary plane.
11514 */
11515 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11516 return -EBUSY;
11517
e6a595d2 11518 /* Can't change pixel format via MI display flips. */
f4510a27 11519 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11520 return -EINVAL;
11521
11522 /*
11523 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11524 * Note that pitch changes could also affect these register.
11525 */
11526 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11527 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11528 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11529 return -EINVAL;
11530
f900db47
CW		 11531 if (i915_terminally_wedged(&dev_priv->gpu_error))
11532 goto out_hang;
11533
b14c5679 11534 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11535 if (work == NULL)
11536 return -ENOMEM;
11537
6b95a207 11538 work->event = event;
b4a98e57 11539 work->crtc = crtc;
ab8d6675 11540 work->old_fb = old_fb;
6b95a207
KH		 11541 INIT_WORK(&work->work, intel_unpin_work_fn);
11542
87b6b101 11543 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11544 if (ret)
11545 goto free_work;
11546
6b95a207 11547 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11548 spin_lock_irq(&dev->event_lock);
6b95a207 11549 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11550 /* Before declaring the flip queue wedged, check if
11551 * the hardware completed the operation behind our backs.
11552 */
11553 if (__intel_pageflip_stall_check(dev, crtc)) {
11554 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11555 page_flip_completed(intel_crtc);
11556 } else {
11557 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11558 spin_unlock_irq(&dev->event_lock);
468f0b44 11559
d6bbafa1
CW		 11560 drm_crtc_vblank_put(crtc);
11561 kfree(work);
11562 return -EBUSY;
11563 }
6b95a207
KH		 11564 }
11565 intel_crtc->unpin_work = work;
5e2d7afc 11566 spin_unlock_irq(&dev->event_lock);
6b95a207 11567
b4a98e57
CW		 11568 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11569 flush_workqueue(dev_priv->wq);
11570
75dfca80 11571 /* Reference the objects for the scheduled work. */
ab8d6675 11572 drm_framebuffer_reference(work->old_fb);
05394f39 11573 drm_gem_object_reference(&obj->base);
6b95a207 11574
f4510a27 11575 crtc->primary->fb = fb;
afd65eb4 11576 update_state_fb(crtc->primary);
1ed1f968 11577
e1f99ce6 11578 work->pending_flip_obj = obj;
e1f99ce6 11579
89ed88ba
CW		 11580 ret = i915_mutex_lock_interruptible(dev);
11581 if (ret)
11582 goto cleanup;
11583
b4a98e57 11584 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11585 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11586
75f7f3ec 11587 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11588 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11589
4fa62c89
VS		 11590 if (IS_VALLEYVIEW(dev)) {
11591 ring = &dev_priv->ring[BCS];
ab8d6675 11592 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11593 /* vlv: DISPLAY_FLIP fails to change tiling */
11594 ring = NULL;
48bf5b2d 11595 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11596 ring = &dev_priv->ring[BCS];
4fa62c89 11597 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11598 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11599 if (ring == NULL || ring->id != RCS)
11600 ring = &dev_priv->ring[BCS];
11601 } else {
11602 ring = &dev_priv->ring[RCS];
11603 }
11604
cf5d8a46
CW		 11605 mmio_flip = use_mmio_flip(ring, obj);
11606
11607 /* When using CS flips, we want to emit semaphores between rings.
11608 * However, when using mmio flips we will create a task to do the
11609 * synchronisation, so all we want here is to pin the framebuffer
11610 * into the display plane and skip any waits.
11611 */
82bc3b2d 11612 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11613 crtc->primary->state,
b4716185 11614 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11615 if (ret)
11616 goto cleanup_pending;
6b95a207 11617
121920fa
TU		 11618 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11619 + intel_crtc->dspaddr_offset;
4fa62c89 11620
cf5d8a46 11621 if (mmio_flip) {
84c33a64
SG		 11622 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11623 page_flip_flags);
d6bbafa1
CW		 11624 if (ret)
11625 goto cleanup_unpin;
11626
f06cc1b9
JH		 11627 i915_gem_request_assign(&work->flip_queued_req,
11628 obj->last_write_req);
d6bbafa1 11629 } else {
d94b5030
CW		 11630 if (obj->last_write_req) {
11631 ret = i915_gem_check_olr(obj->last_write_req);
11632 if (ret)
11633 goto cleanup_unpin;
11634 }
11635
84c33a64 11636 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11637 page_flip_flags);
11638 if (ret)
11639 goto cleanup_unpin;
11640
f06cc1b9
JH		 11641 i915_gem_request_assign(&work->flip_queued_req,
11642 intel_ring_get_request(ring));
d6bbafa1
CW		 11643 }
11644
1e3feefd 11645 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11646 work->enable_stall_check = true;
4fa62c89 11647
ab8d6675 11648 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11649 INTEL_FRONTBUFFER_PRIMARY(pipe));
11650
7ff0ebcc 11651 intel_fbc_disable(dev);
f99d7069 11652 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11653 mutex_unlock(&dev->struct_mutex);
11654
e5510fac
JB		 11655 trace_i915_flip_request(intel_crtc->plane, obj);
11656
6b95a207 11657 return 0;
96b099fd 11658
4fa62c89 11659cleanup_unpin:
82bc3b2d 11660 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11661cleanup_pending:
b4a98e57 11662 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11663 mutex_unlock(&dev->struct_mutex);
11664cleanup:
f4510a27 11665 crtc->primary->fb = old_fb;
afd65eb4 11666 update_state_fb(crtc->primary);
89ed88ba
CW		 11667
11668 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11669 drm_framebuffer_unreference(work->old_fb);
96b099fd 11670
5e2d7afc 11671 spin_lock_irq(&dev->event_lock);
96b099fd 11672 intel_crtc->unpin_work = NULL;
5e2d7afc 11673 spin_unlock_irq(&dev->event_lock);
96b099fd 11674
87b6b101 11675 drm_crtc_vblank_put(crtc);
7317c75e 11676free_work:
96b099fd
CW		 11677 kfree(work);
11678
f900db47
CW		 11679 if (ret == -EIO) {
11680out_hang:
53a366b9 11681 ret = intel_plane_restore(primary);
f0d3dad3 11682 if (ret == 0 && event) {
5e2d7afc 11683 spin_lock_irq(&dev->event_lock);
a071fa00 11684 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11685 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11686 }
f900db47 11687 }
96b099fd 11688 return ret;
6b95a207
KH		 11689}
11690
65b38e0d 11691static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11692 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11693 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11694 .atomic_begin = intel_begin_crtc_commit,
11695 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11696};
11697
9a935856
DV		 11698/**
11699 * intel_modeset_update_staged_output_state
11700 *
11701 * Updates the staged output configuration state, e.g. after we've read out the
11702 * current hw state.
11703 */
11704static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11705{
7668851f 11706 struct intel_crtc *crtc;
9a935856
DV		 11707 struct intel_encoder *encoder;
11708 struct intel_connector *connector;
f6e5b160 11709
3a3371ff 11710 for_each_intel_connector(dev, connector) {
9a935856
DV		 11711 connector->new_encoder =
11712 to_intel_encoder(connector->base.encoder);
11713 }
f6e5b160 11714
b2784e15 11715 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11716 encoder->new_crtc =
11717 to_intel_crtc(encoder->base.crtc);
11718 }
7668851f 11719
d3fcc808 11720 for_each_intel_crtc(dev, crtc) {
83d65738 11721 crtc->new_enabled = crtc->base.state->enable;
7668851f 11722 }
f6e5b160
CW		 11723}
11724
d29b2f9d
ACO		 11725/* Transitional helper to copy current connector/encoder state to
11726 * connector->state. This is needed so that code that is partially
11727 * converted to atomic does the right thing.
11728 */
11729static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11730{
11731 struct intel_connector *connector;
11732
11733 for_each_intel_connector(dev, connector) {
11734 if (connector->base.encoder) {
11735 connector->base.state->best_encoder =
11736 connector->base.encoder;
11737 connector->base.state->crtc =
11738 connector->base.encoder->crtc;
11739 } else {
11740 connector->base.state->best_encoder = NULL;
11741 connector->base.state->crtc = NULL;
11742 }
11743 }
11744}
11745
050f7aeb 11746static void
eba905b2 11747connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11748 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11749{
11750 int bpp = pipe_config->pipe_bpp;
11751
11752 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11753 connector->base.base.id,
c23cc417 11754 connector->base.name);
050f7aeb
DV		 11755
11756 /* Don't use an invalid EDID bpc value */
11757 if (connector->base.display_info.bpc &&
11758 connector->base.display_info.bpc * 3 < bpp) {
11759 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11760 bpp, connector->base.display_info.bpc*3);
11761 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11762 }
11763
11764 /* Clamp bpp to 8 on screens without EDID 1.4 */
11765 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11766 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11767 bpp);
11768 pipe_config->pipe_bpp = 24;
11769 }
11770}
11771
4e53c2e0 11772static int
050f7aeb 11773compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11774 struct intel_crtc_state *pipe_config)
4e53c2e0 11775{
050f7aeb 11776 struct drm_device *dev = crtc->base.dev;
1486017f 11777 struct drm_atomic_state *state;
da3ced29
ACO		 11778 struct drm_connector *connector;
11779 struct drm_connector_state *connector_state;
1486017f 11780 int bpp, i;
4e53c2e0 11781
d328c9d7 11782 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11783 bpp = 10*3;
d328c9d7
DV		 11784 else if (INTEL_INFO(dev)->gen >= 5)
11785 bpp = 12*3;
11786 else
11787 bpp = 8*3;
11788
4e53c2e0 11789
4e53c2e0
DV		 11790 pipe_config->pipe_bpp = bpp;
11791
1486017f
ACO		 11792 state = pipe_config->base.state;
11793
4e53c2e0 11794 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11795 for_each_connector_in_state(state, connector, connector_state, i) {
11796 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11797 continue;
11798
da3ced29
ACO		 11799 connected_sink_compute_bpp(to_intel_connector(connector),
11800 pipe_config);
4e53c2e0
DV		 11801 }
11802
11803 return bpp;
11804}
11805
644db711
DV		 11806static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11807{
11808 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11809 "type: 0x%x flags: 0x%x\n",
1342830c 11810 mode->crtc_clock,
644db711
DV		 11811 mode->crtc_hdisplay, mode->crtc_hsync_start,
11812 mode->crtc_hsync_end, mode->crtc_htotal,
11813 mode->crtc_vdisplay, mode->crtc_vsync_start,
11814 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11815}
11816
c0b03411 11817static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11818 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11819 const char *context)
11820{
6a60cd87
CK		 11821 struct drm_device *dev = crtc->base.dev;
11822 struct drm_plane *plane;
11823 struct intel_plane *intel_plane;
11824 struct intel_plane_state *state;
11825 struct drm_framebuffer *fb;
11826
11827 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11828 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11829
11830 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11831 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11832 pipe_config->pipe_bpp, pipe_config->dither);
11833 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11834 pipe_config->has_pch_encoder,
11835 pipe_config->fdi_lanes,
11836 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11837 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11838 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11839 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11840 pipe_config->has_dp_encoder,
11841 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11842 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11843 pipe_config->dp_m_n.tu);
b95af8be
VK		 11844
11845 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11846 pipe_config->has_dp_encoder,
11847 pipe_config->dp_m2_n2.gmch_m,
11848 pipe_config->dp_m2_n2.gmch_n,
11849 pipe_config->dp_m2_n2.link_m,
11850 pipe_config->dp_m2_n2.link_n,
11851 pipe_config->dp_m2_n2.tu);
11852
55072d19
DV		 11853 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11854 pipe_config->has_audio,
11855 pipe_config->has_infoframe);
11856
c0b03411 11857 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11858 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11859 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11860 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11861 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11862 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11863 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11864 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11865 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11866 crtc->num_scalers,
11867 pipe_config->scaler_state.scaler_users,
11868 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11869 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11870 pipe_config->gmch_pfit.control,
11871 pipe_config->gmch_pfit.pgm_ratios,
11872 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11873 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11874 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11875 pipe_config->pch_pfit.size,
11876 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11877 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11878 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11879
415ff0f6
TU		 11880 if (IS_BROXTON(dev)) {
11881 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11882 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11883 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11884 pipe_config->ddi_pll_sel,
11885 pipe_config->dpll_hw_state.ebb0,
11886 pipe_config->dpll_hw_state.pll0,
11887 pipe_config->dpll_hw_state.pll1,
11888 pipe_config->dpll_hw_state.pll2,
11889 pipe_config->dpll_hw_state.pll3,
11890 pipe_config->dpll_hw_state.pll6,
11891 pipe_config->dpll_hw_state.pll8,
11892 pipe_config->dpll_hw_state.pcsdw12);
11893 } else if (IS_SKYLAKE(dev)) {
11894 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11895 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11896 pipe_config->ddi_pll_sel,
11897 pipe_config->dpll_hw_state.ctrl1,
11898 pipe_config->dpll_hw_state.cfgcr1,
11899 pipe_config->dpll_hw_state.cfgcr2);
11900 } else if (HAS_DDI(dev)) {
11901 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11902 pipe_config->ddi_pll_sel,
11903 pipe_config->dpll_hw_state.wrpll);
11904 } else {
11905 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11906 "fp0: 0x%x, fp1: 0x%x\n",
11907 pipe_config->dpll_hw_state.dpll,
11908 pipe_config->dpll_hw_state.dpll_md,
11909 pipe_config->dpll_hw_state.fp0,
11910 pipe_config->dpll_hw_state.fp1);
11911 }
11912
6a60cd87
CK		 11913 DRM_DEBUG_KMS("planes on this crtc\n");
11914 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11915 intel_plane = to_intel_plane(plane);
11916 if (intel_plane->pipe != crtc->pipe)
11917 continue;
11918
11919 state = to_intel_plane_state(plane->state);
11920 fb = state->base.fb;
11921 if (!fb) {
11922 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11923 "disabled, scaler_id = %d\n",
11924 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11925 plane->base.id, intel_plane->pipe,
11926 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11927 drm_plane_index(plane), state->scaler_id);
11928 continue;
11929 }
11930
11931 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11932 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11933 plane->base.id, intel_plane->pipe,
11934 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11935 drm_plane_index(plane));
11936 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11937 fb->base.id, fb->width, fb->height, fb->pixel_format);
11938 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11939 state->scaler_id,
11940 state->src.x1 >> 16, state->src.y1 >> 16,
11941 drm_rect_width(&state->src) >> 16,
11942 drm_rect_height(&state->src) >> 16,
11943 state->dst.x1, state->dst.y1,
11944 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11945 }
c0b03411
DV		 11946}
11947
bc079e8b
VS		 11948static bool encoders_cloneable(const struct intel_encoder *a,
11949 const struct intel_encoder *b)
accfc0c5 11950{
bc079e8b
VS		 11951 /* masks could be asymmetric, so check both ways */
11952 return a == b || (a->cloneable & (1 << b->type) &&
11953 b->cloneable & (1 << a->type));
11954}
11955
98a221da
ACO		 11956static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11957 struct intel_crtc *crtc,
bc079e8b
VS		 11958 struct intel_encoder *encoder)
11959{
bc079e8b 11960 struct intel_encoder *source_encoder;
da3ced29 11961 struct drm_connector *connector;
98a221da
ACO		 11962 struct drm_connector_state *connector_state;
11963 int i;
bc079e8b 11964
da3ced29 11965 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11966 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11967 continue;
11968
98a221da
ACO		 11969 source_encoder =
11970 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11971 if (!encoders_cloneable(encoder, source_encoder))
11972 return false;
11973 }
11974
11975 return true;
11976}
11977
98a221da
ACO		 11978static bool check_encoder_cloning(struct drm_atomic_state *state,
11979 struct intel_crtc *crtc)
bc079e8b 11980{
accfc0c5 11981 struct intel_encoder *encoder;
da3ced29 11982 struct drm_connector *connector;
98a221da
ACO		 11983 struct drm_connector_state *connector_state;
11984 int i;
accfc0c5 11985
da3ced29 11986 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11987 if (connector_state->crtc != &crtc->base)
11988 continue;
11989
11990 encoder = to_intel_encoder(connector_state->best_encoder);
11991 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11992 return false;
accfc0c5
DV		 11993 }
11994
bc079e8b 11995 return true;
accfc0c5
DV		 11996}
11997
5448a00d 11998static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11999{
5448a00d
ACO		 12000 struct drm_device *dev = state->dev;
12001 struct intel_encoder *encoder;
da3ced29 12002 struct drm_connector *connector;
5448a00d 12003 struct drm_connector_state *connector_state;
00f0b378 12004 unsigned int used_ports = 0;
5448a00d 12005 int i;
00f0b378
VS		 12006
12007 /*
12008 * Walk the connector list instead of the encoder
12009 * list to detect the problem on ddi platforms
12010 * where there's just one encoder per digital port.
12011 */
da3ced29 12012 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12013 if (!connector_state->best_encoder)
00f0b378
VS		 12014 continue;
12015
5448a00d
ACO		 12016 encoder = to_intel_encoder(connector_state->best_encoder);
12017
12018 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12019
12020 switch (encoder->type) {
12021 unsigned int port_mask;
12022 case INTEL_OUTPUT_UNKNOWN:
12023 if (WARN_ON(!HAS_DDI(dev)))
12024 break;
12025 case INTEL_OUTPUT_DISPLAYPORT:
12026 case INTEL_OUTPUT_HDMI:
12027 case INTEL_OUTPUT_EDP:
12028 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12029
12030 /* the same port mustn't appear more than once */
12031 if (used_ports & port_mask)
12032 return false;
12033
12034 used_ports |= port_mask;
12035 default:
12036 break;
12037 }
12038 }
12039
12040 return true;
12041}
12042
83a57153
ACO		 12043static void
12044clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12045{
12046 struct drm_crtc_state tmp_state;
663a3640 12047 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12048 struct intel_dpll_hw_state dpll_hw_state;
12049 enum intel_dpll_id shared_dpll;
8504c74c 12050 uint32_t ddi_pll_sel;
83a57153 12051
7546a384
ACO		 12052 /* FIXME: before the switch to atomic started, a new pipe_config was
12053 * kzalloc'd. Code that depends on any field being zero should be
12054 * fixed, so that the crtc_state can be safely duplicated. For now,
12055 * only fields that are know to not cause problems are preserved. */
12056
83a57153 12057 tmp_state = crtc_state->base;
663a3640 12058 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12059 shared_dpll = crtc_state->shared_dpll;
12060 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12061 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12062
83a57153 12063 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12064
83a57153 12065 crtc_state->base = tmp_state;
663a3640 12066 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12067 crtc_state->shared_dpll = shared_dpll;
12068 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12069 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12070}
12071
548ee15b 12072static int
b8cecdf5 12073intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 12074 struct drm_atomic_state *state,
12075 struct intel_crtc_state *pipe_config)
ee7b9f93 12076{
7758a113 12077 struct intel_encoder *encoder;
da3ced29 12078 struct drm_connector *connector;
0b901879 12079 struct drm_connector_state *connector_state;
d328c9d7 12080 int base_bpp, ret = -EINVAL;
0b901879 12081 int i;
e29c22c0 12082 bool retry = true;
ee7b9f93 12083
98a221da 12084 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 12085 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 12086 return -EINVAL;
accfc0c5
DV		 12087 }
12088
5448a00d 12089 if (!check_digital_port_conflicts(state)) {
00f0b378 12090 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 12091 return -EINVAL;
00f0b378
VS		 12092 }
12093
cdba954e
ACO		 12094 /*
12095 * XXX: Add all connectors to make the crtc state match the encoders.
12096 */
12097 if (!needs_modeset(&pipe_config->base)) {
12098 ret = drm_atomic_add_affected_connectors(state, crtc);
12099 if (ret)
12100 return ret;
12101 }
12102
83a57153 12103 clear_intel_crtc_state(pipe_config);
7758a113 12104
e143a21c
DV		 12105 pipe_config->cpu_transcoder =
12106 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12107
2960bc9c
ID		 12108 /*
12109 * Sanitize sync polarity flags based on requested ones. If neither
12110 * positive or negative polarity is requested, treat this as meaning
12111 * negative polarity.
12112 */
2d112de7 12113 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12114 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12115 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12116
2d112de7 12117 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12118 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12119 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12120
050f7aeb
DV		 12121 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12122 * plane pixel format and any sink constraints into account. Returns the
12123 * source plane bpp so that dithering can be selected on mismatches
12124 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12125 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12126 pipe_config);
12127 if (base_bpp < 0)
4e53c2e0
DV		 12128 goto fail;
12129
e41a56be
VS		 12130 /*
12131 * Determine the real pipe dimensions. Note that stereo modes can
12132 * increase the actual pipe size due to the frame doubling and
12133 * insertion of additional space for blanks between the frame. This
12134 * is stored in the crtc timings. We use the requested mode to do this
12135 * computation to clearly distinguish it from the adjusted mode, which
12136 * can be changed by the connectors in the below retry loop.
12137 */
2d112de7 12138 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12139 &pipe_config->pipe_src_w,
12140 &pipe_config->pipe_src_h);
e41a56be 12141
e29c22c0 12142encoder_retry:
ef1b460d 12143 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12144 pipe_config->port_clock = 0;
ef1b460d 12145 pipe_config->pixel_multiplier = 1;
ff9a6750 12146
135c81b8 12147 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12148 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12149 CRTC_STEREO_DOUBLE);
135c81b8 12150
7758a113
DV		 12151 /* Pass our mode to the connectors and the CRTC to give them a chance to
12152 * adjust it according to limitations or connector properties, and also
12153 * a chance to reject the mode entirely.
47f1c6c9 12154 */
da3ced29 12155 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12156 if (connector_state->crtc != crtc)
7758a113 12157 continue;
7ae89233 12158
0b901879
ACO		 12159 encoder = to_intel_encoder(connector_state->best_encoder);
12160
efea6e8e
DV		 12161 if (!(encoder->compute_config(encoder, pipe_config))) {
12162 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12163 goto fail;
12164 }
ee7b9f93 12165 }
47f1c6c9 12166
ff9a6750
DV		 12167 /* Set default port clock if not overwritten by the encoder. Needs to be
12168 * done afterwards in case the encoder adjusts the mode. */
12169 if (!pipe_config->port_clock)
2d112de7 12170 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12171 * pipe_config->pixel_multiplier;
ff9a6750 12172
a43f6e0f 12173 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12174 if (ret < 0) {
7758a113
DV		 12175 DRM_DEBUG_KMS("CRTC fixup failed\n");
12176 goto fail;
ee7b9f93 12177 }
e29c22c0
DV		 12178
12179 if (ret == RETRY) {
12180 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12181 ret = -EINVAL;
12182 goto fail;
12183 }
12184
12185 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12186 retry = false;
12187 goto encoder_retry;
12188 }
12189
d328c9d7 12190 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12191 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12192 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12193
cdba954e
ACO		 12194 /* Check if we need to force a modeset */
12195 if (pipe_config->has_audio !=
12196 to_intel_crtc_state(crtc->state)->has_audio)
12197 pipe_config->base.mode_changed = true;
12198
12199 /*
12200 * Note we have an issue here with infoframes: current code
12201 * only updates them on the full mode set path per hw
12202 * requirements. So here we should be checking for any
12203 * required changes and forcing a mode set.
12204 */
12205
548ee15b 12206 return 0;
7758a113 12207fail:
548ee15b 12208 return ret;
ee7b9f93 12209}
47f1c6c9 12210
ea9d758d 12211static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12212{
ea9d758d 12213 struct drm_encoder *encoder;
f6e5b160 12214 struct drm_device *dev = crtc->dev;
f6e5b160 12215
ea9d758d
DV		 12216 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12217 if (encoder->crtc == crtc)
12218 return true;
12219
12220 return false;
12221}
12222
12223static void
0a9ab303 12224intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12225{
0a9ab303 12226 struct drm_device *dev = state->dev;
ba41c0de 12227 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12228 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12229 struct drm_crtc *crtc;
12230 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12231 struct drm_connector *connector;
12232
ba41c0de 12233 intel_shared_dpll_commit(dev_priv);
69024de8 12234 drm_atomic_helper_swap_state(state->dev, state);
ba41c0de 12235
b2784e15 12236 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12237 if (!intel_encoder->base.crtc)
12238 continue;
12239
69024de8
ML		 12240 crtc = intel_encoder->base.crtc;
12241 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12242 if (!crtc_state || !needs_modeset(crtc->state))
12243 continue;
ea9d758d 12244
69024de8 12245 intel_encoder->connectors_active = false;
ea9d758d
DV		 12246 }
12247
3cb480bc
ML		 12248 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12249 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12250
7668851f 12251 /* Double check state. */
0a9ab303
ACO		 12252 for_each_crtc(dev, crtc) {
12253 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12254
12255 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
ea9d758d
DV		 12256 }
12257
12258 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12259 if (!connector->encoder || !connector->encoder->crtc)
12260 continue;
12261
69024de8
ML		 12262 crtc = connector->encoder->crtc;
12263 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12264 if (!crtc_state || !needs_modeset(crtc->state))
12265 continue;
ea9d758d 12266
69024de8
ML		 12267 if (crtc->state->enable) {
12268 struct drm_property *dpms_property =
12269 dev->mode_config.dpms_property;
68d34720 12270
69024de8
ML		 12271 connector->dpms = DRM_MODE_DPMS_ON;
12272 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12273
69024de8
ML		 12274 intel_encoder = to_intel_encoder(connector->encoder);
12275 intel_encoder->connectors_active = true;
12276 } else
12277 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12278 }
ea9d758d
DV		 12279}
12280
3bd26263 12281static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12282{
3bd26263 12283 int diff;
f1f644dc
JB		 12284
12285 if (clock1 == clock2)
12286 return true;
12287
12288 if (!clock1 || !clock2)
12289 return false;
12290
12291 diff = abs(clock1 - clock2);
12292
12293 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12294 return true;
12295
12296 return false;
12297}
12298
25c5b266
DV		 12299#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12300 list_for_each_entry((intel_crtc), \
12301 &(dev)->mode_config.crtc_list, \
12302 base.head) \
0973f18f 12303 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12304
0e8ffe1b 12305static bool
2fa2fe9a 12306intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12307 struct intel_crtc_state *current_config,
12308 struct intel_crtc_state *pipe_config)
0e8ffe1b 12309{
66e985c0
DV		 12310#define PIPE_CONF_CHECK_X(name) \
12311 if (current_config->name != pipe_config->name) { \
12312 DRM_ERROR("mismatch in " #name " " \
12313 "(expected 0x%08x, found 0x%08x)\n", \
12314 current_config->name, \
12315 pipe_config->name); \
12316 return false; \
12317 }
12318
08a24034
DV		 12319#define PIPE_CONF_CHECK_I(name) \
12320 if (current_config->name != pipe_config->name) { \
12321 DRM_ERROR("mismatch in " #name " " \
12322 "(expected %i, found %i)\n", \
12323 current_config->name, \
12324 pipe_config->name); \
12325 return false; \
88adfff1
DV		 12326 }
12327
b95af8be
VK		 12328/* This is required for BDW+ where there is only one set of registers for
12329 * switching between high and low RR.
12330 * This macro can be used whenever a comparison has to be made between one
12331 * hw state and multiple sw state variables.
12332 */
12333#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12334 if ((current_config->name != pipe_config->name) && \
12335 (current_config->alt_name != pipe_config->name)) { \
12336 DRM_ERROR("mismatch in " #name " " \
12337 "(expected %i or %i, found %i)\n", \
12338 current_config->name, \
12339 current_config->alt_name, \
12340 pipe_config->name); \
12341 return false; \
12342 }
12343
1bd1bd80
DV		 12344#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12345 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12346 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12347 "(expected %i, found %i)\n", \
12348 current_config->name & (mask), \
12349 pipe_config->name & (mask)); \
12350 return false; \
12351 }
12352
5e550656
VS		 12353#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12354 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12355 DRM_ERROR("mismatch in " #name " " \
12356 "(expected %i, found %i)\n", \
12357 current_config->name, \
12358 pipe_config->name); \
12359 return false; \
12360 }
12361
bb760063
DV		 12362#define PIPE_CONF_QUIRK(quirk) \
12363 ((current_config->quirks | pipe_config->quirks) & (quirk))
12364
eccb140b
DV		 12365 PIPE_CONF_CHECK_I(cpu_transcoder);
12366
08a24034
DV		 12367 PIPE_CONF_CHECK_I(has_pch_encoder);
12368 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12369 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12370 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12371 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12372 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12373 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12374
eb14cb74 12375 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12376
12377 if (INTEL_INFO(dev)->gen < 8) {
12378 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12379 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12380 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12381 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12382 PIPE_CONF_CHECK_I(dp_m_n.tu);
12383
12384 if (current_config->has_drrs) {
12385 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12386 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12387 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12388 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12389 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12390 }
12391 } else {
12392 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12393 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12394 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12395 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12396 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12397 }
eb14cb74 12398
2d112de7
ACO		 12399 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12400 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12401 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12402 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12403 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12404 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12405
2d112de7
ACO		 12406 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12408 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12409 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12410 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12411 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12412
c93f54cf 12413 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12414 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12415 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12416 IS_VALLEYVIEW(dev))
12417 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12418 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12419
9ed109a7
DV		 12420 PIPE_CONF_CHECK_I(has_audio);
12421
2d112de7 12422 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12423 DRM_MODE_FLAG_INTERLACE);
12424
bb760063 12425 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12426 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12427 DRM_MODE_FLAG_PHSYNC);
2d112de7 12428 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12429 DRM_MODE_FLAG_NHSYNC);
2d112de7 12430 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12431 DRM_MODE_FLAG_PVSYNC);
2d112de7 12432 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12433 DRM_MODE_FLAG_NVSYNC);
12434 }
045ac3b5 12435
37327abd
VS		 12436 PIPE_CONF_CHECK_I(pipe_src_w);
12437 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12438
9953599b
DV		 12439 /*
12440 * FIXME: BIOS likes to set up a cloned config with lvds+external
12441 * screen. Since we don't yet re-compute the pipe config when moving
12442 * just the lvds port away to another pipe the sw tracking won't match.
12443 *
12444 * Proper atomic modesets with recomputed global state will fix this.
12445 * Until then just don't check gmch state for inherited modes.
12446 */
12447 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12448 PIPE_CONF_CHECK_I(gmch_pfit.control);
12449 /* pfit ratios are autocomputed by the hw on gen4+ */
12450 if (INTEL_INFO(dev)->gen < 4)
12451 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12452 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12453 }
12454
fd4daa9c
CW		 12455 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12456 if (current_config->pch_pfit.enabled) {
12457 PIPE_CONF_CHECK_I(pch_pfit.pos);
12458 PIPE_CONF_CHECK_I(pch_pfit.size);
12459 }
2fa2fe9a 12460
a1b2278e
CK		 12461 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12462
e59150dc
JB		 12463 /* BDW+ don't expose a synchronous way to read the state */
12464 if (IS_HASWELL(dev))
12465 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12466
282740f7
VS		 12467 PIPE_CONF_CHECK_I(double_wide);
12468
26804afd
DV		 12469 PIPE_CONF_CHECK_X(ddi_pll_sel);
12470
c0d43d62 12471 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12472 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12473 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12474 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12475 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12476 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12477 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12478 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12479 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12480
42571aef
VS		 12481 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12482 PIPE_CONF_CHECK_I(pipe_bpp);
12483
2d112de7 12484 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12485 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12486
66e985c0 12487#undef PIPE_CONF_CHECK_X
08a24034 12488#undef PIPE_CONF_CHECK_I
b95af8be 12489#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12490#undef PIPE_CONF_CHECK_FLAGS
5e550656 12491#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12492#undef PIPE_CONF_QUIRK
88adfff1 12493
0e8ffe1b
DV		 12494 return true;
12495}
12496
08db6652
DL		 12497static void check_wm_state(struct drm_device *dev)
12498{
12499 struct drm_i915_private *dev_priv = dev->dev_private;
12500 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12501 struct intel_crtc *intel_crtc;
12502 int plane;
12503
12504 if (INTEL_INFO(dev)->gen < 9)
12505 return;
12506
12507 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12508 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12509
12510 for_each_intel_crtc(dev, intel_crtc) {
12511 struct skl_ddb_entry *hw_entry, *sw_entry;
12512 const enum pipe pipe = intel_crtc->pipe;
12513
12514 if (!intel_crtc->active)
12515 continue;
12516
12517 /* planes */
dd740780 12518 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12519 hw_entry = &hw_ddb.plane[pipe][plane];
12520 sw_entry = &sw_ddb->plane[pipe][plane];
12521
12522 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12523 continue;
12524
12525 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12526 "(expected (%u,%u), found (%u,%u))\n",
12527 pipe_name(pipe), plane + 1,
12528 sw_entry->start, sw_entry->end,
12529 hw_entry->start, hw_entry->end);
12530 }
12531
12532 /* cursor */
12533 hw_entry = &hw_ddb.cursor[pipe];
12534 sw_entry = &sw_ddb->cursor[pipe];
12535
12536 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12537 continue;
12538
12539 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12540 "(expected (%u,%u), found (%u,%u))\n",
12541 pipe_name(pipe),
12542 sw_entry->start, sw_entry->end,
12543 hw_entry->start, hw_entry->end);
12544 }
12545}
12546
91d1b4bd
DV		 12547static void
12548check_connector_state(struct drm_device *dev)
8af6cf88 12549{
8af6cf88
DV		 12550 struct intel_connector *connector;
12551
3a3371ff 12552 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12553 /* This also checks the encoder/connector hw state with the
12554 * ->get_hw_state callbacks. */
12555 intel_connector_check_state(connector);
12556
e2c719b7 12557 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12558 "connector's staged encoder doesn't match current encoder\n");
12559 }
91d1b4bd
DV		 12560}
12561
12562static void
12563check_encoder_state(struct drm_device *dev)
12564{
12565 struct intel_encoder *encoder;
12566 struct intel_connector *connector;
8af6cf88 12567
b2784e15 12568 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12569 bool enabled = false;
12570 bool active = false;
12571 enum pipe pipe, tracked_pipe;
12572
12573 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12574 encoder->base.base.id,
8e329a03 12575 encoder->base.name);
8af6cf88 12576
e2c719b7 12577 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12578 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12579 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12580 "encoder's active_connectors set, but no crtc\n");
12581
3a3371ff 12582 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12583 if (connector->base.encoder != &encoder->base)
12584 continue;
12585 enabled = true;
12586 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12587 active = true;
12588 }
0e32b39c
DA		 12589 /*
12590 * for MST connectors if we unplug the connector is gone
12591 * away but the encoder is still connected to a crtc
12592 * until a modeset happens in response to the hotplug.
12593 */
12594 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12595 continue;
12596
e2c719b7 12597 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12598 "encoder's enabled state mismatch "
12599 "(expected %i, found %i)\n",
12600 !!encoder->base.crtc, enabled);
e2c719b7 12601 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12602 "active encoder with no crtc\n");
12603
e2c719b7 12604 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12605 "encoder's computed active state doesn't match tracked active state "
12606 "(expected %i, found %i)\n", active, encoder->connectors_active);
12607
12608 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12609 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12610 "encoder's hw state doesn't match sw tracking "
12611 "(expected %i, found %i)\n",
12612 encoder->connectors_active, active);
12613
12614 if (!encoder->base.crtc)
12615 continue;
12616
12617 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12618 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12619 "active encoder's pipe doesn't match"
12620 "(expected %i, found %i)\n",
12621 tracked_pipe, pipe);
12622
12623 }
91d1b4bd
DV		 12624}
12625
12626static void
12627check_crtc_state(struct drm_device *dev)
12628{
fbee40df 12629 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12630 struct intel_crtc *crtc;
12631 struct intel_encoder *encoder;
5cec258b 12632 struct intel_crtc_state pipe_config;
8af6cf88 12633
d3fcc808 12634 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12635 bool enabled = false;
12636 bool active = false;
12637
045ac3b5
JB		 12638 memset(&pipe_config, 0, sizeof(pipe_config));
12639
8af6cf88
DV		 12640 DRM_DEBUG_KMS("[CRTC:%d]\n",
12641 crtc->base.base.id);
12642
83d65738 12643 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12644 "active crtc, but not enabled in sw tracking\n");
12645
b2784e15 12646 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12647 if (encoder->base.crtc != &crtc->base)
12648 continue;
12649 enabled = true;
12650 if (encoder->connectors_active)
12651 active = true;
12652 }
6c49f241 12653
e2c719b7 12654 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12655 "crtc's computed active state doesn't match tracked active state "
12656 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12657 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12658 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12659 "(expected %i, found %i)\n", enabled,
12660 crtc->base.state->enable);
8af6cf88 12661
0e8ffe1b
DV		 12662 active = dev_priv->display.get_pipe_config(crtc,
12663 &pipe_config);
d62cf62a 12664
b6b5d049
VS		 12665 /* hw state is inconsistent with the pipe quirk */
12666 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12667 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12668 active = crtc->active;
12669
b2784e15 12670 for_each_intel_encoder(dev, encoder) {
3eaba51c 12671 enum pipe pipe;
6c49f241
DV		 12672 if (encoder->base.crtc != &crtc->base)
12673 continue;
1d37b689 12674 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12675 encoder->get_config(encoder, &pipe_config);
12676 }
12677
e2c719b7 12678 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12679 "crtc active state doesn't match with hw state "
12680 "(expected %i, found %i)\n", crtc->active, active);
12681
c0b03411 12682 if (active &&
6e3c9717 12683 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12684 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12685 intel_dump_pipe_config(crtc, &pipe_config,
12686 "[hw state]");
6e3c9717 12687 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12688 "[sw state]");
12689 }
8af6cf88
DV		 12690 }
12691}
12692
91d1b4bd
DV		 12693static void
12694check_shared_dpll_state(struct drm_device *dev)
12695{
fbee40df 12696 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12697 struct intel_crtc *crtc;
12698 struct intel_dpll_hw_state dpll_hw_state;
12699 int i;
5358901f
DV		 12700
12701 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12702 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12703 int enabled_crtcs = 0, active_crtcs = 0;
12704 bool active;
12705
12706 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12707
12708 DRM_DEBUG_KMS("%s\n", pll->name);
12709
12710 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12711
e2c719b7 12712 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12713 "more active pll users than references: %i vs %i\n",
3e369b76 12714 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12715 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12716 "pll in active use but not on in sw tracking\n");
e2c719b7 12717 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12718 "pll in on but not on in use in sw tracking\n");
e2c719b7 12719 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12720 "pll on state mismatch (expected %i, found %i)\n",
12721 pll->on, active);
12722
d3fcc808 12723 for_each_intel_crtc(dev, crtc) {
83d65738 12724 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12725 enabled_crtcs++;
12726 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12727 active_crtcs++;
12728 }
e2c719b7 12729 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12730 "pll active crtcs mismatch (expected %i, found %i)\n",
12731 pll->active, active_crtcs);
e2c719b7 12732 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12733 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12734 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12735
e2c719b7 12736 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12737 sizeof(dpll_hw_state)),
12738 "pll hw state mismatch\n");
5358901f 12739 }
8af6cf88
DV		 12740}
12741
91d1b4bd
DV		 12742void
12743intel_modeset_check_state(struct drm_device *dev)
12744{
08db6652 12745 check_wm_state(dev);
91d1b4bd
DV		 12746 check_connector_state(dev);
12747 check_encoder_state(dev);
12748 check_crtc_state(dev);
12749 check_shared_dpll_state(dev);
12750}
12751
5cec258b 12752void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12753 int dotclock)
12754{
12755 /*
12756 * FDI already provided one idea for the dotclock.
12757 * Yell if the encoder disagrees.
12758 */
2d112de7 12759 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12760 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12761 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12762}
12763
80715b2f
VS		 12764static void update_scanline_offset(struct intel_crtc *crtc)
12765{
12766 struct drm_device *dev = crtc->base.dev;
12767
12768 /*
12769 * The scanline counter increments at the leading edge of hsync.
12770 *
12771 * On most platforms it starts counting from vtotal-1 on the
12772 * first active line. That means the scanline counter value is
12773 * always one less than what we would expect. Ie. just after
12774 * start of vblank, which also occurs at start of hsync (on the
12775 * last active line), the scanline counter will read vblank_start-1.
12776 *
12777 * On gen2 the scanline counter starts counting from 1 instead
12778 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12779 * to keep the value positive), instead of adding one.
12780 *
12781 * On HSW+ the behaviour of the scanline counter depends on the output
12782 * type. For DP ports it behaves like most other platforms, but on HDMI
12783 * there's an extra 1 line difference. So we need to add two instead of
12784 * one to the value.
12785 */
12786 if (IS_GEN2(dev)) {
6e3c9717 12787 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12788 int vtotal;
12789
12790 vtotal = mode->crtc_vtotal;
12791 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12792 vtotal /= 2;
12793
12794 crtc->scanline_offset = vtotal - 1;
12795 } else if (HAS_DDI(dev) &&
409ee761 12796 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12797 crtc->scanline_offset = 2;
12798 } else
12799 crtc->scanline_offset = 1;
12800}
12801
5cec258b 12802static struct intel_crtc_state *
7f27126e 12803intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12804 struct drm_atomic_state *state)
7f27126e 12805{
548ee15b 12806 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12807 int ret = 0;
12808
8c7b5ccb
ACO		 12809 ret = drm_atomic_helper_check_modeset(state->dev, state);
12810 if (ret)
12811 return ERR_PTR(ret);
7f27126e 12812
7f27126e
JB		 12813 /*
12814 * Note this needs changes when we start tracking multiple modes
12815 * and crtcs. At that point we'll need to compute the whole config
12816 * (i.e. one pipe_config for each crtc) rather than just the one
12817 * for this crtc.
12818 */
548ee15b
ACO		 12819 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12820 if (IS_ERR(pipe_config))
12821 return pipe_config;
83a57153 12822
4fed33f6 12823 if (!pipe_config->base.enable)
548ee15b 12824 return pipe_config;
7f27126e 12825
8c7b5ccb 12826 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12827 if (ret)
12828 return ERR_PTR(ret);
12829
cdba954e 12830 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, "[modeset]");
db7542dd 12831
8c7b5ccb
ACO		 12832 ret = drm_atomic_helper_check_planes(state->dev, state);
12833 if (ret)
12834 return ERR_PTR(ret);
12835
548ee15b 12836 return pipe_config;
7f27126e
JB		 12837}
12838
0a9ab303 12839static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12840{
225da59b 12841 struct drm_device *dev = state->dev;
ed6739ef 12842 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12843 unsigned clear_pipes = 0;
ed6739ef 12844 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12845 struct intel_crtc_state *intel_crtc_state;
12846 struct drm_crtc *crtc;
12847 struct drm_crtc_state *crtc_state;
ed6739ef 12848 int ret = 0;
0a9ab303 12849 int i;
ed6739ef
ACO		 12850
12851 if (!dev_priv->display.crtc_compute_clock)
12852 return 0;
12853
0a9ab303
ACO		 12854 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12855 intel_crtc = to_intel_crtc(crtc);
4978cc93 12856 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12857
4978cc93 12858 if (needs_modeset(crtc_state)) {
0a9ab303 12859 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12860 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12861 }
0a9ab303
ACO		 12862 }
12863
ed6739ef
ACO		 12864 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12865 if (ret)
12866 goto done;
12867
0a9ab303
ACO		 12868 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12869 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12870 continue;
12871
0a9ab303
ACO		 12872 intel_crtc = to_intel_crtc(crtc);
12873 intel_crtc_state = to_intel_crtc_state(crtc_state);
12874
ed6739ef 12875 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12876 intel_crtc_state);
ed6739ef
ACO		 12877 if (ret) {
12878 intel_shared_dpll_abort_config(dev_priv);
12879 goto done;
12880 }
12881 }
12882
12883done:
12884 return ret;
12885}
12886
054518dd
ACO		 12887/* Code that should eventually be part of atomic_check() */
12888static int __intel_set_mode_checks(struct drm_atomic_state *state)
12889{
12890 struct drm_device *dev = state->dev;
12891 int ret;
12892
12893 /*
12894 * See if the config requires any additional preparation, e.g.
12895 * to adjust global state with pipes off. We need to do this
12896 * here so we can get the modeset_pipe updated config for the new
12897 * mode set on this crtc. For other crtcs we need to use the
12898 * adjusted_mode bits in the crtc directly.
12899 */
b432e5cf
VS		 12900 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12901 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12902 ret = valleyview_modeset_global_pipes(state);
12903 else
12904 ret = broadwell_modeset_global_pipes(state);
12905
054518dd
ACO		 12906 if (ret)
12907 return ret;
12908 }
12909
12910 ret = __intel_set_mode_setup_plls(state);
12911 if (ret)
12912 return ret;
12913
12914 return 0;
12915}
12916
c72d969b 12917static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 12918{
c72d969b 12919 struct drm_device *dev = state->dev;
fbee40df 12920 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 12921 struct drm_crtc *crtc;
12922 struct drm_crtc_state *crtc_state;
c0c36b94 12923 int ret = 0;
0a9ab303 12924 int i;
a6778b3c 12925
054518dd
ACO		 12926 ret = __intel_set_mode_checks(state);
12927 if (ret < 0)
12928 return ret;
12929
d4afb8cc
ACO		 12930 ret = drm_atomic_helper_prepare_planes(dev, state);
12931 if (ret)
12932 return ret;
12933
0a9ab303
ACO		 12934 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12935 if (!needs_modeset(crtc_state))
12936 continue;
460da916 12937
69024de8
ML		 12938 intel_crtc_disable_planes(crtc);
12939 dev_priv->display.crtc_disable(crtc);
12940 if (!crtc_state->enable)
12941 drm_plane_helper_disable(crtc->primary);
ea9d758d 12942 }
a6778b3c 12943
ea9d758d
DV		 12944 /* Only after disabling all output pipelines that will be changed can we
12945 * update the the output configuration. */
0a9ab303 12946 intel_modeset_update_state(state);
f6e5b160 12947
a821fc46
ACO		 12948 /* The state has been swaped above, so state actually contains the
12949 * old state now. */
12950
304603f4 12951 modeset_update_crtc_power_domains(state);
47fab737 12952
d4afb8cc 12953 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12954
12955 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12956 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12957 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12958 continue;
12959
12960 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12961
0a9ab303
ACO		 12962 dev_priv->display.crtc_enable(crtc);
12963 intel_crtc_enable_planes(crtc);
80715b2f 12964 }
a6778b3c 12965
a6778b3c 12966 /* FIXME: add subpixel order */
83a57153 12967
d4afb8cc
ACO		 12968 drm_atomic_helper_cleanup_planes(dev, state);
12969
2bfb4627
ACO		 12970 drm_atomic_state_free(state);
12971
9eb45f22 12972 return 0;
f6e5b160
CW		 12973}
12974
0a9ab303 12975static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12976 struct intel_crtc_state *pipe_config)
f30da187
DV		 12977{
12978 int ret;
12979
c72d969b 12980 ret = __intel_set_mode(pipe_config->base.state);
f30da187
DV		 12981
12982 if (ret == 0)
12983 intel_modeset_check_state(crtc->dev);
12984
12985 return ret;
12986}
12987
7f27126e 12988static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12989 struct drm_atomic_state *state)
7f27126e 12990{
5cec258b 12991 struct intel_crtc_state *pipe_config;
83a57153 12992 int ret = 0;
7f27126e 12993
8c7b5ccb 12994 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12995 if (IS_ERR(pipe_config)) {
12996 ret = PTR_ERR(pipe_config);
12997 goto out;
12998 }
12999
8c7b5ccb 13000 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 13001 if (ret)
13002 goto out;
7f27126e 13003
83a57153
ACO		 13004out:
13005 return ret;
7f27126e
JB		 13006}
13007
c0c36b94
CW		 13008void intel_crtc_restore_mode(struct drm_crtc *crtc)
13009{
83a57153
ACO		 13010 struct drm_device *dev = crtc->dev;
13011 struct drm_atomic_state *state;
4be07317 13012 struct intel_crtc *intel_crtc;
83a57153
ACO		 13013 struct intel_encoder *encoder;
13014 struct intel_connector *connector;
13015 struct drm_connector_state *connector_state;
4be07317 13016 struct intel_crtc_state *crtc_state;
2bfb4627 13017 int ret;
83a57153
ACO		 13018
13019 state = drm_atomic_state_alloc(dev);
13020 if (!state) {
13021 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13022 crtc->base.id);
13023 return;
13024 }
13025
13026 state->acquire_ctx = dev->mode_config.acquire_ctx;
13027
13028 /* The force restore path in the HW readout code relies on the staged
13029 * config still keeping the user requested config while the actual
13030 * state has been overwritten by the configuration read from HW. We
13031 * need to copy the staged config to the atomic state, otherwise the
13032 * mode set will just reapply the state the HW is already in. */
13033 for_each_intel_encoder(dev, encoder) {
13034 if (&encoder->new_crtc->base != crtc)
13035 continue;
13036
13037 for_each_intel_connector(dev, connector) {
13038 if (connector->new_encoder != encoder)
13039 continue;
13040
13041 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13042 if (IS_ERR(connector_state)) {
13043 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13044 connector->base.base.id,
13045 connector->base.name,
13046 PTR_ERR(connector_state));
13047 continue;
13048 }
13049
13050 connector_state->crtc = crtc;
13051 connector_state->best_encoder = &encoder->base;
13052 }
13053 }
13054
4be07317
ACO		 13055 for_each_intel_crtc(dev, intel_crtc) {
13056 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13057 continue;
13058
13059 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13060 if (IS_ERR(crtc_state)) {
13061 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13062 intel_crtc->base.base.id,
13063 PTR_ERR(crtc_state));
13064 continue;
13065 }
13066
49d6fa21
ML		 13067 crtc_state->base.active = crtc_state->base.enable =
13068 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13069
13070 if (&intel_crtc->base == crtc)
13071 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13072 }
13073
d3a40d1b
ACO		 13074 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13075 crtc->primary->fb, crtc->x, crtc->y);
13076
2bfb4627
ACO		 13077 ret = intel_set_mode(crtc, state);
13078 if (ret)
13079 drm_atomic_state_free(state);
c0c36b94
CW		 13080}
13081
25c5b266
DV		 13082#undef for_each_intel_crtc_masked
13083
b7885264
ACO		 13084static bool intel_connector_in_mode_set(struct intel_connector *connector,
13085 struct drm_mode_set *set)
13086{
13087 int ro;
13088
13089 for (ro = 0; ro < set->num_connectors; ro++)
13090 if (set->connectors[ro] == &connector->base)
13091 return true;
13092
13093 return false;
13094}
13095
2e431051 13096static int
9a935856
DV		 13097intel_modeset_stage_output_state(struct drm_device *dev,
13098 struct drm_mode_set *set,
944b0c76 13099 struct drm_atomic_state *state)
50f56119 13100{
9a935856 13101 struct intel_connector *connector;
d5432a9d 13102 struct drm_connector *drm_connector;
944b0c76 13103 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13104 struct drm_crtc *crtc;
13105 struct drm_crtc_state *crtc_state;
13106 int i, ret;
50f56119 13107
9abdda74 13108 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13109 * of connectors. For paranoia, double-check this. */
13110 WARN_ON(!set->fb && (set->num_connectors != 0));
13111 WARN_ON(set->fb && (set->num_connectors == 0));
13112
3a3371ff 13113 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13114 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13115
d5432a9d
ACO		 13116 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13117 continue;
13118
13119 connector_state =
13120 drm_atomic_get_connector_state(state, &connector->base);
13121 if (IS_ERR(connector_state))
13122 return PTR_ERR(connector_state);
13123
b7885264
ACO		 13124 if (in_mode_set) {
13125 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13126 connector_state->best_encoder =
13127 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13128 }
13129
d5432a9d 13130 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13131 continue;
13132
9a935856
DV		 13133 /* If we disable the crtc, disable all its connectors. Also, if
13134 * the connector is on the changing crtc but not on the new
13135 * connector list, disable it. */
b7885264 13136 if (!set->fb || !in_mode_set) {
d5432a9d 13137 connector_state->best_encoder = NULL;
9a935856
DV		 13138
13139 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13140 connector->base.base.id,
c23cc417 13141 connector->base.name);
9a935856 13142 }
50f56119 13143 }
9a935856 13144 /* connector->new_encoder is now updated for all connectors. */
50f56119 13145
d5432a9d
ACO		 13146 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13147 connector = to_intel_connector(drm_connector);
13148
13149 if (!connector_state->best_encoder) {
13150 ret = drm_atomic_set_crtc_for_connector(connector_state,
13151 NULL);
13152 if (ret)
13153 return ret;
7668851f 13154
50f56119 13155 continue;
d5432a9d 13156 }
50f56119 13157
d5432a9d
ACO		 13158 if (intel_connector_in_mode_set(connector, set)) {
13159 struct drm_crtc *crtc = connector->base.state->crtc;
13160
13161 /* If this connector was in a previous crtc, add it
13162 * to the state. We might need to disable it. */
13163 if (crtc) {
13164 crtc_state =
13165 drm_atomic_get_crtc_state(state, crtc);
13166 if (IS_ERR(crtc_state))
13167 return PTR_ERR(crtc_state);
13168 }
13169
13170 ret = drm_atomic_set_crtc_for_connector(connector_state,
13171 set->crtc);
13172 if (ret)
13173 return ret;
13174 }
50f56119
DV		 13175
13176 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13177 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13178 connector_state->crtc)) {
5e2b584e 13179 return -EINVAL;
50f56119 13180 }
944b0c76 13181
9a935856
DV		 13182 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13183 connector->base.base.id,
c23cc417 13184 connector->base.name,
d5432a9d 13185 connector_state->crtc->base.id);
944b0c76 13186
d5432a9d
ACO		 13187 if (connector_state->best_encoder != &connector->encoder->base)
13188 connector->encoder =
13189 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13190 }
7668851f 13191
d5432a9d 13192 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13193 bool has_connectors;
13194
d5432a9d
ACO		 13195 ret = drm_atomic_add_affected_connectors(state, crtc);
13196 if (ret)
13197 return ret;
4be07317 13198
49d6fa21
ML		 13199 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13200 if (has_connectors != crtc_state->enable)
13201 crtc_state->enable =
13202 crtc_state->active = has_connectors;
7668851f
VS		 13203 }
13204
8c7b5ccb
ACO		 13205 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13206 set->fb, set->x, set->y);
13207 if (ret)
13208 return ret;
13209
13210 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13211 if (IS_ERR(crtc_state))
13212 return PTR_ERR(crtc_state);
13213
13214 if (set->mode)
13215 drm_mode_copy(&crtc_state->mode, set->mode);
13216
13217 if (set->num_connectors)
13218 crtc_state->active = true;
13219
2e431051
DV		 13220 return 0;
13221}
13222
bb546623
ACO		 13223static bool primary_plane_visible(struct drm_crtc *crtc)
13224{
13225 struct intel_plane_state *plane_state =
13226 to_intel_plane_state(crtc->primary->state);
13227
13228 return plane_state->visible;
13229}
13230
2e431051
DV		 13231static int intel_crtc_set_config(struct drm_mode_set *set)
13232{
13233 struct drm_device *dev;
83a57153 13234 struct drm_atomic_state *state = NULL;
5cec258b 13235 struct intel_crtc_state *pipe_config;
bb546623 13236 bool primary_plane_was_visible;
2e431051 13237 int ret;
2e431051 13238
8d3e375e
DV		 13239 BUG_ON(!set);
13240 BUG_ON(!set->crtc);
13241 BUG_ON(!set->crtc->helper_private);
2e431051 13242
7e53f3a4
DV		 13243 /* Enforce sane interface api - has been abused by the fb helper. */
13244 BUG_ON(!set->mode && set->fb);
13245 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13246
2e431051
DV		 13247 if (set->fb) {
13248 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13249 set->crtc->base.id, set->fb->base.id,
13250 (int)set->num_connectors, set->x, set->y);
13251 } else {
13252 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13253 }
13254
13255 dev = set->crtc->dev;
13256
83a57153 13257 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13258 if (!state)
13259 return -ENOMEM;
83a57153
ACO		 13260
13261 state->acquire_ctx = dev->mode_config.acquire_ctx;
13262
462a425a 13263 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13264 if (ret)
7cbf41d6 13265 goto out;
2e431051 13266
8c7b5ccb 13267 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13268 if (IS_ERR(pipe_config)) {
6ac0483b 13269 ret = PTR_ERR(pipe_config);
7cbf41d6 13270 goto out;
20664591 13271 }
50f52756 13272
1f9954d0
JB		 13273 intel_update_pipe_size(to_intel_crtc(set->crtc));
13274
bb546623
ACO		 13275 primary_plane_was_visible = primary_plane_visible(set->crtc);
13276
8c7b5ccb 13277 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13278
13279 if (ret == 0 &&
13280 pipe_config->base.enable &&
13281 pipe_config->base.planes_changed &&
13282 !needs_modeset(&pipe_config->base)) {
3b150f08 13283 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13284
13285 /*
13286 * We need to make sure the primary plane is re-enabled if it
13287 * has previously been turned off.
13288 */
bb546623
ACO		 13289 if (ret == 0 && !primary_plane_was_visible &&
13290 primary_plane_visible(set->crtc)) {
3b150f08 13291 WARN_ON(!intel_crtc->active);
87d4300a 13292 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13293 }
13294
7ca51a3a
JB		 13295 /*
13296 * In the fastboot case this may be our only check of the
13297 * state after boot. It would be better to only do it on
13298 * the first update, but we don't have a nice way of doing that
13299 * (and really, set_config isn't used much for high freq page
13300 * flipping, so increasing its cost here shouldn't be a big
13301 * deal).
13302 */
d330a953 13303 if (i915.fastboot && ret == 0)
7ca51a3a 13304 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13305 }
13306
2d05eae1 13307 if (ret) {
bf67dfeb
DV		 13308 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13309 set->crtc->base.id, ret);
2d05eae1 13310 }
50f56119 13311
7cbf41d6 13312out:
2bfb4627
ACO		 13313 if (ret)
13314 drm_atomic_state_free(state);
50f56119
DV		 13315 return ret;
13316}
f6e5b160
CW		 13317
13318static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13319 .gamma_set = intel_crtc_gamma_set,
50f56119 13320 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13321 .destroy = intel_crtc_destroy,
13322 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13323 .atomic_duplicate_state = intel_crtc_duplicate_state,
13324 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13325};
13326
5358901f
DV		 13327static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13328 struct intel_shared_dpll *pll,
13329 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13330{
5358901f 13331 uint32_t val;
ee7b9f93 13332
f458ebbc 13333 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13334 return false;
13335
5358901f 13336 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13337 hw_state->dpll = val;
13338 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13339 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13340
13341 return val & DPLL_VCO_ENABLE;
13342}
13343
15bdd4cf
DV		 13344static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13345 struct intel_shared_dpll *pll)
13346{
3e369b76
ACO		 13347 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13348 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13349}
13350
e7b903d2
DV		 13351static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13352 struct intel_shared_dpll *pll)
13353{
e7b903d2 13354 /* PCH refclock must be enabled first */
89eff4be 13355 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13356
3e369b76 13357 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13358
13359 /* Wait for the clocks to stabilize. */
13360 POSTING_READ(PCH_DPLL(pll->id));
13361 udelay(150);
13362
13363 /* The pixel multiplier can only be updated once the
13364 * DPLL is enabled and the clocks are stable.
13365 *
13366 * So write it again.
13367 */
3e369b76 13368 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13369 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13370 udelay(200);
13371}
13372
13373static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13374 struct intel_shared_dpll *pll)
13375{
13376 struct drm_device *dev = dev_priv->dev;
13377 struct intel_crtc *crtc;
e7b903d2
DV		 13378
13379 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13380 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13381 if (intel_crtc_to_shared_dpll(crtc) == pll)
13382 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13383 }
13384
15bdd4cf
DV		 13385 I915_WRITE(PCH_DPLL(pll->id), 0);
13386 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13387 udelay(200);
13388}
13389
46edb027
DV		 13390static char *ibx_pch_dpll_names[] = {
13391 "PCH DPLL A",
13392 "PCH DPLL B",
13393};
13394
7c74ade1 13395static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13396{
e7b903d2 13397 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13398 int i;
13399
7c74ade1 13400 dev_priv->num_shared_dpll = 2;
ee7b9f93 13401
e72f9fbf 13402 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13403 dev_priv->shared_dplls[i].id = i;
13404 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13405 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13406 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13407 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13408 dev_priv->shared_dplls[i].get_hw_state =
13409 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13410 }
13411}
13412
7c74ade1
DV		 13413static void intel_shared_dpll_init(struct drm_device *dev)
13414{
e7b903d2 13415 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13416
b6283055
VS		 13417 intel_update_cdclk(dev);
13418
9cd86933
DV		 13419 if (HAS_DDI(dev))
13420 intel_ddi_pll_init(dev);
13421 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13422 ibx_pch_dpll_init(dev);
13423 else
13424 dev_priv->num_shared_dpll = 0;
13425
13426 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13427}
13428
1fc0a8f7
TU		 13429/**
13430 * intel_wm_need_update - Check whether watermarks need updating
13431 * @plane: drm plane
13432 * @state: new plane state
13433 *
13434 * Check current plane state versus the new one to determine whether
13435 * watermarks need to be recalculated.
13436 *
13437 * Returns true or false.
13438 */
13439bool intel_wm_need_update(struct drm_plane *plane,
13440 struct drm_plane_state *state)
13441{
13442 /* Update watermarks on tiling changes. */
13443 if (!plane->state->fb || !state->fb ||
13444 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13445 plane->state->rotation != state->rotation)
13446 return true;
13447
13448 return false;
13449}
13450
6beb8c23
MR		 13451/**
13452 * intel_prepare_plane_fb - Prepare fb for usage on plane
13453 * @plane: drm plane to prepare for
13454 * @fb: framebuffer to prepare for presentation
13455 *
13456 * Prepares a framebuffer for usage on a display plane. Generally this
13457 * involves pinning the underlying object and updating the frontbuffer tracking
13458 * bits. Some older platforms need special physical address handling for
13459 * cursor planes.
13460 *
13461 * Returns 0 on success, negative error code on failure.
13462 */
13463int
13464intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13465 struct drm_framebuffer *fb,
13466 const struct drm_plane_state *new_state)
465c120c
MR		 13467{
13468 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13469 struct intel_plane *intel_plane = to_intel_plane(plane);
13470 enum pipe pipe = intel_plane->pipe;
13471 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13472 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13473 unsigned frontbuffer_bits = 0;
13474 int ret = 0;
465c120c 13475
ea2c67bb 13476 if (!obj)
465c120c
MR		 13477 return 0;
13478
6beb8c23
MR		 13479 switch (plane->type) {
13480 case DRM_PLANE_TYPE_PRIMARY:
13481 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13482 break;
13483 case DRM_PLANE_TYPE_CURSOR:
13484 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13485 break;
13486 case DRM_PLANE_TYPE_OVERLAY:
13487 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13488 break;
13489 }
465c120c 13490
6beb8c23 13491 mutex_lock(&dev->struct_mutex);
465c120c 13492
6beb8c23
MR		 13493 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13494 INTEL_INFO(dev)->cursor_needs_physical) {
13495 int align = IS_I830(dev) ? 16 * 1024 : 256;
13496 ret = i915_gem_object_attach_phys(obj, align);
13497 if (ret)
13498 DRM_DEBUG_KMS("failed to attach phys object\n");
13499 } else {
82bc3b2d 13500 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13501 }
465c120c 13502
6beb8c23
MR		 13503 if (ret == 0)
13504 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13505
4c34574f 13506 mutex_unlock(&dev->struct_mutex);
465c120c 13507
6beb8c23
MR		 13508 return ret;
13509}
13510
38f3ce3a
MR		 13511/**
13512 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13513 * @plane: drm plane to clean up for
13514 * @fb: old framebuffer that was on plane
13515 *
13516 * Cleans up a framebuffer that has just been removed from a plane.
13517 */
13518void
13519intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13520 struct drm_framebuffer *fb,
13521 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13522{
13523 struct drm_device *dev = plane->dev;
13524 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13525
13526 if (WARN_ON(!obj))
13527 return;
13528
13529 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13530 !INTEL_INFO(dev)->cursor_needs_physical) {
13531 mutex_lock(&dev->struct_mutex);
82bc3b2d 13532 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13533 mutex_unlock(&dev->struct_mutex);
13534 }
465c120c
MR		 13535}
13536
6156a456
CK		 13537int
13538skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13539{
13540 int max_scale;
13541 struct drm_device *dev;
13542 struct drm_i915_private *dev_priv;
13543 int crtc_clock, cdclk;
13544
13545 if (!intel_crtc || !crtc_state)
13546 return DRM_PLANE_HELPER_NO_SCALING;
13547
13548 dev = intel_crtc->base.dev;
13549 dev_priv = dev->dev_private;
13550 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13551 cdclk = dev_priv->display.get_display_clock_speed(dev);
13552
13553 if (!crtc_clock || !cdclk)
13554 return DRM_PLANE_HELPER_NO_SCALING;
13555
13556 /*
13557 * skl max scale is lower of:
13558 * close to 3 but not 3, -1 is for that purpose
13559 * or
13560 * cdclk/crtc_clock
13561 */
13562 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13563
13564 return max_scale;
13565}
13566
465c120c 13567static int
3c692a41
GP		 13568intel_check_primary_plane(struct drm_plane *plane,
13569 struct intel_plane_state *state)
13570{
32b7eeec
MR		 13571 struct drm_device *dev = plane->dev;
13572 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13573 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13574 struct intel_crtc *intel_crtc;
6156a456 13575 struct intel_crtc_state *crtc_state;
2b875c22 13576 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13577 struct drm_rect *dest = &state->dst;
13578 struct drm_rect *src = &state->src;
13579 const struct drm_rect *clip = &state->clip;
d8106366 13580 bool can_position = false;
6156a456
CK		 13581 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13582 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13583 int ret;
13584
ea2c67bb
MR		 13585 crtc = crtc ? crtc : plane->crtc;
13586 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13587 crtc_state = state->base.state ?
13588 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13589
6156a456 13590 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13591 /* use scaler when colorkey is not required */
13592 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13593 min_scale = 1;
13594 max_scale = skl_max_scale(intel_crtc, crtc_state);
13595 }
d8106366 13596 can_position = true;
6156a456 13597 }
d8106366 13598
c59cb179
MR		 13599 ret = drm_plane_helper_check_update(plane, crtc, fb,
13600 src, dest, clip,
6156a456
CK		 13601 min_scale,
13602 max_scale,
d8106366
SJ		 13603 can_position, true,
13604 &state->visible);
c59cb179
MR		 13605 if (ret)
13606 return ret;
465c120c 13607
32b7eeec 13608 if (intel_crtc->active) {
b70709a6
ML		 13609 struct intel_plane_state *old_state =
13610 to_intel_plane_state(plane->state);
13611
32b7eeec
MR		 13612 intel_crtc->atomic.wait_for_flips = true;
13613
13614 /*
13615 * FBC does not work on some platforms for rotated
13616 * planes, so disable it when rotation is not 0 and
13617 * update it when rotation is set back to 0.
13618 *
13619 * FIXME: This is redundant with the fbc update done in
13620 * the primary plane enable function except that that
13621 * one is done too late. We eventually need to unify
13622 * this.
13623 */
b70709a6 13624 if (state->visible &&
32b7eeec 13625 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13626 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13627 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13628 intel_crtc->atomic.disable_fbc = true;
13629 }
13630
b70709a6 13631 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13632 /*
13633 * BDW signals flip done immediately if the plane
13634 * is disabled, even if the plane enable is already
13635 * armed to occur at the next vblank :(
13636 */
b70709a6 13637 if (IS_BROADWELL(dev))
32b7eeec
MR		 13638 intel_crtc->atomic.wait_vblank = true;
13639 }
13640
13641 intel_crtc->atomic.fb_bits |=
13642 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13643
13644 intel_crtc->atomic.update_fbc = true;
0fda6568 13645
1fc0a8f7 13646 if (intel_wm_need_update(plane, &state->base))
0fda6568 13647 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13648 }
13649
6156a456
CK		 13650 if (INTEL_INFO(dev)->gen >= 9) {
13651 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13652 to_intel_plane(plane), state, 0);
13653 if (ret)
13654 return ret;
13655 }
13656
14af293f
GP		 13657 return 0;
13658}
13659
13660static void
13661intel_commit_primary_plane(struct drm_plane *plane,
13662 struct intel_plane_state *state)
13663{
2b875c22
MR		 13664 struct drm_crtc *crtc = state->base.crtc;
13665 struct drm_framebuffer *fb = state->base.fb;
13666 struct drm_device *dev = plane->dev;
14af293f 13667 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13668 struct intel_crtc *intel_crtc;
14af293f
GP		 13669 struct drm_rect *src = &state->src;
13670
ea2c67bb
MR		 13671 crtc = crtc ? crtc : plane->crtc;
13672 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13673
13674 plane->fb = fb;
9dc806fc
MR		 13675 crtc->x = src->x1 >> 16;
13676 crtc->y = src->y1 >> 16;
ccc759dc 13677
ccc759dc 13678 if (intel_crtc->active) {
27321ae8 13679 if (state->visible)
ccc759dc
GP		 13680 /* FIXME: kill this fastboot hack */
13681 intel_update_pipe_size(intel_crtc);
465c120c 13682
27321ae8
ML		 13683 dev_priv->display.update_primary_plane(crtc, plane->fb,
13684 crtc->x, crtc->y);
ccc759dc 13685 }
465c120c
MR		 13686}
13687
a8ad0d8e
ML		 13688static void
13689intel_disable_primary_plane(struct drm_plane *plane,
13690 struct drm_crtc *crtc,
13691 bool force)
13692{
13693 struct drm_device *dev = plane->dev;
13694 struct drm_i915_private *dev_priv = dev->dev_private;
13695
a8ad0d8e
ML		 13696 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13697}
13698
32b7eeec 13699static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13700{
32b7eeec 13701 struct drm_device *dev = crtc->dev;
140fd38d 13702 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13704 struct intel_plane *intel_plane;
13705 struct drm_plane *p;
13706 unsigned fb_bits = 0;
13707
13708 /* Track fb's for any planes being disabled */
13709 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13710 intel_plane = to_intel_plane(p);
13711
13712 if (intel_crtc->atomic.disabled_planes &
13713 (1 << drm_plane_index(p))) {
13714 switch (p->type) {
13715 case DRM_PLANE_TYPE_PRIMARY:
13716 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13717 break;
13718 case DRM_PLANE_TYPE_CURSOR:
13719 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13720 break;
13721 case DRM_PLANE_TYPE_OVERLAY:
13722 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13723 break;
13724 }
3c692a41 13725
ea2c67bb
MR		 13726 mutex_lock(&dev->struct_mutex);
13727 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13728 mutex_unlock(&dev->struct_mutex);
13729 }
13730 }
3c692a41 13731
32b7eeec
MR		 13732 if (intel_crtc->atomic.wait_for_flips)
13733 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13734
32b7eeec
MR		 13735 if (intel_crtc->atomic.disable_fbc)
13736 intel_fbc_disable(dev);
3c692a41 13737
32b7eeec
MR		 13738 if (intel_crtc->atomic.pre_disable_primary)
13739 intel_pre_disable_primary(crtc);
3c692a41 13740
32b7eeec
MR		 13741 if (intel_crtc->atomic.update_wm)
13742 intel_update_watermarks(crtc);
3c692a41 13743
32b7eeec 13744 intel_runtime_pm_get(dev_priv);
3c692a41 13745
c34c9ee4
MR		 13746 /* Perform vblank evasion around commit operation */
13747 if (intel_crtc->active)
13748 intel_crtc->atomic.evade =
13749 intel_pipe_update_start(intel_crtc,
13750 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13751}
13752
13753static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13754{
13755 struct drm_device *dev = crtc->dev;
13756 struct drm_i915_private *dev_priv = dev->dev_private;
13757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13758 struct drm_plane *p;
13759
c34c9ee4
MR		 13760 if (intel_crtc->atomic.evade)
13761 intel_pipe_update_end(intel_crtc,
13762 intel_crtc->atomic.start_vbl_count);
3c692a41 13763
140fd38d 13764 intel_runtime_pm_put(dev_priv);
3c692a41 13765
32b7eeec
MR		 13766 if (intel_crtc->atomic.wait_vblank)
13767 intel_wait_for_vblank(dev, intel_crtc->pipe);
13768
13769 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13770
13771 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13772 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13773 intel_fbc_update(dev);
ccc759dc 13774 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13775 }
3c692a41 13776
32b7eeec
MR		 13777 if (intel_crtc->atomic.post_enable_primary)
13778 intel_post_enable_primary(crtc);
3c692a41 13779
32b7eeec
MR		 13780 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13781 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13782 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13783 false, false);
13784
13785 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13786}
13787
cf4c7c12 13788/**
4a3b8769
MR		 13789 * intel_plane_destroy - destroy a plane
13790 * @plane: plane to destroy
cf4c7c12 13791 *
4a3b8769
MR		 13792 * Common destruction function for all types of planes (primary, cursor,
13793 * sprite).
cf4c7c12 13794 */
4a3b8769 13795void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13796{
13797 struct intel_plane *intel_plane = to_intel_plane(plane);
13798 drm_plane_cleanup(plane);
13799 kfree(intel_plane);
13800}
13801
65a3fea0 13802const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13803 .update_plane = drm_atomic_helper_update_plane,
13804 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13805 .destroy = intel_plane_destroy,
c196e1d6 13806 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13807 .atomic_get_property = intel_plane_atomic_get_property,
13808 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13809 .atomic_duplicate_state = intel_plane_duplicate_state,
13810 .atomic_destroy_state = intel_plane_destroy_state,
13811
465c120c
MR		 13812};
13813
13814static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13815 int pipe)
13816{
13817 struct intel_plane *primary;
8e7d688b 13818 struct intel_plane_state *state;
465c120c
MR		 13819 const uint32_t *intel_primary_formats;
13820 int num_formats;
13821
13822 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13823 if (primary == NULL)
13824 return NULL;
13825
8e7d688b
MR		 13826 state = intel_create_plane_state(&primary->base);
13827 if (!state) {
ea2c67bb
MR		 13828 kfree(primary);
13829 return NULL;
13830 }
8e7d688b 13831 primary->base.state = &state->base;
ea2c67bb 13832
465c120c
MR		 13833 primary->can_scale = false;
13834 primary->max_downscale = 1;
6156a456
CK		 13835 if (INTEL_INFO(dev)->gen >= 9) {
13836 primary->can_scale = true;
af99ceda 13837 state->scaler_id = -1;
6156a456 13838 }
465c120c
MR		 13839 primary->pipe = pipe;
13840 primary->plane = pipe;
c59cb179
MR		 13841 primary->check_plane = intel_check_primary_plane;
13842 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13843 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13844 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13845 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13846 primary->plane = !pipe;
13847
6c0fd451
DL		 13848 if (INTEL_INFO(dev)->gen >= 9) {
13849 intel_primary_formats = skl_primary_formats;
13850 num_formats = ARRAY_SIZE(skl_primary_formats);
13851 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13852 intel_primary_formats = i965_primary_formats;
13853 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13854 } else {
13855 intel_primary_formats = i8xx_primary_formats;
13856 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13857 }
13858
13859 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13860 &intel_plane_funcs,
465c120c
MR		 13861 intel_primary_formats, num_formats,
13862 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13863
3b7a5119
SJ		 13864 if (INTEL_INFO(dev)->gen >= 4)
13865 intel_create_rotation_property(dev, primary);
48404c1e 13866
ea2c67bb
MR		 13867 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13868
465c120c
MR		 13869 return &primary->base;
13870}
13871
3b7a5119
SJ		 13872void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13873{
13874 if (!dev->mode_config.rotation_property) {
13875 unsigned long flags = BIT(DRM_ROTATE_0) |
13876 BIT(DRM_ROTATE_180);
13877
13878 if (INTEL_INFO(dev)->gen >= 9)
13879 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13880
13881 dev->mode_config.rotation_property =
13882 drm_mode_create_rotation_property(dev, flags);
13883 }
13884 if (dev->mode_config.rotation_property)
13885 drm_object_attach_property(&plane->base.base,
13886 dev->mode_config.rotation_property,
13887 plane->base.state->rotation);
13888}
13889
3d7d6510 13890static int
852e787c
GP		 13891intel_check_cursor_plane(struct drm_plane *plane,
13892 struct intel_plane_state *state)
3d7d6510 13893{
2b875c22 13894 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13895 struct drm_device *dev = plane->dev;
2b875c22 13896 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13897 struct drm_rect *dest = &state->dst;
13898 struct drm_rect *src = &state->src;
13899 const struct drm_rect *clip = &state->clip;
757f9a3e 13900 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13901 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13902 unsigned stride;
13903 int ret;
3d7d6510 13904
ea2c67bb
MR		 13905 crtc = crtc ? crtc : plane->crtc;
13906 intel_crtc = to_intel_crtc(crtc);
13907
757f9a3e 13908 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13909 src, dest, clip,
3d7d6510
MR		 13910 DRM_PLANE_HELPER_NO_SCALING,
13911 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13912 true, true, &state->visible);
757f9a3e
GP		 13913 if (ret)
13914 return ret;
13915
13916
13917 /* if we want to turn off the cursor ignore width and height */
13918 if (!obj)
32b7eeec 13919 goto finish;
757f9a3e 13920
757f9a3e 13921 /* Check for which cursor types we support */
ea2c67bb
MR		 13922 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13923 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13924 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13925 return -EINVAL;
13926 }
13927
ea2c67bb
MR		 13928 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13929 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13930 DRM_DEBUG_KMS("buffer is too small\n");
13931 return -ENOMEM;
13932 }
13933
3a656b54 13934 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13935 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13936 ret = -EINVAL;
13937 }
757f9a3e 13938
32b7eeec
MR		 13939finish:
13940 if (intel_crtc->active) {
3749f463 13941 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13942 intel_crtc->atomic.update_wm = true;
13943
13944 intel_crtc->atomic.fb_bits |=
13945 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13946 }
13947
757f9a3e 13948 return ret;
852e787c 13949}
3d7d6510 13950
a8ad0d8e
ML		 13951static void
13952intel_disable_cursor_plane(struct drm_plane *plane,
13953 struct drm_crtc *crtc,
13954 bool force)
13955{
13956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13957
13958 if (!force) {
13959 plane->fb = NULL;
13960 intel_crtc->cursor_bo = NULL;
13961 intel_crtc->cursor_addr = 0;
13962 }
13963
13964 intel_crtc_update_cursor(crtc, false);
13965}
13966
f4a2cf29 13967static void
852e787c
GP		 13968intel_commit_cursor_plane(struct drm_plane *plane,
13969 struct intel_plane_state *state)
13970{
2b875c22 13971 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13972 struct drm_device *dev = plane->dev;
13973 struct intel_crtc *intel_crtc;
2b875c22 13974 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13975 uint32_t addr;
852e787c 13976
ea2c67bb
MR		 13977 crtc = crtc ? crtc : plane->crtc;
13978 intel_crtc = to_intel_crtc(crtc);
13979
2b875c22 13980 plane->fb = state->base.fb;
ea2c67bb
MR		 13981 crtc->cursor_x = state->base.crtc_x;
13982 crtc->cursor_y = state->base.crtc_y;
13983
a912f12f
GP		 13984 if (intel_crtc->cursor_bo == obj)
13985 goto update;
4ed91096 13986
f4a2cf29 13987 if (!obj)
a912f12f 13988 addr = 0;
f4a2cf29 13989 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13990 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13991 else
a912f12f 13992 addr = obj->phys_handle->busaddr;
852e787c 13993
a912f12f
GP		 13994 intel_crtc->cursor_addr = addr;
13995 intel_crtc->cursor_bo = obj;
13996update:
852e787c 13997
32b7eeec 13998 if (intel_crtc->active)
a912f12f 13999 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14000}
14001
3d7d6510
MR		 14002static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14003 int pipe)
14004{
14005 struct intel_plane *cursor;
8e7d688b 14006 struct intel_plane_state *state;
3d7d6510
MR		 14007
14008 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14009 if (cursor == NULL)
14010 return NULL;
14011
8e7d688b
MR		 14012 state = intel_create_plane_state(&cursor->base);
14013 if (!state) {
ea2c67bb
MR		 14014 kfree(cursor);
14015 return NULL;
14016 }
8e7d688b 14017 cursor->base.state = &state->base;
ea2c67bb 14018
3d7d6510
MR		 14019 cursor->can_scale = false;
14020 cursor->max_downscale = 1;
14021 cursor->pipe = pipe;
14022 cursor->plane = pipe;
c59cb179
MR		 14023 cursor->check_plane = intel_check_cursor_plane;
14024 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14025 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14026
14027 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14028 &intel_plane_funcs,
3d7d6510
MR		 14029 intel_cursor_formats,
14030 ARRAY_SIZE(intel_cursor_formats),
14031 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14032
14033 if (INTEL_INFO(dev)->gen >= 4) {
14034 if (!dev->mode_config.rotation_property)
14035 dev->mode_config.rotation_property =
14036 drm_mode_create_rotation_property(dev,
14037 BIT(DRM_ROTATE_0) |
14038 BIT(DRM_ROTATE_180));
14039 if (dev->mode_config.rotation_property)
14040 drm_object_attach_property(&cursor->base.base,
14041 dev->mode_config.rotation_property,
8e7d688b 14042 state->base.rotation);
4398ad45
VS		 14043 }
14044
af99ceda
CK		 14045 if (INTEL_INFO(dev)->gen >=9)
14046 state->scaler_id = -1;
14047
ea2c67bb
MR		 14048 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14049
3d7d6510
MR		 14050 return &cursor->base;
14051}
14052
549e2bfb
CK		 14053static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14054 struct intel_crtc_state *crtc_state)
14055{
14056 int i;
14057 struct intel_scaler *intel_scaler;
14058 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14059
14060 for (i = 0; i < intel_crtc->num_scalers; i++) {
14061 intel_scaler = &scaler_state->scalers[i];
14062 intel_scaler->in_use = 0;
14063 intel_scaler->id = i;
14064
14065 intel_scaler->mode = PS_SCALER_MODE_DYN;
14066 }
14067
14068 scaler_state->scaler_id = -1;
14069}
14070
b358d0a6 14071static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14072{
fbee40df 14073 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14074 struct intel_crtc *intel_crtc;
f5de6e07 14075 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14076 struct drm_plane *primary = NULL;
14077 struct drm_plane *cursor = NULL;
465c120c 14078 int i, ret;
79e53945 14079
955382f3 14080 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14081 if (intel_crtc == NULL)
14082 return;
14083
f5de6e07
ACO		 14084 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14085 if (!crtc_state)
14086 goto fail;
550acefd
ACO		 14087 intel_crtc->config = crtc_state;
14088 intel_crtc->base.state = &crtc_state->base;
07878248 14089 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14090
549e2bfb
CK		 14091 /* initialize shared scalers */
14092 if (INTEL_INFO(dev)->gen >= 9) {
14093 if (pipe == PIPE_C)
14094 intel_crtc->num_scalers = 1;
14095 else
14096 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14097
14098 skl_init_scalers(dev, intel_crtc, crtc_state);
14099 }
14100
465c120c 14101 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14102 if (!primary)
14103 goto fail;
14104
14105 cursor = intel_cursor_plane_create(dev, pipe);
14106 if (!cursor)
14107 goto fail;
14108
465c120c 14109 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14110 cursor, &intel_crtc_funcs);
14111 if (ret)
14112 goto fail;
79e53945
JB		 14113
14114 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14115 for (i = 0; i < 256; i++) {
14116 intel_crtc->lut_r[i] = i;
14117 intel_crtc->lut_g[i] = i;
14118 intel_crtc->lut_b[i] = i;
14119 }
14120
1f1c2e24
VS		 14121 /*
14122 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14123 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14124 */
80824003
JB		 14125 intel_crtc->pipe = pipe;
14126 intel_crtc->plane = pipe;
3a77c4c4 14127 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14128 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14129 intel_crtc->plane = !pipe;
80824003
JB		 14130 }
14131
4b0e333e
CW		 14132 intel_crtc->cursor_base = ~0;
14133 intel_crtc->cursor_cntl = ~0;
dc41c154 14134 intel_crtc->cursor_size = ~0;
8d7849db 14135
22fd0fab
JB		 14136 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14137 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14138 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14139 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14140
79e53945 14141 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14142
14143 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14144 return;
14145
14146fail:
14147 if (primary)
14148 drm_plane_cleanup(primary);
14149 if (cursor)
14150 drm_plane_cleanup(cursor);
f5de6e07 14151 kfree(crtc_state);
3d7d6510 14152 kfree(intel_crtc);
79e53945
JB		 14153}
14154
752aa88a
JB		 14155enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14156{
14157 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14158 struct drm_device *dev = connector->base.dev;
752aa88a 14159
51fd371b 14160 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14161
d3babd3f 14162 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14163 return INVALID_PIPE;
14164
14165 return to_intel_crtc(encoder->crtc)->pipe;
14166}
14167
08d7b3d1 14168int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14169 struct drm_file *file)
08d7b3d1 14170{
08d7b3d1 14171 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14172 struct drm_crtc *drmmode_crtc;
c05422d5 14173 struct intel_crtc *crtc;
08d7b3d1 14174
7707e653 14175 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14176
7707e653 14177 if (!drmmode_crtc) {
08d7b3d1 14178 DRM_ERROR("no such CRTC id\n");
3f2c2057 14179 return -ENOENT;
08d7b3d1
CW		 14180 }
14181
7707e653 14182 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14183 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14184
c05422d5 14185 return 0;
08d7b3d1
CW		 14186}
14187
66a9278e 14188static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14189{
66a9278e
DV		 14190 struct drm_device *dev = encoder->base.dev;
14191 struct intel_encoder *source_encoder;
79e53945 14192 int index_mask = 0;
79e53945
JB		 14193 int entry = 0;
14194
b2784e15 14195 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14196 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14197 index_mask |= (1 << entry);
14198
79e53945
JB		 14199 entry++;
14200 }
4ef69c7a 14201
79e53945
JB		 14202 return index_mask;
14203}
14204
4d302442
CW		 14205static bool has_edp_a(struct drm_device *dev)
14206{
14207 struct drm_i915_private *dev_priv = dev->dev_private;
14208
14209 if (!IS_MOBILE(dev))
14210 return false;
14211
14212 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14213 return false;
14214
e3589908 14215 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14216 return false;
14217
14218 return true;
14219}
14220
84b4e042
JB		 14221static bool intel_crt_present(struct drm_device *dev)
14222{
14223 struct drm_i915_private *dev_priv = dev->dev_private;
14224
884497ed
DL		 14225 if (INTEL_INFO(dev)->gen >= 9)
14226 return false;
14227
cf404ce4 14228 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14229 return false;
14230
14231 if (IS_CHERRYVIEW(dev))
14232 return false;
14233
14234 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14235 return false;
14236
14237 return true;
14238}
14239
79e53945
JB		 14240static void intel_setup_outputs(struct drm_device *dev)
14241{
725e30ad 14242 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14243 struct intel_encoder *encoder;
cb0953d7 14244 bool dpd_is_edp = false;
79e53945 14245
c9093354 14246 intel_lvds_init(dev);
79e53945 14247
84b4e042 14248 if (intel_crt_present(dev))
79935fca 14249 intel_crt_init(dev);
cb0953d7 14250
c776eb2e
VK		 14251 if (IS_BROXTON(dev)) {
14252 /*
14253 * FIXME: Broxton doesn't support port detection via the
14254 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14255 * detect the ports.
14256 */
14257 intel_ddi_init(dev, PORT_A);
14258 intel_ddi_init(dev, PORT_B);
14259 intel_ddi_init(dev, PORT_C);
14260 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14261 int found;
14262
de31facd
JB		 14263 /*
14264 * Haswell uses DDI functions to detect digital outputs.
14265 * On SKL pre-D0 the strap isn't connected, so we assume
14266 * it's there.
14267 */
0e72a5b5 14268 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14269 /* WaIgnoreDDIAStrap: skl */
14270 if (found ||
14271 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14272 intel_ddi_init(dev, PORT_A);
14273
14274 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14275 * register */
14276 found = I915_READ(SFUSE_STRAP);
14277
14278 if (found & SFUSE_STRAP_DDIB_DETECTED)
14279 intel_ddi_init(dev, PORT_B);
14280 if (found & SFUSE_STRAP_DDIC_DETECTED)
14281 intel_ddi_init(dev, PORT_C);
14282 if (found & SFUSE_STRAP_DDID_DETECTED)
14283 intel_ddi_init(dev, PORT_D);
14284 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14285 int found;
5d8a7752 14286 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14287
14288 if (has_edp_a(dev))
14289 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14290
dc0fa718 14291 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14292 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14293 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14294 if (!found)
e2debe91 14295 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14296 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14297 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14298 }
14299
dc0fa718 14300 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14301 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14302
dc0fa718 14303 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14304 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14305
5eb08b69 14306 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14307 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14308
270b3042 14309 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14310 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14311 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14312 /*
14313 * The DP_DETECTED bit is the latched state of the DDC
14314 * SDA pin at boot. However since eDP doesn't require DDC
14315 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14316 * eDP ports may have been muxed to an alternate function.
14317 * Thus we can't rely on the DP_DETECTED bit alone to detect
14318 * eDP ports. Consult the VBT as well as DP_DETECTED to
14319 * detect eDP ports.
14320 */
d2182a66
VS		 14321 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14322 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14323 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14324 PORT_B);
e17ac6db
VS		 14325 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14326 intel_dp_is_edp(dev, PORT_B))
14327 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14328
d2182a66
VS		 14329 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14330 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14331 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14332 PORT_C);
e17ac6db
VS		 14333 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14334 intel_dp_is_edp(dev, PORT_C))
14335 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14336
9418c1f1 14337 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14338 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14339 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14340 PORT_D);
e17ac6db
VS		 14341 /* eDP not supported on port D, so don't check VBT */
14342 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14343 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14344 }
14345
3cfca973 14346 intel_dsi_init(dev);
103a196f 14347 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14348 bool found = false;
7d57382e 14349
e2debe91 14350 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14351 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14352 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14353 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14354 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14355 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14356 }
27185ae1 14357
e7281eab 14358 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14359 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14360 }
13520b05
KH		 14361
14362 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14363
e2debe91 14364 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14365 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14366 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14367 }
27185ae1 14368
e2debe91 14369 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14370
b01f2c3a
JB		 14371 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14372 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14373 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14374 }
e7281eab 14375 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14376 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14377 }
27185ae1 14378
b01f2c3a 14379 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14380 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14381 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14382 } else if (IS_GEN2(dev))
79e53945
JB		 14383 intel_dvo_init(dev);
14384
103a196f 14385 if (SUPPORTS_TV(dev))
79e53945
JB		 14386 intel_tv_init(dev);
14387
0bc12bcb 14388 intel_psr_init(dev);
7c8f8a70 14389
b2784e15 14390 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14391 encoder->base.possible_crtcs = encoder->crtc_mask;
14392 encoder->base.possible_clones =
66a9278e 14393 intel_encoder_clones(encoder);
79e53945 14394 }
47356eb6 14395
dde86e2d 14396 intel_init_pch_refclk(dev);
270b3042
DV		 14397
14398 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14399}
14400
14401static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14402{
60a5ca01 14403 struct drm_device *dev = fb->dev;
79e53945 14404 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14405
ef2d633e 14406 drm_framebuffer_cleanup(fb);
60a5ca01 14407 mutex_lock(&dev->struct_mutex);
ef2d633e 14408 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14409 drm_gem_object_unreference(&intel_fb->obj->base);
14410 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14411 kfree(intel_fb);
14412}
14413
14414static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14415 struct drm_file *file,
79e53945
JB		 14416 unsigned int *handle)
14417{
14418 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14419 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14420
05394f39 14421 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14422}
14423
14424static const struct drm_framebuffer_funcs intel_fb_funcs = {
14425 .destroy = intel_user_framebuffer_destroy,
14426 .create_handle = intel_user_framebuffer_create_handle,
14427};
14428
b321803d
DL		 14429static
14430u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14431 uint32_t pixel_format)
14432{
14433 u32 gen = INTEL_INFO(dev)->gen;
14434
14435 if (gen >= 9) {
14436 /* "The stride in bytes must not exceed the of the size of 8K
14437 * pixels and 32K bytes."
14438 */
14439 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14440 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14441 return 32*1024;
14442 } else if (gen >= 4) {
14443 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14444 return 16*1024;
14445 else
14446 return 32*1024;
14447 } else if (gen >= 3) {
14448 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14449 return 8*1024;
14450 else
14451 return 16*1024;
14452 } else {
14453 /* XXX DSPC is limited to 4k tiled */
14454 return 8*1024;
14455 }
14456}
14457
b5ea642a
DV		 14458static int intel_framebuffer_init(struct drm_device *dev,
14459 struct intel_framebuffer *intel_fb,
14460 struct drm_mode_fb_cmd2 *mode_cmd,
14461 struct drm_i915_gem_object *obj)
79e53945 14462{
6761dd31 14463 unsigned int aligned_height;
79e53945 14464 int ret;
b321803d 14465 u32 pitch_limit, stride_alignment;
79e53945 14466
dd4916c5
DV		 14467 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14468
2a80eada
DV		 14469 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14470 /* Enforce that fb modifier and tiling mode match, but only for
14471 * X-tiled. This is needed for FBC. */
14472 if (!!(obj->tiling_mode == I915_TILING_X) !=
14473 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14474 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14475 return -EINVAL;
14476 }
14477 } else {
14478 if (obj->tiling_mode == I915_TILING_X)
14479 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14480 else if (obj->tiling_mode == I915_TILING_Y) {
14481 DRM_DEBUG("No Y tiling for legacy addfb\n");
14482 return -EINVAL;
14483 }
14484 }
14485
9a8f0a12
TU		 14486 /* Passed in modifier sanity checking. */
14487 switch (mode_cmd->modifier[0]) {
14488 case I915_FORMAT_MOD_Y_TILED:
14489 case I915_FORMAT_MOD_Yf_TILED:
14490 if (INTEL_INFO(dev)->gen < 9) {
14491 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14492 mode_cmd->modifier[0]);
14493 return -EINVAL;
14494 }
14495 case DRM_FORMAT_MOD_NONE:
14496 case I915_FORMAT_MOD_X_TILED:
14497 break;
14498 default:
c0f40428
JB		 14499 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14500 mode_cmd->modifier[0]);
57cd6508 14501 return -EINVAL;
c16ed4be 14502 }
57cd6508 14503
b321803d
DL		 14504 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14505 mode_cmd->pixel_format);
14506 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14507 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14508 mode_cmd->pitches[0], stride_alignment);
57cd6508 14509 return -EINVAL;
c16ed4be 14510 }
57cd6508 14511
b321803d
DL		 14512 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14513 mode_cmd->pixel_format);
a35cdaa0 14514 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14515 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14516 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14517 "tiled" : "linear",
a35cdaa0 14518 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14519 return -EINVAL;
c16ed4be 14520 }
5d7bd705 14521
2a80eada 14522 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14523 mode_cmd->pitches[0] != obj->stride) {
14524 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14525 mode_cmd->pitches[0], obj->stride);
5d7bd705 14526 return -EINVAL;
c16ed4be 14527 }
5d7bd705 14528
57779d06 14529 /* Reject formats not supported by any plane early. */
308e5bcb 14530 switch (mode_cmd->pixel_format) {
57779d06 14531 case DRM_FORMAT_C8:
04b3924d
VS		 14532 case DRM_FORMAT_RGB565:
14533 case DRM_FORMAT_XRGB8888:
14534 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14535 break;
14536 case DRM_FORMAT_XRGB1555:
c16ed4be 14537 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14538 DRM_DEBUG("unsupported pixel format: %s\n",
14539 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14540 return -EINVAL;
c16ed4be 14541 }
57779d06 14542 break;
57779d06 14543 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14544 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14545 DRM_DEBUG("unsupported pixel format: %s\n",
14546 drm_get_format_name(mode_cmd->pixel_format));
14547 return -EINVAL;
14548 }
14549 break;
14550 case DRM_FORMAT_XBGR8888:
04b3924d 14551 case DRM_FORMAT_XRGB2101010:
57779d06 14552 case DRM_FORMAT_XBGR2101010:
c16ed4be 14553 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14554 DRM_DEBUG("unsupported pixel format: %s\n",
14555 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14556 return -EINVAL;
c16ed4be 14557 }
b5626747 14558 break;
7531208b
DL		 14559 case DRM_FORMAT_ABGR2101010:
14560 if (!IS_VALLEYVIEW(dev)) {
14561 DRM_DEBUG("unsupported pixel format: %s\n",
14562 drm_get_format_name(mode_cmd->pixel_format));
14563 return -EINVAL;
14564 }
14565 break;
04b3924d
VS		 14566 case DRM_FORMAT_YUYV:
14567 case DRM_FORMAT_UYVY:
14568 case DRM_FORMAT_YVYU:
14569 case DRM_FORMAT_VYUY:
c16ed4be 14570 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14571 DRM_DEBUG("unsupported pixel format: %s\n",
14572 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14573 return -EINVAL;
c16ed4be 14574 }
57cd6508
CW		 14575 break;
14576 default:
4ee62c76
VS		 14577 DRM_DEBUG("unsupported pixel format: %s\n",
14578 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14579 return -EINVAL;
14580 }
14581
90f9a336
VS		 14582 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14583 if (mode_cmd->offsets[0] != 0)
14584 return -EINVAL;
14585
ec2c981e 14586 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14587 mode_cmd->pixel_format,
14588 mode_cmd->modifier[0]);
53155c0a
DV		 14589 /* FIXME drm helper for size checks (especially planar formats)? */
14590 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14591 return -EINVAL;
14592
c7d73f6a
DV		 14593 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14594 intel_fb->obj = obj;
80075d49 14595 intel_fb->obj->framebuffer_references++;
c7d73f6a 14596
79e53945
JB		 14597 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14598 if (ret) {
14599 DRM_ERROR("framebuffer init failed %d\n", ret);
14600 return ret;
14601 }
14602
79e53945
JB		 14603 return 0;
14604}
14605
79e53945
JB		 14606static struct drm_framebuffer *
14607intel_user_framebuffer_create(struct drm_device *dev,
14608 struct drm_file *filp,
308e5bcb 14609 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14610{
05394f39 14611 struct drm_i915_gem_object *obj;
79e53945 14612
308e5bcb
JB		 14613 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14614 mode_cmd->handles[0]));
c8725226 14615 if (&obj->base == NULL)
cce13ff7 14616 return ERR_PTR(-ENOENT);
79e53945 14617
d2dff872 14618 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14619}
14620
4520f53a 14621#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14622static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14623{
14624}
14625#endif
14626
79e53945 14627static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14628 .fb_create = intel_user_framebuffer_create,
0632fef6 14629 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14630 .atomic_check = intel_atomic_check,
14631 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14632};
14633
e70236a8
JB		 14634/* Set up chip specific display functions */
14635static void intel_init_display(struct drm_device *dev)
14636{
14637 struct drm_i915_private *dev_priv = dev->dev_private;
14638
ee9300bb
DV		 14639 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14640 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14641 else if (IS_CHERRYVIEW(dev))
14642 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14643 else if (IS_VALLEYVIEW(dev))
14644 dev_priv->display.find_dpll = vlv_find_best_dpll;
14645 else if (IS_PINEVIEW(dev))
14646 dev_priv->display.find_dpll = pnv_find_best_dpll;
14647 else
14648 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14649
bc8d7dff
DL		 14650 if (INTEL_INFO(dev)->gen >= 9) {
14651 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14652 dev_priv->display.get_initial_plane_config =
14653 skylake_get_initial_plane_config;
bc8d7dff
DL		 14654 dev_priv->display.crtc_compute_clock =
14655 haswell_crtc_compute_clock;
14656 dev_priv->display.crtc_enable = haswell_crtc_enable;
14657 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14658 dev_priv->display.update_primary_plane =
14659 skylake_update_primary_plane;
14660 } else if (HAS_DDI(dev)) {
0e8ffe1b 14661 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14662 dev_priv->display.get_initial_plane_config =
14663 ironlake_get_initial_plane_config;
797d0259
ACO		 14664 dev_priv->display.crtc_compute_clock =
14665 haswell_crtc_compute_clock;
4f771f10
PZ		 14666 dev_priv->display.crtc_enable = haswell_crtc_enable;
14667 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14668 dev_priv->display.update_primary_plane =
14669 ironlake_update_primary_plane;
09b4ddf9 14670 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14671 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14672 dev_priv->display.get_initial_plane_config =
14673 ironlake_get_initial_plane_config;
3fb37703
ACO		 14674 dev_priv->display.crtc_compute_clock =
14675 ironlake_crtc_compute_clock;
76e5a89c
DV		 14676 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14677 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14678 dev_priv->display.update_primary_plane =
14679 ironlake_update_primary_plane;
89b667f8
JB		 14680 } else if (IS_VALLEYVIEW(dev)) {
14681 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14682 dev_priv->display.get_initial_plane_config =
14683 i9xx_get_initial_plane_config;
d6dfee7a 14684 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14685 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14686 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14687 dev_priv->display.update_primary_plane =
14688 i9xx_update_primary_plane;
f564048e 14689 } else {
0e8ffe1b 14690 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14691 dev_priv->display.get_initial_plane_config =
14692 i9xx_get_initial_plane_config;
d6dfee7a 14693 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14694 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14695 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14696 dev_priv->display.update_primary_plane =
14697 i9xx_update_primary_plane;
f564048e 14698 }
e70236a8 14699
e70236a8 14700 /* Returns the core display clock speed */
1652d19e
VS		 14701 if (IS_SKYLAKE(dev))
14702 dev_priv->display.get_display_clock_speed =
14703 skylake_get_display_clock_speed;
14704 else if (IS_BROADWELL(dev))
14705 dev_priv->display.get_display_clock_speed =
14706 broadwell_get_display_clock_speed;
14707 else if (IS_HASWELL(dev))
14708 dev_priv->display.get_display_clock_speed =
14709 haswell_get_display_clock_speed;
14710 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14711 dev_priv->display.get_display_clock_speed =
14712 valleyview_get_display_clock_speed;
b37a6434
VS		 14713 else if (IS_GEN5(dev))
14714 dev_priv->display.get_display_clock_speed =
14715 ilk_get_display_clock_speed;
a7c66cd8 14716 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14717 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14718 dev_priv->display.get_display_clock_speed =
14719 i945_get_display_clock_speed;
34edce2f
VS		 14720 else if (IS_GM45(dev))
14721 dev_priv->display.get_display_clock_speed =
14722 gm45_get_display_clock_speed;
14723 else if (IS_CRESTLINE(dev))
14724 dev_priv->display.get_display_clock_speed =
14725 i965gm_get_display_clock_speed;
14726 else if (IS_PINEVIEW(dev))
14727 dev_priv->display.get_display_clock_speed =
14728 pnv_get_display_clock_speed;
14729 else if (IS_G33(dev) || IS_G4X(dev))
14730 dev_priv->display.get_display_clock_speed =
14731 g33_get_display_clock_speed;
e70236a8
JB		 14732 else if (IS_I915G(dev))
14733 dev_priv->display.get_display_clock_speed =
14734 i915_get_display_clock_speed;
257a7ffc 14735 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14736 dev_priv->display.get_display_clock_speed =
14737 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14738 else if (IS_PINEVIEW(dev))
14739 dev_priv->display.get_display_clock_speed =
14740 pnv_get_display_clock_speed;
e70236a8
JB		 14741 else if (IS_I915GM(dev))
14742 dev_priv->display.get_display_clock_speed =
14743 i915gm_get_display_clock_speed;
14744 else if (IS_I865G(dev))
14745 dev_priv->display.get_display_clock_speed =
14746 i865_get_display_clock_speed;
f0f8a9ce 14747 else if (IS_I85X(dev))
e70236a8 14748 dev_priv->display.get_display_clock_speed =
1b1d2716 14749 i85x_get_display_clock_speed;
623e01e5
VS		 14750 else { /* 830 */
14751 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14752 dev_priv->display.get_display_clock_speed =
14753 i830_get_display_clock_speed;
623e01e5 14754 }
e70236a8 14755
7c10a2b5 14756 if (IS_GEN5(dev)) {
3bb11b53 14757 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14758 } else if (IS_GEN6(dev)) {
14759 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14760 } else if (IS_IVYBRIDGE(dev)) {
14761 /* FIXME: detect B0+ stepping and use auto training */
14762 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14763 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14764 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14765 if (IS_BROADWELL(dev))
14766 dev_priv->display.modeset_global_resources =
14767 broadwell_modeset_global_resources;
30a970c6
JB		 14768 } else if (IS_VALLEYVIEW(dev)) {
14769 dev_priv->display.modeset_global_resources =
14770 valleyview_modeset_global_resources;
f8437dd1
VK		 14771 } else if (IS_BROXTON(dev)) {
14772 dev_priv->display.modeset_global_resources =
14773 broxton_modeset_global_resources;
e70236a8 14774 }
8c9f3aaf 14775
8c9f3aaf
JB		 14776 switch (INTEL_INFO(dev)->gen) {
14777 case 2:
14778 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14779 break;
14780
14781 case 3:
14782 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14783 break;
14784
14785 case 4:
14786 case 5:
14787 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14788 break;
14789
14790 case 6:
14791 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14792 break;
7c9017e5 14793 case 7:
4e0bbc31 14794 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14795 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14796 break;
830c81db 14797 case 9:
ba343e02
TU		 14798 /* Drop through - unsupported since execlist only. */
14799 default:
14800 /* Default just returns -ENODEV to indicate unsupported */
14801 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14802 }
7bd688cd
JN		 14803
14804 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14805
14806 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14807}
14808
b690e96c
JB		 14809/*
14810 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14811 * resume, or other times. This quirk makes sure that's the case for
14812 * affected systems.
14813 */
0206e353 14814static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14815{
14816 struct drm_i915_private *dev_priv = dev->dev_private;
14817
14818 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14819 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14820}
14821
b6b5d049
VS		 14822static void quirk_pipeb_force(struct drm_device *dev)
14823{
14824 struct drm_i915_private *dev_priv = dev->dev_private;
14825
14826 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14827 DRM_INFO("applying pipe b force quirk\n");
14828}
14829
435793df
KP		 14830/*
14831 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14832 */
14833static void quirk_ssc_force_disable(struct drm_device *dev)
14834{
14835 struct drm_i915_private *dev_priv = dev->dev_private;
14836 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14837 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14838}
14839
4dca20ef 14840/*
5a15ab5b
CE		 14841 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14842 * brightness value
4dca20ef
CE		 14843 */
14844static void quirk_invert_brightness(struct drm_device *dev)
14845{
14846 struct drm_i915_private *dev_priv = dev->dev_private;
14847 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14848 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14849}
14850
9c72cc6f
SD		 14851/* Some VBT's incorrectly indicate no backlight is present */
14852static void quirk_backlight_present(struct drm_device *dev)
14853{
14854 struct drm_i915_private *dev_priv = dev->dev_private;
14855 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14856 DRM_INFO("applying backlight present quirk\n");
14857}
14858
b690e96c
JB		 14859struct intel_quirk {
14860 int device;
14861 int subsystem_vendor;
14862 int subsystem_device;
14863 void (*hook)(struct drm_device *dev);
14864};
14865
5f85f176
EE		 14866/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14867struct intel_dmi_quirk {
14868 void (*hook)(struct drm_device *dev);
14869 const struct dmi_system_id (*dmi_id_list)[];
14870};
14871
14872static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14873{
14874 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14875 return 1;
14876}
14877
14878static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14879 {
14880 .dmi_id_list = &(const struct dmi_system_id[]) {
14881 {
14882 .callback = intel_dmi_reverse_brightness,
14883 .ident = "NCR Corporation",
14884 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14885 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14886 },
14887 },
14888 { } /* terminating entry */
14889 },
14890 .hook = quirk_invert_brightness,
14891 },
14892};
14893
c43b5634 14894static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14895 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14896 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14897
b690e96c
JB		 14898 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14899 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14900
5f080c0f
VS		 14901 /* 830 needs to leave pipe A & dpll A up */
14902 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14903
b6b5d049
VS		 14904 /* 830 needs to leave pipe B & dpll B up */
14905 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14906
435793df
KP		 14907 /* Lenovo U160 cannot use SSC on LVDS */
14908 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14909
14910 /* Sony Vaio Y cannot use SSC on LVDS */
14911 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14912
be505f64
AH		 14913 /* Acer Aspire 5734Z must invert backlight brightness */
14914 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14915
14916 /* Acer/eMachines G725 */
14917 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14918
14919 /* Acer/eMachines e725 */
14920 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14921
14922 /* Acer/Packard Bell NCL20 */
14923 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14924
14925 /* Acer Aspire 4736Z */
14926 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14927
14928 /* Acer Aspire 5336 */
14929 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14930
14931 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14932 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14933
dfb3d47b
SD		 14934 /* Acer C720 Chromebook (Core i3 4005U) */
14935 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14936
b2a9601c 14937 /* Apple Macbook 2,1 (Core 2 T7400) */
14938 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14939
d4967d8c
SD		 14940 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14941 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14942
14943 /* HP Chromebook 14 (Celeron 2955U) */
14944 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14945
14946 /* Dell Chromebook 11 */
14947 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14948};
14949
14950static void intel_init_quirks(struct drm_device *dev)
14951{
14952 struct pci_dev *d = dev->pdev;
14953 int i;
14954
14955 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14956 struct intel_quirk *q = &intel_quirks[i];
14957
14958 if (d->device == q->device &&
14959 (d->subsystem_vendor == q->subsystem_vendor ||
14960 q->subsystem_vendor == PCI_ANY_ID) &&
14961 (d->subsystem_device == q->subsystem_device ||
14962 q->subsystem_device == PCI_ANY_ID))
14963 q->hook(dev);
14964 }
5f85f176
EE		 14965 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14966 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14967 intel_dmi_quirks[i].hook(dev);
14968 }
b690e96c
JB		 14969}
14970
9cce37f4
JB		 14971/* Disable the VGA plane that we never use */
14972static void i915_disable_vga(struct drm_device *dev)
14973{
14974 struct drm_i915_private *dev_priv = dev->dev_private;
14975 u8 sr1;
766aa1c4 14976 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14977
2b37c616 14978 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14979 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14980 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14981 sr1 = inb(VGA_SR_DATA);
14982 outb(sr1 | 1<<5, VGA_SR_DATA);
14983 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14984 udelay(300);
14985
01f5a626 14986 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14987 POSTING_READ(vga_reg);
14988}
14989
f817586c
DV		 14990void intel_modeset_init_hw(struct drm_device *dev)
14991{
b6283055 14992 intel_update_cdclk(dev);
a8f78b58 14993 intel_prepare_ddi(dev);
f817586c 14994 intel_init_clock_gating(dev);
8090c6b9 14995 intel_enable_gt_powersave(dev);
f817586c
DV		 14996}
14997
79e53945
JB		 14998void intel_modeset_init(struct drm_device *dev)
14999{
652c393a 15000 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15001 int sprite, ret;
8cc87b75 15002 enum pipe pipe;
46f297fb 15003 struct intel_crtc *crtc;
79e53945
JB		 15004
15005 drm_mode_config_init(dev);
15006
15007 dev->mode_config.min_width = 0;
15008 dev->mode_config.min_height = 0;
15009
019d96cb
DA		 15010 dev->mode_config.preferred_depth = 24;
15011 dev->mode_config.prefer_shadow = 1;
15012
25bab385
TU		 15013 dev->mode_config.allow_fb_modifiers = true;
15014
e6ecefaa 15015 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15016
b690e96c
JB		 15017 intel_init_quirks(dev);
15018
1fa61106
ED		 15019 intel_init_pm(dev);
15020
e3c74757
BW		 15021 if (INTEL_INFO(dev)->num_pipes == 0)
15022 return;
15023
e70236a8 15024 intel_init_display(dev);
7c10a2b5 15025 intel_init_audio(dev);
e70236a8 15026
a6c45cf0
CW		 15027 if (IS_GEN2(dev)) {
15028 dev->mode_config.max_width = 2048;
15029 dev->mode_config.max_height = 2048;
15030 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15031 dev->mode_config.max_width = 4096;
15032 dev->mode_config.max_height = 4096;
79e53945 15033 } else {
a6c45cf0
CW		 15034 dev->mode_config.max_width = 8192;
15035 dev->mode_config.max_height = 8192;
79e53945 15036 }
068be561 15037
dc41c154
VS		 15038 if (IS_845G(dev) || IS_I865G(dev)) {
15039 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15040 dev->mode_config.cursor_height = 1023;
15041 } else if (IS_GEN2(dev)) {
068be561
DL		 15042 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15043 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15044 } else {
15045 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15046 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15047 }
15048
5d4545ae 15049 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15050
28c97730 15051 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15052 INTEL_INFO(dev)->num_pipes,
15053 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15054
055e393f 15055 for_each_pipe(dev_priv, pipe) {
8cc87b75 15056 intel_crtc_init(dev, pipe);
3bdcfc0c 15057 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15058 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15059 if (ret)
06da8da2 15060 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15061 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15062 }
79e53945
JB		 15063 }
15064
f42bb70d
JB		 15065 intel_init_dpio(dev);
15066
e72f9fbf 15067 intel_shared_dpll_init(dev);
ee7b9f93 15068
9cce37f4
JB		 15069 /* Just disable it once at startup */
15070 i915_disable_vga(dev);
79e53945 15071 intel_setup_outputs(dev);
11be49eb
CW		 15072
15073 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15074 intel_fbc_disable(dev);
fa9fa083 15075
6e9f798d 15076 drm_modeset_lock_all(dev);
fa9fa083 15077 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15078 drm_modeset_unlock_all(dev);
46f297fb 15079
d3fcc808 15080 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15081 if (!crtc->active)
15082 continue;
15083
46f297fb 15084 /*
46f297fb
JB		 15085 * Note that reserving the BIOS fb up front prevents us
15086 * from stuffing other stolen allocations like the ring
15087 * on top. This prevents some ugliness at boot time, and
15088 * can even allow for smooth boot transitions if the BIOS
15089 * fb is large enough for the active pipe configuration.
15090 */
5724dbd1
DL		 15091 if (dev_priv->display.get_initial_plane_config) {
15092 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15093 &crtc->plane_config);
15094 /*
15095 * If the fb is shared between multiple heads, we'll
15096 * just get the first one.
15097 */
f6936e29 15098 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15099 }
46f297fb 15100 }
2c7111db
CW		 15101}
15102
7fad798e
DV		 15103static void intel_enable_pipe_a(struct drm_device *dev)
15104{
15105 struct intel_connector *connector;
15106 struct drm_connector *crt = NULL;
15107 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15108 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15109
15110 /* We can't just switch on the pipe A, we need to set things up with a
15111 * proper mode and output configuration. As a gross hack, enable pipe A
15112 * by enabling the load detect pipe once. */
3a3371ff 15113 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15114 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15115 crt = &connector->base;
15116 break;
15117 }
15118 }
15119
15120 if (!crt)
15121 return;
15122
208bf9fd 15123 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15124 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15125}
15126
fa555837
DV		 15127static bool
15128intel_check_plane_mapping(struct intel_crtc *crtc)
15129{
7eb552ae
BW		 15130 struct drm_device *dev = crtc->base.dev;
15131 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15132 u32 reg, val;
15133
7eb552ae 15134 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15135 return true;
15136
15137 reg = DSPCNTR(!crtc->plane);
15138 val = I915_READ(reg);
15139
15140 if ((val & DISPLAY_PLANE_ENABLE) &&
15141 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15142 return false;
15143
15144 return true;
15145}
15146
24929352
DV		 15147static void intel_sanitize_crtc(struct intel_crtc *crtc)
15148{
15149 struct drm_device *dev = crtc->base.dev;
15150 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15151 u32 reg;
24929352 15152
24929352 15153 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15154 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15155 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15156
d3eaf884 15157 /* restore vblank interrupts to correct state */
9625604c 15158 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15159 if (crtc->active) {
15160 update_scanline_offset(crtc);
9625604c
DV		 15161 drm_crtc_vblank_on(&crtc->base);
15162 }
d3eaf884 15163
24929352 15164 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15165 * disable the crtc (and hence change the state) if it is wrong. Note
15166 * that gen4+ has a fixed plane -> pipe mapping. */
15167 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15168 struct intel_connector *connector;
15169 bool plane;
15170
24929352
DV		 15171 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15172 crtc->base.base.id);
15173
15174 /* Pipe has the wrong plane attached and the plane is active.
15175 * Temporarily change the plane mapping and disable everything
15176 * ... */
15177 plane = crtc->plane;
b70709a6 15178 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15179 crtc->plane = !plane;
1b509259 15180 intel_crtc_control(&crtc->base, false);
24929352
DV		 15181 crtc->plane = plane;
15182
15183 /* ... and break all links. */
3a3371ff 15184 for_each_intel_connector(dev, connector) {
24929352
DV		 15185 if (connector->encoder->base.crtc != &crtc->base)
15186 continue;
15187
7f1950fb
EE		 15188 connector->base.dpms = DRM_MODE_DPMS_OFF;
15189 connector->base.encoder = NULL;
24929352 15190 }
7f1950fb
EE		 15191 /* multiple connectors may have the same encoder:
15192 * handle them and break crtc link separately */
3a3371ff 15193 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15194 if (connector->encoder->base.crtc == &crtc->base) {
15195 connector->encoder->base.crtc = NULL;
15196 connector->encoder->connectors_active = false;
15197 }
24929352
DV		 15198
15199 WARN_ON(crtc->active);
83d65738 15200 crtc->base.state->enable = false;
49d6fa21 15201 crtc->base.state->active = false;
24929352
DV		 15202 crtc->base.enabled = false;
15203 }
24929352 15204
7fad798e
DV		 15205 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15206 crtc->pipe == PIPE_A && !crtc->active) {
15207 /* BIOS forgot to enable pipe A, this mostly happens after
15208 * resume. Force-enable the pipe to fix this, the update_dpms
15209 * call below we restore the pipe to the right state, but leave
15210 * the required bits on. */
15211 intel_enable_pipe_a(dev);
15212 }
15213
24929352
DV		 15214 /* Adjust the state of the output pipe according to whether we
15215 * have active connectors/encoders. */
15216 intel_crtc_update_dpms(&crtc->base);
15217
83d65738 15218 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15219 struct intel_encoder *encoder;
15220
15221 /* This can happen either due to bugs in the get_hw_state
15222 * functions or because the pipe is force-enabled due to the
15223 * pipe A quirk. */
15224 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15225 crtc->base.base.id,
83d65738 15226 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15227 crtc->active ? "enabled" : "disabled");
15228
83d65738 15229 crtc->base.state->enable = crtc->active;
49d6fa21 15230 crtc->base.state->active = crtc->active;
24929352
DV		 15231 crtc->base.enabled = crtc->active;
15232
15233 /* Because we only establish the connector -> encoder ->
15234 * crtc links if something is active, this means the
15235 * crtc is now deactivated. Break the links. connector
15236 * -> encoder links are only establish when things are
15237 * actually up, hence no need to break them. */
15238 WARN_ON(crtc->active);
15239
15240 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15241 WARN_ON(encoder->connectors_active);
15242 encoder->base.crtc = NULL;
15243 }
15244 }
c5ab3bc0 15245
a3ed6aad 15246 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15247 /*
15248 * We start out with underrun reporting disabled to avoid races.
15249 * For correct bookkeeping mark this on active crtcs.
15250 *
c5ab3bc0
DV		 15251 * Also on gmch platforms we dont have any hardware bits to
15252 * disable the underrun reporting. Which means we need to start
15253 * out with underrun reporting disabled also on inactive pipes,
15254 * since otherwise we'll complain about the garbage we read when
15255 * e.g. coming up after runtime pm.
15256 *
4cc31489
DV		 15257 * No protection against concurrent access is required - at
15258 * worst a fifo underrun happens which also sets this to false.
15259 */
15260 crtc->cpu_fifo_underrun_disabled = true;
15261 crtc->pch_fifo_underrun_disabled = true;
15262 }
24929352
DV		 15263}
15264
15265static void intel_sanitize_encoder(struct intel_encoder *encoder)
15266{
15267 struct intel_connector *connector;
15268 struct drm_device *dev = encoder->base.dev;
15269
15270 /* We need to check both for a crtc link (meaning that the
15271 * encoder is active and trying to read from a pipe) and the
15272 * pipe itself being active. */
15273 bool has_active_crtc = encoder->base.crtc &&
15274 to_intel_crtc(encoder->base.crtc)->active;
15275
15276 if (encoder->connectors_active && !has_active_crtc) {
15277 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15278 encoder->base.base.id,
8e329a03 15279 encoder->base.name);
24929352
DV		 15280
15281 /* Connector is active, but has no active pipe. This is
15282 * fallout from our resume register restoring. Disable
15283 * the encoder manually again. */
15284 if (encoder->base.crtc) {
15285 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15286 encoder->base.base.id,
8e329a03 15287 encoder->base.name);
24929352 15288 encoder->disable(encoder);
a62d1497
VS		 15289 if (encoder->post_disable)
15290 encoder->post_disable(encoder);
24929352 15291 }
7f1950fb
EE		 15292 encoder->base.crtc = NULL;
15293 encoder->connectors_active = false;
24929352
DV		 15294
15295 /* Inconsistent output/port/pipe state happens presumably due to
15296 * a bug in one of the get_hw_state functions. Or someplace else
15297 * in our code, like the register restore mess on resume. Clamp
15298 * things to off as a safer default. */
3a3371ff 15299 for_each_intel_connector(dev, connector) {
24929352
DV		 15300 if (connector->encoder != encoder)
15301 continue;
7f1950fb
EE		 15302 connector->base.dpms = DRM_MODE_DPMS_OFF;
15303 connector->base.encoder = NULL;
24929352
DV		 15304 }
15305 }
15306 /* Enabled encoders without active connectors will be fixed in
15307 * the crtc fixup. */
15308}
15309
04098753 15310void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15311{
15312 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15313 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15314
04098753
ID		 15315 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15316 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15317 i915_disable_vga(dev);
15318 }
15319}
15320
15321void i915_redisable_vga(struct drm_device *dev)
15322{
15323 struct drm_i915_private *dev_priv = dev->dev_private;
15324
8dc8a27c
PZ		 15325 /* This function can be called both from intel_modeset_setup_hw_state or
15326 * at a very early point in our resume sequence, where the power well
15327 * structures are not yet restored. Since this function is at a very
15328 * paranoid "someone might have enabled VGA while we were not looking"
15329 * level, just check if the power well is enabled instead of trying to
15330 * follow the "don't touch the power well if we don't need it" policy
15331 * the rest of the driver uses. */
f458ebbc 15332 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15333 return;
15334
04098753 15335 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15336}
15337
98ec7739
VS		 15338static bool primary_get_hw_state(struct intel_crtc *crtc)
15339{
15340 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15341
15342 if (!crtc->active)
15343 return false;
15344
15345 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15346}
15347
30e984df 15348static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15349{
15350 struct drm_i915_private *dev_priv = dev->dev_private;
15351 enum pipe pipe;
24929352
DV		 15352 struct intel_crtc *crtc;
15353 struct intel_encoder *encoder;
15354 struct intel_connector *connector;
5358901f 15355 int i;
24929352 15356
d3fcc808 15357 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15358 struct drm_plane *primary = crtc->base.primary;
15359 struct intel_plane_state *plane_state;
15360
6e3c9717 15361 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15362
6e3c9717 15363 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15364
0e8ffe1b 15365 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15366 crtc->config);
24929352 15367
83d65738 15368 crtc->base.state->enable = crtc->active;
49d6fa21 15369 crtc->base.state->active = crtc->active;
24929352 15370 crtc->base.enabled = crtc->active;
b70709a6
ML		 15371
15372 plane_state = to_intel_plane_state(primary->state);
15373 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15374
15375 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15376 crtc->base.base.id,
15377 crtc->active ? "enabled" : "disabled");
15378 }
15379
5358901f
DV		 15380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15381 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15382
3e369b76
ACO		 15383 pll->on = pll->get_hw_state(dev_priv, pll,
15384 &pll->config.hw_state);
5358901f 15385 pll->active = 0;
3e369b76 15386 pll->config.crtc_mask = 0;
d3fcc808 15387 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15388 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15389 pll->active++;
3e369b76 15390 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15391 }
5358901f 15392 }
5358901f 15393
1e6f2ddc 15394 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15395 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15396
3e369b76 15397 if (pll->config.crtc_mask)
bd2bb1b9 15398 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15399 }
15400
b2784e15 15401 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15402 pipe = 0;
15403
15404 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15405 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15406 encoder->base.crtc = &crtc->base;
6e3c9717 15407 encoder->get_config(encoder, crtc->config);
24929352
DV		 15408 } else {
15409 encoder->base.crtc = NULL;
15410 }
15411
15412 encoder->connectors_active = false;
6f2bcceb 15413 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15414 encoder->base.base.id,
8e329a03 15415 encoder->base.name,
24929352 15416 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15417 pipe_name(pipe));
24929352
DV		 15418 }
15419
3a3371ff 15420 for_each_intel_connector(dev, connector) {
24929352
DV		 15421 if (connector->get_hw_state(connector)) {
15422 connector->base.dpms = DRM_MODE_DPMS_ON;
15423 connector->encoder->connectors_active = true;
15424 connector->base.encoder = &connector->encoder->base;
15425 } else {
15426 connector->base.dpms = DRM_MODE_DPMS_OFF;
15427 connector->base.encoder = NULL;
15428 }
15429 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15430 connector->base.base.id,
c23cc417 15431 connector->base.name,
24929352
DV		 15432 connector->base.encoder ? "enabled" : "disabled");
15433 }
30e984df
DV		 15434}
15435
15436/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15437 * and i915 state tracking structures. */
15438void intel_modeset_setup_hw_state(struct drm_device *dev,
15439 bool force_restore)
15440{
15441 struct drm_i915_private *dev_priv = dev->dev_private;
15442 enum pipe pipe;
30e984df
DV		 15443 struct intel_crtc *crtc;
15444 struct intel_encoder *encoder;
35c95375 15445 int i;
30e984df
DV		 15446
15447 intel_modeset_readout_hw_state(dev);
24929352 15448
babea61d
JB		 15449 /*
15450 * Now that we have the config, copy it to each CRTC struct
15451 * Note that this could go away if we move to using crtc_config
15452 * checking everywhere.
15453 */
d3fcc808 15454 for_each_intel_crtc(dev, crtc) {
d330a953 15455 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15456 intel_mode_from_pipe_config(&crtc->base.mode,
15457 crtc->config);
babea61d
JB		 15458 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15459 crtc->base.base.id);
15460 drm_mode_debug_printmodeline(&crtc->base.mode);
15461 }
15462 }
15463
24929352 15464 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15465 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15466 intel_sanitize_encoder(encoder);
15467 }
15468
055e393f 15469 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15470 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15471 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15472 intel_dump_pipe_config(crtc, crtc->config,
15473 "[setup_hw_state]");
24929352 15474 }
9a935856 15475
d29b2f9d
ACO		 15476 intel_modeset_update_connector_atomic_state(dev);
15477
35c95375
DV		 15478 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15479 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15480
15481 if (!pll->on || pll->active)
15482 continue;
15483
15484 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15485
15486 pll->disable(dev_priv, pll);
15487 pll->on = false;
15488 }
15489
3078999f
PB		 15490 if (IS_GEN9(dev))
15491 skl_wm_get_hw_state(dev);
15492 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15493 ilk_wm_get_hw_state(dev);
15494
45e2b5f6 15495 if (force_restore) {
7d0bc1ea
VS		 15496 i915_redisable_vga(dev);
15497
f30da187
DV		 15498 /*
15499 * We need to use raw interfaces for restoring state to avoid
15500 * checking (bogus) intermediate states.
15501 */
055e393f 15502 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15503 struct drm_crtc *crtc =
15504 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15505
83a57153 15506 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15507 }
15508 } else {
15509 intel_modeset_update_staged_output_state(dev);
15510 }
8af6cf88
DV		 15511
15512 intel_modeset_check_state(dev);
2c7111db
CW		 15513}
15514
15515void intel_modeset_gem_init(struct drm_device *dev)
15516{
92122789 15517 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15518 struct drm_crtc *c;
2ff8fde1 15519 struct drm_i915_gem_object *obj;
e0d6149b 15520 int ret;
484b41dd 15521
ae48434c
ID		 15522 mutex_lock(&dev->struct_mutex);
15523 intel_init_gt_powersave(dev);
15524 mutex_unlock(&dev->struct_mutex);
15525
92122789
JB		 15526 /*
15527 * There may be no VBT; and if the BIOS enabled SSC we can
15528 * just keep using it to avoid unnecessary flicker. Whereas if the
15529 * BIOS isn't using it, don't assume it will work even if the VBT
15530 * indicates as much.
15531 */
15532 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15533 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15534 DREF_SSC1_ENABLE);
15535
1833b134 15536 intel_modeset_init_hw(dev);
02e792fb
DV		 15537
15538 intel_setup_overlay(dev);
484b41dd
JB		 15539
15540 /*
15541 * Make sure any fbs we allocated at startup are properly
15542 * pinned & fenced. When we do the allocation it's too early
15543 * for this.
15544 */
70e1e0ec 15545 for_each_crtc(dev, c) {
2ff8fde1
MR		 15546 obj = intel_fb_obj(c->primary->fb);
15547 if (obj == NULL)
484b41dd
JB		 15548 continue;
15549
e0d6149b
TU		 15550 mutex_lock(&dev->struct_mutex);
15551 ret = intel_pin_and_fence_fb_obj(c->primary,
15552 c->primary->fb,
15553 c->primary->state,
15554 NULL);
15555 mutex_unlock(&dev->struct_mutex);
15556 if (ret) {
484b41dd
JB		 15557 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15558 to_intel_crtc(c)->pipe);
66e514c1
DA		 15559 drm_framebuffer_unreference(c->primary->fb);
15560 c->primary->fb = NULL;
afd65eb4 15561 update_state_fb(c->primary);
484b41dd
JB		 15562 }
15563 }
0962c3c9
VS		 15564
15565 intel_backlight_register(dev);
79e53945
JB		 15566}
15567
4932e2c3
ID		 15568void intel_connector_unregister(struct intel_connector *intel_connector)
15569{
15570 struct drm_connector *connector = &intel_connector->base;
15571
15572 intel_panel_destroy_backlight(connector);
34ea3d38 15573 drm_connector_unregister(connector);
4932e2c3
ID		 15574}
15575
79e53945
JB		 15576void intel_modeset_cleanup(struct drm_device *dev)
15577{
652c393a 15578 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15579 struct drm_connector *connector;
652c393a 15580
2eb5252e
ID		 15581 intel_disable_gt_powersave(dev);
15582
0962c3c9
VS		 15583 intel_backlight_unregister(dev);
15584
fd0c0642
DV		 15585 /*
15586 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15587 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15588 * experience fancy races otherwise.
15589 */
2aeb7d3a 15590 intel_irq_uninstall(dev_priv);
eb21b92b 15591
fd0c0642
DV		 15592 /*
15593 * Due to the hpd irq storm handling the hotplug work can re-arm the
15594 * poll handlers. Hence disable polling after hpd handling is shut down.
15595 */
f87ea761 15596 drm_kms_helper_poll_fini(dev);
fd0c0642 15597
652c393a
JB		 15598 mutex_lock(&dev->struct_mutex);
15599
723bfd70
JB		 15600 intel_unregister_dsm_handler();
15601
7ff0ebcc 15602 intel_fbc_disable(dev);
e70236a8 15603
69341a5e
KH		 15604 mutex_unlock(&dev->struct_mutex);
15605
1630fe75
CW		 15606 /* flush any delayed tasks or pending work */
15607 flush_scheduled_work();
15608
db31af1d
JN		 15609 /* destroy the backlight and sysfs files before encoders/connectors */
15610 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15611 struct intel_connector *intel_connector;
15612
15613 intel_connector = to_intel_connector(connector);
15614 intel_connector->unregister(intel_connector);
db31af1d 15615 }
d9255d57 15616
79e53945 15617 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15618
15619 intel_cleanup_overlay(dev);
ae48434c
ID		 15620
15621 mutex_lock(&dev->struct_mutex);
15622 intel_cleanup_gt_powersave(dev);
15623 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15624}
15625
f1c79df3
ZW		 15626/*
15627 * Return which encoder is currently attached for connector.
15628 */
df0e9248 15629struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15630{
df0e9248
CW		 15631 return &intel_attached_encoder(connector)->base;
15632}
f1c79df3 15633
df0e9248
CW		 15634void intel_connector_attach_encoder(struct intel_connector *connector,
15635 struct intel_encoder *encoder)
15636{
15637 connector->encoder = encoder;
15638 drm_mode_connector_attach_encoder(&connector->base,
15639 &encoder->base);
79e53945 15640}
28d52043
DA		 15641
15642/*
15643 * set vga decode state - true == enable VGA decode
15644 */
15645int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15646{
15647 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15648 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15649 u16 gmch_ctrl;
15650
75fa041d
CW		 15651 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15652 DRM_ERROR("failed to read control word\n");
15653 return -EIO;
15654 }
15655
c0cc8a55
CW		 15656 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15657 return 0;
15658
28d52043
DA		 15659 if (state)
15660 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15661 else
15662 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15663
15664 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15665 DRM_ERROR("failed to write control word\n");
15666 return -EIO;
15667 }
15668
28d52043
DA		 15669 return 0;
15670}
c4a1d9e4 15671
c4a1d9e4 15672struct intel_display_error_state {
ff57f1b0
PZ		 15673
15674 u32 power_well_driver;
15675
63b66e5b
CW		 15676 int num_transcoders;
15677
c4a1d9e4
CW		 15678 struct intel_cursor_error_state {
15679 u32 control;
15680 u32 position;
15681 u32 base;
15682 u32 size;
52331309 15683 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15684
15685 struct intel_pipe_error_state {
ddf9c536 15686 bool power_domain_on;
c4a1d9e4 15687 u32 source;
f301b1e1 15688 u32 stat;
52331309 15689 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15690
15691 struct intel_plane_error_state {
15692 u32 control;
15693 u32 stride;
15694 u32 size;
15695 u32 pos;
15696 u32 addr;
15697 u32 surface;
15698 u32 tile_offset;
52331309 15699 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15700
15701 struct intel_transcoder_error_state {
ddf9c536 15702 bool power_domain_on;
63b66e5b
CW		 15703 enum transcoder cpu_transcoder;
15704
15705 u32 conf;
15706
15707 u32 htotal;
15708 u32 hblank;
15709 u32 hsync;
15710 u32 vtotal;
15711 u32 vblank;
15712 u32 vsync;
15713 } transcoder[4];
c4a1d9e4
CW		 15714};
15715
15716struct intel_display_error_state *
15717intel_display_capture_error_state(struct drm_device *dev)
15718{
fbee40df 15719 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15720 struct intel_display_error_state *error;
63b66e5b
CW		 15721 int transcoders[] = {
15722 TRANSCODER_A,
15723 TRANSCODER_B,
15724 TRANSCODER_C,
15725 TRANSCODER_EDP,
15726 };
c4a1d9e4
CW		 15727 int i;
15728
63b66e5b
CW		 15729 if (INTEL_INFO(dev)->num_pipes == 0)
15730 return NULL;
15731
9d1cb914 15732 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15733 if (error == NULL)
15734 return NULL;
15735
190be112 15736 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15737 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15738
055e393f 15739 for_each_pipe(dev_priv, i) {
ddf9c536 15740 error->pipe[i].power_domain_on =
f458ebbc
DV		 15741 __intel_display_power_is_enabled(dev_priv,
15742 POWER_DOMAIN_PIPE(i));
ddf9c536 15743 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15744 continue;
15745
5efb3e28
VS		 15746 error->cursor[i].control = I915_READ(CURCNTR(i));
15747 error->cursor[i].position = I915_READ(CURPOS(i));
15748 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15749
15750 error->plane[i].control = I915_READ(DSPCNTR(i));
15751 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15752 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15753 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15754 error->plane[i].pos = I915_READ(DSPPOS(i));
15755 }
ca291363
PZ		 15756 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15757 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15758 if (INTEL_INFO(dev)->gen >= 4) {
15759 error->plane[i].surface = I915_READ(DSPSURF(i));
15760 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15761 }
15762
c4a1d9e4 15763 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15764
3abfce77 15765 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15766 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15767 }
15768
15769 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15770 if (HAS_DDI(dev_priv->dev))
15771 error->num_transcoders++; /* Account for eDP. */
15772
15773 for (i = 0; i < error->num_transcoders; i++) {
15774 enum transcoder cpu_transcoder = transcoders[i];
15775
ddf9c536 15776 error->transcoder[i].power_domain_on =
f458ebbc 15777 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15778 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15779 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15780 continue;
15781
63b66e5b
CW		 15782 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15783
15784 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15785 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15786 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15787 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15788 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15789 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15790 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15791 }
15792
15793 return error;
15794}
15795
edc3d884
MK		 15796#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15797
c4a1d9e4 15798void
edc3d884 15799intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15800 struct drm_device *dev,
15801 struct intel_display_error_state *error)
15802{
055e393f 15803 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15804 int i;
15805
63b66e5b
CW		 15806 if (!error)
15807 return;
15808
edc3d884 15809 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15810 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15811 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15812 error->power_well_driver);
055e393f 15813 for_each_pipe(dev_priv, i) {
edc3d884 15814 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15815 err_printf(m, " Power: %s\n",
15816 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15817 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15818 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15819
15820 err_printf(m, "Plane [%d]:\n", i);
15821 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15822 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15823 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15824 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15825 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15826 }
4b71a570 15827 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15828 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15829 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15830 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15831 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15832 }
15833
edc3d884
MK		 15834 err_printf(m, "Cursor [%d]:\n", i);
15835 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15836 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15837 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15838 }
63b66e5b
CW		 15839
15840 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15841 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15842 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15843 err_printf(m, " Power: %s\n",
15844 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15845 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15846 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15847 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15848 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15849 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15850 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15851 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15852 }
c4a1d9e4 15853}
e2fcdaa9
VS		 15854
15855void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15856{
15857 struct intel_crtc *crtc;
15858
15859 for_each_intel_crtc(dev, crtc) {
15860 struct intel_unpin_work *work;
e2fcdaa9 15861
5e2d7afc 15862 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15863
15864 work = crtc->unpin_work;
15865
15866 if (work && work->event &&
15867 work->event->base.file_priv == file) {
15868 kfree(work->event);
15869 work->event = NULL;
15870 }
15871
5e2d7afc 15872 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15873 }
15874}
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