]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_display.c
Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB
28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH
42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR
44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR
54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR
75};
76
3d7d6510
MR
77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
eb1bfe80
JB
89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
5b18e57c
DV
93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
29407aab 98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV
99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 101static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
d288f65f 103static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
613d2b27
ML
105static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK
107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID
109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
043e9bda 111static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB
115} intel_range_t;
116
117typedef struct {
0206e353
AJ
118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB
120} intel_p2_t;
121
d4906093
ML
122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV
128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
79e50a4f
JN
138/* hrawclock is 1/4 the FSB frequency */
139int intel_hrawclk(struct drm_device *dev)
140{
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 uint32_t clkcfg;
143
144 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
145 if (IS_VALLEYVIEW(dev))
146 return 200;
147
148 clkcfg = I915_READ(CLKCFG);
149 switch (clkcfg & CLKCFG_FSB_MASK) {
150 case CLKCFG_FSB_400:
151 return 100;
152 case CLKCFG_FSB_533:
153 return 133;
154 case CLKCFG_FSB_667:
155 return 166;
156 case CLKCFG_FSB_800:
157 return 200;
158 case CLKCFG_FSB_1067:
159 return 266;
160 case CLKCFG_FSB_1333:
161 return 333;
162 /* these two are just a guess; one of them might be right */
163 case CLKCFG_FSB_1600:
164 case CLKCFG_FSB_1600_ALT:
165 return 400;
166 default:
167 return 133;
168 }
169}
170
021357ac
CW
171static inline u32 /* units of 100MHz */
172intel_fdi_link_freq(struct drm_device *dev)
173{
8b99e68c
CW
174 if (IS_GEN5(dev)) {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
177 } else
178 return 27;
021357ac
CW
179}
180
5d536e28 181static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 182 .dot = { .min = 25000, .max = 350000 },
9c333719 183 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 184 .n = { .min = 2, .max = 16 },
0206e353
AJ
185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 2, .max = 33 },
273e27ca
EA
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP
192};
193
5d536e28
DV
194static const intel_limit_t intel_limits_i8xx_dvo = {
195 .dot = { .min = 25000, .max = 350000 },
9c333719 196 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 197 .n = { .min = 2, .max = 16 },
5d536e28
DV
198 .m = { .min = 96, .max = 140 },
199 .m1 = { .min = 18, .max = 26 },
200 .m2 = { .min = 6, .max = 16 },
201 .p = { .min = 4, .max = 128 },
202 .p1 = { .min = 2, .max = 33 },
203 .p2 = { .dot_limit = 165000,
204 .p2_slow = 4, .p2_fast = 4 },
205};
206
e4b36699 207static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 208 .dot = { .min = 25000, .max = 350000 },
9c333719 209 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 210 .n = { .min = 2, .max = 16 },
0206e353
AJ
211 .m = { .min = 96, .max = 140 },
212 .m1 = { .min = 18, .max = 26 },
213 .m2 = { .min = 6, .max = 16 },
214 .p = { .min = 4, .max = 128 },
215 .p1 = { .min = 1, .max = 6 },
273e27ca
EA
216 .p2 = { .dot_limit = 165000,
217 .p2_slow = 14, .p2_fast = 7 },
e4b36699 218};
273e27ca 219
e4b36699 220static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ
221 .dot = { .min = 20000, .max = 400000 },
222 .vco = { .min = 1400000, .max = 2800000 },
223 .n = { .min = 1, .max = 6 },
224 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ
225 .m1 = { .min = 8, .max = 18 },
226 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
229 .p2 = { .dot_limit = 200000,
230 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
231};
232
233static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ
234 .dot = { .min = 20000, .max = 400000 },
235 .vco = { .min = 1400000, .max = 2800000 },
236 .n = { .min = 1, .max = 6 },
237 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ
238 .m1 = { .min = 8, .max = 18 },
239 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
240 .p = { .min = 7, .max = 98 },
241 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
242 .p2 = { .dot_limit = 112000,
243 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP
244};
245
273e27ca 246
e4b36699 247static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA
248 .dot = { .min = 25000, .max = 270000 },
249 .vco = { .min = 1750000, .max = 3500000},
250 .n = { .min = 1, .max = 4 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 10, .max = 30 },
255 .p1 = { .min = 1, .max = 3},
256 .p2 = { .dot_limit = 270000,
257 .p2_slow = 10,
258 .p2_fast = 10
044c7c41 259 },
e4b36699
KP
260};
261
262static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA
263 .dot = { .min = 22000, .max = 400000 },
264 .vco = { .min = 1750000, .max = 3500000},
265 .n = { .min = 1, .max = 4 },
266 .m = { .min = 104, .max = 138 },
267 .m1 = { .min = 16, .max = 23 },
268 .m2 = { .min = 5, .max = 11 },
269 .p = { .min = 5, .max = 80 },
270 .p1 = { .min = 1, .max = 8},
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
273};
274
275static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA
276 .dot = { .min = 20000, .max = 115000 },
277 .vco = { .min = 1750000, .max = 3500000 },
278 .n = { .min = 1, .max = 3 },
279 .m = { .min = 104, .max = 138 },
280 .m1 = { .min = 17, .max = 23 },
281 .m2 = { .min = 5, .max = 11 },
282 .p = { .min = 28, .max = 112 },
283 .p1 = { .min = 2, .max = 8 },
284 .p2 = { .dot_limit = 0,
285 .p2_slow = 14, .p2_fast = 14
044c7c41 286 },
e4b36699
KP
287};
288
289static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA
290 .dot = { .min = 80000, .max = 224000 },
291 .vco = { .min = 1750000, .max = 3500000 },
292 .n = { .min = 1, .max = 3 },
293 .m = { .min = 104, .max = 138 },
294 .m1 = { .min = 17, .max = 23 },
295 .m2 = { .min = 5, .max = 11 },
296 .p = { .min = 14, .max = 42 },
297 .p1 = { .min = 2, .max = 6 },
298 .p2 = { .dot_limit = 0,
299 .p2_slow = 7, .p2_fast = 7
044c7c41 300 },
e4b36699
KP
301};
302
f2b115e6 303static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ
304 .dot = { .min = 20000, .max = 400000},
305 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 306 /* Pineview's Ncounter is a ring counter */
0206e353
AJ
307 .n = { .min = 3, .max = 6 },
308 .m = { .min = 2, .max = 256 },
273e27ca 309 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ
310 .m1 = { .min = 0, .max = 0 },
311 .m2 = { .min = 0, .max = 254 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
314 .p2 = { .dot_limit = 200000,
315 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
316};
317
f2b115e6 318static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ
319 .dot = { .min = 20000, .max = 400000 },
320 .vco = { .min = 1700000, .max = 3500000 },
321 .n = { .min = 3, .max = 6 },
322 .m = { .min = 2, .max = 256 },
323 .m1 = { .min = 0, .max = 0 },
324 .m2 = { .min = 0, .max = 254 },
325 .p = { .min = 7, .max = 112 },
326 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
327 .p2 = { .dot_limit = 112000,
328 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP
329};
330
273e27ca
EA
331/* Ironlake / Sandybridge
332 *
333 * We calculate clock using (register_value + 2) for N/M1/M2, so here
334 * the range value for them is (actual_value - 2).
335 */
b91ad0ec 336static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA
337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 5 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 5, .max = 80 },
344 .p1 = { .min = 1, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
347};
348
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 118 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
360};
361
362static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA
363 .dot = { .min = 25000, .max = 350000 },
364 .vco = { .min = 1760000, .max = 3510000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 79, .max = 127 },
367 .m1 = { .min = 12, .max = 22 },
368 .m2 = { .min = 5, .max = 9 },
369 .p = { .min = 14, .max = 56 },
370 .p1 = { .min = 2, .max = 8 },
371 .p2 = { .dot_limit = 225000,
372 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW
373};
374
273e27ca 375/* LVDS 100mhz refclk limits. */
b91ad0ec 376static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA
377 .dot = { .min = 25000, .max = 350000 },
378 .vco = { .min = 1760000, .max = 3510000 },
379 .n = { .min = 1, .max = 2 },
380 .m = { .min = 79, .max = 126 },
381 .m1 = { .min = 12, .max = 22 },
382 .m2 = { .min = 5, .max = 9 },
383 .p = { .min = 28, .max = 112 },
0206e353 384 .p1 = { .min = 2, .max = 8 },
273e27ca
EA
385 .p2 = { .dot_limit = 225000,
386 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
387};
388
389static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA
390 .dot = { .min = 25000, .max = 350000 },
391 .vco = { .min = 1760000, .max = 3510000 },
392 .n = { .min = 1, .max = 3 },
393 .m = { .min = 79, .max = 126 },
394 .m1 = { .min = 12, .max = 22 },
395 .m2 = { .min = 5, .max = 9 },
396 .p = { .min = 14, .max = 42 },
0206e353 397 .p1 = { .min = 2, .max = 6 },
273e27ca
EA
398 .p2 = { .dot_limit = 225000,
399 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY
400};
401
dc730512 402static const intel_limit_t intel_limits_vlv = {
f01b7962
VS
403 /*
404 * These are the data rate limits (measured in fast clocks)
405 * since those are the strictest limits we have. The fast
406 * clock and actual rate limits are more relaxed, so checking
407 * them would make no difference.
408 */
409 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 410 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 411 .n = { .min = 1, .max = 7 },
a0c4da24
JB
412 .m1 = { .min = 2, .max = 3 },
413 .m2 = { .min = 11, .max = 156 },
b99ab663 414 .p1 = { .min = 2, .max = 3 },
5fdc9c49 415 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB
416};
417
ef9348c8
CML
418static const intel_limit_t intel_limits_chv = {
419 /*
420 * These are the data rate limits (measured in fast clocks)
421 * since those are the strictest limits we have. The fast
422 * clock and actual rate limits are more relaxed, so checking
423 * them would make no difference.
424 */
425 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 426 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML
427 .n = { .min = 1, .max = 1 },
428 .m1 = { .min = 2, .max = 2 },
429 .m2 = { .min = 24 << 22, .max = 175 << 22 },
430 .p1 = { .min = 2, .max = 4 },
431 .p2 = { .p2_slow = 1, .p2_fast = 14 },
432};
433
5ab7b0b7
ID
434static const intel_limit_t intel_limits_bxt = {
435 /* FIXME: find real dot limits */
436 .dot = { .min = 0, .max = INT_MAX },
e6292556 437 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID
438 .n = { .min = 1, .max = 1 },
439 .m1 = { .min = 2, .max = 2 },
440 /* FIXME: find real m2 limits */
441 .m2 = { .min = 2 << 22, .max = 255 << 22 },
442 .p1 = { .min = 2, .max = 4 },
443 .p2 = { .p2_slow = 1, .p2_fast = 20 },
444};
445
cdba954e
ACO
446static bool
447needs_modeset(struct drm_crtc_state *state)
448{
fc596660 449 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO
450}
451
e0638cdf
PZ
452/**
453 * Returns whether any output on the specified pipe is of the specified type
454 */
4093561b 455bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 456{
409ee761 457 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ
458 struct intel_encoder *encoder;
459
409ee761 460 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ
461 if (encoder->type == type)
462 return true;
463
464 return false;
465}
466
d0737e1d
ACO
467/**
468 * Returns whether any output on the specified pipe will have the specified
469 * type after a staged modeset is complete, i.e., the same as
470 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
471 * encoder->crtc.
472 */
a93e255f
ACO
473static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
474 int type)
d0737e1d 475{
a93e255f 476 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 477 struct drm_connector *connector;
a93e255f 478 struct drm_connector_state *connector_state;
d0737e1d 479 struct intel_encoder *encoder;
a93e255f
ACO
480 int i, num_connectors = 0;
481
da3ced29 482 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO
483 if (connector_state->crtc != crtc_state->base.crtc)
484 continue;
485
486 num_connectors++;
d0737e1d 487
a93e255f
ACO
488 encoder = to_intel_encoder(connector_state->best_encoder);
489 if (encoder->type == type)
d0737e1d 490 return true;
a93e255f
ACO
491 }
492
493 WARN_ON(num_connectors == 0);
d0737e1d
ACO
494
495 return false;
496}
497
a93e255f
ACO
498static const intel_limit_t *
499intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 500{
a93e255f 501 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 502 const intel_limit_t *limit;
b91ad0ec 503
a93e255f 504 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 505 if (intel_is_dual_link_lvds(dev)) {
1b894b59 506 if (refclk == 100000)
b91ad0ec
ZW
507 limit = &intel_limits_ironlake_dual_lvds_100m;
508 else
509 limit = &intel_limits_ironlake_dual_lvds;
510 } else {
1b894b59 511 if (refclk == 100000)
b91ad0ec
ZW
512 limit = &intel_limits_ironlake_single_lvds_100m;
513 else
514 limit = &intel_limits_ironlake_single_lvds;
515 }
c6bb3538 516 } else
b91ad0ec 517 limit = &intel_limits_ironlake_dac;
2c07245f
ZW
518
519 return limit;
520}
521
a93e255f
ACO
522static const intel_limit_t *
523intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 524{
a93e255f 525 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML
526 const intel_limit_t *limit;
527
a93e255f 528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 529 if (intel_is_dual_link_lvds(dev))
e4b36699 530 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 531 else
e4b36699 532 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO
533 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
534 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 535 limit = &intel_limits_g4x_hdmi;
a93e255f 536 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 537 limit = &intel_limits_g4x_sdvo;
044c7c41 538 } else /* The option is for other outputs */
e4b36699 539 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML
540
541 return limit;
542}
543
a93e255f
ACO
544static const intel_limit_t *
545intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 546{
a93e255f 547 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB
548 const intel_limit_t *limit;
549
5ab7b0b7
ID
550 if (IS_BROXTON(dev))
551 limit = &intel_limits_bxt;
552 else if (HAS_PCH_SPLIT(dev))
a93e255f 553 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 554 else if (IS_G4X(dev)) {
a93e255f 555 limit = intel_g4x_limit(crtc_state);
f2b115e6 556 } else if (IS_PINEVIEW(dev)) {
a93e255f 557 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 558 limit = &intel_limits_pineview_lvds;
2177832f 559 else
f2b115e6 560 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML
561 } else if (IS_CHERRYVIEW(dev)) {
562 limit = &intel_limits_chv;
a0c4da24 563 } else if (IS_VALLEYVIEW(dev)) {
dc730512 564 limit = &intel_limits_vlv;
a6c45cf0 565 } else if (!IS_GEN2(dev)) {
a93e255f 566 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW
567 limit = &intel_limits_i9xx_lvds;
568 else
569 limit = &intel_limits_i9xx_sdvo;
79e53945 570 } else {
a93e255f 571 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 572 limit = &intel_limits_i8xx_lvds;
a93e255f 573 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 574 limit = &intel_limits_i8xx_dvo;
5d536e28
DV
575 else
576 limit = &intel_limits_i8xx_dac;
79e53945
JB
577 }
578 return limit;
579}
580
dccbea3b
ID
581/*
582 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
583 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
584 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
585 * The helpers' return value is the rate of the clock that is fed to the
586 * display engine's pipe which can be the above fast dot clock rate or a
587 * divided-down version of it.
588 */
f2b115e6 589/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 590static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 591{
2177832f
SL
592 clock->m = clock->m2 + 2;
593 clock->p = clock->p1 * clock->p2;
ed5ca77e 594 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 595 return 0;
fb03ac01
VS
596 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
598
599 return clock->dot;
2177832f
SL
600}
601
7429e9d4
DV
602static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
603{
604 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
605}
606
dccbea3b 607static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 608{
7429e9d4 609 clock->m = i9xx_dpll_compute_m(clock);
79e53945 610 clock->p = clock->p1 * clock->p2;
ed5ca77e 611 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 612 return 0;
fb03ac01
VS
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
615
616 return clock->dot;
79e53945
JB
617}
618
dccbea3b 619static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID
620{
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 624 return 0;
589eca67
ID
625 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
626 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
627
628 return clock->dot / 5;
589eca67
ID
629}
630
dccbea3b 631int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML
632{
633 clock->m = clock->m1 * clock->m2;
634 clock->p = clock->p1 * clock->p2;
635 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 636 return 0;
ef9348c8
CML
637 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
638 clock->n << 22);
639 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
640
641 return clock->dot / 5;
ef9348c8
CML
642}
643
7c04d1d9 644#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB
645/**
646 * Returns whether the given set of divisors are valid for a given refclk with
647 * the given connectors.
648 */
649
1b894b59
CW
650static bool intel_PLL_is_valid(struct drm_device *dev,
651 const intel_limit_t *limit,
652 const intel_clock_t *clock)
79e53945 653{
f01b7962
VS
654 if (clock->n < limit->n.min || limit->n.max < clock->n)
655 INTELPllInvalid("n out of range\n");
79e53945 656 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 657 INTELPllInvalid("p1 out of range\n");
79e53945 658 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 659 INTELPllInvalid("m2 out of range\n");
79e53945 660 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 661 INTELPllInvalid("m1 out of range\n");
f01b7962 662
5ab7b0b7 663 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS
664 if (clock->m1 <= clock->m2)
665 INTELPllInvalid("m1 <= m2\n");
666
5ab7b0b7 667 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS
668 if (clock->p < limit->p.min || limit->p.max < clock->p)
669 INTELPllInvalid("p out of range\n");
670 if (clock->m < limit->m.min || limit->m.max < clock->m)
671 INTELPllInvalid("m out of range\n");
672 }
673
79e53945 674 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 675 INTELPllInvalid("vco out of range\n");
79e53945
JB
676 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
677 * connector, etc., rather than just a single range.
678 */
679 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 680 INTELPllInvalid("dot out of range\n");
79e53945
JB
681
682 return true;
683}
684
3b1429d9
VS
685static int
686i9xx_select_p2_div(const intel_limit_t *limit,
687 const struct intel_crtc_state *crtc_state,
688 int target)
79e53945 689{
3b1429d9 690 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 691
a93e255f 692 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 693 /*
a210b028
DV
694 * For LVDS just rely on its current settings for dual-channel.
695 * We haven't figured out how to reliably set up different
696 * single/dual channel state, if we even can.
79e53945 697 */
1974cad0 698 if (intel_is_dual_link_lvds(dev))
3b1429d9 699 return limit->p2.p2_fast;
79e53945 700 else
3b1429d9 701 return limit->p2.p2_slow;
79e53945
JB
702 } else {
703 if (target < limit->p2.dot_limit)
3b1429d9 704 return limit->p2.p2_slow;
79e53945 705 else
3b1429d9 706 return limit->p2.p2_fast;
79e53945 707 }
3b1429d9
VS
708}
709
710static bool
711i9xx_find_best_dpll(const intel_limit_t *limit,
712 struct intel_crtc_state *crtc_state,
713 int target, int refclk, intel_clock_t *match_clock,
714 intel_clock_t *best_clock)
715{
716 struct drm_device *dev = crtc_state->base.crtc->dev;
717 intel_clock_t clock;
718 int err = target;
79e53945 719
0206e353 720 memset(best_clock, 0, sizeof(*best_clock));
79e53945 721
3b1429d9
VS
722 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
723
42158660
ZY
724 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
725 clock.m1++) {
726 for (clock.m2 = limit->m2.min;
727 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 728 if (clock.m2 >= clock.m1)
42158660
ZY
729 break;
730 for (clock.n = limit->n.min;
731 clock.n <= limit->n.max; clock.n++) {
732 for (clock.p1 = limit->p1.min;
733 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
734 int this_err;
735
dccbea3b 736 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV
737 if (!intel_PLL_is_valid(dev, limit,
738 &clock))
739 continue;
740 if (match_clock &&
741 clock.p != match_clock->p)
742 continue;
743
744 this_err = abs(clock.dot - target);
745 if (this_err < err) {
746 *best_clock = clock;
747 err = this_err;
748 }
749 }
750 }
751 }
752 }
753
754 return (err != target);
755}
756
757static bool
a93e255f
ACO
758pnv_find_best_dpll(const intel_limit_t *limit,
759 struct intel_crtc_state *crtc_state,
ee9300bb
DV
760 int target, int refclk, intel_clock_t *match_clock,
761 intel_clock_t *best_clock)
79e53945 762{
3b1429d9 763 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 764 intel_clock_t clock;
79e53945
JB
765 int err = target;
766
0206e353 767 memset(best_clock, 0, sizeof(*best_clock));
79e53945 768
3b1429d9
VS
769 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
42158660
ZY
771 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
772 clock.m1++) {
773 for (clock.m2 = limit->m2.min;
774 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY
775 for (clock.n = limit->n.min;
776 clock.n <= limit->n.max; clock.n++) {
777 for (clock.p1 = limit->p1.min;
778 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
779 int this_err;
780
dccbea3b 781 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
79e53945 784 continue;
cec2f356
SP
785 if (match_clock &&
786 clock.p != match_clock->p)
787 continue;
79e53945
JB
788
789 this_err = abs(clock.dot - target);
790 if (this_err < err) {
791 *best_clock = clock;
792 err = this_err;
793 }
794 }
795 }
796 }
797 }
798
799 return (err != target);
800}
801
d4906093 802static bool
a93e255f
ACO
803g4x_find_best_dpll(const intel_limit_t *limit,
804 struct intel_crtc_state *crtc_state,
ee9300bb
DV
805 int target, int refclk, intel_clock_t *match_clock,
806 intel_clock_t *best_clock)
d4906093 807{
3b1429d9 808 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML
809 intel_clock_t clock;
810 int max_n;
3b1429d9 811 bool found = false;
6ba770dc
AJ
812 /* approximately equals target * 0.00585 */
813 int err_most = (target >> 8) + (target >> 9);
d4906093
ML
814
815 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS
816
817 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
818
d4906093 819 max_n = limit->n.max;
f77f13e2 820 /* based on hardware requirement, prefer smaller n to precision */
d4906093 821 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 822 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML
823 for (clock.m1 = limit->m1.max;
824 clock.m1 >= limit->m1.min; clock.m1--) {
825 for (clock.m2 = limit->m2.max;
826 clock.m2 >= limit->m2.min; clock.m2--) {
827 for (clock.p1 = limit->p1.max;
828 clock.p1 >= limit->p1.min; clock.p1--) {
829 int this_err;
830
dccbea3b 831 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW
832 if (!intel_PLL_is_valid(dev, limit,
833 &clock))
d4906093 834 continue;
1b894b59
CW
835
836 this_err = abs(clock.dot - target);
d4906093
ML
837 if (this_err < err_most) {
838 *best_clock = clock;
839 err_most = this_err;
840 max_n = clock.n;
841 found = true;
842 }
843 }
844 }
845 }
846 }
2c07245f
ZW
847 return found;
848}
849
d5dd62bd
ID
850/*
851 * Check if the calculated PLL configuration is more optimal compared to the
852 * best configuration and error found so far. Return the calculated error.
853 */
854static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
855 const intel_clock_t *calculated_clock,
856 const intel_clock_t *best_clock,
857 unsigned int best_error_ppm,
858 unsigned int *error_ppm)
859{
9ca3ba01
ID
860 /*
861 * For CHV ignore the error and consider only the P value.
862 * Prefer a bigger P value based on HW requirements.
863 */
864 if (IS_CHERRYVIEW(dev)) {
865 *error_ppm = 0;
866
867 return calculated_clock->p > best_clock->p;
868 }
869
24be4e46
ID
870 if (WARN_ON_ONCE(!target_freq))
871 return false;
872
d5dd62bd
ID
873 *error_ppm = div_u64(1000000ULL *
874 abs(target_freq - calculated_clock->dot),
875 target_freq);
876 /*
877 * Prefer a better P value over a better (smaller) error if the error
878 * is small. Ensure this preference for future configurations too by
879 * setting the error to 0.
880 */
881 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
882 *error_ppm = 0;
883
884 return true;
885 }
886
887 return *error_ppm + 10 < best_error_ppm;
888}
889
a0c4da24 890static bool
a93e255f
ACO
891vlv_find_best_dpll(const intel_limit_t *limit,
892 struct intel_crtc_state *crtc_state,
ee9300bb
DV
893 int target, int refclk, intel_clock_t *match_clock,
894 intel_clock_t *best_clock)
a0c4da24 895{
a93e255f 896 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 897 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 898 intel_clock_t clock;
69e4f900 899 unsigned int bestppm = 1000000;
27e639bf
VS
900 /* min update 19.2 MHz */
901 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 902 bool found = false;
a0c4da24 903
6b4bf1c4
VS
904 target *= 5; /* fast clock */
905
906 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB
907
908 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 909 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 910 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 911 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 912 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 913 clock.p = clock.p1 * clock.p2;
a0c4da24 914 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 915 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 916 unsigned int ppm;
69e4f900 917
6b4bf1c4
VS
918 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
919 refclk * clock.m1);
920
dccbea3b 921 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 922
f01b7962
VS
923 if (!intel_PLL_is_valid(dev, limit,
924 &clock))
43b0ac53
VS
925 continue;
926
d5dd62bd
ID
927 if (!vlv_PLL_is_optimal(dev, target,
928 &clock,
929 best_clock,
930 bestppm, &ppm))
931 continue;
6b4bf1c4 932
d5dd62bd
ID
933 *best_clock = clock;
934 bestppm = ppm;
935 found = true;
a0c4da24
JB
936 }
937 }
938 }
939 }
a0c4da24 940
49e497ef 941 return found;
a0c4da24 942}
a4fc5ed6 943
ef9348c8 944static bool
a93e255f
ACO
945chv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ef9348c8
CML
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
9ca3ba01 952 unsigned int best_error_ppm;
ef9348c8
CML
953 intel_clock_t clock;
954 uint64_t m2;
955 int found = false;
956
957 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 958 best_error_ppm = 1000000;
ef9348c8
CML
959
960 /*
961 * Based on hardware doc, the n always set to 1, and m1 always
962 * set to 2. If requires to support 200Mhz refclk, we need to
963 * revisit this because n may not 1 anymore.
964 */
965 clock.n = 1, clock.m1 = 2;
966 target *= 5; /* fast clock */
967
968 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
969 for (clock.p2 = limit->p2.p2_fast;
970 clock.p2 >= limit->p2.p2_slow;
971 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 972 unsigned int error_ppm;
ef9348c8
CML
973
974 clock.p = clock.p1 * clock.p2;
975
976 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
977 clock.n) << 22, refclk * clock.m1);
978
979 if (m2 > INT_MAX/clock.m1)
980 continue;
981
982 clock.m2 = m2;
983
dccbea3b 984 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML
985
986 if (!intel_PLL_is_valid(dev, limit, &clock))
987 continue;
988
9ca3ba01
ID
989 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
990 best_error_ppm, &error_ppm))
991 continue;
992
993 *best_clock = clock;
994 best_error_ppm = error_ppm;
995 found = true;
ef9348c8
CML
996 }
997 }
998
999 return found;
1000}
1001
5ab7b0b7
ID
1002bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1003 intel_clock_t *best_clock)
1004{
1005 int refclk = i9xx_get_refclk(crtc_state, 0);
1006
1007 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1008 target_clock, refclk, NULL, best_clock);
1009}
1010
20ddf665
VS
1011bool intel_crtc_active(struct drm_crtc *crtc)
1012{
1013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1014
1015 /* Be paranoid as we can arrive here with only partial
1016 * state retrieved from the hardware during setup.
1017 *
241bfc38 1018 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS
1019 * as Haswell has gained clock readout/fastboot support.
1020 *
66e514c1 1021 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1022 * properly reconstruct framebuffers.
c3d1f436
MR
1023 *
1024 * FIXME: The intel_crtc->active here should be switched to
1025 * crtc->state->active once we have proper CRTC states wired up
1026 * for atomic.
20ddf665 1027 */
c3d1f436 1028 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1029 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS
1030}
1031
a5c961d1
PZ
1032enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1033 enum pipe pipe)
1034{
1035 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1037
6e3c9717 1038 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ
1039}
1040
fbf49ea2
VS
1041static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1042{
1043 struct drm_i915_private *dev_priv = dev->dev_private;
1044 u32 reg = PIPEDSL(pipe);
1045 u32 line1, line2;
1046 u32 line_mask;
1047
1048 if (IS_GEN2(dev))
1049 line_mask = DSL_LINEMASK_GEN2;
1050 else
1051 line_mask = DSL_LINEMASK_GEN3;
1052
1053 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1054 msleep(5);
fbf49ea2
VS
1055 line2 = I915_READ(reg) & line_mask;
1056
1057 return line1 == line2;
1058}
1059
ab7ad7f6
KP
1060/*
1061 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1062 * @crtc: crtc whose pipe to wait for
9d0498a2
JB
1063 *
1064 * After disabling a pipe, we can't wait for vblank in the usual way,
1065 * spinning on the vblank interrupt status bit, since we won't actually
1066 * see an interrupt when the pipe is disabled.
1067 *
ab7ad7f6
KP
1068 * On Gen4 and above:
1069 * wait for the pipe register state bit to turn off
1070 *
1071 * Otherwise:
1072 * wait for the display line value to settle (it usually
1073 * ends up stopping at the start of the next frame).
58e10eb9 1074 *
9d0498a2 1075 */
575f7ab7 1076static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1077{
575f7ab7 1078 struct drm_device *dev = crtc->base.dev;
9d0498a2 1079 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1080 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1081 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP
1082
1083 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1084 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP
1085
1086 /* Wait for the Pipe State to go off */
58e10eb9
CW
1087 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1088 100))
284637d9 1089 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1090 } else {
ab7ad7f6 1091 /* Wait for the display line to settle */
fbf49ea2 1092 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1093 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1094 }
79e53945
JB
1095}
1096
b24e7179
JB
1097static const char *state_string(bool enabled)
1098{
1099 return enabled ? "on" : "off";
1100}
1101
1102/* Only for pre-ILK configs */
55607e8a
DV
1103void assert_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
b24e7179
JB
1105{
1106 int reg;
1107 u32 val;
1108 bool cur_state;
1109
1110 reg = DPLL(pipe);
1111 val = I915_READ(reg);
1112 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1113 I915_STATE_WARN(cur_state != state,
b24e7179
JB
1114 "PLL state assertion failure (expected %s, current %s)\n",
1115 state_string(state), state_string(cur_state));
1116}
b24e7179 1117
23538ef1
JN
1118/* XXX: the dsi pll is shared between MIPI DSI ports */
1119static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1120{
1121 u32 val;
1122 bool cur_state;
1123
a580516d 1124 mutex_lock(&dev_priv->sb_lock);
23538ef1 1125 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1126 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN
1127
1128 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1129 I915_STATE_WARN(cur_state != state,
23538ef1
JN
1130 "DSI PLL state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132}
1133#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1134#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1135
55607e8a 1136struct intel_shared_dpll *
e2b78267
DV
1137intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1138{
1139 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1140
6e3c9717 1141 if (crtc->config->shared_dpll < 0)
e2b78267
DV
1142 return NULL;
1143
6e3c9717 1144 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV
1145}
1146
040484af 1147/* For ILK+ */
55607e8a
DV
1148void assert_shared_dpll(struct drm_i915_private *dev_priv,
1149 struct intel_shared_dpll *pll,
1150 bool state)
040484af 1151{
040484af 1152 bool cur_state;
5358901f 1153 struct intel_dpll_hw_state hw_state;
040484af 1154
92b27b08 1155 if (WARN (!pll,
46edb027 1156 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1157 return;
ee7b9f93 1158
5358901f 1159 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1160 I915_STATE_WARN(cur_state != state,
5358901f
DV
1161 "%s assertion failure (expected %s, current %s)\n",
1162 pll->name, state_string(state), state_string(cur_state));
040484af 1163}
040484af
JB
1164
1165static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1166 enum pipe pipe, bool state)
1167{
1168 int reg;
1169 u32 val;
1170 bool cur_state;
ad80a810
PZ
1171 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1172 pipe);
040484af 1173
affa9354
PZ
1174 if (HAS_DDI(dev_priv->dev)) {
1175 /* DDI does not have a specific FDI_TX register */
ad80a810 1176 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1177 val = I915_READ(reg);
ad80a810 1178 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED
1179 } else {
1180 reg = FDI_TX_CTL(pipe);
1181 val = I915_READ(reg);
1182 cur_state = !!(val & FDI_TX_ENABLE);
1183 }
e2c719b7 1184 I915_STATE_WARN(cur_state != state,
040484af
JB
1185 "FDI TX state assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187}
1188#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1189#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1190
1191static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
1193{
1194 int reg;
1195 u32 val;
1196 bool cur_state;
1197
d63fa0dc
PZ
1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1201 I915_STATE_WARN(cur_state != state,
040484af
JB
1202 "FDI RX state assertion failure (expected %s, current %s)\n",
1203 state_string(state), state_string(cur_state));
1204}
1205#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1206#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1207
1208static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
1213
1214 /* ILK FDI PLL is always enabled */
3d13ef2e 1215 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB
1216 return;
1217
bf507ef7 1218 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1219 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED
1220 return;
1221
040484af
JB
1222 reg = FDI_TX_CTL(pipe);
1223 val = I915_READ(reg);
e2c719b7 1224 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB
1225}
1226
55607e8a
DV
1227void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1228 enum pipe pipe, bool state)
040484af
JB
1229{
1230 int reg;
1231 u32 val;
55607e8a 1232 bool cur_state;
040484af
JB
1233
1234 reg = FDI_RX_CTL(pipe);
1235 val = I915_READ(reg);
55607e8a 1236 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1237 I915_STATE_WARN(cur_state != state,
55607e8a
DV
1238 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1239 state_string(state), state_string(cur_state));
040484af
JB
1240}
1241
b680c37a
DV
1242void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1243 enum pipe pipe)
ea0760cf 1244{
bedd4dba
JN
1245 struct drm_device *dev = dev_priv->dev;
1246 int pp_reg;
ea0760cf
JB
1247 u32 val;
1248 enum pipe panel_pipe = PIPE_A;
0de3b485 1249 bool locked = true;
ea0760cf 1250
bedd4dba
JN
1251 if (WARN_ON(HAS_DDI(dev)))
1252 return;
1253
1254 if (HAS_PCH_SPLIT(dev)) {
1255 u32 port_sel;
1256
ea0760cf 1257 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN
1258 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1259
1260 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1261 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1262 panel_pipe = PIPE_B;
1263 /* XXX: else fix for eDP */
1264 } else if (IS_VALLEYVIEW(dev)) {
1265 /* presumably write lock depends on pipe, not port select */
1266 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1267 panel_pipe = pipe;
ea0760cf
JB
1268 } else {
1269 pp_reg = PP_CONTROL;
bedd4dba
JN
1270 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1271 panel_pipe = PIPE_B;
ea0760cf
JB
1272 }
1273
1274 val = I915_READ(pp_reg);
1275 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1276 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB
1277 locked = false;
1278
e2c719b7 1279 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1280 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1281 pipe_name(pipe));
ea0760cf
JB
1282}
1283
93ce0ba6
JN
1284static void assert_cursor(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, bool state)
1286{
1287 struct drm_device *dev = dev_priv->dev;
1288 bool cur_state;
1289
d9d82081 1290 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1291 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1292 else
5efb3e28 1293 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1294
e2c719b7 1295 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN
1296 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1297 pipe_name(pipe), state_string(state), state_string(cur_state));
1298}
1299#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1300#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1301
b840d907
JB
1302void assert_pipe(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, bool state)
b24e7179
JB
1304{
1305 int reg;
1306 u32 val;
63d7bbe9 1307 bool cur_state;
702e7a56
PZ
1308 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1309 pipe);
b24e7179 1310
b6b5d049
VS
1311 /* if we need the pipe quirk it must be always on */
1312 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1313 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV
1314 state = true;
1315
f458ebbc 1316 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1317 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ
1318 cur_state = false;
1319 } else {
1320 reg = PIPECONF(cpu_transcoder);
1321 val = I915_READ(reg);
1322 cur_state = !!(val & PIPECONF_ENABLE);
1323 }
1324
e2c719b7 1325 I915_STATE_WARN(cur_state != state,
63d7bbe9 1326 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1327 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB
1328}
1329
931872fc
CW
1330static void assert_plane(struct drm_i915_private *dev_priv,
1331 enum plane plane, bool state)
b24e7179
JB
1332{
1333 int reg;
1334 u32 val;
931872fc 1335 bool cur_state;
b24e7179
JB
1336
1337 reg = DSPCNTR(plane);
1338 val = I915_READ(reg);
931872fc 1339 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1340 I915_STATE_WARN(cur_state != state,
931872fc
CW
1341 "plane %c assertion failure (expected %s, current %s)\n",
1342 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB
1343}
1344
931872fc
CW
1345#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1346#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1347
b24e7179
JB
1348static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
1350{
653e1026 1351 struct drm_device *dev = dev_priv->dev;
b24e7179
JB
1352 int reg, i;
1353 u32 val;
1354 int cur_pipe;
1355
653e1026
VS
1356 /* Primary planes are fixed to pipes on gen4+ */
1357 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ
1358 reg = DSPCNTR(pipe);
1359 val = I915_READ(reg);
e2c719b7 1360 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ
1361 "plane %c assertion failure, should be disabled but not\n",
1362 plane_name(pipe));
19ec1358 1363 return;
28c05794 1364 }
19ec1358 1365
b24e7179 1366 /* Need to check both planes against the pipe */
055e393f 1367 for_each_pipe(dev_priv, i) {
b24e7179
JB
1368 reg = DSPCNTR(i);
1369 val = I915_READ(reg);
1370 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1371 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1372 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB
1373 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1374 plane_name(i), pipe_name(pipe));
b24e7179
JB
1375 }
1376}
1377
19332d7a
JB
1378static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1379 enum pipe pipe)
1380{
20674eef 1381 struct drm_device *dev = dev_priv->dev;
1fe47785 1382 int reg, sprite;
19332d7a
JB
1383 u32 val;
1384
7feb8b88 1385 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1386 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1387 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1388 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL
1389 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1390 sprite, pipe_name(pipe));
1391 }
1392 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1393 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1394 reg = SPCNTR(pipe, sprite);
20674eef 1395 val = I915_READ(reg);
e2c719b7 1396 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1397 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1398 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS
1399 }
1400 } else if (INTEL_INFO(dev)->gen >= 7) {
1401 reg = SPRCTL(pipe);
19332d7a 1402 val = I915_READ(reg);
e2c719b7 1403 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1404 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS
1405 plane_name(pipe), pipe_name(pipe));
1406 } else if (INTEL_INFO(dev)->gen >= 5) {
1407 reg = DVSCNTR(pipe);
19332d7a 1408 val = I915_READ(reg);
e2c719b7 1409 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1410 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1411 plane_name(pipe), pipe_name(pipe));
19332d7a
JB
1412 }
1413}
1414
08c71e5e
VS
1415static void assert_vblank_disabled(struct drm_crtc *crtc)
1416{
e2c719b7 1417 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS
1418 drm_crtc_vblank_put(crtc);
1419}
1420
89eff4be 1421static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB
1422{
1423 u32 val;
1424 bool enabled;
1425
e2c719b7 1426 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1427
92f2584a
JB
1428 val = I915_READ(PCH_DREF_CONTROL);
1429 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1430 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1431 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB
1432}
1433
ab9412ba
DV
1434static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe)
92f2584a
JB
1436{
1437 int reg;
1438 u32 val;
1439 bool enabled;
1440
ab9412ba 1441 reg = PCH_TRANSCONF(pipe);
92f2584a
JB
1442 val = I915_READ(reg);
1443 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1444 I915_STATE_WARN(enabled,
9db4a9c7
JB
1445 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1446 pipe_name(pipe));
92f2584a
JB
1447}
1448
4e634389
KP
1449static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP
1451{
1452 if ((val & DP_PORT_EN) == 0)
1453 return false;
1454
1455 if (HAS_PCH_CPT(dev_priv->dev)) {
1456 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1457 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1458 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1459 return false;
44f37d1f
CML
1460 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1461 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1462 return false;
f0575e92
KP
1463 } else {
1464 if ((val & DP_PIPE_MASK) != (pipe << 30))
1465 return false;
1466 }
1467 return true;
1468}
1469
1519b995
KP
1470static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1471 enum pipe pipe, u32 val)
1472{
dc0fa718 1473 if ((val & SDVO_ENABLE) == 0)
1519b995
KP
1474 return false;
1475
1476 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1477 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1478 return false;
44f37d1f
CML
1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1481 return false;
1519b995 1482 } else {
dc0fa718 1483 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP
1484 return false;
1485 }
1486 return true;
1487}
1488
1489static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
1492 if ((val & LVDS_PORT_EN) == 0)
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
1496 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1497 return false;
1498 } else {
1499 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1500 return false;
1501 }
1502 return true;
1503}
1504
1505static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1506 enum pipe pipe, u32 val)
1507{
1508 if ((val & ADPA_DAC_ENABLE) == 0)
1509 return false;
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1515 return false;
1516 }
1517 return true;
1518}
1519
291906f1 1520static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1521 enum pipe pipe, int reg, u32 port_sel)
291906f1 1522{
47a05eca 1523 u32 val = I915_READ(reg);
e2c719b7 1524 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1525 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1526 reg, pipe_name(pipe));
de9a35ab 1527
e2c719b7 1528 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1529 && (val & DP_PIPEB_SELECT),
de9a35ab 1530 "IBX PCH dp port still using transcoder B\n");
291906f1
JB
1531}
1532
1533static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1534 enum pipe pipe, int reg)
1535{
47a05eca 1536 u32 val = I915_READ(reg);
e2c719b7 1537 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1538 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1539 reg, pipe_name(pipe));
de9a35ab 1540
e2c719b7 1541 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1542 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1543 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB
1544}
1545
1546static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1547 enum pipe pipe)
1548{
1549 int reg;
1550 u32 val;
291906f1 1551
f0575e92
KP
1552 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1553 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1554 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB
1555
1556 reg = PCH_ADPA;
1557 val = I915_READ(reg);
e2c719b7 1558 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1559 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1560 pipe_name(pipe));
291906f1
JB
1561
1562 reg = PCH_LVDS;
1563 val = I915_READ(reg);
e2c719b7 1564 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1565 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1566 pipe_name(pipe));
291906f1 1567
e2debe91
PZ
1568 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1569 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1570 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB
1571}
1572
d288f65f 1573static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1574 const struct intel_crtc_state *pipe_config)
87442f73 1575{
426115cf
DV
1576 struct drm_device *dev = crtc->base.dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int reg = DPLL(crtc->pipe);
d288f65f 1579 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1580
426115cf 1581 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV
1582
1583 /* No really, not for ILK+ */
1584 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1585
1586 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1587 if (IS_MOBILE(dev_priv->dev))
426115cf 1588 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1589
426115cf
DV
1590 I915_WRITE(reg, dpll);
1591 POSTING_READ(reg);
1592 udelay(150);
1593
1594 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1595 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1596
d288f65f 1597 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1598 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV
1599
1600 /* We do this three times for luck */
426115cf 1601 I915_WRITE(reg, dpll);
87442f73
DV
1602 POSTING_READ(reg);
1603 udelay(150); /* wait for warmup */
426115cf 1604 I915_WRITE(reg, dpll);
87442f73
DV
1605 POSTING_READ(reg);
1606 udelay(150); /* wait for warmup */
426115cf 1607 I915_WRITE(reg, dpll);
87442f73
DV
1608 POSTING_READ(reg);
1609 udelay(150); /* wait for warmup */
1610}
1611
d288f65f 1612static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
9d556c99
CML
1614{
1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int pipe = crtc->pipe;
1618 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML
1619 u32 tmp;
1620
1621 assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1624
a580516d 1625 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML
1626
1627 /* Enable back the 10bit clock to display controller */
1628 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1629 tmp |= DPIO_DCLKP_EN;
1630 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1631
54433e91
VS
1632 mutex_unlock(&dev_priv->sb_lock);
1633
9d556c99
CML
1634 /*
1635 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1636 */
1637 udelay(1);
1638
1639 /* Enable PLL */
d288f65f 1640 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML
1641
1642 /* Check PLL is locked */
a11b0703 1643 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML
1644 DRM_ERROR("PLL %d failed to lock\n", pipe);
1645
a11b0703 1646 /* not sure when this should be written */
d288f65f 1647 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1648 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML
1649}
1650
1c4e0274
VS
1651static int intel_num_dvo_pipes(struct drm_device *dev)
1652{
1653 struct intel_crtc *crtc;
1654 int count = 0;
1655
1656 for_each_intel_crtc(dev, crtc)
3538b9df 1657 count += crtc->base.state->active &&
409ee761 1658 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS
1659
1660 return count;
1661}
1662
66e3d5c0 1663static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1664{
66e3d5c0
DV
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 int reg = DPLL(crtc->pipe);
6e3c9717 1668 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1669
66e3d5c0 1670 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1671
63d7bbe9 1672 /* No really, not for ILK+ */
3d13ef2e 1673 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB
1674
1675 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV
1676 if (IS_MOBILE(dev) && !IS_I830(dev))
1677 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1678
1c4e0274
VS
1679 /* Enable DVO 2x clock on both PLLs if necessary */
1680 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1681 /*
1682 * It appears to be important that we don't enable this
1683 * for the current pipe before otherwise configuring the
1684 * PLL. No idea how this should be handled if multiple
1685 * DVO outputs are enabled simultaneosly.
1686 */
1687 dpll |= DPLL_DVO_2X_MODE;
1688 I915_WRITE(DPLL(!crtc->pipe),
1689 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1690 }
66e3d5c0
DV
1691
1692 /* Wait for the clocks to stabilize. */
1693 POSTING_READ(reg);
1694 udelay(150);
1695
1696 if (INTEL_INFO(dev)->gen >= 4) {
1697 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1698 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV
1699 } else {
1700 /* The pixel multiplier can only be updated once the
1701 * DPLL is enabled and the clocks are stable.
1702 *
1703 * So write it again.
1704 */
1705 I915_WRITE(reg, dpll);
1706 }
63d7bbe9
JB
1707
1708 /* We do this three times for luck */
66e3d5c0 1709 I915_WRITE(reg, dpll);
63d7bbe9
JB
1710 POSTING_READ(reg);
1711 udelay(150); /* wait for warmup */
66e3d5c0 1712 I915_WRITE(reg, dpll);
63d7bbe9
JB
1713 POSTING_READ(reg);
1714 udelay(150); /* wait for warmup */
66e3d5c0 1715 I915_WRITE(reg, dpll);
63d7bbe9
JB
1716 POSTING_READ(reg);
1717 udelay(150); /* wait for warmup */
1718}
1719
1720/**
50b44a44 1721 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB
1722 * @dev_priv: i915 private structure
1723 * @pipe: pipe PLL to disable
1724 *
1725 * Disable the PLL for @pipe, making sure the pipe is off first.
1726 *
1727 * Note! This is for pre-ILK only.
1728 */
1c4e0274 1729static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1730{
1c4e0274
VS
1731 struct drm_device *dev = crtc->base.dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 enum pipe pipe = crtc->pipe;
1734
1735 /* Disable DVO 2x clock on both PLLs if necessary */
1736 if (IS_I830(dev) &&
409ee761 1737 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1738 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS
1739 I915_WRITE(DPLL(PIPE_B),
1740 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1741 I915_WRITE(DPLL(PIPE_A),
1742 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1743 }
1744
b6b5d049
VS
1745 /* Don't disable pipe or pipe PLLs if needed */
1746 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1747 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB
1748 return;
1749
1750 /* Make sure the pipe isn't still relying on us */
1751 assert_pipe_disabled(dev_priv, pipe);
1752
b8afb911 1753 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1754 POSTING_READ(DPLL(pipe));
63d7bbe9
JB
1755}
1756
f6071166
JB
1757static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1758{
b8afb911 1759 u32 val;
f6071166
JB
1760
1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
1763
e5cbfbfb
ID
1764 /*
1765 * Leave integrated clock source and reference clock enabled for pipe B.
1766 * The latter is needed for VGA hotplug / manual detection.
1767 */
b8afb911 1768 val = DPLL_VGA_MODE_DIS;
f6071166 1769 if (pipe == PIPE_B)
60bfe44f 1770 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB
1771 I915_WRITE(DPLL(pipe), val);
1772 POSTING_READ(DPLL(pipe));
076ed3b2
CML
1773
1774}
1775
1776static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1777{
d752048d 1778 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML
1779 u32 val;
1780
a11b0703
VS
1781 /* Make sure the pipe isn't still relying on us */
1782 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1783
a11b0703 1784 /* Set PLL en = 0 */
60bfe44f
VS
1785 val = DPLL_SSC_REF_CLK_CHV |
1786 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS
1787 if (pipe != PIPE_A)
1788 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1789 I915_WRITE(DPLL(pipe), val);
1790 POSTING_READ(DPLL(pipe));
d752048d 1791
a580516d 1792 mutex_lock(&dev_priv->sb_lock);
d752048d
VS
1793
1794 /* Disable 10bit clock to display controller */
1795 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1796 val &= ~DPIO_DCLKP_EN;
1797 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1798
a580516d 1799 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB
1800}
1801
e4607fcf 1802void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS
1803 struct intel_digital_port *dport,
1804 unsigned int expected_mask)
89b667f8
JB
1805{
1806 u32 port_mask;
00fc31b7 1807 int dpll_reg;
89b667f8 1808
e4607fcf
CML
1809 switch (dport->port) {
1810 case PORT_B:
89b667f8 1811 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1812 dpll_reg = DPLL(0);
e4607fcf
CML
1813 break;
1814 case PORT_C:
89b667f8 1815 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1816 dpll_reg = DPLL(0);
9b6de0a1 1817 expected_mask <<= 4;
00fc31b7
CML
1818 break;
1819 case PORT_D:
1820 port_mask = DPLL_PORTD_READY_MASK;
1821 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML
1822 break;
1823 default:
1824 BUG();
1825 }
89b667f8 1826
9b6de0a1
VS
1827 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1828 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1829 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB
1830}
1831
b14b1055
DV
1832static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1833{
1834 struct drm_device *dev = crtc->base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1837
be19f0ff
CW
1838 if (WARN_ON(pll == NULL))
1839 return;
1840
3e369b76 1841 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV
1842 if (pll->active == 0) {
1843 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1844 WARN_ON(pll->on);
1845 assert_shared_dpll_disabled(dev_priv, pll);
1846
1847 pll->mode_set(dev_priv, pll);
1848 }
1849}
1850
92f2584a 1851/**
85b3894f 1852 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB
1853 * @dev_priv: i915 private structure
1854 * @pipe: pipe PLL to enable
1855 *
1856 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1857 * drives the transcoder clock.
1858 */
85b3894f 1859static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1860{
3d13ef2e
DL
1861 struct drm_device *dev = crtc->base.dev;
1862 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1863 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1864
87a875bb 1865 if (WARN_ON(pll == NULL))
48da64a8
CW
1866 return;
1867
3e369b76 1868 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1869 return;
ee7b9f93 1870
74dd6928 1871 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1872 pll->name, pll->active, pll->on,
e2b78267 1873 crtc->base.base.id);
92f2584a 1874
cdbd2316
DV
1875 if (pll->active++) {
1876 WARN_ON(!pll->on);
e9d6944e 1877 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB
1878 return;
1879 }
f4a091c7 1880 WARN_ON(pll->on);
ee7b9f93 1881
bd2bb1b9
PZ
1882 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1883
46edb027 1884 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1885 pll->enable(dev_priv, pll);
ee7b9f93 1886 pll->on = true;
92f2584a
JB
1887}
1888
f6daaec2 1889static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1890{
3d13ef2e
DL
1891 struct drm_device *dev = crtc->base.dev;
1892 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1893 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1894
92f2584a 1895 /* PCH only available on ILK+ */
80aa9312
JB
1896 if (INTEL_INFO(dev)->gen < 5)
1897 return;
1898
eddfcbcd
ML
1899 if (pll == NULL)
1900 return;
92f2584a 1901
eddfcbcd 1902 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1903 return;
7a419866 1904
46edb027
DV
1905 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1906 pll->name, pll->active, pll->on,
e2b78267 1907 crtc->base.base.id);
7a419866 1908
48da64a8 1909 if (WARN_ON(pll->active == 0)) {
e9d6944e 1910 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW
1911 return;
1912 }
1913
e9d6944e 1914 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1915 WARN_ON(!pll->on);
cdbd2316 1916 if (--pll->active)
7a419866 1917 return;
ee7b9f93 1918
46edb027 1919 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1920 pll->disable(dev_priv, pll);
ee7b9f93 1921 pll->on = false;
bd2bb1b9
PZ
1922
1923 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB
1924}
1925
b8a4f404
PZ
1926static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1927 enum pipe pipe)
040484af 1928{
23670b32 1929 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1930 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1932 uint32_t reg, val, pipeconf_val;
040484af
JB
1933
1934 /* PCH only available on ILK+ */
55522f37 1935 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB
1936
1937 /* Make sure PCH DPLL is enabled */
e72f9fbf 1938 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1939 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB
1940
1941 /* FDI must be feeding us bits for PCH ports */
1942 assert_fdi_tx_enabled(dev_priv, pipe);
1943 assert_fdi_rx_enabled(dev_priv, pipe);
1944
23670b32
DV
1945 if (HAS_PCH_CPT(dev)) {
1946 /* Workaround: Set the timing override bit before enabling the
1947 * pch transcoder. */
1948 reg = TRANS_CHICKEN2(pipe);
1949 val = I915_READ(reg);
1950 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1951 I915_WRITE(reg, val);
59c859d6 1952 }
23670b32 1953
ab9412ba 1954 reg = PCH_TRANSCONF(pipe);
040484af 1955 val = I915_READ(reg);
5f7f726d 1956 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB
1957
1958 if (HAS_PCH_IBX(dev_priv->dev)) {
1959 /*
c5de7c6f
VS
1960 * Make the BPC in transcoder be consistent with
1961 * that in pipeconf reg. For HDMI we must use 8bpc
1962 * here for both 8bpc and 12bpc.
e9bcff5c 1963 */
dfd07d72 1964 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS
1965 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1966 val |= PIPECONF_8BPC;
1967 else
1968 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1969 }
5f7f726d
PZ
1970
1971 val &= ~TRANS_INTERLACE_MASK;
1972 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1973 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1974 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ
1975 val |= TRANS_LEGACY_INTERLACED_ILK;
1976 else
1977 val |= TRANS_INTERLACED;
5f7f726d
PZ
1978 else
1979 val |= TRANS_PROGRESSIVE;
1980
040484af
JB
1981 I915_WRITE(reg, val | TRANS_ENABLE);
1982 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1983 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB
1984}
1985
8fb033d7 1986static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1987 enum transcoder cpu_transcoder)
040484af 1988{
8fb033d7 1989 u32 val, pipeconf_val;
8fb033d7
PZ
1990
1991 /* PCH only available on ILK+ */
55522f37 1992 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1993
8fb033d7 1994 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1995 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1996 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1997
223a6fdf
PZ
1998 /* Workaround: set timing override bit. */
1999 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2000 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ
2001 I915_WRITE(_TRANSA_CHICKEN2, val);
2002
25f3ef11 2003 val = TRANS_ENABLE;
937bb610 2004 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2005
9a76b1c6
PZ
2006 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2007 PIPECONF_INTERLACED_ILK)
a35f2679 2008 val |= TRANS_INTERLACED;
8fb033d7
PZ
2009 else
2010 val |= TRANS_PROGRESSIVE;
2011
ab9412ba
DV
2012 I915_WRITE(LPT_TRANSCONF, val);
2013 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2014 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ
2015}
2016
b8a4f404
PZ
2017static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2018 enum pipe pipe)
040484af 2019{
23670b32
DV
2020 struct drm_device *dev = dev_priv->dev;
2021 uint32_t reg, val;
040484af
JB
2022
2023 /* FDI relies on the transcoder */
2024 assert_fdi_tx_disabled(dev_priv, pipe);
2025 assert_fdi_rx_disabled(dev_priv, pipe);
2026
291906f1
JB
2027 /* Ports must be off as well */
2028 assert_pch_ports_disabled(dev_priv, pipe);
2029
ab9412ba 2030 reg = PCH_TRANSCONF(pipe);
040484af
JB
2031 val = I915_READ(reg);
2032 val &= ~TRANS_ENABLE;
2033 I915_WRITE(reg, val);
2034 /* wait for PCH transcoder off, transcoder state */
2035 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2036 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV
2037
2038 if (!HAS_PCH_IBX(dev)) {
2039 /* Workaround: Clear the timing override chicken bit again. */
2040 reg = TRANS_CHICKEN2(pipe);
2041 val = I915_READ(reg);
2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(reg, val);
2044 }
040484af
JB
2045}
2046
ab4d966c 2047static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2048{
8fb033d7
PZ
2049 u32 val;
2050
ab9412ba 2051 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2052 val &= ~TRANS_ENABLE;
ab9412ba 2053 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2054 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2055 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2056 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ
2057
2058 /* Workaround: clear timing override bit. */
2059 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2060 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2061 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB
2062}
2063
b24e7179 2064/**
309cfea8 2065 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2066 * @crtc: crtc responsible for the pipe
b24e7179 2067 *
0372264a 2068 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2069 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2070 */
e1fdc473 2071static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2072{
0372264a
PZ
2073 struct drm_device *dev = crtc->base.dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 enum pipe pipe = crtc->pipe;
702e7a56
PZ
2076 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2077 pipe);
1a240d4d 2078 enum pipe pch_transcoder;
b24e7179
JB
2079 int reg;
2080 u32 val;
2081
9e2ee2dd
VS
2082 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2083
58c6eaa2 2084 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2085 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV
2086 assert_sprites_disabled(dev_priv, pipe);
2087
681e5811 2088 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ
2089 pch_transcoder = TRANSCODER_A;
2090 else
2091 pch_transcoder = pipe;
2092
b24e7179
JB
2093 /*
2094 * A pipe without a PLL won't actually be able to drive bits from
2095 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2096 * need the check.
2097 */
50360403 2098 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2099 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN
2100 assert_dsi_pll_enabled(dev_priv);
2101 else
2102 assert_pll_enabled(dev_priv, pipe);
040484af 2103 else {
6e3c9717 2104 if (crtc->config->has_pch_encoder) {
040484af 2105 /* if driving the PCH, we need FDI enabled */
cc391bbb 2106 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV
2107 assert_fdi_tx_pll_enabled(dev_priv,
2108 (enum pipe) cpu_transcoder);
040484af
JB
2109 }
2110 /* FIXME: assert CPU port conditions for SNB+ */
2111 }
b24e7179 2112
702e7a56 2113 reg = PIPECONF(cpu_transcoder);
b24e7179 2114 val = I915_READ(reg);
7ad25d48 2115 if (val & PIPECONF_ENABLE) {
b6b5d049
VS
2116 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2117 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2118 return;
7ad25d48 2119 }
00d70b15
CW
2120
2121 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2122 POSTING_READ(reg);
b24e7179
JB
2123}
2124
2125/**
309cfea8 2126 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2127 * @crtc: crtc whose pipes is to be disabled
b24e7179 2128 *
575f7ab7
VS
2129 * Disable the pipe of @crtc, making sure that various hardware
2130 * specific requirements are met, if applicable, e.g. plane
2131 * disabled, panel fitter off, etc.
b24e7179
JB
2132 *
2133 * Will wait until the pipe has shut down before returning.
2134 */
575f7ab7 2135static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2136{
575f7ab7 2137 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2138 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2139 enum pipe pipe = crtc->pipe;
b24e7179
JB
2140 int reg;
2141 u32 val;
2142
9e2ee2dd
VS
2143 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2144
b24e7179
JB
2145 /*
2146 * Make sure planes won't keep trying to pump pixels to us,
2147 * or we might hang the display.
2148 */
2149 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2150 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2151 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
00d70b15
CW
2155 if ((val & PIPECONF_ENABLE) == 0)
2156 return;
2157
67adc644
VS
2158 /*
2159 * Double wide has implications for planes
2160 * so best keep it disabled when not needed.
2161 */
6e3c9717 2162 if (crtc->config->double_wide)
67adc644
VS
2163 val &= ~PIPECONF_DOUBLE_WIDE;
2164
2165 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS
2166 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2167 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS
2168 val &= ~PIPECONF_ENABLE;
2169
2170 I915_WRITE(reg, val);
2171 if ((val & PIPECONF_ENABLE) == 0)
2172 intel_wait_for_pipe_off(crtc);
b24e7179
JB
2173}
2174
693db184
CW
2175static bool need_vtd_wa(struct drm_device *dev)
2176{
2177#ifdef CONFIG_INTEL_IOMMU
2178 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2179 return true;
2180#endif
2181 return false;
2182}
2183
50470bb0 2184unsigned int
6761dd31
TU
2185intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2186 uint64_t fb_format_modifier)
a57ce0b2 2187{
6761dd31
TU
2188 unsigned int tile_height;
2189 uint32_t pixel_bytes;
a57ce0b2 2190
b5d0e9bf
DL
2191 switch (fb_format_modifier) {
2192 case DRM_FORMAT_MOD_NONE:
2193 tile_height = 1;
2194 break;
2195 case I915_FORMAT_MOD_X_TILED:
2196 tile_height = IS_GEN2(dev) ? 16 : 8;
2197 break;
2198 case I915_FORMAT_MOD_Y_TILED:
2199 tile_height = 32;
2200 break;
2201 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU
2202 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2203 switch (pixel_bytes) {
b5d0e9bf 2204 default:
6761dd31 2205 case 1:
b5d0e9bf
DL
2206 tile_height = 64;
2207 break;
6761dd31
TU
2208 case 2:
2209 case 4:
b5d0e9bf
DL
2210 tile_height = 32;
2211 break;
6761dd31 2212 case 8:
b5d0e9bf
DL
2213 tile_height = 16;
2214 break;
6761dd31 2215 case 16:
b5d0e9bf
DL
2216 WARN_ONCE(1,
2217 "128-bit pixels are not supported for display!");
2218 tile_height = 16;
2219 break;
2220 }
2221 break;
2222 default:
2223 MISSING_CASE(fb_format_modifier);
2224 tile_height = 1;
2225 break;
2226 }
091df6cb 2227
6761dd31
TU
2228 return tile_height;
2229}
2230
2231unsigned int
2232intel_fb_align_height(struct drm_device *dev, unsigned int height,
2233 uint32_t pixel_format, uint64_t fb_format_modifier)
2234{
2235 return ALIGN(height, intel_tile_height(dev, pixel_format,
2236 fb_format_modifier));
a57ce0b2
JB
2237}
2238
f64b98cd
TU
2239static int
2240intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2241 const struct drm_plane_state *plane_state)
2242{
50470bb0 2243 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2244 unsigned int tile_height, tile_pitch;
50470bb0 2245
f64b98cd
TU
2246 *view = i915_ggtt_view_normal;
2247
50470bb0
TU
2248 if (!plane_state)
2249 return 0;
2250
121920fa 2251 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU
2252 return 0;
2253
9abc4648 2254 *view = i915_ggtt_view_rotated;
50470bb0
TU
2255
2256 info->height = fb->height;
2257 info->pixel_format = fb->pixel_format;
2258 info->pitch = fb->pitches[0];
2259 info->fb_modifier = fb->modifier[0];
2260
84fe03f7
TU
2261 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2262 fb->modifier[0]);
2263 tile_pitch = PAGE_SIZE / tile_height;
2264 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2265 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2266 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2267
f64b98cd
TU
2268 return 0;
2269}
2270
4e9a86b6
VS
2271static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2272{
2273 if (INTEL_INFO(dev_priv)->gen >= 9)
2274 return 256 * 1024;
985b8bb4
VS
2275 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2276 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS
2277 return 128 * 1024;
2278 else if (INTEL_INFO(dev_priv)->gen >= 4)
2279 return 4 * 1024;
2280 else
44c5905e 2281 return 0;
4e9a86b6
VS
2282}
2283
127bd2ac 2284int
850c4cdc
TU
2285intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2286 struct drm_framebuffer *fb,
82bc3b2d 2287 const struct drm_plane_state *plane_state,
91af127f
JH
2288 struct intel_engine_cs *pipelined,
2289 struct drm_i915_gem_request **pipelined_request)
6b95a207 2290{
850c4cdc 2291 struct drm_device *dev = fb->dev;
ce453d81 2292 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2293 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2294 struct i915_ggtt_view view;
6b95a207
KH
2295 u32 alignment;
2296 int ret;
2297
ebcdd39e
MR
2298 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2299
7b911adc
TU
2300 switch (fb->modifier[0]) {
2301 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2302 alignment = intel_linear_alignment(dev_priv);
6b95a207 2303 break;
7b911adc 2304 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL
2305 if (INTEL_INFO(dev)->gen >= 9)
2306 alignment = 256 * 1024;
2307 else {
2308 /* pin() will align the object as required by fence */
2309 alignment = 0;
2310 }
6b95a207 2311 break;
7b911adc 2312 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL
2313 case I915_FORMAT_MOD_Yf_TILED:
2314 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2315 "Y tiling bo slipped through, driver bug!\n"))
2316 return -EINVAL;
2317 alignment = 1 * 1024 * 1024;
2318 break;
6b95a207 2319 default:
7b911adc
TU
2320 MISSING_CASE(fb->modifier[0]);
2321 return -EINVAL;
6b95a207
KH
2322 }
2323
f64b98cd
TU
2324 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2325 if (ret)
2326 return ret;
2327
693db184
CW
2328 /* Note that the w/a also requires 64 PTE of padding following the
2329 * bo. We currently fill all unused PTE with the shadow page and so
2330 * we should always have valid PTE following the scanout preventing
2331 * the VT-d warning.
2332 */
2333 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2334 alignment = 256 * 1024;
2335
d6dd6843
PZ
2336 /*
2337 * Global gtt pte registers are special registers which actually forward
2338 * writes to a chunk of system memory. Which means that there is no risk
2339 * that the register values disappear as soon as we call
2340 * intel_runtime_pm_put(), so it is correct to wrap only the
2341 * pin/unpin/fence and not more.
2342 */
2343 intel_runtime_pm_get(dev_priv);
2344
ce453d81 2345 dev_priv->mm.interruptible = false;
e6617330 2346 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2347 pipelined_request, &view);
48b956c5 2348 if (ret)
ce453d81 2349 goto err_interruptible;
6b95a207
KH
2350
2351 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2352 * fence, whereas 965+ only requires a fence if using
2353 * framebuffer compression. For simplicity, we always install
2354 * a fence as the cost is not that onerous.
2355 */
06d98131 2356 ret = i915_gem_object_get_fence(obj);
842315ee
ML
2357 if (ret == -EDEADLK) {
2358 /*
2359 * -EDEADLK means there are no free fences
2360 * no pending flips.
2361 *
2362 * This is propagated to atomic, but it uses
2363 * -EDEADLK to force a locking recovery, so
2364 * change the returned error to -EBUSY.
2365 */
2366 ret = -EBUSY;
2367 goto err_unpin;
2368 } else if (ret)
9a5a53b3 2369 goto err_unpin;
1690e1eb 2370
9a5a53b3 2371 i915_gem_object_pin_fence(obj);
6b95a207 2372
ce453d81 2373 dev_priv->mm.interruptible = true;
d6dd6843 2374 intel_runtime_pm_put(dev_priv);
6b95a207 2375 return 0;
48b956c5
CW
2376
2377err_unpin:
f64b98cd 2378 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW
2379err_interruptible:
2380 dev_priv->mm.interruptible = true;
d6dd6843 2381 intel_runtime_pm_put(dev_priv);
48b956c5 2382 return ret;
6b95a207
KH
2383}
2384
82bc3b2d
TU
2385static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2386 const struct drm_plane_state *plane_state)
1690e1eb 2387{
82bc3b2d 2388 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU
2389 struct i915_ggtt_view view;
2390 int ret;
82bc3b2d 2391
ebcdd39e
MR
2392 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2393
f64b98cd
TU
2394 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2395 WARN_ONCE(ret, "Couldn't get view from plane state!");
2396
1690e1eb 2397 i915_gem_object_unpin_fence(obj);
f64b98cd 2398 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW
2399}
2400
c2c75131
DV
2401/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2402 * is assumed to be a power-of-two. */
4e9a86b6
VS
2403unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2404 int *x, int *y,
bc752862
CW
2405 unsigned int tiling_mode,
2406 unsigned int cpp,
2407 unsigned int pitch)
c2c75131 2408{
bc752862
CW
2409 if (tiling_mode != I915_TILING_NONE) {
2410 unsigned int tile_rows, tiles;
c2c75131 2411
bc752862
CW
2412 tile_rows = *y / 8;
2413 *y %= 8;
c2c75131 2414
bc752862
CW
2415 tiles = *x / (512/cpp);
2416 *x %= 512/cpp;
2417
2418 return tile_rows * pitch * 8 + tiles * 4096;
2419 } else {
4e9a86b6 2420 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW
2421 unsigned int offset;
2422
2423 offset = *y * pitch + *x * cpp;
4e9a86b6
VS
2424 *y = (offset & alignment) / pitch;
2425 *x = ((offset & alignment) - *y * pitch) / cpp;
2426 return offset & ~alignment;
bc752862 2427 }
c2c75131
DV
2428}
2429
b35d63fa 2430static int i9xx_format_to_fourcc(int format)
46f297fb
JB
2431{
2432 switch (format) {
2433 case DISPPLANE_8BPP:
2434 return DRM_FORMAT_C8;
2435 case DISPPLANE_BGRX555:
2436 return DRM_FORMAT_XRGB1555;
2437 case DISPPLANE_BGRX565:
2438 return DRM_FORMAT_RGB565;
2439 default:
2440 case DISPPLANE_BGRX888:
2441 return DRM_FORMAT_XRGB8888;
2442 case DISPPLANE_RGBX888:
2443 return DRM_FORMAT_XBGR8888;
2444 case DISPPLANE_BGRX101010:
2445 return DRM_FORMAT_XRGB2101010;
2446 case DISPPLANE_RGBX101010:
2447 return DRM_FORMAT_XBGR2101010;
2448 }
2449}
2450
bc8d7dff
DL
2451static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2452{
2453 switch (format) {
2454 case PLANE_CTL_FORMAT_RGB_565:
2455 return DRM_FORMAT_RGB565;
2456 default:
2457 case PLANE_CTL_FORMAT_XRGB_8888:
2458 if (rgb_order) {
2459 if (alpha)
2460 return DRM_FORMAT_ABGR8888;
2461 else
2462 return DRM_FORMAT_XBGR8888;
2463 } else {
2464 if (alpha)
2465 return DRM_FORMAT_ARGB8888;
2466 else
2467 return DRM_FORMAT_XRGB8888;
2468 }
2469 case PLANE_CTL_FORMAT_XRGB_2101010:
2470 if (rgb_order)
2471 return DRM_FORMAT_XBGR2101010;
2472 else
2473 return DRM_FORMAT_XRGB2101010;
2474 }
2475}
2476
5724dbd1 2477static bool
f6936e29
DV
2478intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2479 struct intel_initial_plane_config *plane_config)
46f297fb
JB
2480{
2481 struct drm_device *dev = crtc->base.dev;
2482 struct drm_i915_gem_object *obj = NULL;
2483 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2484 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV
2485 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2486 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2487 PAGE_SIZE);
2488
2489 size_aligned -= base_aligned;
46f297fb 2490
ff2652ea
CW
2491 if (plane_config->size == 0)
2492 return false;
2493
f37b5c2b
DV
2494 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2495 base_aligned,
2496 base_aligned,
2497 size_aligned);
46f297fb 2498 if (!obj)
484b41dd 2499 return false;
46f297fb 2500
49af449b
DL
2501 obj->tiling_mode = plane_config->tiling;
2502 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2503 obj->stride = fb->pitches[0];
46f297fb 2504
6bf129df
DL
2505 mode_cmd.pixel_format = fb->pixel_format;
2506 mode_cmd.width = fb->width;
2507 mode_cmd.height = fb->height;
2508 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV
2509 mode_cmd.modifier[0] = fb->modifier[0];
2510 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB
2511
2512 mutex_lock(&dev->struct_mutex);
6bf129df 2513 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2514 &mode_cmd, obj)) {
46f297fb
JB
2515 DRM_DEBUG_KMS("intel fb init failed\n");
2516 goto out_unref_obj;
2517 }
46f297fb 2518 mutex_unlock(&dev->struct_mutex);
484b41dd 2519
f6936e29 2520 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2521 return true;
46f297fb
JB
2522
2523out_unref_obj:
2524 drm_gem_object_unreference(&obj->base);
2525 mutex_unlock(&dev->struct_mutex);
484b41dd
JB
2526 return false;
2527}
2528
afd65eb4
MR
2529/* Update plane->state->fb to match plane->fb after driver-internal updates */
2530static void
2531update_state_fb(struct drm_plane *plane)
2532{
2533 if (plane->fb == plane->state->fb)
2534 return;
2535
2536 if (plane->state->fb)
2537 drm_framebuffer_unreference(plane->state->fb);
2538 plane->state->fb = plane->fb;
2539 if (plane->state->fb)
2540 drm_framebuffer_reference(plane->state->fb);
2541}
2542
5724dbd1 2543static void
f6936e29
DV
2544intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2545 struct intel_initial_plane_config *plane_config)
484b41dd
JB
2546{
2547 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2548 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB
2549 struct drm_crtc *c;
2550 struct intel_crtc *i;
2ff8fde1 2551 struct drm_i915_gem_object *obj;
88595ac9 2552 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2553 struct drm_plane_state *plane_state = primary->state;
88595ac9 2554 struct drm_framebuffer *fb;
484b41dd 2555
2d14030b 2556 if (!plane_config->fb)
484b41dd
JB
2557 return;
2558
f6936e29 2559 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV
2560 fb = &plane_config->fb->base;
2561 goto valid_fb;
f55548b5 2562 }
484b41dd 2563
2d14030b 2564 kfree(plane_config->fb);
484b41dd
JB
2565
2566 /*
2567 * Failed to alloc the obj, check to see if we should share
2568 * an fb with another CRTC instead
2569 */
70e1e0ec 2570 for_each_crtc(dev, c) {
484b41dd
JB
2571 i = to_intel_crtc(c);
2572
2573 if (c == &intel_crtc->base)
2574 continue;
2575
2ff8fde1
MR
2576 if (!i->active)
2577 continue;
2578
88595ac9
DV
2579 fb = c->primary->fb;
2580 if (!fb)
484b41dd
JB
2581 continue;
2582
88595ac9 2583 obj = intel_fb_obj(fb);
2ff8fde1 2584 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV
2585 drm_framebuffer_reference(fb);
2586 goto valid_fb;
484b41dd
JB
2587 }
2588 }
88595ac9
DV
2589
2590 return;
2591
2592valid_fb:
be5651f2
ML
2593 plane_state->src_x = plane_state->src_y = 0;
2594 plane_state->src_w = fb->width << 16;
2595 plane_state->src_h = fb->height << 16;
2596
2597 plane_state->crtc_x = plane_state->src_y = 0;
2598 plane_state->crtc_w = fb->width;
2599 plane_state->crtc_h = fb->height;
2600
88595ac9
DV
2601 obj = intel_fb_obj(fb);
2602 if (obj->tiling_mode != I915_TILING_NONE)
2603 dev_priv->preserve_bios_swizzle = true;
2604
be5651f2
ML
2605 drm_framebuffer_reference(fb);
2606 primary->fb = primary->state->fb = fb;
36750f28 2607 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2608 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2609 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB
2610}
2611
29b9bde6
DV
2612static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2613 struct drm_framebuffer *fb,
2614 int x, int y)
81255565
JB
2615{
2616 struct drm_device *dev = crtc->dev;
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML
2619 struct drm_plane *primary = crtc->primary;
2620 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2621 struct drm_i915_gem_object *obj;
81255565 2622 int plane = intel_crtc->plane;
e506a0c6 2623 unsigned long linear_offset;
81255565 2624 u32 dspcntr;
f45651ba 2625 u32 reg = DSPCNTR(plane);
48404c1e 2626 int pixel_size;
f45651ba 2627
b70709a6 2628 if (!visible || !fb) {
fdd508a6
VS
2629 I915_WRITE(reg, 0);
2630 if (INTEL_INFO(dev)->gen >= 4)
2631 I915_WRITE(DSPSURF(plane), 0);
2632 else
2633 I915_WRITE(DSPADDR(plane), 0);
2634 POSTING_READ(reg);
2635 return;
2636 }
2637
c9ba6fad
VS
2638 obj = intel_fb_obj(fb);
2639 if (WARN_ON(obj == NULL))
2640 return;
2641
2642 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2643
f45651ba
VS
2644 dspcntr = DISPPLANE_GAMMA_ENABLE;
2645
fdd508a6 2646 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS
2647
2648 if (INTEL_INFO(dev)->gen < 4) {
2649 if (intel_crtc->pipe == PIPE_B)
2650 dspcntr |= DISPPLANE_SEL_PIPE_B;
2651
2652 /* pipesrc and dspsize control the size that is scaled from,
2653 * which should always be the user's requested size.
2654 */
2655 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO
2656 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2657 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2658 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS
2659 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2660 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO
2661 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2662 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS
2663 I915_WRITE(PRIMPOS(plane), 0);
2664 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2665 }
81255565 2666
57779d06
VS
2667 switch (fb->pixel_format) {
2668 case DRM_FORMAT_C8:
81255565
JB
2669 dspcntr |= DISPPLANE_8BPP;
2670 break;
57779d06 2671 case DRM_FORMAT_XRGB1555:
57779d06 2672 dspcntr |= DISPPLANE_BGRX555;
81255565 2673 break;
57779d06
VS
2674 case DRM_FORMAT_RGB565:
2675 dspcntr |= DISPPLANE_BGRX565;
2676 break;
2677 case DRM_FORMAT_XRGB8888:
57779d06
VS
2678 dspcntr |= DISPPLANE_BGRX888;
2679 break;
2680 case DRM_FORMAT_XBGR8888:
57779d06
VS
2681 dspcntr |= DISPPLANE_RGBX888;
2682 break;
2683 case DRM_FORMAT_XRGB2101010:
57779d06
VS
2684 dspcntr |= DISPPLANE_BGRX101010;
2685 break;
2686 case DRM_FORMAT_XBGR2101010:
57779d06 2687 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB
2688 break;
2689 default:
baba133a 2690 BUG();
81255565 2691 }
57779d06 2692
f45651ba
VS
2693 if (INTEL_INFO(dev)->gen >= 4 &&
2694 obj->tiling_mode != I915_TILING_NONE)
2695 dspcntr |= DISPPLANE_TILED;
81255565 2696
de1aa629
VS
2697 if (IS_G4X(dev))
2698 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2699
b9897127 2700 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2701
c2c75131
DV
2702 if (INTEL_INFO(dev)->gen >= 4) {
2703 intel_crtc->dspaddr_offset =
4e9a86b6
VS
2704 intel_gen4_compute_page_offset(dev_priv,
2705 &x, &y, obj->tiling_mode,
b9897127 2706 pixel_size,
bc752862 2707 fb->pitches[0]);
c2c75131
DV
2708 linear_offset -= intel_crtc->dspaddr_offset;
2709 } else {
e506a0c6 2710 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2711 }
e506a0c6 2712
8e7d688b 2713 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ
2714 dspcntr |= DISPPLANE_ROTATE_180;
2715
6e3c9717
ACO
2716 x += (intel_crtc->config->pipe_src_w - 1);
2717 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ
2718
2719 /* Finding the last pixel of the last line of the display
2720 data and adding to linear_offset*/
2721 linear_offset +=
6e3c9717
ACO
2722 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2723 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ
2724 }
2725
2726 I915_WRITE(reg, dspcntr);
2727
01f2c773 2728 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2729 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV
2730 I915_WRITE(DSPSURF(plane),
2731 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2732 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2733 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2734 } else
f343c5f6 2735 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2736 POSTING_READ(reg);
17638cd6
JB
2737}
2738
29b9bde6
DV
2739static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2740 struct drm_framebuffer *fb,
2741 int x, int y)
17638cd6
JB
2742{
2743 struct drm_device *dev = crtc->dev;
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML
2746 struct drm_plane *primary = crtc->primary;
2747 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2748 struct drm_i915_gem_object *obj;
17638cd6 2749 int plane = intel_crtc->plane;
e506a0c6 2750 unsigned long linear_offset;
17638cd6 2751 u32 dspcntr;
f45651ba 2752 u32 reg = DSPCNTR(plane);
48404c1e 2753 int pixel_size;
f45651ba 2754
b70709a6 2755 if (!visible || !fb) {
fdd508a6
VS
2756 I915_WRITE(reg, 0);
2757 I915_WRITE(DSPSURF(plane), 0);
2758 POSTING_READ(reg);
2759 return;
2760 }
2761
c9ba6fad
VS
2762 obj = intel_fb_obj(fb);
2763 if (WARN_ON(obj == NULL))
2764 return;
2765
2766 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2767
f45651ba
VS
2768 dspcntr = DISPPLANE_GAMMA_ENABLE;
2769
fdd508a6 2770 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS
2771
2772 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2773 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2774
57779d06
VS
2775 switch (fb->pixel_format) {
2776 case DRM_FORMAT_C8:
17638cd6
JB
2777 dspcntr |= DISPPLANE_8BPP;
2778 break;
57779d06
VS
2779 case DRM_FORMAT_RGB565:
2780 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2781 break;
57779d06 2782 case DRM_FORMAT_XRGB8888:
57779d06
VS
2783 dspcntr |= DISPPLANE_BGRX888;
2784 break;
2785 case DRM_FORMAT_XBGR8888:
57779d06
VS
2786 dspcntr |= DISPPLANE_RGBX888;
2787 break;
2788 case DRM_FORMAT_XRGB2101010:
57779d06
VS
2789 dspcntr |= DISPPLANE_BGRX101010;
2790 break;
2791 case DRM_FORMAT_XBGR2101010:
57779d06 2792 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB
2793 break;
2794 default:
baba133a 2795 BUG();
17638cd6
JB
2796 }
2797
2798 if (obj->tiling_mode != I915_TILING_NONE)
2799 dspcntr |= DISPPLANE_TILED;
17638cd6 2800
f45651ba 2801 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2802 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2803
b9897127 2804 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2805 intel_crtc->dspaddr_offset =
4e9a86b6
VS
2806 intel_gen4_compute_page_offset(dev_priv,
2807 &x, &y, obj->tiling_mode,
b9897127 2808 pixel_size,
bc752862 2809 fb->pitches[0]);
c2c75131 2810 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2811 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ
2812 dspcntr |= DISPPLANE_ROTATE_180;
2813
2814 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO
2815 x += (intel_crtc->config->pipe_src_w - 1);
2816 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ
2817
2818 /* Finding the last pixel of the last line of the display
2819 data and adding to linear_offset*/
2820 linear_offset +=
6e3c9717
ACO
2821 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2822 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ
2823 }
2824 }
2825
2826 I915_WRITE(reg, dspcntr);
17638cd6 2827
01f2c773 2828 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV
2829 I915_WRITE(DSPSURF(plane),
2830 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2831 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL
2832 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2833 } else {
2834 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2835 I915_WRITE(DSPLINOFF(plane), linear_offset);
2836 }
17638cd6 2837 POSTING_READ(reg);
17638cd6
JB
2838}
2839
b321803d
DL
2840u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2841 uint32_t pixel_format)
2842{
2843 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2844
2845 /*
2846 * The stride is either expressed as a multiple of 64 bytes
2847 * chunks for linear buffers or in number of tiles for tiled
2848 * buffers.
2849 */
2850 switch (fb_modifier) {
2851 case DRM_FORMAT_MOD_NONE:
2852 return 64;
2853 case I915_FORMAT_MOD_X_TILED:
2854 if (INTEL_INFO(dev)->gen == 2)
2855 return 128;
2856 return 512;
2857 case I915_FORMAT_MOD_Y_TILED:
2858 /* No need to check for old gens and Y tiling since this is
2859 * about the display engine and those will be blocked before
2860 * we get here.
2861 */
2862 return 128;
2863 case I915_FORMAT_MOD_Yf_TILED:
2864 if (bits_per_pixel == 8)
2865 return 64;
2866 else
2867 return 128;
2868 default:
2869 MISSING_CASE(fb_modifier);
2870 return 64;
2871 }
2872}
2873
121920fa
TU
2874unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2875 struct drm_i915_gem_object *obj)
2876{
9abc4648 2877 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU
2878
2879 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2880 view = &i915_ggtt_view_rotated;
121920fa
TU
2881
2882 return i915_gem_obj_ggtt_offset_view(obj, view);
2883}
2884
e435d6e5
ML
2885static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2886{
2887 struct drm_device *dev = intel_crtc->base.dev;
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889
2890 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2891 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2892 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML
2893}
2894
a1b2278e
CK
2895/*
2896 * This function detaches (aka. unbinds) unused scalers in hardware
2897 */
0583236e 2898static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2899{
a1b2278e
CK
2900 struct intel_crtc_scaler_state *scaler_state;
2901 int i;
2902
a1b2278e
CK
2903 scaler_state = &intel_crtc->config->scaler_state;
2904
2905 /* loop through and disable scalers that aren't in use */
2906 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML
2907 if (!scaler_state->scalers[i].in_use)
2908 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK
2909 }
2910}
2911
6156a456 2912u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2913{
6156a456 2914 switch (pixel_format) {
d161cf7a 2915 case DRM_FORMAT_C8:
c34ce3d1 2916 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2917 case DRM_FORMAT_RGB565:
c34ce3d1 2918 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2919 case DRM_FORMAT_XBGR8888:
c34ce3d1 2920 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2921 case DRM_FORMAT_XRGB8888:
c34ce3d1 2922 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK
2923 /*
2924 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2925 * to be already pre-multiplied. We need to add a knob (or a different
2926 * DRM_FORMAT) for user-space to configure that.
2927 */
f75fb42a 2928 case DRM_FORMAT_ABGR8888:
c34ce3d1 2929 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2930 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2931 case DRM_FORMAT_ARGB8888:
c34ce3d1 2932 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2933 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2934 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2935 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2936 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2937 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2938 case DRM_FORMAT_YUYV:
c34ce3d1 2939 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2940 case DRM_FORMAT_YVYU:
c34ce3d1 2941 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2942 case DRM_FORMAT_UYVY:
c34ce3d1 2943 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2944 case DRM_FORMAT_VYUY:
c34ce3d1 2945 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2946 default:
4249eeef 2947 MISSING_CASE(pixel_format);
70d21f0e 2948 }
8cfcba41 2949
c34ce3d1 2950 return 0;
6156a456 2951}
70d21f0e 2952
6156a456
CK
2953u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2954{
6156a456 2955 switch (fb_modifier) {
30af77c4 2956 case DRM_FORMAT_MOD_NONE:
70d21f0e 2957 break;
30af77c4 2958 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2959 return PLANE_CTL_TILED_X;
b321803d 2960 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2961 return PLANE_CTL_TILED_Y;
b321803d 2962 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2963 return PLANE_CTL_TILED_YF;
70d21f0e 2964 default:
6156a456 2965 MISSING_CASE(fb_modifier);
70d21f0e 2966 }
8cfcba41 2967
c34ce3d1 2968 return 0;
6156a456 2969}
70d21f0e 2970
6156a456
CK
2971u32 skl_plane_ctl_rotation(unsigned int rotation)
2972{
3b7a5119 2973 switch (rotation) {
6156a456
CK
2974 case BIT(DRM_ROTATE_0):
2975 break;
1e8df167
SJ
2976 /*
2977 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2978 * while i915 HW rotation is clockwise, thats why this swapping.
2979 */
3b7a5119 2980 case BIT(DRM_ROTATE_90):
1e8df167 2981 return PLANE_CTL_ROTATE_270;
3b7a5119 2982 case BIT(DRM_ROTATE_180):
c34ce3d1 2983 return PLANE_CTL_ROTATE_180;
3b7a5119 2984 case BIT(DRM_ROTATE_270):
1e8df167 2985 return PLANE_CTL_ROTATE_90;
6156a456
CK
2986 default:
2987 MISSING_CASE(rotation);
2988 }
2989
c34ce3d1 2990 return 0;
6156a456
CK
2991}
2992
2993static void skylake_update_primary_plane(struct drm_crtc *crtc,
2994 struct drm_framebuffer *fb,
2995 int x, int y)
2996{
2997 struct drm_device *dev = crtc->dev;
2998 struct drm_i915_private *dev_priv = dev->dev_private;
2999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML
3000 struct drm_plane *plane = crtc->primary;
3001 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK
3002 struct drm_i915_gem_object *obj;
3003 int pipe = intel_crtc->pipe;
3004 u32 plane_ctl, stride_div, stride;
3005 u32 tile_height, plane_offset, plane_size;
3006 unsigned int rotation;
3007 int x_offset, y_offset;
3008 unsigned long surf_addr;
6156a456
CK
3009 struct intel_crtc_state *crtc_state = intel_crtc->config;
3010 struct intel_plane_state *plane_state;
3011 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3012 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3013 int scaler_id = -1;
3014
6156a456
CK
3015 plane_state = to_intel_plane_state(plane->state);
3016
b70709a6 3017 if (!visible || !fb) {
6156a456
CK
3018 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3019 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3020 POSTING_READ(PLANE_CTL(pipe, 0));
3021 return;
3b7a5119 3022 }
70d21f0e 3023
6156a456
CK
3024 plane_ctl = PLANE_CTL_ENABLE |
3025 PLANE_CTL_PIPE_GAMMA_ENABLE |
3026 PLANE_CTL_PIPE_CSC_ENABLE;
3027
3028 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3029 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3030 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3031
3032 rotation = plane->state->rotation;
3033 plane_ctl |= skl_plane_ctl_rotation(rotation);
3034
b321803d
DL
3035 obj = intel_fb_obj(fb);
3036 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3037 fb->pixel_format);
3b7a5119
SJ
3038 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3039
6156a456
CK
3040 /*
3041 * FIXME: intel_plane_state->src, dst aren't set when transitional
3042 * update_plane helpers are called from legacy paths.
3043 * Once full atomic crtc is available, below check can be avoided.
3044 */
3045 if (drm_rect_width(&plane_state->src)) {
3046 scaler_id = plane_state->scaler_id;
3047 src_x = plane_state->src.x1 >> 16;
3048 src_y = plane_state->src.y1 >> 16;
3049 src_w = drm_rect_width(&plane_state->src) >> 16;
3050 src_h = drm_rect_height(&plane_state->src) >> 16;
3051 dst_x = plane_state->dst.x1;
3052 dst_y = plane_state->dst.y1;
3053 dst_w = drm_rect_width(&plane_state->dst);
3054 dst_h = drm_rect_height(&plane_state->dst);
3055
3056 WARN_ON(x != src_x || y != src_y);
3057 } else {
3058 src_w = intel_crtc->config->pipe_src_w;
3059 src_h = intel_crtc->config->pipe_src_h;
3060 }
3061
3b7a5119
SJ
3062 if (intel_rotation_90_or_270(rotation)) {
3063 /* stride = Surface height in tiles */
2614f17d 3064 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ
3065 fb->modifier[0]);
3066 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3067 x_offset = stride * tile_height - y - src_h;
3b7a5119 3068 y_offset = x;
6156a456 3069 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ
3070 } else {
3071 stride = fb->pitches[0] / stride_div;
3072 x_offset = x;
3073 y_offset = y;
6156a456 3074 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ
3075 }
3076 plane_offset = y_offset << 16 | x_offset;
b321803d 3077
70d21f0e 3078 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ
3079 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3080 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3081 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK
3082
3083 if (scaler_id >= 0) {
3084 uint32_t ps_ctrl = 0;
3085
3086 WARN_ON(!dst_w || !dst_h);
3087 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3088 crtc_state->scaler_state.scalers[scaler_id].mode;
3089 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3090 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3091 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3092 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3093 I915_WRITE(PLANE_POS(pipe, 0), 0);
3094 } else {
3095 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3096 }
3097
121920fa 3098 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL
3099
3100 POSTING_READ(PLANE_SURF(pipe, 0));
3101}
3102
17638cd6
JB
3103/* Assume fb object is pinned & idle & fenced and just update base pointers */
3104static int
3105intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3106 int x, int y, enum mode_set_atomic state)
3107{
3108 struct drm_device *dev = crtc->dev;
3109 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3110
ff2a3117 3111 if (dev_priv->fbc.disable_fbc)
7733b49b 3112 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3113
29b9bde6
DV
3114 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3115
3116 return 0;
81255565
JB
3117}
3118
7514747d 3119static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3120{
96a02917
VS
3121 struct drm_crtc *crtc;
3122
70e1e0ec 3123 for_each_crtc(dev, crtc) {
96a02917
VS
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125 enum plane plane = intel_crtc->plane;
3126
3127 intel_prepare_page_flip(dev, plane);
3128 intel_finish_page_flip_plane(dev, plane);
3129 }
7514747d
VS
3130}
3131
3132static void intel_update_primary_planes(struct drm_device *dev)
3133{
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct drm_crtc *crtc;
96a02917 3136
70e1e0ec 3137 for_each_crtc(dev, crtc) {
96a02917
VS
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139
51fd371b 3140 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW
3141 /*
3142 * FIXME: Once we have proper support for primary planes (and
3143 * disabling them without disabling the entire crtc) allow again
66e514c1 3144 * a NULL crtc->primary->fb.
947fdaad 3145 */
f4510a27 3146 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3147 dev_priv->display.update_primary_plane(crtc,
66e514c1 3148 crtc->primary->fb,
262ca2b0
MR
3149 crtc->x,
3150 crtc->y);
51fd371b 3151 drm_modeset_unlock(&crtc->mutex);
96a02917
VS
3152 }
3153}
3154
7514747d
VS
3155void intel_prepare_reset(struct drm_device *dev)
3156{
3157 /* no reset support for gen2 */
3158 if (IS_GEN2(dev))
3159 return;
3160
3161 /* reset doesn't touch the display */
3162 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3163 return;
3164
3165 drm_modeset_lock_all(dev);
f98ce92f
VS
3166 /*
3167 * Disabling the crtcs gracefully seems nicer. Also the
3168 * g33 docs say we should at least disable all the planes.
3169 */
6b72d486 3170 intel_display_suspend(dev);
7514747d
VS
3171}
3172
3173void intel_finish_reset(struct drm_device *dev)
3174{
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177 /*
3178 * Flips in the rings will be nuked by the reset,
3179 * so complete all pending flips so that user space
3180 * will get its events and not get stuck.
3181 */
3182 intel_complete_page_flips(dev);
3183
3184 /* no reset support for gen2 */
3185 if (IS_GEN2(dev))
3186 return;
3187
3188 /* reset doesn't touch the display */
3189 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3190 /*
3191 * Flips in the rings have been nuked by the reset,
3192 * so update the base address of all primary
3193 * planes to the the last fb to make sure we're
3194 * showing the correct fb after a reset.
3195 */
3196 intel_update_primary_planes(dev);
3197 return;
3198 }
3199
3200 /*
3201 * The display has been reset as well,
3202 * so need a full re-initialization.
3203 */
3204 intel_runtime_pm_disable_interrupts(dev_priv);
3205 intel_runtime_pm_enable_interrupts(dev_priv);
3206
3207 intel_modeset_init_hw(dev);
3208
3209 spin_lock_irq(&dev_priv->irq_lock);
3210 if (dev_priv->display.hpd_irq_setup)
3211 dev_priv->display.hpd_irq_setup(dev);
3212 spin_unlock_irq(&dev_priv->irq_lock);
3213
043e9bda 3214 intel_display_resume(dev);
7514747d
VS
3215
3216 intel_hpd_init(dev_priv);
3217
3218 drm_modeset_unlock_all(dev);
3219}
3220
2e2f351d 3221static void
14667a4b
CW
3222intel_finish_fb(struct drm_framebuffer *old_fb)
3223{
2ff8fde1 3224 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3225 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW
3226 bool was_interruptible = dev_priv->mm.interruptible;
3227 int ret;
3228
14667a4b
CW
3229 /* Big Hammer, we also need to ensure that any pending
3230 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3231 * current scanout is retired before unpinning the old
2e2f351d
CW
3232 * framebuffer. Note that we rely on userspace rendering
3233 * into the buffer attached to the pipe they are waiting
3234 * on. If not, userspace generates a GPU hang with IPEHR
3235 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW
3236 *
3237 * This should only fail upon a hung GPU, in which case we
3238 * can safely continue.
3239 */
3240 dev_priv->mm.interruptible = false;
2e2f351d 3241 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW
3242 dev_priv->mm.interruptible = was_interruptible;
3243
2e2f351d 3244 WARN_ON(ret);
14667a4b
CW
3245}
3246
7d5e3799
CW
3247static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3248{
3249 struct drm_device *dev = crtc->dev;
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW
3252 bool pending;
3253
3254 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3255 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3256 return false;
3257
5e2d7afc 3258 spin_lock_irq(&dev->event_lock);
7d5e3799 3259 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3260 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW
3261
3262 return pending;
3263}
3264
e30e8f75
GP
3265static void intel_update_pipe_size(struct intel_crtc *crtc)
3266{
3267 struct drm_device *dev = crtc->base.dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 const struct drm_display_mode *adjusted_mode;
3270
3271 if (!i915.fastboot)
3272 return;
3273
3274 /*
3275 * Update pipe size and adjust fitter if needed: the reason for this is
3276 * that in compute_mode_changes we check the native mode (not the pfit
3277 * mode) to see if we can flip rather than do a full mode set. In the
3278 * fastboot case, we'll flip, but if we don't update the pipesrc and
3279 * pfit state, we'll end up with a big fb scanned out into the wrong
3280 * sized surface.
3281 *
3282 * To fix this properly, we need to hoist the checks up into
3283 * compute_mode_changes (or above), check the actual pfit state and
3284 * whether the platform allows pfit disable with pipe active, and only
3285 * then update the pipesrc and pfit state, even on the flip path.
3286 */
3287
6e3c9717 3288 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP
3289
3290 I915_WRITE(PIPESRC(crtc->pipe),
3291 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3292 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3293 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO
3294 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3295 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP
3296 I915_WRITE(PF_CTL(crtc->pipe), 0);
3297 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3298 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3299 }
6e3c9717
ACO
3300 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3301 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP
3302}
3303
5e84e1a4
ZW
3304static void intel_fdi_normal_train(struct drm_crtc *crtc)
3305{
3306 struct drm_device *dev = crtc->dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309 int pipe = intel_crtc->pipe;
3310 u32 reg, temp;
3311
3312 /* enable normal train */
3313 reg = FDI_TX_CTL(pipe);
3314 temp = I915_READ(reg);
61e499bf 3315 if (IS_IVYBRIDGE(dev)) {
357555c0
JB
3316 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3317 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP
3318 } else {
3319 temp &= ~FDI_LINK_TRAIN_NONE;
3320 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3321 }
5e84e1a4
ZW
3322 I915_WRITE(reg, temp);
3323
3324 reg = FDI_RX_CTL(pipe);
3325 temp = I915_READ(reg);
3326 if (HAS_PCH_CPT(dev)) {
3327 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3328 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3329 } else {
3330 temp &= ~FDI_LINK_TRAIN_NONE;
3331 temp |= FDI_LINK_TRAIN_NONE;
3332 }
3333 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3334
3335 /* wait one idle pattern time */
3336 POSTING_READ(reg);
3337 udelay(1000);
357555c0
JB
3338
3339 /* IVB wants error correction enabled */
3340 if (IS_IVYBRIDGE(dev))
3341 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3342 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW
3343}
3344
8db9d77b
ZW
3345/* The FDI link training functions for ILK/Ibexpeak. */
3346static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3347{
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 int pipe = intel_crtc->pipe;
5eddb70b 3352 u32 reg, temp, tries;
8db9d77b 3353
1c8562f6 3354 /* FDI needs bits from pipe first */
0fc932b8 3355 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3356
e1a44743
AJ
3357 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3358 for train result */
5eddb70b
CW
3359 reg = FDI_RX_IMR(pipe);
3360 temp = I915_READ(reg);
e1a44743
AJ
3361 temp &= ~FDI_RX_SYMBOL_LOCK;
3362 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3363 I915_WRITE(reg, temp);
3364 I915_READ(reg);
e1a44743
AJ
3365 udelay(150);
3366
8db9d77b 3367 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3368 reg = FDI_TX_CTL(pipe);
3369 temp = I915_READ(reg);
627eb5a3 3370 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3371 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW
3372 temp &= ~FDI_LINK_TRAIN_NONE;
3373 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3374 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3375
5eddb70b
CW
3376 reg = FDI_RX_CTL(pipe);
3377 temp = I915_READ(reg);
8db9d77b
ZW
3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW
3380 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3381
3382 POSTING_READ(reg);
8db9d77b
ZW
3383 udelay(150);
3384
5b2adf89 3385 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV
3386 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3387 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3388 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3389
5eddb70b 3390 reg = FDI_RX_IIR(pipe);
e1a44743 3391 for (tries = 0; tries < 5; tries++) {
5eddb70b 3392 temp = I915_READ(reg);
8db9d77b
ZW
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394
3395 if ((temp & FDI_RX_BIT_LOCK)) {
3396 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3397 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
3398 break;
3399 }
8db9d77b 3400 }
e1a44743 3401 if (tries == 5)
5eddb70b 3402 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3403
3404 /* Train 2 */
5eddb70b
CW
3405 reg = FDI_TX_CTL(pipe);
3406 temp = I915_READ(reg);
8db9d77b
ZW
3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3409 I915_WRITE(reg, temp);
8db9d77b 3410
5eddb70b
CW
3411 reg = FDI_RX_CTL(pipe);
3412 temp = I915_READ(reg);
8db9d77b
ZW
3413 temp &= ~FDI_LINK_TRAIN_NONE;
3414 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3415 I915_WRITE(reg, temp);
8db9d77b 3416
5eddb70b
CW
3417 POSTING_READ(reg);
3418 udelay(150);
8db9d77b 3419
5eddb70b 3420 reg = FDI_RX_IIR(pipe);
e1a44743 3421 for (tries = 0; tries < 5; tries++) {
5eddb70b 3422 temp = I915_READ(reg);
8db9d77b
ZW
3423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3424
3425 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3426 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
3427 DRM_DEBUG_KMS("FDI train 2 done.\n");
3428 break;
3429 }
8db9d77b 3430 }
e1a44743 3431 if (tries == 5)
5eddb70b 3432 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3433
3434 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3435
8db9d77b
ZW
3436}
3437
0206e353 3438static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW
3439 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3440 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3441 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3442 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3443};
3444
3445/* The FDI link training functions for SNB/Cougarpoint. */
3446static void gen6_fdi_link_train(struct drm_crtc *crtc)
3447{
3448 struct drm_device *dev = crtc->dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451 int pipe = intel_crtc->pipe;
fa37d39e 3452 u32 reg, temp, i, retry;
8db9d77b 3453
e1a44743
AJ
3454 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3455 for train result */
5eddb70b
CW
3456 reg = FDI_RX_IMR(pipe);
3457 temp = I915_READ(reg);
e1a44743
AJ
3458 temp &= ~FDI_RX_SYMBOL_LOCK;
3459 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3460 I915_WRITE(reg, temp);
3461
3462 POSTING_READ(reg);
e1a44743
AJ
3463 udelay(150);
3464
8db9d77b 3465 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
627eb5a3 3468 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3469 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW
3470 temp &= ~FDI_LINK_TRAIN_NONE;
3471 temp |= FDI_LINK_TRAIN_PATTERN_1;
3472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3473 /* SNB-B */
3474 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3475 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3476
d74cf324
DV
3477 I915_WRITE(FDI_RX_MISC(pipe),
3478 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3479
5eddb70b
CW
3480 reg = FDI_RX_CTL(pipe);
3481 temp = I915_READ(reg);
8db9d77b
ZW
3482 if (HAS_PCH_CPT(dev)) {
3483 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3484 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3485 } else {
3486 temp &= ~FDI_LINK_TRAIN_NONE;
3487 temp |= FDI_LINK_TRAIN_PATTERN_1;
3488 }
5eddb70b
CW
3489 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3490
3491 POSTING_READ(reg);
8db9d77b
ZW
3492 udelay(150);
3493
0206e353 3494 for (i = 0; i < 4; i++) {
5eddb70b
CW
3495 reg = FDI_TX_CTL(pipe);
3496 temp = I915_READ(reg);
8db9d77b
ZW
3497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3498 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
8db9d77b
ZW
3502 udelay(500);
3503
fa37d39e
SP
3504 for (retry = 0; retry < 5; retry++) {
3505 reg = FDI_RX_IIR(pipe);
3506 temp = I915_READ(reg);
3507 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3508 if (temp & FDI_RX_BIT_LOCK) {
3509 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3510 DRM_DEBUG_KMS("FDI train 1 done.\n");
3511 break;
3512 }
3513 udelay(50);
8db9d77b 3514 }
fa37d39e
SP
3515 if (retry < 5)
3516 break;
8db9d77b
ZW
3517 }
3518 if (i == 4)
5eddb70b 3519 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3520
3521 /* Train 2 */
5eddb70b
CW
3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
8db9d77b
ZW
3524 temp &= ~FDI_LINK_TRAIN_NONE;
3525 temp |= FDI_LINK_TRAIN_PATTERN_2;
3526 if (IS_GEN6(dev)) {
3527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3528 /* SNB-B */
3529 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3530 }
5eddb70b 3531 I915_WRITE(reg, temp);
8db9d77b 3532
5eddb70b
CW
3533 reg = FDI_RX_CTL(pipe);
3534 temp = I915_READ(reg);
8db9d77b
ZW
3535 if (HAS_PCH_CPT(dev)) {
3536 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3537 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3538 } else {
3539 temp &= ~FDI_LINK_TRAIN_NONE;
3540 temp |= FDI_LINK_TRAIN_PATTERN_2;
3541 }
5eddb70b
CW
3542 I915_WRITE(reg, temp);
3543
3544 POSTING_READ(reg);
8db9d77b
ZW
3545 udelay(150);
3546
0206e353 3547 for (i = 0; i < 4; i++) {
5eddb70b
CW
3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
8db9d77b
ZW
3550 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3551 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3552 I915_WRITE(reg, temp);
3553
3554 POSTING_READ(reg);
8db9d77b
ZW
3555 udelay(500);
3556
fa37d39e
SP
3557 for (retry = 0; retry < 5; retry++) {
3558 reg = FDI_RX_IIR(pipe);
3559 temp = I915_READ(reg);
3560 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3561 if (temp & FDI_RX_SYMBOL_LOCK) {
3562 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3563 DRM_DEBUG_KMS("FDI train 2 done.\n");
3564 break;
3565 }
3566 udelay(50);
8db9d77b 3567 }
fa37d39e
SP
3568 if (retry < 5)
3569 break;
8db9d77b
ZW
3570 }
3571 if (i == 4)
5eddb70b 3572 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3573
3574 DRM_DEBUG_KMS("FDI train done.\n");
3575}
3576
357555c0
JB
3577/* Manual link training for Ivy Bridge A0 parts */
3578static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3579{
3580 struct drm_device *dev = crtc->dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 int pipe = intel_crtc->pipe;
139ccd3f 3584 u32 reg, temp, i, j;
357555c0
JB
3585
3586 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3587 for train result */
3588 reg = FDI_RX_IMR(pipe);
3589 temp = I915_READ(reg);
3590 temp &= ~FDI_RX_SYMBOL_LOCK;
3591 temp &= ~FDI_RX_BIT_LOCK;
3592 I915_WRITE(reg, temp);
3593
3594 POSTING_READ(reg);
3595 udelay(150);
3596
01a415fd
DV
3597 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3598 I915_READ(FDI_RX_IIR(pipe)));
3599
139ccd3f
JB
3600 /* Try each vswing and preemphasis setting twice before moving on */
3601 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3602 /* disable first in case we need to retry */
3603 reg = FDI_TX_CTL(pipe);
3604 temp = I915_READ(reg);
3605 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3606 temp &= ~FDI_TX_ENABLE;
3607 I915_WRITE(reg, temp);
357555c0 3608
139ccd3f
JB
3609 reg = FDI_RX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 temp &= ~FDI_LINK_TRAIN_AUTO;
3612 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3613 temp &= ~FDI_RX_ENABLE;
3614 I915_WRITE(reg, temp);
357555c0 3615
139ccd3f 3616 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
139ccd3f 3619 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3620 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3621 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB
3623 temp |= snb_b_fdi_train_param[j/2];
3624 temp |= FDI_COMPOSITE_SYNC;
3625 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3626
139ccd3f
JB
3627 I915_WRITE(FDI_RX_MISC(pipe),
3628 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3629
139ccd3f 3630 reg = FDI_RX_CTL(pipe);
357555c0 3631 temp = I915_READ(reg);
139ccd3f
JB
3632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3633 temp |= FDI_COMPOSITE_SYNC;
3634 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3635
139ccd3f
JB
3636 POSTING_READ(reg);
3637 udelay(1); /* should be 0.5us */
357555c0 3638
139ccd3f
JB
3639 for (i = 0; i < 4; i++) {
3640 reg = FDI_RX_IIR(pipe);
3641 temp = I915_READ(reg);
3642 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3643
139ccd3f
JB
3644 if (temp & FDI_RX_BIT_LOCK ||
3645 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3646 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3647 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3648 i);
3649 break;
3650 }
3651 udelay(1); /* should be 0.5us */
3652 }
3653 if (i == 4) {
3654 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3655 continue;
3656 }
357555c0 3657
139ccd3f 3658 /* Train 2 */
357555c0
JB
3659 reg = FDI_TX_CTL(pipe);
3660 temp = I915_READ(reg);
139ccd3f
JB
3661 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3662 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3663 I915_WRITE(reg, temp);
3664
3665 reg = FDI_RX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3668 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB
3669 I915_WRITE(reg, temp);
3670
3671 POSTING_READ(reg);
139ccd3f 3672 udelay(2); /* should be 1.5us */
357555c0 3673
139ccd3f
JB
3674 for (i = 0; i < 4; i++) {
3675 reg = FDI_RX_IIR(pipe);
3676 temp = I915_READ(reg);
3677 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3678
139ccd3f
JB
3679 if (temp & FDI_RX_SYMBOL_LOCK ||
3680 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3681 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3682 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3683 i);
3684 goto train_done;
3685 }
3686 udelay(2); /* should be 1.5us */
357555c0 3687 }
139ccd3f
JB
3688 if (i == 4)
3689 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3690 }
357555c0 3691
139ccd3f 3692train_done:
357555c0
JB
3693 DRM_DEBUG_KMS("FDI train done.\n");
3694}
3695
88cefb6c 3696static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3697{
88cefb6c 3698 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3699 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3700 int pipe = intel_crtc->pipe;
5eddb70b 3701 u32 reg, temp;
79e53945 3702
c64e311e 3703
c98e9dcf 3704 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW
3705 reg = FDI_RX_CTL(pipe);
3706 temp = I915_READ(reg);
627eb5a3 3707 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3708 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3709 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW
3710 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3711
3712 POSTING_READ(reg);
c98e9dcf
JB
3713 udelay(200);
3714
3715 /* Switch from Rawclk to PCDclk */
5eddb70b
CW
3716 temp = I915_READ(reg);
3717 I915_WRITE(reg, temp | FDI_PCDCLK);
3718
3719 POSTING_READ(reg);
c98e9dcf
JB
3720 udelay(200);
3721
20749730
PZ
3722 /* Enable CPU FDI TX PLL, always on for Ironlake */
3723 reg = FDI_TX_CTL(pipe);
3724 temp = I915_READ(reg);
3725 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3726 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3727
20749730
PZ
3728 POSTING_READ(reg);
3729 udelay(100);
6be4a607 3730 }
0e23b99d
JB
3731}
3732
88cefb6c
DV
3733static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3734{
3735 struct drm_device *dev = intel_crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 int pipe = intel_crtc->pipe;
3738 u32 reg, temp;
3739
3740 /* Switch from PCDclk to Rawclk */
3741 reg = FDI_RX_CTL(pipe);
3742 temp = I915_READ(reg);
3743 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3744
3745 /* Disable CPU FDI TX PLL */
3746 reg = FDI_TX_CTL(pipe);
3747 temp = I915_READ(reg);
3748 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3749
3750 POSTING_READ(reg);
3751 udelay(100);
3752
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3756
3757 /* Wait for the clocks to turn off. */
3758 POSTING_READ(reg);
3759 udelay(100);
3760}
3761
0fc932b8
JB
3762static void ironlake_fdi_disable(struct drm_crtc *crtc)
3763{
3764 struct drm_device *dev = crtc->dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767 int pipe = intel_crtc->pipe;
3768 u32 reg, temp;
3769
3770 /* disable CPU FDI tx and PCH FDI rx */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3774 POSTING_READ(reg);
3775
3776 reg = FDI_RX_CTL(pipe);
3777 temp = I915_READ(reg);
3778 temp &= ~(0x7 << 16);
dfd07d72 3779 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
3780 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3781
3782 POSTING_READ(reg);
3783 udelay(100);
3784
3785 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3786 if (HAS_PCH_IBX(dev))
6f06ce18 3787 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB
3788
3789 /* still set train pattern 1 */
3790 reg = FDI_TX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~FDI_LINK_TRAIN_NONE;
3793 temp |= FDI_LINK_TRAIN_PATTERN_1;
3794 I915_WRITE(reg, temp);
3795
3796 reg = FDI_RX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 if (HAS_PCH_CPT(dev)) {
3799 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3800 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3801 } else {
3802 temp &= ~FDI_LINK_TRAIN_NONE;
3803 temp |= FDI_LINK_TRAIN_PATTERN_1;
3804 }
3805 /* BPC in FDI rx is consistent with that in PIPECONF */
3806 temp &= ~(0x07 << 16);
dfd07d72 3807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
3808 I915_WRITE(reg, temp);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812}
3813
5dce5b93
CW
3814bool intel_has_pending_fb_unpin(struct drm_device *dev)
3815{
3816 struct intel_crtc *crtc;
3817
3818 /* Note that we don't need to be called with mode_config.lock here
3819 * as our list of CRTC objects is static for the lifetime of the
3820 * device and so cannot disappear as we iterate. Similarly, we can
3821 * happily treat the predicates as racy, atomic checks as userspace
3822 * cannot claim and pin a new fb without at least acquring the
3823 * struct_mutex and so serialising with us.
3824 */
d3fcc808 3825 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW
3826 if (atomic_read(&crtc->unpin_work_count) == 0)
3827 continue;
3828
3829 if (crtc->unpin_work)
3830 intel_wait_for_vblank(dev, crtc->pipe);
3831
3832 return true;
3833 }
3834
3835 return false;
3836}
3837
d6bbafa1
CW
3838static void page_flip_completed(struct intel_crtc *intel_crtc)
3839{
3840 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3841 struct intel_unpin_work *work = intel_crtc->unpin_work;
3842
3843 /* ensure that the unpin work is consistent wrt ->pending. */
3844 smp_rmb();
3845 intel_crtc->unpin_work = NULL;
3846
3847 if (work->event)
3848 drm_send_vblank_event(intel_crtc->base.dev,
3849 intel_crtc->pipe,
3850 work->event);
3851
3852 drm_crtc_vblank_put(&intel_crtc->base);
3853
3854 wake_up_all(&dev_priv->pending_flip_queue);
3855 queue_work(dev_priv->wq, &work->work);
3856
3857 trace_i915_flip_complete(intel_crtc->plane,
3858 work->pending_flip_obj);
3859}
3860
46a55d30 3861void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3862{
0f91128d 3863 struct drm_device *dev = crtc->dev;
5bb61643 3864 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3865
2c10d571 3866 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW
3867 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3868 !intel_crtc_has_pending_flip(crtc),
3869 60*HZ) == 0)) {
3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3871
5e2d7afc 3872 spin_lock_irq(&dev->event_lock);
9c787942
CW
3873 if (intel_crtc->unpin_work) {
3874 WARN_ONCE(1, "Removing stuck page flip\n");
3875 page_flip_completed(intel_crtc);
3876 }
5e2d7afc 3877 spin_unlock_irq(&dev->event_lock);
9c787942 3878 }
5bb61643 3879
975d568a
CW
3880 if (crtc->primary->fb) {
3881 mutex_lock(&dev->struct_mutex);
3882 intel_finish_fb(crtc->primary->fb);
3883 mutex_unlock(&dev->struct_mutex);
3884 }
e6c3a2a6
CW
3885}
3886
e615efe4
ED
3887/* Program iCLKIP clock to the desired frequency */
3888static void lpt_program_iclkip(struct drm_crtc *crtc)
3889{
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3892 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED
3893 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3894 u32 temp;
3895
a580516d 3896 mutex_lock(&dev_priv->sb_lock);
09153000 3897
e615efe4
ED
3898 /* It is necessary to ungate the pixclk gate prior to programming
3899 * the divisors, and gate it back when it is done.
3900 */
3901 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3902
3903 /* Disable SSCCTL */
3904 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ
3905 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3906 SBI_SSCCTL_DISABLE,
3907 SBI_ICLK);
e615efe4
ED
3908
3909 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3910 if (clock == 20000) {
e615efe4
ED
3911 auxdiv = 1;
3912 divsel = 0x41;
3913 phaseinc = 0x20;
3914 } else {
3915 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL
3916 * but the adjusted_mode->crtc_clock in in KHz. To get the
3917 * divisors, it is necessary to divide one by another, so we
e615efe4
ED
3918 * convert the virtual clock precision to KHz here for higher
3919 * precision.
3920 */
3921 u32 iclk_virtual_root_freq = 172800 * 1000;
3922 u32 iclk_pi_range = 64;
3923 u32 desired_divisor, msb_divisor_value, pi_value;
3924
12d7ceed 3925 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED
3926 msb_divisor_value = desired_divisor / iclk_pi_range;
3927 pi_value = desired_divisor % iclk_pi_range;
3928
3929 auxdiv = 0;
3930 divsel = msb_divisor_value - 2;
3931 phaseinc = pi_value;
3932 }
3933
3934 /* This should not happen with any sane values */
3935 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3936 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3937 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3938 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3939
3940 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3941 clock,
e615efe4
ED
3942 auxdiv,
3943 divsel,
3944 phasedir,
3945 phaseinc);
3946
3947 /* Program SSCDIVINTPHASE6 */
988d6ee8 3948 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED
3949 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3950 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3951 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3952 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3953 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3954 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3955 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED
3956
3957 /* Program SSCAUXDIV */
988d6ee8 3958 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED
3959 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3960 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3961 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED
3962
3963 /* Enable modulator and associated divider */
988d6ee8 3964 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3965 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3966 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED
3967
3968 /* Wait for initialization time */
3969 udelay(24);
3970
3971 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3972
a580516d 3973 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED
3974}
3975
275f01b2
DV
3976static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3977 enum pipe pch_transcoder)
3978{
3979 struct drm_device *dev = crtc->base.dev;
3980 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3981 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV
3982
3983 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3984 I915_READ(HTOTAL(cpu_transcoder)));
3985 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3986 I915_READ(HBLANK(cpu_transcoder)));
3987 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3988 I915_READ(HSYNC(cpu_transcoder)));
3989
3990 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3991 I915_READ(VTOTAL(cpu_transcoder)));
3992 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3993 I915_READ(VBLANK(cpu_transcoder)));
3994 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3995 I915_READ(VSYNC(cpu_transcoder)));
3996 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3997 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3998}
3999
003632d9 4000static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV
4001{
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4003 uint32_t temp;
4004
4005 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4006 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV
4007 return;
4008
4009 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4010 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4011
003632d9
ACO
4012 temp &= ~FDI_BC_BIFURCATION_SELECT;
4013 if (enable)
4014 temp |= FDI_BC_BIFURCATION_SELECT;
4015
4016 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV
4017 I915_WRITE(SOUTH_CHICKEN1, temp);
4018 POSTING_READ(SOUTH_CHICKEN1);
4019}
4020
4021static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4022{
4023 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV
4024
4025 switch (intel_crtc->pipe) {
4026 case PIPE_A:
4027 break;
4028 case PIPE_B:
6e3c9717 4029 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4030 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4031 else
003632d9 4032 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4033
4034 break;
4035 case PIPE_C:
003632d9 4036 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4037
4038 break;
4039 default:
4040 BUG();
4041 }
4042}
4043
f67a559d
JB
4044/*
4045 * Enable PCH resources required for PCH ports:
4046 * - PCH PLLs
4047 * - FDI training & RX/TX
4048 * - update transcoder timings
4049 * - DP transcoding bits
4050 * - transcoder
4051 */
4052static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB
4053{
4054 struct drm_device *dev = crtc->dev;
4055 struct drm_i915_private *dev_priv = dev->dev_private;
4056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4057 int pipe = intel_crtc->pipe;
ee7b9f93 4058 u32 reg, temp;
2c07245f 4059
ab9412ba 4060 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4061
1fbc0d78
DV
4062 if (IS_IVYBRIDGE(dev))
4063 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4064
cd986abb
DV
4065 /* Write the TU size bits before fdi link training, so that error
4066 * detection works. */
4067 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4068 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4069
c98e9dcf 4070 /* For PCH output, training FDI link */
674cf967 4071 dev_priv->display.fdi_link_train(crtc);
2c07245f 4072
3ad8a208
DV
4073 /* We need to program the right clock selection before writing the pixel
4074 * mutliplier into the DPLL. */
303b81e0 4075 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4076 u32 sel;
4b645f14 4077
c98e9dcf 4078 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV
4079 temp |= TRANS_DPLL_ENABLE(pipe);
4080 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4081 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB
4082 temp |= sel;
4083 else
4084 temp &= ~sel;
c98e9dcf 4085 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4086 }
5eddb70b 4087
3ad8a208
DV
4088 /* XXX: pch pll's can be enabled any time before we enable the PCH
4089 * transcoder, and we actually should do this to not upset any PCH
4090 * transcoder that already use the clock when we share it.
4091 *
4092 * Note that enable_shared_dpll tries to do the right thing, but
4093 * get_shared_dpll unconditionally resets the pll - we need that to have
4094 * the right LVDS enable sequence. */
85b3894f 4095 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4096
d9b6cb56
JB
4097 /* set transcoder timing, panel must allow it */
4098 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4099 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4100
303b81e0 4101 intel_fdi_normal_train(crtc);
5e84e1a4 4102
c98e9dcf 4103 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4104 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4105 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW
4106 reg = TRANS_DP_CTL(pipe);
4107 temp = I915_READ(reg);
4108 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA
4109 TRANS_DP_SYNC_MASK |
4110 TRANS_DP_BPC_MASK);
e3ef4479 4111 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4112 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB
4113
4114 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4115 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4116 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4117 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB
4118
4119 switch (intel_trans_dp_port_sel(crtc)) {
4120 case PCH_DP_B:
5eddb70b 4121 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB
4122 break;
4123 case PCH_DP_C:
5eddb70b 4124 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB
4125 break;
4126 case PCH_DP_D:
5eddb70b 4127 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB
4128 break;
4129 default:
e95d41e1 4130 BUG();
32f9d658 4131 }
2c07245f 4132
5eddb70b 4133 I915_WRITE(reg, temp);
6be4a607 4134 }
b52eb4dc 4135
b8a4f404 4136 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB
4137}
4138
1507e5bd
PZ
4139static void lpt_pch_enable(struct drm_crtc *crtc)
4140{
4141 struct drm_device *dev = crtc->dev;
4142 struct drm_i915_private *dev_priv = dev->dev_private;
4143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4144 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4145
ab9412ba 4146 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4147
8c52b5e8 4148 lpt_program_iclkip(crtc);
1507e5bd 4149
0540e488 4150 /* Set transcoder timing. */
275f01b2 4151 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4152
937bb610 4153 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB
4154}
4155
190f68c5
ACO
4156struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4157 struct intel_crtc_state *crtc_state)
ee7b9f93 4158{
e2b78267 4159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4160 struct intel_shared_dpll *pll;
de419ab6 4161 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4162 enum intel_dpll_id i;
ee7b9f93 4163
de419ab6
ML
4164 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4165
98b6bd99
DV
4166 if (HAS_PCH_IBX(dev_priv->dev)) {
4167 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4168 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4169 pll = &dev_priv->shared_dplls[i];
98b6bd99 4170
46edb027
DV
4171 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4172 crtc->base.base.id, pll->name);
98b6bd99 4173
de419ab6 4174 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4175
98b6bd99
DV
4176 goto found;
4177 }
4178
bcddf610
S
4179 if (IS_BROXTON(dev_priv->dev)) {
4180 /* PLL is attached to port in bxt */
4181 struct intel_encoder *encoder;
4182 struct intel_digital_port *intel_dig_port;
4183
4184 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4185 if (WARN_ON(!encoder))
4186 return NULL;
4187
4188 intel_dig_port = enc_to_dig_port(&encoder->base);
4189 /* 1:1 mapping between ports and PLLs */
4190 i = (enum intel_dpll_id)intel_dig_port->port;
4191 pll = &dev_priv->shared_dplls[i];
4192 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4193 crtc->base.base.id, pll->name);
de419ab6 4194 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S
4195
4196 goto found;
4197 }
4198
e72f9fbf
DV
4199 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4200 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB
4201
4202 /* Only want to check enabled timings first */
de419ab6 4203 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB
4204 continue;
4205
190f68c5 4206 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML
4207 &shared_dpll[i].hw_state,
4208 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4209 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4210 crtc->base.base.id, pll->name,
de419ab6 4211 shared_dpll[i].crtc_mask,
8bd31e67 4212 pll->active);
ee7b9f93
JB
4213 goto found;
4214 }
4215 }
4216
4217 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV
4218 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4219 pll = &dev_priv->shared_dplls[i];
de419ab6 4220 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV
4221 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4222 crtc->base.base.id, pll->name);
ee7b9f93
JB
4223 goto found;
4224 }
4225 }
4226
4227 return NULL;
4228
4229found:
de419ab6
ML
4230 if (shared_dpll[i].crtc_mask == 0)
4231 shared_dpll[i].hw_state =
4232 crtc_state->dpll_hw_state;
f2a69f44 4233
190f68c5 4234 crtc_state->shared_dpll = i;
46edb027
DV
4235 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4236 pipe_name(crtc->pipe));
ee7b9f93 4237
de419ab6 4238 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4239
ee7b9f93
JB
4240 return pll;
4241}
4242
de419ab6 4243static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4244{
de419ab6
ML
4245 struct drm_i915_private *dev_priv = to_i915(state->dev);
4246 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO
4247 struct intel_shared_dpll *pll;
4248 enum intel_dpll_id i;
4249
de419ab6
ML
4250 if (!to_intel_atomic_state(state)->dpll_set)
4251 return;
8bd31e67 4252
de419ab6 4253 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO
4254 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4255 pll = &dev_priv->shared_dplls[i];
de419ab6 4256 pll->config = shared_dpll[i];
8bd31e67
ACO
4257 }
4258}
4259
a1520318 4260static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB
4261{
4262 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4263 int dslreg = PIPEDSL(pipe);
d4270e57
JB
4264 u32 temp;
4265
4266 temp = I915_READ(dslreg);
4267 udelay(500);
4268 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4269 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4270 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB
4271 }
4272}
4273
86adf9d7
ML
4274static int
4275skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4276 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4277 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4278{
86adf9d7
ML
4279 struct intel_crtc_scaler_state *scaler_state =
4280 &crtc_state->scaler_state;
4281 struct intel_crtc *intel_crtc =
4282 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4283 int need_scaling;
6156a456
CK
4284
4285 need_scaling = intel_rotation_90_or_270(rotation) ?
4286 (src_h != dst_w || src_w != dst_h):
4287 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK
4288
4289 /*
4290 * if plane is being disabled or scaler is no more required or force detach
4291 * - free scaler binded to this plane/crtc
4292 * - in order to do this, update crtc->scaler_usage
4293 *
4294 * Here scaler state in crtc_state is set free so that
4295 * scaler can be assigned to other user. Actual register
4296 * update to free the scaler is done in plane/panel-fit programming.
4297 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4298 */
86adf9d7 4299 if (force_detach || !need_scaling) {
a1b2278e 4300 if (*scaler_id >= 0) {
86adf9d7 4301 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK
4302 scaler_state->scalers[*scaler_id].in_use = 0;
4303
86adf9d7
ML
4304 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4305 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4306 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK
4307 scaler_state->scaler_users);
4308 *scaler_id = -1;
4309 }
4310 return 0;
4311 }
4312
4313 /* range checks */
4314 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4315 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4316
4317 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4318 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4319 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4320 "size is out of scaler range\n",
86adf9d7 4321 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK
4322 return -EINVAL;
4323 }
4324
86adf9d7
ML
4325 /* mark this plane as a scaler user in crtc_state */
4326 scaler_state->scaler_users |= (1 << scaler_user);
4327 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4328 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4329 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4330 scaler_state->scaler_users);
4331
4332 return 0;
4333}
4334
4335/**
4336 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4337 *
4338 * @state: crtc's scaler state
86adf9d7
ML
4339 *
4340 * Return
4341 * 0 - scaler_usage updated successfully
4342 * error - requested scaling cannot be supported or other error condition
4343 */
e435d6e5 4344int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML
4345{
4346 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4347 struct drm_display_mode *adjusted_mode =
4348 &state->base.adjusted_mode;
4349
4350 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4351 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4352
e435d6e5 4353 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML
4354 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4355 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4356 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML
4357}
4358
4359/**
4360 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4361 *
4362 * @state: crtc's scaler state
86adf9d7
ML
4363 * @plane_state: atomic plane state to update
4364 *
4365 * Return
4366 * 0 - scaler_usage updated successfully
4367 * error - requested scaling cannot be supported or other error condition
4368 */
da20eabd
ML
4369static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4370 struct intel_plane_state *plane_state)
86adf9d7
ML
4371{
4372
4373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML
4374 struct intel_plane *intel_plane =
4375 to_intel_plane(plane_state->base.plane);
86adf9d7
ML
4376 struct drm_framebuffer *fb = plane_state->base.fb;
4377 int ret;
4378
4379 bool force_detach = !fb || !plane_state->visible;
4380
4381 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4382 intel_plane->base.base.id, intel_crtc->pipe,
4383 drm_plane_index(&intel_plane->base));
4384
4385 ret = skl_update_scaler(crtc_state, force_detach,
4386 drm_plane_index(&intel_plane->base),
4387 &plane_state->scaler_id,
4388 plane_state->base.rotation,
4389 drm_rect_width(&plane_state->src) >> 16,
4390 drm_rect_height(&plane_state->src) >> 16,
4391 drm_rect_width(&plane_state->dst),
4392 drm_rect_height(&plane_state->dst));
4393
4394 if (ret || plane_state->scaler_id < 0)
4395 return ret;
4396
a1b2278e 4397 /* check colorkey */
818ed961 4398 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4399 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4400 intel_plane->base.base.id);
a1b2278e
CK
4401 return -EINVAL;
4402 }
4403
4404 /* Check src format */
86adf9d7
ML
4405 switch (fb->pixel_format) {
4406 case DRM_FORMAT_RGB565:
4407 case DRM_FORMAT_XBGR8888:
4408 case DRM_FORMAT_XRGB8888:
4409 case DRM_FORMAT_ABGR8888:
4410 case DRM_FORMAT_ARGB8888:
4411 case DRM_FORMAT_XRGB2101010:
4412 case DRM_FORMAT_XBGR2101010:
4413 case DRM_FORMAT_YUYV:
4414 case DRM_FORMAT_YVYU:
4415 case DRM_FORMAT_UYVY:
4416 case DRM_FORMAT_VYUY:
4417 break;
4418 default:
4419 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4420 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4421 return -EINVAL;
a1b2278e
CK
4422 }
4423
a1b2278e
CK
4424 return 0;
4425}
4426
e435d6e5
ML
4427static void skylake_scaler_disable(struct intel_crtc *crtc)
4428{
4429 int i;
4430
4431 for (i = 0; i < crtc->num_scalers; i++)
4432 skl_detach_scaler(crtc, i);
4433}
4434
4435static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB
4436{
4437 struct drm_device *dev = crtc->base.dev;
4438 struct drm_i915_private *dev_priv = dev->dev_private;
4439 int pipe = crtc->pipe;
a1b2278e
CK
4440 struct intel_crtc_scaler_state *scaler_state =
4441 &crtc->config->scaler_state;
4442
4443 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4444
6e3c9717 4445 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK
4446 int id;
4447
4448 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4449 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4450 return;
4451 }
4452
4453 id = scaler_state->scaler_id;
4454 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4455 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4456 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4457 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4458
4459 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB
4460 }
4461}
4462
b074cec8
JB
4463static void ironlake_pfit_enable(struct intel_crtc *crtc)
4464{
4465 struct drm_device *dev = crtc->base.dev;
4466 struct drm_i915_private *dev_priv = dev->dev_private;
4467 int pipe = crtc->pipe;
4468
6e3c9717 4469 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB
4470 /* Force use of hard-coded filter coefficients
4471 * as some pre-programmed values are broken,
4472 * e.g. x201.
4473 */
4474 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4475 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4476 PF_PIPE_SEL_IVB(pipe));
4477 else
4478 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO
4479 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4480 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB
4481 }
4482}
4483
20bc8673 4484void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4485{
cea165c3
VS
4486 struct drm_device *dev = crtc->base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4488
6e3c9717 4489 if (!crtc->config->ips_enabled)
d77e4531
PZ
4490 return;
4491
cea165c3
VS
4492 /* We can only enable IPS after we enable a plane and wait for a vblank */
4493 intel_wait_for_vblank(dev, crtc->pipe);
4494
d77e4531 4495 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4496 if (IS_BROADWELL(dev)) {
2a114cc1
BW
4497 mutex_lock(&dev_priv->rps.hw_lock);
4498 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4499 mutex_unlock(&dev_priv->rps.hw_lock);
4500 /* Quoting Art Runyan: "its not safe to expect any particular
4501 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB
4502 * mailbox." Moreover, the mailbox may return a bogus state,
4503 * so we need to just enable it and continue on.
2a114cc1
BW
4504 */
4505 } else {
4506 I915_WRITE(IPS_CTL, IPS_ENABLE);
4507 /* The bit only becomes 1 in the next vblank, so this wait here
4508 * is essentially intel_wait_for_vblank. If we don't have this
4509 * and don't wait for vblanks until the end of crtc_enable, then
4510 * the HW state readout code will complain that the expected
4511 * IPS_CTL value is not the one we read. */
4512 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4513 DRM_ERROR("Timed out waiting for IPS enable\n");
4514 }
d77e4531
PZ
4515}
4516
20bc8673 4517void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ
4518{
4519 struct drm_device *dev = crtc->base.dev;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521
6e3c9717 4522 if (!crtc->config->ips_enabled)
d77e4531
PZ
4523 return;
4524
4525 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4526 if (IS_BROADWELL(dev)) {
2a114cc1
BW
4527 mutex_lock(&dev_priv->rps.hw_lock);
4528 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4529 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW
4530 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4531 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4532 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4533 } else {
2a114cc1 4534 I915_WRITE(IPS_CTL, 0);
e59150dc
JB
4535 POSTING_READ(IPS_CTL);
4536 }
d77e4531
PZ
4537
4538 /* We need to wait for a vblank before we can disable the plane. */
4539 intel_wait_for_vblank(dev, crtc->pipe);
4540}
4541
4542/** Loads the palette/gamma unit for the CRTC with the prepared values */
4543static void intel_crtc_load_lut(struct drm_crtc *crtc)
4544{
4545 struct drm_device *dev = crtc->dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4548 enum pipe pipe = intel_crtc->pipe;
4549 int palreg = PALETTE(pipe);
4550 int i;
4551 bool reenable_ips = false;
4552
4553 /* The clocks have to be on to load the palette. */
53d9f4e9 4554 if (!crtc->state->active)
d77e4531
PZ
4555 return;
4556
50360403 4557 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4558 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ
4559 assert_dsi_pll_enabled(dev_priv);
4560 else
4561 assert_pll_enabled(dev_priv, pipe);
4562 }
4563
4564 /* use legacy palette for Ironlake */
7a1db49a 4565 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ
4566 palreg = LGC_PALETTE(pipe);
4567
4568 /* Workaround : Do not read or write the pipe palette/gamma data while
4569 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4570 */
6e3c9717 4571 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ
4572 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4573 GAMMA_MODE_MODE_SPLIT)) {
4574 hsw_disable_ips(intel_crtc);
4575 reenable_ips = true;
4576 }
4577
4578 for (i = 0; i < 256; i++) {
4579 I915_WRITE(palreg + 4 * i,
4580 (intel_crtc->lut_r[i] << 16) |
4581 (intel_crtc->lut_g[i] << 8) |
4582 intel_crtc->lut_b[i]);
4583 }
4584
4585 if (reenable_ips)
4586 hsw_enable_ips(intel_crtc);
4587}
4588
7cac945f 4589static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4590{
7cac945f 4591 if (intel_crtc->overlay) {
d3eedb1a
VS
4592 struct drm_device *dev = intel_crtc->base.dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594
4595 mutex_lock(&dev->struct_mutex);
4596 dev_priv->mm.interruptible = false;
4597 (void) intel_overlay_switch_off(intel_crtc->overlay);
4598 dev_priv->mm.interruptible = true;
4599 mutex_unlock(&dev->struct_mutex);
4600 }
4601
4602 /* Let userspace switch the overlay on again. In most cases userspace
4603 * has to recompute where to put it anyway.
4604 */
4605}
4606
87d4300a
ML
4607/**
4608 * intel_post_enable_primary - Perform operations after enabling primary plane
4609 * @crtc: the CRTC whose primary plane was just enabled
4610 *
4611 * Performs potentially sleeping operations that must be done after the primary
4612 * plane is enabled, such as updating FBC and IPS. Note that this may be
4613 * called due to an explicit primary plane update, or due to an implicit
4614 * re-enable that is caused when a sprite plane is updated to no longer
4615 * completely hide the primary plane.
4616 */
4617static void
4618intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4619{
4620 struct drm_device *dev = crtc->dev;
87d4300a 4621 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS
4622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4623 int pipe = intel_crtc->pipe;
a5c4d7bc 4624
87d4300a
ML
4625 /*
4626 * BDW signals flip done immediately if the plane
4627 * is disabled, even if the plane enable is already
4628 * armed to occur at the next vblank :(
4629 */
4630 if (IS_BROADWELL(dev))
4631 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4632
87d4300a
ML
4633 /*
4634 * FIXME IPS should be fine as long as one plane is
4635 * enabled, but in practice it seems to have problems
4636 * when going from primary only to sprite only and vice
4637 * versa.
4638 */
a5c4d7bc
VS
4639 hsw_enable_ips(intel_crtc);
4640
f99d7069 4641 /*
87d4300a
ML
4642 * Gen2 reports pipe underruns whenever all planes are disabled.
4643 * So don't enable underrun reporting before at least some planes
4644 * are enabled.
4645 * FIXME: Need to fix the logic to work when we turn off all planes
4646 * but leave the pipe running.
f99d7069 4647 */
87d4300a
ML
4648 if (IS_GEN2(dev))
4649 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4650
4651 /* Underruns don't raise interrupts, so check manually. */
4652 if (HAS_GMCH_DISPLAY(dev))
4653 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS
4654}
4655
87d4300a
ML
4656/**
4657 * intel_pre_disable_primary - Perform operations before disabling primary plane
4658 * @crtc: the CRTC whose primary plane is to be disabled
4659 *
4660 * Performs potentially sleeping operations that must be done before the
4661 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4662 * be called due to an explicit primary plane update, or due to an implicit
4663 * disable that is caused when a sprite plane completely hides the primary
4664 * plane.
4665 */
4666static void
4667intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4668{
4669 struct drm_device *dev = crtc->dev;
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672 int pipe = intel_crtc->pipe;
a5c4d7bc 4673
87d4300a
ML
4674 /*
4675 * Gen2 reports pipe underruns whenever all planes are disabled.
4676 * So diasble underrun reporting before all the planes get disabled.
4677 * FIXME: Need to fix the logic to work when we turn off all planes
4678 * but leave the pipe running.
4679 */
4680 if (IS_GEN2(dev))
4681 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4682
87d4300a
ML
4683 /*
4684 * Vblank time updates from the shadow to live plane control register
4685 * are blocked if the memory self-refresh mode is active at that
4686 * moment. So to make sure the plane gets truly disabled, disable
4687 * first the self-refresh mode. The self-refresh enable bit in turn
4688 * will be checked/applied by the HW only at the next frame start
4689 * event which is after the vblank start event, so we need to have a
4690 * wait-for-vblank between disabling the plane and the pipe.
4691 */
262cd2e1 4692 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4693 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS
4694 dev_priv->wm.vlv.cxsr = false;
4695 intel_wait_for_vblank(dev, pipe);
4696 }
87d4300a 4697
87d4300a
ML
4698 /*
4699 * FIXME IPS should be fine as long as one plane is
4700 * enabled, but in practice it seems to have problems
4701 * when going from primary only to sprite only and vice
4702 * versa.
4703 */
a5c4d7bc 4704 hsw_disable_ips(intel_crtc);
87d4300a
ML
4705}
4706
ac21b225
ML
4707static void intel_post_plane_update(struct intel_crtc *crtc)
4708{
4709 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4710 struct drm_device *dev = crtc->base.dev;
7733b49b 4711 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML
4712 struct drm_plane *plane;
4713
4714 if (atomic->wait_vblank)
4715 intel_wait_for_vblank(dev, crtc->pipe);
4716
4717 intel_frontbuffer_flip(dev, atomic->fb_bits);
4718
852eb00d
VS
4719 if (atomic->disable_cxsr)
4720 crtc->wm.cxsr_allowed = true;
4721
f015c551
VS
4722 if (crtc->atomic.update_wm_post)
4723 intel_update_watermarks(&crtc->base);
4724
c80ac854 4725 if (atomic->update_fbc)
7733b49b 4726 intel_fbc_update(dev_priv);
ac21b225
ML
4727
4728 if (atomic->post_enable_primary)
4729 intel_post_enable_primary(&crtc->base);
4730
4731 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4732 intel_update_sprite_watermarks(plane, &crtc->base,
4733 0, 0, 0, false, false);
4734
4735 memset(atomic, 0, sizeof(*atomic));
4736}
4737
4738static void intel_pre_plane_update(struct intel_crtc *crtc)
4739{
4740 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4741 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML
4742 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4743 struct drm_plane *p;
4744
4745 /* Track fb's for any planes being disabled */
ac21b225
ML
4746 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4747 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML
4748
4749 mutex_lock(&dev->struct_mutex);
a9ff8714
VS
4750 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4751 plane->frontbuffer_bit);
ac21b225
ML
4752 mutex_unlock(&dev->struct_mutex);
4753 }
4754
4755 if (atomic->wait_for_flips)
4756 intel_crtc_wait_for_pending_flips(&crtc->base);
4757
c80ac854 4758 if (atomic->disable_fbc)
25ad93fd 4759 intel_fbc_disable_crtc(crtc);
ac21b225 4760
066cf55b
RV
4761 if (crtc->atomic.disable_ips)
4762 hsw_disable_ips(crtc);
4763
ac21b225
ML
4764 if (atomic->pre_disable_primary)
4765 intel_pre_disable_primary(&crtc->base);
852eb00d
VS
4766
4767 if (atomic->disable_cxsr) {
4768 crtc->wm.cxsr_allowed = false;
4769 intel_set_memory_cxsr(dev_priv, false);
4770 }
ac21b225
ML
4771}
4772
d032ffa0 4773static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML
4774{
4775 struct drm_device *dev = crtc->dev;
4776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4777 struct drm_plane *p;
87d4300a
ML
4778 int pipe = intel_crtc->pipe;
4779
7cac945f 4780 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4781
d032ffa0
ML
4782 drm_for_each_plane_mask(p, dev, plane_mask)
4783 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4784
f99d7069
DV
4785 /*
4786 * FIXME: Once we grow proper nuclear flip support out of this we need
4787 * to compute the mask of flip planes precisely. For the time being
4788 * consider this a flip to a NULL plane.
4789 */
4790 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS
4791}
4792
f67a559d
JB
4793static void ironlake_crtc_enable(struct drm_crtc *crtc)
4794{
4795 struct drm_device *dev = crtc->dev;
4796 struct drm_i915_private *dev_priv = dev->dev_private;
4797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4798 struct intel_encoder *encoder;
f67a559d 4799 int pipe = intel_crtc->pipe;
f67a559d 4800
53d9f4e9 4801 if (WARN_ON(intel_crtc->active))
f67a559d
JB
4802 return;
4803
6e3c9717 4804 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV
4805 intel_prepare_shared_dpll(intel_crtc);
4806
6e3c9717 4807 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4808 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV
4809
4810 intel_set_pipe_timings(intel_crtc);
4811
6e3c9717 4812 if (intel_crtc->config->has_pch_encoder) {
29407aab 4813 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4814 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV
4815 }
4816
4817 ironlake_set_pipeconf(crtc);
4818
f67a559d 4819 intel_crtc->active = true;
8664281b 4820
a72e4c9f
DV
4821 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4822 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4823
f6736a1a 4824 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV
4825 if (encoder->pre_enable)
4826 encoder->pre_enable(encoder);
f67a559d 4827
6e3c9717 4828 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV
4829 /* Note: FDI PLL enabling _must_ be done before we enable the
4830 * cpu pipes, hence this is separate from all the other fdi/pch
4831 * enabling. */
88cefb6c 4832 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV
4833 } else {
4834 assert_fdi_tx_disabled(dev_priv, pipe);
4835 assert_fdi_rx_disabled(dev_priv, pipe);
4836 }
f67a559d 4837
b074cec8 4838 ironlake_pfit_enable(intel_crtc);
f67a559d 4839
9c54c0dd
JB
4840 /*
4841 * On ILK+ LUT must be loaded before the pipe is running but with
4842 * clocks enabled
4843 */
4844 intel_crtc_load_lut(crtc);
4845
f37fcc2a 4846 intel_update_watermarks(crtc);
e1fdc473 4847 intel_enable_pipe(intel_crtc);
f67a559d 4848
6e3c9717 4849 if (intel_crtc->config->has_pch_encoder)
f67a559d 4850 ironlake_pch_enable(crtc);
c98e9dcf 4851
f9b61ff6
DV
4852 assert_vblank_disabled(crtc);
4853 drm_crtc_vblank_on(crtc);
4854
fa5c73b1
DV
4855 for_each_encoder_on_crtc(dev, crtc, encoder)
4856 encoder->enable(encoder);
61b77ddd
DV
4857
4858 if (HAS_PCH_CPT(dev))
a1520318 4859 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB
4860}
4861
42db64ef
PZ
4862/* IPS only exists on ULT machines and is tied to pipe A. */
4863static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4864{
f5adf94e 4865 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ
4866}
4867
4f771f10
PZ
4868static void haswell_crtc_enable(struct drm_crtc *crtc)
4869{
4870 struct drm_device *dev = crtc->dev;
4871 struct drm_i915_private *dev_priv = dev->dev_private;
4872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873 struct intel_encoder *encoder;
99d736a2
ML
4874 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4875 struct intel_crtc_state *pipe_config =
4876 to_intel_crtc_state(crtc->state);
4f771f10 4877
53d9f4e9 4878 if (WARN_ON(intel_crtc->active))
4f771f10
PZ
4879 return;
4880
df8ad70c
DV
4881 if (intel_crtc_to_shared_dpll(intel_crtc))
4882 intel_enable_shared_dpll(intel_crtc);
4883
6e3c9717 4884 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4885 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV
4886
4887 intel_set_pipe_timings(intel_crtc);
4888
6e3c9717
ACO
4889 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4890 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4891 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT
4892 }
4893
6e3c9717 4894 if (intel_crtc->config->has_pch_encoder) {
229fca97 4895 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4896 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV
4897 }
4898
4899 haswell_set_pipeconf(crtc);
4900
4901 intel_set_pipe_csc(crtc);
4902
4f771f10 4903 intel_crtc->active = true;
8664281b 4904
a72e4c9f 4905 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ
4906 for_each_encoder_on_crtc(dev, crtc, encoder)
4907 if (encoder->pre_enable)
4908 encoder->pre_enable(encoder);
4909
6e3c9717 4910 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV
4911 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4912 true);
4fe9467d
ID
4913 dev_priv->display.fdi_link_train(crtc);
4914 }
4915
1f544388 4916 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4917
ff6d9f55 4918 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4919 skylake_pfit_enable(intel_crtc);
ff6d9f55 4920 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4921 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB
4922 else
4923 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ
4924
4925 /*
4926 * On ILK+ LUT must be loaded before the pipe is running but with
4927 * clocks enabled
4928 */
4929 intel_crtc_load_lut(crtc);
4930
1f544388 4931 intel_ddi_set_pipe_settings(crtc);
8228c251 4932 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4933
f37fcc2a 4934 intel_update_watermarks(crtc);
e1fdc473 4935 intel_enable_pipe(intel_crtc);
42db64ef 4936
6e3c9717 4937 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4938 lpt_pch_enable(crtc);
4f771f10 4939
6e3c9717 4940 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA
4941 intel_ddi_set_vc_payload_alloc(crtc, true);
4942
f9b61ff6
DV
4943 assert_vblank_disabled(crtc);
4944 drm_crtc_vblank_on(crtc);
4945
8807e55b 4946 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4947 encoder->enable(encoder);
8807e55b
JN
4948 intel_opregion_notify_encoder(encoder, true);
4949 }
4f771f10 4950
e4916946
PZ
4951 /* If we change the relative order between pipe/planes enabling, we need
4952 * to change the workaround. */
99d736a2
ML
4953 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4954 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4955 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4956 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4957 }
4f771f10
PZ
4958}
4959
3f8dce3a
DV
4960static void ironlake_pfit_disable(struct intel_crtc *crtc)
4961{
4962 struct drm_device *dev = crtc->base.dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 int pipe = crtc->pipe;
4965
4966 /* To avoid upsetting the power well on haswell only disable the pfit if
4967 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4968 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV
4969 I915_WRITE(PF_CTL(pipe), 0);
4970 I915_WRITE(PF_WIN_POS(pipe), 0);
4971 I915_WRITE(PF_WIN_SZ(pipe), 0);
4972 }
4973}
4974
6be4a607
JB
4975static void ironlake_crtc_disable(struct drm_crtc *crtc)
4976{
4977 struct drm_device *dev = crtc->dev;
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4980 struct intel_encoder *encoder;
6be4a607 4981 int pipe = intel_crtc->pipe;
5eddb70b 4982 u32 reg, temp;
b52eb4dc 4983
ea9d758d
DV
4984 for_each_encoder_on_crtc(dev, crtc, encoder)
4985 encoder->disable(encoder);
4986
f9b61ff6
DV
4987 drm_crtc_vblank_off(crtc);
4988 assert_vblank_disabled(crtc);
4989
6e3c9717 4990 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4991 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4992
575f7ab7 4993 intel_disable_pipe(intel_crtc);
32f9d658 4994
3f8dce3a 4995 ironlake_pfit_disable(intel_crtc);
2c07245f 4996
5a74f70a
VS
4997 if (intel_crtc->config->has_pch_encoder)
4998 ironlake_fdi_disable(crtc);
4999
bf49ec8c
DV
5000 for_each_encoder_on_crtc(dev, crtc, encoder)
5001 if (encoder->post_disable)
5002 encoder->post_disable(encoder);
2c07245f 5003
6e3c9717 5004 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5005 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5006
d925c59a
DV
5007 if (HAS_PCH_CPT(dev)) {
5008 /* disable TRANS_DP_CTL */
5009 reg = TRANS_DP_CTL(pipe);
5010 temp = I915_READ(reg);
5011 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5012 TRANS_DP_PORT_SEL_MASK);
5013 temp |= TRANS_DP_PORT_SEL_NONE;
5014 I915_WRITE(reg, temp);
5015
5016 /* disable DPLL_SEL */
5017 temp = I915_READ(PCH_DPLL_SEL);
11887397 5018 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5019 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5020 }
e3421a18 5021
d925c59a
DV
5022 ironlake_fdi_pll_disable(intel_crtc);
5023 }
e4ca0612
PJ
5024
5025 intel_crtc->active = false;
5026 intel_update_watermarks(crtc);
6be4a607 5027}
1b3c7a47 5028
4f771f10 5029static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5030{
4f771f10
PZ
5031 struct drm_device *dev = crtc->dev;
5032 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5034 struct intel_encoder *encoder;
6e3c9717 5035 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5036
8807e55b
JN
5037 for_each_encoder_on_crtc(dev, crtc, encoder) {
5038 intel_opregion_notify_encoder(encoder, false);
4f771f10 5039 encoder->disable(encoder);
8807e55b 5040 }
4f771f10 5041
f9b61ff6
DV
5042 drm_crtc_vblank_off(crtc);
5043 assert_vblank_disabled(crtc);
5044
6e3c9717 5045 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV
5046 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5047 false);
575f7ab7 5048 intel_disable_pipe(intel_crtc);
4f771f10 5049
6e3c9717 5050 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS
5051 intel_ddi_set_vc_payload_alloc(crtc, false);
5052
ad80a810 5053 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5054
ff6d9f55 5055 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5056 skylake_scaler_disable(intel_crtc);
ff6d9f55 5057 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5058 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB
5059 else
5060 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5061
1f544388 5062 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5063
6e3c9717 5064 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5065 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5066 intel_ddi_fdi_disable(crtc);
83616634 5067 }
4f771f10 5068
97b040aa
ID
5069 for_each_encoder_on_crtc(dev, crtc, encoder)
5070 if (encoder->post_disable)
5071 encoder->post_disable(encoder);
e4ca0612
PJ
5072
5073 intel_crtc->active = false;
5074 intel_update_watermarks(crtc);
4f771f10
PZ
5075}
5076
2dd24552
JB
5077static void i9xx_pfit_enable(struct intel_crtc *crtc)
5078{
5079 struct drm_device *dev = crtc->base.dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5081 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5082
681a8504 5083 if (!pipe_config->gmch_pfit.control)
2dd24552
JB
5084 return;
5085
2dd24552 5086 /*
c0b03411
DV
5087 * The panel fitter should only be adjusted whilst the pipe is disabled,
5088 * according to register description and PRM.
2dd24552 5089 */
c0b03411
DV
5090 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5091 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5092
b074cec8
JB
5093 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5094 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV
5095
5096 /* Border color in case we don't scale up to the full screen. Black by
5097 * default, change to something else for debugging. */
5098 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB
5099}
5100
d05410f9
DA
5101static enum intel_display_power_domain port_to_power_domain(enum port port)
5102{
5103 switch (port) {
5104 case PORT_A:
5105 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5106 case PORT_B:
5107 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5108 case PORT_C:
5109 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5110 case PORT_D:
5111 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ
5112 case PORT_E:
5113 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA
5114 default:
5115 WARN_ON_ONCE(1);
5116 return POWER_DOMAIN_PORT_OTHER;
5117 }
5118}
5119
77d22dca
ID
5120#define for_each_power_domain(domain, mask) \
5121 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5122 if ((1 << (domain)) & (mask))
5123
319be8ae
ID
5124enum intel_display_power_domain
5125intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5126{
5127 struct drm_device *dev = intel_encoder->base.dev;
5128 struct intel_digital_port *intel_dig_port;
5129
5130 switch (intel_encoder->type) {
5131 case INTEL_OUTPUT_UNKNOWN:
5132 /* Only DDI platforms should ever use this output type */
5133 WARN_ON_ONCE(!HAS_DDI(dev));
5134 case INTEL_OUTPUT_DISPLAYPORT:
5135 case INTEL_OUTPUT_HDMI:
5136 case INTEL_OUTPUT_EDP:
5137 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5138 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA
5139 case INTEL_OUTPUT_DP_MST:
5140 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5141 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID
5142 case INTEL_OUTPUT_ANALOG:
5143 return POWER_DOMAIN_PORT_CRT;
5144 case INTEL_OUTPUT_DSI:
5145 return POWER_DOMAIN_PORT_DSI;
5146 default:
5147 return POWER_DOMAIN_PORT_OTHER;
5148 }
5149}
5150
5151static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5152{
319be8ae
ID
5153 struct drm_device *dev = crtc->dev;
5154 struct intel_encoder *intel_encoder;
5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID
5157 unsigned long mask;
5158 enum transcoder transcoder;
5159
292b990e
ML
5160 if (!crtc->state->active)
5161 return 0;
5162
77d22dca
ID
5163 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5164
5165 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5166 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO
5167 if (intel_crtc->config->pch_pfit.enabled ||
5168 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID
5169 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5170
319be8ae
ID
5171 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5172 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5173
77d22dca
ID
5174 return mask;
5175}
5176
292b990e 5177static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5178{
292b990e
ML
5179 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5181 enum intel_display_power_domain domain;
5182 unsigned long domains, new_domains, old_domains;
77d22dca 5183
292b990e
ML
5184 old_domains = intel_crtc->enabled_power_domains;
5185 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5186
292b990e
ML
5187 domains = new_domains & ~old_domains;
5188
5189 for_each_power_domain(domain, domains)
5190 intel_display_power_get(dev_priv, domain);
5191
5192 return old_domains & ~new_domains;
5193}
5194
5195static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5196 unsigned long domains)
5197{
5198 enum intel_display_power_domain domain;
5199
5200 for_each_power_domain(domain, domains)
5201 intel_display_power_put(dev_priv, domain);
5202}
77d22dca 5203
292b990e
ML
5204static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5205{
5206 struct drm_device *dev = state->dev;
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208 unsigned long put_domains[I915_MAX_PIPES] = {};
5209 struct drm_crtc_state *crtc_state;
5210 struct drm_crtc *crtc;
5211 int i;
77d22dca 5212
292b990e
ML
5213 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5214 if (needs_modeset(crtc->state))
5215 put_domains[to_intel_crtc(crtc)->pipe] =
5216 modeset_get_crtc_power_domains(crtc);
77d22dca
ID
5217 }
5218
27c329ed
ML
5219 if (dev_priv->display.modeset_commit_cdclk) {
5220 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5221
5222 if (cdclk != dev_priv->cdclk_freq &&
5223 !WARN_ON(!state->allow_modeset))
5224 dev_priv->display.modeset_commit_cdclk(state);
5225 }
50f6e502 5226
292b990e
ML
5227 for (i = 0; i < I915_MAX_PIPES; i++)
5228 if (put_domains[i])
5229 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID
5230}
5231
adafdc6f
MK
5232static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5233{
5234 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5235
5236 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5237 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5238 return max_cdclk_freq;
5239 else if (IS_CHERRYVIEW(dev_priv))
5240 return max_cdclk_freq*95/100;
5241 else if (INTEL_INFO(dev_priv)->gen < 4)
5242 return 2*max_cdclk_freq*90/100;
5243 else
5244 return max_cdclk_freq*90/100;
5245}
5246
560a7ae4
DL
5247static void intel_update_max_cdclk(struct drm_device *dev)
5248{
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250
5251 if (IS_SKYLAKE(dev)) {
5252 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5253
5254 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5255 dev_priv->max_cdclk_freq = 675000;
5256 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5257 dev_priv->max_cdclk_freq = 540000;
5258 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5259 dev_priv->max_cdclk_freq = 450000;
5260 else
5261 dev_priv->max_cdclk_freq = 337500;
5262 } else if (IS_BROADWELL(dev)) {
5263 /*
5264 * FIXME with extra cooling we can allow
5265 * 540 MHz for ULX and 675 Mhz for ULT.
5266 * How can we know if extra cooling is
5267 * available? PCI ID, VTB, something else?
5268 */
5269 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5270 dev_priv->max_cdclk_freq = 450000;
5271 else if (IS_BDW_ULX(dev))
5272 dev_priv->max_cdclk_freq = 450000;
5273 else if (IS_BDW_ULT(dev))
5274 dev_priv->max_cdclk_freq = 540000;
5275 else
5276 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK
5277 } else if (IS_CHERRYVIEW(dev)) {
5278 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL
5279 } else if (IS_VALLEYVIEW(dev)) {
5280 dev_priv->max_cdclk_freq = 400000;
5281 } else {
5282 /* otherwise assume cdclk is fixed */
5283 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5284 }
5285
adafdc6f
MK
5286 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5287
560a7ae4
DL
5288 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5289 dev_priv->max_cdclk_freq);
adafdc6f
MK
5290
5291 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5292 dev_priv->max_dotclk_freq);
560a7ae4
DL
5293}
5294
5295static void intel_update_cdclk(struct drm_device *dev)
5296{
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298
5299 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5300 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5301 dev_priv->cdclk_freq);
5302
5303 /*
5304 * Program the gmbus_freq based on the cdclk frequency.
5305 * BSpec erroneously claims we should aim for 4MHz, but
5306 * in fact 1MHz is the correct frequency.
5307 */
5308 if (IS_VALLEYVIEW(dev)) {
5309 /*
5310 * Program the gmbus_freq based on the cdclk frequency.
5311 * BSpec erroneously claims we should aim for 4MHz, but
5312 * in fact 1MHz is the correct frequency.
5313 */
5314 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5315 }
5316
5317 if (dev_priv->max_cdclk_freq == 0)
5318 intel_update_max_cdclk(dev);
5319}
5320
70d0c574 5321static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK
5322{
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324 uint32_t divider;
5325 uint32_t ratio;
5326 uint32_t current_freq;
5327 int ret;
5328
5329 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5330 switch (frequency) {
5331 case 144000:
5332 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5333 ratio = BXT_DE_PLL_RATIO(60);
5334 break;
5335 case 288000:
5336 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5337 ratio = BXT_DE_PLL_RATIO(60);
5338 break;
5339 case 384000:
5340 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5341 ratio = BXT_DE_PLL_RATIO(60);
5342 break;
5343 case 576000:
5344 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5345 ratio = BXT_DE_PLL_RATIO(60);
5346 break;
5347 case 624000:
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5349 ratio = BXT_DE_PLL_RATIO(65);
5350 break;
5351 case 19200:
5352 /*
5353 * Bypass frequency with DE PLL disabled. Init ratio, divider
5354 * to suppress GCC warning.
5355 */
5356 ratio = 0;
5357 divider = 0;
5358 break;
5359 default:
5360 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5361
5362 return;
5363 }
5364
5365 mutex_lock(&dev_priv->rps.hw_lock);
5366 /* Inform power controller of upcoming frequency change */
5367 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5368 0x80000000);
5369 mutex_unlock(&dev_priv->rps.hw_lock);
5370
5371 if (ret) {
5372 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5373 ret, frequency);
5374 return;
5375 }
5376
5377 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5378 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5379 current_freq = current_freq * 500 + 1000;
5380
5381 /*
5382 * DE PLL has to be disabled when
5383 * - setting to 19.2MHz (bypass, PLL isn't used)
5384 * - before setting to 624MHz (PLL needs toggling)
5385 * - before setting to any frequency from 624MHz (PLL needs toggling)
5386 */
5387 if (frequency == 19200 || frequency == 624000 ||
5388 current_freq == 624000) {
5389 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5390 /* Timeout 200us */
5391 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5392 1))
5393 DRM_ERROR("timout waiting for DE PLL unlock\n");
5394 }
5395
5396 if (frequency != 19200) {
5397 uint32_t val;
5398
5399 val = I915_READ(BXT_DE_PLL_CTL);
5400 val &= ~BXT_DE_PLL_RATIO_MASK;
5401 val |= ratio;
5402 I915_WRITE(BXT_DE_PLL_CTL, val);
5403
5404 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5405 /* Timeout 200us */
5406 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5407 DRM_ERROR("timeout waiting for DE PLL lock\n");
5408
5409 val = I915_READ(CDCLK_CTL);
5410 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5411 val |= divider;
5412 /*
5413 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5414 * enable otherwise.
5415 */
5416 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5417 if (frequency >= 500000)
5418 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5419
5420 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5421 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5422 val |= (frequency - 1000) / 500;
5423 I915_WRITE(CDCLK_CTL, val);
5424 }
5425
5426 mutex_lock(&dev_priv->rps.hw_lock);
5427 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5428 DIV_ROUND_UP(frequency, 25000));
5429 mutex_unlock(&dev_priv->rps.hw_lock);
5430
5431 if (ret) {
5432 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5433 ret, frequency);
5434 return;
5435 }
5436
a47871bd 5437 intel_update_cdclk(dev);
f8437dd1
VK
5438}
5439
5440void broxton_init_cdclk(struct drm_device *dev)
5441{
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443 uint32_t val;
5444
5445 /*
5446 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5447 * or else the reset will hang because there is no PCH to respond.
5448 * Move the handshake programming to initialization sequence.
5449 * Previously was left up to BIOS.
5450 */
5451 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5452 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5453 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5454
5455 /* Enable PG1 for cdclk */
5456 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5457
5458 /* check if cd clock is enabled */
5459 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5460 DRM_DEBUG_KMS("Display already initialized\n");
5461 return;
5462 }
5463
5464 /*
5465 * FIXME:
5466 * - The initial CDCLK needs to be read from VBT.
5467 * Need to make this change after VBT has changes for BXT.
5468 * - check if setting the max (or any) cdclk freq is really necessary
5469 * here, it belongs to modeset time
5470 */
5471 broxton_set_cdclk(dev, 624000);
5472
5473 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS
5474 POSTING_READ(DBUF_CTL);
5475
f8437dd1
VK
5476 udelay(10);
5477
5478 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5479 DRM_ERROR("DBuf power enable timeout!\n");
5480}
5481
5482void broxton_uninit_cdclk(struct drm_device *dev)
5483{
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485
5486 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS
5487 POSTING_READ(DBUF_CTL);
5488
f8437dd1
VK
5489 udelay(10);
5490
5491 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5492 DRM_ERROR("DBuf power disable timeout!\n");
5493
5494 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5495 broxton_set_cdclk(dev, 19200);
5496
5497 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5498}
5499
5d96d8af
DL
5500static const struct skl_cdclk_entry {
5501 unsigned int freq;
5502 unsigned int vco;
5503} skl_cdclk_frequencies[] = {
5504 { .freq = 308570, .vco = 8640 },
5505 { .freq = 337500, .vco = 8100 },
5506 { .freq = 432000, .vco = 8640 },
5507 { .freq = 450000, .vco = 8100 },
5508 { .freq = 540000, .vco = 8100 },
5509 { .freq = 617140, .vco = 8640 },
5510 { .freq = 675000, .vco = 8100 },
5511};
5512
5513static unsigned int skl_cdclk_decimal(unsigned int freq)
5514{
5515 return (freq - 1000) / 500;
5516}
5517
5518static unsigned int skl_cdclk_get_vco(unsigned int freq)
5519{
5520 unsigned int i;
5521
5522 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5523 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5524
5525 if (e->freq == freq)
5526 return e->vco;
5527 }
5528
5529 return 8100;
5530}
5531
5532static void
5533skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5534{
5535 unsigned int min_freq;
5536 u32 val;
5537
5538 /* select the minimum CDCLK before enabling DPLL 0 */
5539 val = I915_READ(CDCLK_CTL);
5540 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5541 val |= CDCLK_FREQ_337_308;
5542
5543 if (required_vco == 8640)
5544 min_freq = 308570;
5545 else
5546 min_freq = 337500;
5547
5548 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5549
5550 I915_WRITE(CDCLK_CTL, val);
5551 POSTING_READ(CDCLK_CTL);
5552
5553 /*
5554 * We always enable DPLL0 with the lowest link rate possible, but still
5555 * taking into account the VCO required to operate the eDP panel at the
5556 * desired frequency. The usual DP link rates operate with a VCO of
5557 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5558 * The modeset code is responsible for the selection of the exact link
5559 * rate later on, with the constraint of choosing a frequency that
5560 * works with required_vco.
5561 */
5562 val = I915_READ(DPLL_CTRL1);
5563
5564 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5565 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5566 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5567 if (required_vco == 8640)
5568 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5569 SKL_DPLL0);
5570 else
5571 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5572 SKL_DPLL0);
5573
5574 I915_WRITE(DPLL_CTRL1, val);
5575 POSTING_READ(DPLL_CTRL1);
5576
5577 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5578
5579 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5580 DRM_ERROR("DPLL0 not locked\n");
5581}
5582
5583static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5584{
5585 int ret;
5586 u32 val;
5587
5588 /* inform PCU we want to change CDCLK */
5589 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5590 mutex_lock(&dev_priv->rps.hw_lock);
5591 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5592 mutex_unlock(&dev_priv->rps.hw_lock);
5593
5594 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5595}
5596
5597static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5598{
5599 unsigned int i;
5600
5601 for (i = 0; i < 15; i++) {
5602 if (skl_cdclk_pcu_ready(dev_priv))
5603 return true;
5604 udelay(10);
5605 }
5606
5607 return false;
5608}
5609
5610static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5611{
560a7ae4 5612 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL
5613 u32 freq_select, pcu_ack;
5614
5615 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5616
5617 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5618 DRM_ERROR("failed to inform PCU about cdclk change\n");
5619 return;
5620 }
5621
5622 /* set CDCLK_CTL */
5623 switch(freq) {
5624 case 450000:
5625 case 432000:
5626 freq_select = CDCLK_FREQ_450_432;
5627 pcu_ack = 1;
5628 break;
5629 case 540000:
5630 freq_select = CDCLK_FREQ_540;
5631 pcu_ack = 2;
5632 break;
5633 case 308570:
5634 case 337500:
5635 default:
5636 freq_select = CDCLK_FREQ_337_308;
5637 pcu_ack = 0;
5638 break;
5639 case 617140:
5640 case 675000:
5641 freq_select = CDCLK_FREQ_675_617;
5642 pcu_ack = 3;
5643 break;
5644 }
5645
5646 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5647 POSTING_READ(CDCLK_CTL);
5648
5649 /* inform PCU of the change */
5650 mutex_lock(&dev_priv->rps.hw_lock);
5651 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5652 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL
5653
5654 intel_update_cdclk(dev);
5d96d8af
DL
5655}
5656
5657void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5658{
5659 /* disable DBUF power */
5660 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5661 POSTING_READ(DBUF_CTL);
5662
5663 udelay(10);
5664
5665 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5666 DRM_ERROR("DBuf power disable timeout\n");
5667
5668 /* disable DPLL0 */
5669 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5670 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5671 DRM_ERROR("Couldn't disable DPLL0\n");
5672
5673 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5674}
5675
5676void skl_init_cdclk(struct drm_i915_private *dev_priv)
5677{
5678 u32 val;
5679 unsigned int required_vco;
5680
5681 /* enable PCH reset handshake */
5682 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5683 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5684
5685 /* enable PG1 and Misc I/O */
5686 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5687
39d9b85a
GW
5688 /* DPLL0 not enabled (happens on early BIOS versions) */
5689 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5690 /* enable DPLL0 */
5691 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5692 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL
5693 }
5694
5d96d8af
DL
5695 /* set CDCLK to the frequency the BIOS chose */
5696 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5697
5698 /* enable DBUF power */
5699 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5700 POSTING_READ(DBUF_CTL);
5701
5702 udelay(10);
5703
5704 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5705 DRM_ERROR("DBuf power enable timeout\n");
5706}
5707
dfcab17e 5708/* returns HPLL frequency in kHz */
f8bf63fd 5709static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5710{
586f49dc 5711 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5712
586f49dc 5713 /* Obtain SKU information */
a580516d 5714 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB
5715 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5716 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5717 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5718
dfcab17e 5719 return vco_freq[hpll_freq] * 1000;
30a970c6
JB
5720}
5721
5722/* Adjust CDclk dividers to allow high res or save power if possible */
5723static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5724{
5725 struct drm_i915_private *dev_priv = dev->dev_private;
5726 u32 val, cmd;
5727
164dfd28
VK
5728 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5729 != dev_priv->cdclk_freq);
d60c4473 5730
dfcab17e 5731 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5732 cmd = 2;
dfcab17e 5733 else if (cdclk == 266667)
30a970c6
JB
5734 cmd = 1;
5735 else
5736 cmd = 0;
5737
5738 mutex_lock(&dev_priv->rps.hw_lock);
5739 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5740 val &= ~DSPFREQGUAR_MASK;
5741 val |= (cmd << DSPFREQGUAR_SHIFT);
5742 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5743 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5744 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5745 50)) {
5746 DRM_ERROR("timed out waiting for CDclk change\n");
5747 }
5748 mutex_unlock(&dev_priv->rps.hw_lock);
5749
54433e91
VS
5750 mutex_lock(&dev_priv->sb_lock);
5751
dfcab17e 5752 if (cdclk == 400000) {
6bcda4f0 5753 u32 divider;
30a970c6 5754
6bcda4f0 5755 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5756
30a970c6
JB
5757 /* adjust cdclk divider */
5758 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5759 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB
5760 val |= divider;
5761 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS
5762
5763 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5764 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5765 50))
5766 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB
5767 }
5768
30a970c6
JB
5769 /* adjust self-refresh exit latency value */
5770 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5771 val &= ~0x7f;
5772
5773 /*
5774 * For high bandwidth configs, we set a higher latency in the bunit
5775 * so that the core display fetch happens in time to avoid underruns.
5776 */
dfcab17e 5777 if (cdclk == 400000)
30a970c6
JB
5778 val |= 4500 / 250; /* 4.5 usec */
5779 else
5780 val |= 3000 / 250; /* 3.0 usec */
5781 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5782
a580516d 5783 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5784
b6283055 5785 intel_update_cdclk(dev);
30a970c6
JB
5786}
5787
383c5a6a
VS
5788static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5789{
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 u32 val, cmd;
5792
164dfd28
VK
5793 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5794 != dev_priv->cdclk_freq);
383c5a6a
VS
5795
5796 switch (cdclk) {
383c5a6a
VS
5797 case 333333:
5798 case 320000:
383c5a6a 5799 case 266667:
383c5a6a 5800 case 200000:
383c5a6a
VS
5801 break;
5802 default:
5f77eeb0 5803 MISSING_CASE(cdclk);
383c5a6a
VS
5804 return;
5805 }
5806
9d0d3fda
VS
5807 /*
5808 * Specs are full of misinformation, but testing on actual
5809 * hardware has shown that we just need to write the desired
5810 * CCK divider into the Punit register.
5811 */
5812 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5813
383c5a6a
VS
5814 mutex_lock(&dev_priv->rps.hw_lock);
5815 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5816 val &= ~DSPFREQGUAR_MASK_CHV;
5817 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5818 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5819 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5820 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5821 50)) {
5822 DRM_ERROR("timed out waiting for CDclk change\n");
5823 }
5824 mutex_unlock(&dev_priv->rps.hw_lock);
5825
b6283055 5826 intel_update_cdclk(dev);
383c5a6a
VS
5827}
5828
30a970c6
JB
5829static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5830 int max_pixclk)
5831{
6bcda4f0 5832 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5833 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5834
30a970c6
JB
5835 /*
5836 * Really only a few cases to deal with, as only 4 CDclks are supported:
5837 * 200MHz
5838 * 267MHz
29dc7ef3 5839 * 320/333MHz (depends on HPLL freq)
6cca3195
VS
5840 * 400MHz (VLV only)
5841 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5842 * of the lower bin and adjust if needed.
e37c67a1
VS
5843 *
5844 * We seem to get an unstable or solid color picture at 200MHz.
5845 * Not sure what's wrong. For now use 200MHz only when all pipes
5846 * are off.
30a970c6 5847 */
6cca3195
VS
5848 if (!IS_CHERRYVIEW(dev_priv) &&
5849 max_pixclk > freq_320*limit/100)
dfcab17e 5850 return 400000;
6cca3195 5851 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5852 return freq_320;
e37c67a1 5853 else if (max_pixclk > 0)
dfcab17e 5854 return 266667;
e37c67a1
VS
5855 else
5856 return 200000;
30a970c6
JB
5857}
5858
f8437dd1
VK
5859static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5860 int max_pixclk)
5861{
5862 /*
5863 * FIXME:
5864 * - remove the guardband, it's not needed on BXT
5865 * - set 19.2MHz bypass frequency if there are no active pipes
5866 */
5867 if (max_pixclk > 576000*9/10)
5868 return 624000;
5869 else if (max_pixclk > 384000*9/10)
5870 return 576000;
5871 else if (max_pixclk > 288000*9/10)
5872 return 384000;
5873 else if (max_pixclk > 144000*9/10)
5874 return 288000;
5875 else
5876 return 144000;
5877}
5878
a821fc46
ACO
5879/* Compute the max pixel clock for new configuration. Uses atomic state if
5880 * that's non-NULL, look at current state otherwise. */
5881static int intel_mode_max_pixclk(struct drm_device *dev,
5882 struct drm_atomic_state *state)
30a970c6 5883{
30a970c6 5884 struct intel_crtc *intel_crtc;
304603f4 5885 struct intel_crtc_state *crtc_state;
30a970c6
JB
5886 int max_pixclk = 0;
5887
d3fcc808 5888 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5889 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO
5890 if (IS_ERR(crtc_state))
5891 return PTR_ERR(crtc_state);
5892
5893 if (!crtc_state->base.enable)
5894 continue;
5895
5896 max_pixclk = max(max_pixclk,
5897 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB
5898 }
5899
5900 return max_pixclk;
5901}
5902
27c329ed 5903static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5904{
27c329ed
ML
5905 struct drm_device *dev = state->dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
5907 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5908
304603f4
ACO
5909 if (max_pixclk < 0)
5910 return max_pixclk;
30a970c6 5911
27c329ed
ML
5912 to_intel_atomic_state(state)->cdclk =
5913 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5914
27c329ed
ML
5915 return 0;
5916}
304603f4 5917
27c329ed
ML
5918static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5919{
5920 struct drm_device *dev = state->dev;
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5923
27c329ed
ML
5924 if (max_pixclk < 0)
5925 return max_pixclk;
85a96e7a 5926
27c329ed
ML
5927 to_intel_atomic_state(state)->cdclk =
5928 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5929
27c329ed 5930 return 0;
30a970c6
JB
5931}
5932
1e69cd74
VS
5933static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5934{
5935 unsigned int credits, default_credits;
5936
5937 if (IS_CHERRYVIEW(dev_priv))
5938 default_credits = PFI_CREDIT(12);
5939 else
5940 default_credits = PFI_CREDIT(8);
5941
164dfd28 5942 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS
5943 /* CHV suggested value is 31 or 63 */
5944 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5945 credits = PFI_CREDIT_63;
1e69cd74
VS
5946 else
5947 credits = PFI_CREDIT(15);
5948 } else {
5949 credits = default_credits;
5950 }
5951
5952 /*
5953 * WA - write default credits before re-programming
5954 * FIXME: should we also set the resend bit here?
5955 */
5956 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5957 default_credits);
5958
5959 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5960 credits | PFI_CREDIT_RESEND);
5961
5962 /*
5963 * FIXME is this guaranteed to clear
5964 * immediately or should we poll for it?
5965 */
5966 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5967}
5968
27c329ed 5969static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5970{
a821fc46 5971 struct drm_device *dev = old_state->dev;
27c329ed 5972 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5973 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5974
27c329ed
ML
5975 /*
5976 * FIXME: We can end up here with all power domains off, yet
5977 * with a CDCLK frequency other than the minimum. To account
5978 * for this take the PIPE-A power domain, which covers the HW
5979 * blocks needed for the following programming. This can be
5980 * removed once it's guaranteed that we get here either with
5981 * the minimum CDCLK set, or the required power domains
5982 * enabled.
5983 */
5984 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5985
27c329ed
ML
5986 if (IS_CHERRYVIEW(dev))
5987 cherryview_set_cdclk(dev, req_cdclk);
5988 else
5989 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5990
27c329ed 5991 vlv_program_pfi_credits(dev_priv);
1e69cd74 5992
27c329ed 5993 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB
5994}
5995
89b667f8
JB
5996static void valleyview_crtc_enable(struct drm_crtc *crtc)
5997{
5998 struct drm_device *dev = crtc->dev;
a72e4c9f 5999 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001 struct intel_encoder *encoder;
6002 int pipe = intel_crtc->pipe;
23538ef1 6003 bool is_dsi;
89b667f8 6004
53d9f4e9 6005 if (WARN_ON(intel_crtc->active))
89b667f8
JB
6006 return;
6007
409ee761 6008 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6009
6e3c9717 6010 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6011 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV
6012
6013 intel_set_pipe_timings(intel_crtc);
6014
c14b0485
VS
6015 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017
6018 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6019 I915_WRITE(CHV_CANVAS(pipe), 0);
6020 }
6021
5b18e57c
DV
6022 i9xx_set_pipeconf(intel_crtc);
6023
89b667f8 6024 intel_crtc->active = true;
89b667f8 6025
a72e4c9f 6026 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6027
89b667f8
JB
6028 for_each_encoder_on_crtc(dev, crtc, encoder)
6029 if (encoder->pre_pll_enable)
6030 encoder->pre_pll_enable(encoder);
6031
9d556c99 6032 if (!is_dsi) {
c0b4c660
VS
6033 if (IS_CHERRYVIEW(dev)) {
6034 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6035 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS
6036 } else {
6037 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6038 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6039 }
9d556c99 6040 }
89b667f8
JB
6041
6042 for_each_encoder_on_crtc(dev, crtc, encoder)
6043 if (encoder->pre_enable)
6044 encoder->pre_enable(encoder);
6045
2dd24552
JB
6046 i9xx_pfit_enable(intel_crtc);
6047
63cbb074
VS
6048 intel_crtc_load_lut(crtc);
6049
e1fdc473 6050 intel_enable_pipe(intel_crtc);
be6a6f8e 6051
4b3a9526
VS
6052 assert_vblank_disabled(crtc);
6053 drm_crtc_vblank_on(crtc);
6054
f9b61ff6
DV
6055 for_each_encoder_on_crtc(dev, crtc, encoder)
6056 encoder->enable(encoder);
89b667f8
JB
6057}
6058
f13c2ef3
DV
6059static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6060{
6061 struct drm_device *dev = crtc->base.dev;
6062 struct drm_i915_private *dev_priv = dev->dev_private;
6063
6e3c9717
ACO
6064 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6065 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV
6066}
6067
0b8765c6 6068static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB
6069{
6070 struct drm_device *dev = crtc->dev;
a72e4c9f 6071 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6073 struct intel_encoder *encoder;
79e53945 6074 int pipe = intel_crtc->pipe;
79e53945 6075
53d9f4e9 6076 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW
6077 return;
6078
f13c2ef3
DV
6079 i9xx_set_pll_dividers(intel_crtc);
6080
6e3c9717 6081 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6082 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV
6083
6084 intel_set_pipe_timings(intel_crtc);
6085
5b18e57c
DV
6086 i9xx_set_pipeconf(intel_crtc);
6087
f7abfe8b 6088 intel_crtc->active = true;
6b383a7f 6089
4a3436e8 6090 if (!IS_GEN2(dev))
a72e4c9f 6091 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6092
9d6d9f19
MK
6093 for_each_encoder_on_crtc(dev, crtc, encoder)
6094 if (encoder->pre_enable)
6095 encoder->pre_enable(encoder);
6096
f6736a1a
DV
6097 i9xx_enable_pll(intel_crtc);
6098
2dd24552
JB
6099 i9xx_pfit_enable(intel_crtc);
6100
63cbb074
VS
6101 intel_crtc_load_lut(crtc);
6102
f37fcc2a 6103 intel_update_watermarks(crtc);
e1fdc473 6104 intel_enable_pipe(intel_crtc);
be6a6f8e 6105
4b3a9526
VS
6106 assert_vblank_disabled(crtc);
6107 drm_crtc_vblank_on(crtc);
6108
f9b61ff6
DV
6109 for_each_encoder_on_crtc(dev, crtc, encoder)
6110 encoder->enable(encoder);
0b8765c6 6111}
79e53945 6112
87476d63
DV
6113static void i9xx_pfit_disable(struct intel_crtc *crtc)
6114{
6115 struct drm_device *dev = crtc->base.dev;
6116 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6117
6e3c9717 6118 if (!crtc->config->gmch_pfit.control)
328d8e82 6119 return;
87476d63 6120
328d8e82 6121 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6122
328d8e82
DV
6123 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6124 I915_READ(PFIT_CONTROL));
6125 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV
6126}
6127
0b8765c6
JB
6128static void i9xx_crtc_disable(struct drm_crtc *crtc)
6129{
6130 struct drm_device *dev = crtc->dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6133 struct intel_encoder *encoder;
0b8765c6 6134 int pipe = intel_crtc->pipe;
ef9c3aee 6135
6304cd91
VS
6136 /*
6137 * On gen2 planes are double buffered but the pipe isn't, so we must
6138 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID
6139 * We also need to wait on all gmch platforms because of the
6140 * self-refresh mode constraint explained above.
6304cd91 6141 */
564ed191 6142 intel_wait_for_vblank(dev, pipe);
6304cd91 6143
4b3a9526
VS
6144 for_each_encoder_on_crtc(dev, crtc, encoder)
6145 encoder->disable(encoder);
6146
f9b61ff6
DV
6147 drm_crtc_vblank_off(crtc);
6148 assert_vblank_disabled(crtc);
6149
575f7ab7 6150 intel_disable_pipe(intel_crtc);
24a1f16d 6151
87476d63 6152 i9xx_pfit_disable(intel_crtc);
24a1f16d 6153
89b667f8
JB
6154 for_each_encoder_on_crtc(dev, crtc, encoder)
6155 if (encoder->post_disable)
6156 encoder->post_disable(encoder);
6157
409ee761 6158 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML
6159 if (IS_CHERRYVIEW(dev))
6160 chv_disable_pll(dev_priv, pipe);
6161 else if (IS_VALLEYVIEW(dev))
6162 vlv_disable_pll(dev_priv, pipe);
6163 else
1c4e0274 6164 i9xx_disable_pll(intel_crtc);
076ed3b2 6165 }
0b8765c6 6166
d6db995f
VS
6167 for_each_encoder_on_crtc(dev, crtc, encoder)
6168 if (encoder->post_pll_disable)
6169 encoder->post_pll_disable(encoder);
6170
4a3436e8 6171 if (!IS_GEN2(dev))
a72e4c9f 6172 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ
6173
6174 intel_crtc->active = false;
6175 intel_update_watermarks(crtc);
0b8765c6
JB
6176}
6177
b17d48e2
ML
6178static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6179{
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6182 enum intel_display_power_domain domain;
6183 unsigned long domains;
6184
6185 if (!intel_crtc->active)
6186 return;
6187
a539205a
ML
6188 if (to_intel_plane_state(crtc->primary->state)->visible) {
6189 intel_crtc_wait_for_pending_flips(crtc);
6190 intel_pre_disable_primary(crtc);
6191 }
6192
d032ffa0 6193 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6194 dev_priv->display.crtc_disable(crtc);
1f7457b1 6195 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML
6196
6197 domains = intel_crtc->enabled_power_domains;
6198 for_each_power_domain(domain, domains)
6199 intel_display_power_put(dev_priv, domain);
6200 intel_crtc->enabled_power_domains = 0;
6201}
6202
6b72d486
ML
6203/*
6204 * turn all crtc's off, but do not adjust state
6205 * This has to be paired with a call to intel_modeset_setup_hw_state.
6206 */
70e0bd74 6207int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6208{
70e0bd74
ML
6209 struct drm_mode_config *config = &dev->mode_config;
6210 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6211 struct drm_atomic_state *state;
6b72d486 6212 struct drm_crtc *crtc;
70e0bd74
ML
6213 unsigned crtc_mask = 0;
6214 int ret = 0;
6215
6216 if (WARN_ON(!ctx))
6217 return 0;
6218
6219 lockdep_assert_held(&ctx->ww_ctx);
6220 state = drm_atomic_state_alloc(dev);
6221 if (WARN_ON(!state))
6222 return -ENOMEM;
6223
6224 state->acquire_ctx = ctx;
6225 state->allow_modeset = true;
6226
6227 for_each_crtc(dev, crtc) {
6228 struct drm_crtc_state *crtc_state =
6229 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6230
70e0bd74
ML
6231 ret = PTR_ERR_OR_ZERO(crtc_state);
6232 if (ret)
6233 goto free;
6234
6235 if (!crtc_state->active)
6236 continue;
6237
6238 crtc_state->active = false;
6239 crtc_mask |= 1 << drm_crtc_index(crtc);
6240 }
6241
6242 if (crtc_mask) {
74c090b1 6243 ret = drm_atomic_commit(state);
70e0bd74
ML
6244
6245 if (!ret) {
6246 for_each_crtc(dev, crtc)
6247 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6248 crtc->state->active = true;
6249
6250 return ret;
6251 }
6252 }
6253
6254free:
6255 if (ret)
6256 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6257 drm_atomic_state_free(state);
6258 return ret;
ee7b9f93
JB
6259}
6260
ea5b213a 6261void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6262{
4ef69c7a 6263 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6264
ea5b213a
CW
6265 drm_encoder_cleanup(encoder);
6266 kfree(intel_encoder);
7e7d76c3
JB
6267}
6268
0a91ca29
DV
6269/* Cross check the actual hw state with our own modeset state tracking (and it's
6270 * internal consistency). */
b980514c 6271static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6272{
35dd3c64
ML
6273 struct drm_crtc *crtc = connector->base.state->crtc;
6274
6275 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6276 connector->base.base.id,
6277 connector->base.name);
6278
0a91ca29 6279 if (connector->get_hw_state(connector)) {
35dd3c64
ML
6280 struct drm_encoder *encoder = &connector->encoder->base;
6281 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6282
35dd3c64
ML
6283 I915_STATE_WARN(!crtc,
6284 "connector enabled without attached crtc\n");
0a91ca29 6285
35dd3c64
ML
6286 if (!crtc)
6287 return;
6288
6289 I915_STATE_WARN(!crtc->state->active,
6290 "connector is active, but attached crtc isn't\n");
6291
6292 if (!encoder)
6293 return;
6294
6295 I915_STATE_WARN(conn_state->best_encoder != encoder,
6296 "atomic encoder doesn't match attached encoder\n");
6297
6298 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6299 "attached encoder crtc differs from connector crtc\n");
6300 } else {
4d688a2a
ML
6301 I915_STATE_WARN(crtc && crtc->state->active,
6302 "attached crtc is active, but connector isn't\n");
35dd3c64
ML
6303 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6304 "best encoder set without crtc!\n");
0a91ca29 6305 }
79e53945
JB
6306}
6307
08d9bc92
ACO
6308int intel_connector_init(struct intel_connector *connector)
6309{
6310 struct drm_connector_state *connector_state;
6311
6312 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6313 if (!connector_state)
6314 return -ENOMEM;
6315
6316 connector->base.state = connector_state;
6317 return 0;
6318}
6319
6320struct intel_connector *intel_connector_alloc(void)
6321{
6322 struct intel_connector *connector;
6323
6324 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6325 if (!connector)
6326 return NULL;
6327
6328 if (intel_connector_init(connector) < 0) {
6329 kfree(connector);
6330 return NULL;
6331 }
6332
6333 return connector;
6334}
6335
f0947c37
DV
6336/* Simple connector->get_hw_state implementation for encoders that support only
6337 * one connector and no cloning and hence the encoder state determines the state
6338 * of the connector. */
6339bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6340{
24929352 6341 enum pipe pipe = 0;
f0947c37 6342 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6343
f0947c37 6344 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW
6345}
6346
6d293983 6347static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6348{
6d293983
ACO
6349 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6350 return crtc_state->fdi_lanes;
d272ddfa
VS
6351
6352 return 0;
6353}
6354
6d293983 6355static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6356 struct intel_crtc_state *pipe_config)
1857e1da 6357{
6d293983
ACO
6358 struct drm_atomic_state *state = pipe_config->base.state;
6359 struct intel_crtc *other_crtc;
6360 struct intel_crtc_state *other_crtc_state;
6361
1857e1da
DV
6362 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6363 pipe_name(pipe), pipe_config->fdi_lanes);
6364 if (pipe_config->fdi_lanes > 4) {
6365 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6366 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6367 return -EINVAL;
1857e1da
DV
6368 }
6369
bafb6553 6370 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV
6371 if (pipe_config->fdi_lanes > 2) {
6372 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6373 pipe_config->fdi_lanes);
6d293983 6374 return -EINVAL;
1857e1da 6375 } else {
6d293983 6376 return 0;
1857e1da
DV
6377 }
6378 }
6379
6380 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6381 return 0;
1857e1da
DV
6382
6383 /* Ivybridge 3 pipe is really complicated */
6384 switch (pipe) {
6385 case PIPE_A:
6d293983 6386 return 0;
1857e1da 6387 case PIPE_B:
6d293983
ACO
6388 if (pipe_config->fdi_lanes <= 2)
6389 return 0;
6390
6391 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6392 other_crtc_state =
6393 intel_atomic_get_crtc_state(state, other_crtc);
6394 if (IS_ERR(other_crtc_state))
6395 return PTR_ERR(other_crtc_state);
6396
6397 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV
6398 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6399 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6400 return -EINVAL;
1857e1da 6401 }
6d293983 6402 return 0;
1857e1da 6403 case PIPE_C:
251cc67c
VS
6404 if (pipe_config->fdi_lanes > 2) {
6405 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6406 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6407 return -EINVAL;
251cc67c 6408 }
6d293983
ACO
6409
6410 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6411 other_crtc_state =
6412 intel_atomic_get_crtc_state(state, other_crtc);
6413 if (IS_ERR(other_crtc_state))
6414 return PTR_ERR(other_crtc_state);
6415
6416 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6417 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6418 return -EINVAL;
1857e1da 6419 }
6d293983 6420 return 0;
1857e1da
DV
6421 default:
6422 BUG();
6423 }
6424}
6425
e29c22c0
DV
6426#define RETRY 1
6427static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6428 struct intel_crtc_state *pipe_config)
877d48d5 6429{
1857e1da 6430 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6431 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO
6432 int lane, link_bw, fdi_dotclock, ret;
6433 bool needs_recompute = false;
877d48d5 6434
e29c22c0 6435retry:
877d48d5
DV
6436 /* FDI is a binary signal running at ~2.7GHz, encoding
6437 * each output octet as 10 bits. The actual frequency
6438 * is stored as a divider into a 100MHz clock, and the
6439 * mode pixel clock is stored in units of 1KHz.
6440 * Hence the bw of each lane in terms of the mode signal
6441 * is:
6442 */
6443 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6444
241bfc38 6445 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6446
2bd89a07 6447 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV
6448 pipe_config->pipe_bpp);
6449
6450 pipe_config->fdi_lanes = lane;
6451
2bd89a07 6452 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6453 link_bw, &pipe_config->fdi_m_n);
1857e1da 6454
6d293983
ACO
6455 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6456 intel_crtc->pipe, pipe_config);
6457 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV
6458 pipe_config->pipe_bpp -= 2*3;
6459 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6460 pipe_config->pipe_bpp);
6461 needs_recompute = true;
6462 pipe_config->bw_constrained = true;
6463
6464 goto retry;
6465 }
6466
6467 if (needs_recompute)
6468 return RETRY;
6469
6d293983 6470 return ret;
877d48d5
DV
6471}
6472
8cfb3407
VS
6473static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6474 struct intel_crtc_state *pipe_config)
6475{
6476 if (pipe_config->pipe_bpp > 24)
6477 return false;
6478
6479 /* HSW can handle pixel rate up to cdclk? */
6480 if (IS_HASWELL(dev_priv->dev))
6481 return true;
6482
6483 /*
b432e5cf
VS
6484 * We compare against max which means we must take
6485 * the increased cdclk requirement into account when
6486 * calculating the new cdclk.
6487 *
6488 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS
6489 */
6490 return ilk_pipe_pixel_rate(pipe_config) <=
6491 dev_priv->max_cdclk_freq * 95 / 100;
6492}
6493
42db64ef 6494static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6495 struct intel_crtc_state *pipe_config)
42db64ef 6496{
8cfb3407
VS
6497 struct drm_device *dev = crtc->base.dev;
6498 struct drm_i915_private *dev_priv = dev->dev_private;
6499
d330a953 6500 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS
6501 hsw_crtc_supports_ips(crtc) &&
6502 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ
6503}
6504
a43f6e0f 6505static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6506 struct intel_crtc_state *pipe_config)
79e53945 6507{
a43f6e0f 6508 struct drm_device *dev = crtc->base.dev;
8bd31e67 6509 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6510 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6511
ad3a4479 6512 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6513 if (INTEL_INFO(dev)->gen < 4) {
44913155 6514 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS
6515
6516 /*
6517 * Enable pixel doubling when the dot clock
6518 * is > 90% of the (display) core speed.
6519 *
b397c96b
VS
6520 * GDG double wide on either pipe,
6521 * otherwise pipe A only.
cf532bb2 6522 */
b397c96b 6523 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6524 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6525 clock_limit *= 2;
cf532bb2 6526 pipe_config->double_wide = true;
ad3a4479
VS
6527 }
6528
241bfc38 6529 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6530 return -EINVAL;
2c07245f 6531 }
89749350 6532
1d1d0e27
VS
6533 /*
6534 * Pipe horizontal size must be even in:
6535 * - DVO ganged mode
6536 * - LVDS dual channel mode
6537 * - Double wide pipe
6538 */
a93e255f 6539 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS
6540 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6541 pipe_config->pipe_src_w &= ~1;
6542
8693a824
DL
6543 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6544 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW
6545 */
6546 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6547 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6548 return -EINVAL;
44f46b42 6549
f5adf94e 6550 if (HAS_IPS(dev))
a43f6e0f
DV
6551 hsw_compute_ips_config(crtc, pipe_config);
6552
877d48d5 6553 if (pipe_config->has_pch_encoder)
a43f6e0f 6554 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6555
cf5a15be 6556 return 0;
79e53945
JB
6557}
6558
1652d19e
VS
6559static int skylake_get_display_clock_speed(struct drm_device *dev)
6560{
6561 struct drm_i915_private *dev_priv = to_i915(dev);
6562 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6563 uint32_t cdctl = I915_READ(CDCLK_CTL);
6564 uint32_t linkrate;
6565
414355a7 6566 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6567 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS
6568
6569 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6570 return 540000;
6571
6572 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6573 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6574
71cd8423
DL
6575 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6576 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS
6577 /* vco 8640 */
6578 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6579 case CDCLK_FREQ_450_432:
6580 return 432000;
6581 case CDCLK_FREQ_337_308:
6582 return 308570;
6583 case CDCLK_FREQ_675_617:
6584 return 617140;
6585 default:
6586 WARN(1, "Unknown cd freq selection\n");
6587 }
6588 } else {
6589 /* vco 8100 */
6590 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6591 case CDCLK_FREQ_450_432:
6592 return 450000;
6593 case CDCLK_FREQ_337_308:
6594 return 337500;
6595 case CDCLK_FREQ_675_617:
6596 return 675000;
6597 default:
6598 WARN(1, "Unknown cd freq selection\n");
6599 }
6600 }
6601
6602 /* error case, do as if DPLL0 isn't enabled */
6603 return 24000;
6604}
6605
acd3f3d3
BP
6606static int broxton_get_display_clock_speed(struct drm_device *dev)
6607{
6608 struct drm_i915_private *dev_priv = to_i915(dev);
6609 uint32_t cdctl = I915_READ(CDCLK_CTL);
6610 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6611 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6612 int cdclk;
6613
6614 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6615 return 19200;
6616
6617 cdclk = 19200 * pll_ratio / 2;
6618
6619 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6620 case BXT_CDCLK_CD2X_DIV_SEL_1:
6621 return cdclk; /* 576MHz or 624MHz */
6622 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6623 return cdclk * 2 / 3; /* 384MHz */
6624 case BXT_CDCLK_CD2X_DIV_SEL_2:
6625 return cdclk / 2; /* 288MHz */
6626 case BXT_CDCLK_CD2X_DIV_SEL_4:
6627 return cdclk / 4; /* 144MHz */
6628 }
6629
6630 /* error case, do as if DE PLL isn't enabled */
6631 return 19200;
6632}
6633
1652d19e
VS
6634static int broadwell_get_display_clock_speed(struct drm_device *dev)
6635{
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637 uint32_t lcpll = I915_READ(LCPLL_CTL);
6638 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6639
6640 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6641 return 800000;
6642 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6643 return 450000;
6644 else if (freq == LCPLL_CLK_FREQ_450)
6645 return 450000;
6646 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6647 return 540000;
6648 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6649 return 337500;
6650 else
6651 return 675000;
6652}
6653
6654static int haswell_get_display_clock_speed(struct drm_device *dev)
6655{
6656 struct drm_i915_private *dev_priv = dev->dev_private;
6657 uint32_t lcpll = I915_READ(LCPLL_CTL);
6658 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6659
6660 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6661 return 800000;
6662 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6663 return 450000;
6664 else if (freq == LCPLL_CLK_FREQ_450)
6665 return 450000;
6666 else if (IS_HSW_ULT(dev))
6667 return 337500;
6668 else
6669 return 540000;
79e53945
JB
6670}
6671
25eb05fc
JB
6672static int valleyview_get_display_clock_speed(struct drm_device *dev)
6673{
d197b7d3 6674 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS
6675 u32 val;
6676 int divider;
6677
6bcda4f0
VS
6678 if (dev_priv->hpll_freq == 0)
6679 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6680
a580516d 6681 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6682 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6683 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS
6684
6685 divider = val & DISPLAY_FREQUENCY_VALUES;
6686
7d007f40
VS
6687 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6688 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6689 "cdclk change in progress\n");
6690
6bcda4f0 6691 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB
6692}
6693
b37a6434
VS
6694static int ilk_get_display_clock_speed(struct drm_device *dev)
6695{
6696 return 450000;
6697}
6698
e70236a8
JB
6699static int i945_get_display_clock_speed(struct drm_device *dev)
6700{
6701 return 400000;
6702}
79e53945 6703
e70236a8 6704static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6705{
e907f170 6706 return 333333;
e70236a8 6707}
79e53945 6708
e70236a8
JB
6709static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6710{
6711 return 200000;
6712}
79e53945 6713
257a7ffc
DV
6714static int pnv_get_display_clock_speed(struct drm_device *dev)
6715{
6716 u16 gcfgc = 0;
6717
6718 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6719
6720 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6721 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6722 return 266667;
257a7ffc 6723 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6724 return 333333;
257a7ffc 6725 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6726 return 444444;
257a7ffc
DV
6727 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6728 return 200000;
6729 default:
6730 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6731 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6732 return 133333;
257a7ffc 6733 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6734 return 166667;
257a7ffc
DV
6735 }
6736}
6737
e70236a8
JB
6738static int i915gm_get_display_clock_speed(struct drm_device *dev)
6739{
6740 u16 gcfgc = 0;
79e53945 6741
e70236a8
JB
6742 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6743
6744 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6745 return 133333;
e70236a8
JB
6746 else {
6747 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6748 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6749 return 333333;
e70236a8
JB
6750 default:
6751 case GC_DISPLAY_CLOCK_190_200_MHZ:
6752 return 190000;
79e53945 6753 }
e70236a8
JB
6754 }
6755}
6756
6757static int i865_get_display_clock_speed(struct drm_device *dev)
6758{
e907f170 6759 return 266667;
e70236a8
JB
6760}
6761
1b1d2716 6762static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB
6763{
6764 u16 hpllcc = 0;
1b1d2716 6765
65cd2b3f
VS
6766 /*
6767 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6768 * encoding is different :(
6769 * FIXME is this the right way to detect 852GM/852GMV?
6770 */
6771 if (dev->pdev->revision == 0x1)
6772 return 133333;
6773
1b1d2716
VS
6774 pci_bus_read_config_word(dev->pdev->bus,
6775 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6776
e70236a8
JB
6777 /* Assume that the hardware is in the high speed state. This
6778 * should be the default.
6779 */
6780 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6781 case GC_CLOCK_133_200:
1b1d2716 6782 case GC_CLOCK_133_200_2:
e70236a8
JB
6783 case GC_CLOCK_100_200:
6784 return 200000;
6785 case GC_CLOCK_166_250:
6786 return 250000;
6787 case GC_CLOCK_100_133:
e907f170 6788 return 133333;
1b1d2716
VS
6789 case GC_CLOCK_133_266:
6790 case GC_CLOCK_133_266_2:
6791 case GC_CLOCK_166_266:
6792 return 266667;
e70236a8 6793 }
79e53945 6794
e70236a8
JB
6795 /* Shouldn't happen */
6796 return 0;
6797}
79e53945 6798
e70236a8
JB
6799static int i830_get_display_clock_speed(struct drm_device *dev)
6800{
e907f170 6801 return 133333;
79e53945
JB
6802}
6803
34edce2f
VS
6804static unsigned int intel_hpll_vco(struct drm_device *dev)
6805{
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 static const unsigned int blb_vco[8] = {
6808 [0] = 3200000,
6809 [1] = 4000000,
6810 [2] = 5333333,
6811 [3] = 4800000,
6812 [4] = 6400000,
6813 };
6814 static const unsigned int pnv_vco[8] = {
6815 [0] = 3200000,
6816 [1] = 4000000,
6817 [2] = 5333333,
6818 [3] = 4800000,
6819 [4] = 2666667,
6820 };
6821 static const unsigned int cl_vco[8] = {
6822 [0] = 3200000,
6823 [1] = 4000000,
6824 [2] = 5333333,
6825 [3] = 6400000,
6826 [4] = 3333333,
6827 [5] = 3566667,
6828 [6] = 4266667,
6829 };
6830 static const unsigned int elk_vco[8] = {
6831 [0] = 3200000,
6832 [1] = 4000000,
6833 [2] = 5333333,
6834 [3] = 4800000,
6835 };
6836 static const unsigned int ctg_vco[8] = {
6837 [0] = 3200000,
6838 [1] = 4000000,
6839 [2] = 5333333,
6840 [3] = 6400000,
6841 [4] = 2666667,
6842 [5] = 4266667,
6843 };
6844 const unsigned int *vco_table;
6845 unsigned int vco;
6846 uint8_t tmp = 0;
6847
6848 /* FIXME other chipsets? */
6849 if (IS_GM45(dev))
6850 vco_table = ctg_vco;
6851 else if (IS_G4X(dev))
6852 vco_table = elk_vco;
6853 else if (IS_CRESTLINE(dev))
6854 vco_table = cl_vco;
6855 else if (IS_PINEVIEW(dev))
6856 vco_table = pnv_vco;
6857 else if (IS_G33(dev))
6858 vco_table = blb_vco;
6859 else
6860 return 0;
6861
6862 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6863
6864 vco = vco_table[tmp & 0x7];
6865 if (vco == 0)
6866 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6867 else
6868 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6869
6870 return vco;
6871}
6872
6873static int gm45_get_display_clock_speed(struct drm_device *dev)
6874{
6875 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6876 uint16_t tmp = 0;
6877
6878 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6879
6880 cdclk_sel = (tmp >> 12) & 0x1;
6881
6882 switch (vco) {
6883 case 2666667:
6884 case 4000000:
6885 case 5333333:
6886 return cdclk_sel ? 333333 : 222222;
6887 case 3200000:
6888 return cdclk_sel ? 320000 : 228571;
6889 default:
6890 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6891 return 222222;
6892 }
6893}
6894
6895static int i965gm_get_display_clock_speed(struct drm_device *dev)
6896{
6897 static const uint8_t div_3200[] = { 16, 10, 8 };
6898 static const uint8_t div_4000[] = { 20, 12, 10 };
6899 static const uint8_t div_5333[] = { 24, 16, 14 };
6900 const uint8_t *div_table;
6901 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6902 uint16_t tmp = 0;
6903
6904 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6905
6906 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6907
6908 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6909 goto fail;
6910
6911 switch (vco) {
6912 case 3200000:
6913 div_table = div_3200;
6914 break;
6915 case 4000000:
6916 div_table = div_4000;
6917 break;
6918 case 5333333:
6919 div_table = div_5333;
6920 break;
6921 default:
6922 goto fail;
6923 }
6924
6925 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6926
caf4e252 6927fail:
34edce2f
VS
6928 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6929 return 200000;
6930}
6931
6932static int g33_get_display_clock_speed(struct drm_device *dev)
6933{
6934 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6935 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6936 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6937 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6938 const uint8_t *div_table;
6939 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6940 uint16_t tmp = 0;
6941
6942 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6943
6944 cdclk_sel = (tmp >> 4) & 0x7;
6945
6946 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6947 goto fail;
6948
6949 switch (vco) {
6950 case 3200000:
6951 div_table = div_3200;
6952 break;
6953 case 4000000:
6954 div_table = div_4000;
6955 break;
6956 case 4800000:
6957 div_table = div_4800;
6958 break;
6959 case 5333333:
6960 div_table = div_5333;
6961 break;
6962 default:
6963 goto fail;
6964 }
6965
6966 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6967
caf4e252 6968fail:
34edce2f
VS
6969 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6970 return 190476;
6971}
6972
2c07245f 6973static void
a65851af 6974intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6975{
a65851af
VS
6976 while (*num > DATA_LINK_M_N_MASK ||
6977 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW
6978 *num >>= 1;
6979 *den >>= 1;
6980 }
6981}
6982
a65851af
VS
6983static void compute_m_n(unsigned int m, unsigned int n,
6984 uint32_t *ret_m, uint32_t *ret_n)
6985{
6986 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6987 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6988 intel_reduce_m_n_ratio(ret_m, ret_n);
6989}
6990
e69d0bc1
DV
6991void
6992intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6993 int pixel_clock, int link_clock,
6994 struct intel_link_m_n *m_n)
2c07245f 6995{
e69d0bc1 6996 m_n->tu = 64;
a65851af
VS
6997
6998 compute_m_n(bits_per_pixel * pixel_clock,
6999 link_clock * nlanes * 8,
7000 &m_n->gmch_m, &m_n->gmch_n);
7001
7002 compute_m_n(pixel_clock, link_clock,
7003 &m_n->link_m, &m_n->link_n);
2c07245f
ZW
7004}
7005
a7615030
CW
7006static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7007{
d330a953
JN
7008 if (i915.panel_use_ssc >= 0)
7009 return i915.panel_use_ssc != 0;
41aa3448 7010 return dev_priv->vbt.lvds_use_ssc
435793df 7011 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW
7012}
7013
a93e255f
ACO
7014static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7015 int num_connectors)
c65d77d8 7016{
a93e255f 7017 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB
7018 struct drm_i915_private *dev_priv = dev->dev_private;
7019 int refclk;
7020
a93e255f
ACO
7021 WARN_ON(!crtc_state->base.state);
7022
5ab7b0b7 7023 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7024 refclk = 100000;
a93e255f 7025 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7026 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS
7027 refclk = dev_priv->vbt.lvds_ssc_freq;
7028 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB
7029 } else if (!IS_GEN2(dev)) {
7030 refclk = 96000;
7031 } else {
7032 refclk = 48000;
7033 }
7034
7035 return refclk;
7036}
7037
7429e9d4 7038static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7039{
7df00d7a 7040 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7041}
f47709a9 7042
7429e9d4
DV
7043static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7044{
7045 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB
7046}
7047
f47709a9 7048static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7049 struct intel_crtc_state *crtc_state,
a7516a05
JB
7050 intel_clock_t *reduced_clock)
7051{
f47709a9 7052 struct drm_device *dev = crtc->base.dev;
a7516a05
JB
7053 u32 fp, fp2 = 0;
7054
7055 if (IS_PINEVIEW(dev)) {
190f68c5 7056 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7057 if (reduced_clock)
7429e9d4 7058 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7059 } else {
190f68c5 7060 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7061 if (reduced_clock)
7429e9d4 7062 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB
7063 }
7064
190f68c5 7065 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7066
f47709a9 7067 crtc->lowfreq_avail = false;
a93e255f 7068 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7069 reduced_clock) {
190f68c5 7070 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7071 crtc->lowfreq_avail = true;
a7516a05 7072 } else {
190f68c5 7073 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB
7074 }
7075}
7076
5e69f97f
CML
7077static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7078 pipe)
89b667f8
JB
7079{
7080 u32 reg_val;
7081
7082 /*
7083 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7084 * and set it to a reasonable value instead.
7085 */
ab3c759a 7086 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB
7087 reg_val &= 0xffffff00;
7088 reg_val |= 0x00000030;
ab3c759a 7089 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7090
ab3c759a 7091 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
7092 reg_val &= 0x8cffffff;
7093 reg_val = 0x8c000000;
ab3c759a 7094 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7095
ab3c759a 7096 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7097 reg_val &= 0xffffff00;
ab3c759a 7098 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7099
ab3c759a 7100 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
7101 reg_val &= 0x00ffffff;
7102 reg_val |= 0xb0000000;
ab3c759a 7103 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB
7104}
7105
b551842d
DV
7106static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7107 struct intel_link_m_n *m_n)
7108{
7109 struct drm_device *dev = crtc->base.dev;
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111 int pipe = crtc->pipe;
7112
e3b95f1e
DV
7113 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7114 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7115 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7116 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV
7117}
7118
7119static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
7120 struct intel_link_m_n *m_n,
7121 struct intel_link_m_n *m2_n2)
b551842d
DV
7122{
7123 struct drm_device *dev = crtc->base.dev;
7124 struct drm_i915_private *dev_priv = dev->dev_private;
7125 int pipe = crtc->pipe;
6e3c9717 7126 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV
7127
7128 if (INTEL_INFO(dev)->gen >= 5) {
7129 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7130 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7131 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7132 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK
7133 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7134 * for gen < 8) and if DRRS is supported (to make sure the
7135 * registers are not unnecessarily accessed).
7136 */
44395bfe 7137 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7138 crtc->config->has_drrs) {
f769cd24
VK
7139 I915_WRITE(PIPE_DATA_M2(transcoder),
7140 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7141 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7142 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7143 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7144 }
b551842d 7145 } else {
e3b95f1e
DV
7146 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7147 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7148 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7149 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV
7150 }
7151}
7152
fe3cd48d 7153void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7154{
fe3cd48d
R
7155 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7156
7157 if (m_n == M1_N1) {
7158 dp_m_n = &crtc->config->dp_m_n;
7159 dp_m2_n2 = &crtc->config->dp_m2_n2;
7160 } else if (m_n == M2_N2) {
7161
7162 /*
7163 * M2_N2 registers are not supported. Hence m2_n2 divider value
7164 * needs to be programmed into M1_N1.
7165 */
7166 dp_m_n = &crtc->config->dp_m2_n2;
7167 } else {
7168 DRM_ERROR("Unsupported divider value\n");
7169 return;
7170 }
7171
6e3c9717
ACO
7172 if (crtc->config->has_pch_encoder)
7173 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7174 else
fe3cd48d 7175 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV
7176}
7177
251ac862
DV
7178static void vlv_compute_dpll(struct intel_crtc *crtc,
7179 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV
7180{
7181 u32 dpll, dpll_md;
7182
7183 /*
7184 * Enable DPIO clock input. We should never disable the reference
7185 * clock for pipe B, since VGA hotplug / manual detection depends
7186 * on it.
7187 */
60bfe44f
VS
7188 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7189 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV
7190 /* We should never disable this, set it here for state tracking */
7191 if (crtc->pipe == PIPE_B)
7192 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7193 dpll |= DPLL_VCO_ENABLE;
d288f65f 7194 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7195
d288f65f 7196 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7197 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7198 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV
7199}
7200
d288f65f 7201static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7202 const struct intel_crtc_state *pipe_config)
a0c4da24 7203{
f47709a9 7204 struct drm_device *dev = crtc->base.dev;
a0c4da24 7205 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7206 int pipe = crtc->pipe;
bdd4b6a6 7207 u32 mdiv;
a0c4da24 7208 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7209 u32 coreclk, reg_val;
a0c4da24 7210
a580516d 7211 mutex_lock(&dev_priv->sb_lock);
09153000 7212
d288f65f
VS
7213 bestn = pipe_config->dpll.n;
7214 bestm1 = pipe_config->dpll.m1;
7215 bestm2 = pipe_config->dpll.m2;
7216 bestp1 = pipe_config->dpll.p1;
7217 bestp2 = pipe_config->dpll.p2;
a0c4da24 7218
89b667f8
JB
7219 /* See eDP HDMI DPIO driver vbios notes doc */
7220
7221 /* PLL B needs special handling */
bdd4b6a6 7222 if (pipe == PIPE_B)
5e69f97f 7223 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB
7224
7225 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7226 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB
7227
7228 /* Disable target IRef on PLL */
ab3c759a 7229 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7230 reg_val &= 0x00ffffff;
ab3c759a 7231 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB
7232
7233 /* Disable fast lock */
ab3c759a 7234 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB
7235
7236 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB
7237 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7238 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7239 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7240 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB
7241
7242 /*
7243 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7244 * but we don't support that).
7245 * Note: don't use the DAC post divider as it seems unstable.
7246 */
7247 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7248 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7249
a0c4da24 7250 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7252
89b667f8 7253 /* Set HBR and RBR LPF coefficients */
d288f65f 7254 if (pipe_config->port_clock == 162000 ||
409ee761
ACO
7255 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7256 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7258 0x009f0003);
89b667f8 7259 else
ab3c759a 7260 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB
7261 0x00d0000f);
7262
681a8504 7263 if (pipe_config->has_dp_encoder) {
89b667f8 7264 /* Use SSC source */
bdd4b6a6 7265 if (pipe == PIPE_A)
ab3c759a 7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7267 0x0df40000);
7268 else
ab3c759a 7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7270 0x0df70000);
7271 } else { /* HDMI or VGA */
7272 /* Use bend source */
bdd4b6a6 7273 if (pipe == PIPE_A)
ab3c759a 7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7275 0x0df70000);
7276 else
ab3c759a 7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7278 0x0df40000);
7279 }
a0c4da24 7280
ab3c759a 7281 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7282 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO
7283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7284 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7285 coreclk |= 0x01000000;
ab3c759a 7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7287
ab3c759a 7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7289 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB
7290}
7291
251ac862
DV
7292static void chv_compute_dpll(struct intel_crtc *crtc,
7293 struct intel_crtc_state *pipe_config)
1ae0d137 7294{
60bfe44f
VS
7295 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7296 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS
7297 DPLL_VCO_ENABLE;
7298 if (crtc->pipe != PIPE_A)
d288f65f 7299 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7300
d288f65f
VS
7301 pipe_config->dpll_hw_state.dpll_md =
7302 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS
7303}
7304
d288f65f 7305static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7306 const struct intel_crtc_state *pipe_config)
9d556c99
CML
7307{
7308 struct drm_device *dev = crtc->base.dev;
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 int pipe = crtc->pipe;
7311 int dpll_reg = DPLL(crtc->pipe);
7312 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7313 u32 loopfilter, tribuf_calcntr;
9d556c99 7314 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7315 u32 dpio_val;
9cbe40c1 7316 int vco;
9d556c99 7317
d288f65f
VS
7318 bestn = pipe_config->dpll.n;
7319 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7320 bestm1 = pipe_config->dpll.m1;
7321 bestm2 = pipe_config->dpll.m2 >> 22;
7322 bestp1 = pipe_config->dpll.p1;
7323 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7324 vco = pipe_config->dpll.vco;
a945ce7e 7325 dpio_val = 0;
9cbe40c1 7326 loopfilter = 0;
9d556c99
CML
7327
7328 /*
7329 * Enable Refclk and SSC
7330 */
a11b0703 7331 I915_WRITE(dpll_reg,
d288f65f 7332 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7333
a580516d 7334 mutex_lock(&dev_priv->sb_lock);
9d556c99 7335
9d556c99
CML
7336 /* p1 and p2 divider */
7337 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7338 5 << DPIO_CHV_S1_DIV_SHIFT |
7339 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7340 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7341 1 << DPIO_CHV_K_DIV_SHIFT);
7342
7343 /* Feedback post-divider - m2 */
7344 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7345
7346 /* Feedback refclk divider - n and m1 */
7347 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7348 DPIO_CHV_M1_DIV_BY_2 |
7349 1 << DPIO_CHV_N_DIV_SHIFT);
7350
7351 /* M2 fraction division */
25a25dfc 7352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML
7353
7354 /* M2 fraction division enable */
a945ce7e
VP
7355 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7356 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7357 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7358 if (bestm2_frac)
7359 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7360 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7361
de3a0fde
VP
7362 /* Program digital lock detect threshold */
7363 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7364 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7365 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7366 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7367 if (!bestm2_frac)
7368 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7369 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7370
9d556c99 7371 /* Loop filter */
9cbe40c1
VP
7372 if (vco == 5400000) {
7373 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7374 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7375 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7376 tribuf_calcntr = 0x9;
7377 } else if (vco <= 6200000) {
7378 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7379 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7380 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7381 tribuf_calcntr = 0x9;
7382 } else if (vco <= 6480000) {
7383 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7384 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7385 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7386 tribuf_calcntr = 0x8;
7387 } else {
7388 /* Not supported. Apply the same limits as in the max case */
7389 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7390 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7391 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7392 tribuf_calcntr = 0;
7393 }
9d556c99
CML
7394 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7395
968040b2 7396 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP
7397 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7398 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7399 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7400
9d556c99
CML
7401 /* AFC Recal */
7402 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7403 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7404 DPIO_AFC_RECAL);
7405
a580516d 7406 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML
7407}
7408
d288f65f
VS
7409/**
7410 * vlv_force_pll_on - forcibly enable just the PLL
7411 * @dev_priv: i915 private structure
7412 * @pipe: pipe PLL to enable
7413 * @dpll: PLL configuration
7414 *
7415 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7416 * in cases where we need the PLL enabled even when @pipe is not going to
7417 * be enabled.
7418 */
7419void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7420 const struct dpll *dpll)
7421{
7422 struct intel_crtc *crtc =
7423 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7424 struct intel_crtc_state pipe_config = {
a93e255f 7425 .base.crtc = &crtc->base,
d288f65f
VS
7426 .pixel_multiplier = 1,
7427 .dpll = *dpll,
7428 };
7429
7430 if (IS_CHERRYVIEW(dev)) {
251ac862 7431 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS
7432 chv_prepare_pll(crtc, &pipe_config);
7433 chv_enable_pll(crtc, &pipe_config);
7434 } else {
251ac862 7435 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS
7436 vlv_prepare_pll(crtc, &pipe_config);
7437 vlv_enable_pll(crtc, &pipe_config);
7438 }
7439}
7440
7441/**
7442 * vlv_force_pll_off - forcibly disable just the PLL
7443 * @dev_priv: i915 private structure
7444 * @pipe: pipe PLL to disable
7445 *
7446 * Disable the PLL for @pipe. To be used in cases where we need
7447 * the PLL enabled even when @pipe is not going to be enabled.
7448 */
7449void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7450{
7451 if (IS_CHERRYVIEW(dev))
7452 chv_disable_pll(to_i915(dev), pipe);
7453 else
7454 vlv_disable_pll(to_i915(dev), pipe);
7455}
7456
251ac862
DV
7457static void i9xx_compute_dpll(struct intel_crtc *crtc,
7458 struct intel_crtc_state *crtc_state,
7459 intel_clock_t *reduced_clock,
7460 int num_connectors)
eb1cbe48 7461{
f47709a9 7462 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7463 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV
7464 u32 dpll;
7465 bool is_sdvo;
190f68c5 7466 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7467
190f68c5 7468 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7469
a93e255f
ACO
7470 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7471 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV
7472
7473 dpll = DPLL_VGA_MODE_DIS;
7474
a93e255f 7475 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV
7476 dpll |= DPLLB_MODE_LVDS;
7477 else
7478 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7479
ef1b460d 7480 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7481 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7482 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7483 }
198a037f
DV
7484
7485 if (is_sdvo)
4a33e48d 7486 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7487
190f68c5 7488 if (crtc_state->has_dp_encoder)
4a33e48d 7489 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV
7490
7491 /* compute bitmask from p1 value */
7492 if (IS_PINEVIEW(dev))
7493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7494 else {
7495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7496 if (IS_G4X(dev) && reduced_clock)
7497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7498 }
7499 switch (clock->p2) {
7500 case 5:
7501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7502 break;
7503 case 7:
7504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7505 break;
7506 case 10:
7507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7508 break;
7509 case 14:
7510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7511 break;
7512 }
7513 if (INTEL_INFO(dev)->gen >= 4)
7514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7515
190f68c5 7516 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7517 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7518 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV
7519 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7520 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7521 else
7522 dpll |= PLL_REF_INPUT_DREFCLK;
7523
7524 dpll |= DPLL_VCO_ENABLE;
190f68c5 7525 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7526
eb1cbe48 7527 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7528 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7529 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7530 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV
7531 }
7532}
7533
251ac862
DV
7534static void i8xx_compute_dpll(struct intel_crtc *crtc,
7535 struct intel_crtc_state *crtc_state,
7536 intel_clock_t *reduced_clock,
7537 int num_connectors)
eb1cbe48 7538{
f47709a9 7539 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7540 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7541 u32 dpll;
190f68c5 7542 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7543
190f68c5 7544 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7545
eb1cbe48
DV
7546 dpll = DPLL_VGA_MODE_DIS;
7547
a93e255f 7548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV
7549 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7550 } else {
7551 if (clock->p1 == 2)
7552 dpll |= PLL_P1_DIVIDE_BY_TWO;
7553 else
7554 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7555 if (clock->p2 == 4)
7556 dpll |= PLL_P2_DIVIDE_BY_4;
7557 }
7558
a93e255f 7559 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV
7560 dpll |= DPLL_DVO_2X_MODE;
7561
a93e255f 7562 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV
7563 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7564 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7565 else
7566 dpll |= PLL_REF_INPUT_DREFCLK;
7567
7568 dpll |= DPLL_VCO_ENABLE;
190f68c5 7569 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV
7570}
7571
8a654f3b 7572static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ
7573{
7574 struct drm_device *dev = intel_crtc->base.dev;
7575 struct drm_i915_private *dev_priv = dev->dev_private;
7576 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7577 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7578 struct drm_display_mode *adjusted_mode =
6e3c9717 7579 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS
7580 uint32_t crtc_vtotal, crtc_vblank_end;
7581 int vsyncshift = 0;
4d8a62ea
DV
7582
7583 /* We need to be careful not to changed the adjusted mode, for otherwise
7584 * the hw state checker will get angry at the mismatch. */
7585 crtc_vtotal = adjusted_mode->crtc_vtotal;
7586 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7587
609aeaca 7588 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7589 /* the chip adds 2 halflines automatically */
4d8a62ea
DV
7590 crtc_vtotal -= 1;
7591 crtc_vblank_end -= 1;
609aeaca 7592
409ee761 7593 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS
7594 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7595 else
7596 vsyncshift = adjusted_mode->crtc_hsync_start -
7597 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS
7598 if (vsyncshift < 0)
7599 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ
7600 }
7601
7602 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7603 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7604
fe2b8f9d 7605 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ
7606 (adjusted_mode->crtc_hdisplay - 1) |
7607 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7608 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ
7609 (adjusted_mode->crtc_hblank_start - 1) |
7610 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7611 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ
7612 (adjusted_mode->crtc_hsync_start - 1) |
7613 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7614
fe2b8f9d 7615 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7616 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7617 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7618 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7619 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7620 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7621 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ
7622 (adjusted_mode->crtc_vsync_start - 1) |
7623 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7624
b5e508d4
PZ
7625 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7626 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7627 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7628 * bits. */
7629 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7630 (pipe == PIPE_B || pipe == PIPE_C))
7631 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7632
b0e77b9c
PZ
7633 /* pipesrc controls the size that is scaled from, which should
7634 * always be the user's requested size.
7635 */
7636 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO
7637 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7638 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ
7639}
7640
1bd1bd80 7641static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7642 struct intel_crtc_state *pipe_config)
1bd1bd80
DV
7643{
7644 struct drm_device *dev = crtc->base.dev;
7645 struct drm_i915_private *dev_priv = dev->dev_private;
7646 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7647 uint32_t tmp;
7648
7649 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO
7650 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7651 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7652 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO
7653 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7654 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7655 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO
7656 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7657 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
7658
7659 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO
7660 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7661 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7662 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO
7663 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7664 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7665 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO
7666 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7667 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
7668
7669 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO
7670 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7671 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7672 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV
7673 }
7674
7675 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS
7676 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7677 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7678
2d112de7
ACO
7679 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7680 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV
7681}
7682
f6a83288 7683void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7684 struct intel_crtc_state *pipe_config)
babea61d 7685{
2d112de7
ACO
7686 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7687 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7688 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7689 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7690
2d112de7
ACO
7691 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7692 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7693 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7694 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7695
2d112de7 7696 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7697 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7698
2d112de7
ACO
7699 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7700 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML
7701
7702 mode->hsync = drm_mode_hsync(mode);
7703 mode->vrefresh = drm_mode_vrefresh(mode);
7704 drm_mode_set_name(mode);
babea61d
JB
7705}
7706
84b046f3
DV
7707static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7708{
7709 struct drm_device *dev = intel_crtc->base.dev;
7710 struct drm_i915_private *dev_priv = dev->dev_private;
7711 uint32_t pipeconf;
7712
9f11a9e4 7713 pipeconf = 0;
84b046f3 7714
b6b5d049
VS
7715 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7716 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7717 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7718
6e3c9717 7719 if (intel_crtc->config->double_wide)
cf532bb2 7720 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7721
ff9ce46e
DV
7722 /* only g4x and later have fancy bpc/dither controls */
7723 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7724 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7725 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7726 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7727 PIPECONF_DITHER_TYPE_SP;
84b046f3 7728
6e3c9717 7729 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV
7730 case 18:
7731 pipeconf |= PIPECONF_6BPC;
7732 break;
7733 case 24:
7734 pipeconf |= PIPECONF_8BPC;
7735 break;
7736 case 30:
7737 pipeconf |= PIPECONF_10BPC;
7738 break;
7739 default:
7740 /* Case prevented by intel_choose_pipe_bpp_dither. */
7741 BUG();
84b046f3
DV
7742 }
7743 }
7744
7745 if (HAS_PIPE_CXSR(dev)) {
7746 if (intel_crtc->lowfreq_avail) {
7747 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7748 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7749 } else {
7750 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV
7751 }
7752 }
7753
6e3c9717 7754 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7755 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7756 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS
7757 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7758 else
7759 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7760 } else
84b046f3
DV
7761 pipeconf |= PIPECONF_PROGRESSIVE;
7762
6e3c9717 7763 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7764 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7765
84b046f3
DV
7766 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7767 POSTING_READ(PIPECONF(intel_crtc->pipe));
7768}
7769
190f68c5
ACO
7770static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7771 struct intel_crtc_state *crtc_state)
79e53945 7772{
c7653199 7773 struct drm_device *dev = crtc->base.dev;
79e53945 7774 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7775 int refclk, num_connectors = 0;
c329a4ec
DV
7776 intel_clock_t clock;
7777 bool ok;
7778 bool is_dsi = false;
5eddb70b 7779 struct intel_encoder *encoder;
d4906093 7780 const intel_limit_t *limit;
55bb9992 7781 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7782 struct drm_connector *connector;
55bb9992
ACO
7783 struct drm_connector_state *connector_state;
7784 int i;
79e53945 7785
dd3cd74a
ACO
7786 memset(&crtc_state->dpll_hw_state, 0,
7787 sizeof(crtc_state->dpll_hw_state));
7788
da3ced29 7789 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
7790 if (connector_state->crtc != &crtc->base)
7791 continue;
7792
7793 encoder = to_intel_encoder(connector_state->best_encoder);
7794
5eddb70b 7795 switch (encoder->type) {
e9fd1c02
JN
7796 case INTEL_OUTPUT_DSI:
7797 is_dsi = true;
7798 break;
6847d71b
PZ
7799 default:
7800 break;
79e53945 7801 }
43565a06 7802
c751ce4f 7803 num_connectors++;
79e53945
JB
7804 }
7805
f2335330 7806 if (is_dsi)
5b18e57c 7807 return 0;
f2335330 7808
190f68c5 7809 if (!crtc_state->clock_set) {
a93e255f 7810 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7811
e9fd1c02
JN
7812 /*
7813 * Returns a set of divisors for the desired target clock with
7814 * the given refclk, or FALSE. The returned values represent
7815 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7816 * 2) / p1 / p2.
7817 */
a93e255f
ACO
7818 limit = intel_limit(crtc_state, refclk);
7819 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7820 crtc_state->port_clock,
e9fd1c02 7821 refclk, NULL, &clock);
f2335330 7822 if (!ok) {
e9fd1c02
JN
7823 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7824 return -EINVAL;
7825 }
79e53945 7826
f2335330 7827 /* Compat-code for transition, will disappear. */
190f68c5
ACO
7828 crtc_state->dpll.n = clock.n;
7829 crtc_state->dpll.m1 = clock.m1;
7830 crtc_state->dpll.m2 = clock.m2;
7831 crtc_state->dpll.p1 = clock.p1;
7832 crtc_state->dpll.p2 = clock.p2;
f47709a9 7833 }
7026d4ac 7834
e9fd1c02 7835 if (IS_GEN2(dev)) {
c329a4ec 7836 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7837 num_connectors);
9d556c99 7838 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7839 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7840 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7841 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7842 } else {
c329a4ec 7843 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7844 num_connectors);
e9fd1c02 7845 }
79e53945 7846
c8f7a0db 7847 return 0;
f564048e
EA
7848}
7849
2fa2fe9a 7850static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7851 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
7852{
7853 struct drm_device *dev = crtc->base.dev;
7854 struct drm_i915_private *dev_priv = dev->dev_private;
7855 uint32_t tmp;
7856
dc9e7dec
VS
7857 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7858 return;
7859
2fa2fe9a 7860 tmp = I915_READ(PFIT_CONTROL);
06922821
DV
7861 if (!(tmp & PFIT_ENABLE))
7862 return;
2fa2fe9a 7863
06922821 7864 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV
7865 if (INTEL_INFO(dev)->gen < 4) {
7866 if (crtc->pipe != PIPE_B)
7867 return;
2fa2fe9a
DV
7868 } else {
7869 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7870 return;
7871 }
7872
06922821 7873 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV
7874 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7875 if (INTEL_INFO(dev)->gen < 5)
7876 pipe_config->gmch_pfit.lvds_border_bits =
7877 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7878}
7879
acbec814 7880static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7881 struct intel_crtc_state *pipe_config)
acbec814
JB
7882{
7883 struct drm_device *dev = crtc->base.dev;
7884 struct drm_i915_private *dev_priv = dev->dev_private;
7885 int pipe = pipe_config->cpu_transcoder;
7886 intel_clock_t clock;
7887 u32 mdiv;
662c6ecb 7888 int refclk = 100000;
acbec814 7889
f573de5a
SK
7890 /* In case of MIPI DPLL will not even be used */
7891 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7892 return;
7893
a580516d 7894 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7895 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7896 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB
7897
7898 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7899 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7900 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7901 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7902 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7903
dccbea3b 7904 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB
7905}
7906
5724dbd1
DL
7907static void
7908i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7909 struct intel_initial_plane_config *plane_config)
1ad292b5
JB
7910{
7911 struct drm_device *dev = crtc->base.dev;
7912 struct drm_i915_private *dev_priv = dev->dev_private;
7913 u32 val, base, offset;
7914 int pipe = crtc->pipe, plane = crtc->plane;
7915 int fourcc, pixel_format;
6761dd31 7916 unsigned int aligned_height;
b113d5ee 7917 struct drm_framebuffer *fb;
1b842c89 7918 struct intel_framebuffer *intel_fb;
1ad292b5 7919
42a7b088
DL
7920 val = I915_READ(DSPCNTR(plane));
7921 if (!(val & DISPLAY_PLANE_ENABLE))
7922 return;
7923
d9806c9f 7924 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7925 if (!intel_fb) {
1ad292b5
JB
7926 DRM_DEBUG_KMS("failed to alloc fb\n");
7927 return;
7928 }
7929
1b842c89
DL
7930 fb = &intel_fb->base;
7931
18c5247e
DV
7932 if (INTEL_INFO(dev)->gen >= 4) {
7933 if (val & DISPPLANE_TILED) {
49af449b 7934 plane_config->tiling = I915_TILING_X;
18c5247e
DV
7935 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7936 }
7937 }
1ad292b5
JB
7938
7939 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7940 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL
7941 fb->pixel_format = fourcc;
7942 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB
7943
7944 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7945 if (plane_config->tiling)
1ad292b5
JB
7946 offset = I915_READ(DSPTILEOFF(plane));
7947 else
7948 offset = I915_READ(DSPLINOFF(plane));
7949 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7950 } else {
7951 base = I915_READ(DSPADDR(plane));
7952 }
7953 plane_config->base = base;
7954
7955 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
7956 fb->width = ((val >> 16) & 0xfff) + 1;
7957 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB
7958
7959 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7960 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7961
b113d5ee 7962 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
7963 fb->pixel_format,
7964 fb->modifier[0]);
1ad292b5 7965
f37b5c2b 7966 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7967
2844a921
DL
7968 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7969 pipe_name(pipe), plane, fb->width, fb->height,
7970 fb->bits_per_pixel, base, fb->pitches[0],
7971 plane_config->size);
1ad292b5 7972
2d14030b 7973 plane_config->fb = intel_fb;
1ad292b5
JB
7974}
7975
70b23a98 7976static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7977 struct intel_crtc_state *pipe_config)
70b23a98
VS
7978{
7979 struct drm_device *dev = crtc->base.dev;
7980 struct drm_i915_private *dev_priv = dev->dev_private;
7981 int pipe = pipe_config->cpu_transcoder;
7982 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7983 intel_clock_t clock;
0d7b6b11 7984 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS
7985 int refclk = 100000;
7986
a580516d 7987 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS
7988 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7989 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7990 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7991 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 7992 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 7993 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS
7994
7995 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID
7996 clock.m2 = (pll_dw0 & 0xff) << 22;
7997 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7998 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS
7999 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8000 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8001 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8002
dccbea3b 8003 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS
8004}
8005
0e8ffe1b 8006static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8007 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
8008{
8009 struct drm_device *dev = crtc->base.dev;
8010 struct drm_i915_private *dev_priv = dev->dev_private;
8011 uint32_t tmp;
8012
f458ebbc
DV
8013 if (!intel_display_power_is_enabled(dev_priv,
8014 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID
8015 return false;
8016
e143a21c 8017 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8018 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8019
0e8ffe1b
DV
8020 tmp = I915_READ(PIPECONF(crtc->pipe));
8021 if (!(tmp & PIPECONF_ENABLE))
8022 return false;
8023
42571aef
VS
8024 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8025 switch (tmp & PIPECONF_BPC_MASK) {
8026 case PIPECONF_6BPC:
8027 pipe_config->pipe_bpp = 18;
8028 break;
8029 case PIPECONF_8BPC:
8030 pipe_config->pipe_bpp = 24;
8031 break;
8032 case PIPECONF_10BPC:
8033 pipe_config->pipe_bpp = 30;
8034 break;
8035 default:
8036 break;
8037 }
8038 }
8039
b5a9fa09
DV
8040 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8041 pipe_config->limited_color_range = true;
8042
282740f7
VS
8043 if (INTEL_INFO(dev)->gen < 4)
8044 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8045
1bd1bd80
DV
8046 intel_get_pipe_timings(crtc, pipe_config);
8047
2fa2fe9a
DV
8048 i9xx_get_pfit_config(crtc, pipe_config);
8049
6c49f241
DV
8050 if (INTEL_INFO(dev)->gen >= 4) {
8051 tmp = I915_READ(DPLL_MD(crtc->pipe));
8052 pipe_config->pixel_multiplier =
8053 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8054 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8055 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV
8056 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8057 tmp = I915_READ(DPLL(crtc->pipe));
8058 pipe_config->pixel_multiplier =
8059 ((tmp & SDVO_MULTIPLIER_MASK)
8060 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8061 } else {
8062 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8063 * port and will be fixed up in the encoder->get_config
8064 * function. */
8065 pipe_config->pixel_multiplier = 1;
8066 }
8bcc2795
DV
8067 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8068 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS
8069 /*
8070 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8071 * on 830. Filter it out here so that we don't
8072 * report errors due to that.
8073 */
8074 if (IS_I830(dev))
8075 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8076
8bcc2795
DV
8077 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8078 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS
8079 } else {
8080 /* Mask out read-only status bits. */
8081 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8082 DPLL_PORTC_READY_MASK |
8083 DPLL_PORTB_READY_MASK);
8bcc2795 8084 }
6c49f241 8085
70b23a98
VS
8086 if (IS_CHERRYVIEW(dev))
8087 chv_crtc_clock_get(crtc, pipe_config);
8088 else if (IS_VALLEYVIEW(dev))
acbec814
JB
8089 vlv_crtc_clock_get(crtc, pipe_config);
8090 else
8091 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8092
0f64614d
VS
8093 /*
8094 * Normally the dotclock is filled in by the encoder .get_config()
8095 * but in case the pipe is enabled w/o any ports we need a sane
8096 * default.
8097 */
8098 pipe_config->base.adjusted_mode.crtc_clock =
8099 pipe_config->port_clock / pipe_config->pixel_multiplier;
8100
0e8ffe1b
DV
8101 return true;
8102}
8103
dde86e2d 8104static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB
8105{
8106 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8107 struct intel_encoder *encoder;
74cfd7ac 8108 u32 val, final;
13d83a67 8109 bool has_lvds = false;
199e5d79 8110 bool has_cpu_edp = false;
199e5d79 8111 bool has_panel = false;
99eb6a01
KP
8112 bool has_ck505 = false;
8113 bool can_ssc = false;
13d83a67
JB
8114
8115 /* We need to take the global config into account */
b2784e15 8116 for_each_intel_encoder(dev, encoder) {
199e5d79
KP
8117 switch (encoder->type) {
8118 case INTEL_OUTPUT_LVDS:
8119 has_panel = true;
8120 has_lvds = true;
8121 break;
8122 case INTEL_OUTPUT_EDP:
8123 has_panel = true;
2de6905f 8124 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP
8125 has_cpu_edp = true;
8126 break;
6847d71b
PZ
8127 default:
8128 break;
13d83a67
JB
8129 }
8130 }
8131
99eb6a01 8132 if (HAS_PCH_IBX(dev)) {
41aa3448 8133 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP
8134 can_ssc = has_ck505;
8135 } else {
8136 has_ck505 = false;
8137 can_ssc = true;
8138 }
8139
2de6905f
ID
8140 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8141 has_panel, has_lvds, has_ck505);
13d83a67
JB
8142
8143 /* Ironlake: try to setup display ref clock before DPLL
8144 * enabling. This is only under driver's control after
8145 * PCH B stepping, previous chipset stepping should be
8146 * ignoring this setting.
8147 */
74cfd7ac
CW
8148 val = I915_READ(PCH_DREF_CONTROL);
8149
8150 /* As we must carefully and slowly disable/enable each source in turn,
8151 * compute the final state we want first and check if we need to
8152 * make any changes at all.
8153 */
8154 final = val;
8155 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8156 if (has_ck505)
8157 final |= DREF_NONSPREAD_CK505_ENABLE;
8158 else
8159 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8160
8161 final &= ~DREF_SSC_SOURCE_MASK;
8162 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8163 final &= ~DREF_SSC1_ENABLE;
8164
8165 if (has_panel) {
8166 final |= DREF_SSC_SOURCE_ENABLE;
8167
8168 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8169 final |= DREF_SSC1_ENABLE;
8170
8171 if (has_cpu_edp) {
8172 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8173 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8174 else
8175 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8176 } else
8177 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8178 } else {
8179 final |= DREF_SSC_SOURCE_DISABLE;
8180 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8181 }
8182
8183 if (final == val)
8184 return;
8185
13d83a67 8186 /* Always enable nonspread source */
74cfd7ac 8187 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8188
99eb6a01 8189 if (has_ck505)
74cfd7ac 8190 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8191 else
74cfd7ac 8192 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8193
199e5d79 8194 if (has_panel) {
74cfd7ac
CW
8195 val &= ~DREF_SSC_SOURCE_MASK;
8196 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8197
199e5d79 8198 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8199 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8200 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8201 val |= DREF_SSC1_ENABLE;
e77166b5 8202 } else
74cfd7ac 8203 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP
8204
8205 /* Get SSC going before enabling the outputs */
74cfd7ac 8206 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8207 POSTING_READ(PCH_DREF_CONTROL);
8208 udelay(200);
8209
74cfd7ac 8210 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB
8211
8212 /* Enable CPU source on CPU attached eDP */
199e5d79 8213 if (has_cpu_edp) {
99eb6a01 8214 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8215 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8216 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8217 } else
74cfd7ac 8218 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8219 } else
74cfd7ac 8220 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8221
74cfd7ac 8222 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8223 POSTING_READ(PCH_DREF_CONTROL);
8224 udelay(200);
8225 } else {
8226 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8227
74cfd7ac 8228 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP
8229
8230 /* Turn off CPU output */
74cfd7ac 8231 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8232
74cfd7ac 8233 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8234 POSTING_READ(PCH_DREF_CONTROL);
8235 udelay(200);
8236
8237 /* Turn off the SSC source */
74cfd7ac
CW
8238 val &= ~DREF_SSC_SOURCE_MASK;
8239 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP
8240
8241 /* Turn off SSC1 */
74cfd7ac 8242 val &= ~DREF_SSC1_ENABLE;
199e5d79 8243
74cfd7ac 8244 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB
8245 POSTING_READ(PCH_DREF_CONTROL);
8246 udelay(200);
8247 }
74cfd7ac
CW
8248
8249 BUG_ON(val != final);
13d83a67
JB
8250}
8251
f31f2d55 8252static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8253{
f31f2d55 8254 uint32_t tmp;
dde86e2d 8255
0ff066a9
PZ
8256 tmp = I915_READ(SOUTH_CHICKEN2);
8257 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8258 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8259
0ff066a9
PZ
8260 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8261 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8262 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8263
0ff066a9
PZ
8264 tmp = I915_READ(SOUTH_CHICKEN2);
8265 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8266 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8267
0ff066a9
PZ
8268 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8269 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8270 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ
8271}
8272
8273/* WaMPhyProgramming:hsw */
8274static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8275{
8276 uint32_t tmp;
dde86e2d
PZ
8277
8278 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8279 tmp &= ~(0xFF << 24);
8280 tmp |= (0x12 << 24);
8281 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8282
dde86e2d
PZ
8283 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8284 tmp |= (1 << 11);
8285 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8286
8287 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8288 tmp |= (1 << 11);
8289 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8290
dde86e2d
PZ
8291 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8292 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8293 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8294
8295 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8296 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8297 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8298
0ff066a9
PZ
8299 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8300 tmp &= ~(7 << 13);
8301 tmp |= (5 << 13);
8302 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8303
0ff066a9
PZ
8304 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8305 tmp &= ~(7 << 13);
8306 tmp |= (5 << 13);
8307 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ
8308
8309 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8310 tmp &= ~0xFF;
8311 tmp |= 0x1C;
8312 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8313
8314 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8315 tmp &= ~0xFF;
8316 tmp |= 0x1C;
8317 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8318
8319 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8320 tmp &= ~(0xFF << 16);
8321 tmp |= (0x1C << 16);
8322 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8323
8324 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8325 tmp &= ~(0xFF << 16);
8326 tmp |= (0x1C << 16);
8327 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8328
0ff066a9
PZ
8329 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8330 tmp |= (1 << 27);
8331 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8332
0ff066a9
PZ
8333 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8334 tmp |= (1 << 27);
8335 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8336
0ff066a9
PZ
8337 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8338 tmp &= ~(0xF << 28);
8339 tmp |= (4 << 28);
8340 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8341
0ff066a9
PZ
8342 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8343 tmp &= ~(0xF << 28);
8344 tmp |= (4 << 28);
8345 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ
8346}
8347
2fa86a1f
PZ
8348/* Implements 3 different sequences from BSpec chapter "Display iCLK
8349 * Programming" based on the parameters passed:
8350 * - Sequence to enable CLKOUT_DP
8351 * - Sequence to enable CLKOUT_DP without spread
8352 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8353 */
8354static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8355 bool with_fdi)
f31f2d55
PZ
8356{
8357 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ
8358 uint32_t reg, tmp;
8359
8360 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8361 with_spread = true;
8362 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8363 with_fdi, "LP PCH doesn't have FDI\n"))
8364 with_fdi = false;
f31f2d55 8365
a580516d 8366 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ
8367
8368 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8369 tmp &= ~SBI_SSCCTL_DISABLE;
8370 tmp |= SBI_SSCCTL_PATHALT;
8371 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8372
8373 udelay(24);
8374
2fa86a1f
PZ
8375 if (with_spread) {
8376 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8377 tmp &= ~SBI_SSCCTL_PATHALT;
8378 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8379
2fa86a1f
PZ
8380 if (with_fdi) {
8381 lpt_reset_fdi_mphy(dev_priv);
8382 lpt_program_fdi_mphy(dev_priv);
8383 }
8384 }
dde86e2d 8385
2fa86a1f
PZ
8386 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8387 SBI_GEN0 : SBI_DBUFF0;
8388 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8389 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8390 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8391
a580516d 8392 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ
8393}
8394
47701c3b
PZ
8395/* Sequence to disable CLKOUT_DP */
8396static void lpt_disable_clkout_dp(struct drm_device *dev)
8397{
8398 struct drm_i915_private *dev_priv = dev->dev_private;
8399 uint32_t reg, tmp;
8400
a580516d 8401 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ
8402
8403 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8404 SBI_GEN0 : SBI_DBUFF0;
8405 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8406 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8407 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8408
8409 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8410 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8411 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8412 tmp |= SBI_SSCCTL_PATHALT;
8413 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8414 udelay(32);
8415 }
8416 tmp |= SBI_SSCCTL_DISABLE;
8417 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8418 }
8419
a580516d 8420 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ
8421}
8422
bf8fa3d3
PZ
8423static void lpt_init_pch_refclk(struct drm_device *dev)
8424{
bf8fa3d3
PZ
8425 struct intel_encoder *encoder;
8426 bool has_vga = false;
8427
b2784e15 8428 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ
8429 switch (encoder->type) {
8430 case INTEL_OUTPUT_ANALOG:
8431 has_vga = true;
8432 break;
6847d71b
PZ
8433 default:
8434 break;
bf8fa3d3
PZ
8435 }
8436 }
8437
47701c3b
PZ
8438 if (has_vga)
8439 lpt_enable_clkout_dp(dev, true, true);
8440 else
8441 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ
8442}
8443
dde86e2d
PZ
8444/*
8445 * Initialize reference clocks when the driver loads
8446 */
8447void intel_init_pch_refclk(struct drm_device *dev)
8448{
8449 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8450 ironlake_init_pch_refclk(dev);
8451 else if (HAS_PCH_LPT(dev))
8452 lpt_init_pch_refclk(dev);
8453}
8454
55bb9992 8455static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8456{
55bb9992 8457 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8458 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8459 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8460 struct drm_connector *connector;
55bb9992 8461 struct drm_connector_state *connector_state;
d9d444cb 8462 struct intel_encoder *encoder;
55bb9992 8463 int num_connectors = 0, i;
d9d444cb
JB
8464 bool is_lvds = false;
8465
da3ced29 8466 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
8467 if (connector_state->crtc != crtc_state->base.crtc)
8468 continue;
8469
8470 encoder = to_intel_encoder(connector_state->best_encoder);
8471
d9d444cb
JB
8472 switch (encoder->type) {
8473 case INTEL_OUTPUT_LVDS:
8474 is_lvds = true;
8475 break;
6847d71b
PZ
8476 default:
8477 break;
d9d444cb
JB
8478 }
8479 num_connectors++;
8480 }
8481
8482 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8483 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8484 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8485 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB
8486 }
8487
8488 return 120000;
8489}
8490
6ff93609 8491static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8492{
c8203565 8493 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB
8494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8495 int pipe = intel_crtc->pipe;
c8203565
PZ
8496 uint32_t val;
8497
78114071 8498 val = 0;
c8203565 8499
6e3c9717 8500 switch (intel_crtc->config->pipe_bpp) {
c8203565 8501 case 18:
dfd07d72 8502 val |= PIPECONF_6BPC;
c8203565
PZ
8503 break;
8504 case 24:
dfd07d72 8505 val |= PIPECONF_8BPC;
c8203565
PZ
8506 break;
8507 case 30:
dfd07d72 8508 val |= PIPECONF_10BPC;
c8203565
PZ
8509 break;
8510 case 36:
dfd07d72 8511 val |= PIPECONF_12BPC;
c8203565
PZ
8512 break;
8513 default:
cc769b62
PZ
8514 /* Case prevented by intel_choose_pipe_bpp_dither. */
8515 BUG();
c8203565
PZ
8516 }
8517
6e3c9717 8518 if (intel_crtc->config->dither)
c8203565
PZ
8519 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8520
6e3c9717 8521 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ
8522 val |= PIPECONF_INTERLACED_ILK;
8523 else
8524 val |= PIPECONF_PROGRESSIVE;
8525
6e3c9717 8526 if (intel_crtc->config->limited_color_range)
3685a8f3 8527 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8528
c8203565
PZ
8529 I915_WRITE(PIPECONF(pipe), val);
8530 POSTING_READ(PIPECONF(pipe));
8531}
8532
86d3efce
VS
8533/*
8534 * Set up the pipe CSC unit.
8535 *
8536 * Currently only full range RGB to limited range RGB conversion
8537 * is supported, but eventually this should handle various
8538 * RGB<->YCbCr scenarios as well.
8539 */
50f3b016 8540static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS
8541{
8542 struct drm_device *dev = crtc->dev;
8543 struct drm_i915_private *dev_priv = dev->dev_private;
8544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8545 int pipe = intel_crtc->pipe;
8546 uint16_t coeff = 0x7800; /* 1.0 */
8547
8548 /*
8549 * TODO: Check what kind of values actually come out of the pipe
8550 * with these coeff/postoff values and adjust to get the best
8551 * accuracy. Perhaps we even need to take the bpc value into
8552 * consideration.
8553 */
8554
6e3c9717 8555 if (intel_crtc->config->limited_color_range)
86d3efce
VS
8556 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8557
8558 /*
8559 * GY/GU and RY/RU should be the other way around according
8560 * to BSpec, but reality doesn't agree. Just set them up in
8561 * a way that results in the correct picture.
8562 */
8563 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8564 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8565
8566 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8567 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8568
8569 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8570 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8571
8572 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8573 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8574 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8575
8576 if (INTEL_INFO(dev)->gen > 6) {
8577 uint16_t postoff = 0;
8578
6e3c9717 8579 if (intel_crtc->config->limited_color_range)
32cf0cb0 8580 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS
8581
8582 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8583 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8584 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8585
8586 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8587 } else {
8588 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8589
6e3c9717 8590 if (intel_crtc->config->limited_color_range)
86d3efce
VS
8591 mode |= CSC_BLACK_SCREEN_OFFSET;
8592
8593 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8594 }
8595}
8596
6ff93609 8597static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8598{
756f85cf
PZ
8599 struct drm_device *dev = crtc->dev;
8600 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8602 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8603 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ
8604 uint32_t val;
8605
3eff4faa 8606 val = 0;
ee2b0b38 8607
6e3c9717 8608 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ
8609 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8610
6e3c9717 8611 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ
8612 val |= PIPECONF_INTERLACED_ILK;
8613 else
8614 val |= PIPECONF_PROGRESSIVE;
8615
702e7a56
PZ
8616 I915_WRITE(PIPECONF(cpu_transcoder), val);
8617 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV
8618
8619 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8620 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8621
3cdf122c 8622 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ
8623 val = 0;
8624
6e3c9717 8625 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ
8626 case 18:
8627 val |= PIPEMISC_DITHER_6_BPC;
8628 break;
8629 case 24:
8630 val |= PIPEMISC_DITHER_8_BPC;
8631 break;
8632 case 30:
8633 val |= PIPEMISC_DITHER_10_BPC;
8634 break;
8635 case 36:
8636 val |= PIPEMISC_DITHER_12_BPC;
8637 break;
8638 default:
8639 /* Case prevented by pipe_config_set_bpp. */
8640 BUG();
8641 }
8642
6e3c9717 8643 if (intel_crtc->config->dither)
756f85cf
PZ
8644 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8645
8646 I915_WRITE(PIPEMISC(pipe), val);
8647 }
ee2b0b38
PZ
8648}
8649
6591c6e4 8650static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8651 struct intel_crtc_state *crtc_state,
6591c6e4
PZ
8652 intel_clock_t *clock,
8653 bool *has_reduced_clock,
8654 intel_clock_t *reduced_clock)
8655{
8656 struct drm_device *dev = crtc->dev;
8657 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8658 int refclk;
d4906093 8659 const intel_limit_t *limit;
c329a4ec 8660 bool ret;
79e53945 8661
55bb9992 8662 refclk = ironlake_get_refclk(crtc_state);
79e53945 8663
d4906093
ML
8664 /*
8665 * Returns a set of divisors for the desired target clock with the given
8666 * refclk, or FALSE. The returned values represent the clock equation:
8667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8668 */
a93e255f
ACO
8669 limit = intel_limit(crtc_state, refclk);
8670 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8671 crtc_state->port_clock,
ee9300bb 8672 refclk, NULL, clock);
6591c6e4
PZ
8673 if (!ret)
8674 return false;
cda4b7d3 8675
6591c6e4
PZ
8676 return true;
8677}
8678
d4b1931c
PZ
8679int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8680{
8681 /*
8682 * Account for spread spectrum to avoid
8683 * oversubscribing the link. Max center spread
8684 * is 2.5%; use 5% for safety's sake.
8685 */
8686 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8687 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ
8688}
8689
7429e9d4 8690static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8691{
7429e9d4 8692 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ
8693}
8694
de13a2e3 8695static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8696 struct intel_crtc_state *crtc_state,
7429e9d4 8697 u32 *fp,
9a7c7890 8698 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8699{
de13a2e3 8700 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB
8701 struct drm_device *dev = crtc->dev;
8702 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8703 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8704 struct drm_connector *connector;
55bb9992
ACO
8705 struct drm_connector_state *connector_state;
8706 struct intel_encoder *encoder;
de13a2e3 8707 uint32_t dpll;
55bb9992 8708 int factor, num_connectors = 0, i;
09ede541 8709 bool is_lvds = false, is_sdvo = false;
79e53945 8710
da3ced29 8711 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
8712 if (connector_state->crtc != crtc_state->base.crtc)
8713 continue;
8714
8715 encoder = to_intel_encoder(connector_state->best_encoder);
8716
8717 switch (encoder->type) {
79e53945
JB
8718 case INTEL_OUTPUT_LVDS:
8719 is_lvds = true;
8720 break;
8721 case INTEL_OUTPUT_SDVO:
7d57382e 8722 case INTEL_OUTPUT_HDMI:
79e53945 8723 is_sdvo = true;
79e53945 8724 break;
6847d71b
PZ
8725 default:
8726 break;
79e53945 8727 }
43565a06 8728
c751ce4f 8729 num_connectors++;
79e53945 8730 }
79e53945 8731
c1858123 8732 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA
8733 factor = 21;
8734 if (is_lvds) {
8735 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8736 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8737 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8738 factor = 25;
190f68c5 8739 } else if (crtc_state->sdvo_tv_clock)
8febb297 8740 factor = 20;
c1858123 8741
190f68c5 8742 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8743 *fp |= FP_CB_TUNE;
2c07245f 8744
9a7c7890
DV
8745 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8746 *fp2 |= FP_CB_TUNE;
8747
5eddb70b 8748 dpll = 0;
2c07245f 8749
a07d6787
EA
8750 if (is_lvds)
8751 dpll |= DPLLB_MODE_LVDS;
8752 else
8753 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8754
190f68c5 8755 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8756 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV
8757
8758 if (is_sdvo)
4a33e48d 8759 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8760 if (crtc_state->has_dp_encoder)
4a33e48d 8761 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8762
a07d6787 8763 /* compute bitmask from p1 value */
190f68c5 8764 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8765 /* also FPA1 */
190f68c5 8766 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8767
190f68c5 8768 switch (crtc_state->dpll.p2) {
a07d6787
EA
8769 case 5:
8770 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8771 break;
8772 case 7:
8773 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8774 break;
8775 case 10:
8776 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8777 break;
8778 case 14:
8779 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8780 break;
79e53945
JB
8781 }
8782
b4c09f3b 8783 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8784 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB
8785 else
8786 dpll |= PLL_REF_INPUT_DREFCLK;
8787
959e16d6 8788 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ
8789}
8790
190f68c5
ACO
8791static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8792 struct intel_crtc_state *crtc_state)
de13a2e3 8793{
c7653199 8794 struct drm_device *dev = crtc->base.dev;
de13a2e3 8795 intel_clock_t clock, reduced_clock;
cbbab5bd 8796 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8797 bool ok, has_reduced_clock = false;
8b47047b 8798 bool is_lvds = false;
e2b78267 8799 struct intel_shared_dpll *pll;
de13a2e3 8800
dd3cd74a
ACO
8801 memset(&crtc_state->dpll_hw_state, 0,
8802 sizeof(crtc_state->dpll_hw_state));
8803
409ee761 8804 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8805
5dc5298b
PZ
8806 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8807 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8808
190f68c5 8809 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8810 &has_reduced_clock, &reduced_clock);
190f68c5 8811 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ
8812 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8813 return -EINVAL;
79e53945 8814 }
f47709a9 8815 /* Compat-code for transition, will disappear. */
190f68c5
ACO
8816 if (!crtc_state->clock_set) {
8817 crtc_state->dpll.n = clock.n;
8818 crtc_state->dpll.m1 = clock.m1;
8819 crtc_state->dpll.m2 = clock.m2;
8820 crtc_state->dpll.p1 = clock.p1;
8821 crtc_state->dpll.p2 = clock.p2;
f47709a9 8822 }
79e53945 8823
5dc5298b 8824 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO
8825 if (crtc_state->has_pch_encoder) {
8826 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8827 if (has_reduced_clock)
7429e9d4 8828 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8829
190f68c5 8830 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV
8831 &fp, &reduced_clock,
8832 has_reduced_clock ? &fp2 : NULL);
8833
190f68c5
ACO
8834 crtc_state->dpll_hw_state.dpll = dpll;
8835 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8836 if (has_reduced_clock)
190f68c5 8837 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8838 else
190f68c5 8839 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8840
190f68c5 8841 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8842 if (pll == NULL) {
84f44ce7 8843 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8844 pipe_name(crtc->pipe));
4b645f14
JB
8845 return -EINVAL;
8846 }
3fb37703 8847 }
79e53945 8848
ab585dea 8849 if (is_lvds && has_reduced_clock)
c7653199 8850 crtc->lowfreq_avail = true;
bcd644e0 8851 else
c7653199 8852 crtc->lowfreq_avail = false;
e2b78267 8853
c8f7a0db 8854 return 0;
79e53945
JB
8855}
8856
eb14cb74
VS
8857static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8858 struct intel_link_m_n *m_n)
8859{
8860 struct drm_device *dev = crtc->base.dev;
8861 struct drm_i915_private *dev_priv = dev->dev_private;
8862 enum pipe pipe = crtc->pipe;
8863
8864 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8865 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8866 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8867 & ~TU_SIZE_MASK;
8868 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8869 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8870 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8871}
8872
8873static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8874 enum transcoder transcoder,
b95af8be
VK
8875 struct intel_link_m_n *m_n,
8876 struct intel_link_m_n *m2_n2)
72419203
DV
8877{
8878 struct drm_device *dev = crtc->base.dev;
8879 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8880 enum pipe pipe = crtc->pipe;
72419203 8881
eb14cb74
VS
8882 if (INTEL_INFO(dev)->gen >= 5) {
8883 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8884 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8885 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8886 & ~TU_SIZE_MASK;
8887 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8888 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8889 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK
8890 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8891 * gen < 8) and if DRRS is supported (to make sure the
8892 * registers are not unnecessarily read).
8893 */
8894 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8895 crtc->config->has_drrs) {
b95af8be
VK
8896 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8897 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8898 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8899 & ~TU_SIZE_MASK;
8900 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8901 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8902 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8903 }
eb14cb74
VS
8904 } else {
8905 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8906 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8907 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8908 & ~TU_SIZE_MASK;
8909 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8910 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8911 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8912 }
8913}
8914
8915void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8916 struct intel_crtc_state *pipe_config)
eb14cb74 8917{
681a8504 8918 if (pipe_config->has_pch_encoder)
eb14cb74
VS
8919 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8920 else
8921 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK
8922 &pipe_config->dp_m_n,
8923 &pipe_config->dp_m2_n2);
eb14cb74 8924}
72419203 8925
eb14cb74 8926static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8927 struct intel_crtc_state *pipe_config)
eb14cb74
VS
8928{
8929 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8930 &pipe_config->fdi_m_n, NULL);
72419203
DV
8931}
8932
bd2e244f 8933static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8934 struct intel_crtc_state *pipe_config)
bd2e244f
JB
8935{
8936 struct drm_device *dev = crtc->base.dev;
8937 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK
8938 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8939 uint32_t ps_ctrl = 0;
8940 int id = -1;
8941 int i;
bd2e244f 8942
a1b2278e
CK
8943 /* find scaler attached to this pipe */
8944 for (i = 0; i < crtc->num_scalers; i++) {
8945 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8946 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8947 id = i;
8948 pipe_config->pch_pfit.enabled = true;
8949 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8950 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8951 break;
8952 }
8953 }
bd2e244f 8954
a1b2278e
CK
8955 scaler_state->scaler_id = id;
8956 if (id >= 0) {
8957 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8958 } else {
8959 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB
8960 }
8961}
8962
5724dbd1
DL
8963static void
8964skylake_get_initial_plane_config(struct intel_crtc *crtc,
8965 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL
8966{
8967 struct drm_device *dev = crtc->base.dev;
8968 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8969 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL
8970 int pipe = crtc->pipe;
8971 int fourcc, pixel_format;
6761dd31 8972 unsigned int aligned_height;
bc8d7dff 8973 struct drm_framebuffer *fb;
1b842c89 8974 struct intel_framebuffer *intel_fb;
bc8d7dff 8975
d9806c9f 8976 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8977 if (!intel_fb) {
bc8d7dff
DL
8978 DRM_DEBUG_KMS("failed to alloc fb\n");
8979 return;
8980 }
8981
1b842c89
DL
8982 fb = &intel_fb->base;
8983
bc8d7dff 8984 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL
8985 if (!(val & PLANE_CTL_ENABLE))
8986 goto error;
8987
bc8d7dff
DL
8988 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8989 fourcc = skl_format_to_fourcc(pixel_format,
8990 val & PLANE_CTL_ORDER_RGBX,
8991 val & PLANE_CTL_ALPHA_MASK);
8992 fb->pixel_format = fourcc;
8993 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8994
40f46283
DL
8995 tiling = val & PLANE_CTL_TILED_MASK;
8996 switch (tiling) {
8997 case PLANE_CTL_TILED_LINEAR:
8998 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8999 break;
9000 case PLANE_CTL_TILED_X:
9001 plane_config->tiling = I915_TILING_X;
9002 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9003 break;
9004 case PLANE_CTL_TILED_Y:
9005 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9006 break;
9007 case PLANE_CTL_TILED_YF:
9008 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9009 break;
9010 default:
9011 MISSING_CASE(tiling);
9012 goto error;
9013 }
9014
bc8d7dff
DL
9015 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9016 plane_config->base = base;
9017
9018 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9019
9020 val = I915_READ(PLANE_SIZE(pipe, 0));
9021 fb->height = ((val >> 16) & 0xfff) + 1;
9022 fb->width = ((val >> 0) & 0x1fff) + 1;
9023
9024 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL
9025 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9026 fb->pixel_format);
bc8d7dff
DL
9027 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9028
9029 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
9030 fb->pixel_format,
9031 fb->modifier[0]);
bc8d7dff 9032
f37b5c2b 9033 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL
9034
9035 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9036 pipe_name(pipe), fb->width, fb->height,
9037 fb->bits_per_pixel, base, fb->pitches[0],
9038 plane_config->size);
9039
2d14030b 9040 plane_config->fb = intel_fb;
bc8d7dff
DL
9041 return;
9042
9043error:
9044 kfree(fb);
9045}
9046
2fa2fe9a 9047static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9048 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
9049{
9050 struct drm_device *dev = crtc->base.dev;
9051 struct drm_i915_private *dev_priv = dev->dev_private;
9052 uint32_t tmp;
9053
9054 tmp = I915_READ(PF_CTL(crtc->pipe));
9055
9056 if (tmp & PF_ENABLE) {
fd4daa9c 9057 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV
9058 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9059 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV
9060
9061 /* We currently do not free assignements of panel fitters on
9062 * ivb/hsw (since we don't use the higher upscaling modes which
9063 * differentiates them) so just WARN about this case for now. */
9064 if (IS_GEN7(dev)) {
9065 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9066 PF_PIPE_SEL_IVB(crtc->pipe));
9067 }
2fa2fe9a 9068 }
79e53945
JB
9069}
9070
5724dbd1
DL
9071static void
9072ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9073 struct intel_initial_plane_config *plane_config)
4c6baa59
JB
9074{
9075 struct drm_device *dev = crtc->base.dev;
9076 struct drm_i915_private *dev_priv = dev->dev_private;
9077 u32 val, base, offset;
aeee5a49 9078 int pipe = crtc->pipe;
4c6baa59 9079 int fourcc, pixel_format;
6761dd31 9080 unsigned int aligned_height;
b113d5ee 9081 struct drm_framebuffer *fb;
1b842c89 9082 struct intel_framebuffer *intel_fb;
4c6baa59 9083
42a7b088
DL
9084 val = I915_READ(DSPCNTR(pipe));
9085 if (!(val & DISPLAY_PLANE_ENABLE))
9086 return;
9087
d9806c9f 9088 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9089 if (!intel_fb) {
4c6baa59
JB
9090 DRM_DEBUG_KMS("failed to alloc fb\n");
9091 return;
9092 }
9093
1b842c89
DL
9094 fb = &intel_fb->base;
9095
18c5247e
DV
9096 if (INTEL_INFO(dev)->gen >= 4) {
9097 if (val & DISPPLANE_TILED) {
49af449b 9098 plane_config->tiling = I915_TILING_X;
18c5247e
DV
9099 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9100 }
9101 }
4c6baa59
JB
9102
9103 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9104 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL
9105 fb->pixel_format = fourcc;
9106 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9107
aeee5a49 9108 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9109 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9110 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9111 } else {
49af449b 9112 if (plane_config->tiling)
aeee5a49 9113 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9114 else
aeee5a49 9115 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB
9116 }
9117 plane_config->base = base;
9118
9119 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
9120 fb->width = ((val >> 16) & 0xfff) + 1;
9121 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB
9122
9123 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9124 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9125
b113d5ee 9126 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
9127 fb->pixel_format,
9128 fb->modifier[0]);
4c6baa59 9129
f37b5c2b 9130 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9131
2844a921
DL
9132 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9133 pipe_name(pipe), fb->width, fb->height,
9134 fb->bits_per_pixel, base, fb->pitches[0],
9135 plane_config->size);
b113d5ee 9136
2d14030b 9137 plane_config->fb = intel_fb;
4c6baa59
JB
9138}
9139
0e8ffe1b 9140static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9141 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
9142{
9143 struct drm_device *dev = crtc->base.dev;
9144 struct drm_i915_private *dev_priv = dev->dev_private;
9145 uint32_t tmp;
9146
f458ebbc
DV
9147 if (!intel_display_power_is_enabled(dev_priv,
9148 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ
9149 return false;
9150
e143a21c 9151 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9152 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9153
0e8ffe1b
DV
9154 tmp = I915_READ(PIPECONF(crtc->pipe));
9155 if (!(tmp & PIPECONF_ENABLE))
9156 return false;
9157
42571aef
VS
9158 switch (tmp & PIPECONF_BPC_MASK) {
9159 case PIPECONF_6BPC:
9160 pipe_config->pipe_bpp = 18;
9161 break;
9162 case PIPECONF_8BPC:
9163 pipe_config->pipe_bpp = 24;
9164 break;
9165 case PIPECONF_10BPC:
9166 pipe_config->pipe_bpp = 30;
9167 break;
9168 case PIPECONF_12BPC:
9169 pipe_config->pipe_bpp = 36;
9170 break;
9171 default:
9172 break;
9173 }
9174
b5a9fa09
DV
9175 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9176 pipe_config->limited_color_range = true;
9177
ab9412ba 9178 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV
9179 struct intel_shared_dpll *pll;
9180
88adfff1
DV
9181 pipe_config->has_pch_encoder = true;
9182
627eb5a3
DV
9183 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9184 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9185 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV
9186
9187 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9188
c0d43d62 9189 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV
9190 pipe_config->shared_dpll =
9191 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV
9192 } else {
9193 tmp = I915_READ(PCH_DPLL_SEL);
9194 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9195 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9196 else
9197 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9198 }
66e985c0
DV
9199
9200 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9201
9202 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9203 &pipe_config->dpll_hw_state));
c93f54cf
DV
9204
9205 tmp = pipe_config->dpll_hw_state.dpll;
9206 pipe_config->pixel_multiplier =
9207 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9208 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS
9209
9210 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV
9211 } else {
9212 pipe_config->pixel_multiplier = 1;
627eb5a3
DV
9213 }
9214
1bd1bd80
DV
9215 intel_get_pipe_timings(crtc, pipe_config);
9216
2fa2fe9a
DV
9217 ironlake_get_pfit_config(crtc, pipe_config);
9218
0e8ffe1b
DV
9219 return true;
9220}
9221
be256dc7
PZ
9222static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9223{
9224 struct drm_device *dev = dev_priv->dev;
be256dc7 9225 struct intel_crtc *crtc;
be256dc7 9226
d3fcc808 9227 for_each_intel_crtc(dev, crtc)
e2c719b7 9228 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ
9229 pipe_name(crtc->pipe));
9230
e2c719b7
RC
9231 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9232 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9233 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9234 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9235 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9236 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9237 "CPU PWM1 enabled\n");
c5107b87 9238 if (IS_HASWELL(dev))
e2c719b7 9239 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9240 "CPU PWM2 enabled\n");
e2c719b7 9241 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9242 "PCH PWM1 enabled\n");
e2c719b7 9243 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9244 "Utility pin enabled\n");
e2c719b7 9245 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9246
9926ada1
PZ
9247 /*
9248 * In theory we can still leave IRQs enabled, as long as only the HPD
9249 * interrupts remain enabled. We used to check for that, but since it's
9250 * gen-specific and since we only disable LCPLL after we fully disable
9251 * the interrupts, the check below should be enough.
9252 */
e2c719b7 9253 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ
9254}
9255
9ccd5aeb
PZ
9256static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9257{
9258 struct drm_device *dev = dev_priv->dev;
9259
9260 if (IS_HASWELL(dev))
9261 return I915_READ(D_COMP_HSW);
9262 else
9263 return I915_READ(D_COMP_BDW);
9264}
9265
3c4c9b81
PZ
9266static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9267{
9268 struct drm_device *dev = dev_priv->dev;
9269
9270 if (IS_HASWELL(dev)) {
9271 mutex_lock(&dev_priv->rps.hw_lock);
9272 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9273 val))
f475dadf 9274 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ
9275 mutex_unlock(&dev_priv->rps.hw_lock);
9276 } else {
9ccd5aeb
PZ
9277 I915_WRITE(D_COMP_BDW, val);
9278 POSTING_READ(D_COMP_BDW);
3c4c9b81 9279 }
be256dc7
PZ
9280}
9281
9282/*
9283 * This function implements pieces of two sequences from BSpec:
9284 * - Sequence for display software to disable LCPLL
9285 * - Sequence for display software to allow package C8+
9286 * The steps implemented here are just the steps that actually touch the LCPLL
9287 * register. Callers should take care of disabling all the display engine
9288 * functions, doing the mode unset, fixing interrupts, etc.
9289 */
6ff58d53
PZ
9290static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9291 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ
9292{
9293 uint32_t val;
9294
9295 assert_can_disable_lcpll(dev_priv);
9296
9297 val = I915_READ(LCPLL_CTL);
9298
9299 if (switch_to_fclk) {
9300 val |= LCPLL_CD_SOURCE_FCLK;
9301 I915_WRITE(LCPLL_CTL, val);
9302
9303 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9304 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9305 DRM_ERROR("Switching to FCLK failed\n");
9306
9307 val = I915_READ(LCPLL_CTL);
9308 }
9309
9310 val |= LCPLL_PLL_DISABLE;
9311 I915_WRITE(LCPLL_CTL, val);
9312 POSTING_READ(LCPLL_CTL);
9313
9314 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9315 DRM_ERROR("LCPLL still locked\n");
9316
9ccd5aeb 9317 val = hsw_read_dcomp(dev_priv);
be256dc7 9318 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9319 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
9320 ndelay(100);
9321
9ccd5aeb
PZ
9322 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9323 1))
be256dc7
PZ
9324 DRM_ERROR("D_COMP RCOMP still in progress\n");
9325
9326 if (allow_power_down) {
9327 val = I915_READ(LCPLL_CTL);
9328 val |= LCPLL_POWER_DOWN_ALLOW;
9329 I915_WRITE(LCPLL_CTL, val);
9330 POSTING_READ(LCPLL_CTL);
9331 }
9332}
9333
9334/*
9335 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9336 * source.
9337 */
6ff58d53 9338static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ
9339{
9340 uint32_t val;
9341
9342 val = I915_READ(LCPLL_CTL);
9343
9344 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9345 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9346 return;
9347
a8a8bd54
PZ
9348 /*
9349 * Make sure we're not on PC8 state before disabling PC8, otherwise
9350 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9351 */
59bad947 9352 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9353
be256dc7
PZ
9354 if (val & LCPLL_POWER_DOWN_ALLOW) {
9355 val &= ~LCPLL_POWER_DOWN_ALLOW;
9356 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9357 POSTING_READ(LCPLL_CTL);
be256dc7
PZ
9358 }
9359
9ccd5aeb 9360 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ
9361 val |= D_COMP_COMP_FORCE;
9362 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9363 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
9364
9365 val = I915_READ(LCPLL_CTL);
9366 val &= ~LCPLL_PLL_DISABLE;
9367 I915_WRITE(LCPLL_CTL, val);
9368
9369 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9370 DRM_ERROR("LCPLL not locked yet\n");
9371
9372 if (val & LCPLL_CD_SOURCE_FCLK) {
9373 val = I915_READ(LCPLL_CTL);
9374 val &= ~LCPLL_CD_SOURCE_FCLK;
9375 I915_WRITE(LCPLL_CTL, val);
9376
9377 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9378 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9379 DRM_ERROR("Switching back to LCPLL failed\n");
9380 }
215733fa 9381
59bad947 9382 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9383 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ
9384}
9385
765dab67
PZ
9386/*
9387 * Package states C8 and deeper are really deep PC states that can only be
9388 * reached when all the devices on the system allow it, so even if the graphics
9389 * device allows PC8+, it doesn't mean the system will actually get to these
9390 * states. Our driver only allows PC8+ when going into runtime PM.
9391 *
9392 * The requirements for PC8+ are that all the outputs are disabled, the power
9393 * well is disabled and most interrupts are disabled, and these are also
9394 * requirements for runtime PM. When these conditions are met, we manually do
9395 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9396 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9397 * hang the machine.
9398 *
9399 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9400 * the state of some registers, so when we come back from PC8+ we need to
9401 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9402 * need to take care of the registers kept by RC6. Notice that this happens even
9403 * if we don't put the device in PCI D3 state (which is what currently happens
9404 * because of the runtime PM support).
9405 *
9406 * For more, read "Display Sequences for Package C8" on the hardware
9407 * documentation.
9408 */
a14cb6fc 9409void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9410{
c67a470b
PZ
9411 struct drm_device *dev = dev_priv->dev;
9412 uint32_t val;
9413
c67a470b
PZ
9414 DRM_DEBUG_KMS("Enabling package C8+\n");
9415
c67a470b
PZ
9416 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9417 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9418 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9419 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9420 }
9421
9422 lpt_disable_clkout_dp(dev);
c67a470b
PZ
9423 hsw_disable_lcpll(dev_priv, true, true);
9424}
9425
a14cb6fc 9426void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ
9427{
9428 struct drm_device *dev = dev_priv->dev;
9429 uint32_t val;
9430
c67a470b
PZ
9431 DRM_DEBUG_KMS("Disabling package C8+\n");
9432
9433 hsw_restore_lcpll(dev_priv);
c67a470b
PZ
9434 lpt_init_pch_refclk(dev);
9435
9436 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9437 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9438 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9439 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9440 }
9441
9442 intel_prepare_ddi(dev);
c67a470b
PZ
9443}
9444
27c329ed 9445static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9446{
a821fc46 9447 struct drm_device *dev = old_state->dev;
27c329ed 9448 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9449
27c329ed 9450 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK
9451}
9452
b432e5cf 9453/* compute the max rate for new configuration */
27c329ed 9454static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9455{
b432e5cf 9456 struct intel_crtc *intel_crtc;
27c329ed 9457 struct intel_crtc_state *crtc_state;
b432e5cf 9458 int max_pixel_rate = 0;
b432e5cf 9459
27c329ed
ML
9460 for_each_intel_crtc(state->dev, intel_crtc) {
9461 int pixel_rate;
9462
9463 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9464 if (IS_ERR(crtc_state))
9465 return PTR_ERR(crtc_state);
9466
9467 if (!crtc_state->base.enable)
b432e5cf
VS
9468 continue;
9469
27c329ed 9470 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS
9471
9472 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9473 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS
9474 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9475
9476 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9477 }
9478
9479 return max_pixel_rate;
9480}
9481
9482static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9483{
9484 struct drm_i915_private *dev_priv = dev->dev_private;
9485 uint32_t val, data;
9486 int ret;
9487
9488 if (WARN((I915_READ(LCPLL_CTL) &
9489 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9490 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9491 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9492 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9493 "trying to change cdclk frequency with cdclk not enabled\n"))
9494 return;
9495
9496 mutex_lock(&dev_priv->rps.hw_lock);
9497 ret = sandybridge_pcode_write(dev_priv,
9498 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9499 mutex_unlock(&dev_priv->rps.hw_lock);
9500 if (ret) {
9501 DRM_ERROR("failed to inform pcode about cdclk change\n");
9502 return;
9503 }
9504
9505 val = I915_READ(LCPLL_CTL);
9506 val |= LCPLL_CD_SOURCE_FCLK;
9507 I915_WRITE(LCPLL_CTL, val);
9508
9509 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9510 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9511 DRM_ERROR("Switching to FCLK failed\n");
9512
9513 val = I915_READ(LCPLL_CTL);
9514 val &= ~LCPLL_CLK_FREQ_MASK;
9515
9516 switch (cdclk) {
9517 case 450000:
9518 val |= LCPLL_CLK_FREQ_450;
9519 data = 0;
9520 break;
9521 case 540000:
9522 val |= LCPLL_CLK_FREQ_54O_BDW;
9523 data = 1;
9524 break;
9525 case 337500:
9526 val |= LCPLL_CLK_FREQ_337_5_BDW;
9527 data = 2;
9528 break;
9529 case 675000:
9530 val |= LCPLL_CLK_FREQ_675_BDW;
9531 data = 3;
9532 break;
9533 default:
9534 WARN(1, "invalid cdclk frequency\n");
9535 return;
9536 }
9537
9538 I915_WRITE(LCPLL_CTL, val);
9539
9540 val = I915_READ(LCPLL_CTL);
9541 val &= ~LCPLL_CD_SOURCE_FCLK;
9542 I915_WRITE(LCPLL_CTL, val);
9543
9544 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9545 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9546 DRM_ERROR("Switching back to LCPLL failed\n");
9547
9548 mutex_lock(&dev_priv->rps.hw_lock);
9549 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9550 mutex_unlock(&dev_priv->rps.hw_lock);
9551
9552 intel_update_cdclk(dev);
9553
9554 WARN(cdclk != dev_priv->cdclk_freq,
9555 "cdclk requested %d kHz but got %d kHz\n",
9556 cdclk, dev_priv->cdclk_freq);
9557}
9558
27c329ed 9559static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9560{
27c329ed
ML
9561 struct drm_i915_private *dev_priv = to_i915(state->dev);
9562 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS
9563 int cdclk;
9564
9565 /*
9566 * FIXME should also account for plane ratio
9567 * once 64bpp pixel formats are supported.
9568 */
27c329ed 9569 if (max_pixclk > 540000)
b432e5cf 9570 cdclk = 675000;
27c329ed 9571 else if (max_pixclk > 450000)
b432e5cf 9572 cdclk = 540000;
27c329ed 9573 else if (max_pixclk > 337500)
b432e5cf
VS
9574 cdclk = 450000;
9575 else
9576 cdclk = 337500;
9577
9578 /*
9579 * FIXME move the cdclk caclulation to
9580 * compute_config() so we can fail gracegully.
9581 */
9582 if (cdclk > dev_priv->max_cdclk_freq) {
9583 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9584 cdclk, dev_priv->max_cdclk_freq);
9585 cdclk = dev_priv->max_cdclk_freq;
9586 }
9587
27c329ed 9588 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS
9589
9590 return 0;
9591}
9592
27c329ed 9593static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9594{
27c329ed
ML
9595 struct drm_device *dev = old_state->dev;
9596 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9597
27c329ed 9598 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS
9599}
9600
190f68c5
ACO
9601static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9602 struct intel_crtc_state *crtc_state)
09b4ddf9 9603{
190f68c5 9604 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9605 return -EINVAL;
716c2e55 9606
c7653199 9607 crtc->lowfreq_avail = false;
644cef34 9608
c8f7a0db 9609 return 0;
79e53945
JB
9610}
9611
3760b59c
S
9612static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9613 enum port port,
9614 struct intel_crtc_state *pipe_config)
9615{
9616 switch (port) {
9617 case PORT_A:
9618 pipe_config->ddi_pll_sel = SKL_DPLL0;
9619 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9620 break;
9621 case PORT_B:
9622 pipe_config->ddi_pll_sel = SKL_DPLL1;
9623 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9624 break;
9625 case PORT_C:
9626 pipe_config->ddi_pll_sel = SKL_DPLL2;
9627 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9628 break;
9629 default:
9630 DRM_ERROR("Incorrect port type\n");
9631 }
9632}
9633
96b7dfb7
S
9634static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9635 enum port port,
5cec258b 9636 struct intel_crtc_state *pipe_config)
96b7dfb7 9637{
3148ade7 9638 u32 temp, dpll_ctl1;
96b7dfb7
S
9639
9640 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9641 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9642
9643 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL
9644 case SKL_DPLL0:
9645 /*
9646 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9647 * of the shared DPLL framework and thus needs to be read out
9648 * separately
9649 */
9650 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9651 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9652 break;
96b7dfb7
S
9653 case SKL_DPLL1:
9654 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9655 break;
9656 case SKL_DPLL2:
9657 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9658 break;
9659 case SKL_DPLL3:
9660 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9661 break;
96b7dfb7
S
9662 }
9663}
9664
7d2c8175
DL
9665static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9666 enum port port,
5cec258b 9667 struct intel_crtc_state *pipe_config)
7d2c8175
DL
9668{
9669 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9670
9671 switch (pipe_config->ddi_pll_sel) {
9672 case PORT_CLK_SEL_WRPLL1:
9673 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9674 break;
9675 case PORT_CLK_SEL_WRPLL2:
9676 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9677 break;
9678 }
9679}
9680
26804afd 9681static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9682 struct intel_crtc_state *pipe_config)
26804afd
DV
9683{
9684 struct drm_device *dev = crtc->base.dev;
9685 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9686 struct intel_shared_dpll *pll;
26804afd
DV
9687 enum port port;
9688 uint32_t tmp;
9689
9690 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9691
9692 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9693
96b7dfb7
S
9694 if (IS_SKYLAKE(dev))
9695 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S
9696 else if (IS_BROXTON(dev))
9697 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S
9698 else
9699 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9700
d452c5b6
DV
9701 if (pipe_config->shared_dpll >= 0) {
9702 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9703
9704 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9705 &pipe_config->dpll_hw_state));
9706 }
9707
26804afd
DV
9708 /*
9709 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9710 * DDI E. So just check whether this pipe is wired to DDI E and whether
9711 * the PCH transcoder is on.
9712 */
ca370455
DL
9713 if (INTEL_INFO(dev)->gen < 9 &&
9714 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV
9715 pipe_config->has_pch_encoder = true;
9716
9717 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9718 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9719 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9720
9721 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9722 }
9723}
9724
0e8ffe1b 9725static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9726 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
9727{
9728 struct drm_device *dev = crtc->base.dev;
9729 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9730 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV
9731 uint32_t tmp;
9732
f458ebbc 9733 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID
9734 POWER_DOMAIN_PIPE(crtc->pipe)))
9735 return false;
9736
e143a21c 9737 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV
9738 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9739
eccb140b
DV
9740 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9741 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9742 enum pipe trans_edp_pipe;
9743 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9744 default:
9745 WARN(1, "unknown pipe linked to edp transcoder\n");
9746 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9747 case TRANS_DDI_EDP_INPUT_A_ON:
9748 trans_edp_pipe = PIPE_A;
9749 break;
9750 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9751 trans_edp_pipe = PIPE_B;
9752 break;
9753 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9754 trans_edp_pipe = PIPE_C;
9755 break;
9756 }
9757
9758 if (trans_edp_pipe == crtc->pipe)
9759 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9760 }
9761
f458ebbc 9762 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9763 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ
9764 return false;
9765
eccb140b 9766 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV
9767 if (!(tmp & PIPECONF_ENABLE))
9768 return false;
9769
26804afd 9770 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9771
1bd1bd80
DV
9772 intel_get_pipe_timings(crtc, pipe_config);
9773
a1b2278e
CK
9774 if (INTEL_INFO(dev)->gen >= 9) {
9775 skl_init_scalers(dev, crtc, pipe_config);
9776 }
9777
2fa2fe9a 9778 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK
9779
9780 if (INTEL_INFO(dev)->gen >= 9) {
9781 pipe_config->scaler_state.scaler_id = -1;
9782 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9783 }
9784
bd2e244f 9785 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9786 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9787 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9788 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9789 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB
9790 else
9791 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9792 }
88adfff1 9793
e59150dc
JB
9794 if (IS_HASWELL(dev))
9795 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9796 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9797
ebb69c95
CT
9798 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9799 pipe_config->pixel_multiplier =
9800 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9801 } else {
9802 pipe_config->pixel_multiplier = 1;
9803 }
6c49f241 9804
0e8ffe1b
DV
9805 return true;
9806}
9807
560b85bb
CW
9808static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9809{
9810 struct drm_device *dev = crtc->dev;
9811 struct drm_i915_private *dev_priv = dev->dev_private;
9812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9813 uint32_t cntl = 0, size = 0;
560b85bb 9814
dc41c154 9815 if (base) {
3dd512fb
MR
9816 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9817 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS
9818 unsigned int stride = roundup_pow_of_two(width) * 4;
9819
9820 switch (stride) {
9821 default:
9822 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9823 width, stride);
9824 stride = 256;
9825 /* fallthrough */
9826 case 256:
9827 case 512:
9828 case 1024:
9829 case 2048:
9830 break;
4b0e333e
CW
9831 }
9832
dc41c154
VS
9833 cntl |= CURSOR_ENABLE |
9834 CURSOR_GAMMA_ENABLE |
9835 CURSOR_FORMAT_ARGB |
9836 CURSOR_STRIDE(stride);
9837
9838 size = (height << 12) | width;
4b0e333e 9839 }
560b85bb 9840
dc41c154
VS
9841 if (intel_crtc->cursor_cntl != 0 &&
9842 (intel_crtc->cursor_base != base ||
9843 intel_crtc->cursor_size != size ||
9844 intel_crtc->cursor_cntl != cntl)) {
9845 /* On these chipsets we can only modify the base/size/stride
9846 * whilst the cursor is disabled.
9847 */
9848 I915_WRITE(_CURACNTR, 0);
4b0e333e 9849 POSTING_READ(_CURACNTR);
dc41c154 9850 intel_crtc->cursor_cntl = 0;
4b0e333e 9851 }
560b85bb 9852
99d1f387 9853 if (intel_crtc->cursor_base != base) {
9db4a9c7 9854 I915_WRITE(_CURABASE, base);
99d1f387
VS
9855 intel_crtc->cursor_base = base;
9856 }
4726e0b0 9857
dc41c154
VS
9858 if (intel_crtc->cursor_size != size) {
9859 I915_WRITE(CURSIZE, size);
9860 intel_crtc->cursor_size = size;
4b0e333e 9861 }
560b85bb 9862
4b0e333e 9863 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW
9864 I915_WRITE(_CURACNTR, cntl);
9865 POSTING_READ(_CURACNTR);
4b0e333e 9866 intel_crtc->cursor_cntl = cntl;
560b85bb 9867 }
560b85bb
CW
9868}
9869
560b85bb 9870static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB
9871{
9872 struct drm_device *dev = crtc->dev;
9873 struct drm_i915_private *dev_priv = dev->dev_private;
9874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9875 int pipe = intel_crtc->pipe;
4b0e333e
CW
9876 uint32_t cntl;
9877
9878 cntl = 0;
9879 if (base) {
9880 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9881 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK
9882 case 64:
9883 cntl |= CURSOR_MODE_64_ARGB_AX;
9884 break;
9885 case 128:
9886 cntl |= CURSOR_MODE_128_ARGB_AX;
9887 break;
9888 case 256:
9889 cntl |= CURSOR_MODE_256_ARGB_AX;
9890 break;
9891 default:
3dd512fb 9892 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9893 return;
65a21cd6 9894 }
4b0e333e 9895 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS
9896
9897 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9898 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9899 }
65a21cd6 9900
8e7d688b 9901 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS
9902 cntl |= CURSOR_ROTATE_180;
9903
4b0e333e
CW
9904 if (intel_crtc->cursor_cntl != cntl) {
9905 I915_WRITE(CURCNTR(pipe), cntl);
9906 POSTING_READ(CURCNTR(pipe));
9907 intel_crtc->cursor_cntl = cntl;
65a21cd6 9908 }
4b0e333e 9909
65a21cd6 9910 /* and commit changes on next vblank */
5efb3e28
VS
9911 I915_WRITE(CURBASE(pipe), base);
9912 POSTING_READ(CURBASE(pipe));
99d1f387
VS
9913
9914 intel_crtc->cursor_base = base;
65a21cd6
JB
9915}
9916
cda4b7d3 9917/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW
9918static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9919 bool on)
cda4b7d3
CW
9920{
9921 struct drm_device *dev = crtc->dev;
9922 struct drm_i915_private *dev_priv = dev->dev_private;
9923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9924 int pipe = intel_crtc->pipe;
3d7d6510
MR
9925 int x = crtc->cursor_x;
9926 int y = crtc->cursor_y;
d6e4db15 9927 u32 base = 0, pos = 0;
cda4b7d3 9928
d6e4db15 9929 if (on)
cda4b7d3 9930 base = intel_crtc->cursor_addr;
cda4b7d3 9931
6e3c9717 9932 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS
9933 base = 0;
9934
6e3c9717 9935 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW
9936 base = 0;
9937
9938 if (x < 0) {
3dd512fb 9939 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW
9940 base = 0;
9941
9942 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9943 x = -x;
9944 }
9945 pos |= x << CURSOR_X_SHIFT;
9946
9947 if (y < 0) {
3dd512fb 9948 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW
9949 base = 0;
9950
9951 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9952 y = -y;
9953 }
9954 pos |= y << CURSOR_Y_SHIFT;
9955
4b0e333e 9956 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW
9957 return;
9958
5efb3e28
VS
9959 I915_WRITE(CURPOS(pipe), pos);
9960
4398ad45
VS
9961 /* ILK+ do this automagically */
9962 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9963 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR
9964 base += (intel_crtc->base.cursor->state->crtc_h *
9965 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS
9966 }
9967
8ac54669 9968 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS
9969 i845_update_cursor(crtc, base);
9970 else
9971 i9xx_update_cursor(crtc, base);
cda4b7d3
CW
9972}
9973
dc41c154
VS
9974static bool cursor_size_ok(struct drm_device *dev,
9975 uint32_t width, uint32_t height)
9976{
9977 if (width == 0 || height == 0)
9978 return false;
9979
9980 /*
9981 * 845g/865g are special in that they are only limited by
9982 * the width of their cursors, the height is arbitrary up to
9983 * the precision of the register. Everything else requires
9984 * square cursors, limited to a few power-of-two sizes.
9985 */
9986 if (IS_845G(dev) || IS_I865G(dev)) {
9987 if ((width & 63) != 0)
9988 return false;
9989
9990 if (width > (IS_845G(dev) ? 64 : 512))
9991 return false;
9992
9993 if (height > 1023)
9994 return false;
9995 } else {
9996 switch (width | height) {
9997 case 256:
9998 case 128:
9999 if (IS_GEN2(dev))
10000 return false;
10001 case 64:
10002 break;
10003 default:
10004 return false;
10005 }
10006 }
10007
10008 return true;
10009}
10010
79e53945 10011static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10012 u16 *blue, uint32_t start, uint32_t size)
79e53945 10013{
7203425a 10014 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10016
7203425a 10017 for (i = start; i < end; i++) {
79e53945
JB
10018 intel_crtc->lut_r[i] = red[i] >> 8;
10019 intel_crtc->lut_g[i] = green[i] >> 8;
10020 intel_crtc->lut_b[i] = blue[i] >> 8;
10021 }
10022
10023 intel_crtc_load_lut(crtc);
10024}
10025
79e53945
JB
10026/* VESA 640x480x72Hz mode to set on the pipe */
10027static struct drm_display_mode load_detect_mode = {
10028 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10029 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10030};
10031
a8bb6818
DV
10032struct drm_framebuffer *
10033__intel_framebuffer_create(struct drm_device *dev,
10034 struct drm_mode_fb_cmd2 *mode_cmd,
10035 struct drm_i915_gem_object *obj)
d2dff872
CW
10036{
10037 struct intel_framebuffer *intel_fb;
10038 int ret;
10039
10040 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10041 if (!intel_fb) {
6ccb81f2 10042 drm_gem_object_unreference(&obj->base);
d2dff872
CW
10043 return ERR_PTR(-ENOMEM);
10044 }
10045
10046 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV
10047 if (ret)
10048 goto err;
d2dff872
CW
10049
10050 return &intel_fb->base;
dd4916c5 10051err:
6ccb81f2 10052 drm_gem_object_unreference(&obj->base);
dd4916c5
DV
10053 kfree(intel_fb);
10054
10055 return ERR_PTR(ret);
d2dff872
CW
10056}
10057
b5ea642a 10058static struct drm_framebuffer *
a8bb6818
DV
10059intel_framebuffer_create(struct drm_device *dev,
10060 struct drm_mode_fb_cmd2 *mode_cmd,
10061 struct drm_i915_gem_object *obj)
10062{
10063 struct drm_framebuffer *fb;
10064 int ret;
10065
10066 ret = i915_mutex_lock_interruptible(dev);
10067 if (ret)
10068 return ERR_PTR(ret);
10069 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10070 mutex_unlock(&dev->struct_mutex);
10071
10072 return fb;
10073}
10074
d2dff872
CW
10075static u32
10076intel_framebuffer_pitch_for_width(int width, int bpp)
10077{
10078 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10079 return ALIGN(pitch, 64);
10080}
10081
10082static u32
10083intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10084{
10085 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10086 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW
10087}
10088
10089static struct drm_framebuffer *
10090intel_framebuffer_create_for_mode(struct drm_device *dev,
10091 struct drm_display_mode *mode,
10092 int depth, int bpp)
10093{
10094 struct drm_i915_gem_object *obj;
0fed39bd 10095 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW
10096
10097 obj = i915_gem_alloc_object(dev,
10098 intel_framebuffer_size_for_mode(mode, bpp));
10099 if (obj == NULL)
10100 return ERR_PTR(-ENOMEM);
10101
10102 mode_cmd.width = mode->hdisplay;
10103 mode_cmd.height = mode->vdisplay;
308e5bcb
JB
10104 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10105 bpp);
5ca0c34a 10106 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW
10107
10108 return intel_framebuffer_create(dev, &mode_cmd, obj);
10109}
10110
10111static struct drm_framebuffer *
10112mode_fits_in_fbdev(struct drm_device *dev,
10113 struct drm_display_mode *mode)
10114{
0695726e 10115#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW
10116 struct drm_i915_private *dev_priv = dev->dev_private;
10117 struct drm_i915_gem_object *obj;
10118 struct drm_framebuffer *fb;
10119
4c0e5528 10120 if (!dev_priv->fbdev)
d2dff872
CW
10121 return NULL;
10122
4c0e5528 10123 if (!dev_priv->fbdev->fb)
d2dff872
CW
10124 return NULL;
10125
4c0e5528
DV
10126 obj = dev_priv->fbdev->fb->obj;
10127 BUG_ON(!obj);
10128
8bcd4553 10129 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS
10130 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10131 fb->bits_per_pixel))
d2dff872
CW
10132 return NULL;
10133
01f2c773 10134 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW
10135 return NULL;
10136
10137 return fb;
4520f53a
DV
10138#else
10139 return NULL;
10140#endif
d2dff872
CW
10141}
10142
d3a40d1b
ACO
10143static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10144 struct drm_crtc *crtc,
10145 struct drm_display_mode *mode,
10146 struct drm_framebuffer *fb,
10147 int x, int y)
10148{
10149 struct drm_plane_state *plane_state;
10150 int hdisplay, vdisplay;
10151 int ret;
10152
10153 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10154 if (IS_ERR(plane_state))
10155 return PTR_ERR(plane_state);
10156
10157 if (mode)
10158 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10159 else
10160 hdisplay = vdisplay = 0;
10161
10162 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10163 if (ret)
10164 return ret;
10165 drm_atomic_set_fb_for_plane(plane_state, fb);
10166 plane_state->crtc_x = 0;
10167 plane_state->crtc_y = 0;
10168 plane_state->crtc_w = hdisplay;
10169 plane_state->crtc_h = vdisplay;
10170 plane_state->src_x = x << 16;
10171 plane_state->src_y = y << 16;
10172 plane_state->src_w = hdisplay << 16;
10173 plane_state->src_h = vdisplay << 16;
10174
10175 return 0;
10176}
10177
d2434ab7 10178bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10179 struct drm_display_mode *mode,
51fd371b
RC
10180 struct intel_load_detect_pipe *old,
10181 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB
10182{
10183 struct intel_crtc *intel_crtc;
d2434ab7
DV
10184 struct intel_encoder *intel_encoder =
10185 intel_attached_encoder(connector);
79e53945 10186 struct drm_crtc *possible_crtc;
4ef69c7a 10187 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
10188 struct drm_crtc *crtc = NULL;
10189 struct drm_device *dev = encoder->dev;
94352cf9 10190 struct drm_framebuffer *fb;
51fd371b 10191 struct drm_mode_config *config = &dev->mode_config;
83a57153 10192 struct drm_atomic_state *state = NULL;
944b0c76 10193 struct drm_connector_state *connector_state;
4be07317 10194 struct intel_crtc_state *crtc_state;
51fd371b 10195 int ret, i = -1;
79e53945 10196
d2dff872 10197 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10198 connector->base.id, connector->name,
8e329a03 10199 encoder->base.id, encoder->name);
d2dff872 10200
51fd371b
RC
10201retry:
10202 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10203 if (ret)
ad3c558f 10204 goto fail;
6e9f798d 10205
79e53945
JB
10206 /*
10207 * Algorithm gets a little messy:
7a5e4805 10208 *
79e53945
JB
10209 * - if the connector already has an assigned crtc, use it (but make
10210 * sure it's on first)
7a5e4805 10211 *
79e53945
JB
10212 * - try to find the first unused crtc that can drive this connector,
10213 * and use that if we find one
79e53945
JB
10214 */
10215
10216 /* See if we already have a CRTC for this connector */
10217 if (encoder->crtc) {
10218 crtc = encoder->crtc;
8261b191 10219
51fd371b 10220 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10221 if (ret)
ad3c558f 10222 goto fail;
4d02e2de 10223 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10224 if (ret)
ad3c558f 10225 goto fail;
7b24056b 10226
24218aac 10227 old->dpms_mode = connector->dpms;
8261b191
CW
10228 old->load_detect_temp = false;
10229
10230 /* Make sure the crtc and connector are running */
24218aac
DV
10231 if (connector->dpms != DRM_MODE_DPMS_ON)
10232 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10233
7173188d 10234 return true;
79e53945
JB
10235 }
10236
10237 /* Find an unused one (if possible) */
70e1e0ec 10238 for_each_crtc(dev, possible_crtc) {
79e53945
JB
10239 i++;
10240 if (!(encoder->possible_crtcs & (1 << i)))
10241 continue;
83d65738 10242 if (possible_crtc->state->enable)
a459249c 10243 continue;
a459249c
VS
10244
10245 crtc = possible_crtc;
10246 break;
79e53945
JB
10247 }
10248
10249 /*
10250 * If we didn't find an unused CRTC, don't use any.
10251 */
10252 if (!crtc) {
7173188d 10253 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10254 goto fail;
79e53945
JB
10255 }
10256
51fd371b
RC
10257 ret = drm_modeset_lock(&crtc->mutex, ctx);
10258 if (ret)
ad3c558f 10259 goto fail;
4d02e2de
DV
10260 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10261 if (ret)
ad3c558f 10262 goto fail;
79e53945
JB
10263
10264 intel_crtc = to_intel_crtc(crtc);
24218aac 10265 old->dpms_mode = connector->dpms;
8261b191 10266 old->load_detect_temp = true;
d2dff872 10267 old->release_fb = NULL;
79e53945 10268
83a57153
ACO
10269 state = drm_atomic_state_alloc(dev);
10270 if (!state)
10271 return false;
10272
10273 state->acquire_ctx = ctx;
10274
944b0c76
ACO
10275 connector_state = drm_atomic_get_connector_state(state, connector);
10276 if (IS_ERR(connector_state)) {
10277 ret = PTR_ERR(connector_state);
10278 goto fail;
10279 }
10280
10281 connector_state->crtc = crtc;
10282 connector_state->best_encoder = &intel_encoder->base;
10283
4be07317
ACO
10284 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10285 if (IS_ERR(crtc_state)) {
10286 ret = PTR_ERR(crtc_state);
10287 goto fail;
10288 }
10289
49d6fa21 10290 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10291
6492711d
CW
10292 if (!mode)
10293 mode = &load_detect_mode;
79e53945 10294
d2dff872
CW
10295 /* We need a framebuffer large enough to accommodate all accesses
10296 * that the plane may generate whilst we perform load detection.
10297 * We can not rely on the fbcon either being present (we get called
10298 * during its initialisation to detect all boot displays, or it may
10299 * not even exist) or that it is large enough to satisfy the
10300 * requested mode.
10301 */
94352cf9
DV
10302 fb = mode_fits_in_fbdev(dev, mode);
10303 if (fb == NULL) {
d2dff872 10304 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV
10305 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10306 old->release_fb = fb;
d2dff872
CW
10307 } else
10308 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10309 if (IS_ERR(fb)) {
d2dff872 10310 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10311 goto fail;
79e53945 10312 }
79e53945 10313
d3a40d1b
ACO
10314 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10315 if (ret)
10316 goto fail;
10317
8c7b5ccb
ACO
10318 drm_mode_copy(&crtc_state->base.mode, mode);
10319
74c090b1 10320 if (drm_atomic_commit(state)) {
6492711d 10321 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW
10322 if (old->release_fb)
10323 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10324 goto fail;
79e53945 10325 }
9128b040 10326 crtc->primary->crtc = crtc;
7173188d 10327
79e53945 10328 /* let the connector get through one full cycle before testing */
9d0498a2 10329 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10330 return true;
412b61d8 10331
ad3c558f 10332fail:
e5d958ef
ACO
10333 drm_atomic_state_free(state);
10334 state = NULL;
83a57153 10335
51fd371b
RC
10336 if (ret == -EDEADLK) {
10337 drm_modeset_backoff(ctx);
10338 goto retry;
10339 }
10340
412b61d8 10341 return false;
79e53945
JB
10342}
10343
d2434ab7 10344void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO
10345 struct intel_load_detect_pipe *old,
10346 struct drm_modeset_acquire_ctx *ctx)
79e53945 10347{
83a57153 10348 struct drm_device *dev = connector->dev;
d2434ab7
DV
10349 struct intel_encoder *intel_encoder =
10350 intel_attached_encoder(connector);
4ef69c7a 10351 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10352 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10354 struct drm_atomic_state *state;
944b0c76 10355 struct drm_connector_state *connector_state;
4be07317 10356 struct intel_crtc_state *crtc_state;
d3a40d1b 10357 int ret;
79e53945 10358
d2dff872 10359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10360 connector->base.id, connector->name,
8e329a03 10361 encoder->base.id, encoder->name);
d2dff872 10362
8261b191 10363 if (old->load_detect_temp) {
83a57153 10364 state = drm_atomic_state_alloc(dev);
944b0c76
ACO
10365 if (!state)
10366 goto fail;
83a57153
ACO
10367
10368 state->acquire_ctx = ctx;
10369
944b0c76
ACO
10370 connector_state = drm_atomic_get_connector_state(state, connector);
10371 if (IS_ERR(connector_state))
10372 goto fail;
10373
4be07317
ACO
10374 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10375 if (IS_ERR(crtc_state))
10376 goto fail;
10377
944b0c76
ACO
10378 connector_state->best_encoder = NULL;
10379 connector_state->crtc = NULL;
10380
49d6fa21 10381 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10382
d3a40d1b
ACO
10383 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10384 0, 0);
10385 if (ret)
10386 goto fail;
10387
74c090b1 10388 ret = drm_atomic_commit(state);
2bfb4627
ACO
10389 if (ret)
10390 goto fail;
d2dff872 10391
36206361
DV
10392 if (old->release_fb) {
10393 drm_framebuffer_unregister_private(old->release_fb);
10394 drm_framebuffer_unreference(old->release_fb);
10395 }
d2dff872 10396
0622a53c 10397 return;
79e53945
JB
10398 }
10399
c751ce4f 10400 /* Switch crtc and encoder back off if necessary */
24218aac
DV
10401 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10402 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO
10403
10404 return;
10405fail:
10406 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10407 drm_atomic_state_free(state);
79e53945
JB
10408}
10409
da4a1efa 10410static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10411 const struct intel_crtc_state *pipe_config)
da4a1efa
VS
10412{
10413 struct drm_i915_private *dev_priv = dev->dev_private;
10414 u32 dpll = pipe_config->dpll_hw_state.dpll;
10415
10416 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10417 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS
10418 else if (HAS_PCH_SPLIT(dev))
10419 return 120000;
10420 else if (!IS_GEN2(dev))
10421 return 96000;
10422 else
10423 return 48000;
10424}
10425
79e53945 10426/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10427static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10428 struct intel_crtc_state *pipe_config)
79e53945 10429{
f1f644dc 10430 struct drm_device *dev = crtc->base.dev;
79e53945 10431 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10432 int pipe = pipe_config->cpu_transcoder;
293623f7 10433 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB
10434 u32 fp;
10435 intel_clock_t clock;
dccbea3b 10436 int port_clock;
da4a1efa 10437 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB
10438
10439 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10440 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10441 else
293623f7 10442 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB
10443
10444 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ
10445 if (IS_PINEVIEW(dev)) {
10446 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10447 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL
10448 } else {
10449 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10450 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10451 }
10452
a6c45cf0 10453 if (!IS_GEN2(dev)) {
f2b115e6
AJ
10454 if (IS_PINEVIEW(dev))
10455 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10456 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL
10457 else
10458 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB
10459 DPLL_FPA01_P1_POST_DIV_SHIFT);
10460
10461 switch (dpll & DPLL_MODE_MASK) {
10462 case DPLLB_MODE_DAC_SERIAL:
10463 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10464 5 : 10;
10465 break;
10466 case DPLLB_MODE_LVDS:
10467 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10468 7 : 14;
10469 break;
10470 default:
28c97730 10471 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10472 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10473 return;
79e53945
JB
10474 }
10475
ac58c3f0 10476 if (IS_PINEVIEW(dev))
dccbea3b 10477 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10478 else
dccbea3b 10479 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10480 } else {
0fb58223 10481 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10482 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB
10483
10484 if (is_lvds) {
10485 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10486 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS
10487
10488 if (lvds & LVDS_CLKB_POWER_UP)
10489 clock.p2 = 7;
10490 else
10491 clock.p2 = 14;
79e53945
JB
10492 } else {
10493 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10494 clock.p1 = 2;
10495 else {
10496 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10497 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10498 }
10499 if (dpll & PLL_P2_DIVIDE_BY_4)
10500 clock.p2 = 4;
10501 else
10502 clock.p2 = 2;
79e53945 10503 }
da4a1efa 10504
dccbea3b 10505 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB
10506 }
10507
18442d08
VS
10508 /*
10509 * This value includes pixel_multiplier. We will use
241bfc38 10510 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS
10511 * encoder's get_config() function.
10512 */
dccbea3b 10513 pipe_config->port_clock = port_clock;
f1f644dc
JB
10514}
10515
6878da05
VS
10516int intel_dotclock_calculate(int link_freq,
10517 const struct intel_link_m_n *m_n)
f1f644dc 10518{
f1f644dc
JB
10519 /*
10520 * The calculation for the data clock is:
1041a02f 10521 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10522 * But we want to avoid losing precison if possible, so:
1041a02f 10523 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB
10524 *
10525 * and the link clock is simpler:
1041a02f 10526 * link_clock = (m * link_clock) / n
f1f644dc
JB
10527 */
10528
6878da05
VS
10529 if (!m_n->link_n)
10530 return 0;
f1f644dc 10531
6878da05
VS
10532 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10533}
f1f644dc 10534
18442d08 10535static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10536 struct intel_crtc_state *pipe_config)
6878da05
VS
10537{
10538 struct drm_device *dev = crtc->base.dev;
79e53945 10539
18442d08
VS
10540 /* read out port_clock from the DPLL */
10541 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10542
f1f644dc 10543 /*
18442d08 10544 * This value does not include pixel_multiplier.
241bfc38 10545 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS
10546 * agree once we know their relationship in the encoder's
10547 * get_config() function.
79e53945 10548 */
2d112de7 10549 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS
10550 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10551 &pipe_config->fdi_m_n);
79e53945
JB
10552}
10553
10554/** Returns the currently programmed mode of the given pipe. */
10555struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10556 struct drm_crtc *crtc)
10557{
548f245b 10558 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10560 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10561 struct drm_display_mode *mode;
5cec258b 10562 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ
10563 int htot = I915_READ(HTOTAL(cpu_transcoder));
10564 int hsync = I915_READ(HSYNC(cpu_transcoder));
10565 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10566 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10567 enum pipe pipe = intel_crtc->pipe;
79e53945
JB
10568
10569 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10570 if (!mode)
10571 return NULL;
10572
f1f644dc
JB
10573 /*
10574 * Construct a pipe_config sufficient for getting the clock info
10575 * back out of crtc_clock_get.
10576 *
10577 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10578 * to use a real value here instead.
10579 */
293623f7 10580 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10581 pipe_config.pixel_multiplier = 1;
293623f7
VS
10582 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10583 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10584 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB
10585 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10586
773ae034 10587 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB
10588 mode->hdisplay = (htot & 0xffff) + 1;
10589 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10590 mode->hsync_start = (hsync & 0xffff) + 1;
10591 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10592 mode->vdisplay = (vtot & 0xffff) + 1;
10593 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10594 mode->vsync_start = (vsync & 0xffff) + 1;
10595 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10596
10597 drm_mode_set_name(mode);
79e53945
JB
10598
10599 return mode;
10600}
10601
f047e395
CW
10602void intel_mark_busy(struct drm_device *dev)
10603{
c67a470b
PZ
10604 struct drm_i915_private *dev_priv = dev->dev_private;
10605
f62a0076
CW
10606 if (dev_priv->mm.busy)
10607 return;
10608
43694d69 10609 intel_runtime_pm_get(dev_priv);
c67a470b 10610 i915_update_gfx_val(dev_priv);
43cf3bf0
CW
10611 if (INTEL_INFO(dev)->gen >= 6)
10612 gen6_rps_busy(dev_priv);
f62a0076 10613 dev_priv->mm.busy = true;
f047e395
CW
10614}
10615
10616void intel_mark_idle(struct drm_device *dev)
652c393a 10617{
c67a470b 10618 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10619
f62a0076
CW
10620 if (!dev_priv->mm.busy)
10621 return;
10622
10623 dev_priv->mm.busy = false;
10624
3d13ef2e 10625 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10626 gen6_rps_idle(dev->dev_private);
bb4cdd53 10627
43694d69 10628 intel_runtime_pm_put(dev_priv);
652c393a
JB
10629}
10630
79e53945
JB
10631static void intel_crtc_destroy(struct drm_crtc *crtc)
10632{
10633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV
10634 struct drm_device *dev = crtc->dev;
10635 struct intel_unpin_work *work;
67e77c5a 10636
5e2d7afc 10637 spin_lock_irq(&dev->event_lock);
67e77c5a
DV
10638 work = intel_crtc->unpin_work;
10639 intel_crtc->unpin_work = NULL;
5e2d7afc 10640 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV
10641
10642 if (work) {
10643 cancel_work_sync(&work->work);
10644 kfree(work);
10645 }
79e53945
JB
10646
10647 drm_crtc_cleanup(crtc);
67e77c5a 10648
79e53945
JB
10649 kfree(intel_crtc);
10650}
10651
6b95a207
KH
10652static void intel_unpin_work_fn(struct work_struct *__work)
10653{
10654 struct intel_unpin_work *work =
10655 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS
10656 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10657 struct drm_device *dev = crtc->base.dev;
10658 struct drm_plane *primary = crtc->base.primary;
6b95a207 10659
b4a98e57 10660 mutex_lock(&dev->struct_mutex);
a9ff8714 10661 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10662 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10663
f06cc1b9 10664 if (work->flip_queued_req)
146d84f0 10665 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW
10666 mutex_unlock(&dev->struct_mutex);
10667
a9ff8714 10668 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10669 drm_framebuffer_unreference(work->old_fb);
f99d7069 10670
a9ff8714
VS
10671 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10672 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10673
6b95a207
KH
10674 kfree(work);
10675}
10676
1afe3e9d 10677static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10678 struct drm_crtc *crtc)
6b95a207 10679{
6b95a207
KH
10680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10681 struct intel_unpin_work *work;
6b95a207
KH
10682 unsigned long flags;
10683
10684 /* Ignore early vblank irqs */
10685 if (intel_crtc == NULL)
10686 return;
10687
f326038a
DV
10688 /*
10689 * This is called both by irq handlers and the reset code (to complete
10690 * lost pageflips) so needs the full irqsave spinlocks.
10691 */
6b95a207
KH
10692 spin_lock_irqsave(&dev->event_lock, flags);
10693 work = intel_crtc->unpin_work;
e7d841ca
CW
10694
10695 /* Ensure we don't miss a work->pending update ... */
10696 smp_rmb();
10697
10698 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH
10699 spin_unlock_irqrestore(&dev->event_lock, flags);
10700 return;
10701 }
10702
d6bbafa1 10703 page_flip_completed(intel_crtc);
0af7e4df 10704
6b95a207 10705 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH
10706}
10707
1afe3e9d
JB
10708void intel_finish_page_flip(struct drm_device *dev, int pipe)
10709{
fbee40df 10710 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB
10711 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10712
49b14a5c 10713 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB
10714}
10715
10716void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10717{
fbee40df 10718 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB
10719 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10720
49b14a5c 10721 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB
10722}
10723
75f7f3ec
VS
10724/* Is 'a' after or equal to 'b'? */
10725static bool g4x_flip_count_after_eq(u32 a, u32 b)
10726{
10727 return !((a - b) & 0x80000000);
10728}
10729
10730static bool page_flip_finished(struct intel_crtc *crtc)
10731{
10732 struct drm_device *dev = crtc->base.dev;
10733 struct drm_i915_private *dev_priv = dev->dev_private;
10734
bdfa7542
VS
10735 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10736 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10737 return true;
10738
75f7f3ec
VS
10739 /*
10740 * The relevant registers doen't exist on pre-ctg.
10741 * As the flip done interrupt doesn't trigger for mmio
10742 * flips on gmch platforms, a flip count check isn't
10743 * really needed there. But since ctg has the registers,
10744 * include it in the check anyway.
10745 */
10746 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10747 return true;
10748
10749 /*
10750 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10751 * used the same base address. In that case the mmio flip might
10752 * have completed, but the CS hasn't even executed the flip yet.
10753 *
10754 * A flip count check isn't enough as the CS might have updated
10755 * the base address just after start of vblank, but before we
10756 * managed to process the interrupt. This means we'd complete the
10757 * CS flip too soon.
10758 *
10759 * Combining both checks should get us a good enough result. It may
10760 * still happen that the CS flip has been executed, but has not
10761 * yet actually completed. But in case the base address is the same
10762 * anyway, we don't really care.
10763 */
10764 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10765 crtc->unpin_work->gtt_offset &&
10766 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10767 crtc->unpin_work->flip_count);
10768}
10769
6b95a207
KH
10770void intel_prepare_page_flip(struct drm_device *dev, int plane)
10771{
fbee40df 10772 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH
10773 struct intel_crtc *intel_crtc =
10774 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10775 unsigned long flags;
10776
f326038a
DV
10777
10778 /*
10779 * This is called both by irq handlers and the reset code (to complete
10780 * lost pageflips) so needs the full irqsave spinlocks.
10781 *
10782 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW
10783 * generate a page-flip completion irq, i.e. every modeset
10784 * is also accompanied by a spurious intel_prepare_page_flip().
10785 */
6b95a207 10786 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10787 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10788 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH
10789 spin_unlock_irqrestore(&dev->event_lock, flags);
10790}
10791
eba905b2 10792static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW
10793{
10794 /* Ensure that the work item is consistent when activating it ... */
10795 smp_wmb();
10796 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10797 /* and that it is marked active as soon as the irq could fire. */
10798 smp_wmb();
10799}
10800
8c9f3aaf
JB
10801static int intel_gen2_queue_flip(struct drm_device *dev,
10802 struct drm_crtc *crtc,
10803 struct drm_framebuffer *fb,
ed8d1975 10804 struct drm_i915_gem_object *obj,
6258fbe2 10805 struct drm_i915_gem_request *req,
ed8d1975 10806 uint32_t flags)
8c9f3aaf 10807{
6258fbe2 10808 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB
10810 u32 flip_mask;
10811 int ret;
10812
5fb9de1a 10813 ret = intel_ring_begin(req, 6);
8c9f3aaf 10814 if (ret)
4fa62c89 10815 return ret;
8c9f3aaf
JB
10816
10817 /* Can't queue multiple flips, so wait for the previous
10818 * one to finish before executing the next.
10819 */
10820 if (intel_crtc->plane)
10821 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10822 else
10823 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV
10824 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10825 intel_ring_emit(ring, MI_NOOP);
10826 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10827 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10828 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10829 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10830 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW
10831
10832 intel_mark_page_flip_active(intel_crtc);
83d4092b 10833 return 0;
8c9f3aaf
JB
10834}
10835
10836static int intel_gen3_queue_flip(struct drm_device *dev,
10837 struct drm_crtc *crtc,
10838 struct drm_framebuffer *fb,
ed8d1975 10839 struct drm_i915_gem_object *obj,
6258fbe2 10840 struct drm_i915_gem_request *req,
ed8d1975 10841 uint32_t flags)
8c9f3aaf 10842{
6258fbe2 10843 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB
10845 u32 flip_mask;
10846 int ret;
10847
5fb9de1a 10848 ret = intel_ring_begin(req, 6);
8c9f3aaf 10849 if (ret)
4fa62c89 10850 return ret;
8c9f3aaf
JB
10851
10852 if (intel_crtc->plane)
10853 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10854 else
10855 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV
10856 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10857 intel_ring_emit(ring, MI_NOOP);
10858 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10859 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10860 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10861 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV
10862 intel_ring_emit(ring, MI_NOOP);
10863
e7d841ca 10864 intel_mark_page_flip_active(intel_crtc);
83d4092b 10865 return 0;
8c9f3aaf
JB
10866}
10867
10868static int intel_gen4_queue_flip(struct drm_device *dev,
10869 struct drm_crtc *crtc,
10870 struct drm_framebuffer *fb,
ed8d1975 10871 struct drm_i915_gem_object *obj,
6258fbe2 10872 struct drm_i915_gem_request *req,
ed8d1975 10873 uint32_t flags)
8c9f3aaf 10874{
6258fbe2 10875 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB
10876 struct drm_i915_private *dev_priv = dev->dev_private;
10877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10878 uint32_t pf, pipesrc;
10879 int ret;
10880
5fb9de1a 10881 ret = intel_ring_begin(req, 4);
8c9f3aaf 10882 if (ret)
4fa62c89 10883 return ret;
8c9f3aaf
JB
10884
10885 /* i965+ uses the linear or tiled offsets from the
10886 * Display Registers (which do not change across a page-flip)
10887 * so we need only reprogram the base address.
10888 */
6d90c952
DV
10889 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10890 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10891 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10892 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10893 obj->tiling_mode);
8c9f3aaf
JB
10894
10895 /* XXX Enabling the panel-fitter across page-flip is so far
10896 * untested on non-native modes, so ignore it for now.
10897 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10898 */
10899 pf = 0;
10900 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10901 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW
10902
10903 intel_mark_page_flip_active(intel_crtc);
83d4092b 10904 return 0;
8c9f3aaf
JB
10905}
10906
10907static int intel_gen6_queue_flip(struct drm_device *dev,
10908 struct drm_crtc *crtc,
10909 struct drm_framebuffer *fb,
ed8d1975 10910 struct drm_i915_gem_object *obj,
6258fbe2 10911 struct drm_i915_gem_request *req,
ed8d1975 10912 uint32_t flags)
8c9f3aaf 10913{
6258fbe2 10914 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10917 uint32_t pf, pipesrc;
10918 int ret;
10919
5fb9de1a 10920 ret = intel_ring_begin(req, 4);
8c9f3aaf 10921 if (ret)
4fa62c89 10922 return ret;
8c9f3aaf 10923
6d90c952
DV
10924 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10925 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10926 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10927 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10928
dc257cf1
DV
10929 /* Contrary to the suggestions in the documentation,
10930 * "Enable Panel Fitter" does not seem to be required when page
10931 * flipping with a non-native mode, and worse causes a normal
10932 * modeset to fail.
10933 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10934 */
10935 pf = 0;
8c9f3aaf 10936 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10937 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW
10938
10939 intel_mark_page_flip_active(intel_crtc);
83d4092b 10940 return 0;
8c9f3aaf
JB
10941}
10942
7c9017e5
JB
10943static int intel_gen7_queue_flip(struct drm_device *dev,
10944 struct drm_crtc *crtc,
10945 struct drm_framebuffer *fb,
ed8d1975 10946 struct drm_i915_gem_object *obj,
6258fbe2 10947 struct drm_i915_gem_request *req,
ed8d1975 10948 uint32_t flags)
7c9017e5 10949{
6258fbe2 10950 struct intel_engine_cs *ring = req->ring;
7c9017e5 10951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10952 uint32_t plane_bit = 0;
ffe74d75
CW
10953 int len, ret;
10954
eba905b2 10955 switch (intel_crtc->plane) {
cb05d8de
DV
10956 case PLANE_A:
10957 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10958 break;
10959 case PLANE_B:
10960 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10961 break;
10962 case PLANE_C:
10963 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10964 break;
10965 default:
10966 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10967 return -ENODEV;
cb05d8de
DV
10968 }
10969
ffe74d75 10970 len = 4;
f476828a 10971 if (ring->id == RCS) {
ffe74d75 10972 len += 6;
f476828a
DL
10973 /*
10974 * On Gen 8, SRM is now taking an extra dword to accommodate
10975 * 48bits addresses, and we need a NOOP for the batch size to
10976 * stay even.
10977 */
10978 if (IS_GEN8(dev))
10979 len += 2;
10980 }
ffe74d75 10981
f66fab8e
VS
10982 /*
10983 * BSpec MI_DISPLAY_FLIP for IVB:
10984 * "The full packet must be contained within the same cache line."
10985 *
10986 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10987 * cacheline, if we ever start emitting more commands before
10988 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10989 * then do the cacheline alignment, and finally emit the
10990 * MI_DISPLAY_FLIP.
10991 */
bba09b12 10992 ret = intel_ring_cacheline_align(req);
f66fab8e 10993 if (ret)
4fa62c89 10994 return ret;
f66fab8e 10995
5fb9de1a 10996 ret = intel_ring_begin(req, len);
7c9017e5 10997 if (ret)
4fa62c89 10998 return ret;
7c9017e5 10999
ffe74d75
CW
11000 /* Unmask the flip-done completion message. Note that the bspec says that
11001 * we should do this for both the BCS and RCS, and that we must not unmask
11002 * more than one flip event at any time (or ensure that one flip message
11003 * can be sent by waiting for flip-done prior to queueing new flips).
11004 * Experimentation says that BCS works despite DERRMR masking all
11005 * flip-done completion events and that unmasking all planes at once
11006 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11007 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11008 */
11009 if (ring->id == RCS) {
11010 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11011 intel_ring_emit(ring, DERRMR);
11012 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11013 DERRMR_PIPEB_PRI_FLIP_DONE |
11014 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11015 if (IS_GEN8(dev))
f1afe24f 11016 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL
11017 MI_SRM_LRM_GLOBAL_GTT);
11018 else
f1afe24f 11019 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11020 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW
11021 intel_ring_emit(ring, DERRMR);
11022 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL
11023 if (IS_GEN8(dev)) {
11024 intel_ring_emit(ring, 0);
11025 intel_ring_emit(ring, MI_NOOP);
11026 }
ffe74d75
CW
11027 }
11028
cb05d8de 11029 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11030 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11031 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11032 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW
11033
11034 intel_mark_page_flip_active(intel_crtc);
83d4092b 11035 return 0;
7c9017e5
JB
11036}
11037
84c33a64
SG
11038static bool use_mmio_flip(struct intel_engine_cs *ring,
11039 struct drm_i915_gem_object *obj)
11040{
11041 /*
11042 * This is not being used for older platforms, because
11043 * non-availability of flip done interrupt forces us to use
11044 * CS flips. Older platforms derive flip done using some clever
11045 * tricks involving the flip_pending status bits and vblank irqs.
11046 * So using MMIO flips there would disrupt this mechanism.
11047 */
11048
8e09bf83
CW
11049 if (ring == NULL)
11050 return true;
11051
84c33a64
SG
11052 if (INTEL_INFO(ring->dev)->gen < 5)
11053 return false;
11054
11055 if (i915.use_mmio_flip < 0)
11056 return false;
11057 else if (i915.use_mmio_flip > 0)
11058 return true;
14bf993e
OM
11059 else if (i915.enable_execlists)
11060 return true;
84c33a64 11061 else
b4716185 11062 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG
11063}
11064
ff944564
DL
11065static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11066{
11067 struct drm_device *dev = intel_crtc->base.dev;
11068 struct drm_i915_private *dev_priv = dev->dev_private;
11069 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL
11070 const enum pipe pipe = intel_crtc->pipe;
11071 u32 ctl, stride;
11072
11073 ctl = I915_READ(PLANE_CTL(pipe, 0));
11074 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU
11075 switch (fb->modifier[0]) {
11076 case DRM_FORMAT_MOD_NONE:
11077 break;
11078 case I915_FORMAT_MOD_X_TILED:
ff944564 11079 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU
11080 break;
11081 case I915_FORMAT_MOD_Y_TILED:
11082 ctl |= PLANE_CTL_TILED_Y;
11083 break;
11084 case I915_FORMAT_MOD_Yf_TILED:
11085 ctl |= PLANE_CTL_TILED_YF;
11086 break;
11087 default:
11088 MISSING_CASE(fb->modifier[0]);
11089 }
ff944564
DL
11090
11091 /*
11092 * The stride is either expressed as a multiple of 64 bytes chunks for
11093 * linear buffers or in number of tiles for tiled buffers.
11094 */
2ebef630
TU
11095 stride = fb->pitches[0] /
11096 intel_fb_stride_alignment(dev, fb->modifier[0],
11097 fb->pixel_format);
ff944564
DL
11098
11099 /*
11100 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11101 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11102 */
11103 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11105
11106 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11107 POSTING_READ(PLANE_SURF(pipe, 0));
11108}
11109
11110static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG
11111{
11112 struct drm_device *dev = intel_crtc->base.dev;
11113 struct drm_i915_private *dev_priv = dev->dev_private;
11114 struct intel_framebuffer *intel_fb =
11115 to_intel_framebuffer(intel_crtc->base.primary->fb);
11116 struct drm_i915_gem_object *obj = intel_fb->obj;
11117 u32 dspcntr;
11118 u32 reg;
11119
84c33a64
SG
11120 reg = DSPCNTR(intel_crtc->plane);
11121 dspcntr = I915_READ(reg);
11122
c5d97472
DL
11123 if (obj->tiling_mode != I915_TILING_NONE)
11124 dspcntr |= DISPPLANE_TILED;
11125 else
11126 dspcntr &= ~DISPPLANE_TILED;
11127
84c33a64
SG
11128 I915_WRITE(reg, dspcntr);
11129
11130 I915_WRITE(DSPSURF(intel_crtc->plane),
11131 intel_crtc->unpin_work->gtt_offset);
11132 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11133
ff944564
DL
11134}
11135
11136/*
11137 * XXX: This is the temporary way to update the plane registers until we get
11138 * around to using the usual plane update functions for MMIO flips
11139 */
11140static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11141{
11142 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL
11143
11144 intel_mark_page_flip_active(intel_crtc);
11145
34e0adbb 11146 intel_pipe_update_start(intel_crtc);
ff944564
DL
11147
11148 if (INTEL_INFO(dev)->gen >= 9)
11149 skl_do_mmio_flip(intel_crtc);
11150 else
11151 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11152 ilk_do_mmio_flip(intel_crtc);
11153
34e0adbb 11154 intel_pipe_update_end(intel_crtc);
84c33a64
SG
11155}
11156
9362c7c5 11157static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11158{
b2cfe0ab
CW
11159 struct intel_mmio_flip *mmio_flip =
11160 container_of(work, struct intel_mmio_flip, work);
84c33a64 11161
eed29a5b
DV
11162 if (mmio_flip->req)
11163 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11164 mmio_flip->crtc->reset_counter,
bcafc4e3
CW
11165 false, NULL,
11166 &mmio_flip->i915->rps.mmioflips));
84c33a64 11167
b2cfe0ab
CW
11168 intel_do_mmio_flip(mmio_flip->crtc);
11169
eed29a5b 11170 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11171 kfree(mmio_flip);
84c33a64
SG
11172}
11173
11174static int intel_queue_mmio_flip(struct drm_device *dev,
11175 struct drm_crtc *crtc,
11176 struct drm_framebuffer *fb,
11177 struct drm_i915_gem_object *obj,
11178 struct intel_engine_cs *ring,
11179 uint32_t flags)
11180{
b2cfe0ab
CW
11181 struct intel_mmio_flip *mmio_flip;
11182
11183 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11184 if (mmio_flip == NULL)
11185 return -ENOMEM;
84c33a64 11186
bcafc4e3 11187 mmio_flip->i915 = to_i915(dev);
eed29a5b 11188 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11189 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11190
b2cfe0ab
CW
11191 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11192 schedule_work(&mmio_flip->work);
84c33a64 11193
84c33a64
SG
11194 return 0;
11195}
11196
8c9f3aaf
JB
11197static int intel_default_queue_flip(struct drm_device *dev,
11198 struct drm_crtc *crtc,
11199 struct drm_framebuffer *fb,
ed8d1975 11200 struct drm_i915_gem_object *obj,
6258fbe2 11201 struct drm_i915_gem_request *req,
ed8d1975 11202 uint32_t flags)
8c9f3aaf
JB
11203{
11204 return -ENODEV;
11205}
11206
d6bbafa1
CW
11207static bool __intel_pageflip_stall_check(struct drm_device *dev,
11208 struct drm_crtc *crtc)
11209{
11210 struct drm_i915_private *dev_priv = dev->dev_private;
11211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11212 struct intel_unpin_work *work = intel_crtc->unpin_work;
11213 u32 addr;
11214
11215 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11216 return true;
11217
908565c2
CW
11218 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11219 return false;
11220
d6bbafa1
CW
11221 if (!work->enable_stall_check)
11222 return false;
11223
11224 if (work->flip_ready_vblank == 0) {
3a8a946e
DV
11225 if (work->flip_queued_req &&
11226 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW
11227 return false;
11228
1e3feefd 11229 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW
11230 }
11231
1e3feefd 11232 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW
11233 return false;
11234
11235 /* Potential stall - if we see that the flip has happened,
11236 * assume a missed interrupt. */
11237 if (INTEL_INFO(dev)->gen >= 4)
11238 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11239 else
11240 addr = I915_READ(DSPADDR(intel_crtc->plane));
11241
11242 /* There is a potential issue here with a false positive after a flip
11243 * to the same address. We could address this by checking for a
11244 * non-incrementing frame counter.
11245 */
11246 return addr == work->gtt_offset;
11247}
11248
11249void intel_check_page_flip(struct drm_device *dev, int pipe)
11250{
11251 struct drm_i915_private *dev_priv = dev->dev_private;
11252 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11254 struct intel_unpin_work *work;
f326038a 11255
6c51d46f 11256 WARN_ON(!in_interrupt());
d6bbafa1
CW
11257
11258 if (crtc == NULL)
11259 return;
11260
f326038a 11261 spin_lock(&dev->event_lock);
6ad790c0
CW
11262 work = intel_crtc->unpin_work;
11263 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11264 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11265 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11266 page_flip_completed(intel_crtc);
6ad790c0 11267 work = NULL;
d6bbafa1 11268 }
6ad790c0
CW
11269 if (work != NULL &&
11270 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11271 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11272 spin_unlock(&dev->event_lock);
d6bbafa1
CW
11273}
11274
6b95a207
KH
11275static int intel_crtc_page_flip(struct drm_crtc *crtc,
11276 struct drm_framebuffer *fb,
ed8d1975
KP
11277 struct drm_pending_vblank_event *event,
11278 uint32_t page_flip_flags)
6b95a207
KH
11279{
11280 struct drm_device *dev = crtc->dev;
11281 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11282 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11283 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11285 struct drm_plane *primary = crtc->primary;
a071fa00 11286 enum pipe pipe = intel_crtc->pipe;
6b95a207 11287 struct intel_unpin_work *work;
a4872ba6 11288 struct intel_engine_cs *ring;
cf5d8a46 11289 bool mmio_flip;
91af127f 11290 struct drm_i915_gem_request *request = NULL;
52e68630 11291 int ret;
6b95a207 11292
2ff8fde1
MR
11293 /*
11294 * drm_mode_page_flip_ioctl() should already catch this, but double
11295 * check to be safe. In the future we may enable pageflipping from
11296 * a disabled primary plane.
11297 */
11298 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11299 return -EBUSY;
11300
e6a595d2 11301 /* Can't change pixel format via MI display flips. */
f4510a27 11302 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS
11303 return -EINVAL;
11304
11305 /*
11306 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11307 * Note that pitch changes could also affect these register.
11308 */
11309 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR
11310 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11311 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS
11312 return -EINVAL;
11313
f900db47
CW
11314 if (i915_terminally_wedged(&dev_priv->gpu_error))
11315 goto out_hang;
11316
b14c5679 11317 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH
11318 if (work == NULL)
11319 return -ENOMEM;
11320
6b95a207 11321 work->event = event;
b4a98e57 11322 work->crtc = crtc;
ab8d6675 11323 work->old_fb = old_fb;
6b95a207
KH
11324 INIT_WORK(&work->work, intel_unpin_work_fn);
11325
87b6b101 11326 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB
11327 if (ret)
11328 goto free_work;
11329
6b95a207 11330 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11331 spin_lock_irq(&dev->event_lock);
6b95a207 11332 if (intel_crtc->unpin_work) {
d6bbafa1
CW
11333 /* Before declaring the flip queue wedged, check if
11334 * the hardware completed the operation behind our backs.
11335 */
11336 if (__intel_pageflip_stall_check(dev, crtc)) {
11337 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11338 page_flip_completed(intel_crtc);
11339 } else {
11340 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11341 spin_unlock_irq(&dev->event_lock);
468f0b44 11342
d6bbafa1
CW
11343 drm_crtc_vblank_put(crtc);
11344 kfree(work);
11345 return -EBUSY;
11346 }
6b95a207
KH
11347 }
11348 intel_crtc->unpin_work = work;
5e2d7afc 11349 spin_unlock_irq(&dev->event_lock);
6b95a207 11350
b4a98e57
CW
11351 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11352 flush_workqueue(dev_priv->wq);
11353
75dfca80 11354 /* Reference the objects for the scheduled work. */
ab8d6675 11355 drm_framebuffer_reference(work->old_fb);
05394f39 11356 drm_gem_object_reference(&obj->base);
6b95a207 11357
f4510a27 11358 crtc->primary->fb = fb;
afd65eb4 11359 update_state_fb(crtc->primary);
1ed1f968 11360
e1f99ce6 11361 work->pending_flip_obj = obj;
e1f99ce6 11362
89ed88ba
CW
11363 ret = i915_mutex_lock_interruptible(dev);
11364 if (ret)
11365 goto cleanup;
11366
b4a98e57 11367 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11368 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11369
75f7f3ec 11370 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11371 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11372
4fa62c89
VS
11373 if (IS_VALLEYVIEW(dev)) {
11374 ring = &dev_priv->ring[BCS];
ab8d6675 11375 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW
11376 /* vlv: DISPLAY_FLIP fails to change tiling */
11377 ring = NULL;
48bf5b2d 11378 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11379 ring = &dev_priv->ring[BCS];
4fa62c89 11380 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11381 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS
11382 if (ring == NULL || ring->id != RCS)
11383 ring = &dev_priv->ring[BCS];
11384 } else {
11385 ring = &dev_priv->ring[RCS];
11386 }
11387
cf5d8a46
CW
11388 mmio_flip = use_mmio_flip(ring, obj);
11389
11390 /* When using CS flips, we want to emit semaphores between rings.
11391 * However, when using mmio flips we will create a task to do the
11392 * synchronisation, so all we want here is to pin the framebuffer
11393 * into the display plane and skip any waits.
11394 */
82bc3b2d 11395 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11396 crtc->primary->state,
91af127f 11397 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB
11398 if (ret)
11399 goto cleanup_pending;
6b95a207 11400
121920fa
TU
11401 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11402 + intel_crtc->dspaddr_offset;
4fa62c89 11403
cf5d8a46 11404 if (mmio_flip) {
84c33a64
SG
11405 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11406 page_flip_flags);
d6bbafa1
CW
11407 if (ret)
11408 goto cleanup_unpin;
11409
f06cc1b9
JH
11410 i915_gem_request_assign(&work->flip_queued_req,
11411 obj->last_write_req);
d6bbafa1 11412 } else {
6258fbe2
JH
11413 if (!request) {
11414 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11415 if (ret)
11416 goto cleanup_unpin;
11417 }
11418
11419 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW
11420 page_flip_flags);
11421 if (ret)
11422 goto cleanup_unpin;
11423
6258fbe2 11424 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW
11425 }
11426
91af127f 11427 if (request)
75289874 11428 i915_add_request_no_flush(request);
91af127f 11429
1e3feefd 11430 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11431 work->enable_stall_check = true;
4fa62c89 11432
ab8d6675 11433 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11434 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11435 mutex_unlock(&dev->struct_mutex);
a071fa00 11436
4e1e26f1 11437 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS
11438 intel_frontbuffer_flip_prepare(dev,
11439 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11440
e5510fac
JB
11441 trace_i915_flip_request(intel_crtc->plane, obj);
11442
6b95a207 11443 return 0;
96b099fd 11444
4fa62c89 11445cleanup_unpin:
82bc3b2d 11446 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11447cleanup_pending:
91af127f
JH
11448 if (request)
11449 i915_gem_request_cancel(request);
b4a98e57 11450 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW
11451 mutex_unlock(&dev->struct_mutex);
11452cleanup:
f4510a27 11453 crtc->primary->fb = old_fb;
afd65eb4 11454 update_state_fb(crtc->primary);
89ed88ba
CW
11455
11456 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11457 drm_framebuffer_unreference(work->old_fb);
96b099fd 11458
5e2d7afc 11459 spin_lock_irq(&dev->event_lock);
96b099fd 11460 intel_crtc->unpin_work = NULL;
5e2d7afc 11461 spin_unlock_irq(&dev->event_lock);
96b099fd 11462
87b6b101 11463 drm_crtc_vblank_put(crtc);
7317c75e 11464free_work:
96b099fd
CW
11465 kfree(work);
11466
f900db47 11467 if (ret == -EIO) {
02e0efb5
ML
11468 struct drm_atomic_state *state;
11469 struct drm_plane_state *plane_state;
11470
f900db47 11471out_hang:
02e0efb5
ML
11472 state = drm_atomic_state_alloc(dev);
11473 if (!state)
11474 return -ENOMEM;
11475 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11476
11477retry:
11478 plane_state = drm_atomic_get_plane_state(state, primary);
11479 ret = PTR_ERR_OR_ZERO(plane_state);
11480 if (!ret) {
11481 drm_atomic_set_fb_for_plane(plane_state, fb);
11482
11483 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11484 if (!ret)
11485 ret = drm_atomic_commit(state);
11486 }
11487
11488 if (ret == -EDEADLK) {
11489 drm_modeset_backoff(state->acquire_ctx);
11490 drm_atomic_state_clear(state);
11491 goto retry;
11492 }
11493
11494 if (ret)
11495 drm_atomic_state_free(state);
11496
f0d3dad3 11497 if (ret == 0 && event) {
5e2d7afc 11498 spin_lock_irq(&dev->event_lock);
a071fa00 11499 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11500 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11501 }
f900db47 11502 }
96b099fd 11503 return ret;
6b95a207
KH
11504}
11505
da20eabd
ML
11506
11507/**
11508 * intel_wm_need_update - Check whether watermarks need updating
11509 * @plane: drm plane
11510 * @state: new plane state
11511 *
11512 * Check current plane state versus the new one to determine whether
11513 * watermarks need to be recalculated.
11514 *
11515 * Returns true or false.
11516 */
11517static bool intel_wm_need_update(struct drm_plane *plane,
11518 struct drm_plane_state *state)
11519{
11520 /* Update watermarks on tiling changes. */
11521 if (!plane->state->fb || !state->fb ||
11522 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11523 plane->state->rotation != state->rotation)
11524 return true;
11525
11526 if (plane->state->crtc_w != state->crtc_w)
11527 return true;
11528
11529 return false;
11530}
11531
11532int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11533 struct drm_plane_state *plane_state)
11534{
11535 struct drm_crtc *crtc = crtc_state->crtc;
11536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11537 struct drm_plane *plane = plane_state->plane;
11538 struct drm_device *dev = crtc->dev;
11539 struct drm_i915_private *dev_priv = dev->dev_private;
11540 struct intel_plane_state *old_plane_state =
11541 to_intel_plane_state(plane->state);
11542 int idx = intel_crtc->base.base.id, ret;
11543 int i = drm_plane_index(plane);
11544 bool mode_changed = needs_modeset(crtc_state);
11545 bool was_crtc_enabled = crtc->state->active;
11546 bool is_crtc_enabled = crtc_state->active;
11547
11548 bool turn_off, turn_on, visible, was_visible;
11549 struct drm_framebuffer *fb = plane_state->fb;
11550
11551 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11552 plane->type != DRM_PLANE_TYPE_CURSOR) {
11553 ret = skl_update_scaler_plane(
11554 to_intel_crtc_state(crtc_state),
11555 to_intel_plane_state(plane_state));
11556 if (ret)
11557 return ret;
11558 }
11559
11560 /*
11561 * Disabling a plane is always okay; we just need to update
11562 * fb tracking in a special way since cleanup_fb() won't
11563 * get called by the plane helpers.
11564 */
11565 if (old_plane_state->base.fb && !fb)
11566 intel_crtc->atomic.disabled_planes |= 1 << i;
11567
da20eabd
ML
11568 was_visible = old_plane_state->visible;
11569 visible = to_intel_plane_state(plane_state)->visible;
11570
11571 if (!was_crtc_enabled && WARN_ON(was_visible))
11572 was_visible = false;
11573
11574 if (!is_crtc_enabled && WARN_ON(visible))
11575 visible = false;
11576
11577 if (!was_visible && !visible)
11578 return 0;
11579
11580 turn_off = was_visible && (!visible || mode_changed);
11581 turn_on = visible && (!was_visible || mode_changed);
11582
11583 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11584 plane->base.id, fb ? fb->base.id : -1);
11585
11586 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11587 plane->base.id, was_visible, visible,
11588 turn_off, turn_on, mode_changed);
11589
852eb00d 11590 if (turn_on) {
f015c551 11591 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS
11592 /* must disable cxsr around plane enable/disable */
11593 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11594 intel_crtc->atomic.disable_cxsr = true;
11595 /* to potentially re-enable cxsr */
11596 intel_crtc->atomic.wait_vblank = true;
11597 intel_crtc->atomic.update_wm_post = true;
11598 }
11599 } else if (turn_off) {
f015c551 11600 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS
11601 /* must disable cxsr around plane enable/disable */
11602 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11603 if (is_crtc_enabled)
11604 intel_crtc->atomic.wait_vblank = true;
11605 intel_crtc->atomic.disable_cxsr = true;
11606 }
11607 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11608 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11609 }
da20eabd 11610
8be6ca85 11611 if (visible || was_visible)
a9ff8714
VS
11612 intel_crtc->atomic.fb_bits |=
11613 to_intel_plane(plane)->frontbuffer_bit;
11614
da20eabd
ML
11615 switch (plane->type) {
11616 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML
11617 intel_crtc->atomic.wait_for_flips = true;
11618 intel_crtc->atomic.pre_disable_primary = turn_off;
11619 intel_crtc->atomic.post_enable_primary = turn_on;
11620
066cf55b
RV
11621 if (turn_off) {
11622 /*
11623 * FIXME: Actually if we will still have any other
11624 * plane enabled on the pipe we could let IPS enabled
11625 * still, but for now lets consider that when we make
11626 * primary invisible by setting DSPCNTR to 0 on
11627 * update_primary_plane function IPS needs to be
11628 * disable.
11629 */
11630 intel_crtc->atomic.disable_ips = true;
11631
da20eabd 11632 intel_crtc->atomic.disable_fbc = true;
066cf55b 11633 }
da20eabd
ML
11634
11635 /*
11636 * FBC does not work on some platforms for rotated
11637 * planes, so disable it when rotation is not 0 and
11638 * update it when rotation is set back to 0.
11639 *
11640 * FIXME: This is redundant with the fbc update done in
11641 * the primary plane enable function except that that
11642 * one is done too late. We eventually need to unify
11643 * this.
11644 */
11645
11646 if (visible &&
11647 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11648 dev_priv->fbc.crtc == intel_crtc &&
11649 plane_state->rotation != BIT(DRM_ROTATE_0))
11650 intel_crtc->atomic.disable_fbc = true;
11651
11652 /*
11653 * BDW signals flip done immediately if the plane
11654 * is disabled, even if the plane enable is already
11655 * armed to occur at the next vblank :(
11656 */
11657 if (turn_on && IS_BROADWELL(dev))
11658 intel_crtc->atomic.wait_vblank = true;
11659
11660 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11661 break;
11662 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML
11663 break;
11664 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11665 if (turn_off && !mode_changed) {
da20eabd
ML
11666 intel_crtc->atomic.wait_vblank = true;
11667 intel_crtc->atomic.update_sprite_watermarks |=
11668 1 << i;
11669 }
da20eabd
ML
11670 }
11671 return 0;
11672}
11673
6d3a1ce7
ML
11674static bool encoders_cloneable(const struct intel_encoder *a,
11675 const struct intel_encoder *b)
11676{
11677 /* masks could be asymmetric, so check both ways */
11678 return a == b || (a->cloneable & (1 << b->type) &&
11679 b->cloneable & (1 << a->type));
11680}
11681
11682static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11683 struct intel_crtc *crtc,
11684 struct intel_encoder *encoder)
11685{
11686 struct intel_encoder *source_encoder;
11687 struct drm_connector *connector;
11688 struct drm_connector_state *connector_state;
11689 int i;
11690
11691 for_each_connector_in_state(state, connector, connector_state, i) {
11692 if (connector_state->crtc != &crtc->base)
11693 continue;
11694
11695 source_encoder =
11696 to_intel_encoder(connector_state->best_encoder);
11697 if (!encoders_cloneable(encoder, source_encoder))
11698 return false;
11699 }
11700
11701 return true;
11702}
11703
11704static bool check_encoder_cloning(struct drm_atomic_state *state,
11705 struct intel_crtc *crtc)
11706{
11707 struct intel_encoder *encoder;
11708 struct drm_connector *connector;
11709 struct drm_connector_state *connector_state;
11710 int i;
11711
11712 for_each_connector_in_state(state, connector, connector_state, i) {
11713 if (connector_state->crtc != &crtc->base)
11714 continue;
11715
11716 encoder = to_intel_encoder(connector_state->best_encoder);
11717 if (!check_single_encoder_cloning(state, crtc, encoder))
11718 return false;
11719 }
11720
11721 return true;
11722}
11723
11724static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11725 struct drm_crtc_state *crtc_state)
11726{
cf5a15be 11727 struct drm_device *dev = crtc->dev;
ad421372 11728 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML
11730 struct intel_crtc_state *pipe_config =
11731 to_intel_crtc_state(crtc_state);
6d3a1ce7 11732 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11733 int ret;
6d3a1ce7
ML
11734 bool mode_changed = needs_modeset(crtc_state);
11735
11736 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11737 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11738 return -EINVAL;
11739 }
11740
852eb00d
VS
11741 if (mode_changed && !crtc_state->active)
11742 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11743
ad421372
ML
11744 if (mode_changed && crtc_state->enable &&
11745 dev_priv->display.crtc_compute_clock &&
11746 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11747 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11748 pipe_config);
11749 if (ret)
11750 return ret;
11751 }
11752
e435d6e5
ML
11753 ret = 0;
11754 if (INTEL_INFO(dev)->gen >= 9) {
11755 if (mode_changed)
11756 ret = skl_update_scaler_crtc(pipe_config);
11757
11758 if (!ret)
11759 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11760 pipe_config);
11761 }
11762
11763 return ret;
6d3a1ce7
ML
11764}
11765
65b38e0d 11766static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW
11767 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11768 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR
11769 .atomic_begin = intel_begin_crtc_commit,
11770 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11771 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW
11772};
11773
d29b2f9d
ACO
11774static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11775{
11776 struct intel_connector *connector;
11777
11778 for_each_intel_connector(dev, connector) {
11779 if (connector->base.encoder) {
11780 connector->base.state->best_encoder =
11781 connector->base.encoder;
11782 connector->base.state->crtc =
11783 connector->base.encoder->crtc;
11784 } else {
11785 connector->base.state->best_encoder = NULL;
11786 connector->base.state->crtc = NULL;
11787 }
11788 }
11789}
11790
050f7aeb 11791static void
eba905b2 11792connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11793 struct intel_crtc_state *pipe_config)
050f7aeb
DV
11794{
11795 int bpp = pipe_config->pipe_bpp;
11796
11797 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11798 connector->base.base.id,
c23cc417 11799 connector->base.name);
050f7aeb
DV
11800
11801 /* Don't use an invalid EDID bpc value */
11802 if (connector->base.display_info.bpc &&
11803 connector->base.display_info.bpc * 3 < bpp) {
11804 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11805 bpp, connector->base.display_info.bpc*3);
11806 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11807 }
11808
11809 /* Clamp bpp to 8 on screens without EDID 1.4 */
11810 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11811 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11812 bpp);
11813 pipe_config->pipe_bpp = 24;
11814 }
11815}
11816
4e53c2e0 11817static int
050f7aeb 11818compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11819 struct intel_crtc_state *pipe_config)
4e53c2e0 11820{
050f7aeb 11821 struct drm_device *dev = crtc->base.dev;
1486017f 11822 struct drm_atomic_state *state;
da3ced29
ACO
11823 struct drm_connector *connector;
11824 struct drm_connector_state *connector_state;
1486017f 11825 int bpp, i;
4e53c2e0 11826
d328c9d7 11827 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11828 bpp = 10*3;
d328c9d7
DV
11829 else if (INTEL_INFO(dev)->gen >= 5)
11830 bpp = 12*3;
11831 else
11832 bpp = 8*3;
11833
4e53c2e0 11834
4e53c2e0
DV
11835 pipe_config->pipe_bpp = bpp;
11836
1486017f
ACO
11837 state = pipe_config->base.state;
11838
4e53c2e0 11839 /* Clamp display bpp to EDID value */
da3ced29
ACO
11840 for_each_connector_in_state(state, connector, connector_state, i) {
11841 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV
11842 continue;
11843
da3ced29
ACO
11844 connected_sink_compute_bpp(to_intel_connector(connector),
11845 pipe_config);
4e53c2e0
DV
11846 }
11847
11848 return bpp;
11849}
11850
644db711
DV
11851static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11852{
11853 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11854 "type: 0x%x flags: 0x%x\n",
1342830c 11855 mode->crtc_clock,
644db711
DV
11856 mode->crtc_hdisplay, mode->crtc_hsync_start,
11857 mode->crtc_hsync_end, mode->crtc_htotal,
11858 mode->crtc_vdisplay, mode->crtc_vsync_start,
11859 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11860}
11861
c0b03411 11862static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11863 struct intel_crtc_state *pipe_config,
c0b03411
DV
11864 const char *context)
11865{
6a60cd87
CK
11866 struct drm_device *dev = crtc->base.dev;
11867 struct drm_plane *plane;
11868 struct intel_plane *intel_plane;
11869 struct intel_plane_state *state;
11870 struct drm_framebuffer *fb;
11871
11872 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11873 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV
11874
11875 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11876 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11877 pipe_config->pipe_bpp, pipe_config->dither);
11878 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11879 pipe_config->has_pch_encoder,
11880 pipe_config->fdi_lanes,
11881 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11882 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11883 pipe_config->fdi_m_n.tu);
90a6b7b0 11884 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11885 pipe_config->has_dp_encoder,
90a6b7b0 11886 pipe_config->lane_count,
eb14cb74
VS
11887 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11888 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11889 pipe_config->dp_m_n.tu);
b95af8be 11890
90a6b7b0 11891 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11892 pipe_config->has_dp_encoder,
90a6b7b0 11893 pipe_config->lane_count,
b95af8be
VK
11894 pipe_config->dp_m2_n2.gmch_m,
11895 pipe_config->dp_m2_n2.gmch_n,
11896 pipe_config->dp_m2_n2.link_m,
11897 pipe_config->dp_m2_n2.link_n,
11898 pipe_config->dp_m2_n2.tu);
11899
55072d19
DV
11900 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11901 pipe_config->has_audio,
11902 pipe_config->has_infoframe);
11903
c0b03411 11904 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11905 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11906 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO
11907 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11908 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11909 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS
11910 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11911 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU
11912 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11913 crtc->num_scalers,
11914 pipe_config->scaler_state.scaler_users,
11915 pipe_config->scaler_state.scaler_id);
c0b03411
DV
11916 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11917 pipe_config->gmch_pfit.control,
11918 pipe_config->gmch_pfit.pgm_ratios,
11919 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11920 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11921 pipe_config->pch_pfit.pos,
fd4daa9c
CW
11922 pipe_config->pch_pfit.size,
11923 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11924 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11925 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11926
415ff0f6 11927 if (IS_BROXTON(dev)) {
05712c15 11928 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11929 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11930 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU
11931 pipe_config->ddi_pll_sel,
11932 pipe_config->dpll_hw_state.ebb0,
05712c15 11933 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU
11934 pipe_config->dpll_hw_state.pll0,
11935 pipe_config->dpll_hw_state.pll1,
11936 pipe_config->dpll_hw_state.pll2,
11937 pipe_config->dpll_hw_state.pll3,
11938 pipe_config->dpll_hw_state.pll6,
11939 pipe_config->dpll_hw_state.pll8,
05712c15 11940 pipe_config->dpll_hw_state.pll9,
c8453338 11941 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU
11942 pipe_config->dpll_hw_state.pcsdw12);
11943 } else if (IS_SKYLAKE(dev)) {
11944 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11945 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11946 pipe_config->ddi_pll_sel,
11947 pipe_config->dpll_hw_state.ctrl1,
11948 pipe_config->dpll_hw_state.cfgcr1,
11949 pipe_config->dpll_hw_state.cfgcr2);
11950 } else if (HAS_DDI(dev)) {
11951 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11952 pipe_config->ddi_pll_sel,
11953 pipe_config->dpll_hw_state.wrpll);
11954 } else {
11955 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11956 "fp0: 0x%x, fp1: 0x%x\n",
11957 pipe_config->dpll_hw_state.dpll,
11958 pipe_config->dpll_hw_state.dpll_md,
11959 pipe_config->dpll_hw_state.fp0,
11960 pipe_config->dpll_hw_state.fp1);
11961 }
11962
6a60cd87
CK
11963 DRM_DEBUG_KMS("planes on this crtc\n");
11964 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11965 intel_plane = to_intel_plane(plane);
11966 if (intel_plane->pipe != crtc->pipe)
11967 continue;
11968
11969 state = to_intel_plane_state(plane->state);
11970 fb = state->base.fb;
11971 if (!fb) {
11972 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11973 "disabled, scaler_id = %d\n",
11974 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11975 plane->base.id, intel_plane->pipe,
11976 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11977 drm_plane_index(plane), state->scaler_id);
11978 continue;
11979 }
11980
11981 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11982 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11983 plane->base.id, intel_plane->pipe,
11984 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11985 drm_plane_index(plane));
11986 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11987 fb->base.id, fb->width, fb->height, fb->pixel_format);
11988 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11989 state->scaler_id,
11990 state->src.x1 >> 16, state->src.y1 >> 16,
11991 drm_rect_width(&state->src) >> 16,
11992 drm_rect_height(&state->src) >> 16,
11993 state->dst.x1, state->dst.y1,
11994 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11995 }
c0b03411
DV
11996}
11997
5448a00d 11998static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11999{
5448a00d
ACO
12000 struct drm_device *dev = state->dev;
12001 struct intel_encoder *encoder;
da3ced29 12002 struct drm_connector *connector;
5448a00d 12003 struct drm_connector_state *connector_state;
00f0b378 12004 unsigned int used_ports = 0;
5448a00d 12005 int i;
00f0b378
VS
12006
12007 /*
12008 * Walk the connector list instead of the encoder
12009 * list to detect the problem on ddi platforms
12010 * where there's just one encoder per digital port.
12011 */
da3ced29 12012 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12013 if (!connector_state->best_encoder)
00f0b378
VS
12014 continue;
12015
5448a00d
ACO
12016 encoder = to_intel_encoder(connector_state->best_encoder);
12017
12018 WARN_ON(!connector_state->crtc);
00f0b378
VS
12019
12020 switch (encoder->type) {
12021 unsigned int port_mask;
12022 case INTEL_OUTPUT_UNKNOWN:
12023 if (WARN_ON(!HAS_DDI(dev)))
12024 break;
12025 case INTEL_OUTPUT_DISPLAYPORT:
12026 case INTEL_OUTPUT_HDMI:
12027 case INTEL_OUTPUT_EDP:
12028 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12029
12030 /* the same port mustn't appear more than once */
12031 if (used_ports & port_mask)
12032 return false;
12033
12034 used_ports |= port_mask;
12035 default:
12036 break;
12037 }
12038 }
12039
12040 return true;
12041}
12042
83a57153
ACO
12043static void
12044clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12045{
12046 struct drm_crtc_state tmp_state;
663a3640 12047 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO
12048 struct intel_dpll_hw_state dpll_hw_state;
12049 enum intel_dpll_id shared_dpll;
8504c74c 12050 uint32_t ddi_pll_sel;
c4e2d043 12051 bool force_thru;
83a57153 12052
7546a384
ACO
12053 /* FIXME: before the switch to atomic started, a new pipe_config was
12054 * kzalloc'd. Code that depends on any field being zero should be
12055 * fixed, so that the crtc_state can be safely duplicated. For now,
12056 * only fields that are know to not cause problems are preserved. */
12057
83a57153 12058 tmp_state = crtc_state->base;
663a3640 12059 scaler_state = crtc_state->scaler_state;
4978cc93
ACO
12060 shared_dpll = crtc_state->shared_dpll;
12061 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12062 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12063 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12064
83a57153 12065 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12066
83a57153 12067 crtc_state->base = tmp_state;
663a3640 12068 crtc_state->scaler_state = scaler_state;
4978cc93
ACO
12069 crtc_state->shared_dpll = shared_dpll;
12070 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12071 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12072 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO
12073}
12074
548ee15b 12075static int
b8cecdf5 12076intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12077 struct intel_crtc_state *pipe_config)
ee7b9f93 12078{
b359283a 12079 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12080 struct intel_encoder *encoder;
da3ced29 12081 struct drm_connector *connector;
0b901879 12082 struct drm_connector_state *connector_state;
d328c9d7 12083 int base_bpp, ret = -EINVAL;
0b901879 12084 int i;
e29c22c0 12085 bool retry = true;
ee7b9f93 12086
83a57153 12087 clear_intel_crtc_state(pipe_config);
7758a113 12088
e143a21c
DV
12089 pipe_config->cpu_transcoder =
12090 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12091
2960bc9c
ID
12092 /*
12093 * Sanitize sync polarity flags based on requested ones. If neither
12094 * positive or negative polarity is requested, treat this as meaning
12095 * negative polarity.
12096 */
2d112de7 12097 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12098 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12099 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12100
2d112de7 12101 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12102 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12103 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12104
050f7aeb
DV
12105 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12106 * plane pixel format and any sink constraints into account. Returns the
12107 * source plane bpp so that dithering can be selected on mismatches
12108 * after encoders and crtc also have had their say. */
d328c9d7
DV
12109 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12110 pipe_config);
12111 if (base_bpp < 0)
4e53c2e0
DV
12112 goto fail;
12113
e41a56be
VS
12114 /*
12115 * Determine the real pipe dimensions. Note that stereo modes can
12116 * increase the actual pipe size due to the frame doubling and
12117 * insertion of additional space for blanks between the frame. This
12118 * is stored in the crtc timings. We use the requested mode to do this
12119 * computation to clearly distinguish it from the adjusted mode, which
12120 * can be changed by the connectors in the below retry loop.
12121 */
2d112de7 12122 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP
12123 &pipe_config->pipe_src_w,
12124 &pipe_config->pipe_src_h);
e41a56be 12125
e29c22c0 12126encoder_retry:
ef1b460d 12127 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12128 pipe_config->port_clock = 0;
ef1b460d 12129 pipe_config->pixel_multiplier = 1;
ff9a6750 12130
135c81b8 12131 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO
12132 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12133 CRTC_STEREO_DOUBLE);
135c81b8 12134
7758a113
DV
12135 /* Pass our mode to the connectors and the CRTC to give them a chance to
12136 * adjust it according to limitations or connector properties, and also
12137 * a chance to reject the mode entirely.
47f1c6c9 12138 */
da3ced29 12139 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12140 if (connector_state->crtc != crtc)
7758a113 12141 continue;
7ae89233 12142
0b901879
ACO
12143 encoder = to_intel_encoder(connector_state->best_encoder);
12144
efea6e8e
DV
12145 if (!(encoder->compute_config(encoder, pipe_config))) {
12146 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV
12147 goto fail;
12148 }
ee7b9f93 12149 }
47f1c6c9 12150
ff9a6750
DV
12151 /* Set default port clock if not overwritten by the encoder. Needs to be
12152 * done afterwards in case the encoder adjusts the mode. */
12153 if (!pipe_config->port_clock)
2d112de7 12154 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12155 * pipe_config->pixel_multiplier;
ff9a6750 12156
a43f6e0f 12157 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12158 if (ret < 0) {
7758a113
DV
12159 DRM_DEBUG_KMS("CRTC fixup failed\n");
12160 goto fail;
ee7b9f93 12161 }
e29c22c0
DV
12162
12163 if (ret == RETRY) {
12164 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12165 ret = -EINVAL;
12166 goto fail;
12167 }
12168
12169 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12170 retry = false;
12171 goto encoder_retry;
12172 }
12173
e8fa4270
DV
12174 /* Dithering seems to not pass-through bits correctly when it should, so
12175 * only enable it on 6bpc panels. */
12176 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
4e53c2e0 12177 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12178 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12179
7758a113 12180fail:
548ee15b 12181 return ret;
ee7b9f93 12182}
47f1c6c9 12183
ea9d758d 12184static void
4740b0f2 12185intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12186{
0a9ab303
ACO
12187 struct drm_crtc *crtc;
12188 struct drm_crtc_state *crtc_state;
8a75d157 12189 int i;
ea9d758d 12190
7668851f 12191 /* Double check state. */
8a75d157 12192 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12193 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML
12194
12195 /* Update hwmode for vblank functions */
12196 if (crtc->state->active)
12197 crtc->hwmode = crtc->state->adjusted_mode;
12198 else
12199 crtc->hwmode.crtc_clock = 0;
ea9d758d 12200 }
ea9d758d
DV
12201}
12202
3bd26263 12203static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12204{
3bd26263 12205 int diff;
f1f644dc
JB
12206
12207 if (clock1 == clock2)
12208 return true;
12209
12210 if (!clock1 || !clock2)
12211 return false;
12212
12213 diff = abs(clock1 - clock2);
12214
12215 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12216 return true;
12217
12218 return false;
12219}
12220
25c5b266
DV
12221#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12222 list_for_each_entry((intel_crtc), \
12223 &(dev)->mode_config.crtc_list, \
12224 base.head) \
0973f18f 12225 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12226
cfb23ed6
ML
12227
12228static bool
12229intel_compare_m_n(unsigned int m, unsigned int n,
12230 unsigned int m2, unsigned int n2,
12231 bool exact)
12232{
12233 if (m == m2 && n == n2)
12234 return true;
12235
12236 if (exact || !m || !n || !m2 || !n2)
12237 return false;
12238
12239 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12240
12241 if (m > m2) {
12242 while (m > m2) {
12243 m2 <<= 1;
12244 n2 <<= 1;
12245 }
12246 } else if (m < m2) {
12247 while (m < m2) {
12248 m <<= 1;
12249 n <<= 1;
12250 }
12251 }
12252
12253 return m == m2 && n == n2;
12254}
12255
12256static bool
12257intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12258 struct intel_link_m_n *m2_n2,
12259 bool adjust)
12260{
12261 if (m_n->tu == m2_n2->tu &&
12262 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12263 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12264 intel_compare_m_n(m_n->link_m, m_n->link_n,
12265 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12266 if (adjust)
12267 *m2_n2 = *m_n;
12268
12269 return true;
12270 }
12271
12272 return false;
12273}
12274
0e8ffe1b 12275static bool
2fa2fe9a 12276intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12277 struct intel_crtc_state *current_config,
cfb23ed6
ML
12278 struct intel_crtc_state *pipe_config,
12279 bool adjust)
0e8ffe1b 12280{
cfb23ed6
ML
12281 bool ret = true;
12282
12283#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12284 do { \
12285 if (!adjust) \
12286 DRM_ERROR(fmt, ##__VA_ARGS__); \
12287 else \
12288 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12289 } while (0)
12290
66e985c0
DV
12291#define PIPE_CONF_CHECK_X(name) \
12292 if (current_config->name != pipe_config->name) { \
cfb23ed6 12293 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV
12294 "(expected 0x%08x, found 0x%08x)\n", \
12295 current_config->name, \
12296 pipe_config->name); \
cfb23ed6 12297 ret = false; \
66e985c0
DV
12298 }
12299
08a24034
DV
12300#define PIPE_CONF_CHECK_I(name) \
12301 if (current_config->name != pipe_config->name) { \
cfb23ed6 12302 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV
12303 "(expected %i, found %i)\n", \
12304 current_config->name, \
12305 pipe_config->name); \
cfb23ed6
ML
12306 ret = false; \
12307 }
12308
12309#define PIPE_CONF_CHECK_M_N(name) \
12310 if (!intel_compare_link_m_n(&current_config->name, \
12311 &pipe_config->name,\
12312 adjust)) { \
12313 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12314 "(expected tu %i gmch %i/%i link %i/%i, " \
12315 "found tu %i, gmch %i/%i link %i/%i)\n", \
12316 current_config->name.tu, \
12317 current_config->name.gmch_m, \
12318 current_config->name.gmch_n, \
12319 current_config->name.link_m, \
12320 current_config->name.link_n, \
12321 pipe_config->name.tu, \
12322 pipe_config->name.gmch_m, \
12323 pipe_config->name.gmch_n, \
12324 pipe_config->name.link_m, \
12325 pipe_config->name.link_n); \
12326 ret = false; \
12327 }
12328
12329#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12330 if (!intel_compare_link_m_n(&current_config->name, \
12331 &pipe_config->name, adjust) && \
12332 !intel_compare_link_m_n(&current_config->alt_name, \
12333 &pipe_config->name, adjust)) { \
12334 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12335 "(expected tu %i gmch %i/%i link %i/%i, " \
12336 "or tu %i gmch %i/%i link %i/%i, " \
12337 "found tu %i, gmch %i/%i link %i/%i)\n", \
12338 current_config->name.tu, \
12339 current_config->name.gmch_m, \
12340 current_config->name.gmch_n, \
12341 current_config->name.link_m, \
12342 current_config->name.link_n, \
12343 current_config->alt_name.tu, \
12344 current_config->alt_name.gmch_m, \
12345 current_config->alt_name.gmch_n, \
12346 current_config->alt_name.link_m, \
12347 current_config->alt_name.link_n, \
12348 pipe_config->name.tu, \
12349 pipe_config->name.gmch_m, \
12350 pipe_config->name.gmch_n, \
12351 pipe_config->name.link_m, \
12352 pipe_config->name.link_n); \
12353 ret = false; \
88adfff1
DV
12354 }
12355
b95af8be
VK
12356/* This is required for BDW+ where there is only one set of registers for
12357 * switching between high and low RR.
12358 * This macro can be used whenever a comparison has to be made between one
12359 * hw state and multiple sw state variables.
12360 */
12361#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12362 if ((current_config->name != pipe_config->name) && \
12363 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12364 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK
12365 "(expected %i or %i, found %i)\n", \
12366 current_config->name, \
12367 current_config->alt_name, \
12368 pipe_config->name); \
cfb23ed6 12369 ret = false; \
b95af8be
VK
12370 }
12371
1bd1bd80
DV
12372#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12373 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12374 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV
12375 "(expected %i, found %i)\n", \
12376 current_config->name & (mask), \
12377 pipe_config->name & (mask)); \
cfb23ed6 12378 ret = false; \
1bd1bd80
DV
12379 }
12380
5e550656
VS
12381#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12382 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12383 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS
12384 "(expected %i, found %i)\n", \
12385 current_config->name, \
12386 pipe_config->name); \
cfb23ed6 12387 ret = false; \
5e550656
VS
12388 }
12389
bb760063
DV
12390#define PIPE_CONF_QUIRK(quirk) \
12391 ((current_config->quirks | pipe_config->quirks) & (quirk))
12392
eccb140b
DV
12393 PIPE_CONF_CHECK_I(cpu_transcoder);
12394
08a24034
DV
12395 PIPE_CONF_CHECK_I(has_pch_encoder);
12396 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12397 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12398
eb14cb74 12399 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12400 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK
12401
12402 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML
12403 PIPE_CONF_CHECK_M_N(dp_m_n);
12404
12405 PIPE_CONF_CHECK_I(has_drrs);
12406 if (current_config->has_drrs)
12407 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12408 } else
12409 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12410
2d112de7
ACO
12411 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12412 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12413 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12414 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12415 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12416 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12417
2d112de7
ACO
12418 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12419 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12420 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12421 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12422 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12423 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12424
c93f54cf 12425 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12426 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV
12427 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12428 IS_VALLEYVIEW(dev))
12429 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12430 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12431
9ed109a7
DV
12432 PIPE_CONF_CHECK_I(has_audio);
12433
2d112de7 12434 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV
12435 DRM_MODE_FLAG_INTERLACE);
12436
bb760063 12437 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12438 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12439 DRM_MODE_FLAG_PHSYNC);
2d112de7 12440 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12441 DRM_MODE_FLAG_NHSYNC);
2d112de7 12442 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12443 DRM_MODE_FLAG_PVSYNC);
2d112de7 12444 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV
12445 DRM_MODE_FLAG_NVSYNC);
12446 }
045ac3b5 12447
37327abd
VS
12448 PIPE_CONF_CHECK_I(pipe_src_w);
12449 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12450
e2ff2d4a
DV
12451 PIPE_CONF_CHECK_I(gmch_pfit.control);
12452 /* pfit ratios are autocomputed by the hw on gen4+ */
12453 if (INTEL_INFO(dev)->gen < 4)
12454 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12455 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9953599b 12456
fd4daa9c
CW
12457 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12458 if (current_config->pch_pfit.enabled) {
12459 PIPE_CONF_CHECK_I(pch_pfit.pos);
12460 PIPE_CONF_CHECK_I(pch_pfit.size);
12461 }
2fa2fe9a 12462
a1b2278e
CK
12463 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12464
e59150dc
JB
12465 /* BDW+ don't expose a synchronous way to read the state */
12466 if (IS_HASWELL(dev))
12467 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12468
282740f7
VS
12469 PIPE_CONF_CHECK_I(double_wide);
12470
26804afd
DV
12471 PIPE_CONF_CHECK_X(ddi_pll_sel);
12472
c0d43d62 12473 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12474 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12475 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV
12476 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12477 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12478 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL
12479 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12480 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12481 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12482
42571aef
VS
12483 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12484 PIPE_CONF_CHECK_I(pipe_bpp);
12485
2d112de7 12486 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12487 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12488
66e985c0 12489#undef PIPE_CONF_CHECK_X
08a24034 12490#undef PIPE_CONF_CHECK_I
b95af8be 12491#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12492#undef PIPE_CONF_CHECK_FLAGS
5e550656 12493#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12494#undef PIPE_CONF_QUIRK
cfb23ed6 12495#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12496
cfb23ed6 12497 return ret;
0e8ffe1b
DV
12498}
12499
08db6652
DL
12500static void check_wm_state(struct drm_device *dev)
12501{
12502 struct drm_i915_private *dev_priv = dev->dev_private;
12503 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12504 struct intel_crtc *intel_crtc;
12505 int plane;
12506
12507 if (INTEL_INFO(dev)->gen < 9)
12508 return;
12509
12510 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12511 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12512
12513 for_each_intel_crtc(dev, intel_crtc) {
12514 struct skl_ddb_entry *hw_entry, *sw_entry;
12515 const enum pipe pipe = intel_crtc->pipe;
12516
12517 if (!intel_crtc->active)
12518 continue;
12519
12520 /* planes */
dd740780 12521 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL
12522 hw_entry = &hw_ddb.plane[pipe][plane];
12523 sw_entry = &sw_ddb->plane[pipe][plane];
12524
12525 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12526 continue;
12527
12528 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12529 "(expected (%u,%u), found (%u,%u))\n",
12530 pipe_name(pipe), plane + 1,
12531 sw_entry->start, sw_entry->end,
12532 hw_entry->start, hw_entry->end);
12533 }
12534
12535 /* cursor */
12536 hw_entry = &hw_ddb.cursor[pipe];
12537 sw_entry = &sw_ddb->cursor[pipe];
12538
12539 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12540 continue;
12541
12542 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12543 "(expected (%u,%u), found (%u,%u))\n",
12544 pipe_name(pipe),
12545 sw_entry->start, sw_entry->end,
12546 hw_entry->start, hw_entry->end);
12547 }
12548}
12549
91d1b4bd 12550static void
35dd3c64
ML
12551check_connector_state(struct drm_device *dev,
12552 struct drm_atomic_state *old_state)
8af6cf88 12553{
35dd3c64
ML
12554 struct drm_connector_state *old_conn_state;
12555 struct drm_connector *connector;
12556 int i;
8af6cf88 12557
35dd3c64
ML
12558 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12559 struct drm_encoder *encoder = connector->encoder;
12560 struct drm_connector_state *state = connector->state;
ad3c558f 12561
8af6cf88
DV
12562 /* This also checks the encoder/connector hw state with the
12563 * ->get_hw_state callbacks. */
35dd3c64 12564 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12565
ad3c558f 12566 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12567 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12568 }
91d1b4bd
DV
12569}
12570
12571static void
12572check_encoder_state(struct drm_device *dev)
12573{
12574 struct intel_encoder *encoder;
12575 struct intel_connector *connector;
8af6cf88 12576
b2784e15 12577 for_each_intel_encoder(dev, encoder) {
8af6cf88 12578 bool enabled = false;
4d20cd86 12579 enum pipe pipe;
8af6cf88
DV
12580
12581 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12582 encoder->base.base.id,
8e329a03 12583 encoder->base.name);
8af6cf88 12584
3a3371ff 12585 for_each_intel_connector(dev, connector) {
4d20cd86 12586 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV
12587 continue;
12588 enabled = true;
ad3c558f
ML
12589
12590 I915_STATE_WARN(connector->base.state->crtc !=
12591 encoder->base.crtc,
12592 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12593 }
0e32b39c 12594
e2c719b7 12595 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV
12596 "encoder's enabled state mismatch "
12597 "(expected %i, found %i)\n",
12598 !!encoder->base.crtc, enabled);
7c60d198
ML
12599
12600 if (!encoder->base.crtc) {
4d20cd86 12601 bool active;
7c60d198 12602
4d20cd86
ML
12603 active = encoder->get_hw_state(encoder, &pipe);
12604 I915_STATE_WARN(active,
12605 "encoder detached but still enabled on pipe %c.\n",
12606 pipe_name(pipe));
7c60d198 12607 }
8af6cf88 12608 }
91d1b4bd
DV
12609}
12610
12611static void
4d20cd86 12612check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12613{
fbee40df 12614 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12615 struct intel_encoder *encoder;
4d20cd86
ML
12616 struct drm_crtc_state *old_crtc_state;
12617 struct drm_crtc *crtc;
12618 int i;
8af6cf88 12619
4d20cd86
ML
12620 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12622 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12623 bool active;
8af6cf88 12624
4d20cd86
ML
12625 if (!needs_modeset(crtc->state))
12626 continue;
045ac3b5 12627
4d20cd86
ML
12628 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12629 pipe_config = to_intel_crtc_state(old_crtc_state);
12630 memset(pipe_config, 0, sizeof(*pipe_config));
12631 pipe_config->base.crtc = crtc;
12632 pipe_config->base.state = old_state;
8af6cf88 12633
4d20cd86
ML
12634 DRM_DEBUG_KMS("[CRTC:%d]\n",
12635 crtc->base.id);
8af6cf88 12636
4d20cd86
ML
12637 active = dev_priv->display.get_pipe_config(intel_crtc,
12638 pipe_config);
d62cf62a 12639
b6b5d049 12640 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML
12641 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12642 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12643 active = crtc->state->active;
6c49f241 12644
4d20cd86 12645 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12646 "crtc active state doesn't match with hw state "
4d20cd86 12647 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12648
4d20cd86 12649 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12650 "transitional active state does not match atomic hw state "
4d20cd86
ML
12651 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12652
12653 for_each_encoder_on_crtc(dev, crtc, encoder) {
12654 enum pipe pipe;
12655
12656 active = encoder->get_hw_state(encoder, &pipe);
12657 I915_STATE_WARN(active != crtc->state->active,
12658 "[ENCODER:%i] active %i with crtc active %i\n",
12659 encoder->base.base.id, active, crtc->state->active);
12660
12661 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12662 "Encoder connected to wrong pipe %c\n",
12663 pipe_name(pipe));
12664
12665 if (active)
12666 encoder->get_config(encoder, pipe_config);
12667 }
53d9f4e9 12668
4d20cd86 12669 if (!crtc->state->active)
cfb23ed6
ML
12670 continue;
12671
4d20cd86
ML
12672 sw_config = to_intel_crtc_state(crtc->state);
12673 if (!intel_pipe_config_compare(dev, sw_config,
12674 pipe_config, false)) {
e2c719b7 12675 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12676 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12677 "[hw state]");
4d20cd86 12678 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV
12679 "[sw state]");
12680 }
8af6cf88
DV
12681 }
12682}
12683
91d1b4bd
DV
12684static void
12685check_shared_dpll_state(struct drm_device *dev)
12686{
fbee40df 12687 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV
12688 struct intel_crtc *crtc;
12689 struct intel_dpll_hw_state dpll_hw_state;
12690 int i;
5358901f
DV
12691
12692 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12693 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12694 int enabled_crtcs = 0, active_crtcs = 0;
12695 bool active;
12696
12697 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12698
12699 DRM_DEBUG_KMS("%s\n", pll->name);
12700
12701 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12702
e2c719b7 12703 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12704 "more active pll users than references: %i vs %i\n",
3e369b76 12705 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12706 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12707 "pll in active use but not on in sw tracking\n");
e2c719b7 12708 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12709 "pll in on but not on in use in sw tracking\n");
e2c719b7 12710 I915_STATE_WARN(pll->on != active,
5358901f
DV
12711 "pll on state mismatch (expected %i, found %i)\n",
12712 pll->on, active);
12713
d3fcc808 12714 for_each_intel_crtc(dev, crtc) {
83d65738 12715 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV
12716 enabled_crtcs++;
12717 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12718 active_crtcs++;
12719 }
e2c719b7 12720 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV
12721 "pll active crtcs mismatch (expected %i, found %i)\n",
12722 pll->active, active_crtcs);
e2c719b7 12723 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12724 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12725 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12726
e2c719b7 12727 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV
12728 sizeof(dpll_hw_state)),
12729 "pll hw state mismatch\n");
5358901f 12730 }
8af6cf88
DV
12731}
12732
ee165b1a
ML
12733static void
12734intel_modeset_check_state(struct drm_device *dev,
12735 struct drm_atomic_state *old_state)
91d1b4bd 12736{
08db6652 12737 check_wm_state(dev);
35dd3c64 12738 check_connector_state(dev, old_state);
91d1b4bd 12739 check_encoder_state(dev);
4d20cd86 12740 check_crtc_state(dev, old_state);
91d1b4bd
DV
12741 check_shared_dpll_state(dev);
12742}
12743
5cec258b 12744void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS
12745 int dotclock)
12746{
12747 /*
12748 * FDI already provided one idea for the dotclock.
12749 * Yell if the encoder disagrees.
12750 */
2d112de7 12751 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12752 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12753 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS
12754}
12755
80715b2f
VS
12756static void update_scanline_offset(struct intel_crtc *crtc)
12757{
12758 struct drm_device *dev = crtc->base.dev;
12759
12760 /*
12761 * The scanline counter increments at the leading edge of hsync.
12762 *
12763 * On most platforms it starts counting from vtotal-1 on the
12764 * first active line. That means the scanline counter value is
12765 * always one less than what we would expect. Ie. just after
12766 * start of vblank, which also occurs at start of hsync (on the
12767 * last active line), the scanline counter will read vblank_start-1.
12768 *
12769 * On gen2 the scanline counter starts counting from 1 instead
12770 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12771 * to keep the value positive), instead of adding one.
12772 *
12773 * On HSW+ the behaviour of the scanline counter depends on the output
12774 * type. For DP ports it behaves like most other platforms, but on HDMI
12775 * there's an extra 1 line difference. So we need to add two instead of
12776 * one to the value.
12777 */
12778 if (IS_GEN2(dev)) {
6e3c9717 12779 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS
12780 int vtotal;
12781
12782 vtotal = mode->crtc_vtotal;
12783 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12784 vtotal /= 2;
12785
12786 crtc->scanline_offset = vtotal - 1;
12787 } else if (HAS_DDI(dev) &&
409ee761 12788 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS
12789 crtc->scanline_offset = 2;
12790 } else
12791 crtc->scanline_offset = 1;
12792}
12793
ad421372 12794static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12795{
225da59b 12796 struct drm_device *dev = state->dev;
ed6739ef 12797 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12798 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12799 struct intel_crtc *intel_crtc;
0a9ab303
ACO
12800 struct intel_crtc_state *intel_crtc_state;
12801 struct drm_crtc *crtc;
12802 struct drm_crtc_state *crtc_state;
0a9ab303 12803 int i;
ed6739ef
ACO
12804
12805 if (!dev_priv->display.crtc_compute_clock)
ad421372 12806 return;
ed6739ef 12807
0a9ab303 12808 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML
12809 int dpll;
12810
0a9ab303 12811 intel_crtc = to_intel_crtc(crtc);
4978cc93 12812 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12813 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12814
ad421372 12815 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO
12816 continue;
12817
ad421372 12818 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12819
ad421372
ML
12820 if (!shared_dpll)
12821 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12822
ad421372
ML
12823 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12824 }
ed6739ef
ACO
12825}
12826
99d736a2
ML
12827/*
12828 * This implements the workaround described in the "notes" section of the mode
12829 * set sequence documentation. When going from no pipes or single pipe to
12830 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12831 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12832 */
12833static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12834{
12835 struct drm_crtc_state *crtc_state;
12836 struct intel_crtc *intel_crtc;
12837 struct drm_crtc *crtc;
12838 struct intel_crtc_state *first_crtc_state = NULL;
12839 struct intel_crtc_state *other_crtc_state = NULL;
12840 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12841 int i;
12842
12843 /* look at all crtc's that are going to be enabled in during modeset */
12844 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12845 intel_crtc = to_intel_crtc(crtc);
12846
12847 if (!crtc_state->active || !needs_modeset(crtc_state))
12848 continue;
12849
12850 if (first_crtc_state) {
12851 other_crtc_state = to_intel_crtc_state(crtc_state);
12852 break;
12853 } else {
12854 first_crtc_state = to_intel_crtc_state(crtc_state);
12855 first_pipe = intel_crtc->pipe;
12856 }
12857 }
12858
12859 /* No workaround needed? */
12860 if (!first_crtc_state)
12861 return 0;
12862
12863 /* w/a possibly needed, check how many crtc's are already enabled. */
12864 for_each_intel_crtc(state->dev, intel_crtc) {
12865 struct intel_crtc_state *pipe_config;
12866
12867 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12868 if (IS_ERR(pipe_config))
12869 return PTR_ERR(pipe_config);
12870
12871 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12872
12873 if (!pipe_config->base.active ||
12874 needs_modeset(&pipe_config->base))
12875 continue;
12876
12877 /* 2 or more enabled crtcs means no need for w/a */
12878 if (enabled_pipe != INVALID_PIPE)
12879 return 0;
12880
12881 enabled_pipe = intel_crtc->pipe;
12882 }
12883
12884 if (enabled_pipe != INVALID_PIPE)
12885 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12886 else if (other_crtc_state)
12887 other_crtc_state->hsw_workaround_pipe = first_pipe;
12888
12889 return 0;
12890}
12891
27c329ed
ML
12892static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12893{
12894 struct drm_crtc *crtc;
12895 struct drm_crtc_state *crtc_state;
12896 int ret = 0;
12897
12898 /* add all active pipes to the state */
12899 for_each_crtc(state->dev, crtc) {
12900 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12901 if (IS_ERR(crtc_state))
12902 return PTR_ERR(crtc_state);
12903
12904 if (!crtc_state->active || needs_modeset(crtc_state))
12905 continue;
12906
12907 crtc_state->mode_changed = true;
12908
12909 ret = drm_atomic_add_affected_connectors(state, crtc);
12910 if (ret)
12911 break;
12912
12913 ret = drm_atomic_add_affected_planes(state, crtc);
12914 if (ret)
12915 break;
12916 }
12917
12918 return ret;
12919}
12920
12921
c347a676 12922static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO
12923{
12924 struct drm_device *dev = state->dev;
27c329ed 12925 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO
12926 int ret;
12927
b359283a
ML
12928 if (!check_digital_port_conflicts(state)) {
12929 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12930 return -EINVAL;
12931 }
12932
054518dd
ACO
12933 /*
12934 * See if the config requires any additional preparation, e.g.
12935 * to adjust global state with pipes off. We need to do this
12936 * here so we can get the modeset_pipe updated config for the new
12937 * mode set on this crtc. For other crtcs we need to use the
12938 * adjusted_mode bits in the crtc directly.
12939 */
27c329ed
ML
12940 if (dev_priv->display.modeset_calc_cdclk) {
12941 unsigned int cdclk;
b432e5cf 12942
27c329ed
ML
12943 ret = dev_priv->display.modeset_calc_cdclk(state);
12944
12945 cdclk = to_intel_atomic_state(state)->cdclk;
12946 if (!ret && cdclk != dev_priv->cdclk_freq)
12947 ret = intel_modeset_all_pipes(state);
12948
12949 if (ret < 0)
054518dd 12950 return ret;
27c329ed
ML
12951 } else
12952 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12953
ad421372 12954 intel_modeset_clear_plls(state);
054518dd 12955
99d736a2 12956 if (IS_HASWELL(dev))
ad421372 12957 return haswell_mode_set_planes_workaround(state);
99d736a2 12958
ad421372 12959 return 0;
c347a676
ACO
12960}
12961
74c090b1
ML
12962/**
12963 * intel_atomic_check - validate state object
12964 * @dev: drm device
12965 * @state: state to validate
12966 */
12967static int intel_atomic_check(struct drm_device *dev,
12968 struct drm_atomic_state *state)
c347a676
ACO
12969{
12970 struct drm_crtc *crtc;
12971 struct drm_crtc_state *crtc_state;
12972 int ret, i;
61333b60 12973 bool any_ms = false;
c347a676 12974
74c090b1 12975 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO
12976 if (ret)
12977 return ret;
12978
c347a676 12979 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML
12980 struct intel_crtc_state *pipe_config =
12981 to_intel_crtc_state(crtc_state);
1ed51de9
DV
12982
12983 /* Catch I915_MODE_FLAG_INHERITED */
12984 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12985 crtc_state->mode_changed = true;
cfb23ed6 12986
61333b60
ML
12987 if (!crtc_state->enable) {
12988 if (needs_modeset(crtc_state))
12989 any_ms = true;
c347a676 12990 continue;
61333b60 12991 }
c347a676 12992
26495481 12993 if (!needs_modeset(crtc_state))
cfb23ed6
ML
12994 continue;
12995
26495481
DV
12996 /* FIXME: For only active_changed we shouldn't need to do any
12997 * state recomputation at all. */
12998
1ed51de9
DV
12999 ret = drm_atomic_add_affected_connectors(state, crtc);
13000 if (ret)
13001 return ret;
b359283a 13002
cfb23ed6 13003 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO
13004 if (ret)
13005 return ret;
13006
26495481
DV
13007 if (i915.fastboot &&
13008 intel_pipe_config_compare(state->dev,
cfb23ed6 13009 to_intel_crtc_state(crtc->state),
1ed51de9 13010 pipe_config, true)) {
26495481
DV
13011 crtc_state->mode_changed = false;
13012 }
13013
13014 if (needs_modeset(crtc_state)) {
13015 any_ms = true;
cfb23ed6
ML
13016
13017 ret = drm_atomic_add_affected_planes(state, crtc);
13018 if (ret)
13019 return ret;
13020 }
61333b60 13021
26495481
DV
13022 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13023 needs_modeset(crtc_state) ?
13024 "[modeset]" : "[fastset]");
c347a676
ACO
13025 }
13026
61333b60
ML
13027 if (any_ms) {
13028 ret = intel_modeset_checks(state);
13029
13030 if (ret)
13031 return ret;
27c329ed
ML
13032 } else
13033 to_intel_atomic_state(state)->cdclk =
13034 to_i915(state->dev)->cdclk_freq;
c347a676
ACO
13035
13036 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO
13037}
13038
74c090b1
ML
13039/**
13040 * intel_atomic_commit - commit validated state object
13041 * @dev: DRM device
13042 * @state: the top-level driver state object
13043 * @async: asynchronous commit
13044 *
13045 * This function commits a top-level state object that has been validated
13046 * with drm_atomic_helper_check().
13047 *
13048 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13049 * we can only handle plane-related operations and do not yet support
13050 * asynchronous commit.
13051 *
13052 * RETURNS
13053 * Zero for success or -errno.
13054 */
13055static int intel_atomic_commit(struct drm_device *dev,
13056 struct drm_atomic_state *state,
13057 bool async)
a6778b3c 13058{
fbee40df 13059 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO
13060 struct drm_crtc *crtc;
13061 struct drm_crtc_state *crtc_state;
c0c36b94 13062 int ret = 0;
0a9ab303 13063 int i;
61333b60 13064 bool any_ms = false;
a6778b3c 13065
74c090b1
ML
13066 if (async) {
13067 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13068 return -EINVAL;
13069 }
13070
d4afb8cc
ACO
13071 ret = drm_atomic_helper_prepare_planes(dev, state);
13072 if (ret)
13073 return ret;
13074
1c5e19f8
ML
13075 drm_atomic_helper_swap_state(dev, state);
13076
0a9ab303 13077 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML
13078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13079
61333b60
ML
13080 if (!needs_modeset(crtc->state))
13081 continue;
13082
13083 any_ms = true;
a539205a 13084 intel_pre_plane_update(intel_crtc);
460da916 13085
a539205a
ML
13086 if (crtc_state->active) {
13087 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13088 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML
13089 intel_crtc->active = false;
13090 intel_disable_shared_dpll(intel_crtc);
a539205a 13091 }
b8cecdf5 13092 }
7758a113 13093
ea9d758d
DV
13094 /* Only after disabling all output pipelines that will be changed can we
13095 * update the the output configuration. */
4740b0f2 13096 intel_modeset_update_crtc_state(state);
f6e5b160 13097
4740b0f2
ML
13098 if (any_ms) {
13099 intel_shared_dpll_commit(state);
13100
13101 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13102 modeset_update_crtc_power_domains(state);
4740b0f2 13103 }
47fab737 13104
a6778b3c 13105 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13106 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML
13107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13108 bool modeset = needs_modeset(crtc->state);
13109
13110 if (modeset && crtc->state->active) {
a539205a
ML
13111 update_scanline_offset(to_intel_crtc(crtc));
13112 dev_priv->display.crtc_enable(crtc);
13113 }
80715b2f 13114
f6ac4b2a
ML
13115 if (!modeset)
13116 intel_pre_plane_update(intel_crtc);
13117
a539205a 13118 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13119 intel_post_plane_update(intel_crtc);
80715b2f 13120 }
a6778b3c 13121
a6778b3c 13122 /* FIXME: add subpixel order */
83a57153 13123
74c090b1 13124 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13125 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13126
74c090b1 13127 if (any_ms)
ee165b1a
ML
13128 intel_modeset_check_state(dev, state);
13129
13130 drm_atomic_state_free(state);
f30da187 13131
74c090b1 13132 return 0;
7f27126e
JB
13133}
13134
c0c36b94
CW
13135void intel_crtc_restore_mode(struct drm_crtc *crtc)
13136{
83a57153
ACO
13137 struct drm_device *dev = crtc->dev;
13138 struct drm_atomic_state *state;
e694eb02 13139 struct drm_crtc_state *crtc_state;
2bfb4627 13140 int ret;
83a57153
ACO
13141
13142 state = drm_atomic_state_alloc(dev);
13143 if (!state) {
e694eb02 13144 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO
13145 crtc->base.id);
13146 return;
13147 }
13148
e694eb02 13149 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13150
e694eb02
ML
13151retry:
13152 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13153 ret = PTR_ERR_OR_ZERO(crtc_state);
13154 if (!ret) {
13155 if (!crtc_state->active)
13156 goto out;
83a57153 13157
e694eb02 13158 crtc_state->mode_changed = true;
74c090b1 13159 ret = drm_atomic_commit(state);
83a57153
ACO
13160 }
13161
e694eb02
ML
13162 if (ret == -EDEADLK) {
13163 drm_atomic_state_clear(state);
13164 drm_modeset_backoff(state->acquire_ctx);
13165 goto retry;
4ed9fb37 13166 }
4be07317 13167
2bfb4627 13168 if (ret)
e694eb02 13169out:
2bfb4627 13170 drm_atomic_state_free(state);
c0c36b94
CW
13171}
13172
25c5b266
DV
13173#undef for_each_intel_crtc_masked
13174
f6e5b160 13175static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13176 .gamma_set = intel_crtc_gamma_set,
74c090b1 13177 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW
13178 .destroy = intel_crtc_destroy,
13179 .page_flip = intel_crtc_page_flip,
1356837e
MR
13180 .atomic_duplicate_state = intel_crtc_duplicate_state,
13181 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW
13182};
13183
5358901f
DV
13184static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13185 struct intel_shared_dpll *pll,
13186 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13187{
5358901f 13188 uint32_t val;
ee7b9f93 13189
f458ebbc 13190 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ
13191 return false;
13192
5358901f 13193 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV
13194 hw_state->dpll = val;
13195 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13196 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV
13197
13198 return val & DPLL_VCO_ENABLE;
13199}
13200
15bdd4cf
DV
13201static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13202 struct intel_shared_dpll *pll)
13203{
3e369b76
ACO
13204 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13205 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV
13206}
13207
e7b903d2
DV
13208static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13209 struct intel_shared_dpll *pll)
13210{
e7b903d2 13211 /* PCH refclock must be enabled first */
89eff4be 13212 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13213
3e369b76 13214 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV
13215
13216 /* Wait for the clocks to stabilize. */
13217 POSTING_READ(PCH_DPLL(pll->id));
13218 udelay(150);
13219
13220 /* The pixel multiplier can only be updated once the
13221 * DPLL is enabled and the clocks are stable.
13222 *
13223 * So write it again.
13224 */
3e369b76 13225 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13226 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV
13227 udelay(200);
13228}
13229
13230static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13231 struct intel_shared_dpll *pll)
13232{
13233 struct drm_device *dev = dev_priv->dev;
13234 struct intel_crtc *crtc;
e7b903d2
DV
13235
13236 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13237 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV
13238 if (intel_crtc_to_shared_dpll(crtc) == pll)
13239 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB
13240 }
13241
15bdd4cf
DV
13242 I915_WRITE(PCH_DPLL(pll->id), 0);
13243 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV
13244 udelay(200);
13245}
13246
46edb027
DV
13247static char *ibx_pch_dpll_names[] = {
13248 "PCH DPLL A",
13249 "PCH DPLL B",
13250};
13251
7c74ade1 13252static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13253{
e7b903d2 13254 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB
13255 int i;
13256
7c74ade1 13257 dev_priv->num_shared_dpll = 2;
ee7b9f93 13258
e72f9fbf 13259 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV
13260 dev_priv->shared_dplls[i].id = i;
13261 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13262 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV
13263 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13264 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV
13265 dev_priv->shared_dplls[i].get_hw_state =
13266 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB
13267 }
13268}
13269
7c74ade1
DV
13270static void intel_shared_dpll_init(struct drm_device *dev)
13271{
e7b903d2 13272 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13273
b6283055
VS
13274 intel_update_cdclk(dev);
13275
9cd86933
DV
13276 if (HAS_DDI(dev))
13277 intel_ddi_pll_init(dev);
13278 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV
13279 ibx_pch_dpll_init(dev);
13280 else
13281 dev_priv->num_shared_dpll = 0;
13282
13283 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV
13284}
13285
6beb8c23
MR
13286/**
13287 * intel_prepare_plane_fb - Prepare fb for usage on plane
13288 * @plane: drm plane to prepare for
13289 * @fb: framebuffer to prepare for presentation
13290 *
13291 * Prepares a framebuffer for usage on a display plane. Generally this
13292 * involves pinning the underlying object and updating the frontbuffer tracking
13293 * bits. Some older platforms need special physical address handling for
13294 * cursor planes.
13295 *
13296 * Returns 0 on success, negative error code on failure.
13297 */
13298int
13299intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU
13300 struct drm_framebuffer *fb,
13301 const struct drm_plane_state *new_state)
465c120c
MR
13302{
13303 struct drm_device *dev = plane->dev;
6beb8c23 13304 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR
13305 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13306 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13307 int ret = 0;
465c120c 13308
ea2c67bb 13309 if (!obj)
465c120c
MR
13310 return 0;
13311
6beb8c23 13312 mutex_lock(&dev->struct_mutex);
465c120c 13313
6beb8c23
MR
13314 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13315 INTEL_INFO(dev)->cursor_needs_physical) {
13316 int align = IS_I830(dev) ? 16 * 1024 : 256;
13317 ret = i915_gem_object_attach_phys(obj, align);
13318 if (ret)
13319 DRM_DEBUG_KMS("failed to attach phys object\n");
13320 } else {
91af127f 13321 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13322 }
465c120c 13323
6beb8c23 13324 if (ret == 0)
a9ff8714 13325 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13326
4c34574f 13327 mutex_unlock(&dev->struct_mutex);
465c120c 13328
6beb8c23
MR
13329 return ret;
13330}
13331
38f3ce3a
MR
13332/**
13333 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13334 * @plane: drm plane to clean up for
13335 * @fb: old framebuffer that was on plane
13336 *
13337 * Cleans up a framebuffer that has just been removed from a plane.
13338 */
13339void
13340intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU
13341 struct drm_framebuffer *fb,
13342 const struct drm_plane_state *old_state)
38f3ce3a
MR
13343{
13344 struct drm_device *dev = plane->dev;
13345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13346
13347 if (WARN_ON(!obj))
13348 return;
13349
13350 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13351 !INTEL_INFO(dev)->cursor_needs_physical) {
13352 mutex_lock(&dev->struct_mutex);
82bc3b2d 13353 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR
13354 mutex_unlock(&dev->struct_mutex);
13355 }
465c120c
MR
13356}
13357
6156a456
CK
13358int
13359skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13360{
13361 int max_scale;
13362 struct drm_device *dev;
13363 struct drm_i915_private *dev_priv;
13364 int crtc_clock, cdclk;
13365
13366 if (!intel_crtc || !crtc_state)
13367 return DRM_PLANE_HELPER_NO_SCALING;
13368
13369 dev = intel_crtc->base.dev;
13370 dev_priv = dev->dev_private;
13371 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13372 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK
13373
13374 if (!crtc_clock || !cdclk)
13375 return DRM_PLANE_HELPER_NO_SCALING;
13376
13377 /*
13378 * skl max scale is lower of:
13379 * close to 3 but not 3, -1 is for that purpose
13380 * or
13381 * cdclk/crtc_clock
13382 */
13383 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13384
13385 return max_scale;
13386}
13387
465c120c 13388static int
3c692a41 13389intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13390 struct intel_crtc_state *crtc_state,
3c692a41
GP
13391 struct intel_plane_state *state)
13392{
2b875c22
MR
13393 struct drm_crtc *crtc = state->base.crtc;
13394 struct drm_framebuffer *fb = state->base.fb;
6156a456 13395 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML
13396 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13397 bool can_position = false;
465c120c 13398
061e4b8d
ML
13399 /* use scaler when colorkey is not required */
13400 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13401 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML
13402 min_scale = 1;
13403 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13404 can_position = true;
6156a456 13405 }
d8106366 13406
061e4b8d
ML
13407 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13408 &state->dst, &state->clip,
da20eabd
ML
13409 min_scale, max_scale,
13410 can_position, true,
13411 &state->visible);
14af293f
GP
13412}
13413
13414static void
13415intel_commit_primary_plane(struct drm_plane *plane,
13416 struct intel_plane_state *state)
13417{
2b875c22
MR
13418 struct drm_crtc *crtc = state->base.crtc;
13419 struct drm_framebuffer *fb = state->base.fb;
13420 struct drm_device *dev = plane->dev;
14af293f 13421 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13422 struct intel_crtc *intel_crtc;
14af293f
GP
13423 struct drm_rect *src = &state->src;
13424
ea2c67bb
MR
13425 crtc = crtc ? crtc : plane->crtc;
13426 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR
13427
13428 plane->fb = fb;
9dc806fc
MR
13429 crtc->x = src->x1 >> 16;
13430 crtc->y = src->y1 >> 16;
ccc759dc 13431
a539205a 13432 if (!crtc->state->active)
302d19ac 13433 return;
465c120c 13434
302d19ac
ML
13435 if (state->visible)
13436 /* FIXME: kill this fastboot hack */
13437 intel_update_pipe_size(intel_crtc);
13438
13439 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR
13440}
13441
a8ad0d8e
ML
13442static void
13443intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13444 struct drm_crtc *crtc)
a8ad0d8e
ML
13445{
13446 struct drm_device *dev = plane->dev;
13447 struct drm_i915_private *dev_priv = dev->dev_private;
13448
a8ad0d8e
ML
13449 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13450}
13451
613d2b27
ML
13452static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13453 struct drm_crtc_state *old_crtc_state)
3c692a41 13454{
32b7eeec 13455 struct drm_device *dev = crtc->dev;
3c692a41 13456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13457
f015c551 13458 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13459 intel_update_watermarks(crtc);
3c692a41 13460
c34c9ee4 13461 /* Perform vblank evasion around commit operation */
a539205a 13462 if (crtc->state->active)
34e0adbb 13463 intel_pipe_update_start(intel_crtc);
0583236e
ML
13464
13465 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13466 skl_detach_scalers(intel_crtc);
32b7eeec
MR
13467}
13468
613d2b27
ML
13469static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13470 struct drm_crtc_state *old_crtc_state)
32b7eeec 13471{
32b7eeec 13472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13473
8f539a83 13474 if (crtc->state->active)
34e0adbb 13475 intel_pipe_update_end(intel_crtc);
3c692a41
GP
13476}
13477
cf4c7c12 13478/**
4a3b8769
MR
13479 * intel_plane_destroy - destroy a plane
13480 * @plane: plane to destroy
cf4c7c12 13481 *
4a3b8769
MR
13482 * Common destruction function for all types of planes (primary, cursor,
13483 * sprite).
cf4c7c12 13484 */
4a3b8769 13485void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR
13486{
13487 struct intel_plane *intel_plane = to_intel_plane(plane);
13488 drm_plane_cleanup(plane);
13489 kfree(intel_plane);
13490}
13491
65a3fea0 13492const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR
13493 .update_plane = drm_atomic_helper_update_plane,
13494 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13495 .destroy = intel_plane_destroy,
c196e1d6 13496 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR
13497 .atomic_get_property = intel_plane_atomic_get_property,
13498 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR
13499 .atomic_duplicate_state = intel_plane_duplicate_state,
13500 .atomic_destroy_state = intel_plane_destroy_state,
13501
465c120c
MR
13502};
13503
13504static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13505 int pipe)
13506{
13507 struct intel_plane *primary;
8e7d688b 13508 struct intel_plane_state *state;
465c120c 13509 const uint32_t *intel_primary_formats;
45e3743a 13510 unsigned int num_formats;
465c120c
MR
13511
13512 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13513 if (primary == NULL)
13514 return NULL;
13515
8e7d688b
MR
13516 state = intel_create_plane_state(&primary->base);
13517 if (!state) {
ea2c67bb
MR
13518 kfree(primary);
13519 return NULL;
13520 }
8e7d688b 13521 primary->base.state = &state->base;
ea2c67bb 13522
465c120c
MR
13523 primary->can_scale = false;
13524 primary->max_downscale = 1;
6156a456
CK
13525 if (INTEL_INFO(dev)->gen >= 9) {
13526 primary->can_scale = true;
af99ceda 13527 state->scaler_id = -1;
6156a456 13528 }
465c120c
MR
13529 primary->pipe = pipe;
13530 primary->plane = pipe;
a9ff8714 13531 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR
13532 primary->check_plane = intel_check_primary_plane;
13533 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13534 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR
13535 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13536 primary->plane = !pipe;
13537
6c0fd451
DL
13538 if (INTEL_INFO(dev)->gen >= 9) {
13539 intel_primary_formats = skl_primary_formats;
13540 num_formats = ARRAY_SIZE(skl_primary_formats);
13541 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL
13542 intel_primary_formats = i965_primary_formats;
13543 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL
13544 } else {
13545 intel_primary_formats = i8xx_primary_formats;
13546 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR
13547 }
13548
13549 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13550 &intel_plane_funcs,
465c120c
MR
13551 intel_primary_formats, num_formats,
13552 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13553
3b7a5119
SJ
13554 if (INTEL_INFO(dev)->gen >= 4)
13555 intel_create_rotation_property(dev, primary);
48404c1e 13556
ea2c67bb
MR
13557 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13558
465c120c
MR
13559 return &primary->base;
13560}
13561
3b7a5119
SJ
13562void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13563{
13564 if (!dev->mode_config.rotation_property) {
13565 unsigned long flags = BIT(DRM_ROTATE_0) |
13566 BIT(DRM_ROTATE_180);
13567
13568 if (INTEL_INFO(dev)->gen >= 9)
13569 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13570
13571 dev->mode_config.rotation_property =
13572 drm_mode_create_rotation_property(dev, flags);
13573 }
13574 if (dev->mode_config.rotation_property)
13575 drm_object_attach_property(&plane->base.base,
13576 dev->mode_config.rotation_property,
13577 plane->base.state->rotation);
13578}
13579
3d7d6510 13580static int
852e787c 13581intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13582 struct intel_crtc_state *crtc_state,
852e787c 13583 struct intel_plane_state *state)
3d7d6510 13584{
061e4b8d 13585 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13586 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13587 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP
13588 unsigned stride;
13589 int ret;
3d7d6510 13590
061e4b8d
ML
13591 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13592 &state->dst, &state->clip,
3d7d6510
MR
13593 DRM_PLANE_HELPER_NO_SCALING,
13594 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13595 true, true, &state->visible);
757f9a3e
GP
13596 if (ret)
13597 return ret;
13598
757f9a3e
GP
13599 /* if we want to turn off the cursor ignore width and height */
13600 if (!obj)
da20eabd 13601 return 0;
757f9a3e 13602
757f9a3e 13603 /* Check for which cursor types we support */
061e4b8d 13604 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR
13605 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13606 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP
13607 return -EINVAL;
13608 }
13609
ea2c67bb
MR
13610 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13611 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP
13612 DRM_DEBUG_KMS("buffer is too small\n");
13613 return -ENOMEM;
13614 }
13615
3a656b54 13616 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13617 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13618 return -EINVAL;
32b7eeec
MR
13619 }
13620
da20eabd 13621 return 0;
852e787c 13622}
3d7d6510 13623
a8ad0d8e
ML
13624static void
13625intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13626 struct drm_crtc *crtc)
a8ad0d8e 13627{
a8ad0d8e
ML
13628 intel_crtc_update_cursor(crtc, false);
13629}
13630
f4a2cf29 13631static void
852e787c
GP
13632intel_commit_cursor_plane(struct drm_plane *plane,
13633 struct intel_plane_state *state)
13634{
2b875c22 13635 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR
13636 struct drm_device *dev = plane->dev;
13637 struct intel_crtc *intel_crtc;
2b875c22 13638 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13639 uint32_t addr;
852e787c 13640
ea2c67bb
MR
13641 crtc = crtc ? crtc : plane->crtc;
13642 intel_crtc = to_intel_crtc(crtc);
13643
2b875c22 13644 plane->fb = state->base.fb;
ea2c67bb
MR
13645 crtc->cursor_x = state->base.crtc_x;
13646 crtc->cursor_y = state->base.crtc_y;
13647
a912f12f
GP
13648 if (intel_crtc->cursor_bo == obj)
13649 goto update;
4ed91096 13650
f4a2cf29 13651 if (!obj)
a912f12f 13652 addr = 0;
f4a2cf29 13653 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13654 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13655 else
a912f12f 13656 addr = obj->phys_handle->busaddr;
852e787c 13657
a912f12f
GP
13658 intel_crtc->cursor_addr = addr;
13659 intel_crtc->cursor_bo = obj;
852e787c 13660
302d19ac 13661update:
a539205a 13662 if (crtc->state->active)
a912f12f 13663 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP
13664}
13665
3d7d6510
MR
13666static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13667 int pipe)
13668{
13669 struct intel_plane *cursor;
8e7d688b 13670 struct intel_plane_state *state;
3d7d6510
MR
13671
13672 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13673 if (cursor == NULL)
13674 return NULL;
13675
8e7d688b
MR
13676 state = intel_create_plane_state(&cursor->base);
13677 if (!state) {
ea2c67bb
MR
13678 kfree(cursor);
13679 return NULL;
13680 }
8e7d688b 13681 cursor->base.state = &state->base;
ea2c67bb 13682
3d7d6510
MR
13683 cursor->can_scale = false;
13684 cursor->max_downscale = 1;
13685 cursor->pipe = pipe;
13686 cursor->plane = pipe;
a9ff8714 13687 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR
13688 cursor->check_plane = intel_check_cursor_plane;
13689 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13690 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR
13691
13692 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13693 &intel_plane_funcs,
3d7d6510
MR
13694 intel_cursor_formats,
13695 ARRAY_SIZE(intel_cursor_formats),
13696 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS
13697
13698 if (INTEL_INFO(dev)->gen >= 4) {
13699 if (!dev->mode_config.rotation_property)
13700 dev->mode_config.rotation_property =
13701 drm_mode_create_rotation_property(dev,
13702 BIT(DRM_ROTATE_0) |
13703 BIT(DRM_ROTATE_180));
13704 if (dev->mode_config.rotation_property)
13705 drm_object_attach_property(&cursor->base.base,
13706 dev->mode_config.rotation_property,
8e7d688b 13707 state->base.rotation);
4398ad45
VS
13708 }
13709
af99ceda
CK
13710 if (INTEL_INFO(dev)->gen >=9)
13711 state->scaler_id = -1;
13712
ea2c67bb
MR
13713 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13714
3d7d6510
MR
13715 return &cursor->base;
13716}
13717
549e2bfb
CK
13718static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13719 struct intel_crtc_state *crtc_state)
13720{
13721 int i;
13722 struct intel_scaler *intel_scaler;
13723 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13724
13725 for (i = 0; i < intel_crtc->num_scalers; i++) {
13726 intel_scaler = &scaler_state->scalers[i];
13727 intel_scaler->in_use = 0;
549e2bfb
CK
13728 intel_scaler->mode = PS_SCALER_MODE_DYN;
13729 }
13730
13731 scaler_state->scaler_id = -1;
13732}
13733
b358d0a6 13734static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13735{
fbee40df 13736 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13737 struct intel_crtc *intel_crtc;
f5de6e07 13738 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR
13739 struct drm_plane *primary = NULL;
13740 struct drm_plane *cursor = NULL;
465c120c 13741 int i, ret;
79e53945 13742
955382f3 13743 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB
13744 if (intel_crtc == NULL)
13745 return;
13746
f5de6e07
ACO
13747 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13748 if (!crtc_state)
13749 goto fail;
550acefd
ACO
13750 intel_crtc->config = crtc_state;
13751 intel_crtc->base.state = &crtc_state->base;
07878248 13752 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13753
549e2bfb
CK
13754 /* initialize shared scalers */
13755 if (INTEL_INFO(dev)->gen >= 9) {
13756 if (pipe == PIPE_C)
13757 intel_crtc->num_scalers = 1;
13758 else
13759 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13760
13761 skl_init_scalers(dev, intel_crtc, crtc_state);
13762 }
13763
465c120c 13764 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR
13765 if (!primary)
13766 goto fail;
13767
13768 cursor = intel_cursor_plane_create(dev, pipe);
13769 if (!cursor)
13770 goto fail;
13771
465c120c 13772 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR
13773 cursor, &intel_crtc_funcs);
13774 if (ret)
13775 goto fail;
79e53945
JB
13776
13777 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB
13778 for (i = 0; i < 256; i++) {
13779 intel_crtc->lut_r[i] = i;
13780 intel_crtc->lut_g[i] = i;
13781 intel_crtc->lut_b[i] = i;
13782 }
13783
1f1c2e24
VS
13784 /*
13785 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13786 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13787 */
80824003
JB
13788 intel_crtc->pipe = pipe;
13789 intel_crtc->plane = pipe;
3a77c4c4 13790 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13791 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13792 intel_crtc->plane = !pipe;
80824003
JB
13793 }
13794
4b0e333e
CW
13795 intel_crtc->cursor_base = ~0;
13796 intel_crtc->cursor_cntl = ~0;
dc41c154 13797 intel_crtc->cursor_size = ~0;
8d7849db 13798
852eb00d
VS
13799 intel_crtc->wm.cxsr_allowed = true;
13800
22fd0fab
JB
13801 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13802 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13803 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13804 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13805
79e53945 13806 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV
13807
13808 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR
13809 return;
13810
13811fail:
13812 if (primary)
13813 drm_plane_cleanup(primary);
13814 if (cursor)
13815 drm_plane_cleanup(cursor);
f5de6e07 13816 kfree(crtc_state);
3d7d6510 13817 kfree(intel_crtc);
79e53945
JB
13818}
13819
752aa88a
JB
13820enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13821{
13822 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13823 struct drm_device *dev = connector->base.dev;
752aa88a 13824
51fd371b 13825 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13826
d3babd3f 13827 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB
13828 return INVALID_PIPE;
13829
13830 return to_intel_crtc(encoder->crtc)->pipe;
13831}
13832
08d7b3d1 13833int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13834 struct drm_file *file)
08d7b3d1 13835{
08d7b3d1 13836 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13837 struct drm_crtc *drmmode_crtc;
c05422d5 13838 struct intel_crtc *crtc;
08d7b3d1 13839
7707e653 13840 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13841
7707e653 13842 if (!drmmode_crtc) {
08d7b3d1 13843 DRM_ERROR("no such CRTC id\n");
3f2c2057 13844 return -ENOENT;
08d7b3d1
CW
13845 }
13846
7707e653 13847 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13848 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13849
c05422d5 13850 return 0;
08d7b3d1
CW
13851}
13852
66a9278e 13853static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13854{
66a9278e
DV
13855 struct drm_device *dev = encoder->base.dev;
13856 struct intel_encoder *source_encoder;
79e53945 13857 int index_mask = 0;
79e53945
JB
13858 int entry = 0;
13859
b2784e15 13860 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13861 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV
13862 index_mask |= (1 << entry);
13863
79e53945
JB
13864 entry++;
13865 }
4ef69c7a 13866
79e53945
JB
13867 return index_mask;
13868}
13869
4d302442
CW
13870static bool has_edp_a(struct drm_device *dev)
13871{
13872 struct drm_i915_private *dev_priv = dev->dev_private;
13873
13874 if (!IS_MOBILE(dev))
13875 return false;
13876
13877 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13878 return false;
13879
e3589908 13880 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW
13881 return false;
13882
13883 return true;
13884}
13885
84b4e042
JB
13886static bool intel_crt_present(struct drm_device *dev)
13887{
13888 struct drm_i915_private *dev_priv = dev->dev_private;
13889
884497ed
DL
13890 if (INTEL_INFO(dev)->gen >= 9)
13891 return false;
13892
cf404ce4 13893 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB
13894 return false;
13895
13896 if (IS_CHERRYVIEW(dev))
13897 return false;
13898
13899 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13900 return false;
13901
13902 return true;
13903}
13904
79e53945
JB
13905static void intel_setup_outputs(struct drm_device *dev)
13906{
725e30ad 13907 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13908 struct intel_encoder *encoder;
cb0953d7 13909 bool dpd_is_edp = false;
79e53945 13910
c9093354 13911 intel_lvds_init(dev);
79e53945 13912
84b4e042 13913 if (intel_crt_present(dev))
79935fca 13914 intel_crt_init(dev);
cb0953d7 13915
c776eb2e
VK
13916 if (IS_BROXTON(dev)) {
13917 /*
13918 * FIXME: Broxton doesn't support port detection via the
13919 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13920 * detect the ports.
13921 */
13922 intel_ddi_init(dev, PORT_A);
13923 intel_ddi_init(dev, PORT_B);
13924 intel_ddi_init(dev, PORT_C);
13925 } else if (HAS_DDI(dev)) {
0e72a5b5
ED
13926 int found;
13927
de31facd
JB
13928 /*
13929 * Haswell uses DDI functions to detect digital outputs.
13930 * On SKL pre-D0 the strap isn't connected, so we assume
13931 * it's there.
13932 */
0e72a5b5 13933 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13934 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13935 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED
13936 intel_ddi_init(dev, PORT_A);
13937
13938 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13939 * register */
13940 found = I915_READ(SFUSE_STRAP);
13941
13942 if (found & SFUSE_STRAP_DDIB_DETECTED)
13943 intel_ddi_init(dev, PORT_B);
13944 if (found & SFUSE_STRAP_DDIC_DETECTED)
13945 intel_ddi_init(dev, PORT_C);
13946 if (found & SFUSE_STRAP_DDID_DETECTED)
13947 intel_ddi_init(dev, PORT_D);
2800e4c2
RV
13948 /*
13949 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13950 */
13951 if (IS_SKYLAKE(dev) &&
13952 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13953 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13954 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13955 intel_ddi_init(dev, PORT_E);
13956
0e72a5b5 13957 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13958 int found;
5d8a7752 13959 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV
13960
13961 if (has_edp_a(dev))
13962 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13963
dc0fa718 13964 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13965 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13966 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13967 if (!found)
e2debe91 13968 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13969 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13970 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW
13971 }
13972
dc0fa718 13973 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13974 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13975
dc0fa718 13976 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13977 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13978
5eb08b69 13979 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13980 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13981
270b3042 13982 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13983 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13984 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS
13985 /*
13986 * The DP_DETECTED bit is the latched state of the DDC
13987 * SDA pin at boot. However since eDP doesn't require DDC
13988 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13989 * eDP ports may have been muxed to an alternate function.
13990 * Thus we can't rely on the DP_DETECTED bit alone to detect
13991 * eDP ports. Consult the VBT as well as DP_DETECTED to
13992 * detect eDP ports.
13993 */
d2182a66
VS
13994 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13995 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB
13996 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13997 PORT_B);
e17ac6db
VS
13998 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13999 intel_dp_is_edp(dev, PORT_B))
14000 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14001
d2182a66
VS
14002 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14003 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB
14004 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14005 PORT_C);
e17ac6db
VS
14006 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14007 intel_dp_is_edp(dev, PORT_C))
14008 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14009
9418c1f1 14010 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14011 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS
14012 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14013 PORT_D);
e17ac6db
VS
14014 /* eDP not supported on port D, so don't check VBT */
14015 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14016 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS
14017 }
14018
3cfca973 14019 intel_dsi_init(dev);
09da55dc 14020 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14021 bool found = false;
7d57382e 14022
e2debe91 14023 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14024 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14025 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14026 if (!found && IS_G4X(dev)) {
b01f2c3a 14027 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14028 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14029 }
27185ae1 14030
3fec3d2f 14031 if (!found && IS_G4X(dev))
ab9d7c30 14032 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14033 }
13520b05
KH
14034
14035 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14036
e2debe91 14037 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14038 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14039 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14040 }
27185ae1 14041
e2debe91 14042 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14043
3fec3d2f 14044 if (IS_G4X(dev)) {
b01f2c3a 14045 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14046 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14047 }
3fec3d2f 14048 if (IS_G4X(dev))
ab9d7c30 14049 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14050 }
27185ae1 14051
3fec3d2f 14052 if (IS_G4X(dev) &&
e7281eab 14053 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14054 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14055 } else if (IS_GEN2(dev))
79e53945
JB
14056 intel_dvo_init(dev);
14057
103a196f 14058 if (SUPPORTS_TV(dev))
79e53945
JB
14059 intel_tv_init(dev);
14060
0bc12bcb 14061 intel_psr_init(dev);
7c8f8a70 14062
b2784e15 14063 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW
14064 encoder->base.possible_crtcs = encoder->crtc_mask;
14065 encoder->base.possible_clones =
66a9278e 14066 intel_encoder_clones(encoder);
79e53945 14067 }
47356eb6 14068
dde86e2d 14069 intel_init_pch_refclk(dev);
270b3042
DV
14070
14071 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB
14072}
14073
14074static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14075{
60a5ca01 14076 struct drm_device *dev = fb->dev;
79e53945 14077 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14078
ef2d633e 14079 drm_framebuffer_cleanup(fb);
60a5ca01 14080 mutex_lock(&dev->struct_mutex);
ef2d633e 14081 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS
14082 drm_gem_object_unreference(&intel_fb->obj->base);
14083 mutex_unlock(&dev->struct_mutex);
79e53945
JB
14084 kfree(intel_fb);
14085}
14086
14087static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14088 struct drm_file *file,
79e53945
JB
14089 unsigned int *handle)
14090{
14091 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14092 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14093
05394f39 14094 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB
14095}
14096
86c98588
RV
14097static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14098 struct drm_file *file,
14099 unsigned flags, unsigned color,
14100 struct drm_clip_rect *clips,
14101 unsigned num_clips)
14102{
14103 struct drm_device *dev = fb->dev;
14104 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14105 struct drm_i915_gem_object *obj = intel_fb->obj;
14106
14107 mutex_lock(&dev->struct_mutex);
74b4ea1e 14108 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV
14109 mutex_unlock(&dev->struct_mutex);
14110
14111 return 0;
14112}
14113
79e53945
JB
14114static const struct drm_framebuffer_funcs intel_fb_funcs = {
14115 .destroy = intel_user_framebuffer_destroy,
14116 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14117 .dirty = intel_user_framebuffer_dirty,
79e53945
JB
14118};
14119
b321803d
DL
14120static
14121u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14122 uint32_t pixel_format)
14123{
14124 u32 gen = INTEL_INFO(dev)->gen;
14125
14126 if (gen >= 9) {
14127 /* "The stride in bytes must not exceed the of the size of 8K
14128 * pixels and 32K bytes."
14129 */
14130 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14131 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14132 return 32*1024;
14133 } else if (gen >= 4) {
14134 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14135 return 16*1024;
14136 else
14137 return 32*1024;
14138 } else if (gen >= 3) {
14139 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14140 return 8*1024;
14141 else
14142 return 16*1024;
14143 } else {
14144 /* XXX DSPC is limited to 4k tiled */
14145 return 8*1024;
14146 }
14147}
14148
b5ea642a
DV
14149static int intel_framebuffer_init(struct drm_device *dev,
14150 struct intel_framebuffer *intel_fb,
14151 struct drm_mode_fb_cmd2 *mode_cmd,
14152 struct drm_i915_gem_object *obj)
79e53945 14153{
6761dd31 14154 unsigned int aligned_height;
79e53945 14155 int ret;
b321803d 14156 u32 pitch_limit, stride_alignment;
79e53945 14157
dd4916c5
DV
14158 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14159
2a80eada
DV
14160 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14161 /* Enforce that fb modifier and tiling mode match, but only for
14162 * X-tiled. This is needed for FBC. */
14163 if (!!(obj->tiling_mode == I915_TILING_X) !=
14164 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14165 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14166 return -EINVAL;
14167 }
14168 } else {
14169 if (obj->tiling_mode == I915_TILING_X)
14170 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14171 else if (obj->tiling_mode == I915_TILING_Y) {
14172 DRM_DEBUG("No Y tiling for legacy addfb\n");
14173 return -EINVAL;
14174 }
14175 }
14176
9a8f0a12
TU
14177 /* Passed in modifier sanity checking. */
14178 switch (mode_cmd->modifier[0]) {
14179 case I915_FORMAT_MOD_Y_TILED:
14180 case I915_FORMAT_MOD_Yf_TILED:
14181 if (INTEL_INFO(dev)->gen < 9) {
14182 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14183 mode_cmd->modifier[0]);
14184 return -EINVAL;
14185 }
14186 case DRM_FORMAT_MOD_NONE:
14187 case I915_FORMAT_MOD_X_TILED:
14188 break;
14189 default:
c0f40428
JB
14190 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14191 mode_cmd->modifier[0]);
57cd6508 14192 return -EINVAL;
c16ed4be 14193 }
57cd6508 14194
b321803d
DL
14195 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14196 mode_cmd->pixel_format);
14197 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14198 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14199 mode_cmd->pitches[0], stride_alignment);
57cd6508 14200 return -EINVAL;
c16ed4be 14201 }
57cd6508 14202
b321803d
DL
14203 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14204 mode_cmd->pixel_format);
a35cdaa0 14205 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL
14206 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14207 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14208 "tiled" : "linear",
a35cdaa0 14209 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14210 return -EINVAL;
c16ed4be 14211 }
5d7bd705 14212
2a80eada 14213 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW
14214 mode_cmd->pitches[0] != obj->stride) {
14215 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14216 mode_cmd->pitches[0], obj->stride);
5d7bd705 14217 return -EINVAL;
c16ed4be 14218 }
5d7bd705 14219
57779d06 14220 /* Reject formats not supported by any plane early. */
308e5bcb 14221 switch (mode_cmd->pixel_format) {
57779d06 14222 case DRM_FORMAT_C8:
04b3924d
VS
14223 case DRM_FORMAT_RGB565:
14224 case DRM_FORMAT_XRGB8888:
14225 case DRM_FORMAT_ARGB8888:
57779d06
VS
14226 break;
14227 case DRM_FORMAT_XRGB1555:
c16ed4be 14228 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS
14229 DRM_DEBUG("unsupported pixel format: %s\n",
14230 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14231 return -EINVAL;
c16ed4be 14232 }
57779d06 14233 break;
57779d06 14234 case DRM_FORMAT_ABGR8888:
6c0fd451
DL
14235 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14236 DRM_DEBUG("unsupported pixel format: %s\n",
14237 drm_get_format_name(mode_cmd->pixel_format));
14238 return -EINVAL;
14239 }
14240 break;
14241 case DRM_FORMAT_XBGR8888:
04b3924d 14242 case DRM_FORMAT_XRGB2101010:
57779d06 14243 case DRM_FORMAT_XBGR2101010:
c16ed4be 14244 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS
14245 DRM_DEBUG("unsupported pixel format: %s\n",
14246 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14247 return -EINVAL;
c16ed4be 14248 }
b5626747 14249 break;
7531208b
DL
14250 case DRM_FORMAT_ABGR2101010:
14251 if (!IS_VALLEYVIEW(dev)) {
14252 DRM_DEBUG("unsupported pixel format: %s\n",
14253 drm_get_format_name(mode_cmd->pixel_format));
14254 return -EINVAL;
14255 }
14256 break;
04b3924d
VS
14257 case DRM_FORMAT_YUYV:
14258 case DRM_FORMAT_UYVY:
14259 case DRM_FORMAT_YVYU:
14260 case DRM_FORMAT_VYUY:
c16ed4be 14261 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS
14262 DRM_DEBUG("unsupported pixel format: %s\n",
14263 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14264 return -EINVAL;
c16ed4be 14265 }
57cd6508
CW
14266 break;
14267 default:
4ee62c76
VS
14268 DRM_DEBUG("unsupported pixel format: %s\n",
14269 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW
14270 return -EINVAL;
14271 }
14272
90f9a336
VS
14273 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14274 if (mode_cmd->offsets[0] != 0)
14275 return -EINVAL;
14276
ec2c981e 14277 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV
14278 mode_cmd->pixel_format,
14279 mode_cmd->modifier[0]);
53155c0a
DV
14280 /* FIXME drm helper for size checks (especially planar formats)? */
14281 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14282 return -EINVAL;
14283
c7d73f6a
DV
14284 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14285 intel_fb->obj = obj;
80075d49 14286 intel_fb->obj->framebuffer_references++;
c7d73f6a 14287
79e53945
JB
14288 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14289 if (ret) {
14290 DRM_ERROR("framebuffer init failed %d\n", ret);
14291 return ret;
14292 }
14293
79e53945
JB
14294 return 0;
14295}
14296
79e53945
JB
14297static struct drm_framebuffer *
14298intel_user_framebuffer_create(struct drm_device *dev,
14299 struct drm_file *filp,
308e5bcb 14300 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14301{
05394f39 14302 struct drm_i915_gem_object *obj;
79e53945 14303
308e5bcb
JB
14304 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14305 mode_cmd->handles[0]));
c8725226 14306 if (&obj->base == NULL)
cce13ff7 14307 return ERR_PTR(-ENOENT);
79e53945 14308
d2dff872 14309 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB
14310}
14311
0695726e 14312#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14313static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV
14314{
14315}
14316#endif
14317
79e53945 14318static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14319 .fb_create = intel_user_framebuffer_create,
0632fef6 14320 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR
14321 .atomic_check = intel_atomic_check,
14322 .atomic_commit = intel_atomic_commit,
de419ab6
ML
14323 .atomic_state_alloc = intel_atomic_state_alloc,
14324 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB
14325};
14326
e70236a8
JB
14327/* Set up chip specific display functions */
14328static void intel_init_display(struct drm_device *dev)
14329{
14330 struct drm_i915_private *dev_priv = dev->dev_private;
14331
ee9300bb
DV
14332 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14333 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML
14334 else if (IS_CHERRYVIEW(dev))
14335 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV
14336 else if (IS_VALLEYVIEW(dev))
14337 dev_priv->display.find_dpll = vlv_find_best_dpll;
14338 else if (IS_PINEVIEW(dev))
14339 dev_priv->display.find_dpll = pnv_find_best_dpll;
14340 else
14341 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14342
bc8d7dff
DL
14343 if (INTEL_INFO(dev)->gen >= 9) {
14344 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
14345 dev_priv->display.get_initial_plane_config =
14346 skylake_get_initial_plane_config;
bc8d7dff
DL
14347 dev_priv->display.crtc_compute_clock =
14348 haswell_crtc_compute_clock;
14349 dev_priv->display.crtc_enable = haswell_crtc_enable;
14350 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL
14351 dev_priv->display.update_primary_plane =
14352 skylake_update_primary_plane;
14353 } else if (HAS_DDI(dev)) {
0e8ffe1b 14354 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
14355 dev_priv->display.get_initial_plane_config =
14356 ironlake_get_initial_plane_config;
797d0259
ACO
14357 dev_priv->display.crtc_compute_clock =
14358 haswell_crtc_compute_clock;
4f771f10
PZ
14359 dev_priv->display.crtc_enable = haswell_crtc_enable;
14360 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL
14361 dev_priv->display.update_primary_plane =
14362 ironlake_update_primary_plane;
09b4ddf9 14363 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14364 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL
14365 dev_priv->display.get_initial_plane_config =
14366 ironlake_get_initial_plane_config;
3fb37703
ACO
14367 dev_priv->display.crtc_compute_clock =
14368 ironlake_crtc_compute_clock;
76e5a89c
DV
14369 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14370 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR
14371 dev_priv->display.update_primary_plane =
14372 ironlake_update_primary_plane;
89b667f8
JB
14373 } else if (IS_VALLEYVIEW(dev)) {
14374 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
14375 dev_priv->display.get_initial_plane_config =
14376 i9xx_get_initial_plane_config;
d6dfee7a 14377 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB
14378 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14379 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR
14380 dev_priv->display.update_primary_plane =
14381 i9xx_update_primary_plane;
f564048e 14382 } else {
0e8ffe1b 14383 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
14384 dev_priv->display.get_initial_plane_config =
14385 i9xx_get_initial_plane_config;
d6dfee7a 14386 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV
14387 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14388 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR
14389 dev_priv->display.update_primary_plane =
14390 i9xx_update_primary_plane;
f564048e 14391 }
e70236a8 14392
e70236a8 14393 /* Returns the core display clock speed */
1652d19e
VS
14394 if (IS_SKYLAKE(dev))
14395 dev_priv->display.get_display_clock_speed =
14396 skylake_get_display_clock_speed;
acd3f3d3
BP
14397 else if (IS_BROXTON(dev))
14398 dev_priv->display.get_display_clock_speed =
14399 broxton_get_display_clock_speed;
1652d19e
VS
14400 else if (IS_BROADWELL(dev))
14401 dev_priv->display.get_display_clock_speed =
14402 broadwell_get_display_clock_speed;
14403 else if (IS_HASWELL(dev))
14404 dev_priv->display.get_display_clock_speed =
14405 haswell_get_display_clock_speed;
14406 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB
14407 dev_priv->display.get_display_clock_speed =
14408 valleyview_get_display_clock_speed;
b37a6434
VS
14409 else if (IS_GEN5(dev))
14410 dev_priv->display.get_display_clock_speed =
14411 ilk_get_display_clock_speed;
a7c66cd8 14412 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14413 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB
14414 dev_priv->display.get_display_clock_speed =
14415 i945_get_display_clock_speed;
34edce2f
VS
14416 else if (IS_GM45(dev))
14417 dev_priv->display.get_display_clock_speed =
14418 gm45_get_display_clock_speed;
14419 else if (IS_CRESTLINE(dev))
14420 dev_priv->display.get_display_clock_speed =
14421 i965gm_get_display_clock_speed;
14422 else if (IS_PINEVIEW(dev))
14423 dev_priv->display.get_display_clock_speed =
14424 pnv_get_display_clock_speed;
14425 else if (IS_G33(dev) || IS_G4X(dev))
14426 dev_priv->display.get_display_clock_speed =
14427 g33_get_display_clock_speed;
e70236a8
JB
14428 else if (IS_I915G(dev))
14429 dev_priv->display.get_display_clock_speed =
14430 i915_get_display_clock_speed;
257a7ffc 14431 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB
14432 dev_priv->display.get_display_clock_speed =
14433 i9xx_misc_get_display_clock_speed;
257a7ffc
DV
14434 else if (IS_PINEVIEW(dev))
14435 dev_priv->display.get_display_clock_speed =
14436 pnv_get_display_clock_speed;
e70236a8
JB
14437 else if (IS_I915GM(dev))
14438 dev_priv->display.get_display_clock_speed =
14439 i915gm_get_display_clock_speed;
14440 else if (IS_I865G(dev))
14441 dev_priv->display.get_display_clock_speed =
14442 i865_get_display_clock_speed;
f0f8a9ce 14443 else if (IS_I85X(dev))
e70236a8 14444 dev_priv->display.get_display_clock_speed =
1b1d2716 14445 i85x_get_display_clock_speed;
623e01e5
VS
14446 else { /* 830 */
14447 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB
14448 dev_priv->display.get_display_clock_speed =
14449 i830_get_display_clock_speed;
623e01e5 14450 }
e70236a8 14451
7c10a2b5 14452 if (IS_GEN5(dev)) {
3bb11b53 14453 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ
14454 } else if (IS_GEN6(dev)) {
14455 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ
14456 } else if (IS_IVYBRIDGE(dev)) {
14457 /* FIXME: detect B0+ stepping and use auto training */
14458 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14459 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14460 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML
14461 if (IS_BROADWELL(dev)) {
14462 dev_priv->display.modeset_commit_cdclk =
14463 broadwell_modeset_commit_cdclk;
14464 dev_priv->display.modeset_calc_cdclk =
14465 broadwell_modeset_calc_cdclk;
14466 }
30a970c6 14467 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML
14468 dev_priv->display.modeset_commit_cdclk =
14469 valleyview_modeset_commit_cdclk;
14470 dev_priv->display.modeset_calc_cdclk =
14471 valleyview_modeset_calc_cdclk;
f8437dd1 14472 } else if (IS_BROXTON(dev)) {
27c329ed
ML
14473 dev_priv->display.modeset_commit_cdclk =
14474 broxton_modeset_commit_cdclk;
14475 dev_priv->display.modeset_calc_cdclk =
14476 broxton_modeset_calc_cdclk;
e70236a8 14477 }
8c9f3aaf 14478
8c9f3aaf
JB
14479 switch (INTEL_INFO(dev)->gen) {
14480 case 2:
14481 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14482 break;
14483
14484 case 3:
14485 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14486 break;
14487
14488 case 4:
14489 case 5:
14490 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14491 break;
14492
14493 case 6:
14494 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14495 break;
7c9017e5 14496 case 7:
4e0bbc31 14497 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB
14498 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14499 break;
830c81db 14500 case 9:
ba343e02
TU
14501 /* Drop through - unsupported since execlist only. */
14502 default:
14503 /* Default just returns -ENODEV to indicate unsupported */
14504 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14505 }
7bd688cd
JN
14506
14507 intel_panel_init_backlight_funcs(dev);
e39b999a
VS
14508
14509 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB
14510}
14511
b690e96c
JB
14512/*
14513 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14514 * resume, or other times. This quirk makes sure that's the case for
14515 * affected systems.
14516 */
0206e353 14517static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB
14518{
14519 struct drm_i915_private *dev_priv = dev->dev_private;
14520
14521 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14522 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB
14523}
14524
b6b5d049
VS
14525static void quirk_pipeb_force(struct drm_device *dev)
14526{
14527 struct drm_i915_private *dev_priv = dev->dev_private;
14528
14529 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14530 DRM_INFO("applying pipe b force quirk\n");
14531}
14532
435793df
KP
14533/*
14534 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14535 */
14536static void quirk_ssc_force_disable(struct drm_device *dev)
14537{
14538 struct drm_i915_private *dev_priv = dev->dev_private;
14539 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14540 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP
14541}
14542
4dca20ef 14543/*
5a15ab5b
CE
14544 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14545 * brightness value
4dca20ef
CE
14546 */
14547static void quirk_invert_brightness(struct drm_device *dev)
14548{
14549 struct drm_i915_private *dev_priv = dev->dev_private;
14550 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14551 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP
14552}
14553
9c72cc6f
SD
14554/* Some VBT's incorrectly indicate no backlight is present */
14555static void quirk_backlight_present(struct drm_device *dev)
14556{
14557 struct drm_i915_private *dev_priv = dev->dev_private;
14558 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14559 DRM_INFO("applying backlight present quirk\n");
14560}
14561
b690e96c
JB
14562struct intel_quirk {
14563 int device;
14564 int subsystem_vendor;
14565 int subsystem_device;
14566 void (*hook)(struct drm_device *dev);
14567};
14568
5f85f176
EE
14569/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14570struct intel_dmi_quirk {
14571 void (*hook)(struct drm_device *dev);
14572 const struct dmi_system_id (*dmi_id_list)[];
14573};
14574
14575static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14576{
14577 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14578 return 1;
14579}
14580
14581static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14582 {
14583 .dmi_id_list = &(const struct dmi_system_id[]) {
14584 {
14585 .callback = intel_dmi_reverse_brightness,
14586 .ident = "NCR Corporation",
14587 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14588 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14589 },
14590 },
14591 { } /* terminating entry */
14592 },
14593 .hook = quirk_invert_brightness,
14594 },
14595};
14596
c43b5634 14597static struct intel_quirk intel_quirks[] = {
b690e96c
JB
14598 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14599 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14600
b690e96c
JB
14601 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14602 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14603
5f080c0f
VS
14604 /* 830 needs to leave pipe A & dpll A up */
14605 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14606
b6b5d049
VS
14607 /* 830 needs to leave pipe B & dpll B up */
14608 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14609
435793df
KP
14610 /* Lenovo U160 cannot use SSC on LVDS */
14611 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS
14612
14613 /* Sony Vaio Y cannot use SSC on LVDS */
14614 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14615
be505f64
AH
14616 /* Acer Aspire 5734Z must invert backlight brightness */
14617 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14618
14619 /* Acer/eMachines G725 */
14620 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14621
14622 /* Acer/eMachines e725 */
14623 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14624
14625 /* Acer/Packard Bell NCL20 */
14626 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14627
14628 /* Acer Aspire 4736Z */
14629 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN
14630
14631 /* Acer Aspire 5336 */
14632 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD
14633
14634 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14635 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14636
dfb3d47b
SD
14637 /* Acer C720 Chromebook (Core i3 4005U) */
14638 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14639
b2a9601c 14640 /* Apple Macbook 2,1 (Core 2 T7400) */
14641 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14642
d4967d8c
SD
14643 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14644 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD
14645
14646 /* HP Chromebook 14 (Celeron 2955U) */
14647 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN
14648
14649 /* Dell Chromebook 11 */
14650 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB
14651};
14652
14653static void intel_init_quirks(struct drm_device *dev)
14654{
14655 struct pci_dev *d = dev->pdev;
14656 int i;
14657
14658 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14659 struct intel_quirk *q = &intel_quirks[i];
14660
14661 if (d->device == q->device &&
14662 (d->subsystem_vendor == q->subsystem_vendor ||
14663 q->subsystem_vendor == PCI_ANY_ID) &&
14664 (d->subsystem_device == q->subsystem_device ||
14665 q->subsystem_device == PCI_ANY_ID))
14666 q->hook(dev);
14667 }
5f85f176
EE
14668 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14669 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14670 intel_dmi_quirks[i].hook(dev);
14671 }
b690e96c
JB
14672}
14673
9cce37f4
JB
14674/* Disable the VGA plane that we never use */
14675static void i915_disable_vga(struct drm_device *dev)
14676{
14677 struct drm_i915_private *dev_priv = dev->dev_private;
14678 u8 sr1;
766aa1c4 14679 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14680
2b37c616 14681 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14682 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14683 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB
14684 sr1 = inb(VGA_SR_DATA);
14685 outb(sr1 | 1<<5, VGA_SR_DATA);
14686 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14687 udelay(300);
14688
01f5a626 14689 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB
14690 POSTING_READ(vga_reg);
14691}
14692
f817586c
DV
14693void intel_modeset_init_hw(struct drm_device *dev)
14694{
b6283055 14695 intel_update_cdclk(dev);
a8f78b58 14696 intel_prepare_ddi(dev);
f817586c 14697 intel_init_clock_gating(dev);
8090c6b9 14698 intel_enable_gt_powersave(dev);
f817586c
DV
14699}
14700
79e53945
JB
14701void intel_modeset_init(struct drm_device *dev)
14702{
652c393a 14703 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14704 int sprite, ret;
8cc87b75 14705 enum pipe pipe;
46f297fb 14706 struct intel_crtc *crtc;
79e53945
JB
14707
14708 drm_mode_config_init(dev);
14709
14710 dev->mode_config.min_width = 0;
14711 dev->mode_config.min_height = 0;
14712
019d96cb
DA
14713 dev->mode_config.preferred_depth = 24;
14714 dev->mode_config.prefer_shadow = 1;
14715
25bab385
TU
14716 dev->mode_config.allow_fb_modifiers = true;
14717
e6ecefaa 14718 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14719
b690e96c
JB
14720 intel_init_quirks(dev);
14721
1fa61106
ED
14722 intel_init_pm(dev);
14723
e3c74757
BW
14724 if (INTEL_INFO(dev)->num_pipes == 0)
14725 return;
14726
69f92f67
LW
14727 /*
14728 * There may be no VBT; and if the BIOS enabled SSC we can
14729 * just keep using it to avoid unnecessary flicker. Whereas if the
14730 * BIOS isn't using it, don't assume it will work even if the VBT
14731 * indicates as much.
14732 */
14733 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14734 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14735 DREF_SSC1_ENABLE);
14736
14737 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14738 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14739 bios_lvds_use_ssc ? "en" : "dis",
14740 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14741 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14742 }
14743 }
14744
e70236a8 14745 intel_init_display(dev);
7c10a2b5 14746 intel_init_audio(dev);
e70236a8 14747
a6c45cf0
CW
14748 if (IS_GEN2(dev)) {
14749 dev->mode_config.max_width = 2048;
14750 dev->mode_config.max_height = 2048;
14751 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP
14752 dev->mode_config.max_width = 4096;
14753 dev->mode_config.max_height = 4096;
79e53945 14754 } else {
a6c45cf0
CW
14755 dev->mode_config.max_width = 8192;
14756 dev->mode_config.max_height = 8192;
79e53945 14757 }
068be561 14758
dc41c154
VS
14759 if (IS_845G(dev) || IS_I865G(dev)) {
14760 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14761 dev->mode_config.cursor_height = 1023;
14762 } else if (IS_GEN2(dev)) {
068be561
DL
14763 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14764 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14765 } else {
14766 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14767 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14768 }
14769
5d4545ae 14770 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14771
28c97730 14772 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW
14773 INTEL_INFO(dev)->num_pipes,
14774 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14775
055e393f 14776 for_each_pipe(dev_priv, pipe) {
8cc87b75 14777 intel_crtc_init(dev, pipe);
3bdcfc0c 14778 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14779 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14780 if (ret)
06da8da2 14781 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14782 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14783 }
79e53945
JB
14784 }
14785
e72f9fbf 14786 intel_shared_dpll_init(dev);
ee7b9f93 14787
9cce37f4
JB
14788 /* Just disable it once at startup */
14789 i915_disable_vga(dev);
79e53945 14790 intel_setup_outputs(dev);
11be49eb
CW
14791
14792 /* Just in case the BIOS is doing something questionable. */
7733b49b 14793 intel_fbc_disable(dev_priv);
fa9fa083 14794
6e9f798d 14795 drm_modeset_lock_all(dev);
043e9bda 14796 intel_modeset_setup_hw_state(dev);
6e9f798d 14797 drm_modeset_unlock_all(dev);
46f297fb 14798
d3fcc808 14799 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML
14800 struct intel_initial_plane_config plane_config = {};
14801
46f297fb
JB
14802 if (!crtc->active)
14803 continue;
14804
46f297fb 14805 /*
46f297fb
JB
14806 * Note that reserving the BIOS fb up front prevents us
14807 * from stuffing other stolen allocations like the ring
14808 * on top. This prevents some ugliness at boot time, and
14809 * can even allow for smooth boot transitions if the BIOS
14810 * fb is large enough for the active pipe configuration.
14811 */
eeebeac5
ML
14812 dev_priv->display.get_initial_plane_config(crtc,
14813 &plane_config);
14814
14815 /*
14816 * If the fb is shared between multiple heads, we'll
14817 * just get the first one.
14818 */
14819 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14820 }
2c7111db
CW
14821}
14822
7fad798e
DV
14823static void intel_enable_pipe_a(struct drm_device *dev)
14824{
14825 struct intel_connector *connector;
14826 struct drm_connector *crt = NULL;
14827 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14828 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV
14829
14830 /* We can't just switch on the pipe A, we need to set things up with a
14831 * proper mode and output configuration. As a gross hack, enable pipe A
14832 * by enabling the load detect pipe once. */
3a3371ff 14833 for_each_intel_connector(dev, connector) {
7fad798e
DV
14834 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14835 crt = &connector->base;
14836 break;
14837 }
14838 }
14839
14840 if (!crt)
14841 return;
14842
208bf9fd 14843 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14844 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV
14845}
14846
fa555837
DV
14847static bool
14848intel_check_plane_mapping(struct intel_crtc *crtc)
14849{
7eb552ae
BW
14850 struct drm_device *dev = crtc->base.dev;
14851 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV
14852 u32 reg, val;
14853
7eb552ae 14854 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV
14855 return true;
14856
14857 reg = DSPCNTR(!crtc->plane);
14858 val = I915_READ(reg);
14859
14860 if ((val & DISPLAY_PLANE_ENABLE) &&
14861 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14862 return false;
14863
14864 return true;
14865}
14866
02e93c35
VS
14867static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14868{
14869 struct drm_device *dev = crtc->base.dev;
14870 struct intel_encoder *encoder;
14871
14872 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14873 return true;
14874
14875 return false;
14876}
14877
24929352
DV
14878static void intel_sanitize_crtc(struct intel_crtc *crtc)
14879{
14880 struct drm_device *dev = crtc->base.dev;
14881 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14882 u32 reg;
24929352 14883
24929352 14884 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14885 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV
14886 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14887
d3eaf884 14888 /* restore vblank interrupts to correct state */
9625604c 14889 drm_crtc_vblank_reset(&crtc->base);
d297e103 14890 if (crtc->active) {
3a03dfb0 14891 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14892 update_scanline_offset(crtc);
9625604c
DV
14893 drm_crtc_vblank_on(&crtc->base);
14894 }
d3eaf884 14895
24929352 14896 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV
14897 * disable the crtc (and hence change the state) if it is wrong. Note
14898 * that gen4+ has a fixed plane -> pipe mapping. */
14899 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV
14900 bool plane;
14901
24929352
DV
14902 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14903 crtc->base.base.id);
14904
14905 /* Pipe has the wrong plane attached and the plane is active.
14906 * Temporarily change the plane mapping and disable everything
14907 * ... */
14908 plane = crtc->plane;
b70709a6 14909 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14910 crtc->plane = !plane;
b17d48e2 14911 intel_crtc_disable_noatomic(&crtc->base);
24929352 14912 crtc->plane = plane;
24929352 14913 }
24929352 14914
7fad798e
DV
14915 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14916 crtc->pipe == PIPE_A && !crtc->active) {
14917 /* BIOS forgot to enable pipe A, this mostly happens after
14918 * resume. Force-enable the pipe to fix this, the update_dpms
14919 * call below we restore the pipe to the right state, but leave
14920 * the required bits on. */
14921 intel_enable_pipe_a(dev);
14922 }
14923
24929352
DV
14924 /* Adjust the state of the output pipe according to whether we
14925 * have active connectors/encoders. */
02e93c35 14926 if (!intel_crtc_has_encoders(crtc))
b17d48e2 14927 intel_crtc_disable_noatomic(&crtc->base);
24929352 14928
53d9f4e9 14929 if (crtc->active != crtc->base.state->active) {
02e93c35 14930 struct intel_encoder *encoder;
24929352
DV
14931
14932 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML
14933 * functions or because of calls to intel_crtc_disable_noatomic,
14934 * or because the pipe is force-enabled due to the
24929352
DV
14935 * pipe A quirk. */
14936 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14937 crtc->base.base.id,
83d65738 14938 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV
14939 crtc->active ? "enabled" : "disabled");
14940
4be40c98 14941 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14942 crtc->base.state->active = crtc->active;
24929352
DV
14943 crtc->base.enabled = crtc->active;
14944
14945 /* Because we only establish the connector -> encoder ->
14946 * crtc links if something is active, this means the
14947 * crtc is now deactivated. Break the links. connector
14948 * -> encoder links are only establish when things are
14949 * actually up, hence no need to break them. */
14950 WARN_ON(crtc->active);
14951
2d406bb0 14952 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14953 encoder->base.crtc = NULL;
24929352 14954 }
c5ab3bc0 14955
a3ed6aad 14956 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV
14957 /*
14958 * We start out with underrun reporting disabled to avoid races.
14959 * For correct bookkeeping mark this on active crtcs.
14960 *
c5ab3bc0
DV
14961 * Also on gmch platforms we dont have any hardware bits to
14962 * disable the underrun reporting. Which means we need to start
14963 * out with underrun reporting disabled also on inactive pipes,
14964 * since otherwise we'll complain about the garbage we read when
14965 * e.g. coming up after runtime pm.
14966 *
4cc31489
DV
14967 * No protection against concurrent access is required - at
14968 * worst a fifo underrun happens which also sets this to false.
14969 */
14970 crtc->cpu_fifo_underrun_disabled = true;
14971 crtc->pch_fifo_underrun_disabled = true;
14972 }
24929352
DV
14973}
14974
14975static void intel_sanitize_encoder(struct intel_encoder *encoder)
14976{
14977 struct intel_connector *connector;
14978 struct drm_device *dev = encoder->base.dev;
873ffe69 14979 bool active = false;
24929352
DV
14980
14981 /* We need to check both for a crtc link (meaning that the
14982 * encoder is active and trying to read from a pipe) and the
14983 * pipe itself being active. */
14984 bool has_active_crtc = encoder->base.crtc &&
14985 to_intel_crtc(encoder->base.crtc)->active;
14986
873ffe69
ML
14987 for_each_intel_connector(dev, connector) {
14988 if (connector->base.encoder != &encoder->base)
14989 continue;
14990
14991 active = true;
14992 break;
14993 }
14994
14995 if (active && !has_active_crtc) {
24929352
DV
14996 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14997 encoder->base.base.id,
8e329a03 14998 encoder->base.name);
24929352
DV
14999
15000 /* Connector is active, but has no active pipe. This is
15001 * fallout from our resume register restoring. Disable
15002 * the encoder manually again. */
15003 if (encoder->base.crtc) {
15004 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15005 encoder->base.base.id,
8e329a03 15006 encoder->base.name);
24929352 15007 encoder->disable(encoder);
a62d1497
VS
15008 if (encoder->post_disable)
15009 encoder->post_disable(encoder);
24929352 15010 }
7f1950fb 15011 encoder->base.crtc = NULL;
24929352
DV
15012
15013 /* Inconsistent output/port/pipe state happens presumably due to
15014 * a bug in one of the get_hw_state functions. Or someplace else
15015 * in our code, like the register restore mess on resume. Clamp
15016 * things to off as a safer default. */
3a3371ff 15017 for_each_intel_connector(dev, connector) {
24929352
DV
15018 if (connector->encoder != encoder)
15019 continue;
7f1950fb
EE
15020 connector->base.dpms = DRM_MODE_DPMS_OFF;
15021 connector->base.encoder = NULL;
24929352
DV
15022 }
15023 }
15024 /* Enabled encoders without active connectors will be fixed in
15025 * the crtc fixup. */
15026}
15027
04098753 15028void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM
15029{
15030 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15031 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15032
04098753
ID
15033 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15034 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15035 i915_disable_vga(dev);
15036 }
15037}
15038
15039void i915_redisable_vga(struct drm_device *dev)
15040{
15041 struct drm_i915_private *dev_priv = dev->dev_private;
15042
8dc8a27c
PZ
15043 /* This function can be called both from intel_modeset_setup_hw_state or
15044 * at a very early point in our resume sequence, where the power well
15045 * structures are not yet restored. Since this function is at a very
15046 * paranoid "someone might have enabled VGA while we were not looking"
15047 * level, just check if the power well is enabled instead of trying to
15048 * follow the "don't touch the power well if we don't need it" policy
15049 * the rest of the driver uses. */
f458ebbc 15050 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ
15051 return;
15052
04098753 15053 i915_redisable_vga_power_on(dev);
0fde901f
KM
15054}
15055
98ec7739
VS
15056static bool primary_get_hw_state(struct intel_crtc *crtc)
15057{
15058 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15059
d032ffa0
ML
15060 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15061}
15062
15063static void readout_plane_state(struct intel_crtc *crtc,
15064 struct intel_crtc_state *crtc_state)
15065{
15066 struct intel_plane *p;
4cf0ebbd 15067 struct intel_plane_state *plane_state;
d032ffa0
ML
15068 bool active = crtc_state->base.active;
15069
d032ffa0 15070 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML
15071 if (crtc->pipe != p->pipe)
15072 continue;
15073
4cf0ebbd 15074 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15075
4cf0ebbd
ML
15076 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15077 plane_state->visible = primary_get_hw_state(crtc);
15078 else {
15079 if (active)
15080 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15081
4cf0ebbd 15082 plane_state->visible = false;
d032ffa0
ML
15083 }
15084 }
98ec7739
VS
15085}
15086
30e984df 15087static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV
15088{
15089 struct drm_i915_private *dev_priv = dev->dev_private;
15090 enum pipe pipe;
24929352
DV
15091 struct intel_crtc *crtc;
15092 struct intel_encoder *encoder;
15093 struct intel_connector *connector;
5358901f 15094 int i;
24929352 15095
d3fcc808 15096 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15097 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15098 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15099 crtc->config->base.crtc = &crtc->base;
3b117c8f 15100
0e8ffe1b 15101 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15102 crtc->config);
24929352 15103
49d6fa21 15104 crtc->base.state->active = crtc->active;
24929352 15105 crtc->base.enabled = crtc->active;
b70709a6 15106
5c1e3426
ML
15107 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15108 if (crtc->base.state->active) {
15109 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15110 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15111 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15112
15113 /*
15114 * The initial mode needs to be set in order to keep
15115 * the atomic core happy. It wants a valid mode if the
15116 * crtc's enabled, so we do the above call.
15117 *
15118 * At this point some state updated by the connectors
15119 * in their ->detect() callback has not run yet, so
15120 * no recalculation can be done yet.
15121 *
15122 * Even if we could do a recalculation and modeset
15123 * right now it would cause a double modeset if
15124 * fbdev or userspace chooses a different initial mode.
15125 *
5c1e3426
ML
15126 * If that happens, someone indicated they wanted a
15127 * mode change, which means it's safe to do a full
15128 * recalculation.
15129 */
1ed51de9 15130 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML
15131 }
15132
15133 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15134 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV
15135
15136 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15137 crtc->base.base.id,
15138 crtc->active ? "enabled" : "disabled");
15139 }
15140
5358901f
DV
15141 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15142 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15143
3e369b76
ACO
15144 pll->on = pll->get_hw_state(dev_priv, pll,
15145 &pll->config.hw_state);
5358901f 15146 pll->active = 0;
3e369b76 15147 pll->config.crtc_mask = 0;
d3fcc808 15148 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15149 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15150 pll->active++;
3e369b76 15151 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15152 }
5358901f 15153 }
5358901f 15154
1e6f2ddc 15155 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15156 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15157
3e369b76 15158 if (pll->config.crtc_mask)
bd2bb1b9 15159 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV
15160 }
15161
b2784e15 15162 for_each_intel_encoder(dev, encoder) {
24929352
DV
15163 pipe = 0;
15164
15165 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB
15166 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15167 encoder->base.crtc = &crtc->base;
6e3c9717 15168 encoder->get_config(encoder, crtc->config);
24929352
DV
15169 } else {
15170 encoder->base.crtc = NULL;
15171 }
15172
6f2bcceb 15173 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15174 encoder->base.base.id,
8e329a03 15175 encoder->base.name,
24929352 15176 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15177 pipe_name(pipe));
24929352
DV
15178 }
15179
3a3371ff 15180 for_each_intel_connector(dev, connector) {
24929352
DV
15181 if (connector->get_hw_state(connector)) {
15182 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV
15183 connector->base.encoder = &connector->encoder->base;
15184 } else {
15185 connector->base.dpms = DRM_MODE_DPMS_OFF;
15186 connector->base.encoder = NULL;
15187 }
15188 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15189 connector->base.base.id,
c23cc417 15190 connector->base.name,
24929352
DV
15191 connector->base.encoder ? "enabled" : "disabled");
15192 }
30e984df
DV
15193}
15194
043e9bda
ML
15195/* Scan out the current hw modeset state,
15196 * and sanitizes it to the current state
15197 */
15198static void
15199intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV
15200{
15201 struct drm_i915_private *dev_priv = dev->dev_private;
15202 enum pipe pipe;
30e984df
DV
15203 struct intel_crtc *crtc;
15204 struct intel_encoder *encoder;
35c95375 15205 int i;
30e984df
DV
15206
15207 intel_modeset_readout_hw_state(dev);
24929352
DV
15208
15209 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15210 for_each_intel_encoder(dev, encoder) {
24929352
DV
15211 intel_sanitize_encoder(encoder);
15212 }
15213
055e393f 15214 for_each_pipe(dev_priv, pipe) {
24929352
DV
15215 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15216 intel_sanitize_crtc(crtc);
6e3c9717
ACO
15217 intel_dump_pipe_config(crtc, crtc->config,
15218 "[setup_hw_state]");
24929352 15219 }
9a935856 15220
d29b2f9d
ACO
15221 intel_modeset_update_connector_atomic_state(dev);
15222
35c95375
DV
15223 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15224 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15225
15226 if (!pll->on || pll->active)
15227 continue;
15228
15229 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15230
15231 pll->disable(dev_priv, pll);
15232 pll->on = false;
15233 }
15234
26e1fe4f 15235 if (IS_VALLEYVIEW(dev))
6eb1a681
VS
15236 vlv_wm_get_hw_state(dev);
15237 else if (IS_GEN9(dev))
3078999f
PB
15238 skl_wm_get_hw_state(dev);
15239 else if (HAS_PCH_SPLIT(dev))
243e6a44 15240 ilk_wm_get_hw_state(dev);
292b990e
ML
15241
15242 for_each_intel_crtc(dev, crtc) {
15243 unsigned long put_domains;
15244
15245 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15246 if (WARN_ON(put_domains))
15247 modeset_put_power_domains(dev_priv, put_domains);
15248 }
15249 intel_display_set_init_power(dev_priv, false);
043e9bda 15250}
7d0bc1ea 15251
043e9bda
ML
15252void intel_display_resume(struct drm_device *dev)
15253{
15254 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15255 struct intel_connector *conn;
15256 struct intel_plane *plane;
15257 struct drm_crtc *crtc;
15258 int ret;
f30da187 15259
043e9bda
ML
15260 if (!state)
15261 return;
15262
15263 state->acquire_ctx = dev->mode_config.acquire_ctx;
15264
15265 /* preserve complete old state, including dpll */
15266 intel_atomic_get_shared_dpll_state(state);
15267
15268 for_each_crtc(dev, crtc) {
15269 struct drm_crtc_state *crtc_state =
15270 drm_atomic_get_crtc_state(state, crtc);
15271
15272 ret = PTR_ERR_OR_ZERO(crtc_state);
15273 if (ret)
15274 goto err;
15275
15276 /* force a restore */
15277 crtc_state->mode_changed = true;
45e2b5f6 15278 }
8af6cf88 15279
043e9bda
ML
15280 for_each_intel_plane(dev, plane) {
15281 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15282 if (ret)
15283 goto err;
15284 }
15285
15286 for_each_intel_connector(dev, conn) {
15287 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15288 if (ret)
15289 goto err;
15290 }
15291
15292 intel_modeset_setup_hw_state(dev);
15293
15294 i915_redisable_vga(dev);
74c090b1 15295 ret = drm_atomic_commit(state);
043e9bda
ML
15296 if (!ret)
15297 return;
15298
15299err:
15300 DRM_ERROR("Restoring old state failed with %i\n", ret);
15301 drm_atomic_state_free(state);
2c7111db
CW
15302}
15303
15304void intel_modeset_gem_init(struct drm_device *dev)
15305{
484b41dd 15306 struct drm_crtc *c;
2ff8fde1 15307 struct drm_i915_gem_object *obj;
e0d6149b 15308 int ret;
484b41dd 15309
ae48434c
ID
15310 mutex_lock(&dev->struct_mutex);
15311 intel_init_gt_powersave(dev);
15312 mutex_unlock(&dev->struct_mutex);
15313
1833b134 15314 intel_modeset_init_hw(dev);
02e792fb
DV
15315
15316 intel_setup_overlay(dev);
484b41dd
JB
15317
15318 /*
15319 * Make sure any fbs we allocated at startup are properly
15320 * pinned & fenced. When we do the allocation it's too early
15321 * for this.
15322 */
70e1e0ec 15323 for_each_crtc(dev, c) {
2ff8fde1
MR
15324 obj = intel_fb_obj(c->primary->fb);
15325 if (obj == NULL)
484b41dd
JB
15326 continue;
15327
e0d6149b
TU
15328 mutex_lock(&dev->struct_mutex);
15329 ret = intel_pin_and_fence_fb_obj(c->primary,
15330 c->primary->fb,
15331 c->primary->state,
91af127f 15332 NULL, NULL);
e0d6149b
TU
15333 mutex_unlock(&dev->struct_mutex);
15334 if (ret) {
484b41dd
JB
15335 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15336 to_intel_crtc(c)->pipe);
66e514c1
DA
15337 drm_framebuffer_unreference(c->primary->fb);
15338 c->primary->fb = NULL;
36750f28 15339 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15340 update_state_fb(c->primary);
36750f28 15341 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB
15342 }
15343 }
0962c3c9
VS
15344
15345 intel_backlight_register(dev);
79e53945
JB
15346}
15347
4932e2c3
ID
15348void intel_connector_unregister(struct intel_connector *intel_connector)
15349{
15350 struct drm_connector *connector = &intel_connector->base;
15351
15352 intel_panel_destroy_backlight(connector);
34ea3d38 15353 drm_connector_unregister(connector);
4932e2c3
ID
15354}
15355
79e53945
JB
15356void intel_modeset_cleanup(struct drm_device *dev)
15357{
652c393a 15358 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15359 struct drm_connector *connector;
652c393a 15360
2eb5252e
ID
15361 intel_disable_gt_powersave(dev);
15362
0962c3c9
VS
15363 intel_backlight_unregister(dev);
15364
fd0c0642
DV
15365 /*
15366 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15367 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV
15368 * experience fancy races otherwise.
15369 */
2aeb7d3a 15370 intel_irq_uninstall(dev_priv);
eb21b92b 15371
fd0c0642
DV
15372 /*
15373 * Due to the hpd irq storm handling the hotplug work can re-arm the
15374 * poll handlers. Hence disable polling after hpd handling is shut down.
15375 */
f87ea761 15376 drm_kms_helper_poll_fini(dev);
fd0c0642 15377
723bfd70
JB
15378 intel_unregister_dsm_handler();
15379
7733b49b 15380 intel_fbc_disable(dev_priv);
69341a5e 15381
1630fe75
CW
15382 /* flush any delayed tasks or pending work */
15383 flush_scheduled_work();
15384
db31af1d
JN
15385 /* destroy the backlight and sysfs files before encoders/connectors */
15386 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID
15387 struct intel_connector *intel_connector;
15388
15389 intel_connector = to_intel_connector(connector);
15390 intel_connector->unregister(intel_connector);
db31af1d 15391 }
d9255d57 15392
79e53945 15393 drm_mode_config_cleanup(dev);
4d7bb011
DV
15394
15395 intel_cleanup_overlay(dev);
ae48434c
ID
15396
15397 mutex_lock(&dev->struct_mutex);
15398 intel_cleanup_gt_powersave(dev);
15399 mutex_unlock(&dev->struct_mutex);
79e53945
JB
15400}
15401
f1c79df3
ZW
15402/*
15403 * Return which encoder is currently attached for connector.
15404 */
df0e9248 15405struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15406{
df0e9248
CW
15407 return &intel_attached_encoder(connector)->base;
15408}
f1c79df3 15409
df0e9248
CW
15410void intel_connector_attach_encoder(struct intel_connector *connector,
15411 struct intel_encoder *encoder)
15412{
15413 connector->encoder = encoder;
15414 drm_mode_connector_attach_encoder(&connector->base,
15415 &encoder->base);
79e53945 15416}
28d52043
DA
15417
15418/*
15419 * set vga decode state - true == enable VGA decode
15420 */
15421int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15422{
15423 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15424 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA
15425 u16 gmch_ctrl;
15426
75fa041d
CW
15427 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15428 DRM_ERROR("failed to read control word\n");
15429 return -EIO;
15430 }
15431
c0cc8a55
CW
15432 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15433 return 0;
15434
28d52043
DA
15435 if (state)
15436 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15437 else
15438 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW
15439
15440 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15441 DRM_ERROR("failed to write control word\n");
15442 return -EIO;
15443 }
15444
28d52043
DA
15445 return 0;
15446}
c4a1d9e4 15447
c4a1d9e4 15448struct intel_display_error_state {
ff57f1b0
PZ
15449
15450 u32 power_well_driver;
15451
63b66e5b
CW
15452 int num_transcoders;
15453
c4a1d9e4
CW
15454 struct intel_cursor_error_state {
15455 u32 control;
15456 u32 position;
15457 u32 base;
15458 u32 size;
52331309 15459 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW
15460
15461 struct intel_pipe_error_state {
ddf9c536 15462 bool power_domain_on;
c4a1d9e4 15463 u32 source;
f301b1e1 15464 u32 stat;
52331309 15465 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW
15466
15467 struct intel_plane_error_state {
15468 u32 control;
15469 u32 stride;
15470 u32 size;
15471 u32 pos;
15472 u32 addr;
15473 u32 surface;
15474 u32 tile_offset;
52331309 15475 } plane[I915_MAX_PIPES];
63b66e5b
CW
15476
15477 struct intel_transcoder_error_state {
ddf9c536 15478 bool power_domain_on;
63b66e5b
CW
15479 enum transcoder cpu_transcoder;
15480
15481 u32 conf;
15482
15483 u32 htotal;
15484 u32 hblank;
15485 u32 hsync;
15486 u32 vtotal;
15487 u32 vblank;
15488 u32 vsync;
15489 } transcoder[4];
c4a1d9e4
CW
15490};
15491
15492struct intel_display_error_state *
15493intel_display_capture_error_state(struct drm_device *dev)
15494{
fbee40df 15495 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15496 struct intel_display_error_state *error;
63b66e5b
CW
15497 int transcoders[] = {
15498 TRANSCODER_A,
15499 TRANSCODER_B,
15500 TRANSCODER_C,
15501 TRANSCODER_EDP,
15502 };
c4a1d9e4
CW
15503 int i;
15504
63b66e5b
CW
15505 if (INTEL_INFO(dev)->num_pipes == 0)
15506 return NULL;
15507
9d1cb914 15508 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW
15509 if (error == NULL)
15510 return NULL;
15511
190be112 15512 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ
15513 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15514
055e393f 15515 for_each_pipe(dev_priv, i) {
ddf9c536 15516 error->pipe[i].power_domain_on =
f458ebbc
DV
15517 __intel_display_power_is_enabled(dev_priv,
15518 POWER_DOMAIN_PIPE(i));
ddf9c536 15519 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ
15520 continue;
15521
5efb3e28
VS
15522 error->cursor[i].control = I915_READ(CURCNTR(i));
15523 error->cursor[i].position = I915_READ(CURPOS(i));
15524 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW
15525
15526 error->plane[i].control = I915_READ(DSPCNTR(i));
15527 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15528 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15529 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ
15530 error->plane[i].pos = I915_READ(DSPPOS(i));
15531 }
ca291363
PZ
15532 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15533 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW
15534 if (INTEL_INFO(dev)->gen >= 4) {
15535 error->plane[i].surface = I915_READ(DSPSURF(i));
15536 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15537 }
15538
c4a1d9e4 15539 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15540
3abfce77 15541 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15542 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW
15543 }
15544
15545 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15546 if (HAS_DDI(dev_priv->dev))
15547 error->num_transcoders++; /* Account for eDP. */
15548
15549 for (i = 0; i < error->num_transcoders; i++) {
15550 enum transcoder cpu_transcoder = transcoders[i];
15551
ddf9c536 15552 error->transcoder[i].power_domain_on =
f458ebbc 15553 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15554 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15555 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ
15556 continue;
15557
63b66e5b
CW
15558 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15559
15560 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15561 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15562 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15563 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15564 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15565 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15566 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW
15567 }
15568
15569 return error;
15570}
15571
edc3d884
MK
15572#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15573
c4a1d9e4 15574void
edc3d884 15575intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW
15576 struct drm_device *dev,
15577 struct intel_display_error_state *error)
15578{
055e393f 15579 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW
15580 int i;
15581
63b66e5b
CW
15582 if (!error)
15583 return;
15584
edc3d884 15585 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15586 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15587 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15588 error->power_well_driver);
055e393f 15589 for_each_pipe(dev_priv, i) {
edc3d884 15590 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID
15591 err_printf(m, " Power: %s\n",
15592 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15593 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15594 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK
15595
15596 err_printf(m, "Plane [%d]:\n", i);
15597 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15598 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15599 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK
15600 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15601 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15602 }
4b71a570 15603 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15604 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15605 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK
15606 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15607 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW
15608 }
15609
edc3d884
MK
15610 err_printf(m, "Cursor [%d]:\n", i);
15611 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15612 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15613 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15614 }
63b66e5b
CW
15615
15616 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15617 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15618 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID
15619 err_printf(m, " Power: %s\n",
15620 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW
15621 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15622 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15623 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15624 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15625 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15626 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15627 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15628 }
c4a1d9e4 15629}
e2fcdaa9
VS
15630
15631void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15632{
15633 struct intel_crtc *crtc;
15634
15635 for_each_intel_crtc(dev, crtc) {
15636 struct intel_unpin_work *work;
e2fcdaa9 15637
5e2d7afc 15638 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS
15639
15640 work = crtc->unpin_work;
15641
15642 if (work && work->event &&
15643 work->event->base.file_priv == file) {
15644 kfree(work->event);
15645 work->event = NULL;
15646 }
15647
5e2d7afc 15648 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS
15649 }
15650}