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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 FB |
26 | #include <stdlib.h> |
27 | #include <stdio.h> | |
28 | #include <stdarg.h> | |
29 | #include <string.h> | |
30 | #include <errno.h> | |
31 | #include <unistd.h> | |
32 | #include <inttypes.h> | |
33 | ||
6180a181 FB |
34 | #include "cpu.h" |
35 | #include "exec-all.h" | |
ca10f867 | 36 | #include "qemu-common.h" |
b67d9a52 | 37 | #include "tcg.h" |
b3c7724c | 38 | #include "hw/hw.h" |
cc9e98cb | 39 | #include "hw/qdev.h" |
74576198 | 40 | #include "osdep.h" |
7ba1e619 | 41 | #include "kvm.h" |
29e922b6 | 42 | #include "qemu-timer.h" |
53a5960a PB |
43 | #if defined(CONFIG_USER_ONLY) |
44 | #include <qemu.h> | |
fd052bf6 | 45 | #include <signal.h> |
f01576f1 JL |
46 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
47 | #include <sys/param.h> | |
48 | #if __FreeBSD_version >= 700104 | |
49 | #define HAVE_KINFO_GETVMMAP | |
50 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
51 | #include <sys/time.h> | |
52 | #include <sys/proc.h> | |
53 | #include <machine/profile.h> | |
54 | #define _KERNEL | |
55 | #include <sys/user.h> | |
56 | #undef _KERNEL | |
57 | #undef sigqueue | |
58 | #include <libutil.h> | |
59 | #endif | |
60 | #endif | |
53a5960a | 61 | #endif |
54936004 | 62 | |
fd6ce8f6 | 63 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 64 | //#define DEBUG_FLUSH |
9fa3e853 | 65 | //#define DEBUG_TLB |
67d3b957 | 66 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
67 | |
68 | /* make various TB consistency checks */ | |
5fafdf24 TS |
69 | //#define DEBUG_TB_CHECK |
70 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 71 | |
1196be37 | 72 | //#define DEBUG_IOPORT |
db7b5426 | 73 | //#define DEBUG_SUBPAGE |
1196be37 | 74 | |
99773bd4 PB |
75 | #if !defined(CONFIG_USER_ONLY) |
76 | /* TB consistency checks only implemented for usermode emulation. */ | |
77 | #undef DEBUG_TB_CHECK | |
78 | #endif | |
79 | ||
9fa3e853 FB |
80 | #define SMC_BITMAP_USE_THRESHOLD 10 |
81 | ||
bdaf78e0 | 82 | static TranslationBlock *tbs; |
24ab68ac | 83 | static int code_gen_max_blocks; |
9fa3e853 | 84 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 85 | static int nb_tbs; |
eb51d102 | 86 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 87 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 88 | |
141ac468 BS |
89 | #if defined(__arm__) || defined(__sparc_v9__) |
90 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
91 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
92 | section close to code segment. */ |
93 | #define code_gen_section \ | |
94 | __attribute__((__section__(".gen_code"))) \ | |
95 | __attribute__((aligned (32))) | |
f8e2af11 SW |
96 | #elif defined(_WIN32) |
97 | /* Maximum alignment for Win32 is 16. */ | |
98 | #define code_gen_section \ | |
99 | __attribute__((aligned (16))) | |
d03d860b BS |
100 | #else |
101 | #define code_gen_section \ | |
102 | __attribute__((aligned (32))) | |
103 | #endif | |
104 | ||
105 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
106 | static uint8_t *code_gen_buffer; |
107 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 108 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 109 | static unsigned long code_gen_buffer_max_size; |
24ab68ac | 110 | static uint8_t *code_gen_ptr; |
fd6ce8f6 | 111 | |
e2eef170 | 112 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 113 | int phys_ram_fd; |
74576198 | 114 | static int in_migration; |
94a6b54f | 115 | |
f471a17e | 116 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; |
e2eef170 | 117 | #endif |
9fa3e853 | 118 | |
6a00d601 FB |
119 | CPUState *first_cpu; |
120 | /* current CPU in the current thread. It is only valid inside | |
121 | cpu_exec() */ | |
5fafdf24 | 122 | CPUState *cpu_single_env; |
2e70f6ef | 123 | /* 0 = Do not count executed instructions. |
bf20dc07 | 124 | 1 = Precise instruction counting. |
2e70f6ef PB |
125 | 2 = Adaptive rate instruction counting. */ |
126 | int use_icount = 0; | |
127 | /* Current instruction counter. While executing translated code this may | |
128 | include some instructions that have not yet been executed. */ | |
129 | int64_t qemu_icount; | |
6a00d601 | 130 | |
54936004 | 131 | typedef struct PageDesc { |
92e873b9 | 132 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 133 | TranslationBlock *first_tb; |
9fa3e853 FB |
134 | /* in order to optimize self modifying code, we count the number |
135 | of lookups we do to a given page to use a bitmap */ | |
136 | unsigned int code_write_count; | |
137 | uint8_t *code_bitmap; | |
138 | #if defined(CONFIG_USER_ONLY) | |
139 | unsigned long flags; | |
140 | #endif | |
54936004 FB |
141 | } PageDesc; |
142 | ||
41c1b1c9 | 143 | /* In system mode we want L1_MAP to be based on ram offsets, |
5cd2c5b6 RH |
144 | while in user mode we want it to be based on virtual addresses. */ |
145 | #if !defined(CONFIG_USER_ONLY) | |
41c1b1c9 PB |
146 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
147 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
148 | #else | |
5cd2c5b6 | 149 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
41c1b1c9 | 150 | #endif |
bedb69ea | 151 | #else |
5cd2c5b6 | 152 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
bedb69ea | 153 | #endif |
54936004 | 154 | |
5cd2c5b6 RH |
155 | /* Size of the L2 (and L3, etc) page tables. */ |
156 | #define L2_BITS 10 | |
54936004 FB |
157 | #define L2_SIZE (1 << L2_BITS) |
158 | ||
5cd2c5b6 RH |
159 | /* The bits remaining after N lower levels of page tables. */ |
160 | #define P_L1_BITS_REM \ | |
161 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
162 | #define V_L1_BITS_REM \ | |
163 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
164 | ||
165 | /* Size of the L1 page table. Avoid silly small sizes. */ | |
166 | #if P_L1_BITS_REM < 4 | |
167 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) | |
168 | #else | |
169 | #define P_L1_BITS P_L1_BITS_REM | |
170 | #endif | |
171 | ||
172 | #if V_L1_BITS_REM < 4 | |
173 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
174 | #else | |
175 | #define V_L1_BITS V_L1_BITS_REM | |
176 | #endif | |
177 | ||
178 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) | |
179 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
180 | ||
181 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) | |
182 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
183 | ||
83fb7adf FB |
184 | unsigned long qemu_real_host_page_size; |
185 | unsigned long qemu_host_page_bits; | |
186 | unsigned long qemu_host_page_size; | |
187 | unsigned long qemu_host_page_mask; | |
54936004 | 188 | |
5cd2c5b6 RH |
189 | /* This is a multi-level map on the virtual address space. |
190 | The bottom level has pointers to PageDesc. */ | |
191 | static void *l1_map[V_L1_SIZE]; | |
54936004 | 192 | |
e2eef170 | 193 | #if !defined(CONFIG_USER_ONLY) |
41c1b1c9 PB |
194 | typedef struct PhysPageDesc { |
195 | /* offset in host memory of the page + io_index in the low bits */ | |
196 | ram_addr_t phys_offset; | |
197 | ram_addr_t region_offset; | |
198 | } PhysPageDesc; | |
199 | ||
5cd2c5b6 RH |
200 | /* This is a multi-level map on the physical address space. |
201 | The bottom level has pointers to PhysPageDesc. */ | |
202 | static void *l1_phys_map[P_L1_SIZE]; | |
6d9a1304 | 203 | |
e2eef170 PB |
204 | static void io_mem_init(void); |
205 | ||
33417e70 | 206 | /* io memory support */ |
33417e70 FB |
207 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
208 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 209 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 210 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
211 | static int io_mem_watch; |
212 | #endif | |
33417e70 | 213 | |
34865134 | 214 | /* log support */ |
1e8b27ca JR |
215 | #ifdef WIN32 |
216 | static const char *logfilename = "qemu.log"; | |
217 | #else | |
d9b630fd | 218 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 219 | #endif |
34865134 FB |
220 | FILE *logfile; |
221 | int loglevel; | |
e735b91c | 222 | static int log_append = 0; |
34865134 | 223 | |
e3db7226 | 224 | /* statistics */ |
b3755a91 | 225 | #if !defined(CONFIG_USER_ONLY) |
e3db7226 | 226 | static int tlb_flush_count; |
b3755a91 | 227 | #endif |
e3db7226 FB |
228 | static int tb_flush_count; |
229 | static int tb_phys_invalidate_count; | |
230 | ||
7cb69cae FB |
231 | #ifdef _WIN32 |
232 | static void map_exec(void *addr, long size) | |
233 | { | |
234 | DWORD old_protect; | |
235 | VirtualProtect(addr, size, | |
236 | PAGE_EXECUTE_READWRITE, &old_protect); | |
237 | ||
238 | } | |
239 | #else | |
240 | static void map_exec(void *addr, long size) | |
241 | { | |
4369415f | 242 | unsigned long start, end, page_size; |
7cb69cae | 243 | |
4369415f | 244 | page_size = getpagesize(); |
7cb69cae | 245 | start = (unsigned long)addr; |
4369415f | 246 | start &= ~(page_size - 1); |
7cb69cae FB |
247 | |
248 | end = (unsigned long)addr + size; | |
4369415f FB |
249 | end += page_size - 1; |
250 | end &= ~(page_size - 1); | |
7cb69cae FB |
251 | |
252 | mprotect((void *)start, end - start, | |
253 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
254 | } | |
255 | #endif | |
256 | ||
b346ff46 | 257 | static void page_init(void) |
54936004 | 258 | { |
83fb7adf | 259 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 260 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
261 | #ifdef _WIN32 |
262 | { | |
263 | SYSTEM_INFO system_info; | |
264 | ||
265 | GetSystemInfo(&system_info); | |
266 | qemu_real_host_page_size = system_info.dwPageSize; | |
267 | } | |
268 | #else | |
269 | qemu_real_host_page_size = getpagesize(); | |
270 | #endif | |
83fb7adf FB |
271 | if (qemu_host_page_size == 0) |
272 | qemu_host_page_size = qemu_real_host_page_size; | |
273 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
274 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
275 | qemu_host_page_bits = 0; | |
276 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
277 | qemu_host_page_bits++; | |
278 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
50a9569b | 279 | |
2e9a5713 | 280 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
50a9569b | 281 | { |
f01576f1 JL |
282 | #ifdef HAVE_KINFO_GETVMMAP |
283 | struct kinfo_vmentry *freep; | |
284 | int i, cnt; | |
285 | ||
286 | freep = kinfo_getvmmap(getpid(), &cnt); | |
287 | if (freep) { | |
288 | mmap_lock(); | |
289 | for (i = 0; i < cnt; i++) { | |
290 | unsigned long startaddr, endaddr; | |
291 | ||
292 | startaddr = freep[i].kve_start; | |
293 | endaddr = freep[i].kve_end; | |
294 | if (h2g_valid(startaddr)) { | |
295 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
296 | ||
297 | if (h2g_valid(endaddr)) { | |
298 | endaddr = h2g(endaddr); | |
fd436907 | 299 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
300 | } else { |
301 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
302 | endaddr = ~0ul; | |
fd436907 | 303 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
f01576f1 JL |
304 | #endif |
305 | } | |
306 | } | |
307 | } | |
308 | free(freep); | |
309 | mmap_unlock(); | |
310 | } | |
311 | #else | |
50a9569b | 312 | FILE *f; |
50a9569b | 313 | |
0776590d | 314 | last_brk = (unsigned long)sbrk(0); |
5cd2c5b6 | 315 | |
fd436907 | 316 | f = fopen("/compat/linux/proc/self/maps", "r"); |
50a9569b | 317 | if (f) { |
5cd2c5b6 RH |
318 | mmap_lock(); |
319 | ||
50a9569b | 320 | do { |
5cd2c5b6 RH |
321 | unsigned long startaddr, endaddr; |
322 | int n; | |
323 | ||
324 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
325 | ||
326 | if (n == 2 && h2g_valid(startaddr)) { | |
327 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
328 | ||
329 | if (h2g_valid(endaddr)) { | |
330 | endaddr = h2g(endaddr); | |
331 | } else { | |
332 | endaddr = ~0ul; | |
333 | } | |
334 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
50a9569b AZ |
335 | } |
336 | } while (!feof(f)); | |
5cd2c5b6 | 337 | |
50a9569b | 338 | fclose(f); |
5cd2c5b6 | 339 | mmap_unlock(); |
50a9569b | 340 | } |
f01576f1 | 341 | #endif |
50a9569b AZ |
342 | } |
343 | #endif | |
54936004 FB |
344 | } |
345 | ||
41c1b1c9 | 346 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
54936004 | 347 | { |
41c1b1c9 PB |
348 | PageDesc *pd; |
349 | void **lp; | |
350 | int i; | |
351 | ||
5cd2c5b6 | 352 | #if defined(CONFIG_USER_ONLY) |
2e9a5713 | 353 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ |
5cd2c5b6 RH |
354 | # define ALLOC(P, SIZE) \ |
355 | do { \ | |
356 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
357 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
5cd2c5b6 RH |
358 | } while (0) |
359 | #else | |
360 | # define ALLOC(P, SIZE) \ | |
361 | do { P = qemu_mallocz(SIZE); } while (0) | |
17e2377a | 362 | #endif |
434929bf | 363 | |
5cd2c5b6 RH |
364 | /* Level 1. Always allocated. */ |
365 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
366 | ||
367 | /* Level 2..N-1. */ | |
368 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
369 | void **p = *lp; | |
370 | ||
371 | if (p == NULL) { | |
372 | if (!alloc) { | |
373 | return NULL; | |
374 | } | |
375 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
376 | *lp = p; | |
17e2377a | 377 | } |
5cd2c5b6 RH |
378 | |
379 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
380 | } | |
381 | ||
382 | pd = *lp; | |
383 | if (pd == NULL) { | |
384 | if (!alloc) { | |
385 | return NULL; | |
386 | } | |
387 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
388 | *lp = pd; | |
54936004 | 389 | } |
5cd2c5b6 RH |
390 | |
391 | #undef ALLOC | |
5cd2c5b6 RH |
392 | |
393 | return pd + (index & (L2_SIZE - 1)); | |
54936004 FB |
394 | } |
395 | ||
41c1b1c9 | 396 | static inline PageDesc *page_find(tb_page_addr_t index) |
54936004 | 397 | { |
5cd2c5b6 | 398 | return page_find_alloc(index, 0); |
fd6ce8f6 FB |
399 | } |
400 | ||
6d9a1304 | 401 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 402 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 403 | { |
e3f4e2a4 | 404 | PhysPageDesc *pd; |
5cd2c5b6 RH |
405 | void **lp; |
406 | int i; | |
92e873b9 | 407 | |
5cd2c5b6 RH |
408 | /* Level 1. Always allocated. */ |
409 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); | |
108c49b8 | 410 | |
5cd2c5b6 RH |
411 | /* Level 2..N-1. */ |
412 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
413 | void **p = *lp; | |
414 | if (p == NULL) { | |
415 | if (!alloc) { | |
416 | return NULL; | |
417 | } | |
418 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); | |
419 | } | |
420 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
108c49b8 | 421 | } |
5cd2c5b6 | 422 | |
e3f4e2a4 | 423 | pd = *lp; |
5cd2c5b6 | 424 | if (pd == NULL) { |
e3f4e2a4 | 425 | int i; |
5cd2c5b6 RH |
426 | |
427 | if (!alloc) { | |
108c49b8 | 428 | return NULL; |
5cd2c5b6 RH |
429 | } |
430 | ||
431 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); | |
432 | ||
67c4d23c | 433 | for (i = 0; i < L2_SIZE; i++) { |
5cd2c5b6 RH |
434 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
435 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; | |
67c4d23c | 436 | } |
92e873b9 | 437 | } |
5cd2c5b6 RH |
438 | |
439 | return pd + (index & (L2_SIZE - 1)); | |
92e873b9 FB |
440 | } |
441 | ||
c227f099 | 442 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 443 | { |
108c49b8 | 444 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
445 | } |
446 | ||
c227f099 AL |
447 | static void tlb_protect_code(ram_addr_t ram_addr); |
448 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 449 | target_ulong vaddr); |
c8a706fe PB |
450 | #define mmap_lock() do { } while(0) |
451 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 452 | #endif |
fd6ce8f6 | 453 | |
4369415f FB |
454 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
455 | ||
456 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 457 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
458 | user mode. It will change when a dedicated libc will be used */ |
459 | #define USE_STATIC_CODE_GEN_BUFFER | |
460 | #endif | |
461 | ||
462 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
ebf50fb3 AJ |
463 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
464 | __attribute__((aligned (CODE_GEN_ALIGN))); | |
4369415f FB |
465 | #endif |
466 | ||
8fcd3692 | 467 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 468 | { |
4369415f FB |
469 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
470 | code_gen_buffer = static_code_gen_buffer; | |
471 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
472 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
473 | #else | |
26a5f13b FB |
474 | code_gen_buffer_size = tb_size; |
475 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
476 | #if defined(CONFIG_USER_ONLY) |
477 | /* in user mode, phys_ram_size is not meaningful */ | |
478 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
479 | #else | |
ccbb4d44 | 480 | /* XXX: needs adjustments */ |
94a6b54f | 481 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 482 | #endif |
26a5f13b FB |
483 | } |
484 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
485 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
486 | /* The code gen buffer location may have constraints depending on | |
487 | the host cpu and OS */ | |
488 | #if defined(__linux__) | |
489 | { | |
490 | int flags; | |
141ac468 BS |
491 | void *start = NULL; |
492 | ||
26a5f13b FB |
493 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
494 | #if defined(__x86_64__) | |
495 | flags |= MAP_32BIT; | |
496 | /* Cannot map more than that */ | |
497 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
498 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
499 | #elif defined(__sparc_v9__) |
500 | // Map the buffer below 2G, so we can use direct calls and branches | |
501 | flags |= MAP_FIXED; | |
502 | start = (void *) 0x60000000UL; | |
503 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
504 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 505 | #elif defined(__arm__) |
63d41246 | 506 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
507 | flags |= MAP_FIXED; |
508 | start = (void *) 0x01000000UL; | |
509 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
510 | code_gen_buffer_size = 16 * 1024 * 1024; | |
eba0b893 RH |
511 | #elif defined(__s390x__) |
512 | /* Map the buffer so that we can use direct calls and branches. */ | |
513 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
514 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { | |
515 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; | |
516 | } | |
517 | start = (void *)0x90000000UL; | |
26a5f13b | 518 | #endif |
141ac468 BS |
519 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
520 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
521 | flags, -1, 0); |
522 | if (code_gen_buffer == MAP_FAILED) { | |
523 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
524 | exit(1); | |
525 | } | |
526 | } | |
a167ba50 | 527 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
06e67a82 AL |
528 | { |
529 | int flags; | |
530 | void *addr = NULL; | |
531 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
532 | #if defined(__x86_64__) | |
533 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
534 | * 0x40000000 is free */ | |
535 | flags |= MAP_FIXED; | |
536 | addr = (void *)0x40000000; | |
537 | /* Cannot map more than that */ | |
538 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
539 | code_gen_buffer_size = (800 * 1024 * 1024); | |
540 | #endif | |
541 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
542 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
543 | flags, -1, 0); | |
544 | if (code_gen_buffer == MAP_FAILED) { | |
545 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
546 | exit(1); | |
547 | } | |
548 | } | |
26a5f13b FB |
549 | #else |
550 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
551 | map_exec(code_gen_buffer, code_gen_buffer_size); |
552 | #endif | |
4369415f | 553 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
554 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
555 | code_gen_buffer_max_size = code_gen_buffer_size - | |
239fda31 | 556 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); |
26a5f13b FB |
557 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
558 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
559 | } | |
560 | ||
561 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
562 | (in bytes) allocated to the translation buffer. Zero means default | |
563 | size. */ | |
564 | void cpu_exec_init_all(unsigned long tb_size) | |
565 | { | |
26a5f13b FB |
566 | cpu_gen_init(); |
567 | code_gen_alloc(tb_size); | |
568 | code_gen_ptr = code_gen_buffer; | |
4369415f | 569 | page_init(); |
e2eef170 | 570 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 571 | io_mem_init(); |
e2eef170 | 572 | #endif |
9002ec79 RH |
573 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
574 | /* There's no guest base to take into account, so go ahead and | |
575 | initialize the prologue now. */ | |
576 | tcg_prologue_init(&tcg_ctx); | |
577 | #endif | |
26a5f13b FB |
578 | } |
579 | ||
9656f324 PB |
580 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
581 | ||
e59fb374 | 582 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
583 | { |
584 | CPUState *env = opaque; | |
9656f324 | 585 | |
3098dba0 AJ |
586 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
587 | version_id is increased. */ | |
588 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
589 | tlb_flush(env, 1); |
590 | ||
591 | return 0; | |
592 | } | |
e7f4eff7 JQ |
593 | |
594 | static const VMStateDescription vmstate_cpu_common = { | |
595 | .name = "cpu_common", | |
596 | .version_id = 1, | |
597 | .minimum_version_id = 1, | |
598 | .minimum_version_id_old = 1, | |
e7f4eff7 JQ |
599 | .post_load = cpu_common_post_load, |
600 | .fields = (VMStateField []) { | |
601 | VMSTATE_UINT32(halted, CPUState), | |
602 | VMSTATE_UINT32(interrupt_request, CPUState), | |
603 | VMSTATE_END_OF_LIST() | |
604 | } | |
605 | }; | |
9656f324 PB |
606 | #endif |
607 | ||
950f1472 GC |
608 | CPUState *qemu_get_cpu(int cpu) |
609 | { | |
610 | CPUState *env = first_cpu; | |
611 | ||
612 | while (env) { | |
613 | if (env->cpu_index == cpu) | |
614 | break; | |
615 | env = env->next_cpu; | |
616 | } | |
617 | ||
618 | return env; | |
619 | } | |
620 | ||
6a00d601 | 621 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 622 | { |
6a00d601 FB |
623 | CPUState **penv; |
624 | int cpu_index; | |
625 | ||
c2764719 PB |
626 | #if defined(CONFIG_USER_ONLY) |
627 | cpu_list_lock(); | |
628 | #endif | |
6a00d601 FB |
629 | env->next_cpu = NULL; |
630 | penv = &first_cpu; | |
631 | cpu_index = 0; | |
632 | while (*penv != NULL) { | |
1e9fa730 | 633 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
634 | cpu_index++; |
635 | } | |
636 | env->cpu_index = cpu_index; | |
268a362c | 637 | env->numa_node = 0; |
72cf2d4f BS |
638 | QTAILQ_INIT(&env->breakpoints); |
639 | QTAILQ_INIT(&env->watchpoints); | |
6a00d601 | 640 | *penv = env; |
c2764719 PB |
641 | #if defined(CONFIG_USER_ONLY) |
642 | cpu_list_unlock(); | |
643 | #endif | |
b3c7724c | 644 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
0be71e32 AW |
645 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
646 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, | |
b3c7724c PB |
647 | cpu_save, cpu_load, env); |
648 | #endif | |
fd6ce8f6 FB |
649 | } |
650 | ||
9fa3e853 FB |
651 | static inline void invalidate_page_bitmap(PageDesc *p) |
652 | { | |
653 | if (p->code_bitmap) { | |
59817ccb | 654 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
655 | p->code_bitmap = NULL; |
656 | } | |
657 | p->code_write_count = 0; | |
658 | } | |
659 | ||
5cd2c5b6 RH |
660 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
661 | ||
662 | static void page_flush_tb_1 (int level, void **lp) | |
fd6ce8f6 | 663 | { |
5cd2c5b6 | 664 | int i; |
fd6ce8f6 | 665 | |
5cd2c5b6 RH |
666 | if (*lp == NULL) { |
667 | return; | |
668 | } | |
669 | if (level == 0) { | |
670 | PageDesc *pd = *lp; | |
7296abac | 671 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
672 | pd[i].first_tb = NULL; |
673 | invalidate_page_bitmap(pd + i); | |
fd6ce8f6 | 674 | } |
5cd2c5b6 RH |
675 | } else { |
676 | void **pp = *lp; | |
7296abac | 677 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
678 | page_flush_tb_1 (level - 1, pp + i); |
679 | } | |
680 | } | |
681 | } | |
682 | ||
683 | static void page_flush_tb(void) | |
684 | { | |
685 | int i; | |
686 | for (i = 0; i < V_L1_SIZE; i++) { | |
687 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
fd6ce8f6 FB |
688 | } |
689 | } | |
690 | ||
691 | /* flush all the translation blocks */ | |
d4e8164f | 692 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 693 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 694 | { |
6a00d601 | 695 | CPUState *env; |
0124311e | 696 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
697 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
698 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
699 | nb_tbs, nb_tbs > 0 ? | |
700 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 701 | #endif |
26a5f13b | 702 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
703 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
704 | ||
fd6ce8f6 | 705 | nb_tbs = 0; |
3b46e624 | 706 | |
6a00d601 FB |
707 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
708 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
709 | } | |
9fa3e853 | 710 | |
8a8a608f | 711 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 712 | page_flush_tb(); |
9fa3e853 | 713 | |
fd6ce8f6 | 714 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
715 | /* XXX: flush processor icache at this point if cache flush is |
716 | expensive */ | |
e3db7226 | 717 | tb_flush_count++; |
fd6ce8f6 FB |
718 | } |
719 | ||
720 | #ifdef DEBUG_TB_CHECK | |
721 | ||
bc98a7ef | 722 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
723 | { |
724 | TranslationBlock *tb; | |
725 | int i; | |
726 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
727 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
728 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
729 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
730 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
731 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
732 | " PC=%08lx size=%04x\n", | |
99773bd4 | 733 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
734 | } |
735 | } | |
736 | } | |
737 | } | |
738 | ||
739 | /* verify that all the pages have correct rights for code */ | |
740 | static void tb_page_check(void) | |
741 | { | |
742 | TranslationBlock *tb; | |
743 | int i, flags1, flags2; | |
3b46e624 | 744 | |
99773bd4 PB |
745 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
746 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
747 | flags1 = page_get_flags(tb->pc); |
748 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
749 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
750 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 751 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
752 | } |
753 | } | |
754 | } | |
755 | } | |
756 | ||
757 | #endif | |
758 | ||
759 | /* invalidate one TB */ | |
760 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
761 | int next_offset) | |
762 | { | |
763 | TranslationBlock *tb1; | |
764 | for(;;) { | |
765 | tb1 = *ptb; | |
766 | if (tb1 == tb) { | |
767 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
768 | break; | |
769 | } | |
770 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
771 | } | |
772 | } | |
773 | ||
9fa3e853 FB |
774 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
775 | { | |
776 | TranslationBlock *tb1; | |
777 | unsigned int n1; | |
778 | ||
779 | for(;;) { | |
780 | tb1 = *ptb; | |
781 | n1 = (long)tb1 & 3; | |
782 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
783 | if (tb1 == tb) { | |
784 | *ptb = tb1->page_next[n1]; | |
785 | break; | |
786 | } | |
787 | ptb = &tb1->page_next[n1]; | |
788 | } | |
789 | } | |
790 | ||
d4e8164f FB |
791 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
792 | { | |
793 | TranslationBlock *tb1, **ptb; | |
794 | unsigned int n1; | |
795 | ||
796 | ptb = &tb->jmp_next[n]; | |
797 | tb1 = *ptb; | |
798 | if (tb1) { | |
799 | /* find tb(n) in circular list */ | |
800 | for(;;) { | |
801 | tb1 = *ptb; | |
802 | n1 = (long)tb1 & 3; | |
803 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
804 | if (n1 == n && tb1 == tb) | |
805 | break; | |
806 | if (n1 == 2) { | |
807 | ptb = &tb1->jmp_first; | |
808 | } else { | |
809 | ptb = &tb1->jmp_next[n1]; | |
810 | } | |
811 | } | |
812 | /* now we can suppress tb(n) from the list */ | |
813 | *ptb = tb->jmp_next[n]; | |
814 | ||
815 | tb->jmp_next[n] = NULL; | |
816 | } | |
817 | } | |
818 | ||
819 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
820 | another TB */ | |
821 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
822 | { | |
823 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
824 | } | |
825 | ||
41c1b1c9 | 826 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
fd6ce8f6 | 827 | { |
6a00d601 | 828 | CPUState *env; |
8a40a180 | 829 | PageDesc *p; |
d4e8164f | 830 | unsigned int h, n1; |
41c1b1c9 | 831 | tb_page_addr_t phys_pc; |
8a40a180 | 832 | TranslationBlock *tb1, *tb2; |
3b46e624 | 833 | |
8a40a180 FB |
834 | /* remove the TB from the hash list */ |
835 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
836 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 837 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
838 | offsetof(TranslationBlock, phys_hash_next)); |
839 | ||
840 | /* remove the TB from the page list */ | |
841 | if (tb->page_addr[0] != page_addr) { | |
842 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
843 | tb_page_remove(&p->first_tb, tb); | |
844 | invalidate_page_bitmap(p); | |
845 | } | |
846 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
847 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
848 | tb_page_remove(&p->first_tb, tb); | |
849 | invalidate_page_bitmap(p); | |
850 | } | |
851 | ||
36bdbe54 | 852 | tb_invalidated_flag = 1; |
59817ccb | 853 | |
fd6ce8f6 | 854 | /* remove the TB from the hash list */ |
8a40a180 | 855 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
856 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
857 | if (env->tb_jmp_cache[h] == tb) | |
858 | env->tb_jmp_cache[h] = NULL; | |
859 | } | |
d4e8164f FB |
860 | |
861 | /* suppress this TB from the two jump lists */ | |
862 | tb_jmp_remove(tb, 0); | |
863 | tb_jmp_remove(tb, 1); | |
864 | ||
865 | /* suppress any remaining jumps to this TB */ | |
866 | tb1 = tb->jmp_first; | |
867 | for(;;) { | |
868 | n1 = (long)tb1 & 3; | |
869 | if (n1 == 2) | |
870 | break; | |
871 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
872 | tb2 = tb1->jmp_next[n1]; | |
873 | tb_reset_jump(tb1, n1); | |
874 | tb1->jmp_next[n1] = NULL; | |
875 | tb1 = tb2; | |
876 | } | |
877 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 878 | |
e3db7226 | 879 | tb_phys_invalidate_count++; |
9fa3e853 FB |
880 | } |
881 | ||
882 | static inline void set_bits(uint8_t *tab, int start, int len) | |
883 | { | |
884 | int end, mask, end1; | |
885 | ||
886 | end = start + len; | |
887 | tab += start >> 3; | |
888 | mask = 0xff << (start & 7); | |
889 | if ((start & ~7) == (end & ~7)) { | |
890 | if (start < end) { | |
891 | mask &= ~(0xff << (end & 7)); | |
892 | *tab |= mask; | |
893 | } | |
894 | } else { | |
895 | *tab++ |= mask; | |
896 | start = (start + 8) & ~7; | |
897 | end1 = end & ~7; | |
898 | while (start < end1) { | |
899 | *tab++ = 0xff; | |
900 | start += 8; | |
901 | } | |
902 | if (start < end) { | |
903 | mask = ~(0xff << (end & 7)); | |
904 | *tab |= mask; | |
905 | } | |
906 | } | |
907 | } | |
908 | ||
909 | static void build_page_bitmap(PageDesc *p) | |
910 | { | |
911 | int n, tb_start, tb_end; | |
912 | TranslationBlock *tb; | |
3b46e624 | 913 | |
b2a7081a | 914 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
915 | |
916 | tb = p->first_tb; | |
917 | while (tb != NULL) { | |
918 | n = (long)tb & 3; | |
919 | tb = (TranslationBlock *)((long)tb & ~3); | |
920 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
921 | if (n == 0) { | |
922 | /* NOTE: tb_end may be after the end of the page, but | |
923 | it is not a problem */ | |
924 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
925 | tb_end = tb_start + tb->size; | |
926 | if (tb_end > TARGET_PAGE_SIZE) | |
927 | tb_end = TARGET_PAGE_SIZE; | |
928 | } else { | |
929 | tb_start = 0; | |
930 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
931 | } | |
932 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
933 | tb = tb->page_next[n]; | |
934 | } | |
935 | } | |
936 | ||
2e70f6ef PB |
937 | TranslationBlock *tb_gen_code(CPUState *env, |
938 | target_ulong pc, target_ulong cs_base, | |
939 | int flags, int cflags) | |
d720b93d FB |
940 | { |
941 | TranslationBlock *tb; | |
942 | uint8_t *tc_ptr; | |
41c1b1c9 PB |
943 | tb_page_addr_t phys_pc, phys_page2; |
944 | target_ulong virt_page2; | |
d720b93d FB |
945 | int code_gen_size; |
946 | ||
41c1b1c9 | 947 | phys_pc = get_page_addr_code(env, pc); |
c27004ec | 948 | tb = tb_alloc(pc); |
d720b93d FB |
949 | if (!tb) { |
950 | /* flush must be done */ | |
951 | tb_flush(env); | |
952 | /* cannot fail at this point */ | |
c27004ec | 953 | tb = tb_alloc(pc); |
2e70f6ef PB |
954 | /* Don't forget to invalidate previous TB info. */ |
955 | tb_invalidated_flag = 1; | |
d720b93d FB |
956 | } |
957 | tc_ptr = code_gen_ptr; | |
958 | tb->tc_ptr = tc_ptr; | |
959 | tb->cs_base = cs_base; | |
960 | tb->flags = flags; | |
961 | tb->cflags = cflags; | |
d07bde88 | 962 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 963 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 964 | |
d720b93d | 965 | /* check next page if needed */ |
c27004ec | 966 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 967 | phys_page2 = -1; |
c27004ec | 968 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
41c1b1c9 | 969 | phys_page2 = get_page_addr_code(env, virt_page2); |
d720b93d | 970 | } |
41c1b1c9 | 971 | tb_link_page(tb, phys_pc, phys_page2); |
2e70f6ef | 972 | return tb; |
d720b93d | 973 | } |
3b46e624 | 974 | |
9fa3e853 FB |
975 | /* invalidate all TBs which intersect with the target physical page |
976 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
977 | the same physical page. 'is_cpu_write_access' should be true if called |
978 | from a real cpu write access: the virtual CPU will exit the current | |
979 | TB if code is modified inside this TB. */ | |
41c1b1c9 | 980 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
d720b93d FB |
981 | int is_cpu_write_access) |
982 | { | |
6b917547 | 983 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 984 | CPUState *env = cpu_single_env; |
41c1b1c9 | 985 | tb_page_addr_t tb_start, tb_end; |
6b917547 AL |
986 | PageDesc *p; |
987 | int n; | |
988 | #ifdef TARGET_HAS_PRECISE_SMC | |
989 | int current_tb_not_found = is_cpu_write_access; | |
990 | TranslationBlock *current_tb = NULL; | |
991 | int current_tb_modified = 0; | |
992 | target_ulong current_pc = 0; | |
993 | target_ulong current_cs_base = 0; | |
994 | int current_flags = 0; | |
995 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
996 | |
997 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 998 | if (!p) |
9fa3e853 | 999 | return; |
5fafdf24 | 1000 | if (!p->code_bitmap && |
d720b93d FB |
1001 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
1002 | is_cpu_write_access) { | |
9fa3e853 FB |
1003 | /* build code bitmap */ |
1004 | build_page_bitmap(p); | |
1005 | } | |
1006 | ||
1007 | /* we remove all the TBs in the range [start, end[ */ | |
1008 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
1009 | tb = p->first_tb; | |
1010 | while (tb != NULL) { | |
1011 | n = (long)tb & 3; | |
1012 | tb = (TranslationBlock *)((long)tb & ~3); | |
1013 | tb_next = tb->page_next[n]; | |
1014 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1015 | if (n == 0) { | |
1016 | /* NOTE: tb_end may be after the end of the page, but | |
1017 | it is not a problem */ | |
1018 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1019 | tb_end = tb_start + tb->size; | |
1020 | } else { | |
1021 | tb_start = tb->page_addr[1]; | |
1022 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1023 | } | |
1024 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
1025 | #ifdef TARGET_HAS_PRECISE_SMC |
1026 | if (current_tb_not_found) { | |
1027 | current_tb_not_found = 0; | |
1028 | current_tb = NULL; | |
2e70f6ef | 1029 | if (env->mem_io_pc) { |
d720b93d | 1030 | /* now we have a real cpu fault */ |
2e70f6ef | 1031 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
1032 | } |
1033 | } | |
1034 | if (current_tb == tb && | |
2e70f6ef | 1035 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1036 | /* If we are modifying the current TB, we must stop |
1037 | its execution. We could be more precise by checking | |
1038 | that the modification is after the current PC, but it | |
1039 | would require a specialized function to partially | |
1040 | restore the CPU state */ | |
3b46e624 | 1041 | |
d720b93d | 1042 | current_tb_modified = 1; |
5fafdf24 | 1043 | cpu_restore_state(current_tb, env, |
2e70f6ef | 1044 | env->mem_io_pc, NULL); |
6b917547 AL |
1045 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1046 | ¤t_flags); | |
d720b93d FB |
1047 | } |
1048 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
1049 | /* we need to do that to handle the case where a signal |
1050 | occurs while doing tb_phys_invalidate() */ | |
1051 | saved_tb = NULL; | |
1052 | if (env) { | |
1053 | saved_tb = env->current_tb; | |
1054 | env->current_tb = NULL; | |
1055 | } | |
9fa3e853 | 1056 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
1057 | if (env) { |
1058 | env->current_tb = saved_tb; | |
1059 | if (env->interrupt_request && env->current_tb) | |
1060 | cpu_interrupt(env, env->interrupt_request); | |
1061 | } | |
9fa3e853 FB |
1062 | } |
1063 | tb = tb_next; | |
1064 | } | |
1065 | #if !defined(CONFIG_USER_ONLY) | |
1066 | /* if no code remaining, no need to continue to use slow writes */ | |
1067 | if (!p->first_tb) { | |
1068 | invalidate_page_bitmap(p); | |
d720b93d | 1069 | if (is_cpu_write_access) { |
2e70f6ef | 1070 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1071 | } |
1072 | } | |
1073 | #endif | |
1074 | #ifdef TARGET_HAS_PRECISE_SMC | |
1075 | if (current_tb_modified) { | |
1076 | /* we generate a block containing just the instruction | |
1077 | modifying the memory. It will ensure that it cannot modify | |
1078 | itself */ | |
ea1c1802 | 1079 | env->current_tb = NULL; |
2e70f6ef | 1080 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1081 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1082 | } |
fd6ce8f6 | 1083 | #endif |
9fa3e853 | 1084 | } |
fd6ce8f6 | 1085 | |
9fa3e853 | 1086 | /* len must be <= 8 and start must be a multiple of len */ |
41c1b1c9 | 1087 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
9fa3e853 FB |
1088 | { |
1089 | PageDesc *p; | |
1090 | int offset, b; | |
59817ccb | 1091 | #if 0 |
a4193c8a | 1092 | if (1) { |
93fcfe39 AL |
1093 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1094 | cpu_single_env->mem_io_vaddr, len, | |
1095 | cpu_single_env->eip, | |
1096 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1097 | } |
1098 | #endif | |
9fa3e853 | 1099 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1100 | if (!p) |
9fa3e853 FB |
1101 | return; |
1102 | if (p->code_bitmap) { | |
1103 | offset = start & ~TARGET_PAGE_MASK; | |
1104 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1105 | if (b & ((1 << len) - 1)) | |
1106 | goto do_invalidate; | |
1107 | } else { | |
1108 | do_invalidate: | |
d720b93d | 1109 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1110 | } |
1111 | } | |
1112 | ||
9fa3e853 | 1113 | #if !defined(CONFIG_SOFTMMU) |
41c1b1c9 | 1114 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d720b93d | 1115 | unsigned long pc, void *puc) |
9fa3e853 | 1116 | { |
6b917547 | 1117 | TranslationBlock *tb; |
9fa3e853 | 1118 | PageDesc *p; |
6b917547 | 1119 | int n; |
d720b93d | 1120 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1121 | TranslationBlock *current_tb = NULL; |
d720b93d | 1122 | CPUState *env = cpu_single_env; |
6b917547 AL |
1123 | int current_tb_modified = 0; |
1124 | target_ulong current_pc = 0; | |
1125 | target_ulong current_cs_base = 0; | |
1126 | int current_flags = 0; | |
d720b93d | 1127 | #endif |
9fa3e853 FB |
1128 | |
1129 | addr &= TARGET_PAGE_MASK; | |
1130 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1131 | if (!p) |
9fa3e853 FB |
1132 | return; |
1133 | tb = p->first_tb; | |
d720b93d FB |
1134 | #ifdef TARGET_HAS_PRECISE_SMC |
1135 | if (tb && pc != 0) { | |
1136 | current_tb = tb_find_pc(pc); | |
1137 | } | |
1138 | #endif | |
9fa3e853 FB |
1139 | while (tb != NULL) { |
1140 | n = (long)tb & 3; | |
1141 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1142 | #ifdef TARGET_HAS_PRECISE_SMC |
1143 | if (current_tb == tb && | |
2e70f6ef | 1144 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1145 | /* If we are modifying the current TB, we must stop |
1146 | its execution. We could be more precise by checking | |
1147 | that the modification is after the current PC, but it | |
1148 | would require a specialized function to partially | |
1149 | restore the CPU state */ | |
3b46e624 | 1150 | |
d720b93d FB |
1151 | current_tb_modified = 1; |
1152 | cpu_restore_state(current_tb, env, pc, puc); | |
6b917547 AL |
1153 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1154 | ¤t_flags); | |
d720b93d FB |
1155 | } |
1156 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1157 | tb_phys_invalidate(tb, addr); |
1158 | tb = tb->page_next[n]; | |
1159 | } | |
fd6ce8f6 | 1160 | p->first_tb = NULL; |
d720b93d FB |
1161 | #ifdef TARGET_HAS_PRECISE_SMC |
1162 | if (current_tb_modified) { | |
1163 | /* we generate a block containing just the instruction | |
1164 | modifying the memory. It will ensure that it cannot modify | |
1165 | itself */ | |
ea1c1802 | 1166 | env->current_tb = NULL; |
2e70f6ef | 1167 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1168 | cpu_resume_from_signal(env, puc); |
1169 | } | |
1170 | #endif | |
fd6ce8f6 | 1171 | } |
9fa3e853 | 1172 | #endif |
fd6ce8f6 FB |
1173 | |
1174 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1175 | static inline void tb_alloc_page(TranslationBlock *tb, |
41c1b1c9 | 1176 | unsigned int n, tb_page_addr_t page_addr) |
fd6ce8f6 FB |
1177 | { |
1178 | PageDesc *p; | |
9fa3e853 FB |
1179 | TranslationBlock *last_first_tb; |
1180 | ||
1181 | tb->page_addr[n] = page_addr; | |
5cd2c5b6 | 1182 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
9fa3e853 FB |
1183 | tb->page_next[n] = p->first_tb; |
1184 | last_first_tb = p->first_tb; | |
1185 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1186 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1187 | |
107db443 | 1188 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1189 | |
9fa3e853 | 1190 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1191 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1192 | target_ulong addr; |
1193 | PageDesc *p2; | |
9fa3e853 FB |
1194 | int prot; |
1195 | ||
fd6ce8f6 FB |
1196 | /* force the host page as non writable (writes will have a |
1197 | page fault + mprotect overhead) */ | |
53a5960a | 1198 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1199 | prot = 0; |
53a5960a PB |
1200 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1201 | addr += TARGET_PAGE_SIZE) { | |
1202 | ||
1203 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1204 | if (!p2) | |
1205 | continue; | |
1206 | prot |= p2->flags; | |
1207 | p2->flags &= ~PAGE_WRITE; | |
53a5960a | 1208 | } |
5fafdf24 | 1209 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1210 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1211 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1212 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1213 | page_addr); |
fd6ce8f6 | 1214 | #endif |
fd6ce8f6 | 1215 | } |
9fa3e853 FB |
1216 | #else |
1217 | /* if some code is already present, then the pages are already | |
1218 | protected. So we handle the case where only the first TB is | |
1219 | allocated in a physical page */ | |
1220 | if (!last_first_tb) { | |
6a00d601 | 1221 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1222 | } |
1223 | #endif | |
d720b93d FB |
1224 | |
1225 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1226 | } |
1227 | ||
1228 | /* Allocate a new translation block. Flush the translation buffer if | |
1229 | too many translation blocks or too much generated code. */ | |
c27004ec | 1230 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1231 | { |
1232 | TranslationBlock *tb; | |
fd6ce8f6 | 1233 | |
26a5f13b FB |
1234 | if (nb_tbs >= code_gen_max_blocks || |
1235 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1236 | return NULL; |
fd6ce8f6 FB |
1237 | tb = &tbs[nb_tbs++]; |
1238 | tb->pc = pc; | |
b448f2f3 | 1239 | tb->cflags = 0; |
d4e8164f FB |
1240 | return tb; |
1241 | } | |
1242 | ||
2e70f6ef PB |
1243 | void tb_free(TranslationBlock *tb) |
1244 | { | |
bf20dc07 | 1245 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1246 | Ignore the hard cases and just back up if this TB happens to |
1247 | be the last one generated. */ | |
1248 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1249 | code_gen_ptr = tb->tc_ptr; | |
1250 | nb_tbs--; | |
1251 | } | |
1252 | } | |
1253 | ||
9fa3e853 FB |
1254 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1255 | (-1) to indicate that only one page contains the TB. */ | |
41c1b1c9 PB |
1256 | void tb_link_page(TranslationBlock *tb, |
1257 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) | |
d4e8164f | 1258 | { |
9fa3e853 FB |
1259 | unsigned int h; |
1260 | TranslationBlock **ptb; | |
1261 | ||
c8a706fe PB |
1262 | /* Grab the mmap lock to stop another thread invalidating this TB |
1263 | before we are done. */ | |
1264 | mmap_lock(); | |
9fa3e853 FB |
1265 | /* add in the physical hash table */ |
1266 | h = tb_phys_hash_func(phys_pc); | |
1267 | ptb = &tb_phys_hash[h]; | |
1268 | tb->phys_hash_next = *ptb; | |
1269 | *ptb = tb; | |
fd6ce8f6 FB |
1270 | |
1271 | /* add in the page list */ | |
9fa3e853 FB |
1272 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1273 | if (phys_page2 != -1) | |
1274 | tb_alloc_page(tb, 1, phys_page2); | |
1275 | else | |
1276 | tb->page_addr[1] = -1; | |
9fa3e853 | 1277 | |
d4e8164f FB |
1278 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1279 | tb->jmp_next[0] = NULL; | |
1280 | tb->jmp_next[1] = NULL; | |
1281 | ||
1282 | /* init original jump addresses */ | |
1283 | if (tb->tb_next_offset[0] != 0xffff) | |
1284 | tb_reset_jump(tb, 0); | |
1285 | if (tb->tb_next_offset[1] != 0xffff) | |
1286 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1287 | |
1288 | #ifdef DEBUG_TB_CHECK | |
1289 | tb_page_check(); | |
1290 | #endif | |
c8a706fe | 1291 | mmap_unlock(); |
fd6ce8f6 FB |
1292 | } |
1293 | ||
9fa3e853 FB |
1294 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1295 | tb[1].tc_ptr. Return NULL if not found */ | |
1296 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1297 | { |
9fa3e853 FB |
1298 | int m_min, m_max, m; |
1299 | unsigned long v; | |
1300 | TranslationBlock *tb; | |
a513fe19 FB |
1301 | |
1302 | if (nb_tbs <= 0) | |
1303 | return NULL; | |
1304 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1305 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1306 | return NULL; | |
1307 | /* binary search (cf Knuth) */ | |
1308 | m_min = 0; | |
1309 | m_max = nb_tbs - 1; | |
1310 | while (m_min <= m_max) { | |
1311 | m = (m_min + m_max) >> 1; | |
1312 | tb = &tbs[m]; | |
1313 | v = (unsigned long)tb->tc_ptr; | |
1314 | if (v == tc_ptr) | |
1315 | return tb; | |
1316 | else if (tc_ptr < v) { | |
1317 | m_max = m - 1; | |
1318 | } else { | |
1319 | m_min = m + 1; | |
1320 | } | |
5fafdf24 | 1321 | } |
a513fe19 FB |
1322 | return &tbs[m_max]; |
1323 | } | |
7501267e | 1324 | |
ea041c0e FB |
1325 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1326 | ||
1327 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1328 | { | |
1329 | TranslationBlock *tb1, *tb_next, **ptb; | |
1330 | unsigned int n1; | |
1331 | ||
1332 | tb1 = tb->jmp_next[n]; | |
1333 | if (tb1 != NULL) { | |
1334 | /* find head of list */ | |
1335 | for(;;) { | |
1336 | n1 = (long)tb1 & 3; | |
1337 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1338 | if (n1 == 2) | |
1339 | break; | |
1340 | tb1 = tb1->jmp_next[n1]; | |
1341 | } | |
1342 | /* we are now sure now that tb jumps to tb1 */ | |
1343 | tb_next = tb1; | |
1344 | ||
1345 | /* remove tb from the jmp_first list */ | |
1346 | ptb = &tb_next->jmp_first; | |
1347 | for(;;) { | |
1348 | tb1 = *ptb; | |
1349 | n1 = (long)tb1 & 3; | |
1350 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1351 | if (n1 == n && tb1 == tb) | |
1352 | break; | |
1353 | ptb = &tb1->jmp_next[n1]; | |
1354 | } | |
1355 | *ptb = tb->jmp_next[n]; | |
1356 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1357 | |
ea041c0e FB |
1358 | /* suppress the jump to next tb in generated code */ |
1359 | tb_reset_jump(tb, n); | |
1360 | ||
0124311e | 1361 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1362 | tb_reset_jump_recursive(tb_next); |
1363 | } | |
1364 | } | |
1365 | ||
1366 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1367 | { | |
1368 | tb_reset_jump_recursive2(tb, 0); | |
1369 | tb_reset_jump_recursive2(tb, 1); | |
1370 | } | |
1371 | ||
1fddef4b | 1372 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1373 | #if defined(CONFIG_USER_ONLY) |
1374 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1375 | { | |
1376 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1377 | } | |
1378 | #else | |
d720b93d FB |
1379 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1380 | { | |
c227f099 | 1381 | target_phys_addr_t addr; |
9b3c35e0 | 1382 | target_ulong pd; |
c227f099 | 1383 | ram_addr_t ram_addr; |
c2f07f81 | 1384 | PhysPageDesc *p; |
d720b93d | 1385 | |
c2f07f81 PB |
1386 | addr = cpu_get_phys_page_debug(env, pc); |
1387 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1388 | if (!p) { | |
1389 | pd = IO_MEM_UNASSIGNED; | |
1390 | } else { | |
1391 | pd = p->phys_offset; | |
1392 | } | |
1393 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1394 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1395 | } |
c27004ec | 1396 | #endif |
94df27fd | 1397 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1398 | |
c527ee8f PB |
1399 | #if defined(CONFIG_USER_ONLY) |
1400 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1401 | ||
1402 | { | |
1403 | } | |
1404 | ||
1405 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1406 | int flags, CPUWatchpoint **watchpoint) | |
1407 | { | |
1408 | return -ENOSYS; | |
1409 | } | |
1410 | #else | |
6658ffb8 | 1411 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1412 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1413 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1414 | { |
b4051334 | 1415 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1416 | CPUWatchpoint *wp; |
6658ffb8 | 1417 | |
b4051334 AL |
1418 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1419 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1420 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1421 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1422 | return -EINVAL; | |
1423 | } | |
a1d1bb31 | 1424 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1425 | |
1426 | wp->vaddr = addr; | |
b4051334 | 1427 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1428 | wp->flags = flags; |
1429 | ||
2dc9f411 | 1430 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1431 | if (flags & BP_GDB) |
72cf2d4f | 1432 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1433 | else |
72cf2d4f | 1434 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1435 | |
6658ffb8 | 1436 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1437 | |
1438 | if (watchpoint) | |
1439 | *watchpoint = wp; | |
1440 | return 0; | |
6658ffb8 PB |
1441 | } |
1442 | ||
a1d1bb31 AL |
1443 | /* Remove a specific watchpoint. */ |
1444 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1445 | int flags) | |
6658ffb8 | 1446 | { |
b4051334 | 1447 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1448 | CPUWatchpoint *wp; |
6658ffb8 | 1449 | |
72cf2d4f | 1450 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1451 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1452 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1453 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1454 | return 0; |
1455 | } | |
1456 | } | |
a1d1bb31 | 1457 | return -ENOENT; |
6658ffb8 PB |
1458 | } |
1459 | ||
a1d1bb31 AL |
1460 | /* Remove a specific watchpoint by reference. */ |
1461 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1462 | { | |
72cf2d4f | 1463 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1464 | |
a1d1bb31 AL |
1465 | tlb_flush_page(env, watchpoint->vaddr); |
1466 | ||
1467 | qemu_free(watchpoint); | |
1468 | } | |
1469 | ||
1470 | /* Remove all matching watchpoints. */ | |
1471 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1472 | { | |
c0ce998e | 1473 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1474 | |
72cf2d4f | 1475 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1476 | if (wp->flags & mask) |
1477 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1478 | } |
7d03f82f | 1479 | } |
c527ee8f | 1480 | #endif |
7d03f82f | 1481 | |
a1d1bb31 AL |
1482 | /* Add a breakpoint. */ |
1483 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1484 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1485 | { |
1fddef4b | 1486 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1487 | CPUBreakpoint *bp; |
3b46e624 | 1488 | |
a1d1bb31 | 1489 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1490 | |
a1d1bb31 AL |
1491 | bp->pc = pc; |
1492 | bp->flags = flags; | |
1493 | ||
2dc9f411 | 1494 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1495 | if (flags & BP_GDB) |
72cf2d4f | 1496 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1497 | else |
72cf2d4f | 1498 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1499 | |
d720b93d | 1500 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1501 | |
1502 | if (breakpoint) | |
1503 | *breakpoint = bp; | |
4c3a88a2 FB |
1504 | return 0; |
1505 | #else | |
a1d1bb31 | 1506 | return -ENOSYS; |
4c3a88a2 FB |
1507 | #endif |
1508 | } | |
1509 | ||
a1d1bb31 AL |
1510 | /* Remove a specific breakpoint. */ |
1511 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1512 | { | |
7d03f82f | 1513 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1514 | CPUBreakpoint *bp; |
1515 | ||
72cf2d4f | 1516 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1517 | if (bp->pc == pc && bp->flags == flags) { |
1518 | cpu_breakpoint_remove_by_ref(env, bp); | |
1519 | return 0; | |
1520 | } | |
7d03f82f | 1521 | } |
a1d1bb31 AL |
1522 | return -ENOENT; |
1523 | #else | |
1524 | return -ENOSYS; | |
7d03f82f EI |
1525 | #endif |
1526 | } | |
1527 | ||
a1d1bb31 AL |
1528 | /* Remove a specific breakpoint by reference. */ |
1529 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1530 | { |
1fddef4b | 1531 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1532 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1533 | |
a1d1bb31 AL |
1534 | breakpoint_invalidate(env, breakpoint->pc); |
1535 | ||
1536 | qemu_free(breakpoint); | |
1537 | #endif | |
1538 | } | |
1539 | ||
1540 | /* Remove all matching breakpoints. */ | |
1541 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1542 | { | |
1543 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1544 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1545 | |
72cf2d4f | 1546 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1547 | if (bp->flags & mask) |
1548 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1549 | } |
4c3a88a2 FB |
1550 | #endif |
1551 | } | |
1552 | ||
c33a346e FB |
1553 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1554 | CPU loop after each instruction */ | |
1555 | void cpu_single_step(CPUState *env, int enabled) | |
1556 | { | |
1fddef4b | 1557 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1558 | if (env->singlestep_enabled != enabled) { |
1559 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1560 | if (kvm_enabled()) |
1561 | kvm_update_guest_debug(env, 0); | |
1562 | else { | |
ccbb4d44 | 1563 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1564 | /* XXX: only flush what is necessary */ |
1565 | tb_flush(env); | |
1566 | } | |
c33a346e FB |
1567 | } |
1568 | #endif | |
1569 | } | |
1570 | ||
34865134 FB |
1571 | /* enable or disable low levels log */ |
1572 | void cpu_set_log(int log_flags) | |
1573 | { | |
1574 | loglevel = log_flags; | |
1575 | if (loglevel && !logfile) { | |
11fcfab4 | 1576 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1577 | if (!logfile) { |
1578 | perror(logfilename); | |
1579 | _exit(1); | |
1580 | } | |
9fa3e853 FB |
1581 | #if !defined(CONFIG_SOFTMMU) |
1582 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1583 | { | |
b55266b5 | 1584 | static char logfile_buf[4096]; |
9fa3e853 FB |
1585 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1586 | } | |
bf65f53f FN |
1587 | #elif !defined(_WIN32) |
1588 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1589 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1590 | #endif |
e735b91c PB |
1591 | log_append = 1; |
1592 | } | |
1593 | if (!loglevel && logfile) { | |
1594 | fclose(logfile); | |
1595 | logfile = NULL; | |
34865134 FB |
1596 | } |
1597 | } | |
1598 | ||
1599 | void cpu_set_log_filename(const char *filename) | |
1600 | { | |
1601 | logfilename = strdup(filename); | |
e735b91c PB |
1602 | if (logfile) { |
1603 | fclose(logfile); | |
1604 | logfile = NULL; | |
1605 | } | |
1606 | cpu_set_log(loglevel); | |
34865134 | 1607 | } |
c33a346e | 1608 | |
3098dba0 | 1609 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1610 | { |
3098dba0 AJ |
1611 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1612 | problem and hope the cpu will stop of its own accord. For userspace | |
1613 | emulation this often isn't actually as bad as it sounds. Often | |
1614 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1615 | TranslationBlock *tb; |
c227f099 | 1616 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1617 | |
cab1b4bd | 1618 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1619 | tb = env->current_tb; |
1620 | /* if the cpu is currently executing code, we must unlink it and | |
1621 | all the potentially executing TB */ | |
f76cfe56 | 1622 | if (tb) { |
3098dba0 AJ |
1623 | env->current_tb = NULL; |
1624 | tb_reset_jump_recursive(tb); | |
be214e6c | 1625 | } |
cab1b4bd | 1626 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1627 | } |
1628 | ||
1629 | /* mask must never be zero, except for A20 change call */ | |
1630 | void cpu_interrupt(CPUState *env, int mask) | |
1631 | { | |
1632 | int old_mask; | |
be214e6c | 1633 | |
2e70f6ef | 1634 | old_mask = env->interrupt_request; |
68a79315 | 1635 | env->interrupt_request |= mask; |
3098dba0 | 1636 | |
8edac960 AL |
1637 | #ifndef CONFIG_USER_ONLY |
1638 | /* | |
1639 | * If called from iothread context, wake the target cpu in | |
1640 | * case its halted. | |
1641 | */ | |
1642 | if (!qemu_cpu_self(env)) { | |
1643 | qemu_cpu_kick(env); | |
1644 | return; | |
1645 | } | |
1646 | #endif | |
1647 | ||
2e70f6ef | 1648 | if (use_icount) { |
266910c4 | 1649 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1650 | #ifndef CONFIG_USER_ONLY |
2e70f6ef | 1651 | if (!can_do_io(env) |
be214e6c | 1652 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1653 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1654 | } | |
1655 | #endif | |
1656 | } else { | |
3098dba0 | 1657 | cpu_unlink_tb(env); |
ea041c0e FB |
1658 | } |
1659 | } | |
1660 | ||
b54ad049 FB |
1661 | void cpu_reset_interrupt(CPUState *env, int mask) |
1662 | { | |
1663 | env->interrupt_request &= ~mask; | |
1664 | } | |
1665 | ||
3098dba0 AJ |
1666 | void cpu_exit(CPUState *env) |
1667 | { | |
1668 | env->exit_request = 1; | |
1669 | cpu_unlink_tb(env); | |
1670 | } | |
1671 | ||
c7cd6a37 | 1672 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1673 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1674 | "show generated host assembly code for each compiled TB" }, |
1675 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1676 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1677 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1678 | "show micro ops for each compiled TB" }, |
f193c797 | 1679 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1680 | "show micro ops " |
1681 | #ifdef TARGET_I386 | |
1682 | "before eflags optimization and " | |
f193c797 | 1683 | #endif |
e01a1157 | 1684 | "after liveness analysis" }, |
f193c797 FB |
1685 | { CPU_LOG_INT, "int", |
1686 | "show interrupts/exceptions in short format" }, | |
1687 | { CPU_LOG_EXEC, "exec", | |
1688 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1689 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1690 | "show CPU state before block translation" }, |
f193c797 FB |
1691 | #ifdef TARGET_I386 |
1692 | { CPU_LOG_PCALL, "pcall", | |
1693 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1694 | { CPU_LOG_RESET, "cpu_reset", |
1695 | "show CPU state before CPU resets" }, | |
f193c797 | 1696 | #endif |
8e3a9fd2 | 1697 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1698 | { CPU_LOG_IOPORT, "ioport", |
1699 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1700 | #endif |
f193c797 FB |
1701 | { 0, NULL, NULL }, |
1702 | }; | |
1703 | ||
f6f3fbca MT |
1704 | #ifndef CONFIG_USER_ONLY |
1705 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1706 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1707 | ||
1708 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
9742bf26 YT |
1709 | ram_addr_t size, |
1710 | ram_addr_t phys_offset) | |
f6f3fbca MT |
1711 | { |
1712 | CPUPhysMemoryClient *client; | |
1713 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1714 | client->set_memory(client, start_addr, size, phys_offset); | |
1715 | } | |
1716 | } | |
1717 | ||
1718 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
9742bf26 | 1719 | target_phys_addr_t end) |
f6f3fbca MT |
1720 | { |
1721 | CPUPhysMemoryClient *client; | |
1722 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1723 | int r = client->sync_dirty_bitmap(client, start, end); | |
1724 | if (r < 0) | |
1725 | return r; | |
1726 | } | |
1727 | return 0; | |
1728 | } | |
1729 | ||
1730 | static int cpu_notify_migration_log(int enable) | |
1731 | { | |
1732 | CPUPhysMemoryClient *client; | |
1733 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1734 | int r = client->migration_log(client, enable); | |
1735 | if (r < 0) | |
1736 | return r; | |
1737 | } | |
1738 | return 0; | |
1739 | } | |
1740 | ||
5cd2c5b6 RH |
1741 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, |
1742 | int level, void **lp) | |
f6f3fbca | 1743 | { |
5cd2c5b6 | 1744 | int i; |
f6f3fbca | 1745 | |
5cd2c5b6 RH |
1746 | if (*lp == NULL) { |
1747 | return; | |
1748 | } | |
1749 | if (level == 0) { | |
1750 | PhysPageDesc *pd = *lp; | |
7296abac | 1751 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
1752 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
1753 | client->set_memory(client, pd[i].region_offset, | |
1754 | TARGET_PAGE_SIZE, pd[i].phys_offset); | |
f6f3fbca | 1755 | } |
5cd2c5b6 RH |
1756 | } |
1757 | } else { | |
1758 | void **pp = *lp; | |
7296abac | 1759 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 | 1760 | phys_page_for_each_1(client, level - 1, pp + i); |
f6f3fbca MT |
1761 | } |
1762 | } | |
1763 | } | |
1764 | ||
1765 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1766 | { | |
5cd2c5b6 RH |
1767 | int i; |
1768 | for (i = 0; i < P_L1_SIZE; ++i) { | |
1769 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, | |
1770 | l1_phys_map + 1); | |
f6f3fbca | 1771 | } |
f6f3fbca MT |
1772 | } |
1773 | ||
1774 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1775 | { | |
1776 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1777 | phys_page_for_each(client); | |
1778 | } | |
1779 | ||
1780 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1781 | { | |
1782 | QLIST_REMOVE(client, list); | |
1783 | } | |
1784 | #endif | |
1785 | ||
f193c797 FB |
1786 | static int cmp1(const char *s1, int n, const char *s2) |
1787 | { | |
1788 | if (strlen(s2) != n) | |
1789 | return 0; | |
1790 | return memcmp(s1, s2, n) == 0; | |
1791 | } | |
3b46e624 | 1792 | |
f193c797 FB |
1793 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1794 | int cpu_str_to_log_mask(const char *str) | |
1795 | { | |
c7cd6a37 | 1796 | const CPULogItem *item; |
f193c797 FB |
1797 | int mask; |
1798 | const char *p, *p1; | |
1799 | ||
1800 | p = str; | |
1801 | mask = 0; | |
1802 | for(;;) { | |
1803 | p1 = strchr(p, ','); | |
1804 | if (!p1) | |
1805 | p1 = p + strlen(p); | |
9742bf26 YT |
1806 | if(cmp1(p,p1-p,"all")) { |
1807 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1808 | mask |= item->mask; | |
1809 | } | |
1810 | } else { | |
1811 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1812 | if (cmp1(p, p1 - p, item->name)) | |
1813 | goto found; | |
1814 | } | |
1815 | return 0; | |
f193c797 | 1816 | } |
f193c797 FB |
1817 | found: |
1818 | mask |= item->mask; | |
1819 | if (*p1 != ',') | |
1820 | break; | |
1821 | p = p1 + 1; | |
1822 | } | |
1823 | return mask; | |
1824 | } | |
ea041c0e | 1825 | |
7501267e FB |
1826 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1827 | { | |
1828 | va_list ap; | |
493ae1f0 | 1829 | va_list ap2; |
7501267e FB |
1830 | |
1831 | va_start(ap, fmt); | |
493ae1f0 | 1832 | va_copy(ap2, ap); |
7501267e FB |
1833 | fprintf(stderr, "qemu: fatal: "); |
1834 | vfprintf(stderr, fmt, ap); | |
1835 | fprintf(stderr, "\n"); | |
1836 | #ifdef TARGET_I386 | |
7fe48483 FB |
1837 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1838 | #else | |
1839 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1840 | #endif |
93fcfe39 AL |
1841 | if (qemu_log_enabled()) { |
1842 | qemu_log("qemu: fatal: "); | |
1843 | qemu_log_vprintf(fmt, ap2); | |
1844 | qemu_log("\n"); | |
f9373291 | 1845 | #ifdef TARGET_I386 |
93fcfe39 | 1846 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1847 | #else |
93fcfe39 | 1848 | log_cpu_state(env, 0); |
f9373291 | 1849 | #endif |
31b1a7b4 | 1850 | qemu_log_flush(); |
93fcfe39 | 1851 | qemu_log_close(); |
924edcae | 1852 | } |
493ae1f0 | 1853 | va_end(ap2); |
f9373291 | 1854 | va_end(ap); |
fd052bf6 RV |
1855 | #if defined(CONFIG_USER_ONLY) |
1856 | { | |
1857 | struct sigaction act; | |
1858 | sigfillset(&act.sa_mask); | |
1859 | act.sa_handler = SIG_DFL; | |
1860 | sigaction(SIGABRT, &act, NULL); | |
1861 | } | |
1862 | #endif | |
7501267e FB |
1863 | abort(); |
1864 | } | |
1865 | ||
c5be9f08 TS |
1866 | CPUState *cpu_copy(CPUState *env) |
1867 | { | |
01ba9816 | 1868 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1869 | CPUState *next_cpu = new_env->next_cpu; |
1870 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1871 | #if defined(TARGET_HAS_ICE) |
1872 | CPUBreakpoint *bp; | |
1873 | CPUWatchpoint *wp; | |
1874 | #endif | |
1875 | ||
c5be9f08 | 1876 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1877 | |
1878 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1879 | new_env->next_cpu = next_cpu; |
1880 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1881 | |
1882 | /* Clone all break/watchpoints. | |
1883 | Note: Once we support ptrace with hw-debug register access, make sure | |
1884 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1885 | QTAILQ_INIT(&env->breakpoints); |
1886 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1887 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1888 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1889 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1890 | } | |
72cf2d4f | 1891 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1892 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1893 | wp->flags, NULL); | |
1894 | } | |
1895 | #endif | |
1896 | ||
c5be9f08 TS |
1897 | return new_env; |
1898 | } | |
1899 | ||
0124311e FB |
1900 | #if !defined(CONFIG_USER_ONLY) |
1901 | ||
5c751e99 EI |
1902 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1903 | { | |
1904 | unsigned int i; | |
1905 | ||
1906 | /* Discard jump cache entries for any tb which might potentially | |
1907 | overlap the flushed page. */ | |
1908 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1909 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1910 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1911 | |
1912 | i = tb_jmp_cache_hash_page(addr); | |
1913 | memset (&env->tb_jmp_cache[i], 0, | |
9742bf26 | 1914 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
5c751e99 EI |
1915 | } |
1916 | ||
08738984 IK |
1917 | static CPUTLBEntry s_cputlb_empty_entry = { |
1918 | .addr_read = -1, | |
1919 | .addr_write = -1, | |
1920 | .addr_code = -1, | |
1921 | .addend = -1, | |
1922 | }; | |
1923 | ||
ee8b7021 FB |
1924 | /* NOTE: if flush_global is true, also flush global entries (not |
1925 | implemented yet) */ | |
1926 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1927 | { |
33417e70 | 1928 | int i; |
0124311e | 1929 | |
9fa3e853 FB |
1930 | #if defined(DEBUG_TLB) |
1931 | printf("tlb_flush:\n"); | |
1932 | #endif | |
0124311e FB |
1933 | /* must reset current TB so that interrupts cannot modify the |
1934 | links while we are modifying them */ | |
1935 | env->current_tb = NULL; | |
1936 | ||
33417e70 | 1937 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1938 | int mmu_idx; |
1939 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1940 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1941 | } |
33417e70 | 1942 | } |
9fa3e853 | 1943 | |
8a40a180 | 1944 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1945 | |
d4c430a8 PB |
1946 | env->tlb_flush_addr = -1; |
1947 | env->tlb_flush_mask = 0; | |
e3db7226 | 1948 | tlb_flush_count++; |
33417e70 FB |
1949 | } |
1950 | ||
274da6b2 | 1951 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1952 | { |
5fafdf24 | 1953 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1954 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1955 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1956 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1957 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 1958 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 1959 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 1960 | } |
61382a50 FB |
1961 | } |
1962 | ||
2e12669a | 1963 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1964 | { |
8a40a180 | 1965 | int i; |
cfde4bd9 | 1966 | int mmu_idx; |
0124311e | 1967 | |
9fa3e853 | 1968 | #if defined(DEBUG_TLB) |
108c49b8 | 1969 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1970 | #endif |
d4c430a8 PB |
1971 | /* Check if we need to flush due to large pages. */ |
1972 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { | |
1973 | #if defined(DEBUG_TLB) | |
1974 | printf("tlb_flush_page: forced full flush (" | |
1975 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", | |
1976 | env->tlb_flush_addr, env->tlb_flush_mask); | |
1977 | #endif | |
1978 | tlb_flush(env, 1); | |
1979 | return; | |
1980 | } | |
0124311e FB |
1981 | /* must reset current TB so that interrupts cannot modify the |
1982 | links while we are modifying them */ | |
1983 | env->current_tb = NULL; | |
61382a50 FB |
1984 | |
1985 | addr &= TARGET_PAGE_MASK; | |
1986 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
1987 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
1988 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 1989 | |
5c751e99 | 1990 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
1991 | } |
1992 | ||
9fa3e853 FB |
1993 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1994 | can be detected */ | |
c227f099 | 1995 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1996 | { |
5fafdf24 | 1997 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1998 | ram_addr + TARGET_PAGE_SIZE, |
1999 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
2000 | } |
2001 | ||
9fa3e853 | 2002 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 2003 | tested for self modifying code */ |
c227f099 | 2004 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 2005 | target_ulong vaddr) |
9fa3e853 | 2006 | { |
f7c11b53 | 2007 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
1ccde1cb FB |
2008 | } |
2009 | ||
5fafdf24 | 2010 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
2011 | unsigned long start, unsigned long length) |
2012 | { | |
2013 | unsigned long addr; | |
84b7b8e7 FB |
2014 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
2015 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 2016 | if ((addr - start) < length) { |
0f459d16 | 2017 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
2018 | } |
2019 | } | |
2020 | } | |
2021 | ||
5579c7f3 | 2022 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 2023 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 2024 | int dirty_flags) |
1ccde1cb FB |
2025 | { |
2026 | CPUState *env; | |
4f2ac237 | 2027 | unsigned long length, start1; |
f7c11b53 | 2028 | int i; |
1ccde1cb FB |
2029 | |
2030 | start &= TARGET_PAGE_MASK; | |
2031 | end = TARGET_PAGE_ALIGN(end); | |
2032 | ||
2033 | length = end - start; | |
2034 | if (length == 0) | |
2035 | return; | |
f7c11b53 | 2036 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
f23db169 | 2037 | |
1ccde1cb FB |
2038 | /* we modify the TLB cache so that the dirty bit will be set again |
2039 | when accessing the range */ | |
5579c7f3 PB |
2040 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
2041 | /* Chek that we don't span multiple blocks - this breaks the | |
2042 | address comparisons below. */ | |
2043 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 | |
2044 | != (end - 1) - start) { | |
2045 | abort(); | |
2046 | } | |
2047 | ||
6a00d601 | 2048 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
2049 | int mmu_idx; |
2050 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2051 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2052 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2053 | start1, length); | |
2054 | } | |
6a00d601 | 2055 | } |
1ccde1cb FB |
2056 | } |
2057 | ||
74576198 AL |
2058 | int cpu_physical_memory_set_dirty_tracking(int enable) |
2059 | { | |
f6f3fbca | 2060 | int ret = 0; |
74576198 | 2061 | in_migration = enable; |
f6f3fbca MT |
2062 | ret = cpu_notify_migration_log(!!enable); |
2063 | return ret; | |
74576198 AL |
2064 | } |
2065 | ||
2066 | int cpu_physical_memory_get_dirty_tracking(void) | |
2067 | { | |
2068 | return in_migration; | |
2069 | } | |
2070 | ||
c227f099 AL |
2071 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
2072 | target_phys_addr_t end_addr) | |
2bec46dc | 2073 | { |
7b8f3b78 | 2074 | int ret; |
151f7749 | 2075 | |
f6f3fbca | 2076 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
151f7749 | 2077 | return ret; |
2bec46dc AL |
2078 | } |
2079 | ||
3a7d929e FB |
2080 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2081 | { | |
c227f099 | 2082 | ram_addr_t ram_addr; |
5579c7f3 | 2083 | void *p; |
3a7d929e | 2084 | |
84b7b8e7 | 2085 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
2086 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2087 | + tlb_entry->addend); | |
e890261f | 2088 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
3a7d929e | 2089 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2090 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2091 | } |
2092 | } | |
2093 | } | |
2094 | ||
2095 | /* update the TLB according to the current state of the dirty bits */ | |
2096 | void cpu_tlb_update_dirty(CPUState *env) | |
2097 | { | |
2098 | int i; | |
cfde4bd9 IY |
2099 | int mmu_idx; |
2100 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2101 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2102 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2103 | } | |
3a7d929e FB |
2104 | } |
2105 | ||
0f459d16 | 2106 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2107 | { |
0f459d16 PB |
2108 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2109 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2110 | } |
2111 | ||
0f459d16 PB |
2112 | /* update the TLB corresponding to virtual page vaddr |
2113 | so that it is no longer dirty */ | |
2114 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2115 | { |
1ccde1cb | 2116 | int i; |
cfde4bd9 | 2117 | int mmu_idx; |
1ccde1cb | 2118 | |
0f459d16 | 2119 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2120 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2121 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2122 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2123 | } |
2124 | ||
d4c430a8 PB |
2125 | /* Our TLB does not support large pages, so remember the area covered by |
2126 | large pages and trigger a full TLB flush if these are invalidated. */ | |
2127 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, | |
2128 | target_ulong size) | |
2129 | { | |
2130 | target_ulong mask = ~(size - 1); | |
2131 | ||
2132 | if (env->tlb_flush_addr == (target_ulong)-1) { | |
2133 | env->tlb_flush_addr = vaddr & mask; | |
2134 | env->tlb_flush_mask = mask; | |
2135 | return; | |
2136 | } | |
2137 | /* Extend the existing region to include the new page. | |
2138 | This is a compromise between unnecessary flushes and the cost | |
2139 | of maintaining a full variable size TLB. */ | |
2140 | mask &= env->tlb_flush_mask; | |
2141 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { | |
2142 | mask <<= 1; | |
2143 | } | |
2144 | env->tlb_flush_addr &= mask; | |
2145 | env->tlb_flush_mask = mask; | |
2146 | } | |
2147 | ||
2148 | /* Add a new TLB entry. At most one entry for a given virtual address | |
2149 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the | |
2150 | supplied size is only used by tlb_flush_page. */ | |
2151 | void tlb_set_page(CPUState *env, target_ulong vaddr, | |
2152 | target_phys_addr_t paddr, int prot, | |
2153 | int mmu_idx, target_ulong size) | |
9fa3e853 | 2154 | { |
92e873b9 | 2155 | PhysPageDesc *p; |
4f2ac237 | 2156 | unsigned long pd; |
9fa3e853 | 2157 | unsigned int index; |
4f2ac237 | 2158 | target_ulong address; |
0f459d16 | 2159 | target_ulong code_address; |
355b1943 | 2160 | unsigned long addend; |
84b7b8e7 | 2161 | CPUTLBEntry *te; |
a1d1bb31 | 2162 | CPUWatchpoint *wp; |
c227f099 | 2163 | target_phys_addr_t iotlb; |
9fa3e853 | 2164 | |
d4c430a8 PB |
2165 | assert(size >= TARGET_PAGE_SIZE); |
2166 | if (size != TARGET_PAGE_SIZE) { | |
2167 | tlb_add_large_page(env, vaddr, size); | |
2168 | } | |
92e873b9 | 2169 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2170 | if (!p) { |
2171 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2172 | } else { |
2173 | pd = p->phys_offset; | |
9fa3e853 FB |
2174 | } |
2175 | #if defined(DEBUG_TLB) | |
7fd3f494 SW |
2176 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
2177 | " prot=%x idx=%d pd=0x%08lx\n", | |
2178 | vaddr, paddr, prot, mmu_idx, pd); | |
9fa3e853 FB |
2179 | #endif |
2180 | ||
0f459d16 PB |
2181 | address = vaddr; |
2182 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2183 | /* IO memory case (romd handled later) */ | |
2184 | address |= TLB_MMIO; | |
2185 | } | |
5579c7f3 | 2186 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2187 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2188 | /* Normal RAM. */ | |
2189 | iotlb = pd & TARGET_PAGE_MASK; | |
2190 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2191 | iotlb |= IO_MEM_NOTDIRTY; | |
2192 | else | |
2193 | iotlb |= IO_MEM_ROM; | |
2194 | } else { | |
ccbb4d44 | 2195 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2196 | It would be nice to pass an offset from the base address |
2197 | of that region. This would avoid having to special case RAM, | |
2198 | and avoid full address decoding in every device. | |
2199 | We can't use the high bits of pd for this because | |
2200 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2201 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2202 | if (p) { | |
8da3ff18 PB |
2203 | iotlb += p->region_offset; |
2204 | } else { | |
2205 | iotlb += paddr; | |
2206 | } | |
0f459d16 PB |
2207 | } |
2208 | ||
2209 | code_address = address; | |
2210 | /* Make accesses to pages with watchpoints go via the | |
2211 | watchpoint trap routines. */ | |
72cf2d4f | 2212 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2213 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
bf298f83 JK |
2214 | /* Avoid trapping reads of pages with a write breakpoint. */ |
2215 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
2216 | iotlb = io_mem_watch + paddr; | |
2217 | address |= TLB_MMIO; | |
2218 | break; | |
2219 | } | |
6658ffb8 | 2220 | } |
0f459d16 | 2221 | } |
d79acba4 | 2222 | |
0f459d16 PB |
2223 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2224 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2225 | te = &env->tlb_table[mmu_idx][index]; | |
2226 | te->addend = addend - vaddr; | |
2227 | if (prot & PAGE_READ) { | |
2228 | te->addr_read = address; | |
2229 | } else { | |
2230 | te->addr_read = -1; | |
2231 | } | |
5c751e99 | 2232 | |
0f459d16 PB |
2233 | if (prot & PAGE_EXEC) { |
2234 | te->addr_code = code_address; | |
2235 | } else { | |
2236 | te->addr_code = -1; | |
2237 | } | |
2238 | if (prot & PAGE_WRITE) { | |
2239 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2240 | (pd & IO_MEM_ROMD)) { | |
2241 | /* Write access calls the I/O callback. */ | |
2242 | te->addr_write = address | TLB_MMIO; | |
2243 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2244 | !cpu_physical_memory_is_dirty(pd)) { | |
2245 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2246 | } else { |
0f459d16 | 2247 | te->addr_write = address; |
9fa3e853 | 2248 | } |
0f459d16 PB |
2249 | } else { |
2250 | te->addr_write = -1; | |
9fa3e853 | 2251 | } |
9fa3e853 FB |
2252 | } |
2253 | ||
0124311e FB |
2254 | #else |
2255 | ||
ee8b7021 | 2256 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2257 | { |
2258 | } | |
2259 | ||
2e12669a | 2260 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2261 | { |
2262 | } | |
2263 | ||
edf8e2af MW |
2264 | /* |
2265 | * Walks guest process memory "regions" one by one | |
2266 | * and calls callback function 'fn' for each region. | |
2267 | */ | |
5cd2c5b6 RH |
2268 | |
2269 | struct walk_memory_regions_data | |
2270 | { | |
2271 | walk_memory_regions_fn fn; | |
2272 | void *priv; | |
2273 | unsigned long start; | |
2274 | int prot; | |
2275 | }; | |
2276 | ||
2277 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
b480d9b7 | 2278 | abi_ulong end, int new_prot) |
5cd2c5b6 RH |
2279 | { |
2280 | if (data->start != -1ul) { | |
2281 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2282 | if (rc != 0) { | |
2283 | return rc; | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | data->start = (new_prot ? end : -1ul); | |
2288 | data->prot = new_prot; | |
2289 | ||
2290 | return 0; | |
2291 | } | |
2292 | ||
2293 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
b480d9b7 | 2294 | abi_ulong base, int level, void **lp) |
5cd2c5b6 | 2295 | { |
b480d9b7 | 2296 | abi_ulong pa; |
5cd2c5b6 RH |
2297 | int i, rc; |
2298 | ||
2299 | if (*lp == NULL) { | |
2300 | return walk_memory_regions_end(data, base, 0); | |
2301 | } | |
2302 | ||
2303 | if (level == 0) { | |
2304 | PageDesc *pd = *lp; | |
7296abac | 2305 | for (i = 0; i < L2_SIZE; ++i) { |
5cd2c5b6 RH |
2306 | int prot = pd[i].flags; |
2307 | ||
2308 | pa = base | (i << TARGET_PAGE_BITS); | |
2309 | if (prot != data->prot) { | |
2310 | rc = walk_memory_regions_end(data, pa, prot); | |
2311 | if (rc != 0) { | |
2312 | return rc; | |
9fa3e853 | 2313 | } |
9fa3e853 | 2314 | } |
5cd2c5b6 RH |
2315 | } |
2316 | } else { | |
2317 | void **pp = *lp; | |
7296abac | 2318 | for (i = 0; i < L2_SIZE; ++i) { |
b480d9b7 PB |
2319 | pa = base | ((abi_ulong)i << |
2320 | (TARGET_PAGE_BITS + L2_BITS * level)); | |
5cd2c5b6 RH |
2321 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
2322 | if (rc != 0) { | |
2323 | return rc; | |
2324 | } | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
2331 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2332 | { | |
2333 | struct walk_memory_regions_data data; | |
2334 | unsigned long i; | |
2335 | ||
2336 | data.fn = fn; | |
2337 | data.priv = priv; | |
2338 | data.start = -1ul; | |
2339 | data.prot = 0; | |
2340 | ||
2341 | for (i = 0; i < V_L1_SIZE; i++) { | |
b480d9b7 | 2342 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
5cd2c5b6 RH |
2343 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
2344 | if (rc != 0) { | |
2345 | return rc; | |
9fa3e853 | 2346 | } |
33417e70 | 2347 | } |
5cd2c5b6 RH |
2348 | |
2349 | return walk_memory_regions_end(&data, 0, 0); | |
edf8e2af MW |
2350 | } |
2351 | ||
b480d9b7 PB |
2352 | static int dump_region(void *priv, abi_ulong start, |
2353 | abi_ulong end, unsigned long prot) | |
edf8e2af MW |
2354 | { |
2355 | FILE *f = (FILE *)priv; | |
2356 | ||
b480d9b7 PB |
2357 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
2358 | " "TARGET_ABI_FMT_lx" %c%c%c\n", | |
edf8e2af MW |
2359 | start, end, end - start, |
2360 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2361 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2362 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2363 | ||
2364 | return (0); | |
2365 | } | |
2366 | ||
2367 | /* dump memory mappings */ | |
2368 | void page_dump(FILE *f) | |
2369 | { | |
2370 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2371 | "start", "end", "size", "prot"); | |
2372 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2373 | } |
2374 | ||
53a5960a | 2375 | int page_get_flags(target_ulong address) |
33417e70 | 2376 | { |
9fa3e853 FB |
2377 | PageDesc *p; |
2378 | ||
2379 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2380 | if (!p) |
9fa3e853 FB |
2381 | return 0; |
2382 | return p->flags; | |
2383 | } | |
2384 | ||
376a7909 RH |
2385 | /* Modify the flags of a page and invalidate the code if necessary. |
2386 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2387 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
53a5960a | 2388 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 | 2389 | { |
376a7909 RH |
2390 | target_ulong addr, len; |
2391 | ||
2392 | /* This function should never be called with addresses outside the | |
2393 | guest address space. If this assert fires, it probably indicates | |
2394 | a missing call to h2g_valid. */ | |
b480d9b7 PB |
2395 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2396 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2397 | #endif |
2398 | assert(start < end); | |
9fa3e853 FB |
2399 | |
2400 | start = start & TARGET_PAGE_MASK; | |
2401 | end = TARGET_PAGE_ALIGN(end); | |
376a7909 RH |
2402 | |
2403 | if (flags & PAGE_WRITE) { | |
9fa3e853 | 2404 | flags |= PAGE_WRITE_ORG; |
376a7909 RH |
2405 | } |
2406 | ||
2407 | for (addr = start, len = end - start; | |
2408 | len != 0; | |
2409 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2410 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2411 | ||
2412 | /* If the write protection bit is set, then we invalidate | |
2413 | the code inside. */ | |
5fafdf24 | 2414 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2415 | (flags & PAGE_WRITE) && |
2416 | p->first_tb) { | |
d720b93d | 2417 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2418 | } |
2419 | p->flags = flags; | |
2420 | } | |
33417e70 FB |
2421 | } |
2422 | ||
3d97b40b TS |
2423 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2424 | { | |
2425 | PageDesc *p; | |
2426 | target_ulong end; | |
2427 | target_ulong addr; | |
2428 | ||
376a7909 RH |
2429 | /* This function should never be called with addresses outside the |
2430 | guest address space. If this assert fires, it probably indicates | |
2431 | a missing call to h2g_valid. */ | |
338e9e6c BS |
2432 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
2433 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); | |
376a7909 RH |
2434 | #endif |
2435 | ||
3e0650a9 RH |
2436 | if (len == 0) { |
2437 | return 0; | |
2438 | } | |
376a7909 RH |
2439 | if (start + len - 1 < start) { |
2440 | /* We've wrapped around. */ | |
55f280c9 | 2441 | return -1; |
376a7909 | 2442 | } |
55f280c9 | 2443 | |
3d97b40b TS |
2444 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2445 | start = start & TARGET_PAGE_MASK; | |
2446 | ||
376a7909 RH |
2447 | for (addr = start, len = end - start; |
2448 | len != 0; | |
2449 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
3d97b40b TS |
2450 | p = page_find(addr >> TARGET_PAGE_BITS); |
2451 | if( !p ) | |
2452 | return -1; | |
2453 | if( !(p->flags & PAGE_VALID) ) | |
2454 | return -1; | |
2455 | ||
dae3270c | 2456 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2457 | return -1; |
dae3270c FB |
2458 | if (flags & PAGE_WRITE) { |
2459 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2460 | return -1; | |
2461 | /* unprotect the page if it was put read-only because it | |
2462 | contains translated code */ | |
2463 | if (!(p->flags & PAGE_WRITE)) { | |
2464 | if (!page_unprotect(addr, 0, NULL)) | |
2465 | return -1; | |
2466 | } | |
2467 | return 0; | |
2468 | } | |
3d97b40b TS |
2469 | } |
2470 | return 0; | |
2471 | } | |
2472 | ||
9fa3e853 | 2473 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2474 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2475 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 | 2476 | { |
45d679d6 AJ |
2477 | unsigned int prot; |
2478 | PageDesc *p; | |
53a5960a | 2479 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2480 | |
c8a706fe PB |
2481 | /* Technically this isn't safe inside a signal handler. However we |
2482 | know this only ever happens in a synchronous SEGV handler, so in | |
2483 | practice it seems to be ok. */ | |
2484 | mmap_lock(); | |
2485 | ||
45d679d6 AJ |
2486 | p = page_find(address >> TARGET_PAGE_BITS); |
2487 | if (!p) { | |
c8a706fe | 2488 | mmap_unlock(); |
9fa3e853 | 2489 | return 0; |
c8a706fe | 2490 | } |
45d679d6 | 2491 | |
9fa3e853 FB |
2492 | /* if the page was really writable, then we change its |
2493 | protection back to writable */ | |
45d679d6 AJ |
2494 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
2495 | host_start = address & qemu_host_page_mask; | |
2496 | host_end = host_start + qemu_host_page_size; | |
2497 | ||
2498 | prot = 0; | |
2499 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
2500 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2501 | p->flags |= PAGE_WRITE; | |
2502 | prot |= p->flags; | |
2503 | ||
9fa3e853 FB |
2504 | /* and since the content will be modified, we must invalidate |
2505 | the corresponding translated code. */ | |
45d679d6 | 2506 | tb_invalidate_phys_page(addr, pc, puc); |
9fa3e853 | 2507 | #ifdef DEBUG_TB_CHECK |
45d679d6 | 2508 | tb_invalidate_check(addr); |
9fa3e853 | 2509 | #endif |
9fa3e853 | 2510 | } |
45d679d6 AJ |
2511 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
2512 | prot & PAGE_BITS); | |
2513 | ||
2514 | mmap_unlock(); | |
2515 | return 1; | |
9fa3e853 | 2516 | } |
c8a706fe | 2517 | mmap_unlock(); |
9fa3e853 FB |
2518 | return 0; |
2519 | } | |
2520 | ||
6a00d601 FB |
2521 | static inline void tlb_set_dirty(CPUState *env, |
2522 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2523 | { |
2524 | } | |
9fa3e853 FB |
2525 | #endif /* defined(CONFIG_USER_ONLY) */ |
2526 | ||
e2eef170 | 2527 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2528 | |
c04b2b78 PB |
2529 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2530 | typedef struct subpage_t { | |
2531 | target_phys_addr_t base; | |
f6405247 RH |
2532 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
2533 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; | |
c04b2b78 PB |
2534 | } subpage_t; |
2535 | ||
c227f099 AL |
2536 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2537 | ram_addr_t memory, ram_addr_t region_offset); | |
f6405247 RH |
2538 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
2539 | ram_addr_t orig_memory, | |
2540 | ram_addr_t region_offset); | |
db7b5426 BS |
2541 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2542 | need_subpage) \ | |
2543 | do { \ | |
2544 | if (addr > start_addr) \ | |
2545 | start_addr2 = 0; \ | |
2546 | else { \ | |
2547 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2548 | if (start_addr2 > 0) \ | |
2549 | need_subpage = 1; \ | |
2550 | } \ | |
2551 | \ | |
49e9fba2 | 2552 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2553 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2554 | else { \ | |
2555 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2556 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2557 | need_subpage = 1; \ | |
2558 | } \ | |
2559 | } while (0) | |
2560 | ||
8f2498f9 MT |
2561 | /* register physical memory. |
2562 | For RAM, 'size' must be a multiple of the target page size. | |
2563 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2564 | io memory page. The address used when calling the IO function is |
2565 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2566 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2567 | before calculating this offset. This should not be a problem unless |
2568 | the low bits of start_addr and region_offset differ. */ | |
c227f099 AL |
2569 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
2570 | ram_addr_t size, | |
2571 | ram_addr_t phys_offset, | |
2572 | ram_addr_t region_offset) | |
33417e70 | 2573 | { |
c227f099 | 2574 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2575 | PhysPageDesc *p; |
9d42037b | 2576 | CPUState *env; |
c227f099 | 2577 | ram_addr_t orig_size = size; |
f6405247 | 2578 | subpage_t *subpage; |
33417e70 | 2579 | |
f6f3fbca MT |
2580 | cpu_notify_set_memory(start_addr, size, phys_offset); |
2581 | ||
67c4d23c PB |
2582 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2583 | region_offset = start_addr; | |
2584 | } | |
8da3ff18 | 2585 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2586 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2587 | end_addr = start_addr + (target_phys_addr_t)size; |
49e9fba2 | 2588 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
db7b5426 BS |
2589 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2590 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2591 | ram_addr_t orig_memory = p->phys_offset; |
2592 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2593 | int need_subpage = 0; |
2594 | ||
2595 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2596 | need_subpage); | |
f6405247 | 2597 | if (need_subpage) { |
db7b5426 BS |
2598 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2599 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2600 | &p->phys_offset, orig_memory, |
2601 | p->region_offset); | |
db7b5426 BS |
2602 | } else { |
2603 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2604 | >> IO_MEM_SHIFT]; | |
2605 | } | |
8da3ff18 PB |
2606 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2607 | region_offset); | |
2608 | p->region_offset = 0; | |
db7b5426 BS |
2609 | } else { |
2610 | p->phys_offset = phys_offset; | |
2611 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2612 | (phys_offset & IO_MEM_ROMD)) | |
2613 | phys_offset += TARGET_PAGE_SIZE; | |
2614 | } | |
2615 | } else { | |
2616 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2617 | p->phys_offset = phys_offset; | |
8da3ff18 | 2618 | p->region_offset = region_offset; |
db7b5426 | 2619 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2620 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2621 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2622 | } else { |
c227f099 | 2623 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2624 | int need_subpage = 0; |
2625 | ||
2626 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2627 | end_addr2, need_subpage); | |
2628 | ||
f6405247 | 2629 | if (need_subpage) { |
db7b5426 | 2630 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2631 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2632 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2633 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2634 | phys_offset, region_offset); |
2635 | p->region_offset = 0; | |
db7b5426 BS |
2636 | } |
2637 | } | |
2638 | } | |
8da3ff18 | 2639 | region_offset += TARGET_PAGE_SIZE; |
33417e70 | 2640 | } |
3b46e624 | 2641 | |
9d42037b FB |
2642 | /* since each CPU stores ram addresses in its TLB cache, we must |
2643 | reset the modified entries */ | |
2644 | /* XXX: slow ! */ | |
2645 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2646 | tlb_flush(env, 1); | |
2647 | } | |
33417e70 FB |
2648 | } |
2649 | ||
ba863458 | 2650 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2651 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2652 | { |
2653 | PhysPageDesc *p; | |
2654 | ||
2655 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2656 | if (!p) | |
2657 | return IO_MEM_UNASSIGNED; | |
2658 | return p->phys_offset; | |
2659 | } | |
2660 | ||
c227f099 | 2661 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2662 | { |
2663 | if (kvm_enabled()) | |
2664 | kvm_coalesce_mmio_region(addr, size); | |
2665 | } | |
2666 | ||
c227f099 | 2667 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2668 | { |
2669 | if (kvm_enabled()) | |
2670 | kvm_uncoalesce_mmio_region(addr, size); | |
2671 | } | |
2672 | ||
62a2744c SY |
2673 | void qemu_flush_coalesced_mmio_buffer(void) |
2674 | { | |
2675 | if (kvm_enabled()) | |
2676 | kvm_flush_coalesced_mmio_buffer(); | |
2677 | } | |
2678 | ||
c902760f MT |
2679 | #if defined(__linux__) && !defined(TARGET_S390X) |
2680 | ||
2681 | #include <sys/vfs.h> | |
2682 | ||
2683 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2684 | ||
2685 | static long gethugepagesize(const char *path) | |
2686 | { | |
2687 | struct statfs fs; | |
2688 | int ret; | |
2689 | ||
2690 | do { | |
9742bf26 | 2691 | ret = statfs(path, &fs); |
c902760f MT |
2692 | } while (ret != 0 && errno == EINTR); |
2693 | ||
2694 | if (ret != 0) { | |
9742bf26 YT |
2695 | perror(path); |
2696 | return 0; | |
c902760f MT |
2697 | } |
2698 | ||
2699 | if (fs.f_type != HUGETLBFS_MAGIC) | |
9742bf26 | 2700 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
c902760f MT |
2701 | |
2702 | return fs.f_bsize; | |
2703 | } | |
2704 | ||
04b16653 AW |
2705 | static void *file_ram_alloc(RAMBlock *block, |
2706 | ram_addr_t memory, | |
2707 | const char *path) | |
c902760f MT |
2708 | { |
2709 | char *filename; | |
2710 | void *area; | |
2711 | int fd; | |
2712 | #ifdef MAP_POPULATE | |
2713 | int flags; | |
2714 | #endif | |
2715 | unsigned long hpagesize; | |
2716 | ||
2717 | hpagesize = gethugepagesize(path); | |
2718 | if (!hpagesize) { | |
9742bf26 | 2719 | return NULL; |
c902760f MT |
2720 | } |
2721 | ||
2722 | if (memory < hpagesize) { | |
2723 | return NULL; | |
2724 | } | |
2725 | ||
2726 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2727 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2728 | return NULL; | |
2729 | } | |
2730 | ||
2731 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
9742bf26 | 2732 | return NULL; |
c902760f MT |
2733 | } |
2734 | ||
2735 | fd = mkstemp(filename); | |
2736 | if (fd < 0) { | |
9742bf26 YT |
2737 | perror("unable to create backing store for hugepages"); |
2738 | free(filename); | |
2739 | return NULL; | |
c902760f MT |
2740 | } |
2741 | unlink(filename); | |
2742 | free(filename); | |
2743 | ||
2744 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2745 | ||
2746 | /* | |
2747 | * ftruncate is not supported by hugetlbfs in older | |
2748 | * hosts, so don't bother bailing out on errors. | |
2749 | * If anything goes wrong with it under other filesystems, | |
2750 | * mmap will fail. | |
2751 | */ | |
2752 | if (ftruncate(fd, memory)) | |
9742bf26 | 2753 | perror("ftruncate"); |
c902760f MT |
2754 | |
2755 | #ifdef MAP_POPULATE | |
2756 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2757 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2758 | * to sidestep this quirk. | |
2759 | */ | |
2760 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2761 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2762 | #else | |
2763 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2764 | #endif | |
2765 | if (area == MAP_FAILED) { | |
9742bf26 YT |
2766 | perror("file_ram_alloc: can't mmap RAM pages"); |
2767 | close(fd); | |
2768 | return (NULL); | |
c902760f | 2769 | } |
04b16653 | 2770 | block->fd = fd; |
c902760f MT |
2771 | return area; |
2772 | } | |
2773 | #endif | |
2774 | ||
d17b5288 | 2775 | static ram_addr_t find_ram_offset(ram_addr_t size) |
04b16653 AW |
2776 | { |
2777 | RAMBlock *block, *next_block; | |
09d7ae90 | 2778 | ram_addr_t offset = 0, mingap = ULONG_MAX; |
04b16653 AW |
2779 | |
2780 | if (QLIST_EMPTY(&ram_list.blocks)) | |
2781 | return 0; | |
2782 | ||
2783 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2784 | ram_addr_t end, next = ULONG_MAX; | |
2785 | ||
2786 | end = block->offset + block->length; | |
2787 | ||
2788 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { | |
2789 | if (next_block->offset >= end) { | |
2790 | next = MIN(next, next_block->offset); | |
2791 | } | |
2792 | } | |
2793 | if (next - end >= size && next - end < mingap) { | |
2794 | offset = end; | |
2795 | mingap = next - end; | |
2796 | } | |
2797 | } | |
2798 | return offset; | |
2799 | } | |
2800 | ||
2801 | static ram_addr_t last_ram_offset(void) | |
d17b5288 AW |
2802 | { |
2803 | RAMBlock *block; | |
2804 | ram_addr_t last = 0; | |
2805 | ||
2806 | QLIST_FOREACH(block, &ram_list.blocks, next) | |
2807 | last = MAX(last, block->offset + block->length); | |
2808 | ||
2809 | return last; | |
2810 | } | |
2811 | ||
84b89d78 | 2812 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
6977dfe6 | 2813 | ram_addr_t size, void *host) |
84b89d78 CM |
2814 | { |
2815 | RAMBlock *new_block, *block; | |
2816 | ||
2817 | size = TARGET_PAGE_ALIGN(size); | |
2818 | new_block = qemu_mallocz(sizeof(*new_block)); | |
2819 | ||
2820 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { | |
2821 | char *id = dev->parent_bus->info->get_dev_path(dev); | |
2822 | if (id) { | |
2823 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
2824 | qemu_free(id); | |
2825 | } | |
2826 | } | |
2827 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
2828 | ||
2829 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2830 | if (!strcmp(block->idstr, new_block->idstr)) { | |
2831 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", | |
2832 | new_block->idstr); | |
2833 | abort(); | |
2834 | } | |
2835 | } | |
2836 | ||
6977dfe6 YT |
2837 | if (host) { |
2838 | new_block->host = host; | |
2839 | } else { | |
2840 | if (mem_path) { | |
c902760f | 2841 | #if defined (__linux__) && !defined(TARGET_S390X) |
6977dfe6 YT |
2842 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
2843 | if (!new_block->host) { | |
2844 | new_block->host = qemu_vmalloc(size); | |
e78815a5 | 2845 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2846 | } |
c902760f | 2847 | #else |
6977dfe6 YT |
2848 | fprintf(stderr, "-mem-path option unsupported\n"); |
2849 | exit(1); | |
c902760f | 2850 | #endif |
6977dfe6 | 2851 | } else { |
6b02494d | 2852 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
6977dfe6 YT |
2853 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ |
2854 | new_block->host = mmap((void*)0x1000000, size, | |
2855 | PROT_EXEC|PROT_READ|PROT_WRITE, | |
2856 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
6b02494d | 2857 | #else |
6977dfe6 | 2858 | new_block->host = qemu_vmalloc(size); |
6b02494d | 2859 | #endif |
e78815a5 | 2860 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
6977dfe6 | 2861 | } |
c902760f | 2862 | } |
6977dfe6 | 2863 | |
d17b5288 | 2864 | new_block->offset = find_ram_offset(size); |
94a6b54f PB |
2865 | new_block->length = size; |
2866 | ||
f471a17e | 2867 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
94a6b54f | 2868 | |
f471a17e | 2869 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, |
04b16653 | 2870 | last_ram_offset() >> TARGET_PAGE_BITS); |
d17b5288 | 2871 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
94a6b54f PB |
2872 | 0xff, size >> TARGET_PAGE_BITS); |
2873 | ||
6f0437e8 JK |
2874 | if (kvm_enabled()) |
2875 | kvm_setup_guest_memory(new_block->host, size); | |
2876 | ||
94a6b54f PB |
2877 | return new_block->offset; |
2878 | } | |
e9a1ab19 | 2879 | |
6977dfe6 YT |
2880 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) |
2881 | { | |
2882 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); | |
2883 | } | |
2884 | ||
c227f099 | 2885 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2886 | { |
04b16653 AW |
2887 | RAMBlock *block; |
2888 | ||
2889 | QLIST_FOREACH(block, &ram_list.blocks, next) { | |
2890 | if (addr == block->offset) { | |
2891 | QLIST_REMOVE(block, next); | |
2892 | if (mem_path) { | |
2893 | #if defined (__linux__) && !defined(TARGET_S390X) | |
2894 | if (block->fd) { | |
2895 | munmap(block->host, block->length); | |
2896 | close(block->fd); | |
2897 | } else { | |
2898 | qemu_vfree(block->host); | |
2899 | } | |
2900 | #endif | |
2901 | } else { | |
2902 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) | |
2903 | munmap(block->host, block->length); | |
2904 | #else | |
2905 | qemu_vfree(block->host); | |
2906 | #endif | |
2907 | } | |
2908 | qemu_free(block); | |
2909 | return; | |
2910 | } | |
2911 | } | |
2912 | ||
e9a1ab19 FB |
2913 | } |
2914 | ||
dc828ca1 | 2915 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
2916 | With the exception of the softmmu code in this file, this should |
2917 | only be used for local memory (e.g. video ram) that the device owns, | |
2918 | and knows it isn't going to access beyond the end of the block. | |
2919 | ||
2920 | It should not be used for general purpose DMA. | |
2921 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
2922 | */ | |
c227f099 | 2923 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 2924 | { |
94a6b54f PB |
2925 | RAMBlock *block; |
2926 | ||
f471a17e AW |
2927 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
2928 | if (addr - block->offset < block->length) { | |
2929 | QLIST_REMOVE(block, next); | |
2930 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); | |
2931 | return block->host + (addr - block->offset); | |
2932 | } | |
94a6b54f | 2933 | } |
f471a17e AW |
2934 | |
2935 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
2936 | abort(); | |
2937 | ||
2938 | return NULL; | |
dc828ca1 PB |
2939 | } |
2940 | ||
e890261f | 2941 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
5579c7f3 | 2942 | { |
94a6b54f PB |
2943 | RAMBlock *block; |
2944 | uint8_t *host = ptr; | |
2945 | ||
f471a17e AW |
2946 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
2947 | if (host - block->host < block->length) { | |
e890261f MT |
2948 | *ram_addr = block->offset + (host - block->host); |
2949 | return 0; | |
f471a17e | 2950 | } |
94a6b54f | 2951 | } |
e890261f MT |
2952 | return -1; |
2953 | } | |
f471a17e | 2954 | |
e890261f MT |
2955 | /* Some of the softmmu routines need to translate from a host pointer |
2956 | (typically a TLB entry) back to a ram offset. */ | |
2957 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) | |
2958 | { | |
2959 | ram_addr_t ram_addr; | |
f471a17e | 2960 | |
e890261f MT |
2961 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
2962 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
2963 | abort(); | |
2964 | } | |
2965 | return ram_addr; | |
5579c7f3 PB |
2966 | } |
2967 | ||
c227f099 | 2968 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2969 | { |
67d3b957 | 2970 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2971 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2972 | #endif |
faed1c2a | 2973 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2974 | do_unassigned_access(addr, 0, 0, 0, 1); |
2975 | #endif | |
2976 | return 0; | |
2977 | } | |
2978 | ||
c227f099 | 2979 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2980 | { |
2981 | #ifdef DEBUG_UNASSIGNED | |
2982 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2983 | #endif | |
faed1c2a | 2984 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2985 | do_unassigned_access(addr, 0, 0, 0, 2); |
2986 | #endif | |
2987 | return 0; | |
2988 | } | |
2989 | ||
c227f099 | 2990 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2991 | { |
2992 | #ifdef DEBUG_UNASSIGNED | |
2993 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2994 | #endif | |
faed1c2a | 2995 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2996 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 2997 | #endif |
33417e70 FB |
2998 | return 0; |
2999 | } | |
3000 | ||
c227f099 | 3001 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 3002 | { |
67d3b957 | 3003 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 3004 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 3005 | #endif |
faed1c2a | 3006 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3007 | do_unassigned_access(addr, 1, 0, 0, 1); |
3008 | #endif | |
3009 | } | |
3010 | ||
c227f099 | 3011 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
3012 | { |
3013 | #ifdef DEBUG_UNASSIGNED | |
3014 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3015 | #endif | |
faed1c2a | 3016 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
3017 | do_unassigned_access(addr, 1, 0, 0, 2); |
3018 | #endif | |
3019 | } | |
3020 | ||
c227f099 | 3021 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
3022 | { |
3023 | #ifdef DEBUG_UNASSIGNED | |
3024 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
3025 | #endif | |
faed1c2a | 3026 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 3027 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 3028 | #endif |
33417e70 FB |
3029 | } |
3030 | ||
d60efc6b | 3031 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 3032 | unassigned_mem_readb, |
e18231a3 BS |
3033 | unassigned_mem_readw, |
3034 | unassigned_mem_readl, | |
33417e70 FB |
3035 | }; |
3036 | ||
d60efc6b | 3037 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 3038 | unassigned_mem_writeb, |
e18231a3 BS |
3039 | unassigned_mem_writew, |
3040 | unassigned_mem_writel, | |
33417e70 FB |
3041 | }; |
3042 | ||
c227f099 | 3043 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3044 | uint32_t val) |
9fa3e853 | 3045 | { |
3a7d929e | 3046 | int dirty_flags; |
f7c11b53 | 3047 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3048 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3049 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3050 | tb_invalidate_phys_page_fast(ram_addr, 1); |
f7c11b53 | 3051 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3052 | #endif |
3a7d929e | 3053 | } |
5579c7f3 | 3054 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3055 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3056 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3057 | /* we remove the notdirty callback only if the code has been |
3058 | flushed */ | |
3059 | if (dirty_flags == 0xff) | |
2e70f6ef | 3060 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3061 | } |
3062 | ||
c227f099 | 3063 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3064 | uint32_t val) |
9fa3e853 | 3065 | { |
3a7d929e | 3066 | int dirty_flags; |
f7c11b53 | 3067 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3068 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3069 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3070 | tb_invalidate_phys_page_fast(ram_addr, 2); |
f7c11b53 | 3071 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3072 | #endif |
3a7d929e | 3073 | } |
5579c7f3 | 3074 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3075 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3076 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3077 | /* we remove the notdirty callback only if the code has been |
3078 | flushed */ | |
3079 | if (dirty_flags == 0xff) | |
2e70f6ef | 3080 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3081 | } |
3082 | ||
c227f099 | 3083 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 3084 | uint32_t val) |
9fa3e853 | 3085 | { |
3a7d929e | 3086 | int dirty_flags; |
f7c11b53 | 3087 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
3a7d929e | 3088 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
9fa3e853 | 3089 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e | 3090 | tb_invalidate_phys_page_fast(ram_addr, 4); |
f7c11b53 | 3091 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
9fa3e853 | 3092 | #endif |
3a7d929e | 3093 | } |
5579c7f3 | 3094 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 | 3095 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
f7c11b53 | 3096 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
f23db169 FB |
3097 | /* we remove the notdirty callback only if the code has been |
3098 | flushed */ | |
3099 | if (dirty_flags == 0xff) | |
2e70f6ef | 3100 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
3101 | } |
3102 | ||
d60efc6b | 3103 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
3104 | NULL, /* never used */ |
3105 | NULL, /* never used */ | |
3106 | NULL, /* never used */ | |
3107 | }; | |
3108 | ||
d60efc6b | 3109 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
3110 | notdirty_mem_writeb, |
3111 | notdirty_mem_writew, | |
3112 | notdirty_mem_writel, | |
3113 | }; | |
3114 | ||
0f459d16 | 3115 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 3116 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
3117 | { |
3118 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
3119 | target_ulong pc, cs_base; |
3120 | TranslationBlock *tb; | |
0f459d16 | 3121 | target_ulong vaddr; |
a1d1bb31 | 3122 | CPUWatchpoint *wp; |
06d55cc1 | 3123 | int cpu_flags; |
0f459d16 | 3124 | |
06d55cc1 AL |
3125 | if (env->watchpoint_hit) { |
3126 | /* We re-entered the check after replacing the TB. Now raise | |
3127 | * the debug interrupt so that is will trigger after the | |
3128 | * current instruction. */ | |
3129 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
3130 | return; | |
3131 | } | |
2e70f6ef | 3132 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 3133 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
3134 | if ((vaddr == (wp->vaddr & len_mask) || |
3135 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
3136 | wp->flags |= BP_WATCHPOINT_HIT; |
3137 | if (!env->watchpoint_hit) { | |
3138 | env->watchpoint_hit = wp; | |
3139 | tb = tb_find_pc(env->mem_io_pc); | |
3140 | if (!tb) { | |
3141 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
3142 | "pc=%p", (void *)env->mem_io_pc); | |
3143 | } | |
3144 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); | |
3145 | tb_phys_invalidate(tb, -1); | |
3146 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
3147 | env->exception_index = EXCP_DEBUG; | |
3148 | } else { | |
3149 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
3150 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
3151 | } | |
3152 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 3153 | } |
6e140f28 AL |
3154 | } else { |
3155 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
3156 | } |
3157 | } | |
3158 | } | |
3159 | ||
6658ffb8 PB |
3160 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
3161 | so these check for a hit then pass through to the normal out-of-line | |
3162 | phys routines. */ | |
c227f099 | 3163 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3164 | { |
b4051334 | 3165 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
3166 | return ldub_phys(addr); |
3167 | } | |
3168 | ||
c227f099 | 3169 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3170 | { |
b4051334 | 3171 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
3172 | return lduw_phys(addr); |
3173 | } | |
3174 | ||
c227f099 | 3175 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3176 | { |
b4051334 | 3177 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
3178 | return ldl_phys(addr); |
3179 | } | |
3180 | ||
c227f099 | 3181 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3182 | uint32_t val) |
3183 | { | |
b4051334 | 3184 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
3185 | stb_phys(addr, val); |
3186 | } | |
3187 | ||
c227f099 | 3188 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3189 | uint32_t val) |
3190 | { | |
b4051334 | 3191 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
3192 | stw_phys(addr, val); |
3193 | } | |
3194 | ||
c227f099 | 3195 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3196 | uint32_t val) |
3197 | { | |
b4051334 | 3198 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
3199 | stl_phys(addr, val); |
3200 | } | |
3201 | ||
d60efc6b | 3202 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
3203 | watch_mem_readb, |
3204 | watch_mem_readw, | |
3205 | watch_mem_readl, | |
3206 | }; | |
3207 | ||
d60efc6b | 3208 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
3209 | watch_mem_writeb, |
3210 | watch_mem_writew, | |
3211 | watch_mem_writel, | |
3212 | }; | |
6658ffb8 | 3213 | |
f6405247 RH |
3214 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
3215 | target_phys_addr_t addr, | |
3216 | unsigned int len) | |
db7b5426 | 3217 | { |
f6405247 | 3218 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
3219 | #if defined(DEBUG_SUBPAGE) |
3220 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3221 | mmio, len, addr, idx); | |
3222 | #endif | |
db7b5426 | 3223 | |
f6405247 RH |
3224 | addr += mmio->region_offset[idx]; |
3225 | idx = mmio->sub_io_index[idx]; | |
3226 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); | |
db7b5426 BS |
3227 | } |
3228 | ||
c227f099 | 3229 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
f6405247 | 3230 | uint32_t value, unsigned int len) |
db7b5426 | 3231 | { |
f6405247 | 3232 | unsigned int idx = SUBPAGE_IDX(addr); |
db7b5426 | 3233 | #if defined(DEBUG_SUBPAGE) |
f6405247 RH |
3234 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
3235 | __func__, mmio, len, addr, idx, value); | |
db7b5426 | 3236 | #endif |
f6405247 RH |
3237 | |
3238 | addr += mmio->region_offset[idx]; | |
3239 | idx = mmio->sub_io_index[idx]; | |
3240 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); | |
db7b5426 BS |
3241 | } |
3242 | ||
c227f099 | 3243 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3244 | { |
db7b5426 BS |
3245 | return subpage_readlen(opaque, addr, 0); |
3246 | } | |
3247 | ||
c227f099 | 3248 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3249 | uint32_t value) |
3250 | { | |
db7b5426 BS |
3251 | subpage_writelen(opaque, addr, value, 0); |
3252 | } | |
3253 | ||
c227f099 | 3254 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3255 | { |
db7b5426 BS |
3256 | return subpage_readlen(opaque, addr, 1); |
3257 | } | |
3258 | ||
c227f099 | 3259 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3260 | uint32_t value) |
3261 | { | |
db7b5426 BS |
3262 | subpage_writelen(opaque, addr, value, 1); |
3263 | } | |
3264 | ||
c227f099 | 3265 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 | 3266 | { |
db7b5426 BS |
3267 | return subpage_readlen(opaque, addr, 2); |
3268 | } | |
3269 | ||
f6405247 RH |
3270 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
3271 | uint32_t value) | |
db7b5426 | 3272 | { |
db7b5426 BS |
3273 | subpage_writelen(opaque, addr, value, 2); |
3274 | } | |
3275 | ||
d60efc6b | 3276 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
3277 | &subpage_readb, |
3278 | &subpage_readw, | |
3279 | &subpage_readl, | |
3280 | }; | |
3281 | ||
d60efc6b | 3282 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
3283 | &subpage_writeb, |
3284 | &subpage_writew, | |
3285 | &subpage_writel, | |
3286 | }; | |
3287 | ||
c227f099 AL |
3288 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
3289 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
3290 | { |
3291 | int idx, eidx; | |
3292 | ||
3293 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3294 | return -1; | |
3295 | idx = SUBPAGE_IDX(start); | |
3296 | eidx = SUBPAGE_IDX(end); | |
3297 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 3298 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
3299 | mmio, start, end, idx, eidx, memory); |
3300 | #endif | |
95c318f5 GN |
3301 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
3302 | memory = IO_MEM_UNASSIGNED; | |
f6405247 | 3303 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
db7b5426 | 3304 | for (; idx <= eidx; idx++) { |
f6405247 RH |
3305 | mmio->sub_io_index[idx] = memory; |
3306 | mmio->region_offset[idx] = region_offset; | |
db7b5426 BS |
3307 | } |
3308 | ||
3309 | return 0; | |
3310 | } | |
3311 | ||
f6405247 RH |
3312 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
3313 | ram_addr_t orig_memory, | |
3314 | ram_addr_t region_offset) | |
db7b5426 | 3315 | { |
c227f099 | 3316 | subpage_t *mmio; |
db7b5426 BS |
3317 | int subpage_memory; |
3318 | ||
c227f099 | 3319 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
3320 | |
3321 | mmio->base = base; | |
1eed09cb | 3322 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
db7b5426 | 3323 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3324 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3325 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3326 | #endif |
1eec614b | 3327 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
f6405247 | 3328 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
db7b5426 BS |
3329 | |
3330 | return mmio; | |
3331 | } | |
3332 | ||
88715657 AL |
3333 | static int get_free_io_mem_idx(void) |
3334 | { | |
3335 | int i; | |
3336 | ||
3337 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3338 | if (!io_mem_used[i]) { | |
3339 | io_mem_used[i] = 1; | |
3340 | return i; | |
3341 | } | |
c6703b47 | 3342 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3343 | return -1; |
3344 | } | |
3345 | ||
33417e70 FB |
3346 | /* mem_read and mem_write are arrays of functions containing the |
3347 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3348 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3349 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3350 | modified. If it is zero, a new io zone is allocated. The return |
3351 | value can be used with cpu_register_physical_memory(). (-1) is | |
3352 | returned if error. */ | |
1eed09cb | 3353 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
3354 | CPUReadMemoryFunc * const *mem_read, |
3355 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb | 3356 | void *opaque) |
33417e70 | 3357 | { |
3cab721d RH |
3358 | int i; |
3359 | ||
33417e70 | 3360 | if (io_index <= 0) { |
88715657 AL |
3361 | io_index = get_free_io_mem_idx(); |
3362 | if (io_index == -1) | |
3363 | return io_index; | |
33417e70 | 3364 | } else { |
1eed09cb | 3365 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3366 | if (io_index >= IO_MEM_NB_ENTRIES) |
3367 | return -1; | |
3368 | } | |
b5ff1b31 | 3369 | |
3cab721d RH |
3370 | for (i = 0; i < 3; ++i) { |
3371 | io_mem_read[io_index][i] | |
3372 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); | |
3373 | } | |
3374 | for (i = 0; i < 3; ++i) { | |
3375 | io_mem_write[io_index][i] | |
3376 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); | |
3377 | } | |
a4193c8a | 3378 | io_mem_opaque[io_index] = opaque; |
f6405247 RH |
3379 | |
3380 | return (io_index << IO_MEM_SHIFT); | |
33417e70 | 3381 | } |
61382a50 | 3382 | |
d60efc6b BS |
3383 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
3384 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb AK |
3385 | void *opaque) |
3386 | { | |
3387 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); | |
3388 | } | |
3389 | ||
88715657 AL |
3390 | void cpu_unregister_io_memory(int io_table_address) |
3391 | { | |
3392 | int i; | |
3393 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3394 | ||
3395 | for (i=0;i < 3; i++) { | |
3396 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3397 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3398 | } | |
3399 | io_mem_opaque[io_index] = NULL; | |
3400 | io_mem_used[io_index] = 0; | |
3401 | } | |
3402 | ||
e9179ce1 AK |
3403 | static void io_mem_init(void) |
3404 | { | |
3405 | int i; | |
3406 | ||
3407 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); | |
3408 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); | |
3409 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); | |
3410 | for (i=0; i<5; i++) | |
3411 | io_mem_used[i] = 1; | |
3412 | ||
3413 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
3414 | watch_mem_write, NULL); | |
e9179ce1 AK |
3415 | } |
3416 | ||
e2eef170 PB |
3417 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3418 | ||
13eb76e0 FB |
3419 | /* physical memory access (slow version, mainly for debug) */ |
3420 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3421 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3422 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3423 | { |
3424 | int l, flags; | |
3425 | target_ulong page; | |
53a5960a | 3426 | void * p; |
13eb76e0 FB |
3427 | |
3428 | while (len > 0) { | |
3429 | page = addr & TARGET_PAGE_MASK; | |
3430 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3431 | if (l > len) | |
3432 | l = len; | |
3433 | flags = page_get_flags(page); | |
3434 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3435 | return -1; |
13eb76e0 FB |
3436 | if (is_write) { |
3437 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3438 | return -1; |
579a97f7 | 3439 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3440 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3441 | return -1; |
72fb7daa AJ |
3442 | memcpy(p, buf, l); |
3443 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3444 | } else { |
3445 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3446 | return -1; |
579a97f7 | 3447 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3448 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3449 | return -1; |
72fb7daa | 3450 | memcpy(buf, p, l); |
5b257578 | 3451 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3452 | } |
3453 | len -= l; | |
3454 | buf += l; | |
3455 | addr += l; | |
3456 | } | |
a68fe89c | 3457 | return 0; |
13eb76e0 | 3458 | } |
8df1cd07 | 3459 | |
13eb76e0 | 3460 | #else |
c227f099 | 3461 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3462 | int len, int is_write) |
3463 | { | |
3464 | int l, io_index; | |
3465 | uint8_t *ptr; | |
3466 | uint32_t val; | |
c227f099 | 3467 | target_phys_addr_t page; |
2e12669a | 3468 | unsigned long pd; |
92e873b9 | 3469 | PhysPageDesc *p; |
3b46e624 | 3470 | |
13eb76e0 FB |
3471 | while (len > 0) { |
3472 | page = addr & TARGET_PAGE_MASK; | |
3473 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3474 | if (l > len) | |
3475 | l = len; | |
92e873b9 | 3476 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3477 | if (!p) { |
3478 | pd = IO_MEM_UNASSIGNED; | |
3479 | } else { | |
3480 | pd = p->phys_offset; | |
3481 | } | |
3b46e624 | 3482 | |
13eb76e0 | 3483 | if (is_write) { |
3a7d929e | 3484 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3485 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3486 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3487 | if (p) |
6c2934db | 3488 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3489 | /* XXX: could force cpu_single_env to NULL to avoid |
3490 | potential bugs */ | |
6c2934db | 3491 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3492 | /* 32 bit write access */ |
c27004ec | 3493 | val = ldl_p(buf); |
6c2934db | 3494 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3495 | l = 4; |
6c2934db | 3496 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3497 | /* 16 bit write access */ |
c27004ec | 3498 | val = lduw_p(buf); |
6c2934db | 3499 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3500 | l = 2; |
3501 | } else { | |
1c213d19 | 3502 | /* 8 bit write access */ |
c27004ec | 3503 | val = ldub_p(buf); |
6c2934db | 3504 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3505 | l = 1; |
3506 | } | |
3507 | } else { | |
b448f2f3 FB |
3508 | unsigned long addr1; |
3509 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3510 | /* RAM case */ |
5579c7f3 | 3511 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3512 | memcpy(ptr, buf, l); |
3a7d929e FB |
3513 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3514 | /* invalidate code */ | |
3515 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3516 | /* set dirty bit */ | |
f7c11b53 YT |
3517 | cpu_physical_memory_set_dirty_flags( |
3518 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3519 | } |
13eb76e0 FB |
3520 | } |
3521 | } else { | |
5fafdf24 | 3522 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3523 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3524 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3525 | /* I/O case */ |
3526 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3527 | if (p) |
6c2934db AJ |
3528 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3529 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3530 | /* 32 bit read access */ |
6c2934db | 3531 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3532 | stl_p(buf, val); |
13eb76e0 | 3533 | l = 4; |
6c2934db | 3534 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3535 | /* 16 bit read access */ |
6c2934db | 3536 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3537 | stw_p(buf, val); |
13eb76e0 FB |
3538 | l = 2; |
3539 | } else { | |
1c213d19 | 3540 | /* 8 bit read access */ |
6c2934db | 3541 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3542 | stb_p(buf, val); |
13eb76e0 FB |
3543 | l = 1; |
3544 | } | |
3545 | } else { | |
3546 | /* RAM case */ | |
5579c7f3 | 3547 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3548 | (addr & ~TARGET_PAGE_MASK); |
3549 | memcpy(buf, ptr, l); | |
3550 | } | |
3551 | } | |
3552 | len -= l; | |
3553 | buf += l; | |
3554 | addr += l; | |
3555 | } | |
3556 | } | |
8df1cd07 | 3557 | |
d0ecd2aa | 3558 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3559 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3560 | const uint8_t *buf, int len) |
3561 | { | |
3562 | int l; | |
3563 | uint8_t *ptr; | |
c227f099 | 3564 | target_phys_addr_t page; |
d0ecd2aa FB |
3565 | unsigned long pd; |
3566 | PhysPageDesc *p; | |
3b46e624 | 3567 | |
d0ecd2aa FB |
3568 | while (len > 0) { |
3569 | page = addr & TARGET_PAGE_MASK; | |
3570 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3571 | if (l > len) | |
3572 | l = len; | |
3573 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3574 | if (!p) { | |
3575 | pd = IO_MEM_UNASSIGNED; | |
3576 | } else { | |
3577 | pd = p->phys_offset; | |
3578 | } | |
3b46e624 | 3579 | |
d0ecd2aa | 3580 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3581 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3582 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3583 | /* do nothing */ |
3584 | } else { | |
3585 | unsigned long addr1; | |
3586 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3587 | /* ROM/RAM case */ | |
5579c7f3 | 3588 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3589 | memcpy(ptr, buf, l); |
3590 | } | |
3591 | len -= l; | |
3592 | buf += l; | |
3593 | addr += l; | |
3594 | } | |
3595 | } | |
3596 | ||
6d16c2f8 AL |
3597 | typedef struct { |
3598 | void *buffer; | |
c227f099 AL |
3599 | target_phys_addr_t addr; |
3600 | target_phys_addr_t len; | |
6d16c2f8 AL |
3601 | } BounceBuffer; |
3602 | ||
3603 | static BounceBuffer bounce; | |
3604 | ||
ba223c29 AL |
3605 | typedef struct MapClient { |
3606 | void *opaque; | |
3607 | void (*callback)(void *opaque); | |
72cf2d4f | 3608 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3609 | } MapClient; |
3610 | ||
72cf2d4f BS |
3611 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3612 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3613 | |
3614 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3615 | { | |
3616 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3617 | ||
3618 | client->opaque = opaque; | |
3619 | client->callback = callback; | |
72cf2d4f | 3620 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3621 | return client; |
3622 | } | |
3623 | ||
3624 | void cpu_unregister_map_client(void *_client) | |
3625 | { | |
3626 | MapClient *client = (MapClient *)_client; | |
3627 | ||
72cf2d4f | 3628 | QLIST_REMOVE(client, link); |
34d5e948 | 3629 | qemu_free(client); |
ba223c29 AL |
3630 | } |
3631 | ||
3632 | static void cpu_notify_map_clients(void) | |
3633 | { | |
3634 | MapClient *client; | |
3635 | ||
72cf2d4f BS |
3636 | while (!QLIST_EMPTY(&map_client_list)) { |
3637 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3638 | client->callback(client->opaque); |
34d5e948 | 3639 | cpu_unregister_map_client(client); |
ba223c29 AL |
3640 | } |
3641 | } | |
3642 | ||
6d16c2f8 AL |
3643 | /* Map a physical memory region into a host virtual address. |
3644 | * May map a subset of the requested range, given by and returned in *plen. | |
3645 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3646 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3647 | * Use cpu_register_map_client() to know when retrying the map operation is |
3648 | * likely to succeed. | |
6d16c2f8 | 3649 | */ |
c227f099 AL |
3650 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3651 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3652 | int is_write) |
3653 | { | |
c227f099 AL |
3654 | target_phys_addr_t len = *plen; |
3655 | target_phys_addr_t done = 0; | |
6d16c2f8 AL |
3656 | int l; |
3657 | uint8_t *ret = NULL; | |
3658 | uint8_t *ptr; | |
c227f099 | 3659 | target_phys_addr_t page; |
6d16c2f8 AL |
3660 | unsigned long pd; |
3661 | PhysPageDesc *p; | |
3662 | unsigned long addr1; | |
3663 | ||
3664 | while (len > 0) { | |
3665 | page = addr & TARGET_PAGE_MASK; | |
3666 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3667 | if (l > len) | |
3668 | l = len; | |
3669 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3670 | if (!p) { | |
3671 | pd = IO_MEM_UNASSIGNED; | |
3672 | } else { | |
3673 | pd = p->phys_offset; | |
3674 | } | |
3675 | ||
3676 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3677 | if (done || bounce.buffer) { | |
3678 | break; | |
3679 | } | |
3680 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3681 | bounce.addr = addr; | |
3682 | bounce.len = l; | |
3683 | if (!is_write) { | |
3684 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); | |
3685 | } | |
3686 | ptr = bounce.buffer; | |
3687 | } else { | |
3688 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3689 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3690 | } |
3691 | if (!done) { | |
3692 | ret = ptr; | |
3693 | } else if (ret + done != ptr) { | |
3694 | break; | |
3695 | } | |
3696 | ||
3697 | len -= l; | |
3698 | addr += l; | |
3699 | done += l; | |
3700 | } | |
3701 | *plen = done; | |
3702 | return ret; | |
3703 | } | |
3704 | ||
3705 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3706 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3707 | * the amount of memory that was actually read or written by the caller. | |
3708 | */ | |
c227f099 AL |
3709 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
3710 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
3711 | { |
3712 | if (buffer != bounce.buffer) { | |
3713 | if (is_write) { | |
e890261f | 3714 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
6d16c2f8 AL |
3715 | while (access_len) { |
3716 | unsigned l; | |
3717 | l = TARGET_PAGE_SIZE; | |
3718 | if (l > access_len) | |
3719 | l = access_len; | |
3720 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3721 | /* invalidate code */ | |
3722 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3723 | /* set dirty bit */ | |
f7c11b53 YT |
3724 | cpu_physical_memory_set_dirty_flags( |
3725 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
6d16c2f8 AL |
3726 | } |
3727 | addr1 += l; | |
3728 | access_len -= l; | |
3729 | } | |
3730 | } | |
3731 | return; | |
3732 | } | |
3733 | if (is_write) { | |
3734 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3735 | } | |
f8a83245 | 3736 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3737 | bounce.buffer = NULL; |
ba223c29 | 3738 | cpu_notify_map_clients(); |
6d16c2f8 | 3739 | } |
d0ecd2aa | 3740 | |
8df1cd07 | 3741 | /* warning: addr must be aligned */ |
c227f099 | 3742 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
3743 | { |
3744 | int io_index; | |
3745 | uint8_t *ptr; | |
3746 | uint32_t val; | |
3747 | unsigned long pd; | |
3748 | PhysPageDesc *p; | |
3749 | ||
3750 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3751 | if (!p) { | |
3752 | pd = IO_MEM_UNASSIGNED; | |
3753 | } else { | |
3754 | pd = p->phys_offset; | |
3755 | } | |
3b46e624 | 3756 | |
5fafdf24 | 3757 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3758 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
3759 | /* I/O case */ |
3760 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3761 | if (p) |
3762 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3763 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
3764 | } else { | |
3765 | /* RAM case */ | |
5579c7f3 | 3766 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
3767 | (addr & ~TARGET_PAGE_MASK); |
3768 | val = ldl_p(ptr); | |
3769 | } | |
3770 | return val; | |
3771 | } | |
3772 | ||
84b7b8e7 | 3773 | /* warning: addr must be aligned */ |
c227f099 | 3774 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
3775 | { |
3776 | int io_index; | |
3777 | uint8_t *ptr; | |
3778 | uint64_t val; | |
3779 | unsigned long pd; | |
3780 | PhysPageDesc *p; | |
3781 | ||
3782 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3783 | if (!p) { | |
3784 | pd = IO_MEM_UNASSIGNED; | |
3785 | } else { | |
3786 | pd = p->phys_offset; | |
3787 | } | |
3b46e624 | 3788 | |
2a4188a3 FB |
3789 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
3790 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
3791 | /* I/O case */ |
3792 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3793 | if (p) |
3794 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
3795 | #ifdef TARGET_WORDS_BIGENDIAN |
3796 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
3797 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
3798 | #else | |
3799 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
3800 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
3801 | #endif | |
3802 | } else { | |
3803 | /* RAM case */ | |
5579c7f3 | 3804 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
3805 | (addr & ~TARGET_PAGE_MASK); |
3806 | val = ldq_p(ptr); | |
3807 | } | |
3808 | return val; | |
3809 | } | |
3810 | ||
aab33094 | 3811 | /* XXX: optimize */ |
c227f099 | 3812 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
3813 | { |
3814 | uint8_t val; | |
3815 | cpu_physical_memory_read(addr, &val, 1); | |
3816 | return val; | |
3817 | } | |
3818 | ||
733f0b02 | 3819 | /* warning: addr must be aligned */ |
c227f099 | 3820 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 | 3821 | { |
733f0b02 MT |
3822 | int io_index; |
3823 | uint8_t *ptr; | |
3824 | uint64_t val; | |
3825 | unsigned long pd; | |
3826 | PhysPageDesc *p; | |
3827 | ||
3828 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3829 | if (!p) { | |
3830 | pd = IO_MEM_UNASSIGNED; | |
3831 | } else { | |
3832 | pd = p->phys_offset; | |
3833 | } | |
3834 | ||
3835 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && | |
3836 | !(pd & IO_MEM_ROMD)) { | |
3837 | /* I/O case */ | |
3838 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3839 | if (p) | |
3840 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
3841 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); | |
3842 | } else { | |
3843 | /* RAM case */ | |
3844 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + | |
3845 | (addr & ~TARGET_PAGE_MASK); | |
3846 | val = lduw_p(ptr); | |
3847 | } | |
3848 | return val; | |
aab33094 FB |
3849 | } |
3850 | ||
8df1cd07 FB |
3851 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3852 | and the code inside is not invalidated. It is useful if the dirty | |
3853 | bits are used to track modified PTEs */ | |
c227f099 | 3854 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3855 | { |
3856 | int io_index; | |
3857 | uint8_t *ptr; | |
3858 | unsigned long pd; | |
3859 | PhysPageDesc *p; | |
3860 | ||
3861 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3862 | if (!p) { | |
3863 | pd = IO_MEM_UNASSIGNED; | |
3864 | } else { | |
3865 | pd = p->phys_offset; | |
3866 | } | |
3b46e624 | 3867 | |
3a7d929e | 3868 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3869 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3870 | if (p) |
3871 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3872 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3873 | } else { | |
74576198 | 3874 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 3875 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3876 | stl_p(ptr, val); |
74576198 AL |
3877 | |
3878 | if (unlikely(in_migration)) { | |
3879 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3880 | /* invalidate code */ | |
3881 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3882 | /* set dirty bit */ | |
f7c11b53 YT |
3883 | cpu_physical_memory_set_dirty_flags( |
3884 | addr1, (0xff & ~CODE_DIRTY_FLAG)); | |
74576198 AL |
3885 | } |
3886 | } | |
8df1cd07 FB |
3887 | } |
3888 | } | |
3889 | ||
c227f099 | 3890 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
3891 | { |
3892 | int io_index; | |
3893 | uint8_t *ptr; | |
3894 | unsigned long pd; | |
3895 | PhysPageDesc *p; | |
3896 | ||
3897 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3898 | if (!p) { | |
3899 | pd = IO_MEM_UNASSIGNED; | |
3900 | } else { | |
3901 | pd = p->phys_offset; | |
3902 | } | |
3b46e624 | 3903 | |
bc98a7ef JM |
3904 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3905 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3906 | if (p) |
3907 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
3908 | #ifdef TARGET_WORDS_BIGENDIAN |
3909 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3910 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3911 | #else | |
3912 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3913 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3914 | #endif | |
3915 | } else { | |
5579c7f3 | 3916 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3917 | (addr & ~TARGET_PAGE_MASK); |
3918 | stq_p(ptr, val); | |
3919 | } | |
3920 | } | |
3921 | ||
8df1cd07 | 3922 | /* warning: addr must be aligned */ |
c227f099 | 3923 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3924 | { |
3925 | int io_index; | |
3926 | uint8_t *ptr; | |
3927 | unsigned long pd; | |
3928 | PhysPageDesc *p; | |
3929 | ||
3930 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3931 | if (!p) { | |
3932 | pd = IO_MEM_UNASSIGNED; | |
3933 | } else { | |
3934 | pd = p->phys_offset; | |
3935 | } | |
3b46e624 | 3936 | |
3a7d929e | 3937 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3938 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3939 | if (p) |
3940 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3941 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3942 | } else { | |
3943 | unsigned long addr1; | |
3944 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3945 | /* RAM case */ | |
5579c7f3 | 3946 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3947 | stl_p(ptr, val); |
3a7d929e FB |
3948 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3949 | /* invalidate code */ | |
3950 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3951 | /* set dirty bit */ | |
f7c11b53 YT |
3952 | cpu_physical_memory_set_dirty_flags(addr1, |
3953 | (0xff & ~CODE_DIRTY_FLAG)); | |
3a7d929e | 3954 | } |
8df1cd07 FB |
3955 | } |
3956 | } | |
3957 | ||
aab33094 | 3958 | /* XXX: optimize */ |
c227f099 | 3959 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3960 | { |
3961 | uint8_t v = val; | |
3962 | cpu_physical_memory_write(addr, &v, 1); | |
3963 | } | |
3964 | ||
733f0b02 | 3965 | /* warning: addr must be aligned */ |
c227f099 | 3966 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 | 3967 | { |
733f0b02 MT |
3968 | int io_index; |
3969 | uint8_t *ptr; | |
3970 | unsigned long pd; | |
3971 | PhysPageDesc *p; | |
3972 | ||
3973 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3974 | if (!p) { | |
3975 | pd = IO_MEM_UNASSIGNED; | |
3976 | } else { | |
3977 | pd = p->phys_offset; | |
3978 | } | |
3979 | ||
3980 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3981 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
3982 | if (p) | |
3983 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
3984 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); | |
3985 | } else { | |
3986 | unsigned long addr1; | |
3987 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3988 | /* RAM case */ | |
3989 | ptr = qemu_get_ram_ptr(addr1); | |
3990 | stw_p(ptr, val); | |
3991 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3992 | /* invalidate code */ | |
3993 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); | |
3994 | /* set dirty bit */ | |
3995 | cpu_physical_memory_set_dirty_flags(addr1, | |
3996 | (0xff & ~CODE_DIRTY_FLAG)); | |
3997 | } | |
3998 | } | |
aab33094 FB |
3999 | } |
4000 | ||
4001 | /* XXX: optimize */ | |
c227f099 | 4002 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
4003 | { |
4004 | val = tswap64(val); | |
4005 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
4006 | } | |
4007 | ||
5e2972fd | 4008 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 4009 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 4010 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
4011 | { |
4012 | int l; | |
c227f099 | 4013 | target_phys_addr_t phys_addr; |
9b3c35e0 | 4014 | target_ulong page; |
13eb76e0 FB |
4015 | |
4016 | while (len > 0) { | |
4017 | page = addr & TARGET_PAGE_MASK; | |
4018 | phys_addr = cpu_get_phys_page_debug(env, page); | |
4019 | /* if no physical page mapped, return an error */ | |
4020 | if (phys_addr == -1) | |
4021 | return -1; | |
4022 | l = (page + TARGET_PAGE_SIZE) - addr; | |
4023 | if (l > len) | |
4024 | l = len; | |
5e2972fd | 4025 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
4026 | if (is_write) |
4027 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
4028 | else | |
5e2972fd | 4029 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
4030 | len -= l; |
4031 | buf += l; | |
4032 | addr += l; | |
4033 | } | |
4034 | return 0; | |
4035 | } | |
a68fe89c | 4036 | #endif |
13eb76e0 | 4037 | |
2e70f6ef PB |
4038 | /* in deterministic execution mode, instructions doing device I/Os |
4039 | must be at the end of the TB */ | |
4040 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
4041 | { | |
4042 | TranslationBlock *tb; | |
4043 | uint32_t n, cflags; | |
4044 | target_ulong pc, cs_base; | |
4045 | uint64_t flags; | |
4046 | ||
4047 | tb = tb_find_pc((unsigned long)retaddr); | |
4048 | if (!tb) { | |
4049 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
4050 | retaddr); | |
4051 | } | |
4052 | n = env->icount_decr.u16.low + tb->icount; | |
4053 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
4054 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 4055 | occurred. */ |
2e70f6ef PB |
4056 | n = n - env->icount_decr.u16.low; |
4057 | /* Generate a new TB ending on the I/O insn. */ | |
4058 | n++; | |
4059 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
4060 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 4061 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
4062 | branch. */ |
4063 | #if defined(TARGET_MIPS) | |
4064 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
4065 | env->active_tc.PC -= 4; | |
4066 | env->icount_decr.u16.low++; | |
4067 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
4068 | } | |
4069 | #elif defined(TARGET_SH4) | |
4070 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
4071 | && n > 1) { | |
4072 | env->pc -= 2; | |
4073 | env->icount_decr.u16.low++; | |
4074 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
4075 | } | |
4076 | #endif | |
4077 | /* This should never happen. */ | |
4078 | if (n > CF_COUNT_MASK) | |
4079 | cpu_abort(env, "TB too big during recompile"); | |
4080 | ||
4081 | cflags = n | CF_LAST_IO; | |
4082 | pc = tb->pc; | |
4083 | cs_base = tb->cs_base; | |
4084 | flags = tb->flags; | |
4085 | tb_phys_invalidate(tb, -1); | |
4086 | /* FIXME: In theory this could raise an exception. In practice | |
4087 | we have already translated the block once so it's probably ok. */ | |
4088 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 4089 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
4090 | the first in the TB) then we end up generating a whole new TB and |
4091 | repeating the fault, which is horribly inefficient. | |
4092 | Better would be to execute just this insn uncached, or generate a | |
4093 | second new TB. */ | |
4094 | cpu_resume_from_signal(env, NULL); | |
4095 | } | |
4096 | ||
b3755a91 PB |
4097 | #if !defined(CONFIG_USER_ONLY) |
4098 | ||
e3db7226 FB |
4099 | void dump_exec_info(FILE *f, |
4100 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
4101 | { | |
4102 | int i, target_code_size, max_target_code_size; | |
4103 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
4104 | TranslationBlock *tb; | |
3b46e624 | 4105 | |
e3db7226 FB |
4106 | target_code_size = 0; |
4107 | max_target_code_size = 0; | |
4108 | cross_page = 0; | |
4109 | direct_jmp_count = 0; | |
4110 | direct_jmp2_count = 0; | |
4111 | for(i = 0; i < nb_tbs; i++) { | |
4112 | tb = &tbs[i]; | |
4113 | target_code_size += tb->size; | |
4114 | if (tb->size > max_target_code_size) | |
4115 | max_target_code_size = tb->size; | |
4116 | if (tb->page_addr[1] != -1) | |
4117 | cross_page++; | |
4118 | if (tb->tb_next_offset[0] != 0xffff) { | |
4119 | direct_jmp_count++; | |
4120 | if (tb->tb_next_offset[1] != 0xffff) { | |
4121 | direct_jmp2_count++; | |
4122 | } | |
4123 | } | |
4124 | } | |
4125 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 4126 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
4127 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
4128 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
4129 | cpu_fprintf(f, "TB count %d/%d\n", | |
4130 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 4131 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
4132 | nb_tbs ? target_code_size / nb_tbs : 0, |
4133 | max_target_code_size); | |
5fafdf24 | 4134 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
4135 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
4136 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
4137 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
4138 | cross_page, | |
e3db7226 FB |
4139 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
4140 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 4141 | direct_jmp_count, |
e3db7226 FB |
4142 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
4143 | direct_jmp2_count, | |
4144 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 4145 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
4146 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
4147 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
4148 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 4149 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
4150 | } |
4151 | ||
61382a50 FB |
4152 | #define MMUSUFFIX _cmmu |
4153 | #define GETPC() NULL | |
4154 | #define env cpu_single_env | |
b769d8fe | 4155 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
4156 | |
4157 | #define SHIFT 0 | |
4158 | #include "softmmu_template.h" | |
4159 | ||
4160 | #define SHIFT 1 | |
4161 | #include "softmmu_template.h" | |
4162 | ||
4163 | #define SHIFT 2 | |
4164 | #include "softmmu_template.h" | |
4165 | ||
4166 | #define SHIFT 3 | |
4167 | #include "softmmu_template.h" | |
4168 | ||
4169 | #undef env | |
4170 | ||
4171 | #endif |