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Commit | Line | Data |
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54936004 | 1 | /* |
fd6ce8f6 | 2 | * virtual page mapping and translated block handling |
5fafdf24 | 3 | * |
54936004 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
54936004 | 18 | */ |
67b915a5 | 19 | #include "config.h" |
d5a8f07c FB |
20 | #ifdef _WIN32 |
21 | #include <windows.h> | |
22 | #else | |
a98d49b1 | 23 | #include <sys/types.h> |
d5a8f07c FB |
24 | #include <sys/mman.h> |
25 | #endif | |
54936004 FB |
26 | #include <stdlib.h> |
27 | #include <stdio.h> | |
28 | #include <stdarg.h> | |
29 | #include <string.h> | |
30 | #include <errno.h> | |
31 | #include <unistd.h> | |
32 | #include <inttypes.h> | |
33 | ||
6180a181 FB |
34 | #include "cpu.h" |
35 | #include "exec-all.h" | |
ca10f867 | 36 | #include "qemu-common.h" |
b67d9a52 | 37 | #include "tcg.h" |
b3c7724c | 38 | #include "hw/hw.h" |
74576198 | 39 | #include "osdep.h" |
7ba1e619 | 40 | #include "kvm.h" |
53a5960a PB |
41 | #if defined(CONFIG_USER_ONLY) |
42 | #include <qemu.h> | |
fd052bf6 | 43 | #include <signal.h> |
53a5960a | 44 | #endif |
54936004 | 45 | |
fd6ce8f6 | 46 | //#define DEBUG_TB_INVALIDATE |
66e85a21 | 47 | //#define DEBUG_FLUSH |
9fa3e853 | 48 | //#define DEBUG_TLB |
67d3b957 | 49 | //#define DEBUG_UNASSIGNED |
fd6ce8f6 FB |
50 | |
51 | /* make various TB consistency checks */ | |
5fafdf24 TS |
52 | //#define DEBUG_TB_CHECK |
53 | //#define DEBUG_TLB_CHECK | |
fd6ce8f6 | 54 | |
1196be37 | 55 | //#define DEBUG_IOPORT |
db7b5426 | 56 | //#define DEBUG_SUBPAGE |
1196be37 | 57 | |
99773bd4 PB |
58 | #if !defined(CONFIG_USER_ONLY) |
59 | /* TB consistency checks only implemented for usermode emulation. */ | |
60 | #undef DEBUG_TB_CHECK | |
61 | #endif | |
62 | ||
9fa3e853 FB |
63 | #define SMC_BITMAP_USE_THRESHOLD 10 |
64 | ||
bdaf78e0 | 65 | static TranslationBlock *tbs; |
26a5f13b | 66 | int code_gen_max_blocks; |
9fa3e853 | 67 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
bdaf78e0 | 68 | static int nb_tbs; |
eb51d102 | 69 | /* any access to the tbs or the page table must use this lock */ |
c227f099 | 70 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
fd6ce8f6 | 71 | |
141ac468 BS |
72 | #if defined(__arm__) || defined(__sparc_v9__) |
73 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 | |
74 | have limited branch ranges (possibly also PPC) so place it in a | |
d03d860b BS |
75 | section close to code segment. */ |
76 | #define code_gen_section \ | |
77 | __attribute__((__section__(".gen_code"))) \ | |
78 | __attribute__((aligned (32))) | |
f8e2af11 SW |
79 | #elif defined(_WIN32) |
80 | /* Maximum alignment for Win32 is 16. */ | |
81 | #define code_gen_section \ | |
82 | __attribute__((aligned (16))) | |
d03d860b BS |
83 | #else |
84 | #define code_gen_section \ | |
85 | __attribute__((aligned (32))) | |
86 | #endif | |
87 | ||
88 | uint8_t code_gen_prologue[1024] code_gen_section; | |
bdaf78e0 BS |
89 | static uint8_t *code_gen_buffer; |
90 | static unsigned long code_gen_buffer_size; | |
26a5f13b | 91 | /* threshold to flush the translated code buffer */ |
bdaf78e0 | 92 | static unsigned long code_gen_buffer_max_size; |
fd6ce8f6 FB |
93 | uint8_t *code_gen_ptr; |
94 | ||
e2eef170 | 95 | #if !defined(CONFIG_USER_ONLY) |
9fa3e853 | 96 | int phys_ram_fd; |
1ccde1cb | 97 | uint8_t *phys_ram_dirty; |
74576198 | 98 | static int in_migration; |
94a6b54f PB |
99 | |
100 | typedef struct RAMBlock { | |
101 | uint8_t *host; | |
c227f099 AL |
102 | ram_addr_t offset; |
103 | ram_addr_t length; | |
94a6b54f PB |
104 | struct RAMBlock *next; |
105 | } RAMBlock; | |
106 | ||
107 | static RAMBlock *ram_blocks; | |
108 | /* TODO: When we implement (and use) ram deallocation (e.g. for hotplug) | |
ccbb4d44 | 109 | then we can no longer assume contiguous ram offsets, and external uses |
94a6b54f | 110 | of this variable will break. */ |
c227f099 | 111 | ram_addr_t last_ram_offset; |
e2eef170 | 112 | #endif |
9fa3e853 | 113 | |
6a00d601 FB |
114 | CPUState *first_cpu; |
115 | /* current CPU in the current thread. It is only valid inside | |
116 | cpu_exec() */ | |
5fafdf24 | 117 | CPUState *cpu_single_env; |
2e70f6ef | 118 | /* 0 = Do not count executed instructions. |
bf20dc07 | 119 | 1 = Precise instruction counting. |
2e70f6ef PB |
120 | 2 = Adaptive rate instruction counting. */ |
121 | int use_icount = 0; | |
122 | /* Current instruction counter. While executing translated code this may | |
123 | include some instructions that have not yet been executed. */ | |
124 | int64_t qemu_icount; | |
6a00d601 | 125 | |
54936004 | 126 | typedef struct PageDesc { |
92e873b9 | 127 | /* list of TBs intersecting this ram page */ |
fd6ce8f6 | 128 | TranslationBlock *first_tb; |
9fa3e853 FB |
129 | /* in order to optimize self modifying code, we count the number |
130 | of lookups we do to a given page to use a bitmap */ | |
131 | unsigned int code_write_count; | |
132 | uint8_t *code_bitmap; | |
133 | #if defined(CONFIG_USER_ONLY) | |
134 | unsigned long flags; | |
135 | #endif | |
54936004 FB |
136 | } PageDesc; |
137 | ||
92e873b9 | 138 | typedef struct PhysPageDesc { |
0f459d16 | 139 | /* offset in host memory of the page + io_index in the low bits */ |
c227f099 AL |
140 | ram_addr_t phys_offset; |
141 | ram_addr_t region_offset; | |
92e873b9 FB |
142 | } PhysPageDesc; |
143 | ||
5cd2c5b6 RH |
144 | /* In system mode we want L1_MAP to be based on physical addresses, |
145 | while in user mode we want it to be based on virtual addresses. */ | |
146 | #if !defined(CONFIG_USER_ONLY) | |
147 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
bedb69ea | 148 | #else |
5cd2c5b6 | 149 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
bedb69ea | 150 | #endif |
54936004 | 151 | |
5cd2c5b6 RH |
152 | /* Size of the L2 (and L3, etc) page tables. */ |
153 | #define L2_BITS 10 | |
54936004 FB |
154 | #define L2_SIZE (1 << L2_BITS) |
155 | ||
5cd2c5b6 RH |
156 | /* The bits remaining after N lower levels of page tables. */ |
157 | #define P_L1_BITS_REM \ | |
158 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
159 | #define V_L1_BITS_REM \ | |
160 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) | |
161 | ||
162 | /* Size of the L1 page table. Avoid silly small sizes. */ | |
163 | #if P_L1_BITS_REM < 4 | |
164 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) | |
165 | #else | |
166 | #define P_L1_BITS P_L1_BITS_REM | |
167 | #endif | |
168 | ||
169 | #if V_L1_BITS_REM < 4 | |
170 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) | |
171 | #else | |
172 | #define V_L1_BITS V_L1_BITS_REM | |
173 | #endif | |
174 | ||
175 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) | |
176 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
177 | ||
178 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) | |
179 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
180 | ||
83fb7adf FB |
181 | unsigned long qemu_real_host_page_size; |
182 | unsigned long qemu_host_page_bits; | |
183 | unsigned long qemu_host_page_size; | |
184 | unsigned long qemu_host_page_mask; | |
54936004 | 185 | |
5cd2c5b6 RH |
186 | /* This is a multi-level map on the virtual address space. |
187 | The bottom level has pointers to PageDesc. */ | |
188 | static void *l1_map[V_L1_SIZE]; | |
54936004 | 189 | |
e2eef170 | 190 | #if !defined(CONFIG_USER_ONLY) |
5cd2c5b6 RH |
191 | /* This is a multi-level map on the physical address space. |
192 | The bottom level has pointers to PhysPageDesc. */ | |
193 | static void *l1_phys_map[P_L1_SIZE]; | |
6d9a1304 | 194 | |
e2eef170 PB |
195 | static void io_mem_init(void); |
196 | ||
33417e70 | 197 | /* io memory support */ |
33417e70 FB |
198 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
199 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; | |
a4193c8a | 200 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
511d2b14 | 201 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
6658ffb8 PB |
202 | static int io_mem_watch; |
203 | #endif | |
33417e70 | 204 | |
34865134 | 205 | /* log support */ |
1e8b27ca JR |
206 | #ifdef WIN32 |
207 | static const char *logfilename = "qemu.log"; | |
208 | #else | |
d9b630fd | 209 | static const char *logfilename = "/tmp/qemu.log"; |
1e8b27ca | 210 | #endif |
34865134 FB |
211 | FILE *logfile; |
212 | int loglevel; | |
e735b91c | 213 | static int log_append = 0; |
34865134 | 214 | |
e3db7226 FB |
215 | /* statistics */ |
216 | static int tlb_flush_count; | |
217 | static int tb_flush_count; | |
218 | static int tb_phys_invalidate_count; | |
219 | ||
7cb69cae FB |
220 | #ifdef _WIN32 |
221 | static void map_exec(void *addr, long size) | |
222 | { | |
223 | DWORD old_protect; | |
224 | VirtualProtect(addr, size, | |
225 | PAGE_EXECUTE_READWRITE, &old_protect); | |
226 | ||
227 | } | |
228 | #else | |
229 | static void map_exec(void *addr, long size) | |
230 | { | |
4369415f | 231 | unsigned long start, end, page_size; |
7cb69cae | 232 | |
4369415f | 233 | page_size = getpagesize(); |
7cb69cae | 234 | start = (unsigned long)addr; |
4369415f | 235 | start &= ~(page_size - 1); |
7cb69cae FB |
236 | |
237 | end = (unsigned long)addr + size; | |
4369415f FB |
238 | end += page_size - 1; |
239 | end &= ~(page_size - 1); | |
7cb69cae FB |
240 | |
241 | mprotect((void *)start, end - start, | |
242 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
243 | } | |
244 | #endif | |
245 | ||
b346ff46 | 246 | static void page_init(void) |
54936004 | 247 | { |
83fb7adf | 248 | /* NOTE: we can always suppose that qemu_host_page_size >= |
54936004 | 249 | TARGET_PAGE_SIZE */ |
c2b48b69 AL |
250 | #ifdef _WIN32 |
251 | { | |
252 | SYSTEM_INFO system_info; | |
253 | ||
254 | GetSystemInfo(&system_info); | |
255 | qemu_real_host_page_size = system_info.dwPageSize; | |
256 | } | |
257 | #else | |
258 | qemu_real_host_page_size = getpagesize(); | |
259 | #endif | |
83fb7adf FB |
260 | if (qemu_host_page_size == 0) |
261 | qemu_host_page_size = qemu_real_host_page_size; | |
262 | if (qemu_host_page_size < TARGET_PAGE_SIZE) | |
263 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
264 | qemu_host_page_bits = 0; | |
265 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) | |
266 | qemu_host_page_bits++; | |
267 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
50a9569b AZ |
268 | |
269 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) | |
270 | { | |
50a9569b | 271 | FILE *f; |
50a9569b | 272 | |
0776590d | 273 | last_brk = (unsigned long)sbrk(0); |
5cd2c5b6 | 274 | |
50a9569b AZ |
275 | f = fopen("/proc/self/maps", "r"); |
276 | if (f) { | |
5cd2c5b6 RH |
277 | mmap_lock(); |
278 | ||
50a9569b | 279 | do { |
5cd2c5b6 RH |
280 | unsigned long startaddr, endaddr; |
281 | int n; | |
282 | ||
283 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
284 | ||
285 | if (n == 2 && h2g_valid(startaddr)) { | |
286 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
287 | ||
288 | if (h2g_valid(endaddr)) { | |
289 | endaddr = h2g(endaddr); | |
290 | } else { | |
291 | endaddr = ~0ul; | |
292 | } | |
293 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
50a9569b AZ |
294 | } |
295 | } while (!feof(f)); | |
5cd2c5b6 | 296 | |
50a9569b | 297 | fclose(f); |
5cd2c5b6 | 298 | mmap_unlock(); |
50a9569b AZ |
299 | } |
300 | } | |
301 | #endif | |
54936004 FB |
302 | } |
303 | ||
5cd2c5b6 | 304 | static PageDesc *page_find_alloc(target_ulong index, int alloc) |
54936004 | 305 | { |
5cd2c5b6 RH |
306 | #if defined(CONFIG_USER_ONLY) |
307 | /* We can't use qemu_malloc because it may recurse into a locked mutex. | |
308 | Neither can we record the new pages we reserve while allocating a | |
309 | given page because that may recurse into an unallocated page table | |
310 | entry. Stuff the allocations we do make into a queue and process | |
311 | them after having completed one entire page table allocation. */ | |
312 | ||
313 | unsigned long reserve[2 * (V_L1_SHIFT / L2_BITS)]; | |
314 | int reserve_idx = 0; | |
315 | ||
316 | # define ALLOC(P, SIZE) \ | |
317 | do { \ | |
318 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ | |
319 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ | |
320 | if (h2g_valid(P)) { \ | |
321 | reserve[reserve_idx] = h2g(P); \ | |
322 | reserve[reserve_idx + 1] = SIZE; \ | |
323 | reserve_idx += 2; \ | |
324 | } \ | |
325 | } while (0) | |
326 | #else | |
327 | # define ALLOC(P, SIZE) \ | |
328 | do { P = qemu_mallocz(SIZE); } while (0) | |
17e2377a | 329 | #endif |
434929bf | 330 | |
5cd2c5b6 RH |
331 | PageDesc *pd; |
332 | void **lp; | |
333 | int i; | |
434929bf | 334 | |
5cd2c5b6 RH |
335 | /* Level 1. Always allocated. */ |
336 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
337 | ||
338 | /* Level 2..N-1. */ | |
339 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
340 | void **p = *lp; | |
341 | ||
342 | if (p == NULL) { | |
343 | if (!alloc) { | |
344 | return NULL; | |
345 | } | |
346 | ALLOC(p, sizeof(void *) * L2_SIZE); | |
347 | *lp = p; | |
17e2377a | 348 | } |
5cd2c5b6 RH |
349 | |
350 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
351 | } | |
352 | ||
353 | pd = *lp; | |
354 | if (pd == NULL) { | |
355 | if (!alloc) { | |
356 | return NULL; | |
357 | } | |
358 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); | |
359 | *lp = pd; | |
54936004 | 360 | } |
5cd2c5b6 RH |
361 | |
362 | #undef ALLOC | |
363 | #if defined(CONFIG_USER_ONLY) | |
364 | for (i = 0; i < reserve_idx; i += 2) { | |
365 | unsigned long addr = reserve[i]; | |
366 | unsigned long len = reserve[i + 1]; | |
367 | ||
368 | page_set_flags(addr & TARGET_PAGE_MASK, | |
369 | TARGET_PAGE_ALIGN(addr + len), | |
370 | PAGE_RESERVED); | |
371 | } | |
372 | #endif | |
373 | ||
374 | return pd + (index & (L2_SIZE - 1)); | |
54936004 FB |
375 | } |
376 | ||
00f82b8a | 377 | static inline PageDesc *page_find(target_ulong index) |
54936004 | 378 | { |
5cd2c5b6 | 379 | return page_find_alloc(index, 0); |
fd6ce8f6 FB |
380 | } |
381 | ||
6d9a1304 | 382 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 383 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
92e873b9 | 384 | { |
e3f4e2a4 | 385 | PhysPageDesc *pd; |
5cd2c5b6 RH |
386 | void **lp; |
387 | int i; | |
92e873b9 | 388 | |
5cd2c5b6 RH |
389 | /* Level 1. Always allocated. */ |
390 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); | |
108c49b8 | 391 | |
5cd2c5b6 RH |
392 | /* Level 2..N-1. */ |
393 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { | |
394 | void **p = *lp; | |
395 | if (p == NULL) { | |
396 | if (!alloc) { | |
397 | return NULL; | |
398 | } | |
399 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); | |
400 | } | |
401 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); | |
108c49b8 | 402 | } |
5cd2c5b6 | 403 | |
e3f4e2a4 | 404 | pd = *lp; |
5cd2c5b6 | 405 | if (pd == NULL) { |
e3f4e2a4 | 406 | int i; |
5cd2c5b6 RH |
407 | |
408 | if (!alloc) { | |
108c49b8 | 409 | return NULL; |
5cd2c5b6 RH |
410 | } |
411 | ||
412 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); | |
413 | ||
67c4d23c | 414 | for (i = 0; i < L2_SIZE; i++) { |
5cd2c5b6 RH |
415 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
416 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; | |
67c4d23c | 417 | } |
92e873b9 | 418 | } |
5cd2c5b6 RH |
419 | |
420 | return pd + (index & (L2_SIZE - 1)); | |
92e873b9 FB |
421 | } |
422 | ||
c227f099 | 423 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
92e873b9 | 424 | { |
108c49b8 | 425 | return phys_page_find_alloc(index, 0); |
92e873b9 FB |
426 | } |
427 | ||
c227f099 AL |
428 | static void tlb_protect_code(ram_addr_t ram_addr); |
429 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, | |
3a7d929e | 430 | target_ulong vaddr); |
c8a706fe PB |
431 | #define mmap_lock() do { } while(0) |
432 | #define mmap_unlock() do { } while(0) | |
9fa3e853 | 433 | #endif |
fd6ce8f6 | 434 | |
4369415f FB |
435 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
436 | ||
437 | #if defined(CONFIG_USER_ONLY) | |
ccbb4d44 | 438 | /* Currently it is not recommended to allocate big chunks of data in |
4369415f FB |
439 | user mode. It will change when a dedicated libc will be used */ |
440 | #define USE_STATIC_CODE_GEN_BUFFER | |
441 | #endif | |
442 | ||
443 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
444 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]; | |
445 | #endif | |
446 | ||
8fcd3692 | 447 | static void code_gen_alloc(unsigned long tb_size) |
26a5f13b | 448 | { |
4369415f FB |
449 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
450 | code_gen_buffer = static_code_gen_buffer; | |
451 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
452 | map_exec(code_gen_buffer, code_gen_buffer_size); | |
453 | #else | |
26a5f13b FB |
454 | code_gen_buffer_size = tb_size; |
455 | if (code_gen_buffer_size == 0) { | |
4369415f FB |
456 | #if defined(CONFIG_USER_ONLY) |
457 | /* in user mode, phys_ram_size is not meaningful */ | |
458 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
459 | #else | |
ccbb4d44 | 460 | /* XXX: needs adjustments */ |
94a6b54f | 461 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
4369415f | 462 | #endif |
26a5f13b FB |
463 | } |
464 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) | |
465 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; | |
466 | /* The code gen buffer location may have constraints depending on | |
467 | the host cpu and OS */ | |
468 | #if defined(__linux__) | |
469 | { | |
470 | int flags; | |
141ac468 BS |
471 | void *start = NULL; |
472 | ||
26a5f13b FB |
473 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
474 | #if defined(__x86_64__) | |
475 | flags |= MAP_32BIT; | |
476 | /* Cannot map more than that */ | |
477 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
478 | code_gen_buffer_size = (800 * 1024 * 1024); | |
141ac468 BS |
479 | #elif defined(__sparc_v9__) |
480 | // Map the buffer below 2G, so we can use direct calls and branches | |
481 | flags |= MAP_FIXED; | |
482 | start = (void *) 0x60000000UL; | |
483 | if (code_gen_buffer_size > (512 * 1024 * 1024)) | |
484 | code_gen_buffer_size = (512 * 1024 * 1024); | |
1cb0661e | 485 | #elif defined(__arm__) |
63d41246 | 486 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
1cb0661e AZ |
487 | flags |= MAP_FIXED; |
488 | start = (void *) 0x01000000UL; | |
489 | if (code_gen_buffer_size > 16 * 1024 * 1024) | |
490 | code_gen_buffer_size = 16 * 1024 * 1024; | |
26a5f13b | 491 | #endif |
141ac468 BS |
492 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
493 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
26a5f13b FB |
494 | flags, -1, 0); |
495 | if (code_gen_buffer == MAP_FAILED) { | |
496 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
497 | exit(1); | |
498 | } | |
499 | } | |
a167ba50 | 500 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
06e67a82 AL |
501 | { |
502 | int flags; | |
503 | void *addr = NULL; | |
504 | flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
505 | #if defined(__x86_64__) | |
506 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume | |
507 | * 0x40000000 is free */ | |
508 | flags |= MAP_FIXED; | |
509 | addr = (void *)0x40000000; | |
510 | /* Cannot map more than that */ | |
511 | if (code_gen_buffer_size > (800 * 1024 * 1024)) | |
512 | code_gen_buffer_size = (800 * 1024 * 1024); | |
513 | #endif | |
514 | code_gen_buffer = mmap(addr, code_gen_buffer_size, | |
515 | PROT_WRITE | PROT_READ | PROT_EXEC, | |
516 | flags, -1, 0); | |
517 | if (code_gen_buffer == MAP_FAILED) { | |
518 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); | |
519 | exit(1); | |
520 | } | |
521 | } | |
26a5f13b FB |
522 | #else |
523 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); | |
26a5f13b FB |
524 | map_exec(code_gen_buffer, code_gen_buffer_size); |
525 | #endif | |
4369415f | 526 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
26a5f13b FB |
527 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
528 | code_gen_buffer_max_size = code_gen_buffer_size - | |
529 | code_gen_max_block_size(); | |
530 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
531 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); | |
532 | } | |
533 | ||
534 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
535 | (in bytes) allocated to the translation buffer. Zero means default | |
536 | size. */ | |
537 | void cpu_exec_init_all(unsigned long tb_size) | |
538 | { | |
26a5f13b FB |
539 | cpu_gen_init(); |
540 | code_gen_alloc(tb_size); | |
541 | code_gen_ptr = code_gen_buffer; | |
4369415f | 542 | page_init(); |
e2eef170 | 543 | #if !defined(CONFIG_USER_ONLY) |
26a5f13b | 544 | io_mem_init(); |
e2eef170 | 545 | #endif |
26a5f13b FB |
546 | } |
547 | ||
9656f324 PB |
548 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
549 | ||
e59fb374 | 550 | static int cpu_common_post_load(void *opaque, int version_id) |
e7f4eff7 JQ |
551 | { |
552 | CPUState *env = opaque; | |
9656f324 | 553 | |
3098dba0 AJ |
554 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
555 | version_id is increased. */ | |
556 | env->interrupt_request &= ~0x01; | |
9656f324 PB |
557 | tlb_flush(env, 1); |
558 | ||
559 | return 0; | |
560 | } | |
e7f4eff7 JQ |
561 | |
562 | static const VMStateDescription vmstate_cpu_common = { | |
563 | .name = "cpu_common", | |
564 | .version_id = 1, | |
565 | .minimum_version_id = 1, | |
566 | .minimum_version_id_old = 1, | |
e7f4eff7 JQ |
567 | .post_load = cpu_common_post_load, |
568 | .fields = (VMStateField []) { | |
569 | VMSTATE_UINT32(halted, CPUState), | |
570 | VMSTATE_UINT32(interrupt_request, CPUState), | |
571 | VMSTATE_END_OF_LIST() | |
572 | } | |
573 | }; | |
9656f324 PB |
574 | #endif |
575 | ||
950f1472 GC |
576 | CPUState *qemu_get_cpu(int cpu) |
577 | { | |
578 | CPUState *env = first_cpu; | |
579 | ||
580 | while (env) { | |
581 | if (env->cpu_index == cpu) | |
582 | break; | |
583 | env = env->next_cpu; | |
584 | } | |
585 | ||
586 | return env; | |
587 | } | |
588 | ||
6a00d601 | 589 | void cpu_exec_init(CPUState *env) |
fd6ce8f6 | 590 | { |
6a00d601 FB |
591 | CPUState **penv; |
592 | int cpu_index; | |
593 | ||
c2764719 PB |
594 | #if defined(CONFIG_USER_ONLY) |
595 | cpu_list_lock(); | |
596 | #endif | |
6a00d601 FB |
597 | env->next_cpu = NULL; |
598 | penv = &first_cpu; | |
599 | cpu_index = 0; | |
600 | while (*penv != NULL) { | |
1e9fa730 | 601 | penv = &(*penv)->next_cpu; |
6a00d601 FB |
602 | cpu_index++; |
603 | } | |
604 | env->cpu_index = cpu_index; | |
268a362c | 605 | env->numa_node = 0; |
72cf2d4f BS |
606 | QTAILQ_INIT(&env->breakpoints); |
607 | QTAILQ_INIT(&env->watchpoints); | |
6a00d601 | 608 | *penv = env; |
c2764719 PB |
609 | #if defined(CONFIG_USER_ONLY) |
610 | cpu_list_unlock(); | |
611 | #endif | |
b3c7724c | 612 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
e7f4eff7 | 613 | vmstate_register(cpu_index, &vmstate_cpu_common, env); |
b3c7724c PB |
614 | register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, |
615 | cpu_save, cpu_load, env); | |
616 | #endif | |
fd6ce8f6 FB |
617 | } |
618 | ||
9fa3e853 FB |
619 | static inline void invalidate_page_bitmap(PageDesc *p) |
620 | { | |
621 | if (p->code_bitmap) { | |
59817ccb | 622 | qemu_free(p->code_bitmap); |
9fa3e853 FB |
623 | p->code_bitmap = NULL; |
624 | } | |
625 | p->code_write_count = 0; | |
626 | } | |
627 | ||
5cd2c5b6 RH |
628 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
629 | ||
630 | static void page_flush_tb_1 (int level, void **lp) | |
fd6ce8f6 | 631 | { |
5cd2c5b6 | 632 | int i; |
fd6ce8f6 | 633 | |
5cd2c5b6 RH |
634 | if (*lp == NULL) { |
635 | return; | |
636 | } | |
637 | if (level == 0) { | |
638 | PageDesc *pd = *lp; | |
639 | for (i = 0; i < L2_BITS; ++i) { | |
640 | pd[i].first_tb = NULL; | |
641 | invalidate_page_bitmap(pd + i); | |
fd6ce8f6 | 642 | } |
5cd2c5b6 RH |
643 | } else { |
644 | void **pp = *lp; | |
645 | for (i = 0; i < L2_BITS; ++i) { | |
646 | page_flush_tb_1 (level - 1, pp + i); | |
647 | } | |
648 | } | |
649 | } | |
650 | ||
651 | static void page_flush_tb(void) | |
652 | { | |
653 | int i; | |
654 | for (i = 0; i < V_L1_SIZE; i++) { | |
655 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
fd6ce8f6 FB |
656 | } |
657 | } | |
658 | ||
659 | /* flush all the translation blocks */ | |
d4e8164f | 660 | /* XXX: tb_flush is currently not thread safe */ |
6a00d601 | 661 | void tb_flush(CPUState *env1) |
fd6ce8f6 | 662 | { |
6a00d601 | 663 | CPUState *env; |
0124311e | 664 | #if defined(DEBUG_FLUSH) |
ab3d1727 BS |
665 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
666 | (unsigned long)(code_gen_ptr - code_gen_buffer), | |
667 | nb_tbs, nb_tbs > 0 ? | |
668 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); | |
fd6ce8f6 | 669 | #endif |
26a5f13b | 670 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
a208e54a PB |
671 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
672 | ||
fd6ce8f6 | 673 | nb_tbs = 0; |
3b46e624 | 674 | |
6a00d601 FB |
675 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
676 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); | |
677 | } | |
9fa3e853 | 678 | |
8a8a608f | 679 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
fd6ce8f6 | 680 | page_flush_tb(); |
9fa3e853 | 681 | |
fd6ce8f6 | 682 | code_gen_ptr = code_gen_buffer; |
d4e8164f FB |
683 | /* XXX: flush processor icache at this point if cache flush is |
684 | expensive */ | |
e3db7226 | 685 | tb_flush_count++; |
fd6ce8f6 FB |
686 | } |
687 | ||
688 | #ifdef DEBUG_TB_CHECK | |
689 | ||
bc98a7ef | 690 | static void tb_invalidate_check(target_ulong address) |
fd6ce8f6 FB |
691 | { |
692 | TranslationBlock *tb; | |
693 | int i; | |
694 | address &= TARGET_PAGE_MASK; | |
99773bd4 PB |
695 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
696 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
697 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
698 | address >= tb->pc + tb->size)) { | |
0bf9e31a BS |
699 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
700 | " PC=%08lx size=%04x\n", | |
99773bd4 | 701 | address, (long)tb->pc, tb->size); |
fd6ce8f6 FB |
702 | } |
703 | } | |
704 | } | |
705 | } | |
706 | ||
707 | /* verify that all the pages have correct rights for code */ | |
708 | static void tb_page_check(void) | |
709 | { | |
710 | TranslationBlock *tb; | |
711 | int i, flags1, flags2; | |
3b46e624 | 712 | |
99773bd4 PB |
713 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
714 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { | |
fd6ce8f6 FB |
715 | flags1 = page_get_flags(tb->pc); |
716 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
717 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
718 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
99773bd4 | 719 | (long)tb->pc, tb->size, flags1, flags2); |
fd6ce8f6 FB |
720 | } |
721 | } | |
722 | } | |
723 | } | |
724 | ||
725 | #endif | |
726 | ||
727 | /* invalidate one TB */ | |
728 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, | |
729 | int next_offset) | |
730 | { | |
731 | TranslationBlock *tb1; | |
732 | for(;;) { | |
733 | tb1 = *ptb; | |
734 | if (tb1 == tb) { | |
735 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); | |
736 | break; | |
737 | } | |
738 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); | |
739 | } | |
740 | } | |
741 | ||
9fa3e853 FB |
742 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
743 | { | |
744 | TranslationBlock *tb1; | |
745 | unsigned int n1; | |
746 | ||
747 | for(;;) { | |
748 | tb1 = *ptb; | |
749 | n1 = (long)tb1 & 3; | |
750 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
751 | if (tb1 == tb) { | |
752 | *ptb = tb1->page_next[n1]; | |
753 | break; | |
754 | } | |
755 | ptb = &tb1->page_next[n1]; | |
756 | } | |
757 | } | |
758 | ||
d4e8164f FB |
759 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
760 | { | |
761 | TranslationBlock *tb1, **ptb; | |
762 | unsigned int n1; | |
763 | ||
764 | ptb = &tb->jmp_next[n]; | |
765 | tb1 = *ptb; | |
766 | if (tb1) { | |
767 | /* find tb(n) in circular list */ | |
768 | for(;;) { | |
769 | tb1 = *ptb; | |
770 | n1 = (long)tb1 & 3; | |
771 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
772 | if (n1 == n && tb1 == tb) | |
773 | break; | |
774 | if (n1 == 2) { | |
775 | ptb = &tb1->jmp_first; | |
776 | } else { | |
777 | ptb = &tb1->jmp_next[n1]; | |
778 | } | |
779 | } | |
780 | /* now we can suppress tb(n) from the list */ | |
781 | *ptb = tb->jmp_next[n]; | |
782 | ||
783 | tb->jmp_next[n] = NULL; | |
784 | } | |
785 | } | |
786 | ||
787 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
788 | another TB */ | |
789 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
790 | { | |
791 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); | |
792 | } | |
793 | ||
2e70f6ef | 794 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
fd6ce8f6 | 795 | { |
6a00d601 | 796 | CPUState *env; |
8a40a180 | 797 | PageDesc *p; |
d4e8164f | 798 | unsigned int h, n1; |
c227f099 | 799 | target_phys_addr_t phys_pc; |
8a40a180 | 800 | TranslationBlock *tb1, *tb2; |
3b46e624 | 801 | |
8a40a180 FB |
802 | /* remove the TB from the hash list */ |
803 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
804 | h = tb_phys_hash_func(phys_pc); | |
5fafdf24 | 805 | tb_remove(&tb_phys_hash[h], tb, |
8a40a180 FB |
806 | offsetof(TranslationBlock, phys_hash_next)); |
807 | ||
808 | /* remove the TB from the page list */ | |
809 | if (tb->page_addr[0] != page_addr) { | |
810 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
811 | tb_page_remove(&p->first_tb, tb); | |
812 | invalidate_page_bitmap(p); | |
813 | } | |
814 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
815 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
816 | tb_page_remove(&p->first_tb, tb); | |
817 | invalidate_page_bitmap(p); | |
818 | } | |
819 | ||
36bdbe54 | 820 | tb_invalidated_flag = 1; |
59817ccb | 821 | |
fd6ce8f6 | 822 | /* remove the TB from the hash list */ |
8a40a180 | 823 | h = tb_jmp_cache_hash_func(tb->pc); |
6a00d601 FB |
824 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
825 | if (env->tb_jmp_cache[h] == tb) | |
826 | env->tb_jmp_cache[h] = NULL; | |
827 | } | |
d4e8164f FB |
828 | |
829 | /* suppress this TB from the two jump lists */ | |
830 | tb_jmp_remove(tb, 0); | |
831 | tb_jmp_remove(tb, 1); | |
832 | ||
833 | /* suppress any remaining jumps to this TB */ | |
834 | tb1 = tb->jmp_first; | |
835 | for(;;) { | |
836 | n1 = (long)tb1 & 3; | |
837 | if (n1 == 2) | |
838 | break; | |
839 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
840 | tb2 = tb1->jmp_next[n1]; | |
841 | tb_reset_jump(tb1, n1); | |
842 | tb1->jmp_next[n1] = NULL; | |
843 | tb1 = tb2; | |
844 | } | |
845 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ | |
9fa3e853 | 846 | |
e3db7226 | 847 | tb_phys_invalidate_count++; |
9fa3e853 FB |
848 | } |
849 | ||
850 | static inline void set_bits(uint8_t *tab, int start, int len) | |
851 | { | |
852 | int end, mask, end1; | |
853 | ||
854 | end = start + len; | |
855 | tab += start >> 3; | |
856 | mask = 0xff << (start & 7); | |
857 | if ((start & ~7) == (end & ~7)) { | |
858 | if (start < end) { | |
859 | mask &= ~(0xff << (end & 7)); | |
860 | *tab |= mask; | |
861 | } | |
862 | } else { | |
863 | *tab++ |= mask; | |
864 | start = (start + 8) & ~7; | |
865 | end1 = end & ~7; | |
866 | while (start < end1) { | |
867 | *tab++ = 0xff; | |
868 | start += 8; | |
869 | } | |
870 | if (start < end) { | |
871 | mask = ~(0xff << (end & 7)); | |
872 | *tab |= mask; | |
873 | } | |
874 | } | |
875 | } | |
876 | ||
877 | static void build_page_bitmap(PageDesc *p) | |
878 | { | |
879 | int n, tb_start, tb_end; | |
880 | TranslationBlock *tb; | |
3b46e624 | 881 | |
b2a7081a | 882 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
9fa3e853 FB |
883 | |
884 | tb = p->first_tb; | |
885 | while (tb != NULL) { | |
886 | n = (long)tb & 3; | |
887 | tb = (TranslationBlock *)((long)tb & ~3); | |
888 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
889 | if (n == 0) { | |
890 | /* NOTE: tb_end may be after the end of the page, but | |
891 | it is not a problem */ | |
892 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
893 | tb_end = tb_start + tb->size; | |
894 | if (tb_end > TARGET_PAGE_SIZE) | |
895 | tb_end = TARGET_PAGE_SIZE; | |
896 | } else { | |
897 | tb_start = 0; | |
898 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
899 | } | |
900 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); | |
901 | tb = tb->page_next[n]; | |
902 | } | |
903 | } | |
904 | ||
2e70f6ef PB |
905 | TranslationBlock *tb_gen_code(CPUState *env, |
906 | target_ulong pc, target_ulong cs_base, | |
907 | int flags, int cflags) | |
d720b93d FB |
908 | { |
909 | TranslationBlock *tb; | |
910 | uint8_t *tc_ptr; | |
911 | target_ulong phys_pc, phys_page2, virt_page2; | |
912 | int code_gen_size; | |
913 | ||
c27004ec FB |
914 | phys_pc = get_phys_addr_code(env, pc); |
915 | tb = tb_alloc(pc); | |
d720b93d FB |
916 | if (!tb) { |
917 | /* flush must be done */ | |
918 | tb_flush(env); | |
919 | /* cannot fail at this point */ | |
c27004ec | 920 | tb = tb_alloc(pc); |
2e70f6ef PB |
921 | /* Don't forget to invalidate previous TB info. */ |
922 | tb_invalidated_flag = 1; | |
d720b93d FB |
923 | } |
924 | tc_ptr = code_gen_ptr; | |
925 | tb->tc_ptr = tc_ptr; | |
926 | tb->cs_base = cs_base; | |
927 | tb->flags = flags; | |
928 | tb->cflags = cflags; | |
d07bde88 | 929 | cpu_gen_code(env, tb, &code_gen_size); |
d720b93d | 930 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
3b46e624 | 931 | |
d720b93d | 932 | /* check next page if needed */ |
c27004ec | 933 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
d720b93d | 934 | phys_page2 = -1; |
c27004ec | 935 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
d720b93d FB |
936 | phys_page2 = get_phys_addr_code(env, virt_page2); |
937 | } | |
938 | tb_link_phys(tb, phys_pc, phys_page2); | |
2e70f6ef | 939 | return tb; |
d720b93d | 940 | } |
3b46e624 | 941 | |
9fa3e853 FB |
942 | /* invalidate all TBs which intersect with the target physical page |
943 | starting in range [start;end[. NOTE: start and end must refer to | |
d720b93d FB |
944 | the same physical page. 'is_cpu_write_access' should be true if called |
945 | from a real cpu write access: the virtual CPU will exit the current | |
946 | TB if code is modified inside this TB. */ | |
c227f099 | 947 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
d720b93d FB |
948 | int is_cpu_write_access) |
949 | { | |
6b917547 | 950 | TranslationBlock *tb, *tb_next, *saved_tb; |
d720b93d | 951 | CPUState *env = cpu_single_env; |
9fa3e853 | 952 | target_ulong tb_start, tb_end; |
6b917547 AL |
953 | PageDesc *p; |
954 | int n; | |
955 | #ifdef TARGET_HAS_PRECISE_SMC | |
956 | int current_tb_not_found = is_cpu_write_access; | |
957 | TranslationBlock *current_tb = NULL; | |
958 | int current_tb_modified = 0; | |
959 | target_ulong current_pc = 0; | |
960 | target_ulong current_cs_base = 0; | |
961 | int current_flags = 0; | |
962 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
963 | |
964 | p = page_find(start >> TARGET_PAGE_BITS); | |
5fafdf24 | 965 | if (!p) |
9fa3e853 | 966 | return; |
5fafdf24 | 967 | if (!p->code_bitmap && |
d720b93d FB |
968 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
969 | is_cpu_write_access) { | |
9fa3e853 FB |
970 | /* build code bitmap */ |
971 | build_page_bitmap(p); | |
972 | } | |
973 | ||
974 | /* we remove all the TBs in the range [start, end[ */ | |
975 | /* XXX: see if in some cases it could be faster to invalidate all the code */ | |
976 | tb = p->first_tb; | |
977 | while (tb != NULL) { | |
978 | n = (long)tb & 3; | |
979 | tb = (TranslationBlock *)((long)tb & ~3); | |
980 | tb_next = tb->page_next[n]; | |
981 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
982 | if (n == 0) { | |
983 | /* NOTE: tb_end may be after the end of the page, but | |
984 | it is not a problem */ | |
985 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
986 | tb_end = tb_start + tb->size; | |
987 | } else { | |
988 | tb_start = tb->page_addr[1]; | |
989 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
990 | } | |
991 | if (!(tb_end <= start || tb_start >= end)) { | |
d720b93d FB |
992 | #ifdef TARGET_HAS_PRECISE_SMC |
993 | if (current_tb_not_found) { | |
994 | current_tb_not_found = 0; | |
995 | current_tb = NULL; | |
2e70f6ef | 996 | if (env->mem_io_pc) { |
d720b93d | 997 | /* now we have a real cpu fault */ |
2e70f6ef | 998 | current_tb = tb_find_pc(env->mem_io_pc); |
d720b93d FB |
999 | } |
1000 | } | |
1001 | if (current_tb == tb && | |
2e70f6ef | 1002 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1003 | /* If we are modifying the current TB, we must stop |
1004 | its execution. We could be more precise by checking | |
1005 | that the modification is after the current PC, but it | |
1006 | would require a specialized function to partially | |
1007 | restore the CPU state */ | |
3b46e624 | 1008 | |
d720b93d | 1009 | current_tb_modified = 1; |
5fafdf24 | 1010 | cpu_restore_state(current_tb, env, |
2e70f6ef | 1011 | env->mem_io_pc, NULL); |
6b917547 AL |
1012 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1013 | ¤t_flags); | |
d720b93d FB |
1014 | } |
1015 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
6f5a9f7e FB |
1016 | /* we need to do that to handle the case where a signal |
1017 | occurs while doing tb_phys_invalidate() */ | |
1018 | saved_tb = NULL; | |
1019 | if (env) { | |
1020 | saved_tb = env->current_tb; | |
1021 | env->current_tb = NULL; | |
1022 | } | |
9fa3e853 | 1023 | tb_phys_invalidate(tb, -1); |
6f5a9f7e FB |
1024 | if (env) { |
1025 | env->current_tb = saved_tb; | |
1026 | if (env->interrupt_request && env->current_tb) | |
1027 | cpu_interrupt(env, env->interrupt_request); | |
1028 | } | |
9fa3e853 FB |
1029 | } |
1030 | tb = tb_next; | |
1031 | } | |
1032 | #if !defined(CONFIG_USER_ONLY) | |
1033 | /* if no code remaining, no need to continue to use slow writes */ | |
1034 | if (!p->first_tb) { | |
1035 | invalidate_page_bitmap(p); | |
d720b93d | 1036 | if (is_cpu_write_access) { |
2e70f6ef | 1037 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
d720b93d FB |
1038 | } |
1039 | } | |
1040 | #endif | |
1041 | #ifdef TARGET_HAS_PRECISE_SMC | |
1042 | if (current_tb_modified) { | |
1043 | /* we generate a block containing just the instruction | |
1044 | modifying the memory. It will ensure that it cannot modify | |
1045 | itself */ | |
ea1c1802 | 1046 | env->current_tb = NULL; |
2e70f6ef | 1047 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d | 1048 | cpu_resume_from_signal(env, NULL); |
9fa3e853 | 1049 | } |
fd6ce8f6 | 1050 | #endif |
9fa3e853 | 1051 | } |
fd6ce8f6 | 1052 | |
9fa3e853 | 1053 | /* len must be <= 8 and start must be a multiple of len */ |
c227f099 | 1054 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
9fa3e853 FB |
1055 | { |
1056 | PageDesc *p; | |
1057 | int offset, b; | |
59817ccb | 1058 | #if 0 |
a4193c8a | 1059 | if (1) { |
93fcfe39 AL |
1060 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
1061 | cpu_single_env->mem_io_vaddr, len, | |
1062 | cpu_single_env->eip, | |
1063 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); | |
59817ccb FB |
1064 | } |
1065 | #endif | |
9fa3e853 | 1066 | p = page_find(start >> TARGET_PAGE_BITS); |
5fafdf24 | 1067 | if (!p) |
9fa3e853 FB |
1068 | return; |
1069 | if (p->code_bitmap) { | |
1070 | offset = start & ~TARGET_PAGE_MASK; | |
1071 | b = p->code_bitmap[offset >> 3] >> (offset & 7); | |
1072 | if (b & ((1 << len) - 1)) | |
1073 | goto do_invalidate; | |
1074 | } else { | |
1075 | do_invalidate: | |
d720b93d | 1076 | tb_invalidate_phys_page_range(start, start + len, 1); |
9fa3e853 FB |
1077 | } |
1078 | } | |
1079 | ||
9fa3e853 | 1080 | #if !defined(CONFIG_SOFTMMU) |
c227f099 | 1081 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
d720b93d | 1082 | unsigned long pc, void *puc) |
9fa3e853 | 1083 | { |
6b917547 | 1084 | TranslationBlock *tb; |
9fa3e853 | 1085 | PageDesc *p; |
6b917547 | 1086 | int n; |
d720b93d | 1087 | #ifdef TARGET_HAS_PRECISE_SMC |
6b917547 | 1088 | TranslationBlock *current_tb = NULL; |
d720b93d | 1089 | CPUState *env = cpu_single_env; |
6b917547 AL |
1090 | int current_tb_modified = 0; |
1091 | target_ulong current_pc = 0; | |
1092 | target_ulong current_cs_base = 0; | |
1093 | int current_flags = 0; | |
d720b93d | 1094 | #endif |
9fa3e853 FB |
1095 | |
1096 | addr &= TARGET_PAGE_MASK; | |
1097 | p = page_find(addr >> TARGET_PAGE_BITS); | |
5fafdf24 | 1098 | if (!p) |
9fa3e853 FB |
1099 | return; |
1100 | tb = p->first_tb; | |
d720b93d FB |
1101 | #ifdef TARGET_HAS_PRECISE_SMC |
1102 | if (tb && pc != 0) { | |
1103 | current_tb = tb_find_pc(pc); | |
1104 | } | |
1105 | #endif | |
9fa3e853 FB |
1106 | while (tb != NULL) { |
1107 | n = (long)tb & 3; | |
1108 | tb = (TranslationBlock *)((long)tb & ~3); | |
d720b93d FB |
1109 | #ifdef TARGET_HAS_PRECISE_SMC |
1110 | if (current_tb == tb && | |
2e70f6ef | 1111 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
d720b93d FB |
1112 | /* If we are modifying the current TB, we must stop |
1113 | its execution. We could be more precise by checking | |
1114 | that the modification is after the current PC, but it | |
1115 | would require a specialized function to partially | |
1116 | restore the CPU state */ | |
3b46e624 | 1117 | |
d720b93d FB |
1118 | current_tb_modified = 1; |
1119 | cpu_restore_state(current_tb, env, pc, puc); | |
6b917547 AL |
1120 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1121 | ¤t_flags); | |
d720b93d FB |
1122 | } |
1123 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
9fa3e853 FB |
1124 | tb_phys_invalidate(tb, addr); |
1125 | tb = tb->page_next[n]; | |
1126 | } | |
fd6ce8f6 | 1127 | p->first_tb = NULL; |
d720b93d FB |
1128 | #ifdef TARGET_HAS_PRECISE_SMC |
1129 | if (current_tb_modified) { | |
1130 | /* we generate a block containing just the instruction | |
1131 | modifying the memory. It will ensure that it cannot modify | |
1132 | itself */ | |
ea1c1802 | 1133 | env->current_tb = NULL; |
2e70f6ef | 1134 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
d720b93d FB |
1135 | cpu_resume_from_signal(env, puc); |
1136 | } | |
1137 | #endif | |
fd6ce8f6 | 1138 | } |
9fa3e853 | 1139 | #endif |
fd6ce8f6 FB |
1140 | |
1141 | /* add the tb in the target page and protect it if necessary */ | |
5fafdf24 | 1142 | static inline void tb_alloc_page(TranslationBlock *tb, |
53a5960a | 1143 | unsigned int n, target_ulong page_addr) |
fd6ce8f6 FB |
1144 | { |
1145 | PageDesc *p; | |
9fa3e853 FB |
1146 | TranslationBlock *last_first_tb; |
1147 | ||
1148 | tb->page_addr[n] = page_addr; | |
5cd2c5b6 | 1149 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
9fa3e853 FB |
1150 | tb->page_next[n] = p->first_tb; |
1151 | last_first_tb = p->first_tb; | |
1152 | p->first_tb = (TranslationBlock *)((long)tb | n); | |
1153 | invalidate_page_bitmap(p); | |
fd6ce8f6 | 1154 | |
107db443 | 1155 | #if defined(TARGET_HAS_SMC) || 1 |
d720b93d | 1156 | |
9fa3e853 | 1157 | #if defined(CONFIG_USER_ONLY) |
fd6ce8f6 | 1158 | if (p->flags & PAGE_WRITE) { |
53a5960a PB |
1159 | target_ulong addr; |
1160 | PageDesc *p2; | |
9fa3e853 FB |
1161 | int prot; |
1162 | ||
fd6ce8f6 FB |
1163 | /* force the host page as non writable (writes will have a |
1164 | page fault + mprotect overhead) */ | |
53a5960a | 1165 | page_addr &= qemu_host_page_mask; |
fd6ce8f6 | 1166 | prot = 0; |
53a5960a PB |
1167 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
1168 | addr += TARGET_PAGE_SIZE) { | |
1169 | ||
1170 | p2 = page_find (addr >> TARGET_PAGE_BITS); | |
1171 | if (!p2) | |
1172 | continue; | |
1173 | prot |= p2->flags; | |
1174 | p2->flags &= ~PAGE_WRITE; | |
1175 | page_get_flags(addr); | |
1176 | } | |
5fafdf24 | 1177 | mprotect(g2h(page_addr), qemu_host_page_size, |
fd6ce8f6 FB |
1178 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
1179 | #ifdef DEBUG_TB_INVALIDATE | |
ab3d1727 | 1180 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
53a5960a | 1181 | page_addr); |
fd6ce8f6 | 1182 | #endif |
fd6ce8f6 | 1183 | } |
9fa3e853 FB |
1184 | #else |
1185 | /* if some code is already present, then the pages are already | |
1186 | protected. So we handle the case where only the first TB is | |
1187 | allocated in a physical page */ | |
1188 | if (!last_first_tb) { | |
6a00d601 | 1189 | tlb_protect_code(page_addr); |
9fa3e853 FB |
1190 | } |
1191 | #endif | |
d720b93d FB |
1192 | |
1193 | #endif /* TARGET_HAS_SMC */ | |
fd6ce8f6 FB |
1194 | } |
1195 | ||
1196 | /* Allocate a new translation block. Flush the translation buffer if | |
1197 | too many translation blocks or too much generated code. */ | |
c27004ec | 1198 | TranslationBlock *tb_alloc(target_ulong pc) |
fd6ce8f6 FB |
1199 | { |
1200 | TranslationBlock *tb; | |
fd6ce8f6 | 1201 | |
26a5f13b FB |
1202 | if (nb_tbs >= code_gen_max_blocks || |
1203 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) | |
d4e8164f | 1204 | return NULL; |
fd6ce8f6 FB |
1205 | tb = &tbs[nb_tbs++]; |
1206 | tb->pc = pc; | |
b448f2f3 | 1207 | tb->cflags = 0; |
d4e8164f FB |
1208 | return tb; |
1209 | } | |
1210 | ||
2e70f6ef PB |
1211 | void tb_free(TranslationBlock *tb) |
1212 | { | |
bf20dc07 | 1213 | /* In practice this is mostly used for single use temporary TB |
2e70f6ef PB |
1214 | Ignore the hard cases and just back up if this TB happens to |
1215 | be the last one generated. */ | |
1216 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { | |
1217 | code_gen_ptr = tb->tc_ptr; | |
1218 | nb_tbs--; | |
1219 | } | |
1220 | } | |
1221 | ||
9fa3e853 FB |
1222 | /* add a new TB and link it to the physical page tables. phys_page2 is |
1223 | (-1) to indicate that only one page contains the TB. */ | |
5fafdf24 | 1224 | void tb_link_phys(TranslationBlock *tb, |
9fa3e853 | 1225 | target_ulong phys_pc, target_ulong phys_page2) |
d4e8164f | 1226 | { |
9fa3e853 FB |
1227 | unsigned int h; |
1228 | TranslationBlock **ptb; | |
1229 | ||
c8a706fe PB |
1230 | /* Grab the mmap lock to stop another thread invalidating this TB |
1231 | before we are done. */ | |
1232 | mmap_lock(); | |
9fa3e853 FB |
1233 | /* add in the physical hash table */ |
1234 | h = tb_phys_hash_func(phys_pc); | |
1235 | ptb = &tb_phys_hash[h]; | |
1236 | tb->phys_hash_next = *ptb; | |
1237 | *ptb = tb; | |
fd6ce8f6 FB |
1238 | |
1239 | /* add in the page list */ | |
9fa3e853 FB |
1240 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
1241 | if (phys_page2 != -1) | |
1242 | tb_alloc_page(tb, 1, phys_page2); | |
1243 | else | |
1244 | tb->page_addr[1] = -1; | |
9fa3e853 | 1245 | |
d4e8164f FB |
1246 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
1247 | tb->jmp_next[0] = NULL; | |
1248 | tb->jmp_next[1] = NULL; | |
1249 | ||
1250 | /* init original jump addresses */ | |
1251 | if (tb->tb_next_offset[0] != 0xffff) | |
1252 | tb_reset_jump(tb, 0); | |
1253 | if (tb->tb_next_offset[1] != 0xffff) | |
1254 | tb_reset_jump(tb, 1); | |
8a40a180 FB |
1255 | |
1256 | #ifdef DEBUG_TB_CHECK | |
1257 | tb_page_check(); | |
1258 | #endif | |
c8a706fe | 1259 | mmap_unlock(); |
fd6ce8f6 FB |
1260 | } |
1261 | ||
9fa3e853 FB |
1262 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1263 | tb[1].tc_ptr. Return NULL if not found */ | |
1264 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) | |
fd6ce8f6 | 1265 | { |
9fa3e853 FB |
1266 | int m_min, m_max, m; |
1267 | unsigned long v; | |
1268 | TranslationBlock *tb; | |
a513fe19 FB |
1269 | |
1270 | if (nb_tbs <= 0) | |
1271 | return NULL; | |
1272 | if (tc_ptr < (unsigned long)code_gen_buffer || | |
1273 | tc_ptr >= (unsigned long)code_gen_ptr) | |
1274 | return NULL; | |
1275 | /* binary search (cf Knuth) */ | |
1276 | m_min = 0; | |
1277 | m_max = nb_tbs - 1; | |
1278 | while (m_min <= m_max) { | |
1279 | m = (m_min + m_max) >> 1; | |
1280 | tb = &tbs[m]; | |
1281 | v = (unsigned long)tb->tc_ptr; | |
1282 | if (v == tc_ptr) | |
1283 | return tb; | |
1284 | else if (tc_ptr < v) { | |
1285 | m_max = m - 1; | |
1286 | } else { | |
1287 | m_min = m + 1; | |
1288 | } | |
5fafdf24 | 1289 | } |
a513fe19 FB |
1290 | return &tbs[m_max]; |
1291 | } | |
7501267e | 1292 | |
ea041c0e FB |
1293 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
1294 | ||
1295 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) | |
1296 | { | |
1297 | TranslationBlock *tb1, *tb_next, **ptb; | |
1298 | unsigned int n1; | |
1299 | ||
1300 | tb1 = tb->jmp_next[n]; | |
1301 | if (tb1 != NULL) { | |
1302 | /* find head of list */ | |
1303 | for(;;) { | |
1304 | n1 = (long)tb1 & 3; | |
1305 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1306 | if (n1 == 2) | |
1307 | break; | |
1308 | tb1 = tb1->jmp_next[n1]; | |
1309 | } | |
1310 | /* we are now sure now that tb jumps to tb1 */ | |
1311 | tb_next = tb1; | |
1312 | ||
1313 | /* remove tb from the jmp_first list */ | |
1314 | ptb = &tb_next->jmp_first; | |
1315 | for(;;) { | |
1316 | tb1 = *ptb; | |
1317 | n1 = (long)tb1 & 3; | |
1318 | tb1 = (TranslationBlock *)((long)tb1 & ~3); | |
1319 | if (n1 == n && tb1 == tb) | |
1320 | break; | |
1321 | ptb = &tb1->jmp_next[n1]; | |
1322 | } | |
1323 | *ptb = tb->jmp_next[n]; | |
1324 | tb->jmp_next[n] = NULL; | |
3b46e624 | 1325 | |
ea041c0e FB |
1326 | /* suppress the jump to next tb in generated code */ |
1327 | tb_reset_jump(tb, n); | |
1328 | ||
0124311e | 1329 | /* suppress jumps in the tb on which we could have jumped */ |
ea041c0e FB |
1330 | tb_reset_jump_recursive(tb_next); |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static void tb_reset_jump_recursive(TranslationBlock *tb) | |
1335 | { | |
1336 | tb_reset_jump_recursive2(tb, 0); | |
1337 | tb_reset_jump_recursive2(tb, 1); | |
1338 | } | |
1339 | ||
1fddef4b | 1340 | #if defined(TARGET_HAS_ICE) |
94df27fd PB |
1341 | #if defined(CONFIG_USER_ONLY) |
1342 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) | |
1343 | { | |
1344 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
1345 | } | |
1346 | #else | |
d720b93d FB |
1347 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
1348 | { | |
c227f099 | 1349 | target_phys_addr_t addr; |
9b3c35e0 | 1350 | target_ulong pd; |
c227f099 | 1351 | ram_addr_t ram_addr; |
c2f07f81 | 1352 | PhysPageDesc *p; |
d720b93d | 1353 | |
c2f07f81 PB |
1354 | addr = cpu_get_phys_page_debug(env, pc); |
1355 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
1356 | if (!p) { | |
1357 | pd = IO_MEM_UNASSIGNED; | |
1358 | } else { | |
1359 | pd = p->phys_offset; | |
1360 | } | |
1361 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); | |
706cd4b5 | 1362 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
d720b93d | 1363 | } |
c27004ec | 1364 | #endif |
94df27fd | 1365 | #endif /* TARGET_HAS_ICE */ |
d720b93d | 1366 | |
c527ee8f PB |
1367 | #if defined(CONFIG_USER_ONLY) |
1368 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1369 | ||
1370 | { | |
1371 | } | |
1372 | ||
1373 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, | |
1374 | int flags, CPUWatchpoint **watchpoint) | |
1375 | { | |
1376 | return -ENOSYS; | |
1377 | } | |
1378 | #else | |
6658ffb8 | 1379 | /* Add a watchpoint. */ |
a1d1bb31 AL |
1380 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
1381 | int flags, CPUWatchpoint **watchpoint) | |
6658ffb8 | 1382 | { |
b4051334 | 1383 | target_ulong len_mask = ~(len - 1); |
c0ce998e | 1384 | CPUWatchpoint *wp; |
6658ffb8 | 1385 | |
b4051334 AL |
1386 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
1387 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { | |
1388 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " | |
1389 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); | |
1390 | return -EINVAL; | |
1391 | } | |
a1d1bb31 | 1392 | wp = qemu_malloc(sizeof(*wp)); |
a1d1bb31 AL |
1393 | |
1394 | wp->vaddr = addr; | |
b4051334 | 1395 | wp->len_mask = len_mask; |
a1d1bb31 AL |
1396 | wp->flags = flags; |
1397 | ||
2dc9f411 | 1398 | /* keep all GDB-injected watchpoints in front */ |
c0ce998e | 1399 | if (flags & BP_GDB) |
72cf2d4f | 1400 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
c0ce998e | 1401 | else |
72cf2d4f | 1402 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
6658ffb8 | 1403 | |
6658ffb8 | 1404 | tlb_flush_page(env, addr); |
a1d1bb31 AL |
1405 | |
1406 | if (watchpoint) | |
1407 | *watchpoint = wp; | |
1408 | return 0; | |
6658ffb8 PB |
1409 | } |
1410 | ||
a1d1bb31 AL |
1411 | /* Remove a specific watchpoint. */ |
1412 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, | |
1413 | int flags) | |
6658ffb8 | 1414 | { |
b4051334 | 1415 | target_ulong len_mask = ~(len - 1); |
a1d1bb31 | 1416 | CPUWatchpoint *wp; |
6658ffb8 | 1417 | |
72cf2d4f | 1418 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 | 1419 | if (addr == wp->vaddr && len_mask == wp->len_mask |
6e140f28 | 1420 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
a1d1bb31 | 1421 | cpu_watchpoint_remove_by_ref(env, wp); |
6658ffb8 PB |
1422 | return 0; |
1423 | } | |
1424 | } | |
a1d1bb31 | 1425 | return -ENOENT; |
6658ffb8 PB |
1426 | } |
1427 | ||
a1d1bb31 AL |
1428 | /* Remove a specific watchpoint by reference. */ |
1429 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) | |
1430 | { | |
72cf2d4f | 1431 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
7d03f82f | 1432 | |
a1d1bb31 AL |
1433 | tlb_flush_page(env, watchpoint->vaddr); |
1434 | ||
1435 | qemu_free(watchpoint); | |
1436 | } | |
1437 | ||
1438 | /* Remove all matching watchpoints. */ | |
1439 | void cpu_watchpoint_remove_all(CPUState *env, int mask) | |
1440 | { | |
c0ce998e | 1441 | CPUWatchpoint *wp, *next; |
a1d1bb31 | 1442 | |
72cf2d4f | 1443 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
a1d1bb31 AL |
1444 | if (wp->flags & mask) |
1445 | cpu_watchpoint_remove_by_ref(env, wp); | |
c0ce998e | 1446 | } |
7d03f82f | 1447 | } |
c527ee8f | 1448 | #endif |
7d03f82f | 1449 | |
a1d1bb31 AL |
1450 | /* Add a breakpoint. */ |
1451 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, | |
1452 | CPUBreakpoint **breakpoint) | |
4c3a88a2 | 1453 | { |
1fddef4b | 1454 | #if defined(TARGET_HAS_ICE) |
c0ce998e | 1455 | CPUBreakpoint *bp; |
3b46e624 | 1456 | |
a1d1bb31 | 1457 | bp = qemu_malloc(sizeof(*bp)); |
4c3a88a2 | 1458 | |
a1d1bb31 AL |
1459 | bp->pc = pc; |
1460 | bp->flags = flags; | |
1461 | ||
2dc9f411 | 1462 | /* keep all GDB-injected breakpoints in front */ |
c0ce998e | 1463 | if (flags & BP_GDB) |
72cf2d4f | 1464 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
c0ce998e | 1465 | else |
72cf2d4f | 1466 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
3b46e624 | 1467 | |
d720b93d | 1468 | breakpoint_invalidate(env, pc); |
a1d1bb31 AL |
1469 | |
1470 | if (breakpoint) | |
1471 | *breakpoint = bp; | |
4c3a88a2 FB |
1472 | return 0; |
1473 | #else | |
a1d1bb31 | 1474 | return -ENOSYS; |
4c3a88a2 FB |
1475 | #endif |
1476 | } | |
1477 | ||
a1d1bb31 AL |
1478 | /* Remove a specific breakpoint. */ |
1479 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) | |
1480 | { | |
7d03f82f | 1481 | #if defined(TARGET_HAS_ICE) |
a1d1bb31 AL |
1482 | CPUBreakpoint *bp; |
1483 | ||
72cf2d4f | 1484 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
a1d1bb31 AL |
1485 | if (bp->pc == pc && bp->flags == flags) { |
1486 | cpu_breakpoint_remove_by_ref(env, bp); | |
1487 | return 0; | |
1488 | } | |
7d03f82f | 1489 | } |
a1d1bb31 AL |
1490 | return -ENOENT; |
1491 | #else | |
1492 | return -ENOSYS; | |
7d03f82f EI |
1493 | #endif |
1494 | } | |
1495 | ||
a1d1bb31 AL |
1496 | /* Remove a specific breakpoint by reference. */ |
1497 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) | |
4c3a88a2 | 1498 | { |
1fddef4b | 1499 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1500 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
d720b93d | 1501 | |
a1d1bb31 AL |
1502 | breakpoint_invalidate(env, breakpoint->pc); |
1503 | ||
1504 | qemu_free(breakpoint); | |
1505 | #endif | |
1506 | } | |
1507 | ||
1508 | /* Remove all matching breakpoints. */ | |
1509 | void cpu_breakpoint_remove_all(CPUState *env, int mask) | |
1510 | { | |
1511 | #if defined(TARGET_HAS_ICE) | |
c0ce998e | 1512 | CPUBreakpoint *bp, *next; |
a1d1bb31 | 1513 | |
72cf2d4f | 1514 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
a1d1bb31 AL |
1515 | if (bp->flags & mask) |
1516 | cpu_breakpoint_remove_by_ref(env, bp); | |
c0ce998e | 1517 | } |
4c3a88a2 FB |
1518 | #endif |
1519 | } | |
1520 | ||
c33a346e FB |
1521 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
1522 | CPU loop after each instruction */ | |
1523 | void cpu_single_step(CPUState *env, int enabled) | |
1524 | { | |
1fddef4b | 1525 | #if defined(TARGET_HAS_ICE) |
c33a346e FB |
1526 | if (env->singlestep_enabled != enabled) { |
1527 | env->singlestep_enabled = enabled; | |
e22a25c9 AL |
1528 | if (kvm_enabled()) |
1529 | kvm_update_guest_debug(env, 0); | |
1530 | else { | |
ccbb4d44 | 1531 | /* must flush all the translated code to avoid inconsistencies */ |
e22a25c9 AL |
1532 | /* XXX: only flush what is necessary */ |
1533 | tb_flush(env); | |
1534 | } | |
c33a346e FB |
1535 | } |
1536 | #endif | |
1537 | } | |
1538 | ||
34865134 FB |
1539 | /* enable or disable low levels log */ |
1540 | void cpu_set_log(int log_flags) | |
1541 | { | |
1542 | loglevel = log_flags; | |
1543 | if (loglevel && !logfile) { | |
11fcfab4 | 1544 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
34865134 FB |
1545 | if (!logfile) { |
1546 | perror(logfilename); | |
1547 | _exit(1); | |
1548 | } | |
9fa3e853 FB |
1549 | #if !defined(CONFIG_SOFTMMU) |
1550 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ | |
1551 | { | |
b55266b5 | 1552 | static char logfile_buf[4096]; |
9fa3e853 FB |
1553 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
1554 | } | |
bf65f53f FN |
1555 | #elif !defined(_WIN32) |
1556 | /* Win32 doesn't support line-buffering and requires size >= 2 */ | |
34865134 | 1557 | setvbuf(logfile, NULL, _IOLBF, 0); |
9fa3e853 | 1558 | #endif |
e735b91c PB |
1559 | log_append = 1; |
1560 | } | |
1561 | if (!loglevel && logfile) { | |
1562 | fclose(logfile); | |
1563 | logfile = NULL; | |
34865134 FB |
1564 | } |
1565 | } | |
1566 | ||
1567 | void cpu_set_log_filename(const char *filename) | |
1568 | { | |
1569 | logfilename = strdup(filename); | |
e735b91c PB |
1570 | if (logfile) { |
1571 | fclose(logfile); | |
1572 | logfile = NULL; | |
1573 | } | |
1574 | cpu_set_log(loglevel); | |
34865134 | 1575 | } |
c33a346e | 1576 | |
3098dba0 | 1577 | static void cpu_unlink_tb(CPUState *env) |
ea041c0e | 1578 | { |
3098dba0 AJ |
1579 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
1580 | problem and hope the cpu will stop of its own accord. For userspace | |
1581 | emulation this often isn't actually as bad as it sounds. Often | |
1582 | signals are used primarily to interrupt blocking syscalls. */ | |
ea041c0e | 1583 | TranslationBlock *tb; |
c227f099 | 1584 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
59817ccb | 1585 | |
cab1b4bd | 1586 | spin_lock(&interrupt_lock); |
3098dba0 AJ |
1587 | tb = env->current_tb; |
1588 | /* if the cpu is currently executing code, we must unlink it and | |
1589 | all the potentially executing TB */ | |
f76cfe56 | 1590 | if (tb) { |
3098dba0 AJ |
1591 | env->current_tb = NULL; |
1592 | tb_reset_jump_recursive(tb); | |
be214e6c | 1593 | } |
cab1b4bd | 1594 | spin_unlock(&interrupt_lock); |
3098dba0 AJ |
1595 | } |
1596 | ||
1597 | /* mask must never be zero, except for A20 change call */ | |
1598 | void cpu_interrupt(CPUState *env, int mask) | |
1599 | { | |
1600 | int old_mask; | |
be214e6c | 1601 | |
2e70f6ef | 1602 | old_mask = env->interrupt_request; |
68a79315 | 1603 | env->interrupt_request |= mask; |
3098dba0 | 1604 | |
8edac960 AL |
1605 | #ifndef CONFIG_USER_ONLY |
1606 | /* | |
1607 | * If called from iothread context, wake the target cpu in | |
1608 | * case its halted. | |
1609 | */ | |
1610 | if (!qemu_cpu_self(env)) { | |
1611 | qemu_cpu_kick(env); | |
1612 | return; | |
1613 | } | |
1614 | #endif | |
1615 | ||
2e70f6ef | 1616 | if (use_icount) { |
266910c4 | 1617 | env->icount_decr.u16.high = 0xffff; |
2e70f6ef | 1618 | #ifndef CONFIG_USER_ONLY |
2e70f6ef | 1619 | if (!can_do_io(env) |
be214e6c | 1620 | && (mask & ~old_mask) != 0) { |
2e70f6ef PB |
1621 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
1622 | } | |
1623 | #endif | |
1624 | } else { | |
3098dba0 | 1625 | cpu_unlink_tb(env); |
ea041c0e FB |
1626 | } |
1627 | } | |
1628 | ||
b54ad049 FB |
1629 | void cpu_reset_interrupt(CPUState *env, int mask) |
1630 | { | |
1631 | env->interrupt_request &= ~mask; | |
1632 | } | |
1633 | ||
3098dba0 AJ |
1634 | void cpu_exit(CPUState *env) |
1635 | { | |
1636 | env->exit_request = 1; | |
1637 | cpu_unlink_tb(env); | |
1638 | } | |
1639 | ||
c7cd6a37 | 1640 | const CPULogItem cpu_log_items[] = { |
5fafdf24 | 1641 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
f193c797 FB |
1642 | "show generated host assembly code for each compiled TB" }, |
1643 | { CPU_LOG_TB_IN_ASM, "in_asm", | |
1644 | "show target assembly code for each compiled TB" }, | |
5fafdf24 | 1645 | { CPU_LOG_TB_OP, "op", |
57fec1fe | 1646 | "show micro ops for each compiled TB" }, |
f193c797 | 1647 | { CPU_LOG_TB_OP_OPT, "op_opt", |
e01a1157 BS |
1648 | "show micro ops " |
1649 | #ifdef TARGET_I386 | |
1650 | "before eflags optimization and " | |
f193c797 | 1651 | #endif |
e01a1157 | 1652 | "after liveness analysis" }, |
f193c797 FB |
1653 | { CPU_LOG_INT, "int", |
1654 | "show interrupts/exceptions in short format" }, | |
1655 | { CPU_LOG_EXEC, "exec", | |
1656 | "show trace before each executed TB (lots of logs)" }, | |
9fddaa0c | 1657 | { CPU_LOG_TB_CPU, "cpu", |
e91c8a77 | 1658 | "show CPU state before block translation" }, |
f193c797 FB |
1659 | #ifdef TARGET_I386 |
1660 | { CPU_LOG_PCALL, "pcall", | |
1661 | "show protected mode far calls/returns/exceptions" }, | |
eca1bdf4 AL |
1662 | { CPU_LOG_RESET, "cpu_reset", |
1663 | "show CPU state before CPU resets" }, | |
f193c797 | 1664 | #endif |
8e3a9fd2 | 1665 | #ifdef DEBUG_IOPORT |
fd872598 FB |
1666 | { CPU_LOG_IOPORT, "ioport", |
1667 | "show all i/o ports accesses" }, | |
8e3a9fd2 | 1668 | #endif |
f193c797 FB |
1669 | { 0, NULL, NULL }, |
1670 | }; | |
1671 | ||
f6f3fbca MT |
1672 | #ifndef CONFIG_USER_ONLY |
1673 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list | |
1674 | = QLIST_HEAD_INITIALIZER(memory_client_list); | |
1675 | ||
1676 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, | |
1677 | ram_addr_t size, | |
1678 | ram_addr_t phys_offset) | |
1679 | { | |
1680 | CPUPhysMemoryClient *client; | |
1681 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1682 | client->set_memory(client, start_addr, size, phys_offset); | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, | |
1687 | target_phys_addr_t end) | |
1688 | { | |
1689 | CPUPhysMemoryClient *client; | |
1690 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1691 | int r = client->sync_dirty_bitmap(client, start, end); | |
1692 | if (r < 0) | |
1693 | return r; | |
1694 | } | |
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | static int cpu_notify_migration_log(int enable) | |
1699 | { | |
1700 | CPUPhysMemoryClient *client; | |
1701 | QLIST_FOREACH(client, &memory_client_list, list) { | |
1702 | int r = client->migration_log(client, enable); | |
1703 | if (r < 0) | |
1704 | return r; | |
1705 | } | |
1706 | return 0; | |
1707 | } | |
1708 | ||
5cd2c5b6 RH |
1709 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, |
1710 | int level, void **lp) | |
f6f3fbca | 1711 | { |
5cd2c5b6 | 1712 | int i; |
f6f3fbca | 1713 | |
5cd2c5b6 RH |
1714 | if (*lp == NULL) { |
1715 | return; | |
1716 | } | |
1717 | if (level == 0) { | |
1718 | PhysPageDesc *pd = *lp; | |
1719 | for (i = 0; i < L2_BITS; ++i) { | |
1720 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { | |
1721 | client->set_memory(client, pd[i].region_offset, | |
1722 | TARGET_PAGE_SIZE, pd[i].phys_offset); | |
f6f3fbca | 1723 | } |
5cd2c5b6 RH |
1724 | } |
1725 | } else { | |
1726 | void **pp = *lp; | |
1727 | for (i = 0; i < L2_BITS; ++i) { | |
1728 | phys_page_for_each_1(client, level - 1, pp + i); | |
f6f3fbca MT |
1729 | } |
1730 | } | |
1731 | } | |
1732 | ||
1733 | static void phys_page_for_each(CPUPhysMemoryClient *client) | |
1734 | { | |
5cd2c5b6 RH |
1735 | int i; |
1736 | for (i = 0; i < P_L1_SIZE; ++i) { | |
1737 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, | |
1738 | l1_phys_map + 1); | |
f6f3fbca | 1739 | } |
f6f3fbca MT |
1740 | } |
1741 | ||
1742 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) | |
1743 | { | |
1744 | QLIST_INSERT_HEAD(&memory_client_list, client, list); | |
1745 | phys_page_for_each(client); | |
1746 | } | |
1747 | ||
1748 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) | |
1749 | { | |
1750 | QLIST_REMOVE(client, list); | |
1751 | } | |
1752 | #endif | |
1753 | ||
f193c797 FB |
1754 | static int cmp1(const char *s1, int n, const char *s2) |
1755 | { | |
1756 | if (strlen(s2) != n) | |
1757 | return 0; | |
1758 | return memcmp(s1, s2, n) == 0; | |
1759 | } | |
3b46e624 | 1760 | |
f193c797 FB |
1761 | /* takes a comma separated list of log masks. Return 0 if error. */ |
1762 | int cpu_str_to_log_mask(const char *str) | |
1763 | { | |
c7cd6a37 | 1764 | const CPULogItem *item; |
f193c797 FB |
1765 | int mask; |
1766 | const char *p, *p1; | |
1767 | ||
1768 | p = str; | |
1769 | mask = 0; | |
1770 | for(;;) { | |
1771 | p1 = strchr(p, ','); | |
1772 | if (!p1) | |
1773 | p1 = p + strlen(p); | |
8e3a9fd2 FB |
1774 | if(cmp1(p,p1-p,"all")) { |
1775 | for(item = cpu_log_items; item->mask != 0; item++) { | |
1776 | mask |= item->mask; | |
1777 | } | |
1778 | } else { | |
f193c797 FB |
1779 | for(item = cpu_log_items; item->mask != 0; item++) { |
1780 | if (cmp1(p, p1 - p, item->name)) | |
1781 | goto found; | |
1782 | } | |
1783 | return 0; | |
8e3a9fd2 | 1784 | } |
f193c797 FB |
1785 | found: |
1786 | mask |= item->mask; | |
1787 | if (*p1 != ',') | |
1788 | break; | |
1789 | p = p1 + 1; | |
1790 | } | |
1791 | return mask; | |
1792 | } | |
ea041c0e | 1793 | |
7501267e FB |
1794 | void cpu_abort(CPUState *env, const char *fmt, ...) |
1795 | { | |
1796 | va_list ap; | |
493ae1f0 | 1797 | va_list ap2; |
7501267e FB |
1798 | |
1799 | va_start(ap, fmt); | |
493ae1f0 | 1800 | va_copy(ap2, ap); |
7501267e FB |
1801 | fprintf(stderr, "qemu: fatal: "); |
1802 | vfprintf(stderr, fmt, ap); | |
1803 | fprintf(stderr, "\n"); | |
1804 | #ifdef TARGET_I386 | |
7fe48483 FB |
1805 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
1806 | #else | |
1807 | cpu_dump_state(env, stderr, fprintf, 0); | |
7501267e | 1808 | #endif |
93fcfe39 AL |
1809 | if (qemu_log_enabled()) { |
1810 | qemu_log("qemu: fatal: "); | |
1811 | qemu_log_vprintf(fmt, ap2); | |
1812 | qemu_log("\n"); | |
f9373291 | 1813 | #ifdef TARGET_I386 |
93fcfe39 | 1814 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
f9373291 | 1815 | #else |
93fcfe39 | 1816 | log_cpu_state(env, 0); |
f9373291 | 1817 | #endif |
31b1a7b4 | 1818 | qemu_log_flush(); |
93fcfe39 | 1819 | qemu_log_close(); |
924edcae | 1820 | } |
493ae1f0 | 1821 | va_end(ap2); |
f9373291 | 1822 | va_end(ap); |
fd052bf6 RV |
1823 | #if defined(CONFIG_USER_ONLY) |
1824 | { | |
1825 | struct sigaction act; | |
1826 | sigfillset(&act.sa_mask); | |
1827 | act.sa_handler = SIG_DFL; | |
1828 | sigaction(SIGABRT, &act, NULL); | |
1829 | } | |
1830 | #endif | |
7501267e FB |
1831 | abort(); |
1832 | } | |
1833 | ||
c5be9f08 TS |
1834 | CPUState *cpu_copy(CPUState *env) |
1835 | { | |
01ba9816 | 1836 | CPUState *new_env = cpu_init(env->cpu_model_str); |
c5be9f08 TS |
1837 | CPUState *next_cpu = new_env->next_cpu; |
1838 | int cpu_index = new_env->cpu_index; | |
5a38f081 AL |
1839 | #if defined(TARGET_HAS_ICE) |
1840 | CPUBreakpoint *bp; | |
1841 | CPUWatchpoint *wp; | |
1842 | #endif | |
1843 | ||
c5be9f08 | 1844 | memcpy(new_env, env, sizeof(CPUState)); |
5a38f081 AL |
1845 | |
1846 | /* Preserve chaining and index. */ | |
c5be9f08 TS |
1847 | new_env->next_cpu = next_cpu; |
1848 | new_env->cpu_index = cpu_index; | |
5a38f081 AL |
1849 | |
1850 | /* Clone all break/watchpoints. | |
1851 | Note: Once we support ptrace with hw-debug register access, make sure | |
1852 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
72cf2d4f BS |
1853 | QTAILQ_INIT(&env->breakpoints); |
1854 | QTAILQ_INIT(&env->watchpoints); | |
5a38f081 | 1855 | #if defined(TARGET_HAS_ICE) |
72cf2d4f | 1856 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
5a38f081 AL |
1857 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
1858 | } | |
72cf2d4f | 1859 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
5a38f081 AL |
1860 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
1861 | wp->flags, NULL); | |
1862 | } | |
1863 | #endif | |
1864 | ||
c5be9f08 TS |
1865 | return new_env; |
1866 | } | |
1867 | ||
0124311e FB |
1868 | #if !defined(CONFIG_USER_ONLY) |
1869 | ||
5c751e99 EI |
1870 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
1871 | { | |
1872 | unsigned int i; | |
1873 | ||
1874 | /* Discard jump cache entries for any tb which might potentially | |
1875 | overlap the flushed page. */ | |
1876 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
1877 | memset (&env->tb_jmp_cache[i], 0, | |
1878 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1879 | ||
1880 | i = tb_jmp_cache_hash_page(addr); | |
1881 | memset (&env->tb_jmp_cache[i], 0, | |
1882 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); | |
1883 | } | |
1884 | ||
08738984 IK |
1885 | static CPUTLBEntry s_cputlb_empty_entry = { |
1886 | .addr_read = -1, | |
1887 | .addr_write = -1, | |
1888 | .addr_code = -1, | |
1889 | .addend = -1, | |
1890 | }; | |
1891 | ||
ee8b7021 FB |
1892 | /* NOTE: if flush_global is true, also flush global entries (not |
1893 | implemented yet) */ | |
1894 | void tlb_flush(CPUState *env, int flush_global) | |
33417e70 | 1895 | { |
33417e70 | 1896 | int i; |
0124311e | 1897 | |
9fa3e853 FB |
1898 | #if defined(DEBUG_TLB) |
1899 | printf("tlb_flush:\n"); | |
1900 | #endif | |
0124311e FB |
1901 | /* must reset current TB so that interrupts cannot modify the |
1902 | links while we are modifying them */ | |
1903 | env->current_tb = NULL; | |
1904 | ||
33417e70 | 1905 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
cfde4bd9 IY |
1906 | int mmu_idx; |
1907 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
08738984 | 1908 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
cfde4bd9 | 1909 | } |
33417e70 | 1910 | } |
9fa3e853 | 1911 | |
8a40a180 | 1912 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
9fa3e853 | 1913 | |
e3db7226 | 1914 | tlb_flush_count++; |
33417e70 FB |
1915 | } |
1916 | ||
274da6b2 | 1917 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
61382a50 | 1918 | { |
5fafdf24 | 1919 | if (addr == (tlb_entry->addr_read & |
84b7b8e7 | 1920 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1921 | addr == (tlb_entry->addr_write & |
84b7b8e7 | 1922 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
5fafdf24 | 1923 | addr == (tlb_entry->addr_code & |
84b7b8e7 | 1924 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
08738984 | 1925 | *tlb_entry = s_cputlb_empty_entry; |
84b7b8e7 | 1926 | } |
61382a50 FB |
1927 | } |
1928 | ||
2e12669a | 1929 | void tlb_flush_page(CPUState *env, target_ulong addr) |
33417e70 | 1930 | { |
8a40a180 | 1931 | int i; |
cfde4bd9 | 1932 | int mmu_idx; |
0124311e | 1933 | |
9fa3e853 | 1934 | #if defined(DEBUG_TLB) |
108c49b8 | 1935 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
9fa3e853 | 1936 | #endif |
0124311e FB |
1937 | /* must reset current TB so that interrupts cannot modify the |
1938 | links while we are modifying them */ | |
1939 | env->current_tb = NULL; | |
61382a50 FB |
1940 | |
1941 | addr &= TARGET_PAGE_MASK; | |
1942 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | |
cfde4bd9 IY |
1943 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
1944 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); | |
0124311e | 1945 | |
5c751e99 | 1946 | tlb_flush_jmp_cache(env, addr); |
9fa3e853 FB |
1947 | } |
1948 | ||
9fa3e853 FB |
1949 | /* update the TLBs so that writes to code in the virtual page 'addr' |
1950 | can be detected */ | |
c227f099 | 1951 | static void tlb_protect_code(ram_addr_t ram_addr) |
9fa3e853 | 1952 | { |
5fafdf24 | 1953 | cpu_physical_memory_reset_dirty(ram_addr, |
6a00d601 FB |
1954 | ram_addr + TARGET_PAGE_SIZE, |
1955 | CODE_DIRTY_FLAG); | |
9fa3e853 FB |
1956 | } |
1957 | ||
9fa3e853 | 1958 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
3a7d929e | 1959 | tested for self modifying code */ |
c227f099 | 1960 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
3a7d929e | 1961 | target_ulong vaddr) |
9fa3e853 | 1962 | { |
3a7d929e | 1963 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
1ccde1cb FB |
1964 | } |
1965 | ||
5fafdf24 | 1966 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
1ccde1cb FB |
1967 | unsigned long start, unsigned long length) |
1968 | { | |
1969 | unsigned long addr; | |
84b7b8e7 FB |
1970 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
1971 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; | |
1ccde1cb | 1972 | if ((addr - start) < length) { |
0f459d16 | 1973 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
1ccde1cb FB |
1974 | } |
1975 | } | |
1976 | } | |
1977 | ||
5579c7f3 | 1978 | /* Note: start and end must be within the same ram block. */ |
c227f099 | 1979 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
0a962c02 | 1980 | int dirty_flags) |
1ccde1cb FB |
1981 | { |
1982 | CPUState *env; | |
4f2ac237 | 1983 | unsigned long length, start1; |
0a962c02 FB |
1984 | int i, mask, len; |
1985 | uint8_t *p; | |
1ccde1cb FB |
1986 | |
1987 | start &= TARGET_PAGE_MASK; | |
1988 | end = TARGET_PAGE_ALIGN(end); | |
1989 | ||
1990 | length = end - start; | |
1991 | if (length == 0) | |
1992 | return; | |
0a962c02 | 1993 | len = length >> TARGET_PAGE_BITS; |
f23db169 FB |
1994 | mask = ~dirty_flags; |
1995 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); | |
1996 | for(i = 0; i < len; i++) | |
1997 | p[i] &= mask; | |
1998 | ||
1ccde1cb FB |
1999 | /* we modify the TLB cache so that the dirty bit will be set again |
2000 | when accessing the range */ | |
5579c7f3 PB |
2001 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
2002 | /* Chek that we don't span multiple blocks - this breaks the | |
2003 | address comparisons below. */ | |
2004 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 | |
2005 | != (end - 1) - start) { | |
2006 | abort(); | |
2007 | } | |
2008 | ||
6a00d601 | 2009 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
cfde4bd9 IY |
2010 | int mmu_idx; |
2011 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2012 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2013 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], | |
2014 | start1, length); | |
2015 | } | |
6a00d601 | 2016 | } |
1ccde1cb FB |
2017 | } |
2018 | ||
74576198 AL |
2019 | int cpu_physical_memory_set_dirty_tracking(int enable) |
2020 | { | |
f6f3fbca | 2021 | int ret = 0; |
74576198 | 2022 | in_migration = enable; |
f6f3fbca MT |
2023 | ret = cpu_notify_migration_log(!!enable); |
2024 | return ret; | |
74576198 AL |
2025 | } |
2026 | ||
2027 | int cpu_physical_memory_get_dirty_tracking(void) | |
2028 | { | |
2029 | return in_migration; | |
2030 | } | |
2031 | ||
c227f099 AL |
2032 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
2033 | target_phys_addr_t end_addr) | |
2bec46dc | 2034 | { |
7b8f3b78 | 2035 | int ret; |
151f7749 | 2036 | |
f6f3fbca | 2037 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
151f7749 | 2038 | return ret; |
2bec46dc AL |
2039 | } |
2040 | ||
3a7d929e FB |
2041 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
2042 | { | |
c227f099 | 2043 | ram_addr_t ram_addr; |
5579c7f3 | 2044 | void *p; |
3a7d929e | 2045 | |
84b7b8e7 | 2046 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
5579c7f3 PB |
2047 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
2048 | + tlb_entry->addend); | |
2049 | ram_addr = qemu_ram_addr_from_host(p); | |
3a7d929e | 2050 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
0f459d16 | 2051 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
3a7d929e FB |
2052 | } |
2053 | } | |
2054 | } | |
2055 | ||
2056 | /* update the TLB according to the current state of the dirty bits */ | |
2057 | void cpu_tlb_update_dirty(CPUState *env) | |
2058 | { | |
2059 | int i; | |
cfde4bd9 IY |
2060 | int mmu_idx; |
2061 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { | |
2062 | for(i = 0; i < CPU_TLB_SIZE; i++) | |
2063 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); | |
2064 | } | |
3a7d929e FB |
2065 | } |
2066 | ||
0f459d16 | 2067 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
1ccde1cb | 2068 | { |
0f459d16 PB |
2069 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
2070 | tlb_entry->addr_write = vaddr; | |
1ccde1cb FB |
2071 | } |
2072 | ||
0f459d16 PB |
2073 | /* update the TLB corresponding to virtual page vaddr |
2074 | so that it is no longer dirty */ | |
2075 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) | |
1ccde1cb | 2076 | { |
1ccde1cb | 2077 | int i; |
cfde4bd9 | 2078 | int mmu_idx; |
1ccde1cb | 2079 | |
0f459d16 | 2080 | vaddr &= TARGET_PAGE_MASK; |
1ccde1cb | 2081 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
cfde4bd9 IY |
2082 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
2083 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); | |
9fa3e853 FB |
2084 | } |
2085 | ||
59817ccb FB |
2086 | /* add a new TLB entry. At most one entry for a given virtual address |
2087 | is permitted. Return 0 if OK or 2 if the page could not be mapped | |
2088 | (can only happen in non SOFTMMU mode for I/O pages or pages | |
2089 | conflicting with the host address space). */ | |
5fafdf24 | 2090 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
c227f099 | 2091 | target_phys_addr_t paddr, int prot, |
6ebbf390 | 2092 | int mmu_idx, int is_softmmu) |
9fa3e853 | 2093 | { |
92e873b9 | 2094 | PhysPageDesc *p; |
4f2ac237 | 2095 | unsigned long pd; |
9fa3e853 | 2096 | unsigned int index; |
4f2ac237 | 2097 | target_ulong address; |
0f459d16 | 2098 | target_ulong code_address; |
c227f099 | 2099 | target_phys_addr_t addend; |
9fa3e853 | 2100 | int ret; |
84b7b8e7 | 2101 | CPUTLBEntry *te; |
a1d1bb31 | 2102 | CPUWatchpoint *wp; |
c227f099 | 2103 | target_phys_addr_t iotlb; |
9fa3e853 | 2104 | |
92e873b9 | 2105 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
9fa3e853 FB |
2106 | if (!p) { |
2107 | pd = IO_MEM_UNASSIGNED; | |
9fa3e853 FB |
2108 | } else { |
2109 | pd = p->phys_offset; | |
9fa3e853 FB |
2110 | } |
2111 | #if defined(DEBUG_TLB) | |
6ebbf390 JM |
2112 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
2113 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); | |
9fa3e853 FB |
2114 | #endif |
2115 | ||
2116 | ret = 0; | |
0f459d16 PB |
2117 | address = vaddr; |
2118 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { | |
2119 | /* IO memory case (romd handled later) */ | |
2120 | address |= TLB_MMIO; | |
2121 | } | |
5579c7f3 | 2122 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
0f459d16 PB |
2123 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
2124 | /* Normal RAM. */ | |
2125 | iotlb = pd & TARGET_PAGE_MASK; | |
2126 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) | |
2127 | iotlb |= IO_MEM_NOTDIRTY; | |
2128 | else | |
2129 | iotlb |= IO_MEM_ROM; | |
2130 | } else { | |
ccbb4d44 | 2131 | /* IO handlers are currently passed a physical address. |
0f459d16 PB |
2132 | It would be nice to pass an offset from the base address |
2133 | of that region. This would avoid having to special case RAM, | |
2134 | and avoid full address decoding in every device. | |
2135 | We can't use the high bits of pd for this because | |
2136 | IO_MEM_ROMD uses these as a ram address. */ | |
8da3ff18 PB |
2137 | iotlb = (pd & ~TARGET_PAGE_MASK); |
2138 | if (p) { | |
8da3ff18 PB |
2139 | iotlb += p->region_offset; |
2140 | } else { | |
2141 | iotlb += paddr; | |
2142 | } | |
0f459d16 PB |
2143 | } |
2144 | ||
2145 | code_address = address; | |
2146 | /* Make accesses to pages with watchpoints go via the | |
2147 | watchpoint trap routines. */ | |
72cf2d4f | 2148 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
a1d1bb31 | 2149 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
0f459d16 PB |
2150 | iotlb = io_mem_watch + paddr; |
2151 | /* TODO: The memory case can be optimized by not trapping | |
2152 | reads of pages with a write breakpoint. */ | |
2153 | address |= TLB_MMIO; | |
6658ffb8 | 2154 | } |
0f459d16 | 2155 | } |
d79acba4 | 2156 | |
0f459d16 PB |
2157 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
2158 | env->iotlb[mmu_idx][index] = iotlb - vaddr; | |
2159 | te = &env->tlb_table[mmu_idx][index]; | |
2160 | te->addend = addend - vaddr; | |
2161 | if (prot & PAGE_READ) { | |
2162 | te->addr_read = address; | |
2163 | } else { | |
2164 | te->addr_read = -1; | |
2165 | } | |
5c751e99 | 2166 | |
0f459d16 PB |
2167 | if (prot & PAGE_EXEC) { |
2168 | te->addr_code = code_address; | |
2169 | } else { | |
2170 | te->addr_code = -1; | |
2171 | } | |
2172 | if (prot & PAGE_WRITE) { | |
2173 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || | |
2174 | (pd & IO_MEM_ROMD)) { | |
2175 | /* Write access calls the I/O callback. */ | |
2176 | te->addr_write = address | TLB_MMIO; | |
2177 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && | |
2178 | !cpu_physical_memory_is_dirty(pd)) { | |
2179 | te->addr_write = address | TLB_NOTDIRTY; | |
9fa3e853 | 2180 | } else { |
0f459d16 | 2181 | te->addr_write = address; |
9fa3e853 | 2182 | } |
0f459d16 PB |
2183 | } else { |
2184 | te->addr_write = -1; | |
9fa3e853 | 2185 | } |
9fa3e853 FB |
2186 | return ret; |
2187 | } | |
2188 | ||
0124311e FB |
2189 | #else |
2190 | ||
ee8b7021 | 2191 | void tlb_flush(CPUState *env, int flush_global) |
0124311e FB |
2192 | { |
2193 | } | |
2194 | ||
2e12669a | 2195 | void tlb_flush_page(CPUState *env, target_ulong addr) |
0124311e FB |
2196 | { |
2197 | } | |
2198 | ||
edf8e2af MW |
2199 | /* |
2200 | * Walks guest process memory "regions" one by one | |
2201 | * and calls callback function 'fn' for each region. | |
2202 | */ | |
5cd2c5b6 RH |
2203 | |
2204 | struct walk_memory_regions_data | |
2205 | { | |
2206 | walk_memory_regions_fn fn; | |
2207 | void *priv; | |
2208 | unsigned long start; | |
2209 | int prot; | |
2210 | }; | |
2211 | ||
2212 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
2213 | unsigned long end, int new_prot) | |
2214 | { | |
2215 | if (data->start != -1ul) { | |
2216 | int rc = data->fn(data->priv, data->start, end, data->prot); | |
2217 | if (rc != 0) { | |
2218 | return rc; | |
2219 | } | |
2220 | } | |
2221 | ||
2222 | data->start = (new_prot ? end : -1ul); | |
2223 | data->prot = new_prot; | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
2229 | unsigned long base, int level, void **lp) | |
2230 | { | |
2231 | unsigned long pa; | |
2232 | int i, rc; | |
2233 | ||
2234 | if (*lp == NULL) { | |
2235 | return walk_memory_regions_end(data, base, 0); | |
2236 | } | |
2237 | ||
2238 | if (level == 0) { | |
2239 | PageDesc *pd = *lp; | |
2240 | for (i = 0; i < L2_BITS; ++i) { | |
2241 | int prot = pd[i].flags; | |
2242 | ||
2243 | pa = base | (i << TARGET_PAGE_BITS); | |
2244 | if (prot != data->prot) { | |
2245 | rc = walk_memory_regions_end(data, pa, prot); | |
2246 | if (rc != 0) { | |
2247 | return rc; | |
9fa3e853 | 2248 | } |
9fa3e853 | 2249 | } |
5cd2c5b6 RH |
2250 | } |
2251 | } else { | |
2252 | void **pp = *lp; | |
2253 | for (i = 0; i < L2_BITS; ++i) { | |
2254 | pa = base | (i << (TARGET_PAGE_BITS + L2_BITS * level)); | |
2255 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); | |
2256 | if (rc != 0) { | |
2257 | return rc; | |
2258 | } | |
2259 | } | |
2260 | } | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
2265 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
2266 | { | |
2267 | struct walk_memory_regions_data data; | |
2268 | unsigned long i; | |
2269 | ||
2270 | data.fn = fn; | |
2271 | data.priv = priv; | |
2272 | data.start = -1ul; | |
2273 | data.prot = 0; | |
2274 | ||
2275 | for (i = 0; i < V_L1_SIZE; i++) { | |
2276 | int rc = walk_memory_regions_1(&data, i << V_L1_SHIFT, | |
2277 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); | |
2278 | if (rc != 0) { | |
2279 | return rc; | |
9fa3e853 | 2280 | } |
33417e70 | 2281 | } |
5cd2c5b6 RH |
2282 | |
2283 | return walk_memory_regions_end(&data, 0, 0); | |
edf8e2af MW |
2284 | } |
2285 | ||
2286 | static int dump_region(void *priv, unsigned long start, | |
2287 | unsigned long end, unsigned long prot) | |
2288 | { | |
2289 | FILE *f = (FILE *)priv; | |
2290 | ||
2291 | (void) fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", | |
2292 | start, end, end - start, | |
2293 | ((prot & PAGE_READ) ? 'r' : '-'), | |
2294 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
2295 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
2296 | ||
2297 | return (0); | |
2298 | } | |
2299 | ||
2300 | /* dump memory mappings */ | |
2301 | void page_dump(FILE *f) | |
2302 | { | |
2303 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", | |
2304 | "start", "end", "size", "prot"); | |
2305 | walk_memory_regions(f, dump_region); | |
33417e70 FB |
2306 | } |
2307 | ||
53a5960a | 2308 | int page_get_flags(target_ulong address) |
33417e70 | 2309 | { |
9fa3e853 FB |
2310 | PageDesc *p; |
2311 | ||
2312 | p = page_find(address >> TARGET_PAGE_BITS); | |
33417e70 | 2313 | if (!p) |
9fa3e853 FB |
2314 | return 0; |
2315 | return p->flags; | |
2316 | } | |
2317 | ||
376a7909 RH |
2318 | /* Modify the flags of a page and invalidate the code if necessary. |
2319 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
2320 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
53a5960a | 2321 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
9fa3e853 | 2322 | { |
376a7909 RH |
2323 | target_ulong addr, len; |
2324 | ||
2325 | /* This function should never be called with addresses outside the | |
2326 | guest address space. If this assert fires, it probably indicates | |
2327 | a missing call to h2g_valid. */ | |
2328 | #if HOST_LONG_BITS > L1_MAP_ADDR_SPACE_BITS | |
2329 | assert(end < (1ul << L1_MAP_ADDR_SPACE_BITS)); | |
2330 | #endif | |
2331 | assert(start < end); | |
9fa3e853 FB |
2332 | |
2333 | start = start & TARGET_PAGE_MASK; | |
2334 | end = TARGET_PAGE_ALIGN(end); | |
376a7909 RH |
2335 | |
2336 | if (flags & PAGE_WRITE) { | |
9fa3e853 | 2337 | flags |= PAGE_WRITE_ORG; |
376a7909 RH |
2338 | } |
2339 | ||
2340 | for (addr = start, len = end - start; | |
2341 | len != 0; | |
2342 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2343 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2344 | ||
2345 | /* If the write protection bit is set, then we invalidate | |
2346 | the code inside. */ | |
5fafdf24 | 2347 | if (!(p->flags & PAGE_WRITE) && |
9fa3e853 FB |
2348 | (flags & PAGE_WRITE) && |
2349 | p->first_tb) { | |
d720b93d | 2350 | tb_invalidate_phys_page(addr, 0, NULL); |
9fa3e853 FB |
2351 | } |
2352 | p->flags = flags; | |
2353 | } | |
33417e70 FB |
2354 | } |
2355 | ||
3d97b40b TS |
2356 | int page_check_range(target_ulong start, target_ulong len, int flags) |
2357 | { | |
2358 | PageDesc *p; | |
2359 | target_ulong end; | |
2360 | target_ulong addr; | |
2361 | ||
376a7909 RH |
2362 | /* This function should never be called with addresses outside the |
2363 | guest address space. If this assert fires, it probably indicates | |
2364 | a missing call to h2g_valid. */ | |
2365 | #if HOST_LONG_BITS > L1_MAP_ADDR_SPACE_BITS | |
2366 | assert(start < (1ul << L1_MAP_ADDR_SPACE_BITS)); | |
2367 | #endif | |
2368 | ||
2369 | if (start + len - 1 < start) { | |
2370 | /* We've wrapped around. */ | |
55f280c9 | 2371 | return -1; |
376a7909 | 2372 | } |
55f280c9 | 2373 | |
3d97b40b TS |
2374 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
2375 | start = start & TARGET_PAGE_MASK; | |
2376 | ||
376a7909 RH |
2377 | for (addr = start, len = end - start; |
2378 | len != 0; | |
2379 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
3d97b40b TS |
2380 | p = page_find(addr >> TARGET_PAGE_BITS); |
2381 | if( !p ) | |
2382 | return -1; | |
2383 | if( !(p->flags & PAGE_VALID) ) | |
2384 | return -1; | |
2385 | ||
dae3270c | 2386 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
3d97b40b | 2387 | return -1; |
dae3270c FB |
2388 | if (flags & PAGE_WRITE) { |
2389 | if (!(p->flags & PAGE_WRITE_ORG)) | |
2390 | return -1; | |
2391 | /* unprotect the page if it was put read-only because it | |
2392 | contains translated code */ | |
2393 | if (!(p->flags & PAGE_WRITE)) { | |
2394 | if (!page_unprotect(addr, 0, NULL)) | |
2395 | return -1; | |
2396 | } | |
2397 | return 0; | |
2398 | } | |
3d97b40b TS |
2399 | } |
2400 | return 0; | |
2401 | } | |
2402 | ||
9fa3e853 | 2403 | /* called from signal handler: invalidate the code and unprotect the |
ccbb4d44 | 2404 | page. Return TRUE if the fault was successfully handled. */ |
53a5960a | 2405 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
9fa3e853 FB |
2406 | { |
2407 | unsigned int page_index, prot, pindex; | |
2408 | PageDesc *p, *p1; | |
53a5960a | 2409 | target_ulong host_start, host_end, addr; |
9fa3e853 | 2410 | |
c8a706fe PB |
2411 | /* Technically this isn't safe inside a signal handler. However we |
2412 | know this only ever happens in a synchronous SEGV handler, so in | |
2413 | practice it seems to be ok. */ | |
2414 | mmap_lock(); | |
2415 | ||
83fb7adf | 2416 | host_start = address & qemu_host_page_mask; |
9fa3e853 FB |
2417 | page_index = host_start >> TARGET_PAGE_BITS; |
2418 | p1 = page_find(page_index); | |
c8a706fe PB |
2419 | if (!p1) { |
2420 | mmap_unlock(); | |
9fa3e853 | 2421 | return 0; |
c8a706fe | 2422 | } |
83fb7adf | 2423 | host_end = host_start + qemu_host_page_size; |
9fa3e853 FB |
2424 | p = p1; |
2425 | prot = 0; | |
2426 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { | |
2427 | prot |= p->flags; | |
2428 | p++; | |
2429 | } | |
2430 | /* if the page was really writable, then we change its | |
2431 | protection back to writable */ | |
2432 | if (prot & PAGE_WRITE_ORG) { | |
2433 | pindex = (address - host_start) >> TARGET_PAGE_BITS; | |
2434 | if (!(p1[pindex].flags & PAGE_WRITE)) { | |
5fafdf24 | 2435 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
9fa3e853 FB |
2436 | (prot & PAGE_BITS) | PAGE_WRITE); |
2437 | p1[pindex].flags |= PAGE_WRITE; | |
2438 | /* and since the content will be modified, we must invalidate | |
2439 | the corresponding translated code. */ | |
d720b93d | 2440 | tb_invalidate_phys_page(address, pc, puc); |
9fa3e853 FB |
2441 | #ifdef DEBUG_TB_CHECK |
2442 | tb_invalidate_check(address); | |
2443 | #endif | |
c8a706fe | 2444 | mmap_unlock(); |
9fa3e853 FB |
2445 | return 1; |
2446 | } | |
2447 | } | |
c8a706fe | 2448 | mmap_unlock(); |
9fa3e853 FB |
2449 | return 0; |
2450 | } | |
2451 | ||
6a00d601 FB |
2452 | static inline void tlb_set_dirty(CPUState *env, |
2453 | unsigned long addr, target_ulong vaddr) | |
1ccde1cb FB |
2454 | { |
2455 | } | |
9fa3e853 FB |
2456 | #endif /* defined(CONFIG_USER_ONLY) */ |
2457 | ||
e2eef170 | 2458 | #if !defined(CONFIG_USER_ONLY) |
8da3ff18 | 2459 | |
c04b2b78 PB |
2460 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
2461 | typedef struct subpage_t { | |
2462 | target_phys_addr_t base; | |
2463 | CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4]; | |
2464 | CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4]; | |
2465 | void *opaque[TARGET_PAGE_SIZE][2][4]; | |
2466 | ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4]; | |
2467 | } subpage_t; | |
2468 | ||
c227f099 AL |
2469 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
2470 | ram_addr_t memory, ram_addr_t region_offset); | |
2471 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, | |
2472 | ram_addr_t orig_memory, ram_addr_t region_offset); | |
db7b5426 BS |
2473 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
2474 | need_subpage) \ | |
2475 | do { \ | |
2476 | if (addr > start_addr) \ | |
2477 | start_addr2 = 0; \ | |
2478 | else { \ | |
2479 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ | |
2480 | if (start_addr2 > 0) \ | |
2481 | need_subpage = 1; \ | |
2482 | } \ | |
2483 | \ | |
49e9fba2 | 2484 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
db7b5426 BS |
2485 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
2486 | else { \ | |
2487 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ | |
2488 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ | |
2489 | need_subpage = 1; \ | |
2490 | } \ | |
2491 | } while (0) | |
2492 | ||
8f2498f9 MT |
2493 | /* register physical memory. |
2494 | For RAM, 'size' must be a multiple of the target page size. | |
2495 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an | |
8da3ff18 PB |
2496 | io memory page. The address used when calling the IO function is |
2497 | the offset from the start of the region, plus region_offset. Both | |
ccbb4d44 | 2498 | start_addr and region_offset are rounded down to a page boundary |
8da3ff18 PB |
2499 | before calculating this offset. This should not be a problem unless |
2500 | the low bits of start_addr and region_offset differ. */ | |
c227f099 AL |
2501 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
2502 | ram_addr_t size, | |
2503 | ram_addr_t phys_offset, | |
2504 | ram_addr_t region_offset) | |
33417e70 | 2505 | { |
c227f099 | 2506 | target_phys_addr_t addr, end_addr; |
92e873b9 | 2507 | PhysPageDesc *p; |
9d42037b | 2508 | CPUState *env; |
c227f099 | 2509 | ram_addr_t orig_size = size; |
db7b5426 | 2510 | void *subpage; |
33417e70 | 2511 | |
f6f3fbca MT |
2512 | cpu_notify_set_memory(start_addr, size, phys_offset); |
2513 | ||
67c4d23c PB |
2514 | if (phys_offset == IO_MEM_UNASSIGNED) { |
2515 | region_offset = start_addr; | |
2516 | } | |
8da3ff18 | 2517 | region_offset &= TARGET_PAGE_MASK; |
5fd386f6 | 2518 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
c227f099 | 2519 | end_addr = start_addr + (target_phys_addr_t)size; |
49e9fba2 | 2520 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
db7b5426 BS |
2521 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
2522 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { | |
c227f099 AL |
2523 | ram_addr_t orig_memory = p->phys_offset; |
2524 | target_phys_addr_t start_addr2, end_addr2; | |
db7b5426 BS |
2525 | int need_subpage = 0; |
2526 | ||
2527 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, | |
2528 | need_subpage); | |
4254fab8 | 2529 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 BS |
2530 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
2531 | subpage = subpage_init((addr & TARGET_PAGE_MASK), | |
8da3ff18 PB |
2532 | &p->phys_offset, orig_memory, |
2533 | p->region_offset); | |
db7b5426 BS |
2534 | } else { |
2535 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) | |
2536 | >> IO_MEM_SHIFT]; | |
2537 | } | |
8da3ff18 PB |
2538 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
2539 | region_offset); | |
2540 | p->region_offset = 0; | |
db7b5426 BS |
2541 | } else { |
2542 | p->phys_offset = phys_offset; | |
2543 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || | |
2544 | (phys_offset & IO_MEM_ROMD)) | |
2545 | phys_offset += TARGET_PAGE_SIZE; | |
2546 | } | |
2547 | } else { | |
2548 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2549 | p->phys_offset = phys_offset; | |
8da3ff18 | 2550 | p->region_offset = region_offset; |
db7b5426 | 2551 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
8da3ff18 | 2552 | (phys_offset & IO_MEM_ROMD)) { |
db7b5426 | 2553 | phys_offset += TARGET_PAGE_SIZE; |
0e8f0967 | 2554 | } else { |
c227f099 | 2555 | target_phys_addr_t start_addr2, end_addr2; |
db7b5426 BS |
2556 | int need_subpage = 0; |
2557 | ||
2558 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, | |
2559 | end_addr2, need_subpage); | |
2560 | ||
4254fab8 | 2561 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
db7b5426 | 2562 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
8da3ff18 | 2563 | &p->phys_offset, IO_MEM_UNASSIGNED, |
67c4d23c | 2564 | addr & TARGET_PAGE_MASK); |
db7b5426 | 2565 | subpage_register(subpage, start_addr2, end_addr2, |
8da3ff18 PB |
2566 | phys_offset, region_offset); |
2567 | p->region_offset = 0; | |
db7b5426 BS |
2568 | } |
2569 | } | |
2570 | } | |
8da3ff18 | 2571 | region_offset += TARGET_PAGE_SIZE; |
33417e70 | 2572 | } |
3b46e624 | 2573 | |
9d42037b FB |
2574 | /* since each CPU stores ram addresses in its TLB cache, we must |
2575 | reset the modified entries */ | |
2576 | /* XXX: slow ! */ | |
2577 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
2578 | tlb_flush(env, 1); | |
2579 | } | |
33417e70 FB |
2580 | } |
2581 | ||
ba863458 | 2582 | /* XXX: temporary until new memory mapping API */ |
c227f099 | 2583 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
ba863458 FB |
2584 | { |
2585 | PhysPageDesc *p; | |
2586 | ||
2587 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
2588 | if (!p) | |
2589 | return IO_MEM_UNASSIGNED; | |
2590 | return p->phys_offset; | |
2591 | } | |
2592 | ||
c227f099 | 2593 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2594 | { |
2595 | if (kvm_enabled()) | |
2596 | kvm_coalesce_mmio_region(addr, size); | |
2597 | } | |
2598 | ||
c227f099 | 2599 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
f65ed4c1 AL |
2600 | { |
2601 | if (kvm_enabled()) | |
2602 | kvm_uncoalesce_mmio_region(addr, size); | |
2603 | } | |
2604 | ||
62a2744c SY |
2605 | void qemu_flush_coalesced_mmio_buffer(void) |
2606 | { | |
2607 | if (kvm_enabled()) | |
2608 | kvm_flush_coalesced_mmio_buffer(); | |
2609 | } | |
2610 | ||
c902760f MT |
2611 | #if defined(__linux__) && !defined(TARGET_S390X) |
2612 | ||
2613 | #include <sys/vfs.h> | |
2614 | ||
2615 | #define HUGETLBFS_MAGIC 0x958458f6 | |
2616 | ||
2617 | static long gethugepagesize(const char *path) | |
2618 | { | |
2619 | struct statfs fs; | |
2620 | int ret; | |
2621 | ||
2622 | do { | |
2623 | ret = statfs(path, &fs); | |
2624 | } while (ret != 0 && errno == EINTR); | |
2625 | ||
2626 | if (ret != 0) { | |
2627 | perror("statfs"); | |
2628 | return 0; | |
2629 | } | |
2630 | ||
2631 | if (fs.f_type != HUGETLBFS_MAGIC) | |
2632 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); | |
2633 | ||
2634 | return fs.f_bsize; | |
2635 | } | |
2636 | ||
2637 | static void *file_ram_alloc(ram_addr_t memory, const char *path) | |
2638 | { | |
2639 | char *filename; | |
2640 | void *area; | |
2641 | int fd; | |
2642 | #ifdef MAP_POPULATE | |
2643 | int flags; | |
2644 | #endif | |
2645 | unsigned long hpagesize; | |
2646 | ||
2647 | hpagesize = gethugepagesize(path); | |
2648 | if (!hpagesize) { | |
2649 | return NULL; | |
2650 | } | |
2651 | ||
2652 | if (memory < hpagesize) { | |
2653 | return NULL; | |
2654 | } | |
2655 | ||
2656 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
2657 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); | |
2658 | return NULL; | |
2659 | } | |
2660 | ||
2661 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { | |
2662 | return NULL; | |
2663 | } | |
2664 | ||
2665 | fd = mkstemp(filename); | |
2666 | if (fd < 0) { | |
2667 | perror("mkstemp"); | |
2668 | free(filename); | |
2669 | return NULL; | |
2670 | } | |
2671 | unlink(filename); | |
2672 | free(filename); | |
2673 | ||
2674 | memory = (memory+hpagesize-1) & ~(hpagesize-1); | |
2675 | ||
2676 | /* | |
2677 | * ftruncate is not supported by hugetlbfs in older | |
2678 | * hosts, so don't bother bailing out on errors. | |
2679 | * If anything goes wrong with it under other filesystems, | |
2680 | * mmap will fail. | |
2681 | */ | |
2682 | if (ftruncate(fd, memory)) | |
2683 | perror("ftruncate"); | |
2684 | ||
2685 | #ifdef MAP_POPULATE | |
2686 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case | |
2687 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED | |
2688 | * to sidestep this quirk. | |
2689 | */ | |
2690 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; | |
2691 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); | |
2692 | #else | |
2693 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); | |
2694 | #endif | |
2695 | if (area == MAP_FAILED) { | |
2696 | perror("file_ram_alloc: can't mmap RAM pages"); | |
2697 | close(fd); | |
2698 | return (NULL); | |
2699 | } | |
2700 | return area; | |
2701 | } | |
2702 | #endif | |
2703 | ||
c227f099 | 2704 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
94a6b54f PB |
2705 | { |
2706 | RAMBlock *new_block; | |
2707 | ||
94a6b54f PB |
2708 | size = TARGET_PAGE_ALIGN(size); |
2709 | new_block = qemu_malloc(sizeof(*new_block)); | |
2710 | ||
c902760f MT |
2711 | if (mem_path) { |
2712 | #if defined (__linux__) && !defined(TARGET_S390X) | |
2713 | new_block->host = file_ram_alloc(size, mem_path); | |
2714 | if (!new_block->host) | |
2715 | exit(1); | |
2716 | #else | |
2717 | fprintf(stderr, "-mem-path option unsupported\n"); | |
2718 | exit(1); | |
2719 | #endif | |
2720 | } else { | |
6b02494d | 2721 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
c902760f MT |
2722 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ |
2723 | new_block->host = mmap((void*)0x1000000, size, | |
2724 | PROT_EXEC|PROT_READ|PROT_WRITE, | |
2725 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); | |
6b02494d | 2726 | #else |
c902760f | 2727 | new_block->host = qemu_vmalloc(size); |
6b02494d | 2728 | #endif |
ccb167e9 | 2729 | #ifdef MADV_MERGEABLE |
c902760f | 2730 | madvise(new_block->host, size, MADV_MERGEABLE); |
ccb167e9 | 2731 | #endif |
c902760f | 2732 | } |
94a6b54f PB |
2733 | new_block->offset = last_ram_offset; |
2734 | new_block->length = size; | |
2735 | ||
2736 | new_block->next = ram_blocks; | |
2737 | ram_blocks = new_block; | |
2738 | ||
2739 | phys_ram_dirty = qemu_realloc(phys_ram_dirty, | |
2740 | (last_ram_offset + size) >> TARGET_PAGE_BITS); | |
2741 | memset(phys_ram_dirty + (last_ram_offset >> TARGET_PAGE_BITS), | |
2742 | 0xff, size >> TARGET_PAGE_BITS); | |
2743 | ||
2744 | last_ram_offset += size; | |
2745 | ||
6f0437e8 JK |
2746 | if (kvm_enabled()) |
2747 | kvm_setup_guest_memory(new_block->host, size); | |
2748 | ||
94a6b54f PB |
2749 | return new_block->offset; |
2750 | } | |
e9a1ab19 | 2751 | |
c227f099 | 2752 | void qemu_ram_free(ram_addr_t addr) |
e9a1ab19 | 2753 | { |
94a6b54f | 2754 | /* TODO: implement this. */ |
e9a1ab19 FB |
2755 | } |
2756 | ||
dc828ca1 | 2757 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
5579c7f3 PB |
2758 | With the exception of the softmmu code in this file, this should |
2759 | only be used for local memory (e.g. video ram) that the device owns, | |
2760 | and knows it isn't going to access beyond the end of the block. | |
2761 | ||
2762 | It should not be used for general purpose DMA. | |
2763 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. | |
2764 | */ | |
c227f099 | 2765 | void *qemu_get_ram_ptr(ram_addr_t addr) |
dc828ca1 | 2766 | { |
94a6b54f PB |
2767 | RAMBlock *prev; |
2768 | RAMBlock **prevp; | |
2769 | RAMBlock *block; | |
2770 | ||
94a6b54f PB |
2771 | prev = NULL; |
2772 | prevp = &ram_blocks; | |
2773 | block = ram_blocks; | |
2774 | while (block && (block->offset > addr | |
2775 | || block->offset + block->length <= addr)) { | |
2776 | if (prev) | |
2777 | prevp = &prev->next; | |
2778 | prev = block; | |
2779 | block = block->next; | |
2780 | } | |
2781 | if (!block) { | |
2782 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
2783 | abort(); | |
2784 | } | |
2785 | /* Move this entry to to start of the list. */ | |
2786 | if (prev) { | |
2787 | prev->next = block->next; | |
2788 | block->next = *prevp; | |
2789 | *prevp = block; | |
2790 | } | |
2791 | return block->host + (addr - block->offset); | |
dc828ca1 PB |
2792 | } |
2793 | ||
5579c7f3 PB |
2794 | /* Some of the softmmu routines need to translate from a host pointer |
2795 | (typically a TLB entry) back to a ram offset. */ | |
c227f099 | 2796 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
5579c7f3 | 2797 | { |
94a6b54f | 2798 | RAMBlock *prev; |
94a6b54f PB |
2799 | RAMBlock *block; |
2800 | uint8_t *host = ptr; | |
2801 | ||
94a6b54f | 2802 | prev = NULL; |
94a6b54f PB |
2803 | block = ram_blocks; |
2804 | while (block && (block->host > host | |
2805 | || block->host + block->length <= host)) { | |
94a6b54f PB |
2806 | prev = block; |
2807 | block = block->next; | |
2808 | } | |
2809 | if (!block) { | |
2810 | fprintf(stderr, "Bad ram pointer %p\n", ptr); | |
2811 | abort(); | |
2812 | } | |
2813 | return block->offset + (host - block->host); | |
5579c7f3 PB |
2814 | } |
2815 | ||
c227f099 | 2816 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
33417e70 | 2817 | { |
67d3b957 | 2818 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2819 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
b4f0a316 | 2820 | #endif |
faed1c2a | 2821 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2822 | do_unassigned_access(addr, 0, 0, 0, 1); |
2823 | #endif | |
2824 | return 0; | |
2825 | } | |
2826 | ||
c227f099 | 2827 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2828 | { |
2829 | #ifdef DEBUG_UNASSIGNED | |
2830 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2831 | #endif | |
faed1c2a | 2832 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2833 | do_unassigned_access(addr, 0, 0, 0, 2); |
2834 | #endif | |
2835 | return 0; | |
2836 | } | |
2837 | ||
c227f099 | 2838 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
e18231a3 BS |
2839 | { |
2840 | #ifdef DEBUG_UNASSIGNED | |
2841 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); | |
2842 | #endif | |
faed1c2a | 2843 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2844 | do_unassigned_access(addr, 0, 0, 0, 4); |
67d3b957 | 2845 | #endif |
33417e70 FB |
2846 | return 0; |
2847 | } | |
2848 | ||
c227f099 | 2849 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
33417e70 | 2850 | { |
67d3b957 | 2851 | #ifdef DEBUG_UNASSIGNED |
ab3d1727 | 2852 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
67d3b957 | 2853 | #endif |
faed1c2a | 2854 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2855 | do_unassigned_access(addr, 1, 0, 0, 1); |
2856 | #endif | |
2857 | } | |
2858 | ||
c227f099 | 2859 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2860 | { |
2861 | #ifdef DEBUG_UNASSIGNED | |
2862 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2863 | #endif | |
faed1c2a | 2864 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 BS |
2865 | do_unassigned_access(addr, 1, 0, 0, 2); |
2866 | #endif | |
2867 | } | |
2868 | ||
c227f099 | 2869 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
e18231a3 BS |
2870 | { |
2871 | #ifdef DEBUG_UNASSIGNED | |
2872 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); | |
2873 | #endif | |
faed1c2a | 2874 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
e18231a3 | 2875 | do_unassigned_access(addr, 1, 0, 0, 4); |
b4f0a316 | 2876 | #endif |
33417e70 FB |
2877 | } |
2878 | ||
d60efc6b | 2879 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
33417e70 | 2880 | unassigned_mem_readb, |
e18231a3 BS |
2881 | unassigned_mem_readw, |
2882 | unassigned_mem_readl, | |
33417e70 FB |
2883 | }; |
2884 | ||
d60efc6b | 2885 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
33417e70 | 2886 | unassigned_mem_writeb, |
e18231a3 BS |
2887 | unassigned_mem_writew, |
2888 | unassigned_mem_writel, | |
33417e70 FB |
2889 | }; |
2890 | ||
c227f099 | 2891 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2892 | uint32_t val) |
9fa3e853 | 2893 | { |
3a7d929e | 2894 | int dirty_flags; |
3a7d929e FB |
2895 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2896 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2897 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2898 | tb_invalidate_phys_page_fast(ram_addr, 1); |
2899 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2900 | #endif |
3a7d929e | 2901 | } |
5579c7f3 | 2902 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2903 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2904 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2905 | /* we remove the notdirty callback only if the code has been | |
2906 | flushed */ | |
2907 | if (dirty_flags == 0xff) | |
2e70f6ef | 2908 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2909 | } |
2910 | ||
c227f099 | 2911 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2912 | uint32_t val) |
9fa3e853 | 2913 | { |
3a7d929e | 2914 | int dirty_flags; |
3a7d929e FB |
2915 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2916 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2917 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2918 | tb_invalidate_phys_page_fast(ram_addr, 2); |
2919 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2920 | #endif |
3a7d929e | 2921 | } |
5579c7f3 | 2922 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2923 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2924 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2925 | /* we remove the notdirty callback only if the code has been | |
2926 | flushed */ | |
2927 | if (dirty_flags == 0xff) | |
2e70f6ef | 2928 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2929 | } |
2930 | ||
c227f099 | 2931 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
0f459d16 | 2932 | uint32_t val) |
9fa3e853 | 2933 | { |
3a7d929e | 2934 | int dirty_flags; |
3a7d929e FB |
2935 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
2936 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { | |
9fa3e853 | 2937 | #if !defined(CONFIG_USER_ONLY) |
3a7d929e FB |
2938 | tb_invalidate_phys_page_fast(ram_addr, 4); |
2939 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; | |
9fa3e853 | 2940 | #endif |
3a7d929e | 2941 | } |
5579c7f3 | 2942 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
f23db169 FB |
2943 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
2944 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; | |
2945 | /* we remove the notdirty callback only if the code has been | |
2946 | flushed */ | |
2947 | if (dirty_flags == 0xff) | |
2e70f6ef | 2948 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
9fa3e853 FB |
2949 | } |
2950 | ||
d60efc6b | 2951 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
9fa3e853 FB |
2952 | NULL, /* never used */ |
2953 | NULL, /* never used */ | |
2954 | NULL, /* never used */ | |
2955 | }; | |
2956 | ||
d60efc6b | 2957 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
1ccde1cb FB |
2958 | notdirty_mem_writeb, |
2959 | notdirty_mem_writew, | |
2960 | notdirty_mem_writel, | |
2961 | }; | |
2962 | ||
0f459d16 | 2963 | /* Generate a debug exception if a watchpoint has been hit. */ |
b4051334 | 2964 | static void check_watchpoint(int offset, int len_mask, int flags) |
0f459d16 PB |
2965 | { |
2966 | CPUState *env = cpu_single_env; | |
06d55cc1 AL |
2967 | target_ulong pc, cs_base; |
2968 | TranslationBlock *tb; | |
0f459d16 | 2969 | target_ulong vaddr; |
a1d1bb31 | 2970 | CPUWatchpoint *wp; |
06d55cc1 | 2971 | int cpu_flags; |
0f459d16 | 2972 | |
06d55cc1 AL |
2973 | if (env->watchpoint_hit) { |
2974 | /* We re-entered the check after replacing the TB. Now raise | |
2975 | * the debug interrupt so that is will trigger after the | |
2976 | * current instruction. */ | |
2977 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); | |
2978 | return; | |
2979 | } | |
2e70f6ef | 2980 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
72cf2d4f | 2981 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
b4051334 AL |
2982 | if ((vaddr == (wp->vaddr & len_mask) || |
2983 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { | |
6e140f28 AL |
2984 | wp->flags |= BP_WATCHPOINT_HIT; |
2985 | if (!env->watchpoint_hit) { | |
2986 | env->watchpoint_hit = wp; | |
2987 | tb = tb_find_pc(env->mem_io_pc); | |
2988 | if (!tb) { | |
2989 | cpu_abort(env, "check_watchpoint: could not find TB for " | |
2990 | "pc=%p", (void *)env->mem_io_pc); | |
2991 | } | |
2992 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); | |
2993 | tb_phys_invalidate(tb, -1); | |
2994 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
2995 | env->exception_index = EXCP_DEBUG; | |
2996 | } else { | |
2997 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
2998 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); | |
2999 | } | |
3000 | cpu_resume_from_signal(env, NULL); | |
06d55cc1 | 3001 | } |
6e140f28 AL |
3002 | } else { |
3003 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
0f459d16 PB |
3004 | } |
3005 | } | |
3006 | } | |
3007 | ||
6658ffb8 PB |
3008 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
3009 | so these check for a hit then pass through to the normal out-of-line | |
3010 | phys routines. */ | |
c227f099 | 3011 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3012 | { |
b4051334 | 3013 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
6658ffb8 PB |
3014 | return ldub_phys(addr); |
3015 | } | |
3016 | ||
c227f099 | 3017 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3018 | { |
b4051334 | 3019 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
6658ffb8 PB |
3020 | return lduw_phys(addr); |
3021 | } | |
3022 | ||
c227f099 | 3023 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
6658ffb8 | 3024 | { |
b4051334 | 3025 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
6658ffb8 PB |
3026 | return ldl_phys(addr); |
3027 | } | |
3028 | ||
c227f099 | 3029 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3030 | uint32_t val) |
3031 | { | |
b4051334 | 3032 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
6658ffb8 PB |
3033 | stb_phys(addr, val); |
3034 | } | |
3035 | ||
c227f099 | 3036 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3037 | uint32_t val) |
3038 | { | |
b4051334 | 3039 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
6658ffb8 PB |
3040 | stw_phys(addr, val); |
3041 | } | |
3042 | ||
c227f099 | 3043 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
6658ffb8 PB |
3044 | uint32_t val) |
3045 | { | |
b4051334 | 3046 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
6658ffb8 PB |
3047 | stl_phys(addr, val); |
3048 | } | |
3049 | ||
d60efc6b | 3050 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
6658ffb8 PB |
3051 | watch_mem_readb, |
3052 | watch_mem_readw, | |
3053 | watch_mem_readl, | |
3054 | }; | |
3055 | ||
d60efc6b | 3056 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
6658ffb8 PB |
3057 | watch_mem_writeb, |
3058 | watch_mem_writew, | |
3059 | watch_mem_writel, | |
3060 | }; | |
6658ffb8 | 3061 | |
c227f099 | 3062 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
db7b5426 BS |
3063 | unsigned int len) |
3064 | { | |
db7b5426 BS |
3065 | uint32_t ret; |
3066 | unsigned int idx; | |
3067 | ||
8da3ff18 | 3068 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
3069 | #if defined(DEBUG_SUBPAGE) |
3070 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, | |
3071 | mmio, len, addr, idx); | |
3072 | #endif | |
8da3ff18 PB |
3073 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], |
3074 | addr + mmio->region_offset[idx][0][len]); | |
db7b5426 BS |
3075 | |
3076 | return ret; | |
3077 | } | |
3078 | ||
c227f099 | 3079 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
db7b5426 BS |
3080 | uint32_t value, unsigned int len) |
3081 | { | |
db7b5426 BS |
3082 | unsigned int idx; |
3083 | ||
8da3ff18 | 3084 | idx = SUBPAGE_IDX(addr); |
db7b5426 BS |
3085 | #if defined(DEBUG_SUBPAGE) |
3086 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, | |
3087 | mmio, len, addr, idx, value); | |
3088 | #endif | |
8da3ff18 PB |
3089 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], |
3090 | addr + mmio->region_offset[idx][1][len], | |
3091 | value); | |
db7b5426 BS |
3092 | } |
3093 | ||
c227f099 | 3094 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
3095 | { |
3096 | #if defined(DEBUG_SUBPAGE) | |
3097 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
3098 | #endif | |
3099 | ||
3100 | return subpage_readlen(opaque, addr, 0); | |
3101 | } | |
3102 | ||
c227f099 | 3103 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3104 | uint32_t value) |
3105 | { | |
3106 | #if defined(DEBUG_SUBPAGE) | |
3107 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
3108 | #endif | |
3109 | subpage_writelen(opaque, addr, value, 0); | |
3110 | } | |
3111 | ||
c227f099 | 3112 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
3113 | { |
3114 | #if defined(DEBUG_SUBPAGE) | |
3115 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
3116 | #endif | |
3117 | ||
3118 | return subpage_readlen(opaque, addr, 1); | |
3119 | } | |
3120 | ||
c227f099 | 3121 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
db7b5426 BS |
3122 | uint32_t value) |
3123 | { | |
3124 | #if defined(DEBUG_SUBPAGE) | |
3125 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
3126 | #endif | |
3127 | subpage_writelen(opaque, addr, value, 1); | |
3128 | } | |
3129 | ||
c227f099 | 3130 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
db7b5426 BS |
3131 | { |
3132 | #if defined(DEBUG_SUBPAGE) | |
3133 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); | |
3134 | #endif | |
3135 | ||
3136 | return subpage_readlen(opaque, addr, 2); | |
3137 | } | |
3138 | ||
3139 | static void subpage_writel (void *opaque, | |
c227f099 | 3140 | target_phys_addr_t addr, uint32_t value) |
db7b5426 BS |
3141 | { |
3142 | #if defined(DEBUG_SUBPAGE) | |
3143 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); | |
3144 | #endif | |
3145 | subpage_writelen(opaque, addr, value, 2); | |
3146 | } | |
3147 | ||
d60efc6b | 3148 | static CPUReadMemoryFunc * const subpage_read[] = { |
db7b5426 BS |
3149 | &subpage_readb, |
3150 | &subpage_readw, | |
3151 | &subpage_readl, | |
3152 | }; | |
3153 | ||
d60efc6b | 3154 | static CPUWriteMemoryFunc * const subpage_write[] = { |
db7b5426 BS |
3155 | &subpage_writeb, |
3156 | &subpage_writew, | |
3157 | &subpage_writel, | |
3158 | }; | |
3159 | ||
c227f099 AL |
3160 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
3161 | ram_addr_t memory, ram_addr_t region_offset) | |
db7b5426 BS |
3162 | { |
3163 | int idx, eidx; | |
4254fab8 | 3164 | unsigned int i; |
db7b5426 BS |
3165 | |
3166 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
3167 | return -1; | |
3168 | idx = SUBPAGE_IDX(start); | |
3169 | eidx = SUBPAGE_IDX(end); | |
3170 | #if defined(DEBUG_SUBPAGE) | |
0bf9e31a | 3171 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
db7b5426 BS |
3172 | mmio, start, end, idx, eidx, memory); |
3173 | #endif | |
3174 | memory >>= IO_MEM_SHIFT; | |
3175 | for (; idx <= eidx; idx++) { | |
4254fab8 | 3176 | for (i = 0; i < 4; i++) { |
3ee89922 BS |
3177 | if (io_mem_read[memory][i]) { |
3178 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; | |
3179 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; | |
8da3ff18 | 3180 | mmio->region_offset[idx][0][i] = region_offset; |
3ee89922 BS |
3181 | } |
3182 | if (io_mem_write[memory][i]) { | |
3183 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; | |
3184 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; | |
8da3ff18 | 3185 | mmio->region_offset[idx][1][i] = region_offset; |
3ee89922 | 3186 | } |
4254fab8 | 3187 | } |
db7b5426 BS |
3188 | } |
3189 | ||
3190 | return 0; | |
3191 | } | |
3192 | ||
c227f099 AL |
3193 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
3194 | ram_addr_t orig_memory, ram_addr_t region_offset) | |
db7b5426 | 3195 | { |
c227f099 | 3196 | subpage_t *mmio; |
db7b5426 BS |
3197 | int subpage_memory; |
3198 | ||
c227f099 | 3199 | mmio = qemu_mallocz(sizeof(subpage_t)); |
1eec614b AL |
3200 | |
3201 | mmio->base = base; | |
1eed09cb | 3202 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
db7b5426 | 3203 | #if defined(DEBUG_SUBPAGE) |
1eec614b AL |
3204 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
3205 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); | |
db7b5426 | 3206 | #endif |
1eec614b AL |
3207 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
3208 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory, | |
8da3ff18 | 3209 | region_offset); |
db7b5426 BS |
3210 | |
3211 | return mmio; | |
3212 | } | |
3213 | ||
88715657 AL |
3214 | static int get_free_io_mem_idx(void) |
3215 | { | |
3216 | int i; | |
3217 | ||
3218 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) | |
3219 | if (!io_mem_used[i]) { | |
3220 | io_mem_used[i] = 1; | |
3221 | return i; | |
3222 | } | |
c6703b47 | 3223 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
88715657 AL |
3224 | return -1; |
3225 | } | |
3226 | ||
33417e70 FB |
3227 | /* mem_read and mem_write are arrays of functions containing the |
3228 | function to access byte (index 0), word (index 1) and dword (index | |
0b4e6e3e | 3229 | 2). Functions can be omitted with a NULL function pointer. |
3ee89922 | 3230 | If io_index is non zero, the corresponding io zone is |
4254fab8 BS |
3231 | modified. If it is zero, a new io zone is allocated. The return |
3232 | value can be used with cpu_register_physical_memory(). (-1) is | |
3233 | returned if error. */ | |
1eed09cb | 3234 | static int cpu_register_io_memory_fixed(int io_index, |
d60efc6b BS |
3235 | CPUReadMemoryFunc * const *mem_read, |
3236 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb | 3237 | void *opaque) |
33417e70 | 3238 | { |
4254fab8 | 3239 | int i, subwidth = 0; |
33417e70 FB |
3240 | |
3241 | if (io_index <= 0) { | |
88715657 AL |
3242 | io_index = get_free_io_mem_idx(); |
3243 | if (io_index == -1) | |
3244 | return io_index; | |
33417e70 | 3245 | } else { |
1eed09cb | 3246 | io_index >>= IO_MEM_SHIFT; |
33417e70 FB |
3247 | if (io_index >= IO_MEM_NB_ENTRIES) |
3248 | return -1; | |
3249 | } | |
b5ff1b31 | 3250 | |
33417e70 | 3251 | for(i = 0;i < 3; i++) { |
4254fab8 BS |
3252 | if (!mem_read[i] || !mem_write[i]) |
3253 | subwidth = IO_MEM_SUBWIDTH; | |
33417e70 FB |
3254 | io_mem_read[io_index][i] = mem_read[i]; |
3255 | io_mem_write[io_index][i] = mem_write[i]; | |
3256 | } | |
a4193c8a | 3257 | io_mem_opaque[io_index] = opaque; |
4254fab8 | 3258 | return (io_index << IO_MEM_SHIFT) | subwidth; |
33417e70 | 3259 | } |
61382a50 | 3260 | |
d60efc6b BS |
3261 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
3262 | CPUWriteMemoryFunc * const *mem_write, | |
1eed09cb AK |
3263 | void *opaque) |
3264 | { | |
3265 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); | |
3266 | } | |
3267 | ||
88715657 AL |
3268 | void cpu_unregister_io_memory(int io_table_address) |
3269 | { | |
3270 | int i; | |
3271 | int io_index = io_table_address >> IO_MEM_SHIFT; | |
3272 | ||
3273 | for (i=0;i < 3; i++) { | |
3274 | io_mem_read[io_index][i] = unassigned_mem_read[i]; | |
3275 | io_mem_write[io_index][i] = unassigned_mem_write[i]; | |
3276 | } | |
3277 | io_mem_opaque[io_index] = NULL; | |
3278 | io_mem_used[io_index] = 0; | |
3279 | } | |
3280 | ||
e9179ce1 AK |
3281 | static void io_mem_init(void) |
3282 | { | |
3283 | int i; | |
3284 | ||
3285 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); | |
3286 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); | |
3287 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); | |
3288 | for (i=0; i<5; i++) | |
3289 | io_mem_used[i] = 1; | |
3290 | ||
3291 | io_mem_watch = cpu_register_io_memory(watch_mem_read, | |
3292 | watch_mem_write, NULL); | |
e9179ce1 AK |
3293 | } |
3294 | ||
e2eef170 PB |
3295 | #endif /* !defined(CONFIG_USER_ONLY) */ |
3296 | ||
13eb76e0 FB |
3297 | /* physical memory access (slow version, mainly for debug) */ |
3298 | #if defined(CONFIG_USER_ONLY) | |
a68fe89c PB |
3299 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
3300 | uint8_t *buf, int len, int is_write) | |
13eb76e0 FB |
3301 | { |
3302 | int l, flags; | |
3303 | target_ulong page; | |
53a5960a | 3304 | void * p; |
13eb76e0 FB |
3305 | |
3306 | while (len > 0) { | |
3307 | page = addr & TARGET_PAGE_MASK; | |
3308 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3309 | if (l > len) | |
3310 | l = len; | |
3311 | flags = page_get_flags(page); | |
3312 | if (!(flags & PAGE_VALID)) | |
a68fe89c | 3313 | return -1; |
13eb76e0 FB |
3314 | if (is_write) { |
3315 | if (!(flags & PAGE_WRITE)) | |
a68fe89c | 3316 | return -1; |
579a97f7 | 3317 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3318 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
a68fe89c | 3319 | return -1; |
72fb7daa AJ |
3320 | memcpy(p, buf, l); |
3321 | unlock_user(p, addr, l); | |
13eb76e0 FB |
3322 | } else { |
3323 | if (!(flags & PAGE_READ)) | |
a68fe89c | 3324 | return -1; |
579a97f7 | 3325 | /* XXX: this code should not depend on lock_user */ |
72fb7daa | 3326 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
a68fe89c | 3327 | return -1; |
72fb7daa | 3328 | memcpy(buf, p, l); |
5b257578 | 3329 | unlock_user(p, addr, 0); |
13eb76e0 FB |
3330 | } |
3331 | len -= l; | |
3332 | buf += l; | |
3333 | addr += l; | |
3334 | } | |
a68fe89c | 3335 | return 0; |
13eb76e0 | 3336 | } |
8df1cd07 | 3337 | |
13eb76e0 | 3338 | #else |
c227f099 | 3339 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
13eb76e0 FB |
3340 | int len, int is_write) |
3341 | { | |
3342 | int l, io_index; | |
3343 | uint8_t *ptr; | |
3344 | uint32_t val; | |
c227f099 | 3345 | target_phys_addr_t page; |
2e12669a | 3346 | unsigned long pd; |
92e873b9 | 3347 | PhysPageDesc *p; |
3b46e624 | 3348 | |
13eb76e0 FB |
3349 | while (len > 0) { |
3350 | page = addr & TARGET_PAGE_MASK; | |
3351 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3352 | if (l > len) | |
3353 | l = len; | |
92e873b9 | 3354 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
13eb76e0 FB |
3355 | if (!p) { |
3356 | pd = IO_MEM_UNASSIGNED; | |
3357 | } else { | |
3358 | pd = p->phys_offset; | |
3359 | } | |
3b46e624 | 3360 | |
13eb76e0 | 3361 | if (is_write) { |
3a7d929e | 3362 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
c227f099 | 3363 | target_phys_addr_t addr1 = addr; |
13eb76e0 | 3364 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 | 3365 | if (p) |
6c2934db | 3366 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
6a00d601 FB |
3367 | /* XXX: could force cpu_single_env to NULL to avoid |
3368 | potential bugs */ | |
6c2934db | 3369 | if (l >= 4 && ((addr1 & 3) == 0)) { |
1c213d19 | 3370 | /* 32 bit write access */ |
c27004ec | 3371 | val = ldl_p(buf); |
6c2934db | 3372 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
13eb76e0 | 3373 | l = 4; |
6c2934db | 3374 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
1c213d19 | 3375 | /* 16 bit write access */ |
c27004ec | 3376 | val = lduw_p(buf); |
6c2934db | 3377 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3378 | l = 2; |
3379 | } else { | |
1c213d19 | 3380 | /* 8 bit write access */ |
c27004ec | 3381 | val = ldub_p(buf); |
6c2934db | 3382 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
13eb76e0 FB |
3383 | l = 1; |
3384 | } | |
3385 | } else { | |
b448f2f3 FB |
3386 | unsigned long addr1; |
3387 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
13eb76e0 | 3388 | /* RAM case */ |
5579c7f3 | 3389 | ptr = qemu_get_ram_ptr(addr1); |
13eb76e0 | 3390 | memcpy(ptr, buf, l); |
3a7d929e FB |
3391 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3392 | /* invalidate code */ | |
3393 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3394 | /* set dirty bit */ | |
5fafdf24 | 3395 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
f23db169 | 3396 | (0xff & ~CODE_DIRTY_FLAG); |
3a7d929e | 3397 | } |
13eb76e0 FB |
3398 | } |
3399 | } else { | |
5fafdf24 | 3400 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3401 | !(pd & IO_MEM_ROMD)) { |
c227f099 | 3402 | target_phys_addr_t addr1 = addr; |
13eb76e0 FB |
3403 | /* I/O case */ |
3404 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 | 3405 | if (p) |
6c2934db AJ |
3406 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
3407 | if (l >= 4 && ((addr1 & 3) == 0)) { | |
13eb76e0 | 3408 | /* 32 bit read access */ |
6c2934db | 3409 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
c27004ec | 3410 | stl_p(buf, val); |
13eb76e0 | 3411 | l = 4; |
6c2934db | 3412 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
13eb76e0 | 3413 | /* 16 bit read access */ |
6c2934db | 3414 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
c27004ec | 3415 | stw_p(buf, val); |
13eb76e0 FB |
3416 | l = 2; |
3417 | } else { | |
1c213d19 | 3418 | /* 8 bit read access */ |
6c2934db | 3419 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
c27004ec | 3420 | stb_p(buf, val); |
13eb76e0 FB |
3421 | l = 1; |
3422 | } | |
3423 | } else { | |
3424 | /* RAM case */ | |
5579c7f3 | 3425 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
13eb76e0 FB |
3426 | (addr & ~TARGET_PAGE_MASK); |
3427 | memcpy(buf, ptr, l); | |
3428 | } | |
3429 | } | |
3430 | len -= l; | |
3431 | buf += l; | |
3432 | addr += l; | |
3433 | } | |
3434 | } | |
8df1cd07 | 3435 | |
d0ecd2aa | 3436 | /* used for ROM loading : can write in RAM and ROM */ |
c227f099 | 3437 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
d0ecd2aa FB |
3438 | const uint8_t *buf, int len) |
3439 | { | |
3440 | int l; | |
3441 | uint8_t *ptr; | |
c227f099 | 3442 | target_phys_addr_t page; |
d0ecd2aa FB |
3443 | unsigned long pd; |
3444 | PhysPageDesc *p; | |
3b46e624 | 3445 | |
d0ecd2aa FB |
3446 | while (len > 0) { |
3447 | page = addr & TARGET_PAGE_MASK; | |
3448 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3449 | if (l > len) | |
3450 | l = len; | |
3451 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3452 | if (!p) { | |
3453 | pd = IO_MEM_UNASSIGNED; | |
3454 | } else { | |
3455 | pd = p->phys_offset; | |
3456 | } | |
3b46e624 | 3457 | |
d0ecd2aa | 3458 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
2a4188a3 FB |
3459 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
3460 | !(pd & IO_MEM_ROMD)) { | |
d0ecd2aa FB |
3461 | /* do nothing */ |
3462 | } else { | |
3463 | unsigned long addr1; | |
3464 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3465 | /* ROM/RAM case */ | |
5579c7f3 | 3466 | ptr = qemu_get_ram_ptr(addr1); |
d0ecd2aa FB |
3467 | memcpy(ptr, buf, l); |
3468 | } | |
3469 | len -= l; | |
3470 | buf += l; | |
3471 | addr += l; | |
3472 | } | |
3473 | } | |
3474 | ||
6d16c2f8 AL |
3475 | typedef struct { |
3476 | void *buffer; | |
c227f099 AL |
3477 | target_phys_addr_t addr; |
3478 | target_phys_addr_t len; | |
6d16c2f8 AL |
3479 | } BounceBuffer; |
3480 | ||
3481 | static BounceBuffer bounce; | |
3482 | ||
ba223c29 AL |
3483 | typedef struct MapClient { |
3484 | void *opaque; | |
3485 | void (*callback)(void *opaque); | |
72cf2d4f | 3486 | QLIST_ENTRY(MapClient) link; |
ba223c29 AL |
3487 | } MapClient; |
3488 | ||
72cf2d4f BS |
3489 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
3490 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
ba223c29 AL |
3491 | |
3492 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) | |
3493 | { | |
3494 | MapClient *client = qemu_malloc(sizeof(*client)); | |
3495 | ||
3496 | client->opaque = opaque; | |
3497 | client->callback = callback; | |
72cf2d4f | 3498 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
ba223c29 AL |
3499 | return client; |
3500 | } | |
3501 | ||
3502 | void cpu_unregister_map_client(void *_client) | |
3503 | { | |
3504 | MapClient *client = (MapClient *)_client; | |
3505 | ||
72cf2d4f | 3506 | QLIST_REMOVE(client, link); |
34d5e948 | 3507 | qemu_free(client); |
ba223c29 AL |
3508 | } |
3509 | ||
3510 | static void cpu_notify_map_clients(void) | |
3511 | { | |
3512 | MapClient *client; | |
3513 | ||
72cf2d4f BS |
3514 | while (!QLIST_EMPTY(&map_client_list)) { |
3515 | client = QLIST_FIRST(&map_client_list); | |
ba223c29 | 3516 | client->callback(client->opaque); |
34d5e948 | 3517 | cpu_unregister_map_client(client); |
ba223c29 AL |
3518 | } |
3519 | } | |
3520 | ||
6d16c2f8 AL |
3521 | /* Map a physical memory region into a host virtual address. |
3522 | * May map a subset of the requested range, given by and returned in *plen. | |
3523 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3524 | * Use only for reads OR writes - not for read-modify-write operations. | |
ba223c29 AL |
3525 | * Use cpu_register_map_client() to know when retrying the map operation is |
3526 | * likely to succeed. | |
6d16c2f8 | 3527 | */ |
c227f099 AL |
3528 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
3529 | target_phys_addr_t *plen, | |
6d16c2f8 AL |
3530 | int is_write) |
3531 | { | |
c227f099 AL |
3532 | target_phys_addr_t len = *plen; |
3533 | target_phys_addr_t done = 0; | |
6d16c2f8 AL |
3534 | int l; |
3535 | uint8_t *ret = NULL; | |
3536 | uint8_t *ptr; | |
c227f099 | 3537 | target_phys_addr_t page; |
6d16c2f8 AL |
3538 | unsigned long pd; |
3539 | PhysPageDesc *p; | |
3540 | unsigned long addr1; | |
3541 | ||
3542 | while (len > 0) { | |
3543 | page = addr & TARGET_PAGE_MASK; | |
3544 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3545 | if (l > len) | |
3546 | l = len; | |
3547 | p = phys_page_find(page >> TARGET_PAGE_BITS); | |
3548 | if (!p) { | |
3549 | pd = IO_MEM_UNASSIGNED; | |
3550 | } else { | |
3551 | pd = p->phys_offset; | |
3552 | } | |
3553 | ||
3554 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { | |
3555 | if (done || bounce.buffer) { | |
3556 | break; | |
3557 | } | |
3558 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); | |
3559 | bounce.addr = addr; | |
3560 | bounce.len = l; | |
3561 | if (!is_write) { | |
3562 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); | |
3563 | } | |
3564 | ptr = bounce.buffer; | |
3565 | } else { | |
3566 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
5579c7f3 | 3567 | ptr = qemu_get_ram_ptr(addr1); |
6d16c2f8 AL |
3568 | } |
3569 | if (!done) { | |
3570 | ret = ptr; | |
3571 | } else if (ret + done != ptr) { | |
3572 | break; | |
3573 | } | |
3574 | ||
3575 | len -= l; | |
3576 | addr += l; | |
3577 | done += l; | |
3578 | } | |
3579 | *plen = done; | |
3580 | return ret; | |
3581 | } | |
3582 | ||
3583 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). | |
3584 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3585 | * the amount of memory that was actually read or written by the caller. | |
3586 | */ | |
c227f099 AL |
3587 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
3588 | int is_write, target_phys_addr_t access_len) | |
6d16c2f8 AL |
3589 | { |
3590 | if (buffer != bounce.buffer) { | |
3591 | if (is_write) { | |
c227f099 | 3592 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); |
6d16c2f8 AL |
3593 | while (access_len) { |
3594 | unsigned l; | |
3595 | l = TARGET_PAGE_SIZE; | |
3596 | if (l > access_len) | |
3597 | l = access_len; | |
3598 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3599 | /* invalidate code */ | |
3600 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); | |
3601 | /* set dirty bit */ | |
3602 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3603 | (0xff & ~CODE_DIRTY_FLAG); | |
3604 | } | |
3605 | addr1 += l; | |
3606 | access_len -= l; | |
3607 | } | |
3608 | } | |
3609 | return; | |
3610 | } | |
3611 | if (is_write) { | |
3612 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); | |
3613 | } | |
f8a83245 | 3614 | qemu_vfree(bounce.buffer); |
6d16c2f8 | 3615 | bounce.buffer = NULL; |
ba223c29 | 3616 | cpu_notify_map_clients(); |
6d16c2f8 | 3617 | } |
d0ecd2aa | 3618 | |
8df1cd07 | 3619 | /* warning: addr must be aligned */ |
c227f099 | 3620 | uint32_t ldl_phys(target_phys_addr_t addr) |
8df1cd07 FB |
3621 | { |
3622 | int io_index; | |
3623 | uint8_t *ptr; | |
3624 | uint32_t val; | |
3625 | unsigned long pd; | |
3626 | PhysPageDesc *p; | |
3627 | ||
3628 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3629 | if (!p) { | |
3630 | pd = IO_MEM_UNASSIGNED; | |
3631 | } else { | |
3632 | pd = p->phys_offset; | |
3633 | } | |
3b46e624 | 3634 | |
5fafdf24 | 3635 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
2a4188a3 | 3636 | !(pd & IO_MEM_ROMD)) { |
8df1cd07 FB |
3637 | /* I/O case */ |
3638 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3639 | if (p) |
3640 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3641 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
3642 | } else { | |
3643 | /* RAM case */ | |
5579c7f3 | 3644 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
8df1cd07 FB |
3645 | (addr & ~TARGET_PAGE_MASK); |
3646 | val = ldl_p(ptr); | |
3647 | } | |
3648 | return val; | |
3649 | } | |
3650 | ||
84b7b8e7 | 3651 | /* warning: addr must be aligned */ |
c227f099 | 3652 | uint64_t ldq_phys(target_phys_addr_t addr) |
84b7b8e7 FB |
3653 | { |
3654 | int io_index; | |
3655 | uint8_t *ptr; | |
3656 | uint64_t val; | |
3657 | unsigned long pd; | |
3658 | PhysPageDesc *p; | |
3659 | ||
3660 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3661 | if (!p) { | |
3662 | pd = IO_MEM_UNASSIGNED; | |
3663 | } else { | |
3664 | pd = p->phys_offset; | |
3665 | } | |
3b46e624 | 3666 | |
2a4188a3 FB |
3667 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
3668 | !(pd & IO_MEM_ROMD)) { | |
84b7b8e7 FB |
3669 | /* I/O case */ |
3670 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3671 | if (p) |
3672 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
84b7b8e7 FB |
3673 | #ifdef TARGET_WORDS_BIGENDIAN |
3674 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; | |
3675 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); | |
3676 | #else | |
3677 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); | |
3678 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; | |
3679 | #endif | |
3680 | } else { | |
3681 | /* RAM case */ | |
5579c7f3 | 3682 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
84b7b8e7 FB |
3683 | (addr & ~TARGET_PAGE_MASK); |
3684 | val = ldq_p(ptr); | |
3685 | } | |
3686 | return val; | |
3687 | } | |
3688 | ||
aab33094 | 3689 | /* XXX: optimize */ |
c227f099 | 3690 | uint32_t ldub_phys(target_phys_addr_t addr) |
aab33094 FB |
3691 | { |
3692 | uint8_t val; | |
3693 | cpu_physical_memory_read(addr, &val, 1); | |
3694 | return val; | |
3695 | } | |
3696 | ||
3697 | /* XXX: optimize */ | |
c227f099 | 3698 | uint32_t lduw_phys(target_phys_addr_t addr) |
aab33094 FB |
3699 | { |
3700 | uint16_t val; | |
3701 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); | |
3702 | return tswap16(val); | |
3703 | } | |
3704 | ||
8df1cd07 FB |
3705 | /* warning: addr must be aligned. The ram page is not masked as dirty |
3706 | and the code inside is not invalidated. It is useful if the dirty | |
3707 | bits are used to track modified PTEs */ | |
c227f099 | 3708 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3709 | { |
3710 | int io_index; | |
3711 | uint8_t *ptr; | |
3712 | unsigned long pd; | |
3713 | PhysPageDesc *p; | |
3714 | ||
3715 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3716 | if (!p) { | |
3717 | pd = IO_MEM_UNASSIGNED; | |
3718 | } else { | |
3719 | pd = p->phys_offset; | |
3720 | } | |
3b46e624 | 3721 | |
3a7d929e | 3722 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3723 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3724 | if (p) |
3725 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3726 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3727 | } else { | |
74576198 | 3728 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
5579c7f3 | 3729 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3730 | stl_p(ptr, val); |
74576198 AL |
3731 | |
3732 | if (unlikely(in_migration)) { | |
3733 | if (!cpu_physical_memory_is_dirty(addr1)) { | |
3734 | /* invalidate code */ | |
3735 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3736 | /* set dirty bit */ | |
3737 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= | |
3738 | (0xff & ~CODE_DIRTY_FLAG); | |
3739 | } | |
3740 | } | |
8df1cd07 FB |
3741 | } |
3742 | } | |
3743 | ||
c227f099 | 3744 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
bc98a7ef JM |
3745 | { |
3746 | int io_index; | |
3747 | uint8_t *ptr; | |
3748 | unsigned long pd; | |
3749 | PhysPageDesc *p; | |
3750 | ||
3751 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3752 | if (!p) { | |
3753 | pd = IO_MEM_UNASSIGNED; | |
3754 | } else { | |
3755 | pd = p->phys_offset; | |
3756 | } | |
3b46e624 | 3757 | |
bc98a7ef JM |
3758 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
3759 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); | |
8da3ff18 PB |
3760 | if (p) |
3761 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
bc98a7ef JM |
3762 | #ifdef TARGET_WORDS_BIGENDIAN |
3763 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); | |
3764 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); | |
3765 | #else | |
3766 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); | |
3767 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); | |
3768 | #endif | |
3769 | } else { | |
5579c7f3 | 3770 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bc98a7ef JM |
3771 | (addr & ~TARGET_PAGE_MASK); |
3772 | stq_p(ptr, val); | |
3773 | } | |
3774 | } | |
3775 | ||
8df1cd07 | 3776 | /* warning: addr must be aligned */ |
c227f099 | 3777 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
8df1cd07 FB |
3778 | { |
3779 | int io_index; | |
3780 | uint8_t *ptr; | |
3781 | unsigned long pd; | |
3782 | PhysPageDesc *p; | |
3783 | ||
3784 | p = phys_page_find(addr >> TARGET_PAGE_BITS); | |
3785 | if (!p) { | |
3786 | pd = IO_MEM_UNASSIGNED; | |
3787 | } else { | |
3788 | pd = p->phys_offset; | |
3789 | } | |
3b46e624 | 3790 | |
3a7d929e | 3791 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
8df1cd07 | 3792 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
8da3ff18 PB |
3793 | if (p) |
3794 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; | |
8df1cd07 FB |
3795 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
3796 | } else { | |
3797 | unsigned long addr1; | |
3798 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); | |
3799 | /* RAM case */ | |
5579c7f3 | 3800 | ptr = qemu_get_ram_ptr(addr1); |
8df1cd07 | 3801 | stl_p(ptr, val); |
3a7d929e FB |
3802 | if (!cpu_physical_memory_is_dirty(addr1)) { |
3803 | /* invalidate code */ | |
3804 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); | |
3805 | /* set dirty bit */ | |
f23db169 FB |
3806 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
3807 | (0xff & ~CODE_DIRTY_FLAG); | |
3a7d929e | 3808 | } |
8df1cd07 FB |
3809 | } |
3810 | } | |
3811 | ||
aab33094 | 3812 | /* XXX: optimize */ |
c227f099 | 3813 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3814 | { |
3815 | uint8_t v = val; | |
3816 | cpu_physical_memory_write(addr, &v, 1); | |
3817 | } | |
3818 | ||
3819 | /* XXX: optimize */ | |
c227f099 | 3820 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
aab33094 FB |
3821 | { |
3822 | uint16_t v = tswap16(val); | |
3823 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); | |
3824 | } | |
3825 | ||
3826 | /* XXX: optimize */ | |
c227f099 | 3827 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
aab33094 FB |
3828 | { |
3829 | val = tswap64(val); | |
3830 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); | |
3831 | } | |
3832 | ||
5e2972fd | 3833 | /* virtual memory access for debug (includes writing to ROM) */ |
5fafdf24 | 3834 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
b448f2f3 | 3835 | uint8_t *buf, int len, int is_write) |
13eb76e0 FB |
3836 | { |
3837 | int l; | |
c227f099 | 3838 | target_phys_addr_t phys_addr; |
9b3c35e0 | 3839 | target_ulong page; |
13eb76e0 FB |
3840 | |
3841 | while (len > 0) { | |
3842 | page = addr & TARGET_PAGE_MASK; | |
3843 | phys_addr = cpu_get_phys_page_debug(env, page); | |
3844 | /* if no physical page mapped, return an error */ | |
3845 | if (phys_addr == -1) | |
3846 | return -1; | |
3847 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3848 | if (l > len) | |
3849 | l = len; | |
5e2972fd | 3850 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
5e2972fd AL |
3851 | if (is_write) |
3852 | cpu_physical_memory_write_rom(phys_addr, buf, l); | |
3853 | else | |
5e2972fd | 3854 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
13eb76e0 FB |
3855 | len -= l; |
3856 | buf += l; | |
3857 | addr += l; | |
3858 | } | |
3859 | return 0; | |
3860 | } | |
a68fe89c | 3861 | #endif |
13eb76e0 | 3862 | |
2e70f6ef PB |
3863 | /* in deterministic execution mode, instructions doing device I/Os |
3864 | must be at the end of the TB */ | |
3865 | void cpu_io_recompile(CPUState *env, void *retaddr) | |
3866 | { | |
3867 | TranslationBlock *tb; | |
3868 | uint32_t n, cflags; | |
3869 | target_ulong pc, cs_base; | |
3870 | uint64_t flags; | |
3871 | ||
3872 | tb = tb_find_pc((unsigned long)retaddr); | |
3873 | if (!tb) { | |
3874 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", | |
3875 | retaddr); | |
3876 | } | |
3877 | n = env->icount_decr.u16.low + tb->icount; | |
3878 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); | |
3879 | /* Calculate how many instructions had been executed before the fault | |
bf20dc07 | 3880 | occurred. */ |
2e70f6ef PB |
3881 | n = n - env->icount_decr.u16.low; |
3882 | /* Generate a new TB ending on the I/O insn. */ | |
3883 | n++; | |
3884 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
3885 | they were already the first instruction in the TB. If this is not | |
bf20dc07 | 3886 | the first instruction in a TB then re-execute the preceding |
2e70f6ef PB |
3887 | branch. */ |
3888 | #if defined(TARGET_MIPS) | |
3889 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
3890 | env->active_tc.PC -= 4; | |
3891 | env->icount_decr.u16.low++; | |
3892 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
3893 | } | |
3894 | #elif defined(TARGET_SH4) | |
3895 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
3896 | && n > 1) { | |
3897 | env->pc -= 2; | |
3898 | env->icount_decr.u16.low++; | |
3899 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); | |
3900 | } | |
3901 | #endif | |
3902 | /* This should never happen. */ | |
3903 | if (n > CF_COUNT_MASK) | |
3904 | cpu_abort(env, "TB too big during recompile"); | |
3905 | ||
3906 | cflags = n | CF_LAST_IO; | |
3907 | pc = tb->pc; | |
3908 | cs_base = tb->cs_base; | |
3909 | flags = tb->flags; | |
3910 | tb_phys_invalidate(tb, -1); | |
3911 | /* FIXME: In theory this could raise an exception. In practice | |
3912 | we have already translated the block once so it's probably ok. */ | |
3913 | tb_gen_code(env, pc, cs_base, flags, cflags); | |
bf20dc07 | 3914 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
2e70f6ef PB |
3915 | the first in the TB) then we end up generating a whole new TB and |
3916 | repeating the fault, which is horribly inefficient. | |
3917 | Better would be to execute just this insn uncached, or generate a | |
3918 | second new TB. */ | |
3919 | cpu_resume_from_signal(env, NULL); | |
3920 | } | |
3921 | ||
e3db7226 FB |
3922 | void dump_exec_info(FILE *f, |
3923 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) | |
3924 | { | |
3925 | int i, target_code_size, max_target_code_size; | |
3926 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
3927 | TranslationBlock *tb; | |
3b46e624 | 3928 | |
e3db7226 FB |
3929 | target_code_size = 0; |
3930 | max_target_code_size = 0; | |
3931 | cross_page = 0; | |
3932 | direct_jmp_count = 0; | |
3933 | direct_jmp2_count = 0; | |
3934 | for(i = 0; i < nb_tbs; i++) { | |
3935 | tb = &tbs[i]; | |
3936 | target_code_size += tb->size; | |
3937 | if (tb->size > max_target_code_size) | |
3938 | max_target_code_size = tb->size; | |
3939 | if (tb->page_addr[1] != -1) | |
3940 | cross_page++; | |
3941 | if (tb->tb_next_offset[0] != 0xffff) { | |
3942 | direct_jmp_count++; | |
3943 | if (tb->tb_next_offset[1] != 0xffff) { | |
3944 | direct_jmp2_count++; | |
3945 | } | |
3946 | } | |
3947 | } | |
3948 | /* XXX: avoid using doubles ? */ | |
57fec1fe | 3949 | cpu_fprintf(f, "Translation buffer state:\n"); |
26a5f13b FB |
3950 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
3951 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); | |
3952 | cpu_fprintf(f, "TB count %d/%d\n", | |
3953 | nb_tbs, code_gen_max_blocks); | |
5fafdf24 | 3954 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
e3db7226 FB |
3955 | nb_tbs ? target_code_size / nb_tbs : 0, |
3956 | max_target_code_size); | |
5fafdf24 | 3957 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
e3db7226 FB |
3958 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
3959 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); | |
5fafdf24 TS |
3960 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
3961 | cross_page, | |
e3db7226 FB |
3962 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
3963 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", | |
5fafdf24 | 3964 | direct_jmp_count, |
e3db7226 FB |
3965 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
3966 | direct_jmp2_count, | |
3967 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); | |
57fec1fe | 3968 | cpu_fprintf(f, "\nStatistics:\n"); |
e3db7226 FB |
3969 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
3970 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); | |
3971 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); | |
b67d9a52 | 3972 | tcg_dump_info(f, cpu_fprintf); |
e3db7226 FB |
3973 | } |
3974 | ||
5fafdf24 | 3975 | #if !defined(CONFIG_USER_ONLY) |
61382a50 FB |
3976 | |
3977 | #define MMUSUFFIX _cmmu | |
3978 | #define GETPC() NULL | |
3979 | #define env cpu_single_env | |
b769d8fe | 3980 | #define SOFTMMU_CODE_ACCESS |
61382a50 FB |
3981 | |
3982 | #define SHIFT 0 | |
3983 | #include "softmmu_template.h" | |
3984 | ||
3985 | #define SHIFT 1 | |
3986 | #include "softmmu_template.h" | |
3987 | ||
3988 | #define SHIFT 2 | |
3989 | #include "softmmu_template.h" | |
3990 | ||
3991 | #define SHIFT 3 | |
3992 | #include "softmmu_template.h" | |
3993 | ||
3994 | #undef env | |
3995 | ||
3996 | #endif |