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User-mode GDB stub improvements - handle fork
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CommitLineData
b4608c04
FB
1/*
2 * gdb server stub
5fafdf24 3 *
3475187d 4 * Copyright (c) 2003-2005 Fabrice Bellard
b4608c04
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
978efd6a 20#include "config.h"
56aebc89 21#include "qemu-common.h"
1fddef4b
FB
22#ifdef CONFIG_USER_ONLY
23#include <stdlib.h>
24#include <stdio.h>
25#include <stdarg.h>
26#include <string.h>
27#include <errno.h>
28#include <unistd.h>
978efd6a 29#include <fcntl.h>
1fddef4b
FB
30
31#include "qemu.h"
32#else
87ecb68b
PB
33#include "qemu-char.h"
34#include "sysemu.h"
35#include "gdbstub.h"
1fddef4b 36#endif
67b915a5 37
56aebc89
PB
38#define MAX_PACKET_LENGTH 4096
39
8f447cc7
FB
40#include "qemu_socket.h"
41#ifdef _WIN32
42/* XXX: these constants may be independent of the host ones even for Unix */
43#ifndef SIGTRAP
44#define SIGTRAP 5
45#endif
46#ifndef SIGINT
47#define SIGINT 2
48#endif
49#else
b4608c04 50#include <signal.h>
8f447cc7 51#endif
b4608c04 52
4abe615b 53//#define DEBUG_GDB
b4608c04 54
56aebc89
PB
55typedef struct GDBRegisterState {
56 int base_reg;
57 int num_regs;
58 gdb_reg_cb get_reg;
59 gdb_reg_cb set_reg;
60 const char *xml;
61 struct GDBRegisterState *next;
62} GDBRegisterState;
63
858693c6
FB
64enum RSState {
65 RS_IDLE,
66 RS_GETLINE,
67 RS_CHKSUM1,
68 RS_CHKSUM2,
a2d1ebaf 69 RS_SYSCALL,
858693c6 70};
858693c6 71typedef struct GDBState {
880a7578
AL
72 CPUState *c_cpu; /* current CPU for step/continue ops */
73 CPUState *g_cpu; /* current CPU for other ops */
74 CPUState *query_cpu; /* for q{f|s}ThreadInfo */
41625033 75 enum RSState state; /* parsing state */
56aebc89 76 char line_buf[MAX_PACKET_LENGTH];
858693c6
FB
77 int line_buf_index;
78 int line_csum;
56aebc89 79 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
4046d913 80 int last_packet_len;
1f487ee9 81 int signal;
41625033 82#ifdef CONFIG_USER_ONLY
4046d913 83 int fd;
41625033 84 int running_state;
4046d913
PB
85#else
86 CharDriverState *chr;
41625033 87#endif
858693c6 88} GDBState;
b4608c04 89
60897d36
EI
90/* By default use no IRQs and no timers while single stepping so as to
91 * make single stepping like an ICE HW step.
92 */
93static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
94
880a7578
AL
95static GDBState *gdbserver_state;
96
56aebc89
PB
97/* This is an ugly hack to cope with both new and old gdb.
98 If gdb sends qXfer:features:read then assume we're talking to a newish
99 gdb that understands target descriptions. */
100static int gdb_has_xml;
101
1fddef4b 102#ifdef CONFIG_USER_ONLY
4046d913
PB
103/* XXX: This is not thread safe. Do we care? */
104static int gdbserver_fd = -1;
105
858693c6 106static int get_char(GDBState *s)
b4608c04
FB
107{
108 uint8_t ch;
109 int ret;
110
111 for(;;) {
8f447cc7 112 ret = recv(s->fd, &ch, 1, 0);
b4608c04 113 if (ret < 0) {
1f487ee9
EI
114 if (errno == ECONNRESET)
115 s->fd = -1;
b4608c04
FB
116 if (errno != EINTR && errno != EAGAIN)
117 return -1;
118 } else if (ret == 0) {
1f487ee9
EI
119 close(s->fd);
120 s->fd = -1;
b4608c04
FB
121 return -1;
122 } else {
123 break;
124 }
125 }
126 return ch;
127}
4046d913 128#endif
b4608c04 129
a2d1ebaf
PB
130static gdb_syscall_complete_cb gdb_current_syscall_cb;
131
132enum {
133 GDB_SYS_UNKNOWN,
134 GDB_SYS_ENABLED,
135 GDB_SYS_DISABLED,
136} gdb_syscall_mode;
137
138/* If gdb is connected when the first semihosting syscall occurs then use
139 remote gdb syscalls. Otherwise use native file IO. */
140int use_gdb_syscalls(void)
141{
142 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
880a7578
AL
143 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
144 : GDB_SYS_DISABLED);
a2d1ebaf
PB
145 }
146 return gdb_syscall_mode == GDB_SYS_ENABLED;
147}
148
ba70a624
EI
149/* Resume execution. */
150static inline void gdb_continue(GDBState *s)
151{
152#ifdef CONFIG_USER_ONLY
153 s->running_state = 1;
154#else
155 vm_start();
156#endif
157}
158
858693c6 159static void put_buffer(GDBState *s, const uint8_t *buf, int len)
b4608c04 160{
4046d913 161#ifdef CONFIG_USER_ONLY
b4608c04
FB
162 int ret;
163
164 while (len > 0) {
8f447cc7 165 ret = send(s->fd, buf, len, 0);
b4608c04
FB
166 if (ret < 0) {
167 if (errno != EINTR && errno != EAGAIN)
168 return;
169 } else {
170 buf += ret;
171 len -= ret;
172 }
173 }
4046d913
PB
174#else
175 qemu_chr_write(s->chr, buf, len);
176#endif
b4608c04
FB
177}
178
179static inline int fromhex(int v)
180{
181 if (v >= '0' && v <= '9')
182 return v - '0';
183 else if (v >= 'A' && v <= 'F')
184 return v - 'A' + 10;
185 else if (v >= 'a' && v <= 'f')
186 return v - 'a' + 10;
187 else
188 return 0;
189}
190
191static inline int tohex(int v)
192{
193 if (v < 10)
194 return v + '0';
195 else
196 return v - 10 + 'a';
197}
198
199static void memtohex(char *buf, const uint8_t *mem, int len)
200{
201 int i, c;
202 char *q;
203 q = buf;
204 for(i = 0; i < len; i++) {
205 c = mem[i];
206 *q++ = tohex(c >> 4);
207 *q++ = tohex(c & 0xf);
208 }
209 *q = '\0';
210}
211
212static void hextomem(uint8_t *mem, const char *buf, int len)
213{
214 int i;
215
216 for(i = 0; i < len; i++) {
217 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
218 buf += 2;
219 }
220}
221
b4608c04 222/* return -1 if error, 0 if OK */
56aebc89 223static int put_packet_binary(GDBState *s, const char *buf, int len)
b4608c04 224{
56aebc89 225 int csum, i;
60fe76f3 226 uint8_t *p;
b4608c04 227
b4608c04 228 for(;;) {
4046d913
PB
229 p = s->last_packet;
230 *(p++) = '$';
4046d913
PB
231 memcpy(p, buf, len);
232 p += len;
b4608c04
FB
233 csum = 0;
234 for(i = 0; i < len; i++) {
235 csum += buf[i];
236 }
4046d913
PB
237 *(p++) = '#';
238 *(p++) = tohex((csum >> 4) & 0xf);
239 *(p++) = tohex((csum) & 0xf);
b4608c04 240
4046d913 241 s->last_packet_len = p - s->last_packet;
ffe8ab83 242 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
b4608c04 243
4046d913
PB
244#ifdef CONFIG_USER_ONLY
245 i = get_char(s);
246 if (i < 0)
b4608c04 247 return -1;
4046d913 248 if (i == '+')
b4608c04 249 break;
4046d913
PB
250#else
251 break;
252#endif
b4608c04
FB
253 }
254 return 0;
255}
256
56aebc89
PB
257/* return -1 if error, 0 if OK */
258static int put_packet(GDBState *s, const char *buf)
259{
260#ifdef DEBUG_GDB
261 printf("reply='%s'\n", buf);
262#endif
79808573 263
56aebc89
PB
264 return put_packet_binary(s, buf, strlen(buf));
265}
266
267/* The GDB remote protocol transfers values in target byte order. This means
268 we can use the raw memory access routines to access the value buffer.
269 Conveniently, these also handle the case where the buffer is mis-aligned.
270 */
271#define GET_REG8(val) do { \
272 stb_p(mem_buf, val); \
273 return 1; \
274 } while(0)
275#define GET_REG16(val) do { \
276 stw_p(mem_buf, val); \
277 return 2; \
278 } while(0)
279#define GET_REG32(val) do { \
280 stl_p(mem_buf, val); \
281 return 4; \
282 } while(0)
283#define GET_REG64(val) do { \
284 stq_p(mem_buf, val); \
285 return 8; \
286 } while(0)
287
288#if TARGET_LONG_BITS == 64
289#define GET_REGL(val) GET_REG64(val)
290#define ldtul_p(addr) ldq_p(addr)
291#else
292#define GET_REGL(val) GET_REG32(val)
293#define ldtul_p(addr) ldl_p(addr)
79808573
FB
294#endif
295
56aebc89 296#if defined(TARGET_I386)
5ad265ee
AZ
297
298#ifdef TARGET_X86_64
56aebc89
PB
299static const int gpr_map[16] = {
300 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
301 8, 9, 10, 11, 12, 13, 14, 15
302};
79808573 303#else
56aebc89 304static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
79808573 305#endif
79808573 306
56aebc89
PB
307#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
308
309static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
79808573 310{
56aebc89
PB
311 if (n < CPU_NB_REGS) {
312 GET_REGL(env->regs[gpr_map[n]]);
313 } else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {
314 /* FIXME: byteswap float values. */
315#ifdef USE_X86LDOUBLE
316 memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10);
79808573 317#else
56aebc89 318 memset(mem_buf, 0, 10);
79808573 319#endif
56aebc89
PB
320 return 10;
321 } else if (n >= CPU_NB_REGS + 24) {
322 n -= CPU_NB_REGS + 24;
323 if (n < CPU_NB_REGS) {
324 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
325 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
326 return 16;
327 } else if (n == CPU_NB_REGS) {
328 GET_REG32(env->mxcsr);
329 }
330 } else {
331 n -= CPU_NB_REGS;
332 switch (n) {
333 case 0: GET_REGL(env->eip);
334 case 1: GET_REG32(env->eflags);
335 case 2: GET_REG32(env->segs[R_CS].selector);
336 case 3: GET_REG32(env->segs[R_SS].selector);
337 case 4: GET_REG32(env->segs[R_DS].selector);
338 case 5: GET_REG32(env->segs[R_ES].selector);
339 case 6: GET_REG32(env->segs[R_FS].selector);
340 case 7: GET_REG32(env->segs[R_GS].selector);
341 /* 8...15 x87 regs. */
342 case 16: GET_REG32(env->fpuc);
343 case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11);
344 case 18: GET_REG32(0); /* ftag */
345 case 19: GET_REG32(0); /* fiseg */
346 case 20: GET_REG32(0); /* fioff */
347 case 21: GET_REG32(0); /* foseg */
348 case 22: GET_REG32(0); /* fooff */
349 case 23: GET_REG32(0); /* fop */
350 /* 24+ xmm regs. */
351 }
79808573 352 }
56aebc89 353 return 0;
6da41eaf
FB
354}
355
56aebc89 356static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
6da41eaf 357{
56aebc89 358 uint32_t tmp;
6da41eaf 359
56aebc89
PB
360 if (i < CPU_NB_REGS) {
361 env->regs[gpr_map[i]] = ldtul_p(mem_buf);
362 return sizeof(target_ulong);
363 } else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {
364 i -= CPU_NB_REGS + 8;
365#ifdef USE_X86LDOUBLE
366 memcpy(&env->fpregs[i], mem_buf, 10);
79808573 367#endif
56aebc89
PB
368 return 10;
369 } else if (i >= CPU_NB_REGS + 24) {
370 i -= CPU_NB_REGS + 24;
371 if (i < CPU_NB_REGS) {
372 env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);
373 env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8);
374 return 16;
375 } else if (i == CPU_NB_REGS) {
376 env->mxcsr = ldl_p(mem_buf);
377 return 4;
79808573 378 }
56aebc89
PB
379 } else {
380 i -= CPU_NB_REGS;
381 switch (i) {
382 case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong);
383 case 1: env->eflags = ldl_p(mem_buf); return 4;
384#if defined(CONFIG_USER_ONLY)
385#define LOAD_SEG(index, sreg)\
386 tmp = ldl_p(mem_buf);\
387 if (tmp != env->segs[sreg].selector)\
388 cpu_x86_load_seg(env, sreg, tmp);
389#else
390/* FIXME: Honor segment registers. Needs to avoid raising an exception
391 when the selector is invalid. */
392#define LOAD_SEG(index, sreg) do {} while(0)
6da41eaf 393#endif
56aebc89
PB
394 case 2: LOAD_SEG(10, R_CS); return 4;
395 case 3: LOAD_SEG(11, R_SS); return 4;
396 case 4: LOAD_SEG(12, R_DS); return 4;
397 case 5: LOAD_SEG(13, R_ES); return 4;
398 case 6: LOAD_SEG(14, R_FS); return 4;
399 case 7: LOAD_SEG(15, R_GS); return 4;
400 /* 8...15 x87 regs. */
401 case 16: env->fpuc = ldl_p(mem_buf); return 4;
402 case 17:
403 tmp = ldl_p(mem_buf);
404 env->fpstt = (tmp >> 11) & 7;
405 env->fpus = tmp & ~0x3800;
406 return 4;
407 case 18: /* ftag */ return 4;
408 case 19: /* fiseg */ return 4;
409 case 20: /* fioff */ return 4;
410 case 21: /* foseg */ return 4;
411 case 22: /* fooff */ return 4;
412 case 23: /* fop */ return 4;
413 /* 24+ xmm regs. */
79808573 414 }
79808573 415 }
56aebc89
PB
416 /* Unrecognised register. */
417 return 0;
6da41eaf
FB
418}
419
9e62fd7f 420#elif defined (TARGET_PPC)
9e62fd7f 421
56aebc89 422#define NUM_CORE_REGS 71
9e62fd7f 423
56aebc89 424static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
9e62fd7f 425{
56aebc89
PB
426 if (n < 32) {
427 /* gprs */
428 GET_REGL(env->gpr[n]);
429 } else if (n < 64) {
430 /* fprs */
8d4acf9b 431 stfq_p(mem_buf, env->fpr[n-32]);
56aebc89
PB
432 return 8;
433 } else {
434 switch (n) {
435 case 64: GET_REGL(env->nip);
436 case 65: GET_REGL(env->msr);
437 case 66:
438 {
439 uint32_t cr = 0;
440 int i;
441 for (i = 0; i < 8; i++)
442 cr |= env->crf[i] << (32 - ((i + 1) * 4));
443 GET_REG32(cr);
444 }
445 case 67: GET_REGL(env->lr);
446 case 68: GET_REGL(env->ctr);
3d7b417e 447 case 69: GET_REGL(env->xer);
56aebc89
PB
448 case 70: GET_REG32(0); /* fpscr */
449 }
450 }
451 return 0;
452}
9e62fd7f 453
56aebc89
PB
454static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
455{
456 if (n < 32) {
457 /* gprs */
458 env->gpr[n] = ldtul_p(mem_buf);
459 return sizeof(target_ulong);
460 } else if (n < 64) {
461 /* fprs */
8d4acf9b 462 env->fpr[n-32] = ldfq_p(mem_buf);
56aebc89
PB
463 return 8;
464 } else {
465 switch (n) {
466 case 64:
467 env->nip = ldtul_p(mem_buf);
468 return sizeof(target_ulong);
469 case 65:
470 ppc_store_msr(env, ldtul_p(mem_buf));
471 return sizeof(target_ulong);
472 case 66:
473 {
474 uint32_t cr = ldl_p(mem_buf);
475 int i;
476 for (i = 0; i < 8; i++)
477 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
478 return 4;
479 }
480 case 67:
481 env->lr = ldtul_p(mem_buf);
482 return sizeof(target_ulong);
483 case 68:
484 env->ctr = ldtul_p(mem_buf);
485 return sizeof(target_ulong);
486 case 69:
3d7b417e
AJ
487 env->xer = ldtul_p(mem_buf);
488 return sizeof(target_ulong);
56aebc89
PB
489 case 70:
490 /* fpscr */
491 return 4;
492 }
493 }
494 return 0;
e95c8d51 495}
56aebc89 496
e95c8d51 497#elif defined (TARGET_SPARC)
56aebc89
PB
498
499#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
500#define NUM_CORE_REGS 86
96d19126 501#else
56aebc89 502#define NUM_CORE_REGS 73
96d19126 503#endif
56aebc89 504
96d19126 505#ifdef TARGET_ABI32
56aebc89 506#define GET_REGA(val) GET_REG32(val)
96d19126 507#else
56aebc89 508#define GET_REGA(val) GET_REGL(val)
96d19126 509#endif
e95c8d51 510
56aebc89
PB
511static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
512{
513 if (n < 8) {
514 /* g0..g7 */
515 GET_REGA(env->gregs[n]);
e95c8d51 516 }
56aebc89
PB
517 if (n < 32) {
518 /* register window */
519 GET_REGA(env->regwptr[n - 8]);
e95c8d51 520 }
56aebc89
PB
521#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
522 if (n < 64) {
523 /* fprs */
524 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
e95c8d51
FB
525 }
526 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
56aebc89
PB
527 switch (n) {
528 case 64: GET_REGA(env->y);
529 case 65: GET_REGA(GET_PSR(env));
530 case 66: GET_REGA(env->wim);
531 case 67: GET_REGA(env->tbr);
532 case 68: GET_REGA(env->pc);
533 case 69: GET_REGA(env->npc);
534 case 70: GET_REGA(env->fsr);
535 case 71: GET_REGA(0); /* csr */
536 case 72: GET_REGA(0);
537 }
3475187d 538#else
56aebc89
PB
539 if (n < 64) {
540 /* f0-f31 */
541 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
542 }
543 if (n < 80) {
544 /* f32-f62 (double width, even numbers only) */
545 uint64_t val;
9d9754a3 546
56aebc89
PB
547 val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
548 val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
549 GET_REG64(val);
3475187d 550 }
56aebc89
PB
551 switch (n) {
552 case 80: GET_REGL(env->pc);
553 case 81: GET_REGL(env->npc);
554 case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
17d996e1
BS
555 ((env->asi & 0xff) << 24) |
556 ((env->pstate & 0xfff) << 8) |
557 GET_CWP64(env));
56aebc89
PB
558 case 83: GET_REGL(env->fsr);
559 case 84: GET_REGL(env->fprs);
560 case 85: GET_REGL(env->y);
561 }
3475187d 562#endif
56aebc89 563 return 0;
e95c8d51
FB
564}
565
56aebc89 566static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
e95c8d51 567{
56aebc89
PB
568#if defined(TARGET_ABI32)
569 abi_ulong tmp;
570
571 tmp = ldl_p(mem_buf);
96d19126 572#else
56aebc89
PB
573 target_ulong tmp;
574
575 tmp = ldtul_p(mem_buf);
96d19126 576#endif
e95c8d51 577
56aebc89
PB
578 if (n < 8) {
579 /* g0..g7 */
580 env->gregs[n] = tmp;
581 } else if (n < 32) {
582 /* register window */
583 env->regwptr[n - 8] = tmp;
e95c8d51 584 }
56aebc89
PB
585#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
586 else if (n < 64) {
587 /* fprs */
588 *((uint32_t *)&env->fpr[n - 32]) = tmp;
589 } else {
590 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
591 switch (n) {
592 case 64: env->y = tmp; break;
593 case 65: PUT_PSR(env, tmp); break;
594 case 66: env->wim = tmp; break;
595 case 67: env->tbr = tmp; break;
596 case 68: env->pc = tmp; break;
597 case 69: env->npc = tmp; break;
598 case 70: env->fsr = tmp; break;
599 default: return 0;
600 }
e95c8d51 601 }
56aebc89 602 return 4;
3475187d 603#else
56aebc89
PB
604 else if (n < 64) {
605 /* f0-f31 */
56aebc89
PB
606 env->fpr[n] = ldfl_p(mem_buf);
607 return 4;
608 } else if (n < 80) {
609 /* f32-f62 (double width, even numbers only) */
610 *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
611 *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
612 } else {
613 switch (n) {
614 case 80: env->pc = tmp; break;
615 case 81: env->npc = tmp; break;
616 case 82:
617 PUT_CCR(env, tmp >> 32);
618 env->asi = (tmp >> 24) & 0xff;
619 env->pstate = (tmp >> 8) & 0xfff;
620 PUT_CWP64(env, tmp & 0xff);
621 break;
622 case 83: env->fsr = tmp; break;
623 case 84: env->fprs = tmp; break;
624 case 85: env->y = tmp; break;
625 default: return 0;
626 }
17d996e1 627 }
56aebc89 628 return 8;
3475187d 629#endif
9e62fd7f 630}
1fddef4b 631#elif defined (TARGET_ARM)
6da41eaf 632
56aebc89
PB
633/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
634 whatever the target description contains. Due to a historical mishap
635 the FPA registers appear in between core integer regs and the CPSR.
636 We hack round this by giving the FPA regs zero size when talking to a
637 newer gdb. */
638#define NUM_CORE_REGS 26
639#define GDB_CORE_XML "arm-core.xml"
e6e5906b 640
56aebc89 641static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
e6e5906b 642{
56aebc89
PB
643 if (n < 16) {
644 /* Core integer register. */
645 GET_REG32(env->regs[n]);
646 }
647 if (n < 24) {
648 /* FPA registers. */
649 if (gdb_has_xml)
650 return 0;
651 memset(mem_buf, 0, 12);
652 return 12;
653 }
654 switch (n) {
655 case 24:
656 /* FPA status register. */
657 if (gdb_has_xml)
658 return 0;
659 GET_REG32(0);
660 case 25:
661 /* CPSR */
662 GET_REG32(cpsr_read(env));
663 }
664 /* Unknown register. */
665 return 0;
e6e5906b 666}
6f970bd9 667
56aebc89
PB
668static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
669{
670 uint32_t tmp;
6f970bd9 671
56aebc89 672 tmp = ldl_p(mem_buf);
6f970bd9 673
56aebc89
PB
674 /* Mask out low bit of PC to workaround gdb bugs. This will probably
675 cause problems if we ever implement the Jazelle DBX extensions. */
676 if (n == 15)
677 tmp &= ~1;
6f970bd9 678
56aebc89
PB
679 if (n < 16) {
680 /* Core integer register. */
681 env->regs[n] = tmp;
682 return 4;
683 }
684 if (n < 24) { /* 16-23 */
685 /* FPA registers (ignored). */
686 if (gdb_has_xml)
687 return 0;
688 return 12;
689 }
690 switch (n) {
691 case 24:
692 /* FPA status register (ignored). */
693 if (gdb_has_xml)
694 return 0;
695 return 4;
696 case 25:
697 /* CPSR */
698 cpsr_write (env, tmp, 0xffffffff);
699 return 4;
700 }
701 /* Unknown register. */
702 return 0;
703}
6f970bd9 704
56aebc89 705#elif defined (TARGET_M68K)
6f970bd9 706
56aebc89 707#define NUM_CORE_REGS 18
6f970bd9 708
56aebc89 709#define GDB_CORE_XML "cf-core.xml"
6f970bd9 710
56aebc89
PB
711static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
712{
713 if (n < 8) {
714 /* D0-D7 */
715 GET_REG32(env->dregs[n]);
716 } else if (n < 16) {
717 /* A0-A7 */
718 GET_REG32(env->aregs[n - 8]);
719 } else {
720 switch (n) {
721 case 16: GET_REG32(env->sr);
722 case 17: GET_REG32(env->pc);
723 }
724 }
725 /* FP registers not included here because they vary between
726 ColdFire and m68k. Use XML bits for these. */
727 return 0;
728}
8e33c08c 729
56aebc89
PB
730static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
731{
732 uint32_t tmp;
8e33c08c 733
56aebc89 734 tmp = ldl_p(mem_buf);
8e33c08c 735
56aebc89
PB
736 if (n < 8) {
737 /* D0-D7 */
738 env->dregs[n] = tmp;
739 } else if (n < 8) {
740 /* A0-A7 */
741 env->aregs[n - 8] = tmp;
742 } else {
743 switch (n) {
744 case 16: env->sr = tmp; break;
745 case 17: env->pc = tmp; break;
746 default: return 0;
747 }
748 }
749 return 4;
750}
751#elif defined (TARGET_MIPS)
7ac256b8 752
56aebc89 753#define NUM_CORE_REGS 73
7ac256b8 754
56aebc89
PB
755static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
756{
757 if (n < 32) {
758 GET_REGL(env->active_tc.gpr[n]);
759 }
760 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
761 if (n >= 38 && n < 70) {
762 if (env->CP0_Status & (1 << CP0St_FR))
763 GET_REGL(env->active_fpu.fpr[n - 38].d);
764 else
765 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
766 }
767 switch (n) {
768 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
769 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
770 }
771 }
772 switch (n) {
773 case 32: GET_REGL((int32_t)env->CP0_Status);
774 case 33: GET_REGL(env->active_tc.LO[0]);
775 case 34: GET_REGL(env->active_tc.HI[0]);
776 case 35: GET_REGL(env->CP0_BadVAddr);
777 case 36: GET_REGL((int32_t)env->CP0_Cause);
778 case 37: GET_REGL(env->active_tc.PC);
779 case 72: GET_REGL(0); /* fp */
780 case 89: GET_REGL((int32_t)env->CP0_PRid);
781 }
782 if (n >= 73 && n <= 88) {
783 /* 16 embedded regs. */
784 GET_REGL(0);
785 }
6f970bd9 786
56aebc89 787 return 0;
6f970bd9
FB
788}
789
8e33c08c
TS
790/* convert MIPS rounding mode in FCR31 to IEEE library */
791static unsigned int ieee_rm[] =
792 {
793 float_round_nearest_even,
794 float_round_to_zero,
795 float_round_up,
796 float_round_down
797 };
798#define RESTORE_ROUNDING_MODE \
f01be154 799 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
8e33c08c 800
56aebc89 801static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
6f970bd9 802{
56aebc89 803 target_ulong tmp;
6f970bd9 804
56aebc89 805 tmp = ldtul_p(mem_buf);
6f970bd9 806
56aebc89
PB
807 if (n < 32) {
808 env->active_tc.gpr[n] = tmp;
809 return sizeof(target_ulong);
810 }
811 if (env->CP0_Config1 & (1 << CP0C1_FP)
812 && n >= 38 && n < 73) {
813 if (n < 70) {
7ac256b8 814 if (env->CP0_Status & (1 << CP0St_FR))
56aebc89 815 env->active_fpu.fpr[n - 38].d = tmp;
7ac256b8 816 else
56aebc89
PB
817 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
818 }
819 switch (n) {
820 case 70:
821 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
822 /* set rounding mode */
823 RESTORE_ROUNDING_MODE;
8e33c08c 824#ifndef CONFIG_SOFTFLOAT
56aebc89
PB
825 /* no floating point exception for native float */
826 SET_FP_ENABLE(env->active_fpu.fcr31, 0);
8e33c08c 827#endif
56aebc89
PB
828 break;
829 case 71: env->active_fpu.fcr0 = tmp; break;
830 }
831 return sizeof(target_ulong);
832 }
833 switch (n) {
834 case 32: env->CP0_Status = tmp; break;
835 case 33: env->active_tc.LO[0] = tmp; break;
836 case 34: env->active_tc.HI[0] = tmp; break;
837 case 35: env->CP0_BadVAddr = tmp; break;
838 case 36: env->CP0_Cause = tmp; break;
839 case 37: env->active_tc.PC = tmp; break;
840 case 72: /* fp, ignored */ break;
841 default:
842 if (n > 89)
843 return 0;
844 /* Other registers are readonly. Ignore writes. */
845 break;
846 }
847
848 return sizeof(target_ulong);
6f970bd9 849}
fdf9b3e8 850#elif defined (TARGET_SH4)
6ef99fc5
TS
851
852/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
56aebc89
PB
853/* FIXME: We should use XML for this. */
854
855#define NUM_CORE_REGS 59
6ef99fc5 856
56aebc89 857static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
fdf9b3e8 858{
56aebc89
PB
859 if (n < 8) {
860 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
861 GET_REGL(env->gregs[n + 16]);
862 } else {
863 GET_REGL(env->gregs[n]);
864 }
865 } else if (n < 16) {
866 GET_REGL(env->gregs[n - 8]);
867 } else if (n >= 25 && n < 41) {
868 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
869 } else if (n >= 43 && n < 51) {
870 GET_REGL(env->gregs[n - 43]);
871 } else if (n >= 51 && n < 59) {
872 GET_REGL(env->gregs[n - (51 - 16)]);
873 }
874 switch (n) {
875 case 16: GET_REGL(env->pc);
876 case 17: GET_REGL(env->pr);
877 case 18: GET_REGL(env->gbr);
878 case 19: GET_REGL(env->vbr);
879 case 20: GET_REGL(env->mach);
880 case 21: GET_REGL(env->macl);
881 case 22: GET_REGL(env->sr);
882 case 23: GET_REGL(env->fpul);
883 case 24: GET_REGL(env->fpscr);
884 case 41: GET_REGL(env->ssr);
885 case 42: GET_REGL(env->spc);
886 }
887
888 return 0;
fdf9b3e8
FB
889}
890
56aebc89 891static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
fdf9b3e8 892{
56aebc89
PB
893 uint32_t tmp;
894
895 tmp = ldl_p(mem_buf);
896
897 if (n < 8) {
898 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
899 env->gregs[n + 16] = tmp;
900 } else {
901 env->gregs[n] = tmp;
902 }
903 return 4;
904 } else if (n < 16) {
905 env->gregs[n - 8] = tmp;
906 return 4;
907 } else if (n >= 25 && n < 41) {
908 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
909 } else if (n >= 43 && n < 51) {
910 env->gregs[n - 43] = tmp;
911 return 4;
912 } else if (n >= 51 && n < 59) {
913 env->gregs[n - (51 - 16)] = tmp;
914 return 4;
915 }
916 switch (n) {
917 case 16: env->pc = tmp;
918 case 17: env->pr = tmp;
919 case 18: env->gbr = tmp;
920 case 19: env->vbr = tmp;
921 case 20: env->mach = tmp;
922 case 21: env->macl = tmp;
923 case 22: env->sr = tmp;
924 case 23: env->fpul = tmp;
925 case 24: env->fpscr = tmp;
926 case 41: env->ssr = tmp;
927 case 42: env->spc = tmp;
928 default: return 0;
929 }
930
931 return 4;
fdf9b3e8 932}
f1ccf904
TS
933#elif defined (TARGET_CRIS)
934
56aebc89
PB
935#define NUM_CORE_REGS 49
936
937static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
f1ccf904 938{
56aebc89
PB
939 uint8_t srs;
940
941 srs = env->pregs[PR_SRS];
942 if (n < 16) {
943 GET_REG32(env->regs[n]);
944 }
945
946 if (n >= 21 && n < 32) {
947 GET_REG32(env->pregs[n - 16]);
948 }
949 if (n >= 33 && n < 49) {
950 GET_REG32(env->sregs[srs][n - 33]);
951 }
952 switch (n) {
953 case 16: GET_REG8(env->pregs[0]);
954 case 17: GET_REG8(env->pregs[1]);
955 case 18: GET_REG32(env->pregs[2]);
956 case 19: GET_REG8(srs);
957 case 20: GET_REG16(env->pregs[4]);
958 case 32: GET_REG32(env->pc);
959 }
960
961 return 0;
f1ccf904 962}
56aebc89
PB
963
964static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
f1ccf904 965{
56aebc89
PB
966 uint32_t tmp;
967
968 if (n > 49)
969 return 0;
970
971 tmp = ldl_p(mem_buf);
972
973 if (n < 16) {
974 env->regs[n] = tmp;
975 }
976
d7b6967a
EI
977 if (n >= 21 && n < 32) {
978 env->pregs[n - 16] = tmp;
979 }
980
981 /* FIXME: Should support function regs be writable? */
56aebc89
PB
982 switch (n) {
983 case 16: return 1;
984 case 17: return 1;
d7b6967a 985 case 18: env->pregs[PR_PID] = tmp; break;
56aebc89
PB
986 case 19: return 1;
987 case 20: return 2;
988 case 32: env->pc = tmp; break;
989 }
990
991 return 4;
f1ccf904 992}
19bf517b
AJ
993#elif defined (TARGET_ALPHA)
994
995#define NUM_CORE_REGS 65
996
997static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
998{
999 if (n < 31) {
1000 GET_REGL(env->ir[n]);
1001 }
1002 else if (n == 31) {
1003 GET_REGL(0);
1004 }
1005 else if (n<63) {
1006 uint64_t val;
1007
1008 val=*((uint64_t *)&env->fir[n-32]);
1009 GET_REGL(val);
1010 }
1011 else if (n==63) {
1012 GET_REGL(env->fpcr);
1013 }
1014 else if (n==64) {
1015 GET_REGL(env->pc);
1016 }
1017 else {
1018 GET_REGL(0);
1019 }
1020
1021 return 0;
1022}
1023
1024static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1025{
1026 target_ulong tmp;
1027 tmp = ldtul_p(mem_buf);
1028
1029 if (n < 31) {
1030 env->ir[n] = tmp;
1031 }
1032
1033 if (n > 31 && n < 63) {
1034 env->fir[n - 32] = ldfl_p(mem_buf);
1035 }
1036
1037 if (n == 64 ) {
1038 env->pc=tmp;
1039 }
1040
1041 return 8;
1042}
56aebc89
PB
1043#else
1044
1045#define NUM_CORE_REGS 0
1046
1047static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
f1ccf904 1048{
56aebc89 1049 return 0;
f1ccf904
TS
1050}
1051
56aebc89 1052static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
f1ccf904 1053{
56aebc89
PB
1054 return 0;
1055}
f1ccf904 1056
56aebc89 1057#endif
f1ccf904 1058
56aebc89 1059static int num_g_regs = NUM_CORE_REGS;
f1ccf904 1060
56aebc89
PB
1061#ifdef GDB_CORE_XML
1062/* Encode data using the encoding for 'x' packets. */
1063static int memtox(char *buf, const char *mem, int len)
1064{
1065 char *p = buf;
1066 char c;
1067
1068 while (len--) {
1069 c = *(mem++);
1070 switch (c) {
1071 case '#': case '$': case '*': case '}':
1072 *(p++) = '}';
1073 *(p++) = c ^ 0x20;
1074 break;
1075 default:
1076 *(p++) = c;
1077 break;
1078 }
1079 }
1080 return p - buf;
1081}
f1ccf904 1082
3faf778e 1083static const char *get_feature_xml(const char *p, const char **newp)
56aebc89
PB
1084{
1085 extern const char *const xml_builtin[][2];
1086 size_t len;
1087 int i;
1088 const char *name;
1089 static char target_xml[1024];
1090
1091 len = 0;
1092 while (p[len] && p[len] != ':')
1093 len++;
1094 *newp = p + len;
1095
1096 name = NULL;
1097 if (strncmp(p, "target.xml", len) == 0) {
1098 /* Generate the XML description for this CPU. */
1099 if (!target_xml[0]) {
1100 GDBRegisterState *r;
1101
5b3715bf
BS
1102 snprintf(target_xml, sizeof(target_xml),
1103 "<?xml version=\"1.0\"?>"
1104 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1105 "<target>"
1106 "<xi:include href=\"%s\"/>",
1107 GDB_CORE_XML);
56aebc89 1108
880a7578 1109 for (r = first_cpu->gdb_regs; r; r = r->next) {
56aebc89
PB
1110 strcat(target_xml, "<xi:include href=\"");
1111 strcat(target_xml, r->xml);
1112 strcat(target_xml, "\"/>");
1113 }
1114 strcat(target_xml, "</target>");
1115 }
1116 return target_xml;
1117 }
1118 for (i = 0; ; i++) {
1119 name = xml_builtin[i][0];
1120 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1121 break;
1122 }
1123 return name ? xml_builtin[i][1] : NULL;
1124}
1125#endif
f1ccf904 1126
56aebc89
PB
1127static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1128{
1129 GDBRegisterState *r;
f1ccf904 1130
56aebc89
PB
1131 if (reg < NUM_CORE_REGS)
1132 return cpu_gdb_read_register(env, mem_buf, reg);
f1ccf904 1133
56aebc89
PB
1134 for (r = env->gdb_regs; r; r = r->next) {
1135 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1136 return r->get_reg(env, mem_buf, reg - r->base_reg);
1137 }
1138 }
1139 return 0;
f1ccf904
TS
1140}
1141
56aebc89 1142static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
f1ccf904 1143{
56aebc89 1144 GDBRegisterState *r;
f1ccf904 1145
56aebc89
PB
1146 if (reg < NUM_CORE_REGS)
1147 return cpu_gdb_write_register(env, mem_buf, reg);
1148
1149 for (r = env->gdb_regs; r; r = r->next) {
1150 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1151 return r->set_reg(env, mem_buf, reg - r->base_reg);
1152 }
1153 }
6da41eaf
FB
1154 return 0;
1155}
1156
56aebc89
PB
1157/* Register a supplemental set of CPU registers. If g_pos is nonzero it
1158 specifies the first register number and these registers are included in
1159 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1160 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1161 */
1162
1163void gdb_register_coprocessor(CPUState * env,
1164 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1165 int num_regs, const char *xml, int g_pos)
6da41eaf 1166{
56aebc89
PB
1167 GDBRegisterState *s;
1168 GDBRegisterState **p;
1169 static int last_reg = NUM_CORE_REGS;
1170
1171 s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1172 s->base_reg = last_reg;
1173 s->num_regs = num_regs;
1174 s->get_reg = get_reg;
1175 s->set_reg = set_reg;
1176 s->xml = xml;
1177 p = &env->gdb_regs;
1178 while (*p) {
1179 /* Check for duplicates. */
1180 if (strcmp((*p)->xml, xml) == 0)
1181 return;
1182 p = &(*p)->next;
1183 }
1184 /* Add to end of list. */
1185 last_reg += num_regs;
1186 *p = s;
1187 if (g_pos) {
1188 if (g_pos != s->base_reg) {
1189 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1190 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1191 } else {
1192 num_g_regs = last_reg;
1193 }
1194 }
6da41eaf
FB
1195}
1196
a1d1bb31
AL
1197/* GDB breakpoint/watchpoint types */
1198#define GDB_BREAKPOINT_SW 0
1199#define GDB_BREAKPOINT_HW 1
1200#define GDB_WATCHPOINT_WRITE 2
1201#define GDB_WATCHPOINT_READ 3
1202#define GDB_WATCHPOINT_ACCESS 4
1203
1204#ifndef CONFIG_USER_ONLY
1205static const int xlat_gdb_type[] = {
1206 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1207 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1208 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1209};
1210#endif
1211
880a7578 1212static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
a1d1bb31 1213{
880a7578
AL
1214 CPUState *env;
1215 int err = 0;
1216
a1d1bb31
AL
1217 switch (type) {
1218 case GDB_BREAKPOINT_SW:
1219 case GDB_BREAKPOINT_HW:
880a7578
AL
1220 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1221 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1222 if (err)
1223 break;
1224 }
1225 return err;
a1d1bb31
AL
1226#ifndef CONFIG_USER_ONLY
1227 case GDB_WATCHPOINT_WRITE:
1228 case GDB_WATCHPOINT_READ:
1229 case GDB_WATCHPOINT_ACCESS:
880a7578
AL
1230 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1231 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1232 NULL);
1233 if (err)
1234 break;
1235 }
1236 return err;
a1d1bb31
AL
1237#endif
1238 default:
1239 return -ENOSYS;
1240 }
1241}
1242
880a7578 1243static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
a1d1bb31 1244{
880a7578
AL
1245 CPUState *env;
1246 int err = 0;
1247
a1d1bb31
AL
1248 switch (type) {
1249 case GDB_BREAKPOINT_SW:
1250 case GDB_BREAKPOINT_HW:
880a7578
AL
1251 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1252 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1253 if (err)
1254 break;
1255 }
1256 return err;
a1d1bb31
AL
1257#ifndef CONFIG_USER_ONLY
1258 case GDB_WATCHPOINT_WRITE:
1259 case GDB_WATCHPOINT_READ:
1260 case GDB_WATCHPOINT_ACCESS:
880a7578
AL
1261 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1262 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1263 if (err)
1264 break;
1265 }
1266 return err;
a1d1bb31
AL
1267#endif
1268 default:
1269 return -ENOSYS;
1270 }
1271}
1272
880a7578 1273static void gdb_breakpoint_remove_all(void)
a1d1bb31 1274{
880a7578
AL
1275 CPUState *env;
1276
1277 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1278 cpu_breakpoint_remove_all(env, BP_GDB);
a1d1bb31 1279#ifndef CONFIG_USER_ONLY
880a7578 1280 cpu_watchpoint_remove_all(env, BP_GDB);
a1d1bb31 1281#endif
880a7578 1282 }
a1d1bb31
AL
1283}
1284
880a7578 1285static int gdb_handle_packet(GDBState *s, const char *line_buf)
b4608c04 1286{
880a7578 1287 CPUState *env;
b4608c04 1288 const char *p;
880a7578 1289 int ch, reg_size, type, res, thread;
56aebc89
PB
1290 char buf[MAX_PACKET_LENGTH];
1291 uint8_t mem_buf[MAX_PACKET_LENGTH];
1292 uint8_t *registers;
9d9754a3 1293 target_ulong addr, len;
3b46e624 1294
858693c6
FB
1295#ifdef DEBUG_GDB
1296 printf("command='%s'\n", line_buf);
1297#endif
1298 p = line_buf;
1299 ch = *p++;
1300 switch(ch) {
1301 case '?':
1fddef4b 1302 /* TODO: Make this return the correct value for user-mode. */
880a7578
AL
1303 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", SIGTRAP,
1304 s->c_cpu->cpu_index+1);
858693c6 1305 put_packet(s, buf);
7d03f82f
EI
1306 /* Remove all the breakpoints when this query is issued,
1307 * because gdb is doing and initial connect and the state
1308 * should be cleaned up.
1309 */
880a7578 1310 gdb_breakpoint_remove_all();
858693c6
FB
1311 break;
1312 case 'c':
1313 if (*p != '\0') {
9d9754a3 1314 addr = strtoull(p, (char **)&p, 16);
4c3a88a2 1315#if defined(TARGET_I386)
880a7578 1316 s->c_cpu->eip = addr;
5be1a8e0 1317#elif defined (TARGET_PPC)
880a7578 1318 s->c_cpu->nip = addr;
8d5f07fa 1319#elif defined (TARGET_SPARC)
880a7578
AL
1320 s->c_cpu->pc = addr;
1321 s->c_cpu->npc = addr + 4;
b5ff1b31 1322#elif defined (TARGET_ARM)
880a7578 1323 s->c_cpu->regs[15] = addr;
fdf9b3e8 1324#elif defined (TARGET_SH4)
880a7578 1325 s->c_cpu->pc = addr;
8fac5803 1326#elif defined (TARGET_MIPS)
880a7578 1327 s->c_cpu->active_tc.PC = addr;
f1ccf904 1328#elif defined (TARGET_CRIS)
880a7578 1329 s->c_cpu->pc = addr;
19bf517b
AJ
1330#elif defined (TARGET_ALPHA)
1331 s->c_cpu->pc = addr;
4c3a88a2 1332#endif
858693c6 1333 }
ba70a624 1334 gdb_continue(s);
41625033 1335 return RS_IDLE;
1f487ee9
EI
1336 case 'C':
1337 s->signal = strtoul(p, (char **)&p, 16);
1338 gdb_continue(s);
1339 return RS_IDLE;
7d03f82f
EI
1340 case 'k':
1341 /* Kill the target */
1342 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1343 exit(0);
1344 case 'D':
1345 /* Detach packet */
880a7578 1346 gdb_breakpoint_remove_all();
7d03f82f
EI
1347 gdb_continue(s);
1348 put_packet(s, "OK");
1349 break;
858693c6
FB
1350 case 's':
1351 if (*p != '\0') {
8fac5803 1352 addr = strtoull(p, (char **)&p, 16);
c33a346e 1353#if defined(TARGET_I386)
880a7578 1354 s->c_cpu->eip = addr;
5be1a8e0 1355#elif defined (TARGET_PPC)
880a7578 1356 s->c_cpu->nip = addr;
8d5f07fa 1357#elif defined (TARGET_SPARC)
880a7578
AL
1358 s->c_cpu->pc = addr;
1359 s->c_cpu->npc = addr + 4;
b5ff1b31 1360#elif defined (TARGET_ARM)
880a7578 1361 s->c_cpu->regs[15] = addr;
fdf9b3e8 1362#elif defined (TARGET_SH4)
880a7578 1363 s->c_cpu->pc = addr;
8fac5803 1364#elif defined (TARGET_MIPS)
880a7578 1365 s->c_cpu->active_tc.PC = addr;
f1ccf904 1366#elif defined (TARGET_CRIS)
880a7578 1367 s->c_cpu->pc = addr;
19bf517b
AJ
1368#elif defined (TARGET_ALPHA)
1369 s->c_cpu->pc = addr;
c33a346e 1370#endif
858693c6 1371 }
880a7578 1372 cpu_single_step(s->c_cpu, sstep_flags);
ba70a624 1373 gdb_continue(s);
41625033 1374 return RS_IDLE;
a2d1ebaf
PB
1375 case 'F':
1376 {
1377 target_ulong ret;
1378 target_ulong err;
1379
1380 ret = strtoull(p, (char **)&p, 16);
1381 if (*p == ',') {
1382 p++;
1383 err = strtoull(p, (char **)&p, 16);
1384 } else {
1385 err = 0;
1386 }
1387 if (*p == ',')
1388 p++;
1389 type = *p;
1390 if (gdb_current_syscall_cb)
880a7578 1391 gdb_current_syscall_cb(s->c_cpu, ret, err);
a2d1ebaf
PB
1392 if (type == 'C') {
1393 put_packet(s, "T02");
1394 } else {
ba70a624 1395 gdb_continue(s);
a2d1ebaf
PB
1396 }
1397 }
1398 break;
858693c6 1399 case 'g':
56aebc89
PB
1400 len = 0;
1401 for (addr = 0; addr < num_g_regs; addr++) {
880a7578 1402 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
56aebc89
PB
1403 len += reg_size;
1404 }
1405 memtohex(buf, mem_buf, len);
858693c6
FB
1406 put_packet(s, buf);
1407 break;
1408 case 'G':
56aebc89 1409 registers = mem_buf;
858693c6
FB
1410 len = strlen(p) / 2;
1411 hextomem((uint8_t *)registers, p, len);
56aebc89 1412 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
880a7578 1413 reg_size = gdb_write_register(s->g_cpu, registers, addr);
56aebc89
PB
1414 len -= reg_size;
1415 registers += reg_size;
1416 }
858693c6
FB
1417 put_packet(s, "OK");
1418 break;
1419 case 'm':
9d9754a3 1420 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
1421 if (*p == ',')
1422 p++;
9d9754a3 1423 len = strtoull(p, NULL, 16);
880a7578 1424 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
6f970bd9
FB
1425 put_packet (s, "E14");
1426 } else {
1427 memtohex(buf, mem_buf, len);
1428 put_packet(s, buf);
1429 }
858693c6
FB
1430 break;
1431 case 'M':
9d9754a3 1432 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
1433 if (*p == ',')
1434 p++;
9d9754a3 1435 len = strtoull(p, (char **)&p, 16);
b328f873 1436 if (*p == ':')
858693c6
FB
1437 p++;
1438 hextomem(mem_buf, p, len);
880a7578 1439 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
905f20b1 1440 put_packet(s, "E14");
858693c6
FB
1441 else
1442 put_packet(s, "OK");
1443 break;
56aebc89
PB
1444 case 'p':
1445 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1446 This works, but can be very slow. Anything new enough to
1447 understand XML also knows how to use this properly. */
1448 if (!gdb_has_xml)
1449 goto unknown_command;
1450 addr = strtoull(p, (char **)&p, 16);
880a7578 1451 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
56aebc89
PB
1452 if (reg_size) {
1453 memtohex(buf, mem_buf, reg_size);
1454 put_packet(s, buf);
1455 } else {
1456 put_packet(s, "E14");
1457 }
1458 break;
1459 case 'P':
1460 if (!gdb_has_xml)
1461 goto unknown_command;
1462 addr = strtoull(p, (char **)&p, 16);
1463 if (*p == '=')
1464 p++;
1465 reg_size = strlen(p) / 2;
1466 hextomem(mem_buf, p, reg_size);
880a7578 1467 gdb_write_register(s->g_cpu, mem_buf, addr);
56aebc89
PB
1468 put_packet(s, "OK");
1469 break;
858693c6 1470 case 'Z':
858693c6
FB
1471 case 'z':
1472 type = strtoul(p, (char **)&p, 16);
1473 if (*p == ',')
1474 p++;
9d9754a3 1475 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
1476 if (*p == ',')
1477 p++;
9d9754a3 1478 len = strtoull(p, (char **)&p, 16);
a1d1bb31 1479 if (ch == 'Z')
880a7578 1480 res = gdb_breakpoint_insert(addr, len, type);
a1d1bb31 1481 else
880a7578 1482 res = gdb_breakpoint_remove(addr, len, type);
a1d1bb31
AL
1483 if (res >= 0)
1484 put_packet(s, "OK");
1485 else if (res == -ENOSYS)
0f459d16 1486 put_packet(s, "");
a1d1bb31
AL
1487 else
1488 put_packet(s, "E22");
858693c6 1489 break;
880a7578
AL
1490 case 'H':
1491 type = *p++;
1492 thread = strtoull(p, (char **)&p, 16);
1493 if (thread == -1 || thread == 0) {
1494 put_packet(s, "OK");
1495 break;
1496 }
1497 for (env = first_cpu; env != NULL; env = env->next_cpu)
1498 if (env->cpu_index + 1 == thread)
1499 break;
1500 if (env == NULL) {
1501 put_packet(s, "E22");
1502 break;
1503 }
1504 switch (type) {
1505 case 'c':
1506 s->c_cpu = env;
1507 put_packet(s, "OK");
1508 break;
1509 case 'g':
1510 s->g_cpu = env;
1511 put_packet(s, "OK");
1512 break;
1513 default:
1514 put_packet(s, "E22");
1515 break;
1516 }
1517 break;
1518 case 'T':
1519 thread = strtoull(p, (char **)&p, 16);
1520#ifndef CONFIG_USER_ONLY
1521 if (thread > 0 && thread < smp_cpus + 1)
1522#else
1523 if (thread == 1)
1524#endif
1525 put_packet(s, "OK");
1526 else
1527 put_packet(s, "E22");
1528 break;
978efd6a 1529 case 'q':
60897d36
EI
1530 case 'Q':
1531 /* parse any 'q' packets here */
1532 if (!strcmp(p,"qemu.sstepbits")) {
1533 /* Query Breakpoint bit definitions */
363a37d5
BS
1534 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1535 SSTEP_ENABLE,
1536 SSTEP_NOIRQ,
1537 SSTEP_NOTIMER);
60897d36
EI
1538 put_packet(s, buf);
1539 break;
1540 } else if (strncmp(p,"qemu.sstep",10) == 0) {
1541 /* Display or change the sstep_flags */
1542 p += 10;
1543 if (*p != '=') {
1544 /* Display current setting */
363a37d5 1545 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
60897d36
EI
1546 put_packet(s, buf);
1547 break;
1548 }
1549 p++;
1550 type = strtoul(p, (char **)&p, 16);
1551 sstep_flags = type;
1552 put_packet(s, "OK");
1553 break;
880a7578
AL
1554 } else if (strcmp(p,"C") == 0) {
1555 /* "Current thread" remains vague in the spec, so always return
1556 * the first CPU (gdb returns the first thread). */
1557 put_packet(s, "QC1");
1558 break;
1559 } else if (strcmp(p,"fThreadInfo") == 0) {
1560 s->query_cpu = first_cpu;
1561 goto report_cpuinfo;
1562 } else if (strcmp(p,"sThreadInfo") == 0) {
1563 report_cpuinfo:
1564 if (s->query_cpu) {
1565 snprintf(buf, sizeof(buf), "m%x", s->query_cpu->cpu_index+1);
1566 put_packet(s, buf);
1567 s->query_cpu = s->query_cpu->next_cpu;
1568 } else
1569 put_packet(s, "l");
1570 break;
1571 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
1572 thread = strtoull(p+16, (char **)&p, 16);
1573 for (env = first_cpu; env != NULL; env = env->next_cpu)
1574 if (env->cpu_index + 1 == thread) {
1575 len = snprintf((char *)mem_buf, sizeof(mem_buf),
1576 "CPU#%d [%s]", env->cpu_index,
1577 env->halted ? "halted " : "running");
1578 memtohex(buf, mem_buf, len);
1579 put_packet(s, buf);
1580 break;
1581 }
1582 break;
60897d36
EI
1583 }
1584#ifdef CONFIG_LINUX_USER
1585 else if (strncmp(p, "Offsets", 7) == 0) {
880a7578 1586 TaskState *ts = s->c_cpu->opaque;
978efd6a 1587
363a37d5
BS
1588 snprintf(buf, sizeof(buf),
1589 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1590 ";Bss=" TARGET_ABI_FMT_lx,
1591 ts->info->code_offset,
1592 ts->info->data_offset,
1593 ts->info->data_offset);
978efd6a
PB
1594 put_packet(s, buf);
1595 break;
1596 }
978efd6a 1597#endif
56aebc89 1598 if (strncmp(p, "Supported", 9) == 0) {
5b3715bf 1599 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
56aebc89
PB
1600#ifdef GDB_CORE_XML
1601 strcat(buf, ";qXfer:features:read+");
1602#endif
1603 put_packet(s, buf);
1604 break;
1605 }
1606#ifdef GDB_CORE_XML
1607 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
1608 const char *xml;
1609 target_ulong total_len;
1610
1611 gdb_has_xml = 1;
1612 p += 19;
880a7578 1613 xml = get_feature_xml(p, &p);
56aebc89 1614 if (!xml) {
5b3715bf 1615 snprintf(buf, sizeof(buf), "E00");
56aebc89
PB
1616 put_packet(s, buf);
1617 break;
1618 }
1619
1620 if (*p == ':')
1621 p++;
1622 addr = strtoul(p, (char **)&p, 16);
1623 if (*p == ',')
1624 p++;
1625 len = strtoul(p, (char **)&p, 16);
1626
1627 total_len = strlen(xml);
1628 if (addr > total_len) {
5b3715bf 1629 snprintf(buf, sizeof(buf), "E00");
56aebc89
PB
1630 put_packet(s, buf);
1631 break;
1632 }
1633 if (len > (MAX_PACKET_LENGTH - 5) / 2)
1634 len = (MAX_PACKET_LENGTH - 5) / 2;
1635 if (len < total_len - addr) {
1636 buf[0] = 'm';
1637 len = memtox(buf + 1, xml + addr, len);
1638 } else {
1639 buf[0] = 'l';
1640 len = memtox(buf + 1, xml + addr, total_len - addr);
1641 }
1642 put_packet_binary(s, buf, len + 1);
1643 break;
1644 }
1645#endif
1646 /* Unrecognised 'q' command. */
1647 goto unknown_command;
1648
858693c6 1649 default:
56aebc89 1650 unknown_command:
858693c6
FB
1651 /* put empty packet */
1652 buf[0] = '\0';
1653 put_packet(s, buf);
1654 break;
1655 }
1656 return RS_IDLE;
1657}
1658
880a7578
AL
1659void gdb_set_stop_cpu(CPUState *env)
1660{
1661 gdbserver_state->c_cpu = env;
1662 gdbserver_state->g_cpu = env;
1663}
1664
1fddef4b 1665#ifndef CONFIG_USER_ONLY
858693c6
FB
1666static void gdb_vm_stopped(void *opaque, int reason)
1667{
880a7578
AL
1668 GDBState *s = gdbserver_state;
1669 CPUState *env = s->c_cpu;
858693c6 1670 char buf[256];
d6fc1b39 1671 const char *type;
858693c6
FB
1672 int ret;
1673
a2d1ebaf
PB
1674 if (s->state == RS_SYSCALL)
1675 return;
1676
858693c6 1677 /* disable single step if it was enable */
880a7578 1678 cpu_single_step(env, 0);
858693c6 1679
e80cfcfc 1680 if (reason == EXCP_DEBUG) {
880a7578
AL
1681 if (env->watchpoint_hit) {
1682 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
a1d1bb31 1683 case BP_MEM_READ:
d6fc1b39
AL
1684 type = "r";
1685 break;
a1d1bb31 1686 case BP_MEM_ACCESS:
d6fc1b39
AL
1687 type = "a";
1688 break;
1689 default:
1690 type = "";
1691 break;
1692 }
880a7578
AL
1693 snprintf(buf, sizeof(buf),
1694 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
1695 SIGTRAP, env->cpu_index+1, type,
1696 env->watchpoint_hit->vaddr);
6658ffb8 1697 put_packet(s, buf);
880a7578 1698 env->watchpoint_hit = NULL;
6658ffb8
PB
1699 return;
1700 }
880a7578 1701 tb_flush(env);
858693c6 1702 ret = SIGTRAP;
bbeb7b5c
FB
1703 } else if (reason == EXCP_INTERRUPT) {
1704 ret = SIGINT;
1705 } else {
858693c6 1706 ret = 0;
bbeb7b5c 1707 }
880a7578 1708 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, env->cpu_index+1);
858693c6
FB
1709 put_packet(s, buf);
1710}
1fddef4b 1711#endif
858693c6 1712
a2d1ebaf
PB
1713/* Send a gdb syscall request.
1714 This accepts limited printf-style format specifiers, specifically:
a87295e8
PB
1715 %x - target_ulong argument printed in hex.
1716 %lx - 64-bit argument printed in hex.
1717 %s - string pointer (target_ulong) and length (int) pair. */
7ccfb2eb 1718void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
a2d1ebaf
PB
1719{
1720 va_list va;
1721 char buf[256];
1722 char *p;
1723 target_ulong addr;
a87295e8 1724 uint64_t i64;
a2d1ebaf
PB
1725 GDBState *s;
1726
880a7578 1727 s = gdbserver_state;
a2d1ebaf
PB
1728 if (!s)
1729 return;
1730 gdb_current_syscall_cb = cb;
1731 s->state = RS_SYSCALL;
1732#ifndef CONFIG_USER_ONLY
1733 vm_stop(EXCP_DEBUG);
1734#endif
1735 s->state = RS_IDLE;
1736 va_start(va, fmt);
1737 p = buf;
1738 *(p++) = 'F';
1739 while (*fmt) {
1740 if (*fmt == '%') {
1741 fmt++;
1742 switch (*fmt++) {
1743 case 'x':
1744 addr = va_arg(va, target_ulong);
363a37d5 1745 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
a2d1ebaf 1746 break;
a87295e8
PB
1747 case 'l':
1748 if (*(fmt++) != 'x')
1749 goto bad_format;
1750 i64 = va_arg(va, uint64_t);
363a37d5 1751 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
a87295e8 1752 break;
a2d1ebaf
PB
1753 case 's':
1754 addr = va_arg(va, target_ulong);
363a37d5
BS
1755 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
1756 addr, va_arg(va, int));
a2d1ebaf
PB
1757 break;
1758 default:
a87295e8 1759 bad_format:
a2d1ebaf
PB
1760 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1761 fmt - 1);
1762 break;
1763 }
1764 } else {
1765 *(p++) = *(fmt++);
1766 }
1767 }
8a93e02a 1768 *p = 0;
a2d1ebaf
PB
1769 va_end(va);
1770 put_packet(s, buf);
1771#ifdef CONFIG_USER_ONLY
880a7578 1772 gdb_handlesig(s->c_cpu, 0);
a2d1ebaf 1773#else
880a7578 1774 cpu_interrupt(s->c_cpu, CPU_INTERRUPT_EXIT);
a2d1ebaf
PB
1775#endif
1776}
1777
6a00d601 1778static void gdb_read_byte(GDBState *s, int ch)
858693c6
FB
1779{
1780 int i, csum;
60fe76f3 1781 uint8_t reply;
858693c6 1782
1fddef4b 1783#ifndef CONFIG_USER_ONLY
4046d913
PB
1784 if (s->last_packet_len) {
1785 /* Waiting for a response to the last packet. If we see the start
1786 of a new command then abandon the previous response. */
1787 if (ch == '-') {
1788#ifdef DEBUG_GDB
1789 printf("Got NACK, retransmitting\n");
1790#endif
ffe8ab83 1791 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
4046d913
PB
1792 }
1793#ifdef DEBUG_GDB
1794 else if (ch == '+')
1795 printf("Got ACK\n");
1796 else
1797 printf("Got '%c' when expecting ACK/NACK\n", ch);
1798#endif
1799 if (ch == '+' || ch == '$')
1800 s->last_packet_len = 0;
1801 if (ch != '$')
1802 return;
1803 }
858693c6
FB
1804 if (vm_running) {
1805 /* when the CPU is running, we cannot do anything except stop
1806 it when receiving a char */
1807 vm_stop(EXCP_INTERRUPT);
5fafdf24 1808 } else
1fddef4b 1809#endif
41625033 1810 {
858693c6
FB
1811 switch(s->state) {
1812 case RS_IDLE:
1813 if (ch == '$') {
1814 s->line_buf_index = 0;
1815 s->state = RS_GETLINE;
c33a346e 1816 }
b4608c04 1817 break;
858693c6
FB
1818 case RS_GETLINE:
1819 if (ch == '#') {
1820 s->state = RS_CHKSUM1;
1821 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1822 s->state = RS_IDLE;
4c3a88a2 1823 } else {
858693c6 1824 s->line_buf[s->line_buf_index++] = ch;
4c3a88a2
FB
1825 }
1826 break;
858693c6
FB
1827 case RS_CHKSUM1:
1828 s->line_buf[s->line_buf_index] = '\0';
1829 s->line_csum = fromhex(ch) << 4;
1830 s->state = RS_CHKSUM2;
1831 break;
1832 case RS_CHKSUM2:
1833 s->line_csum |= fromhex(ch);
1834 csum = 0;
1835 for(i = 0; i < s->line_buf_index; i++) {
1836 csum += s->line_buf[i];
1837 }
1838 if (s->line_csum != (csum & 0xff)) {
60fe76f3
TS
1839 reply = '-';
1840 put_buffer(s, &reply, 1);
858693c6 1841 s->state = RS_IDLE;
4c3a88a2 1842 } else {
60fe76f3
TS
1843 reply = '+';
1844 put_buffer(s, &reply, 1);
880a7578 1845 s->state = gdb_handle_packet(s, s->line_buf);
4c3a88a2
FB
1846 }
1847 break;
a2d1ebaf
PB
1848 default:
1849 abort();
858693c6
FB
1850 }
1851 }
1852}
1853
1fddef4b
FB
1854#ifdef CONFIG_USER_ONLY
1855int
1856gdb_handlesig (CPUState *env, int sig)
1857{
1858 GDBState *s;
1859 char buf[256];
1860 int n;
1861
880a7578 1862 s = gdbserver_state;
1f487ee9
EI
1863 if (gdbserver_fd < 0 || s->fd < 0)
1864 return sig;
1fddef4b
FB
1865
1866 /* disable single step if it was enabled */
1867 cpu_single_step(env, 0);
1868 tb_flush(env);
1869
1870 if (sig != 0)
1871 {
1872 snprintf(buf, sizeof(buf), "S%02x", sig);
1873 put_packet(s, buf);
1874 }
1f487ee9
EI
1875 /* put_packet() might have detected that the peer terminated the
1876 connection. */
1877 if (s->fd < 0)
1878 return sig;
1fddef4b 1879
1fddef4b
FB
1880 sig = 0;
1881 s->state = RS_IDLE;
41625033
FB
1882 s->running_state = 0;
1883 while (s->running_state == 0) {
1fddef4b
FB
1884 n = read (s->fd, buf, 256);
1885 if (n > 0)
1886 {
1887 int i;
1888
1889 for (i = 0; i < n; i++)
6a00d601 1890 gdb_read_byte (s, buf[i]);
1fddef4b
FB
1891 }
1892 else if (n == 0 || errno != EAGAIN)
1893 {
1894 /* XXX: Connection closed. Should probably wait for annother
1895 connection before continuing. */
1896 return sig;
1897 }
41625033 1898 }
1f487ee9
EI
1899 sig = s->signal;
1900 s->signal = 0;
1fddef4b
FB
1901 return sig;
1902}
e9009676
FB
1903
1904/* Tell the remote gdb that the process has exited. */
1905void gdb_exit(CPUState *env, int code)
1906{
1907 GDBState *s;
1908 char buf[4];
1909
880a7578 1910 s = gdbserver_state;
1f487ee9
EI
1911 if (gdbserver_fd < 0 || s->fd < 0)
1912 return;
e9009676
FB
1913
1914 snprintf(buf, sizeof(buf), "W%02x", code);
1915 put_packet(s, buf);
1916}
1917
1fddef4b 1918
880a7578 1919static void gdb_accept(void)
858693c6
FB
1920{
1921 GDBState *s;
1922 struct sockaddr_in sockaddr;
1923 socklen_t len;
1924 int val, fd;
1925
1926 for(;;) {
1927 len = sizeof(sockaddr);
1928 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1929 if (fd < 0 && errno != EINTR) {
1930 perror("accept");
1931 return;
1932 } else if (fd >= 0) {
b4608c04
FB
1933 break;
1934 }
1935 }
858693c6
FB
1936
1937 /* set short latency */
1938 val = 1;
8f447cc7 1939 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
3b46e624 1940
880a7578
AL
1941 s = qemu_mallocz(sizeof(GDBState));
1942 if (!s) {
1943 errno = ENOMEM;
1944 perror("accept");
1945 return;
1946 }
1947
1fddef4b 1948 memset (s, 0, sizeof (GDBState));
880a7578
AL
1949 s->c_cpu = first_cpu;
1950 s->g_cpu = first_cpu;
858693c6 1951 s->fd = fd;
56aebc89 1952 gdb_has_xml = 0;
858693c6 1953
880a7578 1954 gdbserver_state = s;
a2d1ebaf 1955
858693c6 1956 fcntl(fd, F_SETFL, O_NONBLOCK);
858693c6
FB
1957}
1958
1959static int gdbserver_open(int port)
1960{
1961 struct sockaddr_in sockaddr;
1962 int fd, val, ret;
1963
1964 fd = socket(PF_INET, SOCK_STREAM, 0);
1965 if (fd < 0) {
1966 perror("socket");
1967 return -1;
1968 }
1969
1970 /* allow fast reuse */
1971 val = 1;
8f447cc7 1972 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
858693c6
FB
1973
1974 sockaddr.sin_family = AF_INET;
1975 sockaddr.sin_port = htons(port);
1976 sockaddr.sin_addr.s_addr = 0;
1977 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1978 if (ret < 0) {
1979 perror("bind");
1980 return -1;
1981 }
1982 ret = listen(fd, 0);
1983 if (ret < 0) {
1984 perror("listen");
1985 return -1;
1986 }
858693c6
FB
1987 return fd;
1988}
1989
1990int gdbserver_start(int port)
1991{
1992 gdbserver_fd = gdbserver_open(port);
1993 if (gdbserver_fd < 0)
1994 return -1;
1995 /* accept connections */
880a7578 1996 gdb_accept();
4046d913
PB
1997 return 0;
1998}
2b1319c8
AJ
1999
2000/* Disable gdb stub for child processes. */
2001void gdbserver_fork(CPUState *env)
2002{
2003 GDBState *s = gdbserver_state;
2004 if (s->fd < 0)
2005 return;
2006 close(s->fd);
2007 s->fd = -1;
2008 cpu_breakpoint_remove_all(env, BP_GDB);
2009 cpu_watchpoint_remove_all(env, BP_GDB);
2010}
1fddef4b 2011#else
aa1f17c1 2012static int gdb_chr_can_receive(void *opaque)
4046d913 2013{
56aebc89
PB
2014 /* We can handle an arbitrarily large amount of data.
2015 Pick the maximum packet size, which is as good as anything. */
2016 return MAX_PACKET_LENGTH;
4046d913
PB
2017}
2018
aa1f17c1 2019static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
4046d913 2020{
4046d913
PB
2021 int i;
2022
2023 for (i = 0; i < size; i++) {
880a7578 2024 gdb_read_byte(gdbserver_state, buf[i]);
4046d913
PB
2025 }
2026}
2027
2028static void gdb_chr_event(void *opaque, int event)
2029{
2030 switch (event) {
2031 case CHR_EVENT_RESET:
2032 vm_stop(EXCP_INTERRUPT);
56aebc89 2033 gdb_has_xml = 0;
4046d913
PB
2034 break;
2035 default:
2036 break;
2037 }
2038}
2039
cfc3475a 2040int gdbserver_start(const char *port)
4046d913
PB
2041{
2042 GDBState *s;
cfc3475a
PB
2043 char gdbstub_port_name[128];
2044 int port_num;
2045 char *p;
2046 CharDriverState *chr;
2047
2048 if (!port || !*port)
2049 return -1;
4046d913 2050
cfc3475a
PB
2051 port_num = strtol(port, &p, 10);
2052 if (*p == 0) {
2053 /* A numeric value is interpreted as a port number. */
2054 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
2055 "tcp::%d,nowait,nodelay,server", port_num);
2056 port = gdbstub_port_name;
2057 }
2058
5ccfae10 2059 chr = qemu_chr_open("gdb", port);
4046d913
PB
2060 if (!chr)
2061 return -1;
2062
2063 s = qemu_mallocz(sizeof(GDBState));
2064 if (!s) {
2065 return -1;
2066 }
880a7578
AL
2067 s->c_cpu = first_cpu;
2068 s->g_cpu = first_cpu;
4046d913 2069 s->chr = chr;
880a7578 2070 gdbserver_state = s;
aa1f17c1 2071 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
880a7578
AL
2072 gdb_chr_event, NULL);
2073 qemu_add_vm_stop_handler(gdb_vm_stopped, NULL);
b4608c04
FB
2074 return 0;
2075}
4046d913 2076#endif