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f5d8c8cd SZ |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
12b16722 | 29 | #include "qemu/osdep.h" |
da34e65c | 30 | #include "qapi/error.h" |
f5d8c8cd SZ |
31 | #include "qemu/bitmap.h" |
32 | #include "trace.h" | |
2e5b09fd | 33 | #include "hw/core/cpu.h" |
fcf5ef2a | 34 | #include "target/arm/cpu.h" |
f5d8c8cd SZ |
35 | #include "hw/acpi/acpi-defs.h" |
36 | #include "hw/acpi/acpi.h" | |
37 | #include "hw/nvram/fw_cfg.h" | |
38 | #include "hw/acpi/bios-linker-loader.h" | |
f5d8c8cd | 39 | #include "hw/acpi/aml-build.h" |
82f76c67 | 40 | #include "hw/acpi/utils.h" |
48cefd94 | 41 | #include "hw/acpi/pci.h" |
cff51ac9 SK |
42 | #include "hw/acpi/memory_hotplug.h" |
43 | #include "hw/acpi/generic_event_device.h" | |
80bde693 | 44 | #include "hw/acpi/tpm.h" |
84344884 | 45 | #include "hw/pci/pcie_host.h" |
d4e5de1a | 46 | #include "hw/pci/pci.h" |
06d2dd49 | 47 | #include "hw/pci-host/gpex.h" |
d05fdab4 | 48 | #include "hw/arm/virt.h" |
b5a60bee | 49 | #include "hw/mem/nvdimm.h" |
5ab540e9 | 50 | #include "hw/platform-bus.h" |
2b302e1e | 51 | #include "sysemu/numa.h" |
71e8a915 | 52 | #include "sysemu/reset.h" |
80bde693 | 53 | #include "sysemu/tpm.h" |
13e5c54d | 54 | #include "kvm_arm.h" |
d6454270 | 55 | #include "migration/vmstate.h" |
aa16508f | 56 | #include "hw/acpi/ghes.h" |
f5d8c8cd | 57 | |
dfccd8cf SZ |
58 | #define ARM_SPI_BASE 32 |
59 | ||
451b1570 YM |
60 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
61 | ||
9cd07db9 | 62 | static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) |
dfccd8cf | 63 | { |
9cd07db9 | 64 | MachineState *ms = MACHINE(vms); |
dfccd8cf SZ |
65 | uint16_t i; |
66 | ||
9cd07db9 | 67 | for (i = 0; i < ms->smp.cpus; i++) { |
f460be43 | 68 | Aml *dev = aml_device("C%.03X", i); |
dfccd8cf SZ |
69 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); |
70 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
71 | aml_append(scope, dev); | |
72 | } | |
73 | } | |
74 | ||
75 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
45fcf539 | 76 | uint32_t uart_irq) |
dfccd8cf SZ |
77 | { |
78 | Aml *dev = aml_device("COM0"); | |
79 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
80 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
81 | ||
82 | Aml *crs = aml_resource_template(); | |
83 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
84 | uart_memmap->size, AML_READ_WRITE)); | |
85 | aml_append(crs, | |
86 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 87 | AML_EXCLUSIVE, &uart_irq, 1)); |
dfccd8cf | 88 | aml_append(dev, aml_name_decl("_CRS", crs)); |
f264d51d | 89 | |
dfccd8cf SZ |
90 | aml_append(scope, dev); |
91 | } | |
92 | ||
70bee80d GS |
93 | static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) |
94 | { | |
95 | Aml *dev = aml_device("FWCF"); | |
96 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); | |
97 | /* device present, functioning, decoding, not shown in UI */ | |
98 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
3b5c492b | 99 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
70bee80d GS |
100 | |
101 | Aml *crs = aml_resource_template(); | |
102 | aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, | |
103 | fw_cfg_memmap->size, AML_READ_WRITE)); | |
104 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
105 | aml_append(scope, dev); | |
106 | } | |
107 | ||
dfccd8cf SZ |
108 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) |
109 | { | |
110 | Aml *dev, *crs; | |
111 | hwaddr base = flash_memmap->base; | |
cd37aaf8 | 112 | hwaddr size = flash_memmap->size / 2; |
dfccd8cf SZ |
113 | |
114 | dev = aml_device("FLS0"); | |
115 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
116 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
117 | ||
118 | crs = aml_resource_template(); | |
119 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
120 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
121 | aml_append(scope, dev); | |
122 | ||
123 | dev = aml_device("FLS1"); | |
124 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
125 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
126 | crs = aml_resource_template(); | |
127 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
128 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
129 | aml_append(scope, dev); | |
130 | } | |
131 | ||
132 | static void acpi_dsdt_add_virtio(Aml *scope, | |
133 | const MemMapEntry *virtio_mmio_memmap, | |
45fcf539 | 134 | uint32_t mmio_irq, int num) |
dfccd8cf SZ |
135 | { |
136 | hwaddr base = virtio_mmio_memmap->base; | |
137 | hwaddr size = virtio_mmio_memmap->size; | |
dfccd8cf SZ |
138 | int i; |
139 | ||
140 | for (i = 0; i < num; i++) { | |
45fcf539 | 141 | uint32_t irq = mmio_irq + i; |
dfccd8cf SZ |
142 | Aml *dev = aml_device("VR%02u", i); |
143 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); | |
144 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
76266d99 | 145 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
dfccd8cf SZ |
146 | |
147 | Aml *crs = aml_resource_template(); | |
148 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
149 | aml_append(crs, | |
150 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 151 | AML_EXCLUSIVE, &irq, 1)); |
dfccd8cf SZ |
152 | aml_append(dev, aml_name_decl("_CRS", crs)); |
153 | aml_append(scope, dev); | |
154 | base += size; | |
155 | } | |
156 | } | |
157 | ||
45fcf539 | 158 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, |
6f9765fb YM |
159 | uint32_t irq, bool use_highmem, bool highmem_ecam, |
160 | VirtMachineState *vms) | |
d4e5de1a | 161 | { |
601d626d | 162 | int ecam_id = VIRT_ECAM_ID(highmem_ecam); |
06d2dd49 GH |
163 | struct GPEXConfig cfg = { |
164 | .mmio32 = memmap[VIRT_PCIE_MMIO], | |
165 | .pio = memmap[VIRT_PCIE_PIO], | |
166 | .ecam = memmap[ecam_id], | |
167 | .irq = irq, | |
6f9765fb | 168 | .bus = vms->bus, |
06d2dd49 | 169 | }; |
d4e5de1a | 170 | |
5125f9cd | 171 | if (use_highmem) { |
06d2dd49 | 172 | cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; |
5125f9cd PF |
173 | } |
174 | ||
06d2dd49 | 175 | acpi_dsdt_add_gpex(scope, &cfg); |
d4e5de1a SZ |
176 | } |
177 | ||
aeb1a36d SZ |
178 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, |
179 | uint32_t gpio_irq) | |
180 | { | |
181 | Aml *dev = aml_device("GPO0"); | |
182 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
aeb1a36d SZ |
183 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
184 | ||
185 | Aml *crs = aml_resource_template(); | |
186 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
187 | AML_READ_WRITE)); | |
188 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
189 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
190 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
c1a158b7 SZ |
191 | |
192 | Aml *aei = aml_resource_template(); | |
193 | /* Pin 3 for power button */ | |
194 | const uint32_t pin_list[1] = {3}; | |
195 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
196 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
197 | "GPO0", NULL, 0)); | |
198 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
199 | ||
200 | /* _E03 is handle for power button */ | |
201 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
202 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
203 | aml_int(0x80))); | |
204 | aml_append(dev, method); | |
aeb1a36d SZ |
205 | aml_append(scope, dev); |
206 | } | |
207 | ||
5ab540e9 EA |
208 | static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) |
209 | { | |
210 | PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); | |
211 | hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; | |
212 | SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); | |
213 | MemoryRegion *sbdev_mr; | |
214 | hwaddr tpm_base; | |
215 | ||
216 | if (!sbdev) { | |
217 | return; | |
218 | } | |
219 | ||
220 | tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
221 | assert(tpm_base != -1); | |
222 | ||
223 | tpm_base += pbus_base; | |
224 | ||
225 | sbdev_mr = sysbus_mmio_get_region(sbdev, 0); | |
226 | ||
227 | Aml *dev = aml_device("TPM0"); | |
228 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
229 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
230 | ||
231 | Aml *crs = aml_resource_template(); | |
232 | aml_append(crs, | |
233 | aml_memory32_fixed(tpm_base, | |
234 | (uint32_t)memory_region_size(sbdev_mr), | |
235 | AML_READ_WRITE)); | |
236 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
237 | aml_append(scope, dev); | |
238 | } | |
239 | ||
e78f1222 | 240 | static void |
a703b4f6 | 241 | build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
e78f1222 | 242 | { |
a703b4f6 | 243 | int nb_nodes, iort_start = table_data->len; |
e78f1222 PM |
244 | AcpiIortIdMapping *idmap; |
245 | AcpiIortItsGroup *its; | |
246 | AcpiIortTable *iort; | |
a703b4f6 | 247 | AcpiIortSmmu3 *smmu; |
6e3e7239 | 248 | size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; |
e78f1222 PM |
249 | AcpiIortRC *rc; |
250 | ||
251 | iort = acpi_data_push(table_data, sizeof(*iort)); | |
252 | ||
a703b4f6 PM |
253 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
254 | nb_nodes = 3; /* RC, ITS, SMMUv3 */ | |
255 | } else { | |
256 | nb_nodes = 2; /* RC, ITS */ | |
257 | } | |
258 | ||
e78f1222 | 259 | iort_length = sizeof(*iort); |
a703b4f6 | 260 | iort->node_count = cpu_to_le32(nb_nodes); |
6e3e7239 SZ |
261 | /* |
262 | * Use a copy in case table_data->data moves during acpi_data_push | |
263 | * operations. | |
264 | */ | |
265 | iort_node_offset = sizeof(*iort); | |
266 | iort->node_offset = cpu_to_le32(iort_node_offset); | |
e78f1222 PM |
267 | |
268 | /* ITS group node */ | |
269 | node_size = sizeof(*its) + sizeof(uint32_t); | |
270 | iort_length += node_size; | |
271 | its = acpi_data_push(table_data, node_size); | |
272 | ||
273 | its->type = ACPI_IORT_NODE_ITS_GROUP; | |
274 | its->length = cpu_to_le16(node_size); | |
275 | its->its_count = cpu_to_le32(1); | |
276 | its->identifiers[0] = 0; /* MADT translation_id */ | |
277 | ||
a703b4f6 | 278 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
41c4fb94 | 279 | int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; |
a703b4f6 PM |
280 | |
281 | /* SMMUv3 node */ | |
6e3e7239 | 282 | smmu_offset = iort_node_offset + node_size; |
a703b4f6 PM |
283 | node_size = sizeof(*smmu) + sizeof(*idmap); |
284 | iort_length += node_size; | |
285 | smmu = acpi_data_push(table_data, node_size); | |
286 | ||
287 | smmu->type = ACPI_IORT_NODE_SMMU_V3; | |
288 | smmu->length = cpu_to_le16(node_size); | |
289 | smmu->mapping_count = cpu_to_le32(1); | |
290 | smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); | |
291 | smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); | |
29bbccc2 | 292 | smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); |
a703b4f6 PM |
293 | smmu->event_gsiv = cpu_to_le32(irq); |
294 | smmu->pri_gsiv = cpu_to_le32(irq + 1); | |
295 | smmu->gerr_gsiv = cpu_to_le32(irq + 2); | |
296 | smmu->sync_gsiv = cpu_to_le32(irq + 3); | |
297 | ||
298 | /* Identity RID mapping covering the whole input RID range */ | |
299 | idmap = &smmu->id_mapping_array[0]; | |
300 | idmap->input_base = 0; | |
301 | idmap->id_count = cpu_to_le32(0xFFFF); | |
302 | idmap->output_base = 0; | |
303 | /* output IORT node is the ITS group node (the first node) */ | |
6e3e7239 | 304 | idmap->output_reference = cpu_to_le32(iort_node_offset); |
a703b4f6 PM |
305 | } |
306 | ||
e78f1222 PM |
307 | /* Root Complex Node */ |
308 | node_size = sizeof(*rc) + sizeof(*idmap); | |
309 | iort_length += node_size; | |
310 | rc = acpi_data_push(table_data, node_size); | |
311 | ||
312 | rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; | |
313 | rc->length = cpu_to_le16(node_size); | |
314 | rc->mapping_count = cpu_to_le32(1); | |
315 | rc->mapping_offset = cpu_to_le32(sizeof(*rc)); | |
316 | ||
317 | /* fully coherent device */ | |
318 | rc->memory_properties.cache_coherency = cpu_to_le32(1); | |
319 | rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ | |
320 | rc->pci_segment_number = 0; /* MCFG pci_segment */ | |
321 | ||
322 | /* Identity RID mapping covering the whole input RID range */ | |
323 | idmap = &rc->id_mapping_array[0]; | |
324 | idmap->input_base = 0; | |
325 | idmap->id_count = cpu_to_le32(0xFFFF); | |
326 | idmap->output_base = 0; | |
a703b4f6 PM |
327 | |
328 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { | |
329 | /* output IORT node is the smmuv3 node */ | |
330 | idmap->output_reference = cpu_to_le32(smmu_offset); | |
331 | } else { | |
332 | /* output IORT node is the ITS group node (the first node) */ | |
6e3e7239 | 333 | idmap->output_reference = cpu_to_le32(iort_node_offset); |
a703b4f6 | 334 | } |
e78f1222 | 335 | |
6e3e7239 SZ |
336 | /* |
337 | * Update the pointer address in case table_data->data moves during above | |
338 | * acpi_data_push operations. | |
339 | */ | |
340 | iort = (AcpiIortTable *)(table_data->data + iort_start); | |
e78f1222 PM |
341 | iort->length = cpu_to_le32(iort_length); |
342 | ||
343 | build_header(linker, table_data, (void *)(table_data->data + iort_start), | |
602b4582 MP |
344 | "IORT", table_data->len - iort_start, 0, vms->oem_id, |
345 | vms->oem_table_id); | |
e78f1222 PM |
346 | } |
347 | ||
f264d51d | 348 | static void |
da4f09a7 | 349 | build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
f264d51d AJ |
350 | { |
351 | AcpiSerialPortConsoleRedirection *spcr; | |
da4f09a7 AJ |
352 | const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART]; |
353 | int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE; | |
4d027afe | 354 | int spcr_start = table_data->len; |
f264d51d AJ |
355 | |
356 | spcr = acpi_data_push(table_data, sizeof(*spcr)); | |
357 | ||
358 | spcr->interface_type = 0x3; /* ARM PL011 UART */ | |
359 | ||
360 | spcr->base_address.space_id = AML_SYSTEM_MEMORY; | |
361 | spcr->base_address.bit_width = 8; | |
362 | spcr->base_address.bit_offset = 0; | |
363 | spcr->base_address.access_width = 1; | |
364 | spcr->base_address.address = cpu_to_le64(uart_memmap->base); | |
365 | ||
366 | spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */ | |
367 | spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */ | |
368 | ||
369 | spcr->baud = 3; /* Baud Rate: 3 = 9600 */ | |
370 | spcr->parity = 0; /* No Parity */ | |
371 | spcr->stopbits = 1; /* 1 Stop bit */ | |
372 | spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */ | |
373 | spcr->term_type = 0; /* Terminal Type: 0 = VT100 */ | |
374 | ||
375 | spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */ | |
376 | spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */ | |
377 | ||
4d027afe | 378 | build_header(linker, table_data, (void *)(table_data->data + spcr_start), |
602b4582 MP |
379 | "SPCR", table_data->len - spcr_start, 2, vms->oem_id, |
380 | vms->oem_table_id); | |
f264d51d AJ |
381 | } |
382 | ||
2b302e1e | 383 | static void |
da4f09a7 | 384 | build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
2b302e1e SZ |
385 | { |
386 | AcpiSystemResourceAffinityTable *srat; | |
387 | AcpiSratProcessorGiccAffinity *core; | |
388 | AcpiSratMemoryAffinity *numamem; | |
4ccf5826 | 389 | int i, srat_start; |
2b302e1e | 390 | uint64_t mem_base; |
4ccf5826 | 391 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
aa570207 TX |
392 | MachineState *ms = MACHINE(vms); |
393 | const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); | |
2b302e1e SZ |
394 | |
395 | srat_start = table_data->len; | |
396 | srat = acpi_data_push(table_data, sizeof(*srat)); | |
397 | srat->reserved1 = cpu_to_le32(1); | |
398 | ||
4ccf5826 | 399 | for (i = 0; i < cpu_list->len; ++i) { |
2b302e1e SZ |
400 | core = acpi_data_push(table_data, sizeof(*core)); |
401 | core->type = ACPI_SRAT_PROCESSOR_GICC; | |
402 | core->length = sizeof(*core); | |
d41f3e75 | 403 | core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id); |
2b302e1e SZ |
404 | core->acpi_processor_uid = cpu_to_le32(i); |
405 | core->flags = cpu_to_le32(1); | |
406 | } | |
2b302e1e | 407 | |
da4f09a7 | 408 | mem_base = vms->memmap[VIRT_MEM].base; |
aa570207 | 409 | for (i = 0; i < ms->numa_state->num_nodes; ++i) { |
7e721e7b | 410 | if (ms->numa_state->nodes[i].node_mem > 0) { |
66c353ce | 411 | numamem = acpi_data_push(table_data, sizeof(*numamem)); |
7e721e7b TX |
412 | build_srat_memory(numamem, mem_base, |
413 | ms->numa_state->nodes[i].node_mem, i, | |
66c353ce | 414 | MEM_AFFINITY_ENABLED); |
7e721e7b | 415 | mem_base += ms->numa_state->nodes[i].node_mem; |
66c353ce | 416 | } |
2b302e1e SZ |
417 | } |
418 | ||
c3b0cf6e VV |
419 | if (ms->nvdimms_state->is_enabled) { |
420 | nvdimm_build_srat(table_data); | |
421 | } | |
422 | ||
442da7dc SK |
423 | if (ms->device_memory) { |
424 | numamem = acpi_data_push(table_data, sizeof *numamem); | |
425 | build_srat_memory(numamem, ms->device_memory->base, | |
426 | memory_region_size(&ms->device_memory->mr), | |
427 | ms->numa_state->num_nodes - 1, | |
428 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
429 | } | |
430 | ||
4d027afe | 431 | build_header(linker, table_data, (void *)(table_data->data + srat_start), |
602b4582 MP |
432 | "SRAT", table_data->len - srat_start, 3, vms->oem_id, |
433 | vms->oem_table_id); | |
2b302e1e SZ |
434 | } |
435 | ||
ee246400 SZ |
436 | /* GTDT */ |
437 | static void | |
8dd845d3 | 438 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
ee246400 | 439 | { |
8dd845d3 | 440 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
ee246400 SZ |
441 | int gtdt_start = table_data->len; |
442 | AcpiGenericTimerTable *gtdt; | |
8dd845d3 AJ |
443 | uint32_t irqflags; |
444 | ||
445 | if (vmc->claim_edge_triggered_timers) { | |
446 | irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; | |
447 | } else { | |
448 | irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; | |
449 | } | |
ee246400 SZ |
450 | |
451 | gtdt = acpi_data_push(table_data, sizeof *gtdt); | |
452 | /* The interrupt values are the same with the device tree when adding 16 */ | |
330afe05 | 453 | gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); |
8dd845d3 | 454 | gtdt->secure_el1_flags = cpu_to_le32(irqflags); |
ee246400 | 455 | |
330afe05 | 456 | gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); |
8dd845d3 | 457 | gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | |
aca4bbf4 | 458 | ACPI_GTDT_CAP_ALWAYS_ON); |
ee246400 | 459 | |
330afe05 | 460 | gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); |
8dd845d3 | 461 | gtdt->virtual_timer_flags = cpu_to_le32(irqflags); |
ee246400 | 462 | |
330afe05 | 463 | gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); |
8dd845d3 | 464 | gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); |
ee246400 SZ |
465 | |
466 | build_header(linker, table_data, | |
467 | (void *)(table_data->data + gtdt_start), "GTDT", | |
602b4582 MP |
468 | table_data->len - gtdt_start, 2, vms->oem_id, |
469 | vms->oem_table_id); | |
ee246400 SZ |
470 | } |
471 | ||
982d06c5 SZ |
472 | /* MADT */ |
473 | static void | |
da4f09a7 | 474 | build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
982d06c5 | 475 | { |
da4f09a7 | 476 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
982d06c5 | 477 | int madt_start = table_data->len; |
da4f09a7 AJ |
478 | const MemMapEntry *memmap = vms->memmap; |
479 | const int *irqmap = vms->irqmap; | |
982d06c5 | 480 | AcpiMadtGenericDistributor *gicd; |
ca793736 | 481 | AcpiMadtGenericMsiFrame *gic_msi; |
982d06c5 SZ |
482 | int i; |
483 | ||
b3b0e814 | 484 | acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); |
982d06c5 | 485 | |
982d06c5 SZ |
486 | gicd = acpi_data_push(table_data, sizeof *gicd); |
487 | gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR; | |
488 | gicd->length = sizeof(*gicd); | |
330afe05 | 489 | gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base); |
da4f09a7 | 490 | gicd->version = vms->gic_version; |
982d06c5 | 491 | |
9cd07db9 | 492 | for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { |
6e2ed65f AJ |
493 | AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data, |
494 | sizeof(*gicc)); | |
5d9c1756 SZ |
495 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); |
496 | ||
6e2ed65f | 497 | gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE; |
f2fbface | 498 | gicc->length = sizeof(*gicc); |
da4f09a7 | 499 | if (vms->gic_version == 2) { |
330afe05 | 500 | gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base); |
55ef3233 LM |
501 | gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base); |
502 | gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base); | |
f2fbface | 503 | } |
330afe05 AJ |
504 | gicc->cpu_interface_number = cpu_to_le32(i); |
505 | gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity); | |
506 | gicc->uid = cpu_to_le32(i); | |
6e2ed65f | 507 | gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED); |
8433dee0 | 508 | |
929e754d | 509 | if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { |
8433dee0 SZ |
510 | gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); |
511 | } | |
55ef3233 LM |
512 | if (vms->virt) { |
513 | gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); | |
f29cacfb | 514 | } |
f2fbface SZ |
515 | } |
516 | ||
da4f09a7 | 517 | if (vms->gic_version == 3) { |
13e5c54d | 518 | AcpiMadtGenericTranslator *gic_its; |
a1de312f | 519 | int nb_redist_regions = virt_gicv3_redist_region_count(vms); |
b92ad394 PF |
520 | AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data, |
521 | sizeof *gicr); | |
522 | ||
523 | gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; | |
524 | gicr->length = sizeof(*gicr); | |
525 | gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base); | |
526 | gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size); | |
13e5c54d | 527 | |
a1de312f EA |
528 | if (nb_redist_regions == 2) { |
529 | gicr = acpi_data_push(table_data, sizeof(*gicr)); | |
530 | gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; | |
531 | gicr->length = sizeof(*gicr); | |
bf424a12 EA |
532 | gicr->base_address = |
533 | cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); | |
534 | gicr->range_length = | |
535 | cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); | |
a1de312f EA |
536 | } |
537 | ||
da4f09a7 | 538 | if (its_class_name() && !vmc->no_its) { |
13cda487 AJ |
539 | gic_its = acpi_data_push(table_data, sizeof *gic_its); |
540 | gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR; | |
541 | gic_its->length = sizeof(*gic_its); | |
542 | gic_its->translation_id = 0; | |
543 | gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base); | |
13e5c54d | 544 | } |
b92ad394 | 545 | } else { |
b92ad394 PF |
546 | gic_msi = acpi_data_push(table_data, sizeof *gic_msi); |
547 | gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME; | |
548 | gic_msi->length = sizeof(*gic_msi); | |
549 | gic_msi->gic_msi_frame_id = 0; | |
550 | gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base); | |
551 | gic_msi->flags = cpu_to_le32(1); | |
552 | gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS); | |
553 | gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE); | |
554 | } | |
ca793736 | 555 | |
982d06c5 SZ |
556 | build_header(linker, table_data, |
557 | (void *)(table_data->data + madt_start), "APIC", | |
602b4582 MP |
558 | table_data->len - madt_start, 3, vms->oem_id, |
559 | vms->oem_table_id); | |
982d06c5 SZ |
560 | } |
561 | ||
c2f7c0c3 | 562 | /* FADT */ |
8612f8bd IM |
563 | static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, |
564 | VirtMachineState *vms, unsigned dsdt_tbl_offset) | |
c2f7c0c3 | 565 | { |
dd1b2037 IM |
566 | /* ACPI v5.1 */ |
567 | AcpiFadtData fadt = { | |
568 | .rev = 5, | |
569 | .minor_ver = 1, | |
570 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, | |
571 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | |
572 | }; | |
79e993a0 AJ |
573 | |
574 | switch (vms->psci_conduit) { | |
575 | case QEMU_PSCI_CONDUIT_DISABLED: | |
dd1b2037 | 576 | fadt.arm_boot_arch = 0; |
79e993a0 AJ |
577 | break; |
578 | case QEMU_PSCI_CONDUIT_HVC: | |
dd1b2037 IM |
579 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | |
580 | ACPI_FADT_ARM_PSCI_USE_HVC; | |
79e993a0 AJ |
581 | break; |
582 | case QEMU_PSCI_CONDUIT_SMC: | |
dd1b2037 | 583 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; |
79e993a0 AJ |
584 | break; |
585 | default: | |
586 | g_assert_not_reached(); | |
587 | } | |
c2f7c0c3 | 588 | |
602b4582 | 589 | build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); |
c2f7c0c3 SZ |
590 | } |
591 | ||
dfccd8cf SZ |
592 | /* DSDT */ |
593 | static void | |
da4f09a7 | 594 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
dfccd8cf | 595 | { |
2c1fb4d5 | 596 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
dfccd8cf | 597 | Aml *scope, *dsdt; |
cff51ac9 | 598 | MachineState *ms = MACHINE(vms); |
da4f09a7 AJ |
599 | const MemMapEntry *memmap = vms->memmap; |
600 | const int *irqmap = vms->irqmap; | |
dfccd8cf SZ |
601 | |
602 | dsdt = init_aml_allocator(); | |
603 | /* Reserve space for header */ | |
604 | acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); | |
605 | ||
67736a25 SZ |
606 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. |
607 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
608 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
609 | * the RTC ACPI device at all when using UEFI. | |
610 | */ | |
dfccd8cf | 611 | scope = aml_scope("\\_SB"); |
9cd07db9 | 612 | acpi_dsdt_add_cpus(scope, vms); |
dfccd8cf SZ |
613 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], |
614 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
2c1fb4d5 AJ |
615 | if (vmc->acpi_expose_flash) { |
616 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | |
617 | } | |
70bee80d | 618 | acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); |
dfccd8cf SZ |
619 | acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], |
620 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); | |
5125f9cd | 621 | acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), |
6f9765fb | 622 | vms->highmem, vms->highmem_ecam, vms); |
cff51ac9 SK |
623 | if (vms->acpi_dev) { |
624 | build_ged_aml(scope, "\\_SB."GED_DEVICE, | |
625 | HOTPLUG_HANDLER(vms->acpi_dev), | |
626 | irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, | |
627 | memmap[VIRT_ACPI_GED].base); | |
1962f31b SK |
628 | } else { |
629 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], | |
630 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
cff51ac9 SK |
631 | } |
632 | ||
633 | if (vms->acpi_dev) { | |
634 | uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), | |
635 | "ged-event", &error_abort); | |
636 | ||
637 | if (event & ACPI_GED_MEM_HOTPLUG_EVT) { | |
638 | build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, | |
639 | AML_SYSTEM_MEMORY, | |
640 | memmap[VIRT_PCDIMM_ACPI].base); | |
641 | } | |
642 | } | |
643 | ||
ac6aa59a | 644 | acpi_dsdt_add_power_button(scope); |
5ab540e9 | 645 | acpi_dsdt_add_tpm(scope, vms); |
d4e5de1a | 646 | |
dfccd8cf SZ |
647 | aml_append(dsdt, scope); |
648 | ||
649 | /* copy AML table into ACPI tables blob and patch header there */ | |
650 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); | |
651 | build_header(linker, table_data, | |
652 | (void *)(table_data->data + table_data->len - dsdt->buf->len), | |
602b4582 MP |
653 | "DSDT", dsdt->buf->len, 2, vms->oem_id, |
654 | vms->oem_table_id); | |
dfccd8cf SZ |
655 | free_aml_allocator(); |
656 | } | |
657 | ||
f5d8c8cd SZ |
658 | typedef |
659 | struct AcpiBuildState { | |
660 | /* Copy of table in RAM (for patching). */ | |
661 | MemoryRegion *table_mr; | |
662 | MemoryRegion *rsdp_mr; | |
663 | MemoryRegion *linker_mr; | |
664 | /* Is table patched? */ | |
665 | bool patched; | |
f5d8c8cd SZ |
666 | } AcpiBuildState; |
667 | ||
451b1570 YM |
668 | static void acpi_align_size(GArray *blob, unsigned align) |
669 | { | |
670 | /* | |
671 | * Align size to multiple of given size. This reduces the chance | |
672 | * we need to change size in the future (breaking cross version migration). | |
673 | */ | |
674 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); | |
675 | } | |
676 | ||
f5d8c8cd | 677 | static |
da4f09a7 | 678 | void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
f5d8c8cd | 679 | { |
da4f09a7 | 680 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
f5d8c8cd | 681 | GArray *table_offsets; |
cb51ac2f | 682 | unsigned dsdt, xsdt; |
dfccd8cf | 683 | GArray *tables_blob = tables->table_data; |
aa570207 | 684 | MachineState *ms = MACHINE(vms); |
f5d8c8cd SZ |
685 | |
686 | table_offsets = g_array_new(false, true /* clear */, | |
687 | sizeof(uint32_t)); | |
688 | ||
ad9671b8 IM |
689 | bios_linker_loader_alloc(tables->linker, |
690 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
f5d8c8cd SZ |
691 | 64, false /* high memory */); |
692 | ||
dfccd8cf | 693 | /* DSDT is pointed to by FADT */ |
c2f7c0c3 | 694 | dsdt = tables_blob->len; |
da4f09a7 | 695 | build_dsdt(tables_blob, tables->linker, vms); |
dfccd8cf | 696 | |
d0652b57 | 697 | /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ |
c2f7c0c3 | 698 | acpi_add_table(table_offsets, tables_blob); |
8612f8bd | 699 | build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); |
c2f7c0c3 | 700 | |
982d06c5 | 701 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 702 | build_madt(tables_blob, tables->linker, vms); |
982d06c5 | 703 | |
ee246400 | 704 | acpi_add_table(table_offsets, tables_blob); |
8dd845d3 | 705 | build_gtdt(tables_blob, tables->linker, vms); |
ee246400 | 706 | |
84344884 | 707 | acpi_add_table(table_offsets, tables_blob); |
48cefd94 WY |
708 | { |
709 | AcpiMcfgInfo mcfg = { | |
710 | .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, | |
711 | .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, | |
712 | }; | |
602b4582 MP |
713 | build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, |
714 | vms->oem_table_id); | |
48cefd94 | 715 | } |
84344884 | 716 | |
f264d51d | 717 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 718 | build_spcr(tables_blob, tables->linker, vms); |
f264d51d | 719 | |
aa16508f DG |
720 | if (vms->ras) { |
721 | build_ghes_error_table(tables->hardware_errors, tables->linker); | |
205cc75d | 722 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
723 | acpi_build_hest(tables_blob, tables->linker, vms->oem_id, |
724 | vms->oem_table_id); | |
aa16508f DG |
725 | } |
726 | ||
aa570207 | 727 | if (ms->numa_state->num_nodes > 0) { |
2b302e1e | 728 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 729 | build_srat(tables_blob, tables->linker, vms); |
118154b7 | 730 | if (ms->numa_state->have_numa_distance) { |
94a66456 | 731 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
732 | build_slit(tables_blob, tables->linker, ms, vms->oem_id, |
733 | vms->oem_table_id); | |
94a66456 | 734 | } |
2b302e1e SZ |
735 | } |
736 | ||
b5a60bee KL |
737 | if (ms->nvdimms_state->is_enabled) { |
738 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, | |
602b4582 MP |
739 | ms->nvdimms_state, ms->ram_slots, vms->oem_id, |
740 | vms->oem_table_id); | |
b5a60bee KL |
741 | } |
742 | ||
da4f09a7 | 743 | if (its_class_name() && !vmc->no_its) { |
e78f1222 | 744 | acpi_add_table(table_offsets, tables_blob); |
a703b4f6 | 745 | build_iort(tables_blob, tables->linker, vms); |
e78f1222 PM |
746 | } |
747 | ||
80bde693 EA |
748 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { |
749 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 MP |
750 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, |
751 | vms->oem_table_id); | |
80bde693 EA |
752 | } |
753 | ||
cb51ac2f AB |
754 | /* XSDT is pointed to by RSDP */ |
755 | xsdt = tables_blob->len; | |
602b4582 MP |
756 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, |
757 | vms->oem_table_id); | |
243bdb79 | 758 | |
d4bec5d8 | 759 | /* RSDP is in FSEG memory, so allocate it separately */ |
5c5fce1a SO |
760 | { |
761 | AcpiRsdpData rsdp_data = { | |
762 | .revision = 2, | |
602b4582 | 763 | .oem_id = vms->oem_id, |
5c5fce1a SO |
764 | .xsdt_tbl_offset = &xsdt, |
765 | .rsdt_tbl_offset = NULL, | |
766 | }; | |
767 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
768 | } | |
d4bec5d8 | 769 | |
451b1570 YM |
770 | /* |
771 | * The align size is 128, warn if 64k is not enough therefore | |
772 | * the align size could be resized. | |
773 | */ | |
774 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { | |
775 | warn_report("ACPI table size %u exceeds %d bytes," | |
776 | " migration may not work", | |
777 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
778 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
779 | " or PCI bridges."); | |
780 | } | |
781 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); | |
782 | ||
783 | ||
f5d8c8cd SZ |
784 | /* Cleanup memory that's no longer used. */ |
785 | g_array_free(table_offsets, true); | |
786 | } | |
787 | ||
788 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
789 | { | |
790 | uint32_t size = acpi_data_len(data); | |
791 | ||
792 | /* Make sure RAM size is correct - in case it got changed | |
793 | * e.g. by migration */ | |
794 | memory_region_ram_resize(mr, size, &error_abort); | |
795 | ||
796 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
797 | memory_region_set_dirty(mr, 0, size); | |
798 | } | |
799 | ||
3f8752b4 | 800 | static void virt_acpi_build_update(void *build_opaque) |
f5d8c8cd SZ |
801 | { |
802 | AcpiBuildState *build_state = build_opaque; | |
803 | AcpiBuildTables tables; | |
804 | ||
805 | /* No state to update or already patched? Nothing to do. */ | |
806 | if (!build_state || build_state->patched) { | |
807 | return; | |
808 | } | |
809 | build_state->patched = true; | |
810 | ||
811 | acpi_build_tables_init(&tables); | |
812 | ||
4dad9e74 | 813 | virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); |
f5d8c8cd SZ |
814 | |
815 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
816 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
0e9b9eda | 817 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
f5d8c8cd | 818 | |
f5d8c8cd SZ |
819 | acpi_build_tables_cleanup(&tables, true); |
820 | } | |
821 | ||
822 | static void virt_acpi_build_reset(void *build_opaque) | |
823 | { | |
824 | AcpiBuildState *build_state = build_opaque; | |
825 | build_state->patched = false; | |
826 | } | |
827 | ||
f5d8c8cd SZ |
828 | static const VMStateDescription vmstate_virt_acpi_build = { |
829 | .name = "virt_acpi_build", | |
830 | .version_id = 1, | |
831 | .minimum_version_id = 1, | |
832 | .fields = (VMStateField[]) { | |
833 | VMSTATE_BOOL(patched, AcpiBuildState), | |
834 | VMSTATE_END_OF_LIST() | |
835 | }, | |
836 | }; | |
837 | ||
e9a8e474 | 838 | void virt_acpi_setup(VirtMachineState *vms) |
f5d8c8cd SZ |
839 | { |
840 | AcpiBuildTables tables; | |
841 | AcpiBuildState *build_state; | |
a08a6462 | 842 | AcpiGedState *acpi_ged_state; |
f5d8c8cd | 843 | |
af1f60a4 | 844 | if (!vms->fw_cfg) { |
f5d8c8cd SZ |
845 | trace_virt_acpi_setup(); |
846 | return; | |
847 | } | |
848 | ||
17e89077 | 849 | if (!virt_is_acpi_enabled(vms)) { |
f5d8c8cd SZ |
850 | trace_virt_acpi_setup(); |
851 | return; | |
852 | } | |
853 | ||
854 | build_state = g_malloc0(sizeof *build_state); | |
f5d8c8cd SZ |
855 | |
856 | acpi_build_tables_init(&tables); | |
da4f09a7 | 857 | virt_acpi_build(vms, &tables); |
f5d8c8cd SZ |
858 | |
859 | /* Now expose it all to Guest */ | |
82f76c67 WY |
860 | build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, |
861 | build_state, tables.table_data, | |
862 | ACPI_BUILD_TABLE_FILE, | |
863 | ACPI_BUILD_TABLE_MAX_SIZE); | |
f5d8c8cd SZ |
864 | assert(build_state->table_mr != NULL); |
865 | ||
866 | build_state->linker_mr = | |
82f76c67 | 867 | acpi_add_rom_blob(virt_acpi_build_update, build_state, |
6c2b24d1 DH |
868 | tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, |
869 | ACPI_BUILD_LOADER_MAX_SIZE); | |
f5d8c8cd | 870 | |
af1f60a4 AJ |
871 | fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, |
872 | acpi_data_len(tables.tcpalog)); | |
f5d8c8cd | 873 | |
a08a6462 DG |
874 | if (vms->ras) { |
875 | assert(vms->acpi_dev); | |
876 | acpi_ged_state = ACPI_GED(vms->acpi_dev); | |
877 | acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, | |
878 | vms->fw_cfg, tables.hardware_errors); | |
879 | } | |
880 | ||
82f76c67 WY |
881 | build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, |
882 | build_state, tables.rsdp, | |
883 | ACPI_BUILD_RSDP_FILE, 0); | |
f5d8c8cd SZ |
884 | |
885 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
886 | virt_acpi_build_reset(build_state); | |
887 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
888 | ||
889 | /* Cleanup tables but don't free the memory: we track it | |
890 | * in build_state. | |
891 | */ | |
892 | acpi_build_tables_cleanup(&tables, false); | |
893 | } |