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f5d8c8cd SZ |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
12b16722 | 29 | #include "qemu/osdep.h" |
da34e65c | 30 | #include "qapi/error.h" |
f5d8c8cd | 31 | #include "qemu/bitmap.h" |
13a63743 | 32 | #include "qemu/error-report.h" |
f5d8c8cd | 33 | #include "trace.h" |
2e5b09fd | 34 | #include "hw/core/cpu.h" |
fcf5ef2a | 35 | #include "target/arm/cpu.h" |
f5d8c8cd SZ |
36 | #include "hw/acpi/acpi-defs.h" |
37 | #include "hw/acpi/acpi.h" | |
4c7f4f4f | 38 | #include "hw/nvram/fw_cfg_acpi.h" |
f5d8c8cd | 39 | #include "hw/acpi/bios-linker-loader.h" |
f5d8c8cd | 40 | #include "hw/acpi/aml-build.h" |
82f76c67 | 41 | #include "hw/acpi/utils.h" |
48cefd94 | 42 | #include "hw/acpi/pci.h" |
cff51ac9 SK |
43 | #include "hw/acpi/memory_hotplug.h" |
44 | #include "hw/acpi/generic_event_device.h" | |
80bde693 | 45 | #include "hw/acpi/tpm.h" |
7cbd3fd3 | 46 | #include "hw/acpi/hmat.h" |
84344884 | 47 | #include "hw/pci/pcie_host.h" |
d4e5de1a | 48 | #include "hw/pci/pci.h" |
42e0f050 | 49 | #include "hw/pci/pci_bus.h" |
06d2dd49 | 50 | #include "hw/pci-host/gpex.h" |
d05fdab4 | 51 | #include "hw/arm/virt.h" |
0c40daf0 | 52 | #include "hw/intc/arm_gicv3_its_common.h" |
b5a60bee | 53 | #include "hw/mem/nvdimm.h" |
5ab540e9 | 54 | #include "hw/platform-bus.h" |
2b302e1e | 55 | #include "sysemu/numa.h" |
71e8a915 | 56 | #include "sysemu/reset.h" |
80bde693 | 57 | #include "sysemu/tpm.h" |
d6454270 | 58 | #include "migration/vmstate.h" |
aa16508f | 59 | #include "hw/acpi/ghes.h" |
cf1a5cc9 | 60 | #include "hw/acpi/viot.h" |
f5d8c8cd | 61 | |
dfccd8cf SZ |
62 | #define ARM_SPI_BASE 32 |
63 | ||
451b1570 YM |
64 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
65 | ||
9cd07db9 | 66 | static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) |
dfccd8cf | 67 | { |
9cd07db9 | 68 | MachineState *ms = MACHINE(vms); |
dfccd8cf SZ |
69 | uint16_t i; |
70 | ||
9cd07db9 | 71 | for (i = 0; i < ms->smp.cpus; i++) { |
f460be43 | 72 | Aml *dev = aml_device("C%.03X", i); |
dfccd8cf SZ |
73 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); |
74 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
75 | aml_append(scope, dev); | |
76 | } | |
77 | } | |
78 | ||
79 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
45fcf539 | 80 | uint32_t uart_irq) |
dfccd8cf SZ |
81 | { |
82 | Aml *dev = aml_device("COM0"); | |
83 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
84 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
85 | ||
86 | Aml *crs = aml_resource_template(); | |
87 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
88 | uart_memmap->size, AML_READ_WRITE)); | |
89 | aml_append(crs, | |
90 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 91 | AML_EXCLUSIVE, &uart_irq, 1)); |
dfccd8cf | 92 | aml_append(dev, aml_name_decl("_CRS", crs)); |
f264d51d | 93 | |
dfccd8cf SZ |
94 | aml_append(scope, dev); |
95 | } | |
96 | ||
dfccd8cf SZ |
97 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) |
98 | { | |
99 | Aml *dev, *crs; | |
100 | hwaddr base = flash_memmap->base; | |
cd37aaf8 | 101 | hwaddr size = flash_memmap->size / 2; |
dfccd8cf SZ |
102 | |
103 | dev = aml_device("FLS0"); | |
104 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
105 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
106 | ||
107 | crs = aml_resource_template(); | |
108 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
109 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
110 | aml_append(scope, dev); | |
111 | ||
112 | dev = aml_device("FLS1"); | |
113 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
114 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
115 | crs = aml_resource_template(); | |
116 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
117 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
118 | aml_append(scope, dev); | |
119 | } | |
120 | ||
121 | static void acpi_dsdt_add_virtio(Aml *scope, | |
122 | const MemMapEntry *virtio_mmio_memmap, | |
45fcf539 | 123 | uint32_t mmio_irq, int num) |
dfccd8cf SZ |
124 | { |
125 | hwaddr base = virtio_mmio_memmap->base; | |
126 | hwaddr size = virtio_mmio_memmap->size; | |
dfccd8cf SZ |
127 | int i; |
128 | ||
129 | for (i = 0; i < num; i++) { | |
45fcf539 | 130 | uint32_t irq = mmio_irq + i; |
dfccd8cf SZ |
131 | Aml *dev = aml_device("VR%02u", i); |
132 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); | |
133 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
76266d99 | 134 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
dfccd8cf SZ |
135 | |
136 | Aml *crs = aml_resource_template(); | |
137 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
138 | aml_append(crs, | |
139 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 140 | AML_EXCLUSIVE, &irq, 1)); |
dfccd8cf SZ |
141 | aml_append(dev, aml_name_decl("_CRS", crs)); |
142 | aml_append(scope, dev); | |
143 | base += size; | |
144 | } | |
145 | } | |
146 | ||
45fcf539 | 147 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, |
c8f008c4 | 148 | uint32_t irq, VirtMachineState *vms) |
d4e5de1a | 149 | { |
c8f008c4 | 150 | int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); |
06d2dd49 GH |
151 | struct GPEXConfig cfg = { |
152 | .mmio32 = memmap[VIRT_PCIE_MMIO], | |
153 | .pio = memmap[VIRT_PCIE_PIO], | |
154 | .ecam = memmap[ecam_id], | |
155 | .irq = irq, | |
6f9765fb | 156 | .bus = vms->bus, |
06d2dd49 | 157 | }; |
d4e5de1a | 158 | |
c8f008c4 | 159 | if (vms->highmem_mmio) { |
06d2dd49 | 160 | cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; |
5125f9cd PF |
161 | } |
162 | ||
06d2dd49 | 163 | acpi_dsdt_add_gpex(scope, &cfg); |
d4e5de1a SZ |
164 | } |
165 | ||
aeb1a36d SZ |
166 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, |
167 | uint32_t gpio_irq) | |
168 | { | |
169 | Aml *dev = aml_device("GPO0"); | |
170 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
aeb1a36d SZ |
171 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
172 | ||
173 | Aml *crs = aml_resource_template(); | |
174 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
175 | AML_READ_WRITE)); | |
176 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
177 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
178 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
c1a158b7 SZ |
179 | |
180 | Aml *aei = aml_resource_template(); | |
181 | /* Pin 3 for power button */ | |
182 | const uint32_t pin_list[1] = {3}; | |
183 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
184 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
185 | "GPO0", NULL, 0)); | |
186 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
187 | ||
188 | /* _E03 is handle for power button */ | |
189 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
190 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
191 | aml_int(0x80))); | |
192 | aml_append(dev, method); | |
aeb1a36d SZ |
193 | aml_append(scope, dev); |
194 | } | |
195 | ||
f50be48a | 196 | #ifdef CONFIG_TPM |
5ab540e9 EA |
197 | static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) |
198 | { | |
199 | PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); | |
200 | hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; | |
201 | SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); | |
202 | MemoryRegion *sbdev_mr; | |
203 | hwaddr tpm_base; | |
204 | ||
205 | if (!sbdev) { | |
206 | return; | |
207 | } | |
208 | ||
209 | tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
210 | assert(tpm_base != -1); | |
211 | ||
212 | tpm_base += pbus_base; | |
213 | ||
214 | sbdev_mr = sysbus_mmio_get_region(sbdev, 0); | |
215 | ||
216 | Aml *dev = aml_device("TPM0"); | |
217 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
5903646d | 218 | aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); |
5ab540e9 EA |
219 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
220 | ||
221 | Aml *crs = aml_resource_template(); | |
222 | aml_append(crs, | |
223 | aml_memory32_fixed(tpm_base, | |
224 | (uint32_t)memory_region_size(sbdev_mr), | |
225 | AML_READ_WRITE)); | |
226 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
227 | aml_append(scope, dev); | |
228 | } | |
f50be48a | 229 | #endif |
5ab540e9 | 230 | |
271cbb2f | 231 | #define ID_MAPPING_ENTRY_SIZE 20 |
1c2cb7e0 EA |
232 | #define SMMU_V3_ENTRY_SIZE 68 |
233 | #define ROOT_COMPLEX_ENTRY_SIZE 36 | |
271cbb2f IM |
234 | #define IORT_NODE_OFFSET 48 |
235 | ||
236 | static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, | |
237 | uint32_t id_count, uint32_t out_ref) | |
238 | { | |
1c2cb7e0 | 239 | /* Table 4 ID mapping format */ |
271cbb2f IM |
240 | build_append_int_noprefix(table_data, input_base, 4); /* Input base */ |
241 | build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ | |
242 | build_append_int_noprefix(table_data, input_base, 4); /* Output base */ | |
243 | build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ | |
1c2cb7e0 EA |
244 | /* Flags */ |
245 | build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4); | |
271cbb2f IM |
246 | } |
247 | ||
248 | struct AcpiIortIdMapping { | |
249 | uint32_t input_base; | |
250 | uint32_t id_count; | |
251 | }; | |
252 | typedef struct AcpiIortIdMapping AcpiIortIdMapping; | |
253 | ||
42e0f050 XW |
254 | /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ |
255 | static int | |
256 | iort_host_bridges(Object *obj, void *opaque) | |
257 | { | |
258 | GArray *idmap_blob = opaque; | |
259 | ||
260 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
261 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
262 | ||
263 | if (bus && !pci_bus_bypass_iommu(bus)) { | |
264 | int min_bus, max_bus; | |
265 | ||
266 | pci_bus_range(bus, &min_bus, &max_bus); | |
267 | ||
268 | AcpiIortIdMapping idmap = { | |
269 | .input_base = min_bus << 8, | |
270 | .id_count = (max_bus - min_bus + 1) << 8, | |
271 | }; | |
272 | g_array_append_val(idmap_blob, idmap); | |
273 | } | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static int iort_idmap_compare(gconstpointer a, gconstpointer b) | |
280 | { | |
281 | AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; | |
282 | AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; | |
283 | ||
284 | return idmap_a->input_base - idmap_b->input_base; | |
285 | } | |
286 | ||
3548494e IM |
287 | /* |
288 | * Input Output Remapping Table (IORT) | |
289 | * Conforms to "IO Remapping Table System Software on ARM Platforms", | |
1c2cb7e0 | 290 | * Document number: ARM DEN 0049E.b, Feb 2021 |
3548494e | 291 | */ |
e78f1222 | 292 | static void |
a703b4f6 | 293 | build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
e78f1222 | 294 | { |
3548494e | 295 | int i, nb_nodes, rc_mapping_count; |
271cbb2f | 296 | const uint32_t iort_node_offset = IORT_NODE_OFFSET; |
3548494e | 297 | size_t node_size, smmu_offset = 0; |
271cbb2f | 298 | AcpiIortIdMapping *idmap; |
1c2cb7e0 | 299 | uint32_t id = 0; |
42e0f050 XW |
300 | GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); |
301 | GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); | |
e78f1222 | 302 | |
1c2cb7e0 | 303 | AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id, |
3548494e | 304 | .oem_table_id = vms->oem_table_id }; |
271cbb2f IM |
305 | /* Table 2 The IORT */ |
306 | acpi_table_begin(&table, table_data); | |
e78f1222 | 307 | |
a703b4f6 | 308 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
42e0f050 XW |
309 | AcpiIortIdMapping next_range = {0}; |
310 | ||
311 | object_child_foreach_recursive(object_get_root(), | |
312 | iort_host_bridges, smmu_idmaps); | |
313 | ||
314 | /* Sort the smmu idmap by input_base */ | |
315 | g_array_sort(smmu_idmaps, iort_idmap_compare); | |
316 | ||
317 | /* | |
318 | * Split the whole RIDs by mapping from RC to SMMU, | |
319 | * build the ID mapping from RC to ITS directly. | |
320 | */ | |
321 | for (i = 0; i < smmu_idmaps->len; i++) { | |
322 | idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); | |
323 | ||
324 | if (next_range.input_base < idmap->input_base) { | |
325 | next_range.id_count = idmap->input_base - next_range.input_base; | |
326 | g_array_append_val(its_idmaps, next_range); | |
327 | } | |
328 | ||
329 | next_range.input_base = idmap->input_base + idmap->id_count; | |
330 | } | |
331 | ||
332 | /* Append the last RC -> ITS ID mapping */ | |
333 | if (next_range.input_base < 0xFFFF) { | |
334 | next_range.id_count = 0xFFFF - next_range.input_base; | |
335 | g_array_append_val(its_idmaps, next_range); | |
336 | } | |
337 | ||
a703b4f6 | 338 | nb_nodes = 3; /* RC, ITS, SMMUv3 */ |
42e0f050 | 339 | rc_mapping_count = smmu_idmaps->len + its_idmaps->len; |
a703b4f6 PM |
340 | } else { |
341 | nb_nodes = 2; /* RC, ITS */ | |
42e0f050 | 342 | rc_mapping_count = 1; |
a703b4f6 | 343 | } |
3548494e IM |
344 | /* Number of IORT Nodes */ |
345 | build_append_int_noprefix(table_data, nb_nodes, 4); | |
271cbb2f | 346 | |
3548494e | 347 | /* Offset to Array of IORT Nodes */ |
271cbb2f | 348 | build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); |
3548494e | 349 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
e78f1222 | 350 | |
1c2cb7e0 | 351 | /* Table 12 ITS Group Format */ |
271cbb2f IM |
352 | build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ |
353 | node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; | |
354 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
1c2cb7e0 EA |
355 | build_append_int_noprefix(table_data, 1, 1); /* Revision */ |
356 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
271cbb2f IM |
357 | build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ |
358 | build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ | |
359 | build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ | |
360 | /* GIC ITS Identifier Array */ | |
361 | build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); | |
e78f1222 | 362 | |
a703b4f6 | 363 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
41c4fb94 | 364 | int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; |
a703b4f6 | 365 | |
271cbb2f | 366 | smmu_offset = table_data->len - table.table_offset; |
1c2cb7e0 | 367 | /* Table 9 SMMUv3 Format */ |
271cbb2f IM |
368 | build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ |
369 | node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; | |
370 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
1c2cb7e0 EA |
371 | build_append_int_noprefix(table_data, 4, 1); /* Revision */ |
372 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
271cbb2f IM |
373 | build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */ |
374 | /* Reference to ID Array */ | |
375 | build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); | |
376 | /* Base address */ | |
377 | build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); | |
378 | /* Flags */ | |
1c2cb7e0 | 379 | build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); |
271cbb2f IM |
380 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
381 | build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ | |
382 | /* Model */ | |
383 | build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); | |
384 | build_append_int_noprefix(table_data, irq, 4); /* Event */ | |
385 | build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ | |
386 | build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ | |
387 | build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ | |
1c2cb7e0 EA |
388 | build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ |
389 | /* DeviceID mapping index (ignored since interrupts are GSIV based) */ | |
390 | build_append_int_noprefix(table_data, 0, 4); | |
271cbb2f | 391 | |
a703b4f6 | 392 | /* output IORT node is the ITS group node (the first node) */ |
271cbb2f | 393 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); |
a703b4f6 PM |
394 | } |
395 | ||
1c2cb7e0 | 396 | /* Table 17 Root Complex Node */ |
271cbb2f IM |
397 | build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ |
398 | node_size = ROOT_COMPLEX_ENTRY_SIZE + | |
399 | ID_MAPPING_ENTRY_SIZE * rc_mapping_count; | |
400 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
1c2cb7e0 EA |
401 | build_append_int_noprefix(table_data, 3, 1); /* Revision */ |
402 | build_append_int_noprefix(table_data, id++, 4); /* Identifier */ | |
271cbb2f IM |
403 | /* Number of ID mappings */ |
404 | build_append_int_noprefix(table_data, rc_mapping_count, 4); | |
405 | /* Reference to ID Array */ | |
406 | build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); | |
407 | ||
1c2cb7e0 | 408 | /* Table 14 Memory access properties */ |
271cbb2f IM |
409 | /* CCA: Cache Coherent Attribute */ |
410 | build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); | |
411 | build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ | |
412 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
1c2cb7e0 EA |
413 | /* Table 15 Memory Access Flags */ |
414 | build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1); | |
271cbb2f IM |
415 | |
416 | build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ | |
417 | /* MCFG pci_segment */ | |
418 | build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ | |
419 | ||
1c2cb7e0 EA |
420 | /* Memory address size limit */ |
421 | build_append_int_noprefix(table_data, 64, 1); | |
422 | ||
423 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
424 | ||
271cbb2f | 425 | /* Output Reference */ |
a703b4f6 | 426 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
42e0f050 XW |
427 | AcpiIortIdMapping *range; |
428 | ||
429 | /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ | |
430 | for (i = 0; i < smmu_idmaps->len; i++) { | |
42e0f050 | 431 | range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); |
42e0f050 | 432 | /* output IORT node is the smmuv3 node */ |
271cbb2f IM |
433 | build_iort_id_mapping(table_data, range->input_base, |
434 | range->id_count, smmu_offset); | |
42e0f050 XW |
435 | } |
436 | ||
437 | /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ | |
438 | for (i = 0; i < its_idmaps->len; i++) { | |
42e0f050 | 439 | range = &g_array_index(its_idmaps, AcpiIortIdMapping, i); |
42e0f050 | 440 | /* output IORT node is the ITS group node (the first node) */ |
271cbb2f IM |
441 | build_iort_id_mapping(table_data, range->input_base, |
442 | range->id_count, iort_node_offset); | |
42e0f050 | 443 | } |
a703b4f6 PM |
444 | } else { |
445 | /* output IORT node is the ITS group node (the first node) */ | |
271cbb2f | 446 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); |
a703b4f6 | 447 | } |
e78f1222 | 448 | |
3548494e | 449 | acpi_table_end(linker, &table); |
42e0f050 XW |
450 | g_array_free(smmu_idmaps, true); |
451 | g_array_free(its_idmaps, true); | |
e78f1222 PM |
452 | } |
453 | ||
a86d86ac IM |
454 | /* |
455 | * Serial Port Console Redirection Table (SPCR) | |
456 | * Rev: 1.07 | |
457 | */ | |
f264d51d | 458 | static void |
da4f09a7 | 459 | build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
f264d51d | 460 | { |
a86d86ac IM |
461 | AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id, |
462 | .oem_table_id = vms->oem_table_id }; | |
f264d51d | 463 | |
a86d86ac | 464 | acpi_table_begin(&table, table_data); |
f264d51d | 465 | |
a86d86ac IM |
466 | /* Interface Type */ |
467 | build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ | |
468 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
469 | /* Base Address */ | |
41f7b58b | 470 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, |
a86d86ac IM |
471 | vms->memmap[VIRT_UART].base); |
472 | /* Interrupt Type */ | |
473 | build_append_int_noprefix(table_data, | |
474 | (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); | |
475 | build_append_int_noprefix(table_data, 0, 1); /* IRQ */ | |
476 | /* Global System Interrupt */ | |
477 | build_append_int_noprefix(table_data, | |
478 | vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); | |
479 | build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ | |
480 | build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */ | |
481 | /* Stop Bits */ | |
482 | build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1); | |
483 | /* Flow Control */ | |
484 | build_append_int_noprefix(table_data, | |
485 | (1 << 1) /* RTS/CTS hardware flow control */, 1); | |
486 | /* Terminal Type */ | |
487 | build_append_int_noprefix(table_data, 0 /* VT100 */, 1); | |
488 | build_append_int_noprefix(table_data, 0, 1); /* Language */ | |
489 | /* PCI Device ID */ | |
490 | build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); | |
491 | /* PCI Vendor ID */ | |
492 | build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); | |
493 | build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */ | |
494 | build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */ | |
495 | build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */ | |
496 | build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */ | |
497 | build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */ | |
498 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
f264d51d | 499 | |
a86d86ac | 500 | acpi_table_end(linker, &table); |
f264d51d AJ |
501 | } |
502 | ||
e5b6d55a IM |
503 | /* |
504 | * ACPI spec, Revision 5.1 | |
505 | * 5.2.16 System Resource Affinity Table (SRAT) | |
506 | */ | |
2b302e1e | 507 | static void |
da4f09a7 | 508 | build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
2b302e1e | 509 | { |
255bf20f | 510 | int i; |
2b302e1e | 511 | uint64_t mem_base; |
4ccf5826 | 512 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
aa570207 TX |
513 | MachineState *ms = MACHINE(vms); |
514 | const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); | |
255bf20f IM |
515 | AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, |
516 | .oem_table_id = vms->oem_table_id }; | |
2b302e1e | 517 | |
255bf20f IM |
518 | acpi_table_begin(&table, table_data); |
519 | build_append_int_noprefix(table_data, 1, 4); /* Reserved */ | |
520 | build_append_int_noprefix(table_data, 0, 8); /* Reserved */ | |
2b302e1e | 521 | |
4ccf5826 | 522 | for (i = 0; i < cpu_list->len; ++i) { |
e5b6d55a IM |
523 | uint32_t nodeid = cpu_list->cpus[i].props.node_id; |
524 | /* | |
525 | * 5.2.16.4 GICC Affinity Structure | |
526 | */ | |
527 | build_append_int_noprefix(table_data, 3, 1); /* Type */ | |
528 | build_append_int_noprefix(table_data, 18, 1); /* Length */ | |
529 | build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ | |
530 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
531 | /* Flags, Table 5-76 */ | |
532 | build_append_int_noprefix(table_data, 1 /* Enabled */, 4); | |
533 | build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ | |
2b302e1e | 534 | } |
2b302e1e | 535 | |
da4f09a7 | 536 | mem_base = vms->memmap[VIRT_MEM].base; |
aa570207 | 537 | for (i = 0; i < ms->numa_state->num_nodes; ++i) { |
7e721e7b | 538 | if (ms->numa_state->nodes[i].node_mem > 0) { |
e5b6d55a | 539 | build_srat_memory(table_data, mem_base, |
7e721e7b | 540 | ms->numa_state->nodes[i].node_mem, i, |
66c353ce | 541 | MEM_AFFINITY_ENABLED); |
7e721e7b | 542 | mem_base += ms->numa_state->nodes[i].node_mem; |
66c353ce | 543 | } |
2b302e1e SZ |
544 | } |
545 | ||
c3b0cf6e VV |
546 | if (ms->nvdimms_state->is_enabled) { |
547 | nvdimm_build_srat(table_data); | |
548 | } | |
549 | ||
442da7dc | 550 | if (ms->device_memory) { |
e5b6d55a | 551 | build_srat_memory(table_data, ms->device_memory->base, |
442da7dc SK |
552 | memory_region_size(&ms->device_memory->mr), |
553 | ms->numa_state->num_nodes - 1, | |
554 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
555 | } | |
556 | ||
255bf20f | 557 | acpi_table_end(linker, &table); |
2b302e1e SZ |
558 | } |
559 | ||
41041e57 IM |
560 | /* |
561 | * ACPI spec, Revision 5.1 | |
562 | * 5.2.24 Generic Timer Description Table (GTDT) | |
563 | */ | |
ee246400 | 564 | static void |
8dd845d3 | 565 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
ee246400 | 566 | { |
8dd845d3 | 567 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
41041e57 IM |
568 | /* |
569 | * Table 5-117 Flag Definitions | |
570 | * set only "Timer interrupt Mode" and assume "Timer Interrupt | |
571 | * polarity" bit as '0: Interrupt is Active high' | |
572 | */ | |
573 | uint32_t irqflags = vmc->claim_edge_triggered_timers ? | |
574 | 1 : /* Interrupt is Edge triggered */ | |
575 | 0; /* Interrupt is Level triggered */ | |
576 | AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id, | |
577 | .oem_table_id = vms->oem_table_id }; | |
ee246400 | 578 | |
41041e57 | 579 | acpi_table_begin(&table, table_data); |
ee246400 | 580 | |
41041e57 | 581 | /* CntControlBase Physical Address */ |
5dbc9a27 | 582 | build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); |
41041e57 IM |
583 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
584 | /* | |
585 | * FIXME: clarify comment: | |
586 | * The interrupt values are the same with the device tree when adding 16 | |
587 | */ | |
588 | /* Secure EL1 timer GSIV */ | |
9036e917 | 589 | build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4); |
41041e57 IM |
590 | /* Secure EL1 timer Flags */ |
591 | build_append_int_noprefix(table_data, irqflags, 4); | |
592 | /* Non-Secure EL1 timer GSIV */ | |
9036e917 | 593 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4); |
41041e57 IM |
594 | /* Non-Secure EL1 timer Flags */ |
595 | build_append_int_noprefix(table_data, irqflags | | |
596 | 1UL << 2, /* Always-on Capability */ | |
597 | 4); | |
598 | /* Virtual timer GSIV */ | |
9036e917 | 599 | build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4); |
41041e57 IM |
600 | /* Virtual Timer Flags */ |
601 | build_append_int_noprefix(table_data, irqflags, 4); | |
602 | /* Non-Secure EL2 timer GSIV */ | |
9036e917 | 603 | build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4); |
41041e57 IM |
604 | /* Non-Secure EL2 timer Flags */ |
605 | build_append_int_noprefix(table_data, irqflags, 4); | |
606 | /* CntReadBase Physical address */ | |
5dbc9a27 | 607 | build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8); |
41041e57 IM |
608 | /* Platform Timer Count */ |
609 | build_append_int_noprefix(table_data, 0, 4); | |
610 | /* Platform Timer Offset */ | |
611 | build_append_int_noprefix(table_data, 0, 4); | |
ee246400 | 612 | |
41041e57 | 613 | acpi_table_end(linker, &table); |
ee246400 SZ |
614 | } |
615 | ||
f0dc9a5d EA |
616 | /* Debug Port Table 2 (DBG2) */ |
617 | static void | |
618 | build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | |
619 | { | |
620 | AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id, | |
621 | .oem_table_id = vms->oem_table_id }; | |
622 | int dbg2devicelength; | |
623 | const char name[] = "COM0"; | |
624 | const int namespace_length = sizeof(name); | |
625 | ||
626 | acpi_table_begin(&table, table_data); | |
627 | ||
628 | dbg2devicelength = 22 + /* BaseAddressRegister[] offset */ | |
629 | 12 + /* BaseAddressRegister[] */ | |
630 | 4 + /* AddressSize[] */ | |
631 | namespace_length /* NamespaceString[] */; | |
632 | ||
633 | /* OffsetDbgDeviceInfo */ | |
634 | build_append_int_noprefix(table_data, 44, 4); | |
635 | /* NumberDbgDeviceInfo */ | |
636 | build_append_int_noprefix(table_data, 1, 4); | |
637 | ||
638 | /* Table 2. Debug Device Information structure format */ | |
639 | build_append_int_noprefix(table_data, 0, 1); /* Revision */ | |
640 | build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */ | |
641 | /* NumberofGenericAddressRegisters */ | |
642 | build_append_int_noprefix(table_data, 1, 1); | |
643 | /* NameSpaceStringLength */ | |
644 | build_append_int_noprefix(table_data, namespace_length, 2); | |
645 | build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */ | |
646 | build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */ | |
647 | /* OemDataOffset (0 means no OEM data) */ | |
648 | build_append_int_noprefix(table_data, 0, 2); | |
649 | ||
650 | /* Port Type */ | |
651 | build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2); | |
652 | /* Port Subtype */ | |
653 | build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2); | |
654 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
655 | /* BaseAddressRegisterOffset */ | |
656 | build_append_int_noprefix(table_data, 22, 2); | |
657 | /* AddressSizeOffset */ | |
658 | build_append_int_noprefix(table_data, 34, 2); | |
659 | ||
660 | /* BaseAddressRegister[] */ | |
41f7b58b | 661 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, |
f0dc9a5d EA |
662 | vms->memmap[VIRT_UART].base); |
663 | ||
664 | /* AddressSize[] */ | |
665 | build_append_int_noprefix(table_data, | |
666 | vms->memmap[VIRT_UART].size, 4); | |
667 | ||
668 | /* NamespaceString[] */ | |
669 | g_array_append_vals(table_data, name, namespace_length); | |
670 | ||
671 | acpi_table_end(linker, &table); | |
672 | }; | |
673 | ||
99a7545f | 674 | /* |
7fe4c35c | 675 | * ACPI spec, Revision 6.0 Errata A |
99a7545f IM |
676 | * 5.2.12 Multiple APIC Description Table (MADT) |
677 | */ | |
37f33084 IM |
678 | static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) |
679 | { | |
680 | build_append_int_noprefix(table_data, 0xE, 1); /* Type */ | |
681 | build_append_int_noprefix(table_data, 16, 1); /* Length */ | |
682 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
b3db996f | 683 | /* Discovery Range Base Address */ |
37f33084 IM |
684 | build_append_int_noprefix(table_data, base, 8); |
685 | build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ | |
686 | } | |
687 | ||
982d06c5 | 688 | static void |
da4f09a7 | 689 | build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
982d06c5 | 690 | { |
37f33084 | 691 | int i; |
da4f09a7 | 692 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
da4f09a7 | 693 | const MemMapEntry *memmap = vms->memmap; |
7fe4c35c | 694 | AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id, |
99a7545f | 695 | .oem_table_id = vms->oem_table_id }; |
982d06c5 | 696 | |
99a7545f IM |
697 | acpi_table_begin(&table, table_data); |
698 | /* Local Interrupt Controller Address */ | |
699 | build_append_int_noprefix(table_data, 0, 4); | |
37f33084 IM |
700 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ |
701 | ||
702 | /* 5.2.12.15 GIC Distributor Structure */ | |
703 | build_append_int_noprefix(table_data, 0xC, 1); /* Type */ | |
704 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
705 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
706 | build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ | |
707 | /* Physical Base Address */ | |
708 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); | |
709 | build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ | |
710 | /* GIC version */ | |
711 | build_append_int_noprefix(table_data, vms->gic_version, 1); | |
712 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
982d06c5 | 713 | |
9cd07db9 | 714 | for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { |
5d9c1756 | 715 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); |
37f33084 | 716 | uint64_t physical_base_address = 0, gich = 0, gicv = 0; |
9036e917 | 717 | uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0; |
37f33084 | 718 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? |
9036e917 | 719 | VIRTUAL_PMU_IRQ : 0; |
5d9c1756 | 720 | |
e1f04578 | 721 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
37f33084 IM |
722 | physical_base_address = memmap[VIRT_GIC_CPU].base; |
723 | gicv = memmap[VIRT_GIC_VCPU].base; | |
724 | gich = memmap[VIRT_GIC_HYP].base; | |
f2fbface | 725 | } |
8433dee0 | 726 | |
37f33084 IM |
727 | /* 5.2.12.14 GIC Structure */ |
728 | build_append_int_noprefix(table_data, 0xB, 1); /* Type */ | |
7fe4c35c | 729 | build_append_int_noprefix(table_data, 80, 1); /* Length */ |
37f33084 IM |
730 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ |
731 | build_append_int_noprefix(table_data, i, 4); /* GIC ID */ | |
732 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
733 | /* Flags */ | |
734 | build_append_int_noprefix(table_data, 1, 4); /* Enabled */ | |
735 | /* Parking Protocol Version */ | |
736 | build_append_int_noprefix(table_data, 0, 4); | |
737 | /* Performance Interrupt GSIV */ | |
738 | build_append_int_noprefix(table_data, pmu_interrupt, 4); | |
739 | build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ | |
740 | /* Physical Base Address */ | |
741 | build_append_int_noprefix(table_data, physical_base_address, 8); | |
742 | build_append_int_noprefix(table_data, gicv, 8); /* GICV */ | |
743 | build_append_int_noprefix(table_data, gich, 8); /* GICH */ | |
744 | /* VGIC Maintenance interrupt */ | |
745 | build_append_int_noprefix(table_data, vgic_interrupt, 4); | |
746 | build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ | |
747 | /* MPIDR */ | |
748 | build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); | |
7fe4c35c ML |
749 | /* Processor Power Efficiency Class */ |
750 | build_append_int_noprefix(table_data, 0, 1); | |
751 | /* Reserved */ | |
752 | build_append_int_noprefix(table_data, 0, 3); | |
f2fbface SZ |
753 | } |
754 | ||
e1f04578 | 755 | if (vms->gic_version != VIRT_GIC_VERSION_2) { |
37f33084 IM |
756 | build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, |
757 | memmap[VIRT_GIC_REDIST].size); | |
758 | if (virt_gicv3_redist_region_count(vms) == 2) { | |
759 | build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, | |
760 | memmap[VIRT_HIGH_GIC_REDIST2].size); | |
a1de312f EA |
761 | } |
762 | ||
da4f09a7 | 763 | if (its_class_name() && !vmc->no_its) { |
37f33084 IM |
764 | /* |
765 | * ACPI spec, Revision 6.0 Errata A | |
766 | * (original 6.0 definition has invalid Length) | |
767 | * 5.2.12.18 GIC ITS Structure | |
768 | */ | |
769 | build_append_int_noprefix(table_data, 0xF, 1); /* Type */ | |
770 | build_append_int_noprefix(table_data, 20, 1); /* Length */ | |
771 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
772 | build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ | |
773 | /* Physical Base Address */ | |
774 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); | |
775 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
13e5c54d | 776 | } |
b92ad394 | 777 | } else { |
37f33084 IM |
778 | const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; |
779 | ||
780 | /* 5.2.12.16 GIC MSI Frame Structure */ | |
781 | build_append_int_noprefix(table_data, 0xD, 1); /* Type */ | |
782 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
783 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
784 | build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ | |
785 | /* Physical Base Address */ | |
786 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); | |
787 | build_append_int_noprefix(table_data, 1, 4); /* Flags */ | |
788 | /* SPI Count */ | |
789 | build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); | |
790 | build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ | |
b92ad394 | 791 | } |
99a7545f | 792 | acpi_table_end(linker, &table); |
982d06c5 SZ |
793 | } |
794 | ||
c2f7c0c3 | 795 | /* FADT */ |
4496d1d3 | 796 | static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, |
8612f8bd | 797 | VirtMachineState *vms, unsigned dsdt_tbl_offset) |
c2f7c0c3 | 798 | { |
4496d1d3 | 799 | /* ACPI v6.0 */ |
dd1b2037 | 800 | AcpiFadtData fadt = { |
4496d1d3 ML |
801 | .rev = 6, |
802 | .minor_ver = 0, | |
dd1b2037 IM |
803 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, |
804 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | |
805 | }; | |
79e993a0 AJ |
806 | |
807 | switch (vms->psci_conduit) { | |
808 | case QEMU_PSCI_CONDUIT_DISABLED: | |
dd1b2037 | 809 | fadt.arm_boot_arch = 0; |
79e993a0 AJ |
810 | break; |
811 | case QEMU_PSCI_CONDUIT_HVC: | |
dd1b2037 IM |
812 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | |
813 | ACPI_FADT_ARM_PSCI_USE_HVC; | |
79e993a0 AJ |
814 | break; |
815 | case QEMU_PSCI_CONDUIT_SMC: | |
dd1b2037 | 816 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; |
79e993a0 AJ |
817 | break; |
818 | default: | |
819 | g_assert_not_reached(); | |
820 | } | |
c2f7c0c3 | 821 | |
602b4582 | 822 | build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); |
c2f7c0c3 SZ |
823 | } |
824 | ||
dfccd8cf SZ |
825 | /* DSDT */ |
826 | static void | |
da4f09a7 | 827 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
dfccd8cf | 828 | { |
2c1fb4d5 | 829 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
dfccd8cf | 830 | Aml *scope, *dsdt; |
cff51ac9 | 831 | MachineState *ms = MACHINE(vms); |
da4f09a7 AJ |
832 | const MemMapEntry *memmap = vms->memmap; |
833 | const int *irqmap = vms->irqmap; | |
fc02b869 IM |
834 | AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, |
835 | .oem_table_id = vms->oem_table_id }; | |
dfccd8cf | 836 | |
fc02b869 | 837 | acpi_table_begin(&table, table_data); |
dfccd8cf | 838 | dsdt = init_aml_allocator(); |
dfccd8cf | 839 | |
67736a25 SZ |
840 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. |
841 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
842 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
843 | * the RTC ACPI device at all when using UEFI. | |
844 | */ | |
dfccd8cf | 845 | scope = aml_scope("\\_SB"); |
9cd07db9 | 846 | acpi_dsdt_add_cpus(scope, vms); |
dfccd8cf SZ |
847 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], |
848 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
2c1fb4d5 AJ |
849 | if (vmc->acpi_expose_flash) { |
850 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | |
851 | } | |
4c7f4f4f | 852 | fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); |
dfccd8cf SZ |
853 | acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], |
854 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); | |
c8f008c4 | 855 | acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); |
cff51ac9 SK |
856 | if (vms->acpi_dev) { |
857 | build_ged_aml(scope, "\\_SB."GED_DEVICE, | |
858 | HOTPLUG_HANDLER(vms->acpi_dev), | |
859 | irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, | |
860 | memmap[VIRT_ACPI_GED].base); | |
1962f31b SK |
861 | } else { |
862 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], | |
863 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
cff51ac9 SK |
864 | } |
865 | ||
866 | if (vms->acpi_dev) { | |
867 | uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), | |
868 | "ged-event", &error_abort); | |
869 | ||
870 | if (event & ACPI_GED_MEM_HOTPLUG_EVT) { | |
871 | build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, | |
872 | AML_SYSTEM_MEMORY, | |
873 | memmap[VIRT_PCDIMM_ACPI].base); | |
874 | } | |
875 | } | |
876 | ||
ac6aa59a | 877 | acpi_dsdt_add_power_button(scope); |
f50be48a | 878 | #ifdef CONFIG_TPM |
5ab540e9 | 879 | acpi_dsdt_add_tpm(scope, vms); |
f50be48a | 880 | #endif |
d4e5de1a | 881 | |
dfccd8cf SZ |
882 | aml_append(dsdt, scope); |
883 | ||
fc02b869 | 884 | /* copy AML table into ACPI tables blob */ |
dfccd8cf | 885 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
fc02b869 IM |
886 | |
887 | acpi_table_end(linker, &table); | |
dfccd8cf SZ |
888 | free_aml_allocator(); |
889 | } | |
890 | ||
f5d8c8cd SZ |
891 | typedef |
892 | struct AcpiBuildState { | |
893 | /* Copy of table in RAM (for patching). */ | |
894 | MemoryRegion *table_mr; | |
895 | MemoryRegion *rsdp_mr; | |
896 | MemoryRegion *linker_mr; | |
897 | /* Is table patched? */ | |
898 | bool patched; | |
f5d8c8cd SZ |
899 | } AcpiBuildState; |
900 | ||
451b1570 YM |
901 | static void acpi_align_size(GArray *blob, unsigned align) |
902 | { | |
903 | /* | |
904 | * Align size to multiple of given size. This reduces the chance | |
905 | * we need to change size in the future (breaking cross version migration). | |
906 | */ | |
907 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); | |
908 | } | |
909 | ||
f5d8c8cd | 910 | static |
da4f09a7 | 911 | void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
f5d8c8cd | 912 | { |
da4f09a7 | 913 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
f5d8c8cd | 914 | GArray *table_offsets; |
cb51ac2f | 915 | unsigned dsdt, xsdt; |
dfccd8cf | 916 | GArray *tables_blob = tables->table_data; |
aa570207 | 917 | MachineState *ms = MACHINE(vms); |
f5d8c8cd SZ |
918 | |
919 | table_offsets = g_array_new(false, true /* clear */, | |
920 | sizeof(uint32_t)); | |
921 | ||
ad9671b8 IM |
922 | bios_linker_loader_alloc(tables->linker, |
923 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
f5d8c8cd SZ |
924 | 64, false /* high memory */); |
925 | ||
dfccd8cf | 926 | /* DSDT is pointed to by FADT */ |
c2f7c0c3 | 927 | dsdt = tables_blob->len; |
da4f09a7 | 928 | build_dsdt(tables_blob, tables->linker, vms); |
dfccd8cf | 929 | |
70d23ed5 | 930 | /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ |
c2f7c0c3 | 931 | acpi_add_table(table_offsets, tables_blob); |
4496d1d3 | 932 | build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); |
c2f7c0c3 | 933 | |
982d06c5 | 934 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 935 | build_madt(tables_blob, tables->linker, vms); |
982d06c5 | 936 | |
70d23ed5 YW |
937 | if (!vmc->no_cpu_topology) { |
938 | acpi_add_table(table_offsets, tables_blob); | |
939 | build_pptt(tables_blob, tables->linker, ms, | |
940 | vms->oem_id, vms->oem_table_id); | |
941 | } | |
942 | ||
ee246400 | 943 | acpi_add_table(table_offsets, tables_blob); |
8dd845d3 | 944 | build_gtdt(tables_blob, tables->linker, vms); |
ee246400 | 945 | |
84344884 | 946 | acpi_add_table(table_offsets, tables_blob); |
48cefd94 WY |
947 | { |
948 | AcpiMcfgInfo mcfg = { | |
949 | .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, | |
950 | .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, | |
951 | }; | |
602b4582 MP |
952 | build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, |
953 | vms->oem_table_id); | |
48cefd94 | 954 | } |
84344884 | 955 | |
f264d51d | 956 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 957 | build_spcr(tables_blob, tables->linker, vms); |
f264d51d | 958 | |
f0dc9a5d EA |
959 | acpi_add_table(table_offsets, tables_blob); |
960 | build_dbg2(tables_blob, tables->linker, vms); | |
961 | ||
aa16508f DG |
962 | if (vms->ras) { |
963 | build_ghes_error_table(tables->hardware_errors, tables->linker); | |
205cc75d | 964 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
965 | acpi_build_hest(tables_blob, tables->linker, vms->oem_id, |
966 | vms->oem_table_id); | |
aa16508f DG |
967 | } |
968 | ||
aa570207 | 969 | if (ms->numa_state->num_nodes > 0) { |
2b302e1e | 970 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 971 | build_srat(tables_blob, tables->linker, vms); |
118154b7 | 972 | if (ms->numa_state->have_numa_distance) { |
94a66456 | 973 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
974 | build_slit(tables_blob, tables->linker, ms, vms->oem_id, |
975 | vms->oem_table_id); | |
94a66456 | 976 | } |
7cbd3fd3 XC |
977 | |
978 | if (ms->numa_state->hmat_enabled) { | |
979 | acpi_add_table(table_offsets, tables_blob); | |
980 | build_hmat(tables_blob, tables->linker, ms->numa_state, | |
981 | vms->oem_id, vms->oem_table_id); | |
982 | } | |
2b302e1e SZ |
983 | } |
984 | ||
b5a60bee KL |
985 | if (ms->nvdimms_state->is_enabled) { |
986 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, | |
602b4582 MP |
987 | ms->nvdimms_state, ms->ram_slots, vms->oem_id, |
988 | vms->oem_table_id); | |
b5a60bee KL |
989 | } |
990 | ||
da4f09a7 | 991 | if (its_class_name() && !vmc->no_its) { |
e78f1222 | 992 | acpi_add_table(table_offsets, tables_blob); |
a703b4f6 | 993 | build_iort(tables_blob, tables->linker, vms); |
e78f1222 PM |
994 | } |
995 | ||
f50be48a | 996 | #ifdef CONFIG_TPM |
80bde693 EA |
997 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { |
998 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 MP |
999 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, |
1000 | vms->oem_table_id); | |
80bde693 | 1001 | } |
f50be48a | 1002 | #endif |
80bde693 | 1003 | |
cf1a5cc9 JPB |
1004 | if (vms->iommu == VIRT_IOMMU_VIRTIO) { |
1005 | acpi_add_table(table_offsets, tables_blob); | |
1006 | build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, | |
1007 | vms->oem_id, vms->oem_table_id); | |
1008 | } | |
1009 | ||
cb51ac2f AB |
1010 | /* XSDT is pointed to by RSDP */ |
1011 | xsdt = tables_blob->len; | |
602b4582 MP |
1012 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, |
1013 | vms->oem_table_id); | |
243bdb79 | 1014 | |
d4bec5d8 | 1015 | /* RSDP is in FSEG memory, so allocate it separately */ |
5c5fce1a SO |
1016 | { |
1017 | AcpiRsdpData rsdp_data = { | |
1018 | .revision = 2, | |
602b4582 | 1019 | .oem_id = vms->oem_id, |
5c5fce1a SO |
1020 | .xsdt_tbl_offset = &xsdt, |
1021 | .rsdt_tbl_offset = NULL, | |
1022 | }; | |
1023 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
1024 | } | |
d4bec5d8 | 1025 | |
451b1570 YM |
1026 | /* |
1027 | * The align size is 128, warn if 64k is not enough therefore | |
1028 | * the align size could be resized. | |
1029 | */ | |
1030 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { | |
1031 | warn_report("ACPI table size %u exceeds %d bytes," | |
1032 | " migration may not work", | |
1033 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
1034 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
1035 | " or PCI bridges."); | |
1036 | } | |
1037 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); | |
1038 | ||
1039 | ||
f5d8c8cd SZ |
1040 | /* Cleanup memory that's no longer used. */ |
1041 | g_array_free(table_offsets, true); | |
1042 | } | |
1043 | ||
1044 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
1045 | { | |
1046 | uint32_t size = acpi_data_len(data); | |
1047 | ||
1048 | /* Make sure RAM size is correct - in case it got changed | |
1049 | * e.g. by migration */ | |
1050 | memory_region_ram_resize(mr, size, &error_abort); | |
1051 | ||
1052 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
1053 | memory_region_set_dirty(mr, 0, size); | |
1054 | } | |
1055 | ||
3f8752b4 | 1056 | static void virt_acpi_build_update(void *build_opaque) |
f5d8c8cd SZ |
1057 | { |
1058 | AcpiBuildState *build_state = build_opaque; | |
1059 | AcpiBuildTables tables; | |
1060 | ||
1061 | /* No state to update or already patched? Nothing to do. */ | |
1062 | if (!build_state || build_state->patched) { | |
1063 | return; | |
1064 | } | |
1065 | build_state->patched = true; | |
1066 | ||
1067 | acpi_build_tables_init(&tables); | |
1068 | ||
4dad9e74 | 1069 | virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); |
f5d8c8cd SZ |
1070 | |
1071 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
1072 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
0e9b9eda | 1073 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
f5d8c8cd | 1074 | |
f5d8c8cd SZ |
1075 | acpi_build_tables_cleanup(&tables, true); |
1076 | } | |
1077 | ||
1078 | static void virt_acpi_build_reset(void *build_opaque) | |
1079 | { | |
1080 | AcpiBuildState *build_state = build_opaque; | |
1081 | build_state->patched = false; | |
1082 | } | |
1083 | ||
f5d8c8cd SZ |
1084 | static const VMStateDescription vmstate_virt_acpi_build = { |
1085 | .name = "virt_acpi_build", | |
1086 | .version_id = 1, | |
1087 | .minimum_version_id = 1, | |
607ef570 | 1088 | .fields = (const VMStateField[]) { |
f5d8c8cd SZ |
1089 | VMSTATE_BOOL(patched, AcpiBuildState), |
1090 | VMSTATE_END_OF_LIST() | |
1091 | }, | |
1092 | }; | |
1093 | ||
e9a8e474 | 1094 | void virt_acpi_setup(VirtMachineState *vms) |
f5d8c8cd SZ |
1095 | { |
1096 | AcpiBuildTables tables; | |
1097 | AcpiBuildState *build_state; | |
a08a6462 | 1098 | AcpiGedState *acpi_ged_state; |
f5d8c8cd | 1099 | |
af1f60a4 | 1100 | if (!vms->fw_cfg) { |
f5d8c8cd SZ |
1101 | trace_virt_acpi_setup(); |
1102 | return; | |
1103 | } | |
1104 | ||
17e89077 | 1105 | if (!virt_is_acpi_enabled(vms)) { |
f5d8c8cd SZ |
1106 | trace_virt_acpi_setup(); |
1107 | return; | |
1108 | } | |
1109 | ||
1110 | build_state = g_malloc0(sizeof *build_state); | |
f5d8c8cd SZ |
1111 | |
1112 | acpi_build_tables_init(&tables); | |
da4f09a7 | 1113 | virt_acpi_build(vms, &tables); |
f5d8c8cd SZ |
1114 | |
1115 | /* Now expose it all to Guest */ | |
82f76c67 WY |
1116 | build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1117 | build_state, tables.table_data, | |
6930ba0d | 1118 | ACPI_BUILD_TABLE_FILE); |
f5d8c8cd SZ |
1119 | assert(build_state->table_mr != NULL); |
1120 | ||
6930ba0d DH |
1121 | build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1122 | build_state, | |
1123 | tables.linker->cmd_blob, | |
1124 | ACPI_BUILD_LOADER_FILE); | |
f5d8c8cd | 1125 | |
af1f60a4 AJ |
1126 | fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, |
1127 | acpi_data_len(tables.tcpalog)); | |
f5d8c8cd | 1128 | |
a08a6462 DG |
1129 | if (vms->ras) { |
1130 | assert(vms->acpi_dev); | |
1131 | acpi_ged_state = ACPI_GED(vms->acpi_dev); | |
1132 | acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, | |
1133 | vms->fw_cfg, tables.hardware_errors); | |
1134 | } | |
1135 | ||
82f76c67 WY |
1136 | build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1137 | build_state, tables.rsdp, | |
6930ba0d | 1138 | ACPI_BUILD_RSDP_FILE); |
f5d8c8cd SZ |
1139 | |
1140 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
1141 | virt_acpi_build_reset(build_state); | |
1142 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
1143 | ||
1144 | /* Cleanup tables but don't free the memory: we track it | |
1145 | * in build_state. | |
1146 | */ | |
1147 | acpi_build_tables_cleanup(&tables, false); | |
1148 | } |