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f5d8c8cd SZ |
1 | /* Support for generating ACPI tables and passing them to Guests |
2 | * | |
3 | * ARM virt ACPI generation | |
4 | * | |
5 | * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> | |
6 | * Copyright (C) 2006 Fabrice Bellard | |
7 | * Copyright (C) 2013 Red Hat Inc | |
8 | * | |
9 | * Author: Michael S. Tsirkin <mst@redhat.com> | |
10 | * | |
11 | * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. | |
12 | * | |
13 | * Author: Shannon Zhao <zhaoshenglong@huawei.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | ||
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | ||
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
12b16722 | 29 | #include "qemu/osdep.h" |
da34e65c | 30 | #include "qapi/error.h" |
f5d8c8cd SZ |
31 | #include "qemu/bitmap.h" |
32 | #include "trace.h" | |
2e5b09fd | 33 | #include "hw/core/cpu.h" |
fcf5ef2a | 34 | #include "target/arm/cpu.h" |
f5d8c8cd SZ |
35 | #include "hw/acpi/acpi-defs.h" |
36 | #include "hw/acpi/acpi.h" | |
37 | #include "hw/nvram/fw_cfg.h" | |
38 | #include "hw/acpi/bios-linker-loader.h" | |
f5d8c8cd | 39 | #include "hw/acpi/aml-build.h" |
82f76c67 | 40 | #include "hw/acpi/utils.h" |
48cefd94 | 41 | #include "hw/acpi/pci.h" |
cff51ac9 SK |
42 | #include "hw/acpi/memory_hotplug.h" |
43 | #include "hw/acpi/generic_event_device.h" | |
80bde693 | 44 | #include "hw/acpi/tpm.h" |
84344884 | 45 | #include "hw/pci/pcie_host.h" |
d4e5de1a | 46 | #include "hw/pci/pci.h" |
42e0f050 | 47 | #include "hw/pci/pci_bus.h" |
06d2dd49 | 48 | #include "hw/pci-host/gpex.h" |
d05fdab4 | 49 | #include "hw/arm/virt.h" |
b5a60bee | 50 | #include "hw/mem/nvdimm.h" |
5ab540e9 | 51 | #include "hw/platform-bus.h" |
2b302e1e | 52 | #include "sysemu/numa.h" |
71e8a915 | 53 | #include "sysemu/reset.h" |
80bde693 | 54 | #include "sysemu/tpm.h" |
13e5c54d | 55 | #include "kvm_arm.h" |
d6454270 | 56 | #include "migration/vmstate.h" |
aa16508f | 57 | #include "hw/acpi/ghes.h" |
f5d8c8cd | 58 | |
dfccd8cf SZ |
59 | #define ARM_SPI_BASE 32 |
60 | ||
451b1570 YM |
61 | #define ACPI_BUILD_TABLE_SIZE 0x20000 |
62 | ||
9cd07db9 | 63 | static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) |
dfccd8cf | 64 | { |
9cd07db9 | 65 | MachineState *ms = MACHINE(vms); |
dfccd8cf SZ |
66 | uint16_t i; |
67 | ||
9cd07db9 | 68 | for (i = 0; i < ms->smp.cpus; i++) { |
f460be43 | 69 | Aml *dev = aml_device("C%.03X", i); |
dfccd8cf SZ |
70 | aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); |
71 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
72 | aml_append(scope, dev); | |
73 | } | |
74 | } | |
75 | ||
76 | static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, | |
45fcf539 | 77 | uint32_t uart_irq) |
dfccd8cf SZ |
78 | { |
79 | Aml *dev = aml_device("COM0"); | |
80 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011"))); | |
81 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
82 | ||
83 | Aml *crs = aml_resource_template(); | |
84 | aml_append(crs, aml_memory32_fixed(uart_memmap->base, | |
85 | uart_memmap->size, AML_READ_WRITE)); | |
86 | aml_append(crs, | |
87 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 88 | AML_EXCLUSIVE, &uart_irq, 1)); |
dfccd8cf | 89 | aml_append(dev, aml_name_decl("_CRS", crs)); |
f264d51d | 90 | |
dfccd8cf SZ |
91 | aml_append(scope, dev); |
92 | } | |
93 | ||
70bee80d GS |
94 | static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) |
95 | { | |
96 | Aml *dev = aml_device("FWCF"); | |
97 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); | |
98 | /* device present, functioning, decoding, not shown in UI */ | |
99 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | |
3b5c492b | 100 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
70bee80d GS |
101 | |
102 | Aml *crs = aml_resource_template(); | |
103 | aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, | |
104 | fw_cfg_memmap->size, AML_READ_WRITE)); | |
105 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
106 | aml_append(scope, dev); | |
107 | } | |
108 | ||
dfccd8cf SZ |
109 | static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) |
110 | { | |
111 | Aml *dev, *crs; | |
112 | hwaddr base = flash_memmap->base; | |
cd37aaf8 | 113 | hwaddr size = flash_memmap->size / 2; |
dfccd8cf SZ |
114 | |
115 | dev = aml_device("FLS0"); | |
116 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
117 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
118 | ||
119 | crs = aml_resource_template(); | |
120 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
121 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
122 | aml_append(scope, dev); | |
123 | ||
124 | dev = aml_device("FLS1"); | |
125 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); | |
126 | aml_append(dev, aml_name_decl("_UID", aml_int(1))); | |
127 | crs = aml_resource_template(); | |
128 | aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE)); | |
129 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
130 | aml_append(scope, dev); | |
131 | } | |
132 | ||
133 | static void acpi_dsdt_add_virtio(Aml *scope, | |
134 | const MemMapEntry *virtio_mmio_memmap, | |
45fcf539 | 135 | uint32_t mmio_irq, int num) |
dfccd8cf SZ |
136 | { |
137 | hwaddr base = virtio_mmio_memmap->base; | |
138 | hwaddr size = virtio_mmio_memmap->size; | |
dfccd8cf SZ |
139 | int i; |
140 | ||
141 | for (i = 0; i < num; i++) { | |
45fcf539 | 142 | uint32_t irq = mmio_irq + i; |
dfccd8cf SZ |
143 | Aml *dev = aml_device("VR%02u", i); |
144 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); | |
145 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | |
76266d99 | 146 | aml_append(dev, aml_name_decl("_CCA", aml_int(1))); |
dfccd8cf SZ |
147 | |
148 | Aml *crs = aml_resource_template(); | |
149 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | |
150 | aml_append(crs, | |
151 | aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
45fcf539 | 152 | AML_EXCLUSIVE, &irq, 1)); |
dfccd8cf SZ |
153 | aml_append(dev, aml_name_decl("_CRS", crs)); |
154 | aml_append(scope, dev); | |
155 | base += size; | |
156 | } | |
157 | } | |
158 | ||
45fcf539 | 159 | static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, |
6f9765fb YM |
160 | uint32_t irq, bool use_highmem, bool highmem_ecam, |
161 | VirtMachineState *vms) | |
d4e5de1a | 162 | { |
601d626d | 163 | int ecam_id = VIRT_ECAM_ID(highmem_ecam); |
06d2dd49 GH |
164 | struct GPEXConfig cfg = { |
165 | .mmio32 = memmap[VIRT_PCIE_MMIO], | |
166 | .pio = memmap[VIRT_PCIE_PIO], | |
167 | .ecam = memmap[ecam_id], | |
168 | .irq = irq, | |
6f9765fb | 169 | .bus = vms->bus, |
06d2dd49 | 170 | }; |
d4e5de1a | 171 | |
5125f9cd | 172 | if (use_highmem) { |
06d2dd49 | 173 | cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; |
5125f9cd PF |
174 | } |
175 | ||
06d2dd49 | 176 | acpi_dsdt_add_gpex(scope, &cfg); |
d4e5de1a SZ |
177 | } |
178 | ||
aeb1a36d SZ |
179 | static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, |
180 | uint32_t gpio_irq) | |
181 | { | |
182 | Aml *dev = aml_device("GPO0"); | |
183 | aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); | |
aeb1a36d SZ |
184 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); |
185 | ||
186 | Aml *crs = aml_resource_template(); | |
187 | aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size, | |
188 | AML_READ_WRITE)); | |
189 | aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, | |
190 | AML_EXCLUSIVE, &gpio_irq, 1)); | |
191 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
c1a158b7 SZ |
192 | |
193 | Aml *aei = aml_resource_template(); | |
194 | /* Pin 3 for power button */ | |
195 | const uint32_t pin_list[1] = {3}; | |
196 | aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH, | |
197 | AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1, | |
198 | "GPO0", NULL, 0)); | |
199 | aml_append(dev, aml_name_decl("_AEI", aei)); | |
200 | ||
201 | /* _E03 is handle for power button */ | |
202 | Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED); | |
203 | aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), | |
204 | aml_int(0x80))); | |
205 | aml_append(dev, method); | |
aeb1a36d SZ |
206 | aml_append(scope, dev); |
207 | } | |
208 | ||
f50be48a | 209 | #ifdef CONFIG_TPM |
5ab540e9 EA |
210 | static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms) |
211 | { | |
212 | PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); | |
213 | hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; | |
214 | SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); | |
215 | MemoryRegion *sbdev_mr; | |
216 | hwaddr tpm_base; | |
217 | ||
218 | if (!sbdev) { | |
219 | return; | |
220 | } | |
221 | ||
222 | tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); | |
223 | assert(tpm_base != -1); | |
224 | ||
225 | tpm_base += pbus_base; | |
226 | ||
227 | sbdev_mr = sysbus_mmio_get_region(sbdev, 0); | |
228 | ||
229 | Aml *dev = aml_device("TPM0"); | |
230 | aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); | |
231 | aml_append(dev, aml_name_decl("_UID", aml_int(0))); | |
232 | ||
233 | Aml *crs = aml_resource_template(); | |
234 | aml_append(crs, | |
235 | aml_memory32_fixed(tpm_base, | |
236 | (uint32_t)memory_region_size(sbdev_mr), | |
237 | AML_READ_WRITE)); | |
238 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
239 | aml_append(scope, dev); | |
240 | } | |
f50be48a | 241 | #endif |
5ab540e9 | 242 | |
271cbb2f IM |
243 | #define ID_MAPPING_ENTRY_SIZE 20 |
244 | #define SMMU_V3_ENTRY_SIZE 60 | |
245 | #define ROOT_COMPLEX_ENTRY_SIZE 32 | |
246 | #define IORT_NODE_OFFSET 48 | |
247 | ||
248 | static void build_iort_id_mapping(GArray *table_data, uint32_t input_base, | |
249 | uint32_t id_count, uint32_t out_ref) | |
250 | { | |
251 | /* Identity RID mapping covering the whole input RID range */ | |
252 | build_append_int_noprefix(table_data, input_base, 4); /* Input base */ | |
253 | build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */ | |
254 | build_append_int_noprefix(table_data, input_base, 4); /* Output base */ | |
255 | build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */ | |
256 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ | |
257 | } | |
258 | ||
259 | struct AcpiIortIdMapping { | |
260 | uint32_t input_base; | |
261 | uint32_t id_count; | |
262 | }; | |
263 | typedef struct AcpiIortIdMapping AcpiIortIdMapping; | |
264 | ||
42e0f050 XW |
265 | /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ |
266 | static int | |
267 | iort_host_bridges(Object *obj, void *opaque) | |
268 | { | |
269 | GArray *idmap_blob = opaque; | |
270 | ||
271 | if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { | |
272 | PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; | |
273 | ||
274 | if (bus && !pci_bus_bypass_iommu(bus)) { | |
275 | int min_bus, max_bus; | |
276 | ||
277 | pci_bus_range(bus, &min_bus, &max_bus); | |
278 | ||
279 | AcpiIortIdMapping idmap = { | |
280 | .input_base = min_bus << 8, | |
281 | .id_count = (max_bus - min_bus + 1) << 8, | |
282 | }; | |
283 | g_array_append_val(idmap_blob, idmap); | |
284 | } | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | static int iort_idmap_compare(gconstpointer a, gconstpointer b) | |
291 | { | |
292 | AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a; | |
293 | AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b; | |
294 | ||
295 | return idmap_a->input_base - idmap_b->input_base; | |
296 | } | |
297 | ||
3548494e IM |
298 | /* |
299 | * Input Output Remapping Table (IORT) | |
300 | * Conforms to "IO Remapping Table System Software on ARM Platforms", | |
301 | * Document number: ARM DEN 0049B, October 2015 | |
302 | */ | |
e78f1222 | 303 | static void |
a703b4f6 | 304 | build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
e78f1222 | 305 | { |
3548494e | 306 | int i, nb_nodes, rc_mapping_count; |
271cbb2f | 307 | const uint32_t iort_node_offset = IORT_NODE_OFFSET; |
3548494e | 308 | size_t node_size, smmu_offset = 0; |
271cbb2f | 309 | AcpiIortIdMapping *idmap; |
42e0f050 XW |
310 | GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); |
311 | GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping)); | |
e78f1222 | 312 | |
3548494e IM |
313 | AcpiTable table = { .sig = "IORT", .rev = 0, .oem_id = vms->oem_id, |
314 | .oem_table_id = vms->oem_table_id }; | |
271cbb2f IM |
315 | /* Table 2 The IORT */ |
316 | acpi_table_begin(&table, table_data); | |
e78f1222 | 317 | |
a703b4f6 | 318 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
42e0f050 XW |
319 | AcpiIortIdMapping next_range = {0}; |
320 | ||
321 | object_child_foreach_recursive(object_get_root(), | |
322 | iort_host_bridges, smmu_idmaps); | |
323 | ||
324 | /* Sort the smmu idmap by input_base */ | |
325 | g_array_sort(smmu_idmaps, iort_idmap_compare); | |
326 | ||
327 | /* | |
328 | * Split the whole RIDs by mapping from RC to SMMU, | |
329 | * build the ID mapping from RC to ITS directly. | |
330 | */ | |
331 | for (i = 0; i < smmu_idmaps->len; i++) { | |
332 | idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); | |
333 | ||
334 | if (next_range.input_base < idmap->input_base) { | |
335 | next_range.id_count = idmap->input_base - next_range.input_base; | |
336 | g_array_append_val(its_idmaps, next_range); | |
337 | } | |
338 | ||
339 | next_range.input_base = idmap->input_base + idmap->id_count; | |
340 | } | |
341 | ||
342 | /* Append the last RC -> ITS ID mapping */ | |
343 | if (next_range.input_base < 0xFFFF) { | |
344 | next_range.id_count = 0xFFFF - next_range.input_base; | |
345 | g_array_append_val(its_idmaps, next_range); | |
346 | } | |
347 | ||
a703b4f6 | 348 | nb_nodes = 3; /* RC, ITS, SMMUv3 */ |
42e0f050 | 349 | rc_mapping_count = smmu_idmaps->len + its_idmaps->len; |
a703b4f6 PM |
350 | } else { |
351 | nb_nodes = 2; /* RC, ITS */ | |
42e0f050 | 352 | rc_mapping_count = 1; |
a703b4f6 | 353 | } |
3548494e IM |
354 | /* Number of IORT Nodes */ |
355 | build_append_int_noprefix(table_data, nb_nodes, 4); | |
271cbb2f | 356 | |
3548494e | 357 | /* Offset to Array of IORT Nodes */ |
271cbb2f | 358 | build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); |
3548494e | 359 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ |
e78f1222 | 360 | |
271cbb2f IM |
361 | /* 3.1.1.3 ITS group node */ |
362 | build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ | |
363 | node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */; | |
364 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
365 | build_append_int_noprefix(table_data, 0, 1); /* Revision */ | |
366 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
367 | build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */ | |
368 | build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */ | |
369 | build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ | |
370 | /* GIC ITS Identifier Array */ | |
371 | build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); | |
e78f1222 | 372 | |
a703b4f6 | 373 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
41c4fb94 | 374 | int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; |
a703b4f6 | 375 | |
271cbb2f IM |
376 | smmu_offset = table_data->len - table.table_offset; |
377 | /* 3.1.1.2 SMMUv3 */ | |
378 | build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */ | |
379 | node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; | |
380 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
381 | build_append_int_noprefix(table_data, 0, 1); /* Revision */ | |
382 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
383 | build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */ | |
384 | /* Reference to ID Array */ | |
385 | build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); | |
386 | /* Base address */ | |
387 | build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); | |
388 | /* Flags */ | |
389 | build_append_int_noprefix(table_data, 1 /* COHACC OverrideNote */, 4); | |
390 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
391 | build_append_int_noprefix(table_data, 0, 8); /* VATOS address */ | |
392 | /* Model */ | |
393 | build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4); | |
394 | build_append_int_noprefix(table_data, irq, 4); /* Event */ | |
395 | build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */ | |
396 | build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */ | |
397 | build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */ | |
398 | ||
a703b4f6 | 399 | /* output IORT node is the ITS group node (the first node) */ |
271cbb2f | 400 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); |
a703b4f6 PM |
401 | } |
402 | ||
271cbb2f IM |
403 | /* Table 16 Root Complex Node */ |
404 | build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */ | |
405 | node_size = ROOT_COMPLEX_ENTRY_SIZE + | |
406 | ID_MAPPING_ENTRY_SIZE * rc_mapping_count; | |
407 | build_append_int_noprefix(table_data, node_size, 2); /* Length */ | |
408 | build_append_int_noprefix(table_data, 0, 1); /* Revision */ | |
409 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
410 | /* Number of ID mappings */ | |
411 | build_append_int_noprefix(table_data, rc_mapping_count, 4); | |
412 | /* Reference to ID Array */ | |
413 | build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4); | |
414 | ||
415 | /* Table 13 Memory access properties */ | |
416 | /* CCA: Cache Coherent Attribute */ | |
417 | build_append_int_noprefix(table_data, 1 /* fully coherent */, 4); | |
418 | build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */ | |
419 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
420 | /* MAF: Note Memory Access Flags */ | |
421 | build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DCAS = 1 */, 1); | |
422 | ||
423 | build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */ | |
424 | /* MCFG pci_segment */ | |
425 | build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */ | |
426 | ||
427 | /* Output Reference */ | |
a703b4f6 | 428 | if (vms->iommu == VIRT_IOMMU_SMMUV3) { |
42e0f050 XW |
429 | AcpiIortIdMapping *range; |
430 | ||
431 | /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ | |
432 | for (i = 0; i < smmu_idmaps->len; i++) { | |
42e0f050 | 433 | range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); |
42e0f050 | 434 | /* output IORT node is the smmuv3 node */ |
271cbb2f IM |
435 | build_iort_id_mapping(table_data, range->input_base, |
436 | range->id_count, smmu_offset); | |
42e0f050 XW |
437 | } |
438 | ||
439 | /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ | |
440 | for (i = 0; i < its_idmaps->len; i++) { | |
42e0f050 | 441 | range = &g_array_index(its_idmaps, AcpiIortIdMapping, i); |
42e0f050 | 442 | /* output IORT node is the ITS group node (the first node) */ |
271cbb2f IM |
443 | build_iort_id_mapping(table_data, range->input_base, |
444 | range->id_count, iort_node_offset); | |
42e0f050 | 445 | } |
a703b4f6 PM |
446 | } else { |
447 | /* output IORT node is the ITS group node (the first node) */ | |
271cbb2f | 448 | build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET); |
a703b4f6 | 449 | } |
e78f1222 | 450 | |
3548494e | 451 | acpi_table_end(linker, &table); |
42e0f050 XW |
452 | g_array_free(smmu_idmaps, true); |
453 | g_array_free(its_idmaps, true); | |
e78f1222 PM |
454 | } |
455 | ||
a86d86ac IM |
456 | /* |
457 | * Serial Port Console Redirection Table (SPCR) | |
458 | * Rev: 1.07 | |
459 | */ | |
f264d51d | 460 | static void |
da4f09a7 | 461 | build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
f264d51d | 462 | { |
a86d86ac IM |
463 | AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id, |
464 | .oem_table_id = vms->oem_table_id }; | |
f264d51d | 465 | |
a86d86ac | 466 | acpi_table_begin(&table, table_data); |
f264d51d | 467 | |
a86d86ac IM |
468 | /* Interface Type */ |
469 | build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ | |
470 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
471 | /* Base Address */ | |
472 | build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, | |
473 | vms->memmap[VIRT_UART].base); | |
474 | /* Interrupt Type */ | |
475 | build_append_int_noprefix(table_data, | |
476 | (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); | |
477 | build_append_int_noprefix(table_data, 0, 1); /* IRQ */ | |
478 | /* Global System Interrupt */ | |
479 | build_append_int_noprefix(table_data, | |
480 | vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); | |
481 | build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ | |
482 | build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */ | |
483 | /* Stop Bits */ | |
484 | build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1); | |
485 | /* Flow Control */ | |
486 | build_append_int_noprefix(table_data, | |
487 | (1 << 1) /* RTS/CTS hardware flow control */, 1); | |
488 | /* Terminal Type */ | |
489 | build_append_int_noprefix(table_data, 0 /* VT100 */, 1); | |
490 | build_append_int_noprefix(table_data, 0, 1); /* Language */ | |
491 | /* PCI Device ID */ | |
492 | build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); | |
493 | /* PCI Vendor ID */ | |
494 | build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); | |
495 | build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */ | |
496 | build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */ | |
497 | build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */ | |
498 | build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */ | |
499 | build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */ | |
500 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
f264d51d | 501 | |
a86d86ac | 502 | acpi_table_end(linker, &table); |
f264d51d AJ |
503 | } |
504 | ||
e5b6d55a IM |
505 | /* |
506 | * ACPI spec, Revision 5.1 | |
507 | * 5.2.16 System Resource Affinity Table (SRAT) | |
508 | */ | |
2b302e1e | 509 | static void |
da4f09a7 | 510 | build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
2b302e1e | 511 | { |
255bf20f | 512 | int i; |
2b302e1e | 513 | uint64_t mem_base; |
4ccf5826 | 514 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
aa570207 TX |
515 | MachineState *ms = MACHINE(vms); |
516 | const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); | |
255bf20f IM |
517 | AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, |
518 | .oem_table_id = vms->oem_table_id }; | |
2b302e1e | 519 | |
255bf20f IM |
520 | acpi_table_begin(&table, table_data); |
521 | build_append_int_noprefix(table_data, 1, 4); /* Reserved */ | |
522 | build_append_int_noprefix(table_data, 0, 8); /* Reserved */ | |
2b302e1e | 523 | |
4ccf5826 | 524 | for (i = 0; i < cpu_list->len; ++i) { |
e5b6d55a IM |
525 | uint32_t nodeid = cpu_list->cpus[i].props.node_id; |
526 | /* | |
527 | * 5.2.16.4 GICC Affinity Structure | |
528 | */ | |
529 | build_append_int_noprefix(table_data, 3, 1); /* Type */ | |
530 | build_append_int_noprefix(table_data, 18, 1); /* Length */ | |
531 | build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ | |
532 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
533 | /* Flags, Table 5-76 */ | |
534 | build_append_int_noprefix(table_data, 1 /* Enabled */, 4); | |
535 | build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ | |
2b302e1e | 536 | } |
2b302e1e | 537 | |
da4f09a7 | 538 | mem_base = vms->memmap[VIRT_MEM].base; |
aa570207 | 539 | for (i = 0; i < ms->numa_state->num_nodes; ++i) { |
7e721e7b | 540 | if (ms->numa_state->nodes[i].node_mem > 0) { |
e5b6d55a | 541 | build_srat_memory(table_data, mem_base, |
7e721e7b | 542 | ms->numa_state->nodes[i].node_mem, i, |
66c353ce | 543 | MEM_AFFINITY_ENABLED); |
7e721e7b | 544 | mem_base += ms->numa_state->nodes[i].node_mem; |
66c353ce | 545 | } |
2b302e1e SZ |
546 | } |
547 | ||
c3b0cf6e VV |
548 | if (ms->nvdimms_state->is_enabled) { |
549 | nvdimm_build_srat(table_data); | |
550 | } | |
551 | ||
442da7dc | 552 | if (ms->device_memory) { |
e5b6d55a | 553 | build_srat_memory(table_data, ms->device_memory->base, |
442da7dc SK |
554 | memory_region_size(&ms->device_memory->mr), |
555 | ms->numa_state->num_nodes - 1, | |
556 | MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); | |
557 | } | |
558 | ||
255bf20f | 559 | acpi_table_end(linker, &table); |
2b302e1e SZ |
560 | } |
561 | ||
ee246400 SZ |
562 | /* GTDT */ |
563 | static void | |
8dd845d3 | 564 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
ee246400 | 565 | { |
8dd845d3 | 566 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
ee246400 SZ |
567 | int gtdt_start = table_data->len; |
568 | AcpiGenericTimerTable *gtdt; | |
8dd845d3 AJ |
569 | uint32_t irqflags; |
570 | ||
571 | if (vmc->claim_edge_triggered_timers) { | |
572 | irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE; | |
573 | } else { | |
574 | irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL; | |
575 | } | |
ee246400 SZ |
576 | |
577 | gtdt = acpi_data_push(table_data, sizeof *gtdt); | |
578 | /* The interrupt values are the same with the device tree when adding 16 */ | |
330afe05 | 579 | gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16); |
8dd845d3 | 580 | gtdt->secure_el1_flags = cpu_to_le32(irqflags); |
ee246400 | 581 | |
330afe05 | 582 | gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16); |
8dd845d3 | 583 | gtdt->non_secure_el1_flags = cpu_to_le32(irqflags | |
aca4bbf4 | 584 | ACPI_GTDT_CAP_ALWAYS_ON); |
ee246400 | 585 | |
330afe05 | 586 | gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16); |
8dd845d3 | 587 | gtdt->virtual_timer_flags = cpu_to_le32(irqflags); |
ee246400 | 588 | |
330afe05 | 589 | gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16); |
8dd845d3 | 590 | gtdt->non_secure_el2_flags = cpu_to_le32(irqflags); |
ee246400 SZ |
591 | |
592 | build_header(linker, table_data, | |
593 | (void *)(table_data->data + gtdt_start), "GTDT", | |
602b4582 MP |
594 | table_data->len - gtdt_start, 2, vms->oem_id, |
595 | vms->oem_table_id); | |
ee246400 SZ |
596 | } |
597 | ||
99a7545f | 598 | /* |
37f33084 | 599 | * ACPI spec, Revision 5.1 Errata A |
99a7545f IM |
600 | * 5.2.12 Multiple APIC Description Table (MADT) |
601 | */ | |
37f33084 IM |
602 | static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size) |
603 | { | |
604 | build_append_int_noprefix(table_data, 0xE, 1); /* Type */ | |
605 | build_append_int_noprefix(table_data, 16, 1); /* Length */ | |
606 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
607 | /* Discovery Range Base Addres */ | |
608 | build_append_int_noprefix(table_data, base, 8); | |
609 | build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */ | |
610 | } | |
611 | ||
982d06c5 | 612 | static void |
da4f09a7 | 613 | build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
982d06c5 | 614 | { |
37f33084 | 615 | int i; |
da4f09a7 | 616 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
da4f09a7 | 617 | const MemMapEntry *memmap = vms->memmap; |
99a7545f IM |
618 | AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = vms->oem_id, |
619 | .oem_table_id = vms->oem_table_id }; | |
982d06c5 | 620 | |
99a7545f IM |
621 | acpi_table_begin(&table, table_data); |
622 | /* Local Interrupt Controller Address */ | |
623 | build_append_int_noprefix(table_data, 0, 4); | |
37f33084 IM |
624 | build_append_int_noprefix(table_data, 0, 4); /* Flags */ |
625 | ||
626 | /* 5.2.12.15 GIC Distributor Structure */ | |
627 | build_append_int_noprefix(table_data, 0xC, 1); /* Type */ | |
628 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
629 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
630 | build_append_int_noprefix(table_data, 0, 4); /* GIC ID */ | |
631 | /* Physical Base Address */ | |
632 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8); | |
633 | build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */ | |
634 | /* GIC version */ | |
635 | build_append_int_noprefix(table_data, vms->gic_version, 1); | |
636 | build_append_int_noprefix(table_data, 0, 3); /* Reserved */ | |
982d06c5 | 637 | |
9cd07db9 | 638 | for (i = 0; i < MACHINE(vms)->smp.cpus; i++) { |
5d9c1756 | 639 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); |
37f33084 IM |
640 | uint64_t physical_base_address = 0, gich = 0, gicv = 0; |
641 | uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0; | |
642 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? | |
643 | PPI(VIRTUAL_PMU_IRQ) : 0; | |
5d9c1756 | 644 | |
da4f09a7 | 645 | if (vms->gic_version == 2) { |
37f33084 IM |
646 | physical_base_address = memmap[VIRT_GIC_CPU].base; |
647 | gicv = memmap[VIRT_GIC_VCPU].base; | |
648 | gich = memmap[VIRT_GIC_HYP].base; | |
f2fbface | 649 | } |
8433dee0 | 650 | |
37f33084 IM |
651 | /* 5.2.12.14 GIC Structure */ |
652 | build_append_int_noprefix(table_data, 0xB, 1); /* Type */ | |
653 | build_append_int_noprefix(table_data, 76, 1); /* Length */ | |
654 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
655 | build_append_int_noprefix(table_data, i, 4); /* GIC ID */ | |
656 | build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ | |
657 | /* Flags */ | |
658 | build_append_int_noprefix(table_data, 1, 4); /* Enabled */ | |
659 | /* Parking Protocol Version */ | |
660 | build_append_int_noprefix(table_data, 0, 4); | |
661 | /* Performance Interrupt GSIV */ | |
662 | build_append_int_noprefix(table_data, pmu_interrupt, 4); | |
663 | build_append_int_noprefix(table_data, 0, 8); /* Parked Address */ | |
664 | /* Physical Base Address */ | |
665 | build_append_int_noprefix(table_data, physical_base_address, 8); | |
666 | build_append_int_noprefix(table_data, gicv, 8); /* GICV */ | |
667 | build_append_int_noprefix(table_data, gich, 8); /* GICH */ | |
668 | /* VGIC Maintenance interrupt */ | |
669 | build_append_int_noprefix(table_data, vgic_interrupt, 4); | |
670 | build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ | |
671 | /* MPIDR */ | |
672 | build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); | |
f2fbface SZ |
673 | } |
674 | ||
da4f09a7 | 675 | if (vms->gic_version == 3) { |
37f33084 IM |
676 | build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, |
677 | memmap[VIRT_GIC_REDIST].size); | |
678 | if (virt_gicv3_redist_region_count(vms) == 2) { | |
679 | build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base, | |
680 | memmap[VIRT_HIGH_GIC_REDIST2].size); | |
a1de312f EA |
681 | } |
682 | ||
da4f09a7 | 683 | if (its_class_name() && !vmc->no_its) { |
37f33084 IM |
684 | /* |
685 | * FIXME: Structure is from Revision 6.0 where 'GIC Structure' | |
686 | * has additional fields on top of implemented 5.1 Errata A, | |
687 | * to make it consistent with v6.0 we need to bump everything | |
688 | * to v6.0 | |
689 | */ | |
690 | /* | |
691 | * ACPI spec, Revision 6.0 Errata A | |
692 | * (original 6.0 definition has invalid Length) | |
693 | * 5.2.12.18 GIC ITS Structure | |
694 | */ | |
695 | build_append_int_noprefix(table_data, 0xF, 1); /* Type */ | |
696 | build_append_int_noprefix(table_data, 20, 1); /* Length */ | |
697 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
698 | build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ | |
699 | /* Physical Base Address */ | |
700 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8); | |
701 | build_append_int_noprefix(table_data, 0, 4); /* Reserved */ | |
13e5c54d | 702 | } |
b92ad394 | 703 | } else { |
37f33084 IM |
704 | const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE; |
705 | ||
706 | /* 5.2.12.16 GIC MSI Frame Structure */ | |
707 | build_append_int_noprefix(table_data, 0xD, 1); /* Type */ | |
708 | build_append_int_noprefix(table_data, 24, 1); /* Length */ | |
709 | build_append_int_noprefix(table_data, 0, 2); /* Reserved */ | |
710 | build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */ | |
711 | /* Physical Base Address */ | |
712 | build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8); | |
713 | build_append_int_noprefix(table_data, 1, 4); /* Flags */ | |
714 | /* SPI Count */ | |
715 | build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2); | |
716 | build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */ | |
b92ad394 | 717 | } |
99a7545f | 718 | acpi_table_end(linker, &table); |
982d06c5 SZ |
719 | } |
720 | ||
c2f7c0c3 | 721 | /* FADT */ |
8612f8bd IM |
722 | static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, |
723 | VirtMachineState *vms, unsigned dsdt_tbl_offset) | |
c2f7c0c3 | 724 | { |
dd1b2037 IM |
725 | /* ACPI v5.1 */ |
726 | AcpiFadtData fadt = { | |
727 | .rev = 5, | |
728 | .minor_ver = 1, | |
729 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, | |
730 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | |
731 | }; | |
79e993a0 AJ |
732 | |
733 | switch (vms->psci_conduit) { | |
734 | case QEMU_PSCI_CONDUIT_DISABLED: | |
dd1b2037 | 735 | fadt.arm_boot_arch = 0; |
79e993a0 AJ |
736 | break; |
737 | case QEMU_PSCI_CONDUIT_HVC: | |
dd1b2037 IM |
738 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT | |
739 | ACPI_FADT_ARM_PSCI_USE_HVC; | |
79e993a0 AJ |
740 | break; |
741 | case QEMU_PSCI_CONDUIT_SMC: | |
dd1b2037 | 742 | fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT; |
79e993a0 AJ |
743 | break; |
744 | default: | |
745 | g_assert_not_reached(); | |
746 | } | |
c2f7c0c3 | 747 | |
602b4582 | 748 | build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); |
c2f7c0c3 SZ |
749 | } |
750 | ||
dfccd8cf SZ |
751 | /* DSDT */ |
752 | static void | |
da4f09a7 | 753 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
dfccd8cf | 754 | { |
2c1fb4d5 | 755 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
dfccd8cf | 756 | Aml *scope, *dsdt; |
cff51ac9 | 757 | MachineState *ms = MACHINE(vms); |
da4f09a7 AJ |
758 | const MemMapEntry *memmap = vms->memmap; |
759 | const int *irqmap = vms->irqmap; | |
fc02b869 IM |
760 | AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id, |
761 | .oem_table_id = vms->oem_table_id }; | |
dfccd8cf | 762 | |
fc02b869 | 763 | acpi_table_begin(&table, table_data); |
dfccd8cf | 764 | dsdt = init_aml_allocator(); |
dfccd8cf | 765 | |
67736a25 SZ |
766 | /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. |
767 | * While UEFI can use libfdt to disable the RTC device node in the DTB that | |
768 | * it passes to the OS, it cannot modify AML. Therefore, we won't generate | |
769 | * the RTC ACPI device at all when using UEFI. | |
770 | */ | |
dfccd8cf | 771 | scope = aml_scope("\\_SB"); |
9cd07db9 | 772 | acpi_dsdt_add_cpus(scope, vms); |
dfccd8cf SZ |
773 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], |
774 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | |
2c1fb4d5 AJ |
775 | if (vmc->acpi_expose_flash) { |
776 | acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | |
777 | } | |
70bee80d | 778 | acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); |
dfccd8cf SZ |
779 | acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], |
780 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); | |
5125f9cd | 781 | acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), |
6f9765fb | 782 | vms->highmem, vms->highmem_ecam, vms); |
cff51ac9 SK |
783 | if (vms->acpi_dev) { |
784 | build_ged_aml(scope, "\\_SB."GED_DEVICE, | |
785 | HOTPLUG_HANDLER(vms->acpi_dev), | |
786 | irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY, | |
787 | memmap[VIRT_ACPI_GED].base); | |
1962f31b SK |
788 | } else { |
789 | acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], | |
790 | (irqmap[VIRT_GPIO] + ARM_SPI_BASE)); | |
cff51ac9 SK |
791 | } |
792 | ||
793 | if (vms->acpi_dev) { | |
794 | uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev), | |
795 | "ged-event", &error_abort); | |
796 | ||
797 | if (event & ACPI_GED_MEM_HOTPLUG_EVT) { | |
798 | build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL, | |
799 | AML_SYSTEM_MEMORY, | |
800 | memmap[VIRT_PCDIMM_ACPI].base); | |
801 | } | |
802 | } | |
803 | ||
ac6aa59a | 804 | acpi_dsdt_add_power_button(scope); |
f50be48a | 805 | #ifdef CONFIG_TPM |
5ab540e9 | 806 | acpi_dsdt_add_tpm(scope, vms); |
f50be48a | 807 | #endif |
d4e5de1a | 808 | |
dfccd8cf SZ |
809 | aml_append(dsdt, scope); |
810 | ||
fc02b869 | 811 | /* copy AML table into ACPI tables blob */ |
dfccd8cf | 812 | g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); |
fc02b869 IM |
813 | |
814 | acpi_table_end(linker, &table); | |
dfccd8cf SZ |
815 | free_aml_allocator(); |
816 | } | |
817 | ||
f5d8c8cd SZ |
818 | typedef |
819 | struct AcpiBuildState { | |
820 | /* Copy of table in RAM (for patching). */ | |
821 | MemoryRegion *table_mr; | |
822 | MemoryRegion *rsdp_mr; | |
823 | MemoryRegion *linker_mr; | |
824 | /* Is table patched? */ | |
825 | bool patched; | |
f5d8c8cd SZ |
826 | } AcpiBuildState; |
827 | ||
451b1570 YM |
828 | static void acpi_align_size(GArray *blob, unsigned align) |
829 | { | |
830 | /* | |
831 | * Align size to multiple of given size. This reduces the chance | |
832 | * we need to change size in the future (breaking cross version migration). | |
833 | */ | |
834 | g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); | |
835 | } | |
836 | ||
f5d8c8cd | 837 | static |
da4f09a7 | 838 | void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
f5d8c8cd | 839 | { |
da4f09a7 | 840 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
f5d8c8cd | 841 | GArray *table_offsets; |
cb51ac2f | 842 | unsigned dsdt, xsdt; |
dfccd8cf | 843 | GArray *tables_blob = tables->table_data; |
aa570207 | 844 | MachineState *ms = MACHINE(vms); |
f5d8c8cd SZ |
845 | |
846 | table_offsets = g_array_new(false, true /* clear */, | |
847 | sizeof(uint32_t)); | |
848 | ||
ad9671b8 IM |
849 | bios_linker_loader_alloc(tables->linker, |
850 | ACPI_BUILD_TABLE_FILE, tables_blob, | |
f5d8c8cd SZ |
851 | 64, false /* high memory */); |
852 | ||
dfccd8cf | 853 | /* DSDT is pointed to by FADT */ |
c2f7c0c3 | 854 | dsdt = tables_blob->len; |
da4f09a7 | 855 | build_dsdt(tables_blob, tables->linker, vms); |
dfccd8cf | 856 | |
d0652b57 | 857 | /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ |
c2f7c0c3 | 858 | acpi_add_table(table_offsets, tables_blob); |
8612f8bd | 859 | build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); |
c2f7c0c3 | 860 | |
982d06c5 | 861 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 862 | build_madt(tables_blob, tables->linker, vms); |
982d06c5 | 863 | |
ee246400 | 864 | acpi_add_table(table_offsets, tables_blob); |
8dd845d3 | 865 | build_gtdt(tables_blob, tables->linker, vms); |
ee246400 | 866 | |
84344884 | 867 | acpi_add_table(table_offsets, tables_blob); |
48cefd94 WY |
868 | { |
869 | AcpiMcfgInfo mcfg = { | |
870 | .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, | |
871 | .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, | |
872 | }; | |
602b4582 MP |
873 | build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id, |
874 | vms->oem_table_id); | |
48cefd94 | 875 | } |
84344884 | 876 | |
f264d51d | 877 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 878 | build_spcr(tables_blob, tables->linker, vms); |
f264d51d | 879 | |
aa16508f DG |
880 | if (vms->ras) { |
881 | build_ghes_error_table(tables->hardware_errors, tables->linker); | |
205cc75d | 882 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
883 | acpi_build_hest(tables_blob, tables->linker, vms->oem_id, |
884 | vms->oem_table_id); | |
aa16508f DG |
885 | } |
886 | ||
aa570207 | 887 | if (ms->numa_state->num_nodes > 0) { |
2b302e1e | 888 | acpi_add_table(table_offsets, tables_blob); |
da4f09a7 | 889 | build_srat(tables_blob, tables->linker, vms); |
118154b7 | 890 | if (ms->numa_state->have_numa_distance) { |
94a66456 | 891 | acpi_add_table(table_offsets, tables_blob); |
602b4582 MP |
892 | build_slit(tables_blob, tables->linker, ms, vms->oem_id, |
893 | vms->oem_table_id); | |
94a66456 | 894 | } |
2b302e1e SZ |
895 | } |
896 | ||
b5a60bee KL |
897 | if (ms->nvdimms_state->is_enabled) { |
898 | nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, | |
602b4582 MP |
899 | ms->nvdimms_state, ms->ram_slots, vms->oem_id, |
900 | vms->oem_table_id); | |
b5a60bee KL |
901 | } |
902 | ||
da4f09a7 | 903 | if (its_class_name() && !vmc->no_its) { |
e78f1222 | 904 | acpi_add_table(table_offsets, tables_blob); |
a703b4f6 | 905 | build_iort(tables_blob, tables->linker, vms); |
e78f1222 PM |
906 | } |
907 | ||
f50be48a | 908 | #ifdef CONFIG_TPM |
80bde693 EA |
909 | if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { |
910 | acpi_add_table(table_offsets, tables_blob); | |
602b4582 MP |
911 | build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id, |
912 | vms->oem_table_id); | |
80bde693 | 913 | } |
f50be48a | 914 | #endif |
80bde693 | 915 | |
cb51ac2f AB |
916 | /* XSDT is pointed to by RSDP */ |
917 | xsdt = tables_blob->len; | |
602b4582 MP |
918 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, |
919 | vms->oem_table_id); | |
243bdb79 | 920 | |
d4bec5d8 | 921 | /* RSDP is in FSEG memory, so allocate it separately */ |
5c5fce1a SO |
922 | { |
923 | AcpiRsdpData rsdp_data = { | |
924 | .revision = 2, | |
602b4582 | 925 | .oem_id = vms->oem_id, |
5c5fce1a SO |
926 | .xsdt_tbl_offset = &xsdt, |
927 | .rsdt_tbl_offset = NULL, | |
928 | }; | |
929 | build_rsdp(tables->rsdp, tables->linker, &rsdp_data); | |
930 | } | |
d4bec5d8 | 931 | |
451b1570 YM |
932 | /* |
933 | * The align size is 128, warn if 64k is not enough therefore | |
934 | * the align size could be resized. | |
935 | */ | |
936 | if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { | |
937 | warn_report("ACPI table size %u exceeds %d bytes," | |
938 | " migration may not work", | |
939 | tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); | |
940 | error_printf("Try removing CPUs, NUMA nodes, memory slots" | |
941 | " or PCI bridges."); | |
942 | } | |
943 | acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); | |
944 | ||
945 | ||
f5d8c8cd SZ |
946 | /* Cleanup memory that's no longer used. */ |
947 | g_array_free(table_offsets, true); | |
948 | } | |
949 | ||
950 | static void acpi_ram_update(MemoryRegion *mr, GArray *data) | |
951 | { | |
952 | uint32_t size = acpi_data_len(data); | |
953 | ||
954 | /* Make sure RAM size is correct - in case it got changed | |
955 | * e.g. by migration */ | |
956 | memory_region_ram_resize(mr, size, &error_abort); | |
957 | ||
958 | memcpy(memory_region_get_ram_ptr(mr), data->data, size); | |
959 | memory_region_set_dirty(mr, 0, size); | |
960 | } | |
961 | ||
3f8752b4 | 962 | static void virt_acpi_build_update(void *build_opaque) |
f5d8c8cd SZ |
963 | { |
964 | AcpiBuildState *build_state = build_opaque; | |
965 | AcpiBuildTables tables; | |
966 | ||
967 | /* No state to update or already patched? Nothing to do. */ | |
968 | if (!build_state || build_state->patched) { | |
969 | return; | |
970 | } | |
971 | build_state->patched = true; | |
972 | ||
973 | acpi_build_tables_init(&tables); | |
974 | ||
4dad9e74 | 975 | virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables); |
f5d8c8cd SZ |
976 | |
977 | acpi_ram_update(build_state->table_mr, tables.table_data); | |
978 | acpi_ram_update(build_state->rsdp_mr, tables.rsdp); | |
0e9b9eda | 979 | acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); |
f5d8c8cd | 980 | |
f5d8c8cd SZ |
981 | acpi_build_tables_cleanup(&tables, true); |
982 | } | |
983 | ||
984 | static void virt_acpi_build_reset(void *build_opaque) | |
985 | { | |
986 | AcpiBuildState *build_state = build_opaque; | |
987 | build_state->patched = false; | |
988 | } | |
989 | ||
f5d8c8cd SZ |
990 | static const VMStateDescription vmstate_virt_acpi_build = { |
991 | .name = "virt_acpi_build", | |
992 | .version_id = 1, | |
993 | .minimum_version_id = 1, | |
994 | .fields = (VMStateField[]) { | |
995 | VMSTATE_BOOL(patched, AcpiBuildState), | |
996 | VMSTATE_END_OF_LIST() | |
997 | }, | |
998 | }; | |
999 | ||
e9a8e474 | 1000 | void virt_acpi_setup(VirtMachineState *vms) |
f5d8c8cd SZ |
1001 | { |
1002 | AcpiBuildTables tables; | |
1003 | AcpiBuildState *build_state; | |
a08a6462 | 1004 | AcpiGedState *acpi_ged_state; |
f5d8c8cd | 1005 | |
af1f60a4 | 1006 | if (!vms->fw_cfg) { |
f5d8c8cd SZ |
1007 | trace_virt_acpi_setup(); |
1008 | return; | |
1009 | } | |
1010 | ||
17e89077 | 1011 | if (!virt_is_acpi_enabled(vms)) { |
f5d8c8cd SZ |
1012 | trace_virt_acpi_setup(); |
1013 | return; | |
1014 | } | |
1015 | ||
1016 | build_state = g_malloc0(sizeof *build_state); | |
f5d8c8cd SZ |
1017 | |
1018 | acpi_build_tables_init(&tables); | |
da4f09a7 | 1019 | virt_acpi_build(vms, &tables); |
f5d8c8cd SZ |
1020 | |
1021 | /* Now expose it all to Guest */ | |
82f76c67 WY |
1022 | build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1023 | build_state, tables.table_data, | |
6930ba0d | 1024 | ACPI_BUILD_TABLE_FILE); |
f5d8c8cd SZ |
1025 | assert(build_state->table_mr != NULL); |
1026 | ||
6930ba0d DH |
1027 | build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1028 | build_state, | |
1029 | tables.linker->cmd_blob, | |
1030 | ACPI_BUILD_LOADER_FILE); | |
f5d8c8cd | 1031 | |
af1f60a4 AJ |
1032 | fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, |
1033 | acpi_data_len(tables.tcpalog)); | |
f5d8c8cd | 1034 | |
a08a6462 DG |
1035 | if (vms->ras) { |
1036 | assert(vms->acpi_dev); | |
1037 | acpi_ged_state = ACPI_GED(vms->acpi_dev); | |
1038 | acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state, | |
1039 | vms->fw_cfg, tables.hardware_errors); | |
1040 | } | |
1041 | ||
82f76c67 WY |
1042 | build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, |
1043 | build_state, tables.rsdp, | |
6930ba0d | 1044 | ACPI_BUILD_RSDP_FILE); |
f5d8c8cd SZ |
1045 | |
1046 | qemu_register_reset(virt_acpi_build_reset, build_state); | |
1047 | virt_acpi_build_reset(build_state); | |
1048 | vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); | |
1049 | ||
1050 | /* Cleanup tables but don't free the memory: we track it | |
1051 | * in build_state. | |
1052 | */ | |
1053 | acpi_build_tables_cleanup(&tables, false); | |
1054 | } |