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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
5fafdf24 | 5 | * |
6f7e9aec FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
5d20fa6b | 24 | |
cfb9de9c | 25 | #include "sysbus.h" |
43b443b6 | 26 | #include "scsi.h" |
1cd3af54 | 27 | #include "esp.h" |
6f7e9aec FB |
28 | |
29 | /* debug ESP card */ | |
2f275b8f | 30 | //#define DEBUG_ESP |
6f7e9aec | 31 | |
67e999be | 32 | /* |
5ad6bb97 BS |
33 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
34 | * also produced as NCR89C100. See | |
67e999be FB |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
36 | * and | |
37 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
38 | */ | |
39 | ||
6f7e9aec | 40 | #ifdef DEBUG_ESP |
001faf32 BS |
41 | #define DPRINTF(fmt, ...) \ |
42 | do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) | |
6f7e9aec | 43 | #else |
001faf32 | 44 | #define DPRINTF(fmt, ...) do {} while (0) |
6f7e9aec FB |
45 | #endif |
46 | ||
001faf32 BS |
47 | #define ESP_ERROR(fmt, ...) \ |
48 | do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) | |
8dea1dd4 | 49 | |
5aca8c3b | 50 | #define ESP_REGS 16 |
8dea1dd4 | 51 | #define TI_BUFSZ 16 |
67e999be | 52 | |
4e9aec74 | 53 | typedef struct ESPState ESPState; |
6f7e9aec | 54 | |
4e9aec74 | 55 | struct ESPState { |
cfb9de9c | 56 | SysBusDevice busdev; |
5d20fa6b | 57 | uint32_t it_shift; |
70c0de96 | 58 | qemu_irq irq; |
5aca8c3b BS |
59 | uint8_t rregs[ESP_REGS]; |
60 | uint8_t wregs[ESP_REGS]; | |
67e999be | 61 | int32_t ti_size; |
4f6200f0 | 62 | uint32_t ti_rptr, ti_wptr; |
4f6200f0 | 63 | uint8_t ti_buf[TI_BUFSZ]; |
22548760 BS |
64 | uint32_t sense; |
65 | uint32_t dma; | |
ca9c39fa | 66 | SCSIBus bus; |
2e5d83bb | 67 | SCSIDevice *current_dev; |
5c6c0e51 | 68 | SCSIRequest *current_req; |
9f149aa9 | 69 | uint8_t cmdbuf[TI_BUFSZ]; |
22548760 BS |
70 | uint32_t cmdlen; |
71 | uint32_t do_cmd; | |
4d611c9a | 72 | |
6787f5fa | 73 | /* The amount of data left in the current DMA transfer. */ |
4d611c9a | 74 | uint32_t dma_left; |
6787f5fa PB |
75 | /* The size of the current DMA transfer. Zero if no transfer is in |
76 | progress. */ | |
77 | uint32_t dma_counter; | |
a917d384 | 78 | uint8_t *async_buf; |
4d611c9a | 79 | uint32_t async_len; |
8b17de88 | 80 | |
ff9868ec BS |
81 | ESPDMAMemoryReadWriteFunc dma_memory_read; |
82 | ESPDMAMemoryReadWriteFunc dma_memory_write; | |
67e999be | 83 | void *dma_opaque; |
73d74342 BS |
84 | int dma_enabled; |
85 | void (*dma_cb)(ESPState *s); | |
4e9aec74 | 86 | }; |
6f7e9aec | 87 | |
5ad6bb97 BS |
88 | #define ESP_TCLO 0x0 |
89 | #define ESP_TCMID 0x1 | |
90 | #define ESP_FIFO 0x2 | |
91 | #define ESP_CMD 0x3 | |
92 | #define ESP_RSTAT 0x4 | |
93 | #define ESP_WBUSID 0x4 | |
94 | #define ESP_RINTR 0x5 | |
95 | #define ESP_WSEL 0x5 | |
96 | #define ESP_RSEQ 0x6 | |
97 | #define ESP_WSYNTP 0x6 | |
98 | #define ESP_RFLAGS 0x7 | |
99 | #define ESP_WSYNO 0x7 | |
100 | #define ESP_CFG1 0x8 | |
101 | #define ESP_RRES1 0x9 | |
102 | #define ESP_WCCF 0x9 | |
103 | #define ESP_RRES2 0xa | |
104 | #define ESP_WTEST 0xa | |
105 | #define ESP_CFG2 0xb | |
106 | #define ESP_CFG3 0xc | |
107 | #define ESP_RES3 0xd | |
108 | #define ESP_TCHI 0xe | |
109 | #define ESP_RES4 0xf | |
110 | ||
111 | #define CMD_DMA 0x80 | |
112 | #define CMD_CMD 0x7f | |
113 | ||
114 | #define CMD_NOP 0x00 | |
115 | #define CMD_FLUSH 0x01 | |
116 | #define CMD_RESET 0x02 | |
117 | #define CMD_BUSRESET 0x03 | |
118 | #define CMD_TI 0x10 | |
119 | #define CMD_ICCS 0x11 | |
120 | #define CMD_MSGACC 0x12 | |
0fd0eb21 | 121 | #define CMD_PAD 0x18 |
5ad6bb97 | 122 | #define CMD_SATN 0x1a |
5e1e0a3b | 123 | #define CMD_SEL 0x41 |
5ad6bb97 BS |
124 | #define CMD_SELATN 0x42 |
125 | #define CMD_SELATNS 0x43 | |
126 | #define CMD_ENSEL 0x44 | |
127 | ||
2f275b8f FB |
128 | #define STAT_DO 0x00 |
129 | #define STAT_DI 0x01 | |
130 | #define STAT_CD 0x02 | |
131 | #define STAT_ST 0x03 | |
8dea1dd4 BS |
132 | #define STAT_MO 0x06 |
133 | #define STAT_MI 0x07 | |
5ad6bb97 | 134 | #define STAT_PIO_MASK 0x06 |
2f275b8f FB |
135 | |
136 | #define STAT_TC 0x10 | |
4d611c9a PB |
137 | #define STAT_PE 0x20 |
138 | #define STAT_GE 0x40 | |
c73f96fd | 139 | #define STAT_INT 0x80 |
2f275b8f | 140 | |
8dea1dd4 BS |
141 | #define BUSID_DID 0x07 |
142 | ||
2f275b8f FB |
143 | #define INTR_FC 0x08 |
144 | #define INTR_BS 0x10 | |
145 | #define INTR_DC 0x20 | |
9e61bde5 | 146 | #define INTR_RST 0x80 |
2f275b8f FB |
147 | |
148 | #define SEQ_0 0x0 | |
149 | #define SEQ_CD 0x4 | |
150 | ||
5ad6bb97 BS |
151 | #define CFG1_RESREPT 0x40 |
152 | ||
5ad6bb97 BS |
153 | #define TCHI_FAS100A 0x4 |
154 | ||
c73f96fd BS |
155 | static void esp_raise_irq(ESPState *s) |
156 | { | |
157 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
158 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
159 | qemu_irq_raise(s->irq); | |
dca47edd | 160 | DPRINTF("Raise IRQ\n"); |
c73f96fd BS |
161 | } |
162 | } | |
163 | ||
164 | static void esp_lower_irq(ESPState *s) | |
165 | { | |
166 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
167 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
168 | qemu_irq_lower(s->irq); | |
dca47edd | 169 | DPRINTF("Lower IRQ\n"); |
c73f96fd BS |
170 | } |
171 | } | |
172 | ||
73d74342 BS |
173 | static void esp_dma_enable(void *opaque, int irq, int level) |
174 | { | |
175 | DeviceState *d = opaque; | |
176 | ESPState *s = container_of(d, ESPState, busdev.qdev); | |
177 | ||
178 | if (level) { | |
179 | s->dma_enabled = 1; | |
180 | DPRINTF("Raise enable\n"); | |
181 | if (s->dma_cb) { | |
182 | s->dma_cb(s); | |
183 | s->dma_cb = NULL; | |
184 | } | |
185 | } else { | |
186 | DPRINTF("Lower enable\n"); | |
187 | s->dma_enabled = 0; | |
188 | } | |
189 | } | |
190 | ||
22548760 | 191 | static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
2f275b8f | 192 | { |
a917d384 | 193 | uint32_t dmalen; |
2f275b8f FB |
194 | int target; |
195 | ||
8dea1dd4 | 196 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 197 | if (s->dma) { |
fc4d65da | 198 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
8b17de88 | 199 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 200 | } else { |
fc4d65da BS |
201 | dmalen = s->ti_size; |
202 | memcpy(buf, s->ti_buf, dmalen); | |
f930d07e | 203 | buf[0] = 0; |
4f6200f0 | 204 | } |
fc4d65da | 205 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target); |
2e5d83bb | 206 | |
2f275b8f | 207 | s->ti_size = 0; |
4f6200f0 FB |
208 | s->ti_rptr = 0; |
209 | s->ti_wptr = 0; | |
2f275b8f | 210 | |
a917d384 PB |
211 | if (s->current_dev) { |
212 | /* Started a new command before the old one finished. Cancel it. */ | |
5c6c0e51 | 213 | s->current_dev->info->cancel_io(s->current_req); |
a917d384 PB |
214 | s->async_len = 0; |
215 | } | |
216 | ||
ca9c39fa | 217 | if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) { |
2e5d83bb | 218 | // No such drive |
c73f96fd | 219 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
220 | s->rregs[ESP_RINTR] = INTR_DC; |
221 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 222 | esp_raise_irq(s); |
f930d07e | 223 | return 0; |
2f275b8f | 224 | } |
ca9c39fa | 225 | s->current_dev = s->bus.devs[target]; |
9f149aa9 PB |
226 | return dmalen; |
227 | } | |
228 | ||
f2818f22 | 229 | static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
9f149aa9 PB |
230 | { |
231 | int32_t datalen; | |
232 | int lun; | |
233 | ||
f2818f22 AT |
234 | DPRINTF("do_busid_cmd: busid 0x%x\n", busid); |
235 | lun = busid & 7; | |
5c6c0e51 HR |
236 | s->current_req = s->current_dev->info->alloc_req(s->current_dev, 0, lun); |
237 | datalen = s->current_dev->info->send_command(s->current_req, buf); | |
67e999be FB |
238 | s->ti_size = datalen; |
239 | if (datalen != 0) { | |
c73f96fd | 240 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 241 | s->dma_left = 0; |
6787f5fa | 242 | s->dma_counter = 0; |
2e5d83bb | 243 | if (datalen > 0) { |
5ad6bb97 | 244 | s->rregs[ESP_RSTAT] |= STAT_DI; |
5c6c0e51 | 245 | s->current_dev->info->read_data(s->current_req); |
2e5d83bb | 246 | } else { |
5ad6bb97 | 247 | s->rregs[ESP_RSTAT] |= STAT_DO; |
5c6c0e51 | 248 | s->current_dev->info->write_data(s->current_req); |
b9788fc4 | 249 | } |
2f275b8f | 250 | } |
5ad6bb97 BS |
251 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
252 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 253 | esp_raise_irq(s); |
2f275b8f FB |
254 | } |
255 | ||
f2818f22 AT |
256 | static void do_cmd(ESPState *s, uint8_t *buf) |
257 | { | |
258 | uint8_t busid = buf[0]; | |
259 | ||
260 | do_busid_cmd(s, &buf[1], busid); | |
261 | } | |
262 | ||
9f149aa9 PB |
263 | static void handle_satn(ESPState *s) |
264 | { | |
265 | uint8_t buf[32]; | |
266 | int len; | |
267 | ||
73d74342 BS |
268 | if (!s->dma_enabled) { |
269 | s->dma_cb = handle_satn; | |
270 | return; | |
271 | } | |
9f149aa9 PB |
272 | len = get_cmd(s, buf); |
273 | if (len) | |
274 | do_cmd(s, buf); | |
275 | } | |
276 | ||
f2818f22 AT |
277 | static void handle_s_without_atn(ESPState *s) |
278 | { | |
279 | uint8_t buf[32]; | |
280 | int len; | |
281 | ||
73d74342 BS |
282 | if (!s->dma_enabled) { |
283 | s->dma_cb = handle_s_without_atn; | |
284 | return; | |
285 | } | |
f2818f22 AT |
286 | len = get_cmd(s, buf); |
287 | if (len) { | |
288 | do_busid_cmd(s, buf, 0); | |
289 | } | |
290 | } | |
291 | ||
9f149aa9 PB |
292 | static void handle_satn_stop(ESPState *s) |
293 | { | |
73d74342 BS |
294 | if (!s->dma_enabled) { |
295 | s->dma_cb = handle_satn_stop; | |
296 | return; | |
297 | } | |
9f149aa9 PB |
298 | s->cmdlen = get_cmd(s, s->cmdbuf); |
299 | if (s->cmdlen) { | |
300 | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); | |
301 | s->do_cmd = 1; | |
c73f96fd | 302 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
303 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
304 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 305 | esp_raise_irq(s); |
9f149aa9 PB |
306 | } |
307 | } | |
308 | ||
0fc5c15a | 309 | static void write_response(ESPState *s) |
2f275b8f | 310 | { |
0fc5c15a PB |
311 | DPRINTF("Transfer status (sense=%d)\n", s->sense); |
312 | s->ti_buf[0] = s->sense; | |
313 | s->ti_buf[1] = 0; | |
4f6200f0 | 314 | if (s->dma) { |
8b17de88 | 315 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 316 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
317 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
318 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 319 | } else { |
f930d07e BS |
320 | s->ti_size = 2; |
321 | s->ti_rptr = 0; | |
322 | s->ti_wptr = 0; | |
5ad6bb97 | 323 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 324 | } |
c73f96fd | 325 | esp_raise_irq(s); |
2f275b8f | 326 | } |
4f6200f0 | 327 | |
a917d384 PB |
328 | static void esp_dma_done(ESPState *s) |
329 | { | |
c73f96fd | 330 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
331 | s->rregs[ESP_RINTR] = INTR_BS; |
332 | s->rregs[ESP_RSEQ] = 0; | |
333 | s->rregs[ESP_RFLAGS] = 0; | |
334 | s->rregs[ESP_TCLO] = 0; | |
335 | s->rregs[ESP_TCMID] = 0; | |
c73f96fd | 336 | esp_raise_irq(s); |
a917d384 PB |
337 | } |
338 | ||
4d611c9a PB |
339 | static void esp_do_dma(ESPState *s) |
340 | { | |
67e999be | 341 | uint32_t len; |
4d611c9a | 342 | int to_device; |
a917d384 | 343 | |
67e999be | 344 | to_device = (s->ti_size < 0); |
a917d384 | 345 | len = s->dma_left; |
4d611c9a | 346 | if (s->do_cmd) { |
4d611c9a | 347 | DPRINTF("command len %d + %d\n", s->cmdlen, len); |
8b17de88 | 348 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a PB |
349 | s->ti_size = 0; |
350 | s->cmdlen = 0; | |
351 | s->do_cmd = 0; | |
352 | do_cmd(s, s->cmdbuf); | |
353 | return; | |
a917d384 PB |
354 | } |
355 | if (s->async_len == 0) { | |
356 | /* Defer until data is available. */ | |
357 | return; | |
358 | } | |
359 | if (len > s->async_len) { | |
360 | len = s->async_len; | |
361 | } | |
362 | if (to_device) { | |
8b17de88 | 363 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 364 | } else { |
8b17de88 | 365 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 366 | } |
a917d384 PB |
367 | s->dma_left -= len; |
368 | s->async_buf += len; | |
369 | s->async_len -= len; | |
6787f5fa PB |
370 | if (to_device) |
371 | s->ti_size += len; | |
372 | else | |
373 | s->ti_size -= len; | |
a917d384 | 374 | if (s->async_len == 0) { |
4d611c9a | 375 | if (to_device) { |
67e999be | 376 | // ti_size is negative |
5c6c0e51 | 377 | s->current_dev->info->write_data(s->current_req); |
4d611c9a | 378 | } else { |
5c6c0e51 | 379 | s->current_dev->info->read_data(s->current_req); |
6787f5fa | 380 | /* If there is still data to be read from the device then |
8dea1dd4 | 381 | complete the DMA operation immediately. Otherwise defer |
6787f5fa PB |
382 | until the scsi layer has completed. */ |
383 | if (s->dma_left == 0 && s->ti_size > 0) { | |
384 | esp_dma_done(s); | |
385 | } | |
4d611c9a | 386 | } |
6787f5fa PB |
387 | } else { |
388 | /* Partially filled a scsi buffer. Complete immediately. */ | |
a917d384 PB |
389 | esp_dma_done(s); |
390 | } | |
4d611c9a PB |
391 | } |
392 | ||
5c6c0e51 | 393 | static void esp_command_complete(SCSIRequest *req, int reason, uint32_t arg) |
2e5d83bb | 394 | { |
5c6c0e51 | 395 | ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent); |
2e5d83bb | 396 | |
4d611c9a PB |
397 | if (reason == SCSI_REASON_DONE) { |
398 | DPRINTF("SCSI Command complete\n"); | |
399 | if (s->ti_size != 0) | |
400 | DPRINTF("SCSI command completed unexpectedly\n"); | |
401 | s->ti_size = 0; | |
a917d384 PB |
402 | s->dma_left = 0; |
403 | s->async_len = 0; | |
404 | if (arg) | |
4d611c9a | 405 | DPRINTF("Command failed\n"); |
a917d384 | 406 | s->sense = arg; |
5ad6bb97 | 407 | s->rregs[ESP_RSTAT] = STAT_ST; |
a917d384 | 408 | esp_dma_done(s); |
5c6c0e51 HR |
409 | if (s->current_req) { |
410 | scsi_req_unref(s->current_req); | |
411 | s->current_req = NULL; | |
412 | s->current_dev = NULL; | |
413 | } | |
4d611c9a PB |
414 | } else { |
415 | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size); | |
a917d384 | 416 | s->async_len = arg; |
5c6c0e51 | 417 | s->async_buf = s->current_dev->info->get_buf(req); |
6787f5fa | 418 | if (s->dma_left) { |
a917d384 | 419 | esp_do_dma(s); |
6787f5fa PB |
420 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
421 | /* If this was the last part of a DMA transfer then the | |
422 | completion interrupt is deferred to here. */ | |
423 | esp_dma_done(s); | |
424 | } | |
4d611c9a | 425 | } |
2e5d83bb PB |
426 | } |
427 | ||
2f275b8f FB |
428 | static void handle_ti(ESPState *s) |
429 | { | |
4d611c9a | 430 | uint32_t dmalen, minlen; |
2f275b8f | 431 | |
5ad6bb97 | 432 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
db59203d PB |
433 | if (dmalen==0) { |
434 | dmalen=0x10000; | |
435 | } | |
6787f5fa | 436 | s->dma_counter = dmalen; |
db59203d | 437 | |
9f149aa9 PB |
438 | if (s->do_cmd) |
439 | minlen = (dmalen < 32) ? dmalen : 32; | |
67e999be FB |
440 | else if (s->ti_size < 0) |
441 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
442 | else |
443 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
db59203d | 444 | DPRINTF("Transfer Information len %d\n", minlen); |
4f6200f0 | 445 | if (s->dma) { |
4d611c9a | 446 | s->dma_left = minlen; |
5ad6bb97 | 447 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 448 | esp_do_dma(s); |
9f149aa9 PB |
449 | } else if (s->do_cmd) { |
450 | DPRINTF("command len %d\n", s->cmdlen); | |
451 | s->ti_size = 0; | |
452 | s->cmdlen = 0; | |
453 | s->do_cmd = 0; | |
454 | do_cmd(s, s->cmdbuf); | |
455 | return; | |
456 | } | |
2f275b8f FB |
457 | } |
458 | ||
85948643 | 459 | static void esp_hard_reset(DeviceState *d) |
6f7e9aec | 460 | { |
63235df8 | 461 | ESPState *s = container_of(d, ESPState, busdev.qdev); |
67e999be | 462 | |
5aca8c3b BS |
463 | memset(s->rregs, 0, ESP_REGS); |
464 | memset(s->wregs, 0, ESP_REGS); | |
5ad6bb97 | 465 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a |
4e9aec74 PB |
466 | s->ti_size = 0; |
467 | s->ti_rptr = 0; | |
468 | s->ti_wptr = 0; | |
4e9aec74 | 469 | s->dma = 0; |
9f149aa9 | 470 | s->do_cmd = 0; |
73d74342 | 471 | s->dma_cb = NULL; |
8dea1dd4 BS |
472 | |
473 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
474 | } |
475 | ||
85948643 BS |
476 | static void esp_soft_reset(DeviceState *d) |
477 | { | |
478 | ESPState *s = container_of(d, ESPState, busdev.qdev); | |
479 | ||
480 | qemu_irq_lower(s->irq); | |
481 | esp_hard_reset(d); | |
482 | } | |
483 | ||
2d069bab BS |
484 | static void parent_esp_reset(void *opaque, int irq, int level) |
485 | { | |
85948643 BS |
486 | if (level) { |
487 | esp_soft_reset(opaque); | |
488 | } | |
2d069bab BS |
489 | } |
490 | ||
73d74342 BS |
491 | static void esp_gpio_demux(void *opaque, int irq, int level) |
492 | { | |
493 | switch (irq) { | |
494 | case 0: | |
495 | parent_esp_reset(opaque, irq, level); | |
496 | break; | |
497 | case 1: | |
498 | esp_dma_enable(opaque, irq, level); | |
499 | break; | |
500 | } | |
501 | } | |
502 | ||
c227f099 | 503 | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
6f7e9aec FB |
504 | { |
505 | ESPState *s = opaque; | |
2814df28 | 506 | uint32_t saddr, old_val; |
6f7e9aec | 507 | |
e64d7d59 | 508 | saddr = addr >> s->it_shift; |
9e61bde5 | 509 | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); |
6f7e9aec | 510 | switch (saddr) { |
5ad6bb97 | 511 | case ESP_FIFO: |
f930d07e BS |
512 | if (s->ti_size > 0) { |
513 | s->ti_size--; | |
5ad6bb97 | 514 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
8dea1dd4 BS |
515 | /* Data out. */ |
516 | ESP_ERROR("PIO data read not implemented\n"); | |
5ad6bb97 | 517 | s->rregs[ESP_FIFO] = 0; |
2e5d83bb | 518 | } else { |
5ad6bb97 | 519 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
2e5d83bb | 520 | } |
c73f96fd | 521 | esp_raise_irq(s); |
f930d07e BS |
522 | } |
523 | if (s->ti_size == 0) { | |
4f6200f0 FB |
524 | s->ti_rptr = 0; |
525 | s->ti_wptr = 0; | |
526 | } | |
f930d07e | 527 | break; |
5ad6bb97 | 528 | case ESP_RINTR: |
2814df28 BS |
529 | /* Clear sequence step, interrupt register and all status bits |
530 | except TC */ | |
531 | old_val = s->rregs[ESP_RINTR]; | |
532 | s->rregs[ESP_RINTR] = 0; | |
533 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
534 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 535 | esp_lower_irq(s); |
2814df28 BS |
536 | |
537 | return old_val; | |
6f7e9aec | 538 | default: |
f930d07e | 539 | break; |
6f7e9aec | 540 | } |
2f275b8f | 541 | return s->rregs[saddr]; |
6f7e9aec FB |
542 | } |
543 | ||
c227f099 | 544 | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
6f7e9aec FB |
545 | { |
546 | ESPState *s = opaque; | |
547 | uint32_t saddr; | |
548 | ||
e64d7d59 | 549 | saddr = addr >> s->it_shift; |
5ad6bb97 BS |
550 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], |
551 | val); | |
6f7e9aec | 552 | switch (saddr) { |
5ad6bb97 BS |
553 | case ESP_TCLO: |
554 | case ESP_TCMID: | |
555 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 556 | break; |
5ad6bb97 | 557 | case ESP_FIFO: |
9f149aa9 PB |
558 | if (s->do_cmd) { |
559 | s->cmdbuf[s->cmdlen++] = val & 0xff; | |
8dea1dd4 BS |
560 | } else if (s->ti_size == TI_BUFSZ - 1) { |
561 | ESP_ERROR("fifo overrun\n"); | |
2e5d83bb PB |
562 | } else { |
563 | s->ti_size++; | |
564 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
565 | } | |
f930d07e | 566 | break; |
5ad6bb97 | 567 | case ESP_CMD: |
4f6200f0 | 568 | s->rregs[saddr] = val; |
5ad6bb97 | 569 | if (val & CMD_DMA) { |
f930d07e | 570 | s->dma = 1; |
6787f5fa | 571 | /* Reload DMA counter. */ |
5ad6bb97 BS |
572 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
573 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
f930d07e BS |
574 | } else { |
575 | s->dma = 0; | |
576 | } | |
5ad6bb97 BS |
577 | switch(val & CMD_CMD) { |
578 | case CMD_NOP: | |
f930d07e BS |
579 | DPRINTF("NOP (%2.2x)\n", val); |
580 | break; | |
5ad6bb97 | 581 | case CMD_FLUSH: |
f930d07e | 582 | DPRINTF("Flush FIFO (%2.2x)\n", val); |
9e61bde5 | 583 | //s->ti_size = 0; |
5ad6bb97 BS |
584 | s->rregs[ESP_RINTR] = INTR_FC; |
585 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 586 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 587 | break; |
5ad6bb97 | 588 | case CMD_RESET: |
f930d07e | 589 | DPRINTF("Chip reset (%2.2x)\n", val); |
85948643 | 590 | esp_soft_reset(&s->busdev.qdev); |
f930d07e | 591 | break; |
5ad6bb97 | 592 | case CMD_BUSRESET: |
f930d07e | 593 | DPRINTF("Bus reset (%2.2x)\n", val); |
5ad6bb97 BS |
594 | s->rregs[ESP_RINTR] = INTR_RST; |
595 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 596 | esp_raise_irq(s); |
9e61bde5 | 597 | } |
f930d07e | 598 | break; |
5ad6bb97 | 599 | case CMD_TI: |
f930d07e BS |
600 | handle_ti(s); |
601 | break; | |
5ad6bb97 | 602 | case CMD_ICCS: |
f930d07e BS |
603 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); |
604 | write_response(s); | |
4bf5801d BS |
605 | s->rregs[ESP_RINTR] = INTR_FC; |
606 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 607 | break; |
5ad6bb97 | 608 | case CMD_MSGACC: |
f930d07e | 609 | DPRINTF("Message Accepted (%2.2x)\n", val); |
5ad6bb97 BS |
610 | s->rregs[ESP_RINTR] = INTR_DC; |
611 | s->rregs[ESP_RSEQ] = 0; | |
4e2a68c1 AT |
612 | s->rregs[ESP_RFLAGS] = 0; |
613 | esp_raise_irq(s); | |
f930d07e | 614 | break; |
0fd0eb21 BS |
615 | case CMD_PAD: |
616 | DPRINTF("Transfer padding (%2.2x)\n", val); | |
617 | s->rregs[ESP_RSTAT] = STAT_TC; | |
618 | s->rregs[ESP_RINTR] = INTR_FC; | |
619 | s->rregs[ESP_RSEQ] = 0; | |
620 | break; | |
5ad6bb97 | 621 | case CMD_SATN: |
f930d07e BS |
622 | DPRINTF("Set ATN (%2.2x)\n", val); |
623 | break; | |
5e1e0a3b BS |
624 | case CMD_SEL: |
625 | DPRINTF("Select without ATN (%2.2x)\n", val); | |
f2818f22 | 626 | handle_s_without_atn(s); |
5e1e0a3b | 627 | break; |
5ad6bb97 | 628 | case CMD_SELATN: |
5e1e0a3b | 629 | DPRINTF("Select with ATN (%2.2x)\n", val); |
f930d07e BS |
630 | handle_satn(s); |
631 | break; | |
5ad6bb97 | 632 | case CMD_SELATNS: |
5e1e0a3b | 633 | DPRINTF("Select with ATN & stop (%2.2x)\n", val); |
f930d07e BS |
634 | handle_satn_stop(s); |
635 | break; | |
5ad6bb97 | 636 | case CMD_ENSEL: |
74ec6048 | 637 | DPRINTF("Enable selection (%2.2x)\n", val); |
e3926838 | 638 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 639 | break; |
f930d07e | 640 | default: |
8dea1dd4 | 641 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val); |
f930d07e BS |
642 | break; |
643 | } | |
644 | break; | |
5ad6bb97 | 645 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 646 | break; |
5ad6bb97 | 647 | case ESP_CFG1: |
4f6200f0 FB |
648 | s->rregs[saddr] = val; |
649 | break; | |
5ad6bb97 | 650 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 651 | break; |
b44c08fa | 652 | case ESP_CFG2 ... ESP_RES4: |
4f6200f0 FB |
653 | s->rregs[saddr] = val; |
654 | break; | |
6f7e9aec | 655 | default: |
8dea1dd4 BS |
656 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr); |
657 | return; | |
6f7e9aec | 658 | } |
2f275b8f | 659 | s->wregs[saddr] = val; |
6f7e9aec FB |
660 | } |
661 | ||
d60efc6b | 662 | static CPUReadMemoryFunc * const esp_mem_read[3] = { |
6f7e9aec | 663 | esp_mem_readb, |
7c560456 BS |
664 | NULL, |
665 | NULL, | |
6f7e9aec FB |
666 | }; |
667 | ||
d60efc6b | 668 | static CPUWriteMemoryFunc * const esp_mem_write[3] = { |
6f7e9aec | 669 | esp_mem_writeb, |
7c560456 | 670 | NULL, |
daa41b00 | 671 | esp_mem_writeb, |
6f7e9aec FB |
672 | }; |
673 | ||
cc9952f3 BS |
674 | static const VMStateDescription vmstate_esp = { |
675 | .name ="esp", | |
676 | .version_id = 3, | |
677 | .minimum_version_id = 3, | |
678 | .minimum_version_id_old = 3, | |
679 | .fields = (VMStateField []) { | |
680 | VMSTATE_BUFFER(rregs, ESPState), | |
681 | VMSTATE_BUFFER(wregs, ESPState), | |
682 | VMSTATE_INT32(ti_size, ESPState), | |
683 | VMSTATE_UINT32(ti_rptr, ESPState), | |
684 | VMSTATE_UINT32(ti_wptr, ESPState), | |
685 | VMSTATE_BUFFER(ti_buf, ESPState), | |
686 | VMSTATE_UINT32(sense, ESPState), | |
687 | VMSTATE_UINT32(dma, ESPState), | |
688 | VMSTATE_BUFFER(cmdbuf, ESPState), | |
689 | VMSTATE_UINT32(cmdlen, ESPState), | |
690 | VMSTATE_UINT32(do_cmd, ESPState), | |
691 | VMSTATE_UINT32(dma_left, ESPState), | |
692 | VMSTATE_END_OF_LIST() | |
693 | } | |
694 | }; | |
6f7e9aec | 695 | |
c227f099 | 696 | void esp_init(target_phys_addr_t espaddr, int it_shift, |
ff9868ec BS |
697 | ESPDMAMemoryReadWriteFunc dma_memory_read, |
698 | ESPDMAMemoryReadWriteFunc dma_memory_write, | |
73d74342 BS |
699 | void *dma_opaque, qemu_irq irq, qemu_irq *reset, |
700 | qemu_irq *dma_enable) | |
6f7e9aec | 701 | { |
cfb9de9c PB |
702 | DeviceState *dev; |
703 | SysBusDevice *s; | |
ee6847d1 | 704 | ESPState *esp; |
cfb9de9c PB |
705 | |
706 | dev = qdev_create(NULL, "esp"); | |
ee6847d1 GH |
707 | esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
708 | esp->dma_memory_read = dma_memory_read; | |
709 | esp->dma_memory_write = dma_memory_write; | |
710 | esp->dma_opaque = dma_opaque; | |
711 | esp->it_shift = it_shift; | |
73d74342 BS |
712 | /* XXX for now until rc4030 has been changed to use DMA enable signal */ |
713 | esp->dma_enabled = 1; | |
e23a1b33 | 714 | qdev_init_nofail(dev); |
cfb9de9c PB |
715 | s = sysbus_from_qdev(dev); |
716 | sysbus_connect_irq(s, 0, irq); | |
717 | sysbus_mmio_map(s, 0, espaddr); | |
74ff8d90 | 718 | *reset = qdev_get_gpio_in(dev, 0); |
73d74342 | 719 | *dma_enable = qdev_get_gpio_in(dev, 1); |
cfb9de9c | 720 | } |
6f7e9aec | 721 | |
cfdc1bb0 PB |
722 | static const struct SCSIBusOps esp_scsi_ops = { |
723 | .complete = esp_command_complete | |
724 | }; | |
725 | ||
81a322d4 | 726 | static int esp_init1(SysBusDevice *dev) |
cfb9de9c PB |
727 | { |
728 | ESPState *s = FROM_SYSBUS(ESPState, dev); | |
729 | int esp_io_memory; | |
6f7e9aec | 730 | |
cfb9de9c | 731 | sysbus_init_irq(dev, &s->irq); |
cfb9de9c | 732 | assert(s->it_shift != -1); |
6f7e9aec | 733 | |
2507c12a AG |
734 | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s, |
735 | DEVICE_NATIVE_ENDIAN); | |
cfb9de9c | 736 | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
6f7e9aec | 737 | |
73d74342 | 738 | qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2); |
2d069bab | 739 | |
cfdc1bb0 | 740 | scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, &esp_scsi_ops); |
fa66b909 | 741 | return scsi_bus_legacy_handle_cmdline(&s->bus); |
67e999be | 742 | } |
cfb9de9c | 743 | |
63235df8 BS |
744 | static SysBusDeviceInfo esp_info = { |
745 | .init = esp_init1, | |
746 | .qdev.name = "esp", | |
747 | .qdev.size = sizeof(ESPState), | |
748 | .qdev.vmsd = &vmstate_esp, | |
85948643 | 749 | .qdev.reset = esp_hard_reset, |
63235df8 BS |
750 | .qdev.props = (Property[]) { |
751 | {.name = NULL} | |
752 | } | |
753 | }; | |
754 | ||
cfb9de9c PB |
755 | static void esp_register_devices(void) |
756 | { | |
63235df8 | 757 | sysbus_register_withprop(&esp_info); |
cfb9de9c PB |
758 | } |
759 | ||
760 | device_init(esp_register_devices) |