]>
Commit | Line | Data |
---|---|---|
6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
cfb9de9c | 26 | #include "sysbus.h" |
1cd3af54 | 27 | #include "esp.h" |
bf4b9889 | 28 | #include "trace.h" |
3af4e9aa | 29 | #include "qemu-log.h" |
6f7e9aec | 30 | |
67e999be | 31 | /* |
5ad6bb97 BS |
32 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
33 | * also produced as NCR89C100. See | |
67e999be FB |
34 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
35 | * and | |
36 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
37 | */ | |
38 | ||
c73f96fd BS |
39 | static void esp_raise_irq(ESPState *s) |
40 | { | |
41 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
42 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
43 | qemu_irq_raise(s->irq); | |
bf4b9889 | 44 | trace_esp_raise_irq(); |
c73f96fd BS |
45 | } |
46 | } | |
47 | ||
48 | static void esp_lower_irq(ESPState *s) | |
49 | { | |
50 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
51 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
52 | qemu_irq_lower(s->irq); | |
bf4b9889 | 53 | trace_esp_lower_irq(); |
c73f96fd BS |
54 | } |
55 | } | |
56 | ||
9c7e23fc | 57 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 58 | { |
73d74342 BS |
59 | if (level) { |
60 | s->dma_enabled = 1; | |
bf4b9889 | 61 | trace_esp_dma_enable(); |
73d74342 BS |
62 | if (s->dma_cb) { |
63 | s->dma_cb(s); | |
64 | s->dma_cb = NULL; | |
65 | } | |
66 | } else { | |
bf4b9889 | 67 | trace_esp_dma_disable(); |
73d74342 BS |
68 | s->dma_enabled = 0; |
69 | } | |
70 | } | |
71 | ||
9c7e23fc | 72 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 73 | { |
e6810db8 | 74 | ESPState *s = req->hba_private; |
94d3f98a PB |
75 | |
76 | if (req == s->current_req) { | |
77 | scsi_req_unref(s->current_req); | |
78 | s->current_req = NULL; | |
79 | s->current_dev = NULL; | |
80 | } | |
81 | } | |
82 | ||
22548760 | 83 | static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
2f275b8f | 84 | { |
a917d384 | 85 | uint32_t dmalen; |
2f275b8f FB |
86 | int target; |
87 | ||
8dea1dd4 | 88 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 89 | if (s->dma) { |
fc4d65da | 90 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
8b17de88 | 91 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 92 | } else { |
fc4d65da BS |
93 | dmalen = s->ti_size; |
94 | memcpy(buf, s->ti_buf, dmalen); | |
75ef8496 | 95 | buf[0] = buf[2] >> 5; |
4f6200f0 | 96 | } |
bf4b9889 | 97 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 98 | |
2f275b8f | 99 | s->ti_size = 0; |
4f6200f0 FB |
100 | s->ti_rptr = 0; |
101 | s->ti_wptr = 0; | |
2f275b8f | 102 | |
429bef69 | 103 | if (s->current_req) { |
a917d384 | 104 | /* Started a new command before the old one finished. Cancel it. */ |
94d3f98a | 105 | scsi_req_cancel(s->current_req); |
a917d384 PB |
106 | s->async_len = 0; |
107 | } | |
108 | ||
0d3545e7 | 109 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); |
f48a7a6e | 110 | if (!s->current_dev) { |
2e5d83bb | 111 | // No such drive |
c73f96fd | 112 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
113 | s->rregs[ESP_RINTR] = INTR_DC; |
114 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 115 | esp_raise_irq(s); |
f930d07e | 116 | return 0; |
2f275b8f | 117 | } |
9f149aa9 PB |
118 | return dmalen; |
119 | } | |
120 | ||
f2818f22 | 121 | static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
9f149aa9 PB |
122 | { |
123 | int32_t datalen; | |
124 | int lun; | |
f48a7a6e | 125 | SCSIDevice *current_lun; |
9f149aa9 | 126 | |
bf4b9889 | 127 | trace_esp_do_busid_cmd(busid); |
f2818f22 | 128 | lun = busid & 7; |
0d3545e7 | 129 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); |
e6810db8 | 130 | s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); |
c39ce112 | 131 | datalen = scsi_req_enqueue(s->current_req); |
67e999be FB |
132 | s->ti_size = datalen; |
133 | if (datalen != 0) { | |
c73f96fd | 134 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 135 | s->dma_left = 0; |
6787f5fa | 136 | s->dma_counter = 0; |
2e5d83bb | 137 | if (datalen > 0) { |
5ad6bb97 | 138 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 139 | } else { |
5ad6bb97 | 140 | s->rregs[ESP_RSTAT] |= STAT_DO; |
b9788fc4 | 141 | } |
ad3376cc | 142 | scsi_req_continue(s->current_req); |
2f275b8f | 143 | } |
5ad6bb97 BS |
144 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
145 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 146 | esp_raise_irq(s); |
2f275b8f FB |
147 | } |
148 | ||
f2818f22 AT |
149 | static void do_cmd(ESPState *s, uint8_t *buf) |
150 | { | |
151 | uint8_t busid = buf[0]; | |
152 | ||
153 | do_busid_cmd(s, &buf[1], busid); | |
154 | } | |
155 | ||
9f149aa9 PB |
156 | static void handle_satn(ESPState *s) |
157 | { | |
158 | uint8_t buf[32]; | |
159 | int len; | |
160 | ||
1b26eaa1 | 161 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
162 | s->dma_cb = handle_satn; |
163 | return; | |
164 | } | |
9f149aa9 PB |
165 | len = get_cmd(s, buf); |
166 | if (len) | |
167 | do_cmd(s, buf); | |
168 | } | |
169 | ||
f2818f22 AT |
170 | static void handle_s_without_atn(ESPState *s) |
171 | { | |
172 | uint8_t buf[32]; | |
173 | int len; | |
174 | ||
1b26eaa1 | 175 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
176 | s->dma_cb = handle_s_without_atn; |
177 | return; | |
178 | } | |
f2818f22 AT |
179 | len = get_cmd(s, buf); |
180 | if (len) { | |
181 | do_busid_cmd(s, buf, 0); | |
182 | } | |
183 | } | |
184 | ||
9f149aa9 PB |
185 | static void handle_satn_stop(ESPState *s) |
186 | { | |
1b26eaa1 | 187 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
188 | s->dma_cb = handle_satn_stop; |
189 | return; | |
190 | } | |
9f149aa9 PB |
191 | s->cmdlen = get_cmd(s, s->cmdbuf); |
192 | if (s->cmdlen) { | |
bf4b9889 | 193 | trace_esp_handle_satn_stop(s->cmdlen); |
9f149aa9 | 194 | s->do_cmd = 1; |
c73f96fd | 195 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
196 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
197 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 198 | esp_raise_irq(s); |
9f149aa9 PB |
199 | } |
200 | } | |
201 | ||
0fc5c15a | 202 | static void write_response(ESPState *s) |
2f275b8f | 203 | { |
bf4b9889 | 204 | trace_esp_write_response(s->status); |
3944966d | 205 | s->ti_buf[0] = s->status; |
0fc5c15a | 206 | s->ti_buf[1] = 0; |
4f6200f0 | 207 | if (s->dma) { |
8b17de88 | 208 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 209 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
210 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
211 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 212 | } else { |
f930d07e BS |
213 | s->ti_size = 2; |
214 | s->ti_rptr = 0; | |
215 | s->ti_wptr = 0; | |
5ad6bb97 | 216 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 217 | } |
c73f96fd | 218 | esp_raise_irq(s); |
2f275b8f | 219 | } |
4f6200f0 | 220 | |
a917d384 PB |
221 | static void esp_dma_done(ESPState *s) |
222 | { | |
c73f96fd | 223 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
224 | s->rregs[ESP_RINTR] = INTR_BS; |
225 | s->rregs[ESP_RSEQ] = 0; | |
226 | s->rregs[ESP_RFLAGS] = 0; | |
227 | s->rregs[ESP_TCLO] = 0; | |
228 | s->rregs[ESP_TCMID] = 0; | |
c73f96fd | 229 | esp_raise_irq(s); |
a917d384 PB |
230 | } |
231 | ||
4d611c9a PB |
232 | static void esp_do_dma(ESPState *s) |
233 | { | |
67e999be | 234 | uint32_t len; |
4d611c9a | 235 | int to_device; |
a917d384 | 236 | |
67e999be | 237 | to_device = (s->ti_size < 0); |
a917d384 | 238 | len = s->dma_left; |
4d611c9a | 239 | if (s->do_cmd) { |
bf4b9889 | 240 | trace_esp_do_dma(s->cmdlen, len); |
8b17de88 | 241 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a PB |
242 | s->ti_size = 0; |
243 | s->cmdlen = 0; | |
244 | s->do_cmd = 0; | |
245 | do_cmd(s, s->cmdbuf); | |
246 | return; | |
a917d384 PB |
247 | } |
248 | if (s->async_len == 0) { | |
249 | /* Defer until data is available. */ | |
250 | return; | |
251 | } | |
252 | if (len > s->async_len) { | |
253 | len = s->async_len; | |
254 | } | |
255 | if (to_device) { | |
8b17de88 | 256 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 257 | } else { |
8b17de88 | 258 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 259 | } |
a917d384 PB |
260 | s->dma_left -= len; |
261 | s->async_buf += len; | |
262 | s->async_len -= len; | |
6787f5fa PB |
263 | if (to_device) |
264 | s->ti_size += len; | |
265 | else | |
266 | s->ti_size -= len; | |
a917d384 | 267 | if (s->async_len == 0) { |
ad3376cc PB |
268 | scsi_req_continue(s->current_req); |
269 | /* If there is still data to be read from the device then | |
270 | complete the DMA operation immediately. Otherwise defer | |
271 | until the scsi layer has completed. */ | |
272 | if (to_device || s->dma_left != 0 || s->ti_size == 0) { | |
273 | return; | |
4d611c9a | 274 | } |
a917d384 | 275 | } |
ad3376cc PB |
276 | |
277 | /* Partially filled a scsi buffer. Complete immediately. */ | |
278 | esp_dma_done(s); | |
4d611c9a PB |
279 | } |
280 | ||
9c7e23fc | 281 | void esp_command_complete(SCSIRequest *req, uint32_t status, |
01e95455 | 282 | size_t resid) |
2e5d83bb | 283 | { |
e6810db8 | 284 | ESPState *s = req->hba_private; |
2e5d83bb | 285 | |
bf4b9889 | 286 | trace_esp_command_complete(); |
c6df7102 | 287 | if (s->ti_size != 0) { |
bf4b9889 | 288 | trace_esp_command_complete_unexpected(); |
c6df7102 PB |
289 | } |
290 | s->ti_size = 0; | |
291 | s->dma_left = 0; | |
292 | s->async_len = 0; | |
aba1f023 | 293 | if (status) { |
bf4b9889 | 294 | trace_esp_command_complete_fail(); |
c6df7102 | 295 | } |
aba1f023 | 296 | s->status = status; |
c6df7102 PB |
297 | s->rregs[ESP_RSTAT] = STAT_ST; |
298 | esp_dma_done(s); | |
299 | if (s->current_req) { | |
300 | scsi_req_unref(s->current_req); | |
301 | s->current_req = NULL; | |
302 | s->current_dev = NULL; | |
303 | } | |
304 | } | |
305 | ||
9c7e23fc | 306 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 307 | { |
e6810db8 | 308 | ESPState *s = req->hba_private; |
c6df7102 | 309 | |
bf4b9889 | 310 | trace_esp_transfer_data(s->dma_left, s->ti_size); |
aba1f023 | 311 | s->async_len = len; |
c6df7102 PB |
312 | s->async_buf = scsi_req_get_buf(req); |
313 | if (s->dma_left) { | |
314 | esp_do_dma(s); | |
315 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { | |
316 | /* If this was the last part of a DMA transfer then the | |
317 | completion interrupt is deferred to here. */ | |
a917d384 | 318 | esp_dma_done(s); |
4d611c9a | 319 | } |
2e5d83bb PB |
320 | } |
321 | ||
2f275b8f FB |
322 | static void handle_ti(ESPState *s) |
323 | { | |
4d611c9a | 324 | uint32_t dmalen, minlen; |
2f275b8f | 325 | |
7246e160 HP |
326 | if (s->dma && !s->dma_enabled) { |
327 | s->dma_cb = handle_ti; | |
328 | return; | |
329 | } | |
330 | ||
5ad6bb97 | 331 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8); |
db59203d PB |
332 | if (dmalen==0) { |
333 | dmalen=0x10000; | |
334 | } | |
6787f5fa | 335 | s->dma_counter = dmalen; |
db59203d | 336 | |
9f149aa9 PB |
337 | if (s->do_cmd) |
338 | minlen = (dmalen < 32) ? dmalen : 32; | |
67e999be FB |
339 | else if (s->ti_size < 0) |
340 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
341 | else |
342 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
bf4b9889 | 343 | trace_esp_handle_ti(minlen); |
4f6200f0 | 344 | if (s->dma) { |
4d611c9a | 345 | s->dma_left = minlen; |
5ad6bb97 | 346 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 347 | esp_do_dma(s); |
9f149aa9 | 348 | } else if (s->do_cmd) { |
bf4b9889 | 349 | trace_esp_handle_ti_cmd(s->cmdlen); |
9f149aa9 PB |
350 | s->ti_size = 0; |
351 | s->cmdlen = 0; | |
352 | s->do_cmd = 0; | |
353 | do_cmd(s, s->cmdbuf); | |
354 | return; | |
355 | } | |
2f275b8f FB |
356 | } |
357 | ||
9c7e23fc | 358 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 359 | { |
5aca8c3b BS |
360 | memset(s->rregs, 0, ESP_REGS); |
361 | memset(s->wregs, 0, ESP_REGS); | |
d32e4b3d | 362 | s->rregs[ESP_TCHI] = s->chip_id; |
4e9aec74 PB |
363 | s->ti_size = 0; |
364 | s->ti_rptr = 0; | |
365 | s->ti_wptr = 0; | |
4e9aec74 | 366 | s->dma = 0; |
9f149aa9 | 367 | s->do_cmd = 0; |
73d74342 | 368 | s->dma_cb = NULL; |
8dea1dd4 BS |
369 | |
370 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
371 | } |
372 | ||
a391fdbc | 373 | static void esp_soft_reset(ESPState *s) |
85948643 | 374 | { |
85948643 | 375 | qemu_irq_lower(s->irq); |
a391fdbc | 376 | esp_hard_reset(s); |
85948643 BS |
377 | } |
378 | ||
a391fdbc | 379 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 380 | { |
85948643 | 381 | if (level) { |
a391fdbc | 382 | esp_soft_reset(s); |
85948643 | 383 | } |
2d069bab BS |
384 | } |
385 | ||
9c7e23fc | 386 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 387 | { |
a391fdbc | 388 | uint32_t old_val; |
73d74342 | 389 | |
bf4b9889 | 390 | trace_esp_mem_readb(saddr, s->rregs[saddr]); |
6f7e9aec | 391 | switch (saddr) { |
5ad6bb97 | 392 | case ESP_FIFO: |
f930d07e BS |
393 | if (s->ti_size > 0) { |
394 | s->ti_size--; | |
5ad6bb97 | 395 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
8dea1dd4 | 396 | /* Data out. */ |
3af4e9aa HP |
397 | qemu_log_mask(LOG_UNIMP, |
398 | "esp: PIO data read not implemented\n"); | |
5ad6bb97 | 399 | s->rregs[ESP_FIFO] = 0; |
2e5d83bb | 400 | } else { |
5ad6bb97 | 401 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
2e5d83bb | 402 | } |
c73f96fd | 403 | esp_raise_irq(s); |
f930d07e BS |
404 | } |
405 | if (s->ti_size == 0) { | |
4f6200f0 FB |
406 | s->ti_rptr = 0; |
407 | s->ti_wptr = 0; | |
408 | } | |
f930d07e | 409 | break; |
5ad6bb97 | 410 | case ESP_RINTR: |
2814df28 BS |
411 | /* Clear sequence step, interrupt register and all status bits |
412 | except TC */ | |
413 | old_val = s->rregs[ESP_RINTR]; | |
414 | s->rregs[ESP_RINTR] = 0; | |
415 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
416 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 417 | esp_lower_irq(s); |
2814df28 BS |
418 | |
419 | return old_val; | |
6f7e9aec | 420 | default: |
f930d07e | 421 | break; |
6f7e9aec | 422 | } |
2f275b8f | 423 | return s->rregs[saddr]; |
6f7e9aec FB |
424 | } |
425 | ||
9c7e23fc | 426 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 427 | { |
bf4b9889 | 428 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 429 | switch (saddr) { |
5ad6bb97 BS |
430 | case ESP_TCLO: |
431 | case ESP_TCMID: | |
432 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 433 | break; |
5ad6bb97 | 434 | case ESP_FIFO: |
9f149aa9 PB |
435 | if (s->do_cmd) { |
436 | s->cmdbuf[s->cmdlen++] = val & 0xff; | |
8dea1dd4 | 437 | } else if (s->ti_size == TI_BUFSZ - 1) { |
3af4e9aa | 438 | trace_esp_error_fifo_overrun(); |
2e5d83bb PB |
439 | } else { |
440 | s->ti_size++; | |
441 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
442 | } | |
f930d07e | 443 | break; |
5ad6bb97 | 444 | case ESP_CMD: |
4f6200f0 | 445 | s->rregs[saddr] = val; |
5ad6bb97 | 446 | if (val & CMD_DMA) { |
f930d07e | 447 | s->dma = 1; |
6787f5fa | 448 | /* Reload DMA counter. */ |
5ad6bb97 BS |
449 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
450 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
f930d07e BS |
451 | } else { |
452 | s->dma = 0; | |
453 | } | |
5ad6bb97 BS |
454 | switch(val & CMD_CMD) { |
455 | case CMD_NOP: | |
bf4b9889 | 456 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 457 | break; |
5ad6bb97 | 458 | case CMD_FLUSH: |
bf4b9889 | 459 | trace_esp_mem_writeb_cmd_flush(val); |
9e61bde5 | 460 | //s->ti_size = 0; |
5ad6bb97 BS |
461 | s->rregs[ESP_RINTR] = INTR_FC; |
462 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 463 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 464 | break; |
5ad6bb97 | 465 | case CMD_RESET: |
bf4b9889 | 466 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 467 | esp_soft_reset(s); |
f930d07e | 468 | break; |
5ad6bb97 | 469 | case CMD_BUSRESET: |
bf4b9889 | 470 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 BS |
471 | s->rregs[ESP_RINTR] = INTR_RST; |
472 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 473 | esp_raise_irq(s); |
9e61bde5 | 474 | } |
f930d07e | 475 | break; |
5ad6bb97 | 476 | case CMD_TI: |
f930d07e BS |
477 | handle_ti(s); |
478 | break; | |
5ad6bb97 | 479 | case CMD_ICCS: |
bf4b9889 | 480 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 481 | write_response(s); |
4bf5801d BS |
482 | s->rregs[ESP_RINTR] = INTR_FC; |
483 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 484 | break; |
5ad6bb97 | 485 | case CMD_MSGACC: |
bf4b9889 | 486 | trace_esp_mem_writeb_cmd_msgacc(val); |
5ad6bb97 BS |
487 | s->rregs[ESP_RINTR] = INTR_DC; |
488 | s->rregs[ESP_RSEQ] = 0; | |
4e2a68c1 AT |
489 | s->rregs[ESP_RFLAGS] = 0; |
490 | esp_raise_irq(s); | |
f930d07e | 491 | break; |
0fd0eb21 | 492 | case CMD_PAD: |
bf4b9889 | 493 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 BS |
494 | s->rregs[ESP_RSTAT] = STAT_TC; |
495 | s->rregs[ESP_RINTR] = INTR_FC; | |
496 | s->rregs[ESP_RSEQ] = 0; | |
497 | break; | |
5ad6bb97 | 498 | case CMD_SATN: |
bf4b9889 | 499 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 500 | break; |
6915bff1 HP |
501 | case CMD_RSTATN: |
502 | trace_esp_mem_writeb_cmd_rstatn(val); | |
503 | break; | |
5e1e0a3b | 504 | case CMD_SEL: |
bf4b9889 | 505 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 506 | handle_s_without_atn(s); |
5e1e0a3b | 507 | break; |
5ad6bb97 | 508 | case CMD_SELATN: |
bf4b9889 | 509 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
510 | handle_satn(s); |
511 | break; | |
5ad6bb97 | 512 | case CMD_SELATNS: |
bf4b9889 | 513 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
514 | handle_satn_stop(s); |
515 | break; | |
5ad6bb97 | 516 | case CMD_ENSEL: |
bf4b9889 | 517 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 518 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 519 | break; |
6fe84c18 HP |
520 | case CMD_DISSEL: |
521 | trace_esp_mem_writeb_cmd_dissel(val); | |
522 | s->rregs[ESP_RINTR] = 0; | |
523 | esp_raise_irq(s); | |
524 | break; | |
f930d07e | 525 | default: |
3af4e9aa | 526 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
527 | break; |
528 | } | |
529 | break; | |
5ad6bb97 | 530 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 531 | break; |
5ad6bb97 | 532 | case ESP_CFG1: |
4f6200f0 FB |
533 | s->rregs[saddr] = val; |
534 | break; | |
5ad6bb97 | 535 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 536 | break; |
b44c08fa | 537 | case ESP_CFG2 ... ESP_RES4: |
4f6200f0 FB |
538 | s->rregs[saddr] = val; |
539 | break; | |
6f7e9aec | 540 | default: |
3af4e9aa | 541 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 542 | return; |
6f7e9aec | 543 | } |
2f275b8f | 544 | s->wregs[saddr] = val; |
6f7e9aec FB |
545 | } |
546 | ||
67bb5314 AK |
547 | static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr, |
548 | unsigned size, bool is_write) | |
549 | { | |
550 | return (size == 1) || (is_write && size == 4); | |
551 | } | |
6f7e9aec | 552 | |
9c7e23fc | 553 | const VMStateDescription vmstate_esp = { |
cc9952f3 BS |
554 | .name ="esp", |
555 | .version_id = 3, | |
556 | .minimum_version_id = 3, | |
557 | .minimum_version_id_old = 3, | |
558 | .fields = (VMStateField []) { | |
559 | VMSTATE_BUFFER(rregs, ESPState), | |
560 | VMSTATE_BUFFER(wregs, ESPState), | |
561 | VMSTATE_INT32(ti_size, ESPState), | |
562 | VMSTATE_UINT32(ti_rptr, ESPState), | |
563 | VMSTATE_UINT32(ti_wptr, ESPState), | |
564 | VMSTATE_BUFFER(ti_buf, ESPState), | |
3944966d | 565 | VMSTATE_UINT32(status, ESPState), |
cc9952f3 BS |
566 | VMSTATE_UINT32(dma, ESPState), |
567 | VMSTATE_BUFFER(cmdbuf, ESPState), | |
568 | VMSTATE_UINT32(cmdlen, ESPState), | |
569 | VMSTATE_UINT32(do_cmd, ESPState), | |
570 | VMSTATE_UINT32(dma_left, ESPState), | |
571 | VMSTATE_END_OF_LIST() | |
572 | } | |
573 | }; | |
6f7e9aec | 574 | |
a391fdbc HP |
575 | typedef struct { |
576 | SysBusDevice busdev; | |
577 | MemoryRegion iomem; | |
578 | uint32_t it_shift; | |
579 | ESPState esp; | |
580 | } SysBusESPState; | |
581 | ||
582 | static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr, | |
583 | uint64_t val, unsigned int size) | |
584 | { | |
585 | SysBusESPState *sysbus = opaque; | |
586 | uint32_t saddr; | |
587 | ||
588 | saddr = addr >> sysbus->it_shift; | |
589 | esp_reg_write(&sysbus->esp, saddr, val); | |
590 | } | |
591 | ||
592 | static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr, | |
593 | unsigned int size) | |
594 | { | |
595 | SysBusESPState *sysbus = opaque; | |
596 | uint32_t saddr; | |
597 | ||
598 | saddr = addr >> sysbus->it_shift; | |
599 | return esp_reg_read(&sysbus->esp, saddr); | |
600 | } | |
601 | ||
602 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
603 | .read = sysbus_esp_mem_read, | |
604 | .write = sysbus_esp_mem_write, | |
605 | .endianness = DEVICE_NATIVE_ENDIAN, | |
606 | .valid.accepts = esp_mem_accepts, | |
607 | }; | |
608 | ||
c227f099 | 609 | void esp_init(target_phys_addr_t espaddr, int it_shift, |
ff9868ec BS |
610 | ESPDMAMemoryReadWriteFunc dma_memory_read, |
611 | ESPDMAMemoryReadWriteFunc dma_memory_write, | |
73d74342 BS |
612 | void *dma_opaque, qemu_irq irq, qemu_irq *reset, |
613 | qemu_irq *dma_enable) | |
6f7e9aec | 614 | { |
cfb9de9c PB |
615 | DeviceState *dev; |
616 | SysBusDevice *s; | |
a391fdbc | 617 | SysBusESPState *sysbus; |
ee6847d1 | 618 | ESPState *esp; |
cfb9de9c PB |
619 | |
620 | dev = qdev_create(NULL, "esp"); | |
a391fdbc HP |
621 | sysbus = DO_UPCAST(SysBusESPState, busdev.qdev, dev); |
622 | esp = &sysbus->esp; | |
ee6847d1 GH |
623 | esp->dma_memory_read = dma_memory_read; |
624 | esp->dma_memory_write = dma_memory_write; | |
625 | esp->dma_opaque = dma_opaque; | |
a391fdbc | 626 | sysbus->it_shift = it_shift; |
73d74342 BS |
627 | /* XXX for now until rc4030 has been changed to use DMA enable signal */ |
628 | esp->dma_enabled = 1; | |
e23a1b33 | 629 | qdev_init_nofail(dev); |
cfb9de9c PB |
630 | s = sysbus_from_qdev(dev); |
631 | sysbus_connect_irq(s, 0, irq); | |
632 | sysbus_mmio_map(s, 0, espaddr); | |
74ff8d90 | 633 | *reset = qdev_get_gpio_in(dev, 0); |
73d74342 | 634 | *dma_enable = qdev_get_gpio_in(dev, 1); |
cfb9de9c | 635 | } |
6f7e9aec | 636 | |
afd4030c PB |
637 | static const struct SCSIBusInfo esp_scsi_info = { |
638 | .tcq = false, | |
7e0380b9 PB |
639 | .max_target = ESP_MAX_DEVS, |
640 | .max_lun = 7, | |
afd4030c | 641 | |
c6df7102 | 642 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
643 | .complete = esp_command_complete, |
644 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
645 | }; |
646 | ||
a391fdbc | 647 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 648 | { |
a391fdbc HP |
649 | DeviceState *d = opaque; |
650 | SysBusESPState *sysbus = container_of(d, SysBusESPState, busdev.qdev); | |
651 | ESPState *s = &sysbus->esp; | |
652 | ||
653 | switch (irq) { | |
654 | case 0: | |
655 | parent_esp_reset(s, irq, level); | |
656 | break; | |
657 | case 1: | |
658 | esp_dma_enable(opaque, irq, level); | |
659 | break; | |
660 | } | |
661 | } | |
662 | ||
663 | static int sysbus_esp_init(SysBusDevice *dev) | |
664 | { | |
665 | SysBusESPState *sysbus = FROM_SYSBUS(SysBusESPState, dev); | |
666 | ESPState *s = &sysbus->esp; | |
6f7e9aec | 667 | |
cfb9de9c | 668 | sysbus_init_irq(dev, &s->irq); |
a391fdbc | 669 | assert(sysbus->it_shift != -1); |
6f7e9aec | 670 | |
d32e4b3d | 671 | s->chip_id = TCHI_FAS100A; |
a391fdbc HP |
672 | memory_region_init_io(&sysbus->iomem, &sysbus_esp_mem_ops, sysbus, |
673 | "esp", ESP_REGS << sysbus->it_shift); | |
674 | sysbus_init_mmio(dev, &sysbus->iomem); | |
6f7e9aec | 675 | |
a391fdbc | 676 | qdev_init_gpio_in(&dev->qdev, sysbus_esp_gpio_demux, 2); |
2d069bab | 677 | |
afd4030c | 678 | scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info); |
fa66b909 | 679 | return scsi_bus_legacy_handle_cmdline(&s->bus); |
67e999be | 680 | } |
cfb9de9c | 681 | |
a391fdbc HP |
682 | static void sysbus_esp_hard_reset(DeviceState *dev) |
683 | { | |
684 | SysBusESPState *sysbus = DO_UPCAST(SysBusESPState, busdev.qdev, dev); | |
685 | esp_hard_reset(&sysbus->esp); | |
686 | } | |
687 | ||
688 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
689 | .name = "sysbusespscsi", | |
690 | .version_id = 0, | |
691 | .minimum_version_id = 0, | |
692 | .minimum_version_id_old = 0, | |
693 | .fields = (VMStateField[]) { | |
694 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), | |
695 | VMSTATE_END_OF_LIST() | |
696 | } | |
999e12bb AL |
697 | }; |
698 | ||
a391fdbc | 699 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 700 | { |
39bffca2 | 701 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
702 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
703 | ||
a391fdbc HP |
704 | k->init = sysbus_esp_init; |
705 | dc->reset = sysbus_esp_hard_reset; | |
706 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
999e12bb AL |
707 | } |
708 | ||
1f077308 | 709 | static const TypeInfo sysbus_esp_info = { |
39bffca2 AL |
710 | .name = "esp", |
711 | .parent = TYPE_SYS_BUS_DEVICE, | |
a391fdbc HP |
712 | .instance_size = sizeof(SysBusESPState), |
713 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
714 | }; |
715 | ||
83f7d43a | 716 | static void esp_register_types(void) |
cfb9de9c | 717 | { |
a391fdbc | 718 | type_register_static(&sysbus_esp_info); |
cfb9de9c PB |
719 | } |
720 | ||
83f7d43a | 721 | type_init(esp_register_types) |