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intel_iommu: Add support for Extended Interrupt Mode
[mirror_qemu.git] / hw / i386 / intel_iommu.c
CommitLineData
1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
b6a0aa05 22#include "qemu/osdep.h"
1da12ec4
LT		 23#include "hw/sysbus.h"
24#include "exec/address-spaces.h"
25#include "intel_iommu_internal.h"
7df953bd 26#include "hw/pci/pci.h"
3cb3b154 27#include "hw/pci/pci_bus.h"
621d983a 28#include "hw/i386/pc.h"
04af0e18
PX		 29#include "hw/boards.h"
30#include "hw/i386/x86-iommu.h"
cb135f59 31#include "hw/pci-host/q35.h"
1da12ec4
LT		 32
33/*#define DEBUG_INTEL_IOMMU*/
34#ifdef DEBUG_INTEL_IOMMU
35enum {
36 DEBUG_GENERAL, DEBUG_CSR, DEBUG_INV, DEBUG_MMU, DEBUG_FLOG,
a5861439 37 DEBUG_CACHE, DEBUG_IR,
1da12ec4
LT		 38};
39#define VTD_DBGBIT(x) (1 << DEBUG_##x)
40static int vtd_dbgflags = VTD_DBGBIT(GENERAL) | VTD_DBGBIT(CSR);
41
42#define VTD_DPRINTF(what, fmt, ...) do { \
43 if (vtd_dbgflags & VTD_DBGBIT(what)) { \
44 fprintf(stderr, "(vtd)%s: " fmt "\n", __func__, \
45 ## __VA_ARGS__); } \
46 } while (0)
47#else
48#define VTD_DPRINTF(what, fmt, ...) do {} while (0)
49#endif
50
51static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
52 uint64_t wmask, uint64_t w1cmask)
53{
54 stq_le_p(&s->csr[addr], val);
55 stq_le_p(&s->wmask[addr], wmask);
56 stq_le_p(&s->w1cmask[addr], w1cmask);
57}
58
59static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
60{
61 stq_le_p(&s->womask[addr], mask);
62}
63
64static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
65 uint32_t wmask, uint32_t w1cmask)
66{
67 stl_le_p(&s->csr[addr], val);
68 stl_le_p(&s->wmask[addr], wmask);
69 stl_le_p(&s->w1cmask[addr], w1cmask);
70}
71
72static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
73{
74 stl_le_p(&s->womask[addr], mask);
75}
76
77/* "External" get/set operations */
78static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
79{
80 uint64_t oldval = ldq_le_p(&s->csr[addr]);
81 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
82 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
83 stq_le_p(&s->csr[addr],
84 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
85}
86
87static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
88{
89 uint32_t oldval = ldl_le_p(&s->csr[addr]);
90 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
91 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
92 stl_le_p(&s->csr[addr],
93 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
94}
95
96static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
97{
98 uint64_t val = ldq_le_p(&s->csr[addr]);
99 uint64_t womask = ldq_le_p(&s->womask[addr]);
100 return val & ~womask;
101}
102
103static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
104{
105 uint32_t val = ldl_le_p(&s->csr[addr]);
106 uint32_t womask = ldl_le_p(&s->womask[addr]);
107 return val & ~womask;
108}
109
110/* "Internal" get/set operations */
111static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
112{
113 return ldq_le_p(&s->csr[addr]);
114}
115
116static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
117{
118 return ldl_le_p(&s->csr[addr]);
119}
120
121static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
122{
123 stq_le_p(&s->csr[addr], val);
124}
125
126static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
127 uint32_t clear, uint32_t mask)
128{
129 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
130 stl_le_p(&s->csr[addr], new_val);
131 return new_val;
132}
133
134static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
135 uint64_t clear, uint64_t mask)
136{
137 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
138 stq_le_p(&s->csr[addr], new_val);
139 return new_val;
140}
141
b5a280c0
LT		 142/* GHashTable functions */
143static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
144{
145 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
146}
147
148static guint vtd_uint64_hash(gconstpointer v)
149{
150 return (guint)*(const uint64_t *)v;
151}
152
153static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
154 gpointer user_data)
155{
156 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
157 uint16_t domain_id = *(uint16_t *)user_data;
158 return entry->domain_id == domain_id;
159}
160
d66b969b
JW		 161/* The shift of an addr for a certain level of paging structure */
162static inline uint32_t vtd_slpt_level_shift(uint32_t level)
163{
164 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
165}
166
167static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
168{
169 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
170}
171
b5a280c0
LT		 172static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
173 gpointer user_data)
174{
175 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
176 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
d66b969b
JW		 177 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
178 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
b5a280c0 179 return (entry->domain_id == info->domain_id) &&
d66b969b
JW		 180 (((entry->gfn & info->mask) == gfn) ||
181 (entry->gfn == gfn_tlb));
b5a280c0
LT		 182}
183
d92fa2dc
LT		 184/* Reset all the gen of VTDAddressSpace to zero and set the gen of
185 * IntelIOMMUState to 1.
186 */
187static void vtd_reset_context_cache(IntelIOMMUState *s)
188{
d92fa2dc 189 VTDAddressSpace *vtd_as;
7df953bd
KO		 190 VTDBus *vtd_bus;
191 GHashTableIter bus_it;
d92fa2dc
LT		 192 uint32_t devfn_it;
193
7df953bd
KO		 194 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
195
d92fa2dc 196 VTD_DPRINTF(CACHE, "global context_cache_gen=1");
7df953bd 197 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
04af0e18 198 for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 199 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 200 if (!vtd_as) {
201 continue;
202 }
203 vtd_as->context_cache_entry.context_cache_gen = 0;
204 }
205 }
206 s->context_cache_gen = 1;
207}
208
b5a280c0
LT		 209static void vtd_reset_iotlb(IntelIOMMUState *s)
210{
211 assert(s->iotlb);
212 g_hash_table_remove_all(s->iotlb);
213}
214
d66b969b
JW		 215static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint8_t source_id,
216 uint32_t level)
217{
218 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
219 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
220}
221
222static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
223{
224 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
225}
226
b5a280c0
LT		 227static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
228 hwaddr addr)
229{
d66b969b 230 VTDIOTLBEntry *entry;
b5a280c0 231 uint64_t key;
d66b969b
JW		 232 int level;
233
234 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
235 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
236 source_id, level);
237 entry = g_hash_table_lookup(s->iotlb, &key);
238 if (entry) {
239 goto out;
240 }
241 }
b5a280c0 242
d66b969b
JW		 243out:
244 return entry;
b5a280c0
LT		 245}
246
247static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
248 uint16_t domain_id, hwaddr addr, uint64_t slpte,
d66b969b
JW		 249 bool read_flags, bool write_flags,
250 uint32_t level)
b5a280c0
LT		 251{
252 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
253 uint64_t *key = g_malloc(sizeof(*key));
d66b969b 254 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
b5a280c0
LT		 255
256 VTD_DPRINTF(CACHE, "update iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64
257 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr, slpte,
258 domain_id);
259 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
260 VTD_DPRINTF(CACHE, "iotlb exceeds size limit, forced to reset");
261 vtd_reset_iotlb(s);
262 }
263
264 entry->gfn = gfn;
265 entry->domain_id = domain_id;
266 entry->slpte = slpte;
267 entry->read_flags = read_flags;
268 entry->write_flags = write_flags;
d66b969b
JW		 269 entry->mask = vtd_slpt_level_page_mask(level);
270 *key = vtd_get_iotlb_key(gfn, source_id, level);
b5a280c0
LT		 271 g_hash_table_replace(s->iotlb, key, entry);
272}
273
1da12ec4
LT		 274/* Given the reg addr of both the message data and address, generate an
275 * interrupt via MSI.
276 */
277static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
278 hwaddr mesg_data_reg)
279{
280 hwaddr addr;
281 uint32_t data;
282
283 assert(mesg_data_reg < DMAR_REG_SIZE);
284 assert(mesg_addr_reg < DMAR_REG_SIZE);
285
286 addr = vtd_get_long_raw(s, mesg_addr_reg);
287 data = vtd_get_long_raw(s, mesg_data_reg);
288
289 VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, addr, data);
42874d3a
PM		 290 address_space_stl_le(&address_space_memory, addr, data,
291 MEMTXATTRS_UNSPECIFIED, NULL);
1da12ec4
LT		 292}
293
294/* Generate a fault event to software via MSI if conditions are met.
295 * Notice that the value of FSTS_REG being passed to it should be the one
296 * before any update.
297 */
298static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
299{
300 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
301 pre_fsts & VTD_FSTS_IQE) {
302 VTD_DPRINTF(FLOG, "there are previous interrupt conditions "
303 "to be serviced by software, fault event is not generated "
304 "(FSTS_REG 0x%"PRIx32 ")", pre_fsts);
305 return;
306 }
307 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
308 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
309 VTD_DPRINTF(FLOG, "Interrupt Mask set, fault event is not generated");
310 } else {
311 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
312 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
313 }
314}
315
316/* Check if the Fault (F) field of the Fault Recording Register referenced by
317 * @index is Set.
318 */
319static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
320{
321 /* Each reg is 128-bit */
322 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
323 addr += 8; /* Access the high 64-bit half */
324
325 assert(index < DMAR_FRCD_REG_NR);
326
327 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
328}
329
330/* Update the PPF field of Fault Status Register.
331 * Should be called whenever change the F field of any fault recording
332 * registers.
333 */
334static void vtd_update_fsts_ppf(IntelIOMMUState *s)
335{
336 uint32_t i;
337 uint32_t ppf_mask = 0;
338
339 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
340 if (vtd_is_frcd_set(s, i)) {
341 ppf_mask = VTD_FSTS_PPF;
342 break;
343 }
344 }
345 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
346 VTD_DPRINTF(FLOG, "set PPF of FSTS_REG to %d", ppf_mask ? 1 : 0);
347}
348
349static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
350{
351 /* Each reg is 128-bit */
352 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
353 addr += 8; /* Access the high 64-bit half */
354
355 assert(index < DMAR_FRCD_REG_NR);
356
357 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
358 vtd_update_fsts_ppf(s);
359}
360
361/* Must not update F field now, should be done later */
362static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
363 uint16_t source_id, hwaddr addr,
364 VTDFaultReason fault, bool is_write)
365{
366 uint64_t hi = 0, lo;
367 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
368
369 assert(index < DMAR_FRCD_REG_NR);
370
371 lo = VTD_FRCD_FI(addr);
372 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
373 if (!is_write) {
374 hi |= VTD_FRCD_T;
375 }
376 vtd_set_quad_raw(s, frcd_reg_addr, lo);
377 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
378 VTD_DPRINTF(FLOG, "record to FRCD_REG #%"PRIu16 ": hi 0x%"PRIx64
379 ", lo 0x%"PRIx64, index, hi, lo);
380}
381
382/* Try to collapse multiple pending faults from the same requester */
383static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
384{
385 uint32_t i;
386 uint64_t frcd_reg;
387 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
388
389 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
390 frcd_reg = vtd_get_quad_raw(s, addr);
391 VTD_DPRINTF(FLOG, "frcd_reg #%d 0x%"PRIx64, i, frcd_reg);
392 if ((frcd_reg & VTD_FRCD_F) &&
393 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
394 return true;
395 }
396 addr += 16; /* 128-bit for each */
397 }
398 return false;
399}
400
401/* Log and report an DMAR (address translation) fault to software */
402static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
403 hwaddr addr, VTDFaultReason fault,
404 bool is_write)
405{
406 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
407
408 assert(fault < VTD_FR_MAX);
409
410 if (fault == VTD_FR_RESERVED_ERR) {
411 /* This is not a normal fault reason case. Drop it. */
412 return;
413 }
414 VTD_DPRINTF(FLOG, "sid 0x%"PRIx16 ", fault %d, addr 0x%"PRIx64
415 ", is_write %d", source_id, fault, addr, is_write);
416 if (fsts_reg & VTD_FSTS_PFO) {
417 VTD_DPRINTF(FLOG, "new fault is not recorded due to "
418 "Primary Fault Overflow");
419 return;
420 }
421 if (vtd_try_collapse_fault(s, source_id)) {
422 VTD_DPRINTF(FLOG, "new fault is not recorded due to "
423 "compression of faults");
424 return;
425 }
426 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
427 VTD_DPRINTF(FLOG, "Primary Fault Overflow and "
428 "new fault is not recorded, set PFO field");
429 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
430 return;
431 }
432
433 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
434
435 if (fsts_reg & VTD_FSTS_PPF) {
436 VTD_DPRINTF(FLOG, "there are pending faults already, "
437 "fault event is not generated");
438 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
439 s->next_frcd_reg++;
440 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
441 s->next_frcd_reg = 0;
442 }
443 } else {
444 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
445 VTD_FSTS_FRI(s->next_frcd_reg));
446 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
447 s->next_frcd_reg++;
448 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
449 s->next_frcd_reg = 0;
450 }
451 /* This case actually cause the PPF to be Set.
452 * So generate fault event (interrupt).
453 */
454 vtd_generate_fault_event(s, fsts_reg);
455 }
456}
457
ed7b8fbc
LT		 458/* Handle Invalidation Queue Errors of queued invalidation interface error
459 * conditions.
460 */
461static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
462{
463 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
464
465 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
466 vtd_generate_fault_event(s, fsts_reg);
467}
468
469/* Set the IWC field and try to generate an invalidation completion interrupt */
470static void vtd_generate_completion_event(IntelIOMMUState *s)
471{
472 VTD_DPRINTF(INV, "completes an invalidation wait command with "
473 "Interrupt Flag");
474 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
475 VTD_DPRINTF(INV, "there is a previous interrupt condition to be "
476 "serviced by software, "
477 "new invalidation event is not generated");
478 return;
479 }
480 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
481 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
482 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
483 VTD_DPRINTF(INV, "IM filed in IECTL_REG is set, new invalidation "
484 "event is not generated");
485 return;
486 } else {
487 /* Generate the interrupt event */
488 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
489 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
490 }
491}
492
1da12ec4
LT		 493static inline bool vtd_root_entry_present(VTDRootEntry *root)
494{
495 return root->val & VTD_ROOT_ENTRY_P;
496}
497
498static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
499 VTDRootEntry *re)
500{
501 dma_addr_t addr;
502
503 addr = s->root + index * sizeof(*re);
504 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
505 VTD_DPRINTF(GENERAL, "error: fail to access root-entry at 0x%"PRIx64
506 " + %"PRIu8, s->root, index);
507 re->val = 0;
508 return -VTD_FR_ROOT_TABLE_INV;
509 }
510 re->val = le64_to_cpu(re->val);
511 return 0;
512}
513
514static inline bool vtd_context_entry_present(VTDContextEntry *context)
515{
516 return context->lo & VTD_CONTEXT_ENTRY_P;
517}
518
519static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
520 VTDContextEntry *ce)
521{
522 dma_addr_t addr;
523
524 if (!vtd_root_entry_present(root)) {
525 VTD_DPRINTF(GENERAL, "error: root-entry is not present");
526 return -VTD_FR_ROOT_ENTRY_P;
527 }
528 addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
529 if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
530 VTD_DPRINTF(GENERAL, "error: fail to access context-entry at 0x%"PRIx64
531 " + %"PRIu8,
532 (uint64_t)(root->val & VTD_ROOT_ENTRY_CTP), index);
533 return -VTD_FR_CONTEXT_TABLE_INV;
534 }
535 ce->lo = le64_to_cpu(ce->lo);
536 ce->hi = le64_to_cpu(ce->hi);
537 return 0;
538}
539
540static inline dma_addr_t vtd_get_slpt_base_from_context(VTDContextEntry *ce)
541{
542 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
543}
544
1da12ec4
LT		 545static inline uint64_t vtd_get_slpte_addr(uint64_t slpte)
546{
547 return slpte & VTD_SL_PT_BASE_ADDR_MASK;
548}
549
550/* Whether the pte indicates the address of the page frame */
551static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
552{
553 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
554}
555
556/* Get the content of a spte located in @base_addr[@index] */
557static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
558{
559 uint64_t slpte;
560
561 assert(index < VTD_SL_PT_ENTRY_NR);
562
563 if (dma_memory_read(&address_space_memory,
564 base_addr + index * sizeof(slpte), &slpte,
565 sizeof(slpte))) {
566 slpte = (uint64_t)-1;
567 return slpte;
568 }
569 slpte = le64_to_cpu(slpte);
570 return slpte;
571}
572
573/* Given a gpa and the level of paging structure, return the offset of current
574 * level.
575 */
576static inline uint32_t vtd_gpa_level_offset(uint64_t gpa, uint32_t level)
577{
578 return (gpa >> vtd_slpt_level_shift(level)) &
579 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
580}
581
582/* Check Capability Register to see if the @level of page-table is supported */
583static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
584{
585 return VTD_CAP_SAGAW_MASK & s->cap &
586 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
587}
588
589/* Get the page-table level that hardware should use for the second-level
590 * page-table walk from the Address Width field of context-entry.
591 */
592static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *ce)
593{
594 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
595}
596
597static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce)
598{
599 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
600}
601
602static const uint64_t vtd_paging_entry_rsvd_field[] = {
603 [0] = ~0ULL,
604 /* For not large page */
605 [1] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
606 [2] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
607 [3] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
608 [4] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
609 /* For large page */
610 [5] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
611 [6] = 0x1ff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
612 [7] = 0x3ffff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
613 [8] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
614};
615
616static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
617{
618 if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
619 /* Maybe large page */
620 return slpte & vtd_paging_entry_rsvd_field[level + 4];
621 } else {
622 return slpte & vtd_paging_entry_rsvd_field[level];
623 }
624}
625
626/* Given the @gpa, get relevant @slptep. @slpte_level will be the last level
627 * of the translation, can be used for deciding the size of large page.
628 */
629static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64_t gpa, bool is_write,
630 uint64_t *slptep, uint32_t *slpte_level,
631 bool *reads, bool *writes)
632{
633 dma_addr_t addr = vtd_get_slpt_base_from_context(ce);
634 uint32_t level = vtd_get_level_from_context_entry(ce);
635 uint32_t offset;
636 uint64_t slpte;
637 uint32_t ce_agaw = vtd_get_agaw_from_context_entry(ce);
638 uint64_t access_right_check;
639
640 /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP_REG
641 * and AW in context-entry.
642 */
643 if (gpa & ~((1ULL << MIN(ce_agaw, VTD_MGAW)) - 1)) {
644 VTD_DPRINTF(GENERAL, "error: gpa 0x%"PRIx64 " exceeds limits", gpa);
645 return -VTD_FR_ADDR_BEYOND_MGAW;
646 }
647
648 /* FIXME: what is the Atomics request here? */
649 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
650
651 while (true) {
652 offset = vtd_gpa_level_offset(gpa, level);
653 slpte = vtd_get_slpte(addr, offset);
654
655 if (slpte == (uint64_t)-1) {
656 VTD_DPRINTF(GENERAL, "error: fail to access second-level paging "
657 "entry at level %"PRIu32 " for gpa 0x%"PRIx64,
658 level, gpa);
659 if (level == vtd_get_level_from_context_entry(ce)) {
660 /* Invalid programming of context-entry */
661 return -VTD_FR_CONTEXT_ENTRY_INV;
662 } else {
663 return -VTD_FR_PAGING_ENTRY_INV;
664 }
665 }
666 *reads = (*reads) && (slpte & VTD_SL_R);
667 *writes = (*writes) && (slpte & VTD_SL_W);
668 if (!(slpte & access_right_check)) {
669 VTD_DPRINTF(GENERAL, "error: lack of %s permission for "
670 "gpa 0x%"PRIx64 " slpte 0x%"PRIx64,
671 (is_write ? "write" : "read"), gpa, slpte);
672 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
673 }
674 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
675 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in second "
676 "level paging entry level %"PRIu32 " slpte 0x%"PRIx64,
677 level, slpte);
678 return -VTD_FR_PAGING_ENTRY_RSVD;
679 }
680
681 if (vtd_is_last_slpte(slpte, level)) {
682 *slptep = slpte;
683 *slpte_level = level;
684 return 0;
685 }
686 addr = vtd_get_slpte_addr(slpte);
687 level--;
688 }
689}
690
691/* Map a device to its corresponding domain (context-entry) */
692static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
693 uint8_t devfn, VTDContextEntry *ce)
694{
695 VTDRootEntry re;
696 int ret_fr;
697
698 ret_fr = vtd_get_root_entry(s, bus_num, &re);
699 if (ret_fr) {
700 return ret_fr;
701 }
702
703 if (!vtd_root_entry_present(&re)) {
704 VTD_DPRINTF(GENERAL, "error: root-entry #%"PRIu8 " is not present",
705 bus_num);
706 return -VTD_FR_ROOT_ENTRY_P;
707 } else if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) {
708 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in root-entry "
709 "hi 0x%"PRIx64 " lo 0x%"PRIx64, re.rsvd, re.val);
710 return -VTD_FR_ROOT_ENTRY_RSVD;
711 }
712
713 ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
714 if (ret_fr) {
715 return ret_fr;
716 }
717
718 if (!vtd_context_entry_present(ce)) {
719 VTD_DPRINTF(GENERAL,
720 "error: context-entry #%"PRIu8 "(bus #%"PRIu8 ") "
721 "is not present", devfn, bus_num);
722 return -VTD_FR_CONTEXT_ENTRY_P;
723 } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
724 (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) {
725 VTD_DPRINTF(GENERAL,
726 "error: non-zero reserved field in context-entry "
727 "hi 0x%"PRIx64 " lo 0x%"PRIx64, ce->hi, ce->lo);
728 return -VTD_FR_CONTEXT_ENTRY_RSVD;
729 }
730 /* Check if the programming of context-entry is valid */
731 if (!vtd_is_level_supported(s, vtd_get_level_from_context_entry(ce))) {
732 VTD_DPRINTF(GENERAL, "error: unsupported Address Width value in "
733 "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,
734 ce->hi, ce->lo);
735 return -VTD_FR_CONTEXT_ENTRY_INV;
736 } else if (ce->lo & VTD_CONTEXT_ENTRY_TT) {
737 VTD_DPRINTF(GENERAL, "error: unsupported Translation Type in "
738 "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,
739 ce->hi, ce->lo);
740 return -VTD_FR_CONTEXT_ENTRY_INV;
741 }
742 return 0;
743}
744
745static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
746{
747 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
748}
749
750static const bool vtd_qualified_faults[] = {
751 [VTD_FR_RESERVED] = false,
752 [VTD_FR_ROOT_ENTRY_P] = false,
753 [VTD_FR_CONTEXT_ENTRY_P] = true,
754 [VTD_FR_CONTEXT_ENTRY_INV] = true,
755 [VTD_FR_ADDR_BEYOND_MGAW] = true,
756 [VTD_FR_WRITE] = true,
757 [VTD_FR_READ] = true,
758 [VTD_FR_PAGING_ENTRY_INV] = true,
759 [VTD_FR_ROOT_TABLE_INV] = false,
760 [VTD_FR_CONTEXT_TABLE_INV] = false,
761 [VTD_FR_ROOT_ENTRY_RSVD] = false,
762 [VTD_FR_PAGING_ENTRY_RSVD] = true,
763 [VTD_FR_CONTEXT_ENTRY_TT] = true,
764 [VTD_FR_RESERVED_ERR] = false,
765 [VTD_FR_MAX] = false,
766};
767
768/* To see if a fault condition is "qualified", which is reported to software
769 * only if the FPD field in the context-entry used to process the faulting
770 * request is 0.
771 */
772static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
773{
774 return vtd_qualified_faults[fault];
775}
776
777static inline bool vtd_is_interrupt_addr(hwaddr addr)
778{
779 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
780}
781
782/* Map dev to context-entry then do a paging-structures walk to do a iommu
783 * translation.
79e2b9ae
PB		 784 *
785 * Called from RCU critical section.
786 *
1da12ec4
LT		 787 * @bus_num: The bus number
788 * @devfn: The devfn, which is the combined of device and function number
789 * @is_write: The access is a write operation
790 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
791 */
7df953bd 792static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1da12ec4
LT		 793 uint8_t devfn, hwaddr addr, bool is_write,
794 IOMMUTLBEntry *entry)
795{
d92fa2dc 796 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4 797 VTDContextEntry ce;
7df953bd 798 uint8_t bus_num = pci_bus_num(bus);
d92fa2dc 799 VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
d66b969b 800 uint64_t slpte, page_mask;
1da12ec4
LT		 801 uint32_t level;
802 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
803 int ret_fr;
804 bool is_fpd_set = false;
805 bool reads = true;
806 bool writes = true;
b5a280c0 807 VTDIOTLBEntry *iotlb_entry;
1da12ec4
LT		 808
809 /* Check if the request is in interrupt address range */
810 if (vtd_is_interrupt_addr(addr)) {
811 if (is_write) {
812 /* FIXME: since we don't know the length of the access here, we
813 * treat Non-DWORD length write requests without PASID as
814 * interrupt requests, too. Withoud interrupt remapping support,
815 * we just use 1:1 mapping.
816 */
817 VTD_DPRINTF(MMU, "write request to interrupt address "
818 "gpa 0x%"PRIx64, addr);
819 entry->iova = addr & VTD_PAGE_MASK_4K;
820 entry->translated_addr = addr & VTD_PAGE_MASK_4K;
821 entry->addr_mask = ~VTD_PAGE_MASK_4K;
822 entry->perm = IOMMU_WO;
823 return;
824 } else {
825 VTD_DPRINTF(GENERAL, "error: read request from interrupt address "
826 "gpa 0x%"PRIx64, addr);
827 vtd_report_dmar_fault(s, source_id, addr, VTD_FR_READ, is_write);
828 return;
829 }
830 }
b5a280c0
LT		 831 /* Try to fetch slpte form IOTLB */
832 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
833 if (iotlb_entry) {
834 VTD_DPRINTF(CACHE, "hit iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64
835 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr,
836 iotlb_entry->slpte, iotlb_entry->domain_id);
837 slpte = iotlb_entry->slpte;
838 reads = iotlb_entry->read_flags;
839 writes = iotlb_entry->write_flags;
d66b969b 840 page_mask = iotlb_entry->mask;
b5a280c0
LT		 841 goto out;
842 }
d92fa2dc
LT		 843 /* Try to fetch context-entry from cache first */
844 if (cc_entry->context_cache_gen == s->context_cache_gen) {
845 VTD_DPRINTF(CACHE, "hit context-cache bus %d devfn %d "
846 "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 ")",
847 bus_num, devfn, cc_entry->context_entry.hi,
848 cc_entry->context_entry.lo, cc_entry->context_cache_gen);
849 ce = cc_entry->context_entry;
850 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
851 } else {
852 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
853 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
854 if (ret_fr) {
855 ret_fr = -ret_fr;
856 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
857 VTD_DPRINTF(FLOG, "fault processing is disabled for DMA "
858 "requests through this context-entry "
859 "(with FPD Set)");
860 } else {
861 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
862 }
863 return;
1da12ec4 864 }
d92fa2dc
LT		 865 /* Update context-cache */
866 VTD_DPRINTF(CACHE, "update context-cache bus %d devfn %d "
867 "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 "->%"PRIu32 ")",
868 bus_num, devfn, ce.hi, ce.lo,
869 cc_entry->context_cache_gen, s->context_cache_gen);
870 cc_entry->context_entry = ce;
871 cc_entry->context_cache_gen = s->context_cache_gen;
1da12ec4
LT		 872 }
873
874 ret_fr = vtd_gpa_to_slpte(&ce, addr, is_write, &slpte, &level,
875 &reads, &writes);
876 if (ret_fr) {
877 ret_fr = -ret_fr;
878 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
879 VTD_DPRINTF(FLOG, "fault processing is disabled for DMA requests "
880 "through this context-entry (with FPD Set)");
881 } else {
882 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
883 }
884 return;
885 }
886
d66b969b 887 page_mask = vtd_slpt_level_page_mask(level);
b5a280c0 888 vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
d66b969b 889 reads, writes, level);
b5a280c0 890out:
d66b969b
JW		 891 entry->iova = addr & page_mask;
892 entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
893 entry->addr_mask = ~page_mask;
1da12ec4
LT		 894 entry->perm = (writes ? 2 : 0) + (reads ? 1 : 0);
895}
896
897static void vtd_root_table_setup(IntelIOMMUState *s)
898{
899 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
900 s->root_extended = s->root & VTD_RTADDR_RTT;
901 s->root &= VTD_RTADDR_ADDR_MASK;
902
903 VTD_DPRINTF(CSR, "root_table addr 0x%"PRIx64 " %s", s->root,
904 (s->root_extended ? "(extended)" : ""));
905}
906
02a2cbc8
PX		 907static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
908 uint32_t index, uint32_t mask)
909{
910 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
911}
912
a5861439
PX		 913static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
914{
915 uint64_t value = 0;
916 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
917 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
918 s->intr_root = value & VTD_IRTA_ADDR_MASK;
28589311 919 s->intr_eime = value & VTD_IRTA_EIME;
a5861439 920
02a2cbc8
PX		 921 /* Notify global invalidation */
922 vtd_iec_notify_all(s, true, 0, 0);
a5861439
PX		 923
924 VTD_DPRINTF(CSR, "int remap table addr 0x%"PRIx64 " size %"PRIu32,
925 s->intr_root, s->intr_size);
926}
927
d92fa2dc
LT		 928static void vtd_context_global_invalidate(IntelIOMMUState *s)
929{
930 s->context_cache_gen++;
931 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
932 vtd_reset_context_cache(s);
933 }
934}
935
7df953bd
KO		 936
937/* Find the VTD address space currently associated with a given bus number,
938 */
939static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
940{
941 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
942 if (!vtd_bus) {
943 /* Iterate over the registered buses to find the one
944 * which currently hold this bus number, and update the bus_num lookup table:
945 */
946 GHashTableIter iter;
947
948 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
949 while (g_hash_table_iter_next (&iter, NULL, (void**)&vtd_bus)) {
950 if (pci_bus_num(vtd_bus->bus) == bus_num) {
951 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
952 return vtd_bus;
953 }
954 }
955 }
956 return vtd_bus;
957}
958
d92fa2dc
LT		 959/* Do a context-cache device-selective invalidation.
960 * @func_mask: FM field after shifting
961 */
962static void vtd_context_device_invalidate(IntelIOMMUState *s,
963 uint16_t source_id,
964 uint16_t func_mask)
965{
966 uint16_t mask;
7df953bd 967 VTDBus *vtd_bus;
d92fa2dc
LT		 968 VTDAddressSpace *vtd_as;
969 uint16_t devfn;
970 uint16_t devfn_it;
971
972 switch (func_mask & 3) {
973 case 0:
974 mask = 0; /* No bits in the SID field masked */
975 break;
976 case 1:
977 mask = 4; /* Mask bit 2 in the SID field */
978 break;
979 case 2:
980 mask = 6; /* Mask bit 2:1 in the SID field */
981 break;
982 case 3:
983 mask = 7; /* Mask bit 2:0 in the SID field */
984 break;
985 }
986 VTD_DPRINTF(INV, "device-selective invalidation source 0x%"PRIx16
987 " mask %"PRIu16, source_id, mask);
7df953bd
KO		 988 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
989 if (vtd_bus) {
d92fa2dc 990 devfn = VTD_SID_TO_DEVFN(source_id);
04af0e18 991 for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 992 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 993 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
994 VTD_DPRINTF(INV, "invalidate context-cahce of devfn 0x%"PRIx16,
995 devfn_it);
996 vtd_as->context_cache_entry.context_cache_gen = 0;
997 }
998 }
999 }
1000}
1001
1da12ec4
LT		 1002/* Context-cache invalidation
1003 * Returns the Context Actual Invalidation Granularity.
1004 * @val: the content of the CCMD_REG
1005 */
1006static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1007{
1008 uint64_t caig;
1009 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1010
1011 switch (type) {
d92fa2dc
LT		 1012 case VTD_CCMD_DOMAIN_INVL:
1013 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1014 (uint16_t)VTD_CCMD_DID(val));
1015 /* Fall through */
1da12ec4 1016 case VTD_CCMD_GLOBAL_INVL:
d92fa2dc 1017 VTD_DPRINTF(INV, "global invalidation");
1da12ec4 1018 caig = VTD_CCMD_GLOBAL_INVL_A;
d92fa2dc 1019 vtd_context_global_invalidate(s);
1da12ec4
LT		 1020 break;
1021
1022 case VTD_CCMD_DEVICE_INVL:
1da12ec4 1023 caig = VTD_CCMD_DEVICE_INVL_A;
d92fa2dc 1024 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1da12ec4
LT		 1025 break;
1026
1027 default:
d92fa2dc 1028 VTD_DPRINTF(GENERAL, "error: invalid granularity");
1da12ec4
LT		 1029 caig = 0;
1030 }
1031 return caig;
1032}
1033
b5a280c0
LT		 1034static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1035{
1036 vtd_reset_iotlb(s);
1037}
1038
1039static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1040{
1041 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1042 &domain_id);
1043}
1044
1045static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1046 hwaddr addr, uint8_t am)
1047{
1048 VTDIOTLBPageInvInfo info;
1049
1050 assert(am <= VTD_MAMV);
1051 info.domain_id = domain_id;
d66b969b 1052 info.addr = addr;
b5a280c0
LT		 1053 info.mask = ~((1 << am) - 1);
1054 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
1055}
1056
1da12ec4
LT		 1057/* Flush IOTLB
1058 * Returns the IOTLB Actual Invalidation Granularity.
1059 * @val: the content of the IOTLB_REG
1060 */
1061static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1062{
1063 uint64_t iaig;
1064 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
b5a280c0
LT		 1065 uint16_t domain_id;
1066 hwaddr addr;
1067 uint8_t am;
1da12ec4
LT		 1068
1069 switch (type) {
1070 case VTD_TLB_GLOBAL_FLUSH:
b5a280c0 1071 VTD_DPRINTF(INV, "global invalidation");
1da12ec4 1072 iaig = VTD_TLB_GLOBAL_FLUSH_A;
b5a280c0 1073 vtd_iotlb_global_invalidate(s);
1da12ec4
LT		 1074 break;
1075
1076 case VTD_TLB_DSI_FLUSH:
b5a280c0
LT		 1077 domain_id = VTD_TLB_DID(val);
1078 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1079 domain_id);
1da12ec4 1080 iaig = VTD_TLB_DSI_FLUSH_A;
b5a280c0 1081 vtd_iotlb_domain_invalidate(s, domain_id);
1da12ec4
LT		 1082 break;
1083
1084 case VTD_TLB_PSI_FLUSH:
b5a280c0
LT		 1085 domain_id = VTD_TLB_DID(val);
1086 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1087 am = VTD_IVA_AM(addr);
1088 addr = VTD_IVA_ADDR(addr);
1089 VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1090 " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1091 if (am > VTD_MAMV) {
1092 VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1093 "%"PRIu8, (uint8_t)VTD_MAMV);
1094 iaig = 0;
1095 break;
1096 }
1da12ec4 1097 iaig = VTD_TLB_PSI_FLUSH_A;
b5a280c0 1098 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1da12ec4
LT		 1099 break;
1100
1101 default:
b5a280c0 1102 VTD_DPRINTF(GENERAL, "error: invalid granularity");
1da12ec4
LT		 1103 iaig = 0;
1104 }
1105 return iaig;
1106}
1107
ed7b8fbc
LT		 1108static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s)
1109{
1110 return s->iq_tail == 0;
1111}
1112
1113static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1114{
1115 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1116 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1117}
1118
1119static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1120{
1121 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1122
1123 VTD_DPRINTF(INV, "Queued Invalidation Enable %s", (en ? "on" : "off"));
1124 if (en) {
1125 if (vtd_queued_inv_enable_check(s)) {
1126 s->iq = iqa_val & VTD_IQA_IQA_MASK;
1127 /* 2^(x+8) entries */
1128 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1129 s->qi_enabled = true;
1130 VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val);
1131 VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d",
1132 s->iq, s->iq_size);
1133 /* Ok - report back to driver */
1134 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1135 } else {
1136 VTD_DPRINTF(GENERAL, "error: can't enable Queued Invalidation: "
1137 "tail %"PRIu16, s->iq_tail);
1138 }
1139 } else {
1140 if (vtd_queued_inv_disable_check(s)) {
1141 /* disable Queued Invalidation */
1142 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1143 s->iq_head = 0;
1144 s->qi_enabled = false;
1145 /* Ok - report back to driver */
1146 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1147 } else {
1148 VTD_DPRINTF(GENERAL, "error: can't disable Queued Invalidation: "
1149 "head %"PRIu16 ", tail %"PRIu16
1150 ", last_descriptor %"PRIu8,
1151 s->iq_head, s->iq_tail, s->iq_last_desc_type);
1152 }
1153 }
1154}
1155
1da12ec4
LT		 1156/* Set Root Table Pointer */
1157static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1158{
1159 VTD_DPRINTF(CSR, "set Root Table Pointer");
1160
1161 vtd_root_table_setup(s);
1162 /* Ok - report back to driver */
1163 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1164}
1165
a5861439
PX		 1166/* Set Interrupt Remap Table Pointer */
1167static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1168{
1169 VTD_DPRINTF(CSR, "set Interrupt Remap Table Pointer");
1170
1171 vtd_interrupt_remap_table_setup(s);
1172 /* Ok - report back to driver */
1173 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1174}
1175
1da12ec4
LT		 1176/* Handle Translation Enable/Disable */
1177static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1178{
1179 VTD_DPRINTF(CSR, "Translation Enable %s", (en ? "on" : "off"));
1180
1181 if (en) {
1182 s->dmar_enabled = true;
1183 /* Ok - report back to driver */
1184 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1185 } else {
1186 s->dmar_enabled = false;
1187
1188 /* Clear the index of Fault Recording Register */
1189 s->next_frcd_reg = 0;
1190 /* Ok - report back to driver */
1191 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1192 }
1193}
1194
80de52ba
PX		 1195/* Handle Interrupt Remap Enable/Disable */
1196static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1197{
1198 VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
1199
1200 if (en) {
1201 s->intr_enabled = true;
1202 /* Ok - report back to driver */
1203 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1204 } else {
1205 s->intr_enabled = false;
1206 /* Ok - report back to driver */
1207 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1208 }
1209}
1210
1da12ec4
LT		 1211/* Handle write to Global Command Register */
1212static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1213{
1214 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1215 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1216 uint32_t changed = status ^ val;
1217
1218 VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status);
1219 if (changed & VTD_GCMD_TE) {
1220 /* Translation enable/disable */
1221 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1222 }
1223 if (val & VTD_GCMD_SRTP) {
1224 /* Set/update the root-table pointer */
1225 vtd_handle_gcmd_srtp(s);
1226 }
ed7b8fbc
LT		 1227 if (changed & VTD_GCMD_QIE) {
1228 /* Queued Invalidation Enable */
1229 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1230 }
a5861439
PX		 1231 if (val & VTD_GCMD_SIRTP) {
1232 /* Set/update the interrupt remapping root-table pointer */
1233 vtd_handle_gcmd_sirtp(s);
1234 }
80de52ba
PX		 1235 if (changed & VTD_GCMD_IRE) {
1236 /* Interrupt remap enable/disable */
1237 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1238 }
1da12ec4
LT		 1239}
1240
1241/* Handle write to Context Command Register */
1242static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1243{
1244 uint64_t ret;
1245 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1246
1247 /* Context-cache invalidation request */
1248 if (val & VTD_CCMD_ICC) {
ed7b8fbc
LT		 1249 if (s->qi_enabled) {
1250 VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1251 "should not use register-based invalidation");
1252 return;
1253 }
1da12ec4
LT		 1254 ret = vtd_context_cache_invalidate(s, val);
1255 /* Invalidation completed. Change something to show */
1256 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1257 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1258 ret);
1259 VTD_DPRINTF(INV, "CCMD_REG write-back val: 0x%"PRIx64, ret);
1260 }
1261}
1262
1263/* Handle write to IOTLB Invalidation Register */
1264static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1265{
1266 uint64_t ret;
1267 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1268
1269 /* IOTLB invalidation request */
1270 if (val & VTD_TLB_IVT) {
ed7b8fbc
LT		 1271 if (s->qi_enabled) {
1272 VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1273 "should not use register-based invalidation");
1274 return;
1275 }
1da12ec4
LT		 1276 ret = vtd_iotlb_flush(s, val);
1277 /* Invalidation completed. Change something to show */
1278 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1279 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1280 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1281 VTD_DPRINTF(INV, "IOTLB_REG write-back val: 0x%"PRIx64, ret);
1282 }
1283}
1284
ed7b8fbc
LT		 1285/* Fetch an Invalidation Descriptor from the Invalidation Queue */
1286static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1287 VTDInvDesc *inv_desc)
1288{
1289 dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1290 if (dma_memory_read(&address_space_memory, addr, inv_desc,
1291 sizeof(*inv_desc))) {
1292 VTD_DPRINTF(GENERAL, "error: fail to fetch Invalidation Descriptor "
1293 "base_addr 0x%"PRIx64 " offset %"PRIu32, base_addr, offset);
1294 inv_desc->lo = 0;
1295 inv_desc->hi = 0;
1296
1297 return false;
1298 }
1299 inv_desc->lo = le64_to_cpu(inv_desc->lo);
1300 inv_desc->hi = le64_to_cpu(inv_desc->hi);
1301 return true;
1302}
1303
1304static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1305{
1306 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1307 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
1308 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Invalidation "
1309 "Wait Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1310 inv_desc->hi, inv_desc->lo);
1311 return false;
1312 }
1313 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1314 /* Status Write */
1315 uint32_t status_data = (uint32_t)(inv_desc->lo >>
1316 VTD_INV_DESC_WAIT_DATA_SHIFT);
1317
1318 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1319
1320 /* FIXME: need to be masked with HAW? */
1321 dma_addr_t status_addr = inv_desc->hi;
1322 VTD_DPRINTF(INV, "status data 0x%x, status addr 0x%"PRIx64,
1323 status_data, status_addr);
1324 status_data = cpu_to_le32(status_data);
1325 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1326 sizeof(status_data))) {
1327 VTD_DPRINTF(GENERAL, "error: fail to perform a coherent write");
1328 return false;
1329 }
1330 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1331 /* Interrupt flag */
1332 VTD_DPRINTF(INV, "Invalidation Wait Descriptor interrupt completion");
1333 vtd_generate_completion_event(s);
1334 } else {
1335 VTD_DPRINTF(GENERAL, "error: invalid Invalidation Wait Descriptor: "
1336 "hi 0x%"PRIx64 " lo 0x%"PRIx64, inv_desc->hi, inv_desc->lo);
1337 return false;
1338 }
1339 return true;
1340}
1341
d92fa2dc
LT		 1342static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1343 VTDInvDesc *inv_desc)
1344{
1345 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
1346 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Context-cache "
1347 "Invalidate Descriptor");
1348 return false;
1349 }
1350 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1351 case VTD_INV_DESC_CC_DOMAIN:
1352 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1353 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
1354 /* Fall through */
1355 case VTD_INV_DESC_CC_GLOBAL:
1356 VTD_DPRINTF(INV, "global invalidation");
1357 vtd_context_global_invalidate(s);
1358 break;
1359
1360 case VTD_INV_DESC_CC_DEVICE:
1361 vtd_context_device_invalidate(s, VTD_INV_DESC_CC_SID(inv_desc->lo),
1362 VTD_INV_DESC_CC_FM(inv_desc->lo));
1363 break;
1364
1365 default:
1366 VTD_DPRINTF(GENERAL, "error: invalid granularity in Context-cache "
1367 "Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1368 inv_desc->hi, inv_desc->lo);
1369 return false;
1370 }
1371 return true;
1372}
1373
b5a280c0
LT		 1374static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1375{
1376 uint16_t domain_id;
1377 uint8_t am;
1378 hwaddr addr;
1379
1380 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1381 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
1382 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in IOTLB "
1383 "Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1384 inv_desc->hi, inv_desc->lo);
1385 return false;
1386 }
1387
1388 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1389 case VTD_INV_DESC_IOTLB_GLOBAL:
1390 VTD_DPRINTF(INV, "global invalidation");
1391 vtd_iotlb_global_invalidate(s);
1392 break;
1393
1394 case VTD_INV_DESC_IOTLB_DOMAIN:
1395 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1396 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1397 domain_id);
1398 vtd_iotlb_domain_invalidate(s, domain_id);
1399 break;
1400
1401 case VTD_INV_DESC_IOTLB_PAGE:
1402 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1403 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1404 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
1405 VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1406 " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1407 if (am > VTD_MAMV) {
1408 VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1409 "%"PRIu8, (uint8_t)VTD_MAMV);
1410 return false;
1411 }
1412 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1413 break;
1414
1415 default:
1416 VTD_DPRINTF(GENERAL, "error: invalid granularity in IOTLB Invalidate "
1417 "Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1418 inv_desc->hi, inv_desc->lo);
1419 return false;
1420 }
1421 return true;
1422}
1423
02a2cbc8
PX		 1424static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
1425 VTDInvDesc *inv_desc)
1426{
1427 VTD_DPRINTF(INV, "inv ir glob %d index %d mask %d",
1428 inv_desc->iec.granularity,
1429 inv_desc->iec.index,
1430 inv_desc->iec.index_mask);
1431
1432 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
1433 inv_desc->iec.index,
1434 inv_desc->iec.index_mask);
1435
1436 return true;
1437}
1438
ed7b8fbc
LT		 1439static bool vtd_process_inv_desc(IntelIOMMUState *s)
1440{
1441 VTDInvDesc inv_desc;
1442 uint8_t desc_type;
1443
1444 VTD_DPRINTF(INV, "iq head %"PRIu16, s->iq_head);
1445 if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1446 s->iq_last_desc_type = VTD_INV_DESC_NONE;
1447 return false;
1448 }
1449 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1450 /* FIXME: should update at first or at last? */
1451 s->iq_last_desc_type = desc_type;
1452
1453 switch (desc_type) {
1454 case VTD_INV_DESC_CC:
1455 VTD_DPRINTF(INV, "Context-cache Invalidate Descriptor hi 0x%"PRIx64
1456 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
d92fa2dc
LT		 1457 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1458 return false;
1459 }
ed7b8fbc
LT		 1460 break;
1461
1462 case VTD_INV_DESC_IOTLB:
1463 VTD_DPRINTF(INV, "IOTLB Invalidate Descriptor hi 0x%"PRIx64
1464 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
b5a280c0
LT		 1465 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1466 return false;
1467 }
ed7b8fbc
LT		 1468 break;
1469
1470 case VTD_INV_DESC_WAIT:
1471 VTD_DPRINTF(INV, "Invalidation Wait Descriptor hi 0x%"PRIx64
1472 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1473 if (!vtd_process_wait_desc(s, &inv_desc)) {
1474 return false;
1475 }
1476 break;
1477
b7910472 1478 case VTD_INV_DESC_IEC:
02a2cbc8
PX		 1479 VTD_DPRINTF(INV, "Invalidation Interrupt Entry Cache "
1480 "Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1481 inv_desc.hi, inv_desc.lo);
1482 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
1483 return false;
1484 }
b7910472
PX		 1485 break;
1486
ed7b8fbc
LT		 1487 default:
1488 VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type "
1489 "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8,
1490 inv_desc.hi, inv_desc.lo, desc_type);
1491 return false;
1492 }
1493 s->iq_head++;
1494 if (s->iq_head == s->iq_size) {
1495 s->iq_head = 0;
1496 }
1497 return true;
1498}
1499
1500/* Try to fetch and process more Invalidation Descriptors */
1501static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1502{
1503 VTD_DPRINTF(INV, "fetch Invalidation Descriptors");
1504 if (s->iq_tail >= s->iq_size) {
1505 /* Detects an invalid Tail pointer */
1506 VTD_DPRINTF(GENERAL, "error: iq_tail is %"PRIu16
1507 " while iq_size is %"PRIu16, s->iq_tail, s->iq_size);
1508 vtd_handle_inv_queue_error(s);
1509 return;
1510 }
1511 while (s->iq_head != s->iq_tail) {
1512 if (!vtd_process_inv_desc(s)) {
1513 /* Invalidation Queue Errors */
1514 vtd_handle_inv_queue_error(s);
1515 break;
1516 }
1517 /* Must update the IQH_REG in time */
1518 vtd_set_quad_raw(s, DMAR_IQH_REG,
1519 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
1520 VTD_IQH_QH_MASK);
1521 }
1522}
1523
1524/* Handle write to Invalidation Queue Tail Register */
1525static void vtd_handle_iqt_write(IntelIOMMUState *s)
1526{
1527 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
1528
1529 s->iq_tail = VTD_IQT_QT(val);
1530 VTD_DPRINTF(INV, "set iq tail %"PRIu16, s->iq_tail);
1531 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1532 /* Process Invalidation Queue here */
1533 vtd_fetch_inv_desc(s);
1534 }
1535}
1536
1da12ec4
LT		 1537static void vtd_handle_fsts_write(IntelIOMMUState *s)
1538{
1539 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
1540 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1541 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
1542
1543 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
1544 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1545 VTD_DPRINTF(FLOG, "all pending interrupt conditions serviced, clear "
1546 "IP field of FECTL_REG");
1547 }
ed7b8fbc
LT		 1548 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1549 * Descriptors if there are any when Queued Invalidation is enabled?
1550 */
1da12ec4
LT		 1551}
1552
1553static void vtd_handle_fectl_write(IntelIOMMUState *s)
1554{
1555 uint32_t fectl_reg;
1556 /* FIXME: when software clears the IM field, check the IP field. But do we
1557 * need to compare the old value and the new value to conclude that
1558 * software clears the IM field? Or just check if the IM field is zero?
1559 */
1560 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1561 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
1562 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
1563 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1564 VTD_DPRINTF(FLOG, "IM field is cleared, generate "
1565 "fault event interrupt");
1566 }
1567}
1568
ed7b8fbc
LT		 1569static void vtd_handle_ics_write(IntelIOMMUState *s)
1570{
1571 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
1572 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1573
1574 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
1575 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1576 VTD_DPRINTF(INV, "pending completion interrupt condition serviced, "
1577 "clear IP field of IECTL_REG");
1578 }
1579}
1580
1581static void vtd_handle_iectl_write(IntelIOMMUState *s)
1582{
1583 uint32_t iectl_reg;
1584 /* FIXME: when software clears the IM field, check the IP field. But do we
1585 * need to compare the old value and the new value to conclude that
1586 * software clears the IM field? Or just check if the IM field is zero?
1587 */
1588 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1589 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
1590 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
1591 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1592 VTD_DPRINTF(INV, "IM field is cleared, generate "
1593 "invalidation event interrupt");
1594 }
1595}
1596
1da12ec4
LT		 1597static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
1598{
1599 IntelIOMMUState *s = opaque;
1600 uint64_t val;
1601
1602 if (addr + size > DMAR_REG_SIZE) {
1603 VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1604 ", got 0x%"PRIx64 " %d",
1605 (uint64_t)DMAR_REG_SIZE, addr, size);
1606 return (uint64_t)-1;
1607 }
1608
1609 switch (addr) {
1610 /* Root Table Address Register, 64-bit */
1611 case DMAR_RTADDR_REG:
1612 if (size == 4) {
1613 val = s->root & ((1ULL << 32) - 1);
1614 } else {
1615 val = s->root;
1616 }
1617 break;
1618
1619 case DMAR_RTADDR_REG_HI:
1620 assert(size == 4);
1621 val = s->root >> 32;
1622 break;
1623
ed7b8fbc
LT		 1624 /* Invalidation Queue Address Register, 64-bit */
1625 case DMAR_IQA_REG:
1626 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
1627 if (size == 4) {
1628 val = val & ((1ULL << 32) - 1);
1629 }
1630 break;
1631
1632 case DMAR_IQA_REG_HI:
1633 assert(size == 4);
1634 val = s->iq >> 32;
1635 break;
1636
1da12ec4
LT		 1637 default:
1638 if (size == 4) {
1639 val = vtd_get_long(s, addr);
1640 } else {
1641 val = vtd_get_quad(s, addr);
1642 }
1643 }
1644 VTD_DPRINTF(CSR, "addr 0x%"PRIx64 " size %d val 0x%"PRIx64,
1645 addr, size, val);
1646 return val;
1647}
1648
1649static void vtd_mem_write(void *opaque, hwaddr addr,
1650 uint64_t val, unsigned size)
1651{
1652 IntelIOMMUState *s = opaque;
1653
1654 if (addr + size > DMAR_REG_SIZE) {
1655 VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1656 ", got 0x%"PRIx64 " %d",
1657 (uint64_t)DMAR_REG_SIZE, addr, size);
1658 return;
1659 }
1660
1661 switch (addr) {
1662 /* Global Command Register, 32-bit */
1663 case DMAR_GCMD_REG:
1664 VTD_DPRINTF(CSR, "DMAR_GCMD_REG write addr 0x%"PRIx64
1665 ", size %d, val 0x%"PRIx64, addr, size, val);
1666 vtd_set_long(s, addr, val);
1667 vtd_handle_gcmd_write(s);
1668 break;
1669
1670 /* Context Command Register, 64-bit */
1671 case DMAR_CCMD_REG:
1672 VTD_DPRINTF(CSR, "DMAR_CCMD_REG write addr 0x%"PRIx64
1673 ", size %d, val 0x%"PRIx64, addr, size, val);
1674 if (size == 4) {
1675 vtd_set_long(s, addr, val);
1676 } else {
1677 vtd_set_quad(s, addr, val);
1678 vtd_handle_ccmd_write(s);
1679 }
1680 break;
1681
1682 case DMAR_CCMD_REG_HI:
1683 VTD_DPRINTF(CSR, "DMAR_CCMD_REG_HI write addr 0x%"PRIx64
1684 ", size %d, val 0x%"PRIx64, addr, size, val);
1685 assert(size == 4);
1686 vtd_set_long(s, addr, val);
1687 vtd_handle_ccmd_write(s);
1688 break;
1689
1690 /* IOTLB Invalidation Register, 64-bit */
1691 case DMAR_IOTLB_REG:
1692 VTD_DPRINTF(INV, "DMAR_IOTLB_REG write addr 0x%"PRIx64
1693 ", size %d, val 0x%"PRIx64, addr, size, val);
1694 if (size == 4) {
1695 vtd_set_long(s, addr, val);
1696 } else {
1697 vtd_set_quad(s, addr, val);
1698 vtd_handle_iotlb_write(s);
1699 }
1700 break;
1701
1702 case DMAR_IOTLB_REG_HI:
1703 VTD_DPRINTF(INV, "DMAR_IOTLB_REG_HI write addr 0x%"PRIx64
1704 ", size %d, val 0x%"PRIx64, addr, size, val);
1705 assert(size == 4);
1706 vtd_set_long(s, addr, val);
1707 vtd_handle_iotlb_write(s);
1708 break;
1709
b5a280c0
LT		 1710 /* Invalidate Address Register, 64-bit */
1711 case DMAR_IVA_REG:
1712 VTD_DPRINTF(INV, "DMAR_IVA_REG write addr 0x%"PRIx64
1713 ", size %d, val 0x%"PRIx64, addr, size, val);
1714 if (size == 4) {
1715 vtd_set_long(s, addr, val);
1716 } else {
1717 vtd_set_quad(s, addr, val);
1718 }
1719 break;
1720
1721 case DMAR_IVA_REG_HI:
1722 VTD_DPRINTF(INV, "DMAR_IVA_REG_HI write addr 0x%"PRIx64
1723 ", size %d, val 0x%"PRIx64, addr, size, val);
1724 assert(size == 4);
1725 vtd_set_long(s, addr, val);
1726 break;
1727
1da12ec4
LT		 1728 /* Fault Status Register, 32-bit */
1729 case DMAR_FSTS_REG:
1730 VTD_DPRINTF(FLOG, "DMAR_FSTS_REG write addr 0x%"PRIx64
1731 ", size %d, val 0x%"PRIx64, addr, size, val);
1732 assert(size == 4);
1733 vtd_set_long(s, addr, val);
1734 vtd_handle_fsts_write(s);
1735 break;
1736
1737 /* Fault Event Control Register, 32-bit */
1738 case DMAR_FECTL_REG:
1739 VTD_DPRINTF(FLOG, "DMAR_FECTL_REG write addr 0x%"PRIx64
1740 ", size %d, val 0x%"PRIx64, addr, size, val);
1741 assert(size == 4);
1742 vtd_set_long(s, addr, val);
1743 vtd_handle_fectl_write(s);
1744 break;
1745
1746 /* Fault Event Data Register, 32-bit */
1747 case DMAR_FEDATA_REG:
1748 VTD_DPRINTF(FLOG, "DMAR_FEDATA_REG write addr 0x%"PRIx64
1749 ", size %d, val 0x%"PRIx64, addr, size, val);
1750 assert(size == 4);
1751 vtd_set_long(s, addr, val);
1752 break;
1753
1754 /* Fault Event Address Register, 32-bit */
1755 case DMAR_FEADDR_REG:
1756 VTD_DPRINTF(FLOG, "DMAR_FEADDR_REG write addr 0x%"PRIx64
1757 ", size %d, val 0x%"PRIx64, addr, size, val);
1758 assert(size == 4);
1759 vtd_set_long(s, addr, val);
1760 break;
1761
1762 /* Fault Event Upper Address Register, 32-bit */
1763 case DMAR_FEUADDR_REG:
1764 VTD_DPRINTF(FLOG, "DMAR_FEUADDR_REG write addr 0x%"PRIx64
1765 ", size %d, val 0x%"PRIx64, addr, size, val);
1766 assert(size == 4);
1767 vtd_set_long(s, addr, val);
1768 break;
1769
1770 /* Protected Memory Enable Register, 32-bit */
1771 case DMAR_PMEN_REG:
1772 VTD_DPRINTF(CSR, "DMAR_PMEN_REG write addr 0x%"PRIx64
1773 ", size %d, val 0x%"PRIx64, addr, size, val);
1774 assert(size == 4);
1775 vtd_set_long(s, addr, val);
1776 break;
1777
1778 /* Root Table Address Register, 64-bit */
1779 case DMAR_RTADDR_REG:
1780 VTD_DPRINTF(CSR, "DMAR_RTADDR_REG write addr 0x%"PRIx64
1781 ", size %d, val 0x%"PRIx64, addr, size, val);
1782 if (size == 4) {
1783 vtd_set_long(s, addr, val);
1784 } else {
1785 vtd_set_quad(s, addr, val);
1786 }
1787 break;
1788
1789 case DMAR_RTADDR_REG_HI:
1790 VTD_DPRINTF(CSR, "DMAR_RTADDR_REG_HI write addr 0x%"PRIx64
1791 ", size %d, val 0x%"PRIx64, addr, size, val);
1792 assert(size == 4);
1793 vtd_set_long(s, addr, val);
1794 break;
1795
ed7b8fbc
LT		 1796 /* Invalidation Queue Tail Register, 64-bit */
1797 case DMAR_IQT_REG:
1798 VTD_DPRINTF(INV, "DMAR_IQT_REG write addr 0x%"PRIx64
1799 ", size %d, val 0x%"PRIx64, addr, size, val);
1800 if (size == 4) {
1801 vtd_set_long(s, addr, val);
1802 } else {
1803 vtd_set_quad(s, addr, val);
1804 }
1805 vtd_handle_iqt_write(s);
1806 break;
1807
1808 case DMAR_IQT_REG_HI:
1809 VTD_DPRINTF(INV, "DMAR_IQT_REG_HI write addr 0x%"PRIx64
1810 ", size %d, val 0x%"PRIx64, addr, size, val);
1811 assert(size == 4);
1812 vtd_set_long(s, addr, val);
1813 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
1814 break;
1815
1816 /* Invalidation Queue Address Register, 64-bit */
1817 case DMAR_IQA_REG:
1818 VTD_DPRINTF(INV, "DMAR_IQA_REG write addr 0x%"PRIx64
1819 ", size %d, val 0x%"PRIx64, addr, size, val);
1820 if (size == 4) {
1821 vtd_set_long(s, addr, val);
1822 } else {
1823 vtd_set_quad(s, addr, val);
1824 }
1825 break;
1826
1827 case DMAR_IQA_REG_HI:
1828 VTD_DPRINTF(INV, "DMAR_IQA_REG_HI write addr 0x%"PRIx64
1829 ", size %d, val 0x%"PRIx64, addr, size, val);
1830 assert(size == 4);
1831 vtd_set_long(s, addr, val);
1832 break;
1833
1834 /* Invalidation Completion Status Register, 32-bit */
1835 case DMAR_ICS_REG:
1836 VTD_DPRINTF(INV, "DMAR_ICS_REG write addr 0x%"PRIx64
1837 ", size %d, val 0x%"PRIx64, addr, size, val);
1838 assert(size == 4);
1839 vtd_set_long(s, addr, val);
1840 vtd_handle_ics_write(s);
1841 break;
1842
1843 /* Invalidation Event Control Register, 32-bit */
1844 case DMAR_IECTL_REG:
1845 VTD_DPRINTF(INV, "DMAR_IECTL_REG write addr 0x%"PRIx64
1846 ", size %d, val 0x%"PRIx64, addr, size, val);
1847 assert(size == 4);
1848 vtd_set_long(s, addr, val);
1849 vtd_handle_iectl_write(s);
1850 break;
1851
1852 /* Invalidation Event Data Register, 32-bit */
1853 case DMAR_IEDATA_REG:
1854 VTD_DPRINTF(INV, "DMAR_IEDATA_REG write addr 0x%"PRIx64
1855 ", size %d, val 0x%"PRIx64, addr, size, val);
1856 assert(size == 4);
1857 vtd_set_long(s, addr, val);
1858 break;
1859
1860 /* Invalidation Event Address Register, 32-bit */
1861 case DMAR_IEADDR_REG:
1862 VTD_DPRINTF(INV, "DMAR_IEADDR_REG write addr 0x%"PRIx64
1863 ", size %d, val 0x%"PRIx64, addr, size, val);
1864 assert(size == 4);
1865 vtd_set_long(s, addr, val);
1866 break;
1867
1868 /* Invalidation Event Upper Address Register, 32-bit */
1869 case DMAR_IEUADDR_REG:
1870 VTD_DPRINTF(INV, "DMAR_IEUADDR_REG write addr 0x%"PRIx64
1871 ", size %d, val 0x%"PRIx64, addr, size, val);
1872 assert(size == 4);
1873 vtd_set_long(s, addr, val);
1874 break;
1875
1da12ec4
LT		 1876 /* Fault Recording Registers, 128-bit */
1877 case DMAR_FRCD_REG_0_0:
1878 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_0 write addr 0x%"PRIx64
1879 ", size %d, val 0x%"PRIx64, addr, size, val);
1880 if (size == 4) {
1881 vtd_set_long(s, addr, val);
1882 } else {
1883 vtd_set_quad(s, addr, val);
1884 }
1885 break;
1886
1887 case DMAR_FRCD_REG_0_1:
1888 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_1 write addr 0x%"PRIx64
1889 ", size %d, val 0x%"PRIx64, addr, size, val);
1890 assert(size == 4);
1891 vtd_set_long(s, addr, val);
1892 break;
1893
1894 case DMAR_FRCD_REG_0_2:
1895 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_2 write addr 0x%"PRIx64
1896 ", size %d, val 0x%"PRIx64, addr, size, val);
1897 if (size == 4) {
1898 vtd_set_long(s, addr, val);
1899 } else {
1900 vtd_set_quad(s, addr, val);
1901 /* May clear bit 127 (Fault), update PPF */
1902 vtd_update_fsts_ppf(s);
1903 }
1904 break;
1905
1906 case DMAR_FRCD_REG_0_3:
1907 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_3 write addr 0x%"PRIx64
1908 ", size %d, val 0x%"PRIx64, addr, size, val);
1909 assert(size == 4);
1910 vtd_set_long(s, addr, val);
1911 /* May clear bit 127 (Fault), update PPF */
1912 vtd_update_fsts_ppf(s);
1913 break;
1914
a5861439
PX		 1915 case DMAR_IRTA_REG:
1916 VTD_DPRINTF(IR, "DMAR_IRTA_REG write addr 0x%"PRIx64
1917 ", size %d, val 0x%"PRIx64, addr, size, val);
1918 if (size == 4) {
1919 vtd_set_long(s, addr, val);
1920 } else {
1921 vtd_set_quad(s, addr, val);
1922 }
1923 break;
1924
1925 case DMAR_IRTA_REG_HI:
1926 VTD_DPRINTF(IR, "DMAR_IRTA_REG_HI write addr 0x%"PRIx64
1927 ", size %d, val 0x%"PRIx64, addr, size, val);
1928 assert(size == 4);
1929 vtd_set_long(s, addr, val);
1930 break;
1931
1da12ec4
LT		 1932 default:
1933 VTD_DPRINTF(GENERAL, "error: unhandled reg write addr 0x%"PRIx64
1934 ", size %d, val 0x%"PRIx64, addr, size, val);
1935 if (size == 4) {
1936 vtd_set_long(s, addr, val);
1937 } else {
1938 vtd_set_quad(s, addr, val);
1939 }
1940 }
1941}
1942
1943static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr,
1944 bool is_write)
1945{
1946 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
1947 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4
LT		 1948 IOMMUTLBEntry ret = {
1949 .target_as = &address_space_memory,
1950 .iova = addr,
1951 .translated_addr = 0,
1952 .addr_mask = ~(hwaddr)0,
1953 .perm = IOMMU_NONE,
1954 };
1955
1956 if (!s->dmar_enabled) {
1957 /* DMAR disabled, passthrough, use 4k-page*/
1958 ret.iova = addr & VTD_PAGE_MASK_4K;
1959 ret.translated_addr = addr & VTD_PAGE_MASK_4K;
1960 ret.addr_mask = ~VTD_PAGE_MASK_4K;
1961 ret.perm = IOMMU_RW;
1962 return ret;
1963 }
1964
7df953bd 1965 vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr,
d92fa2dc 1966 is_write, &ret);
1da12ec4
LT		 1967 VTD_DPRINTF(MMU,
1968 "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8
7df953bd 1969 " gpa 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bus),
d92fa2dc
LT		 1970 VTD_PCI_SLOT(vtd_as->devfn), VTD_PCI_FUNC(vtd_as->devfn),
1971 vtd_as->devfn, addr, ret.translated_addr);
1da12ec4
LT		 1972 return ret;
1973}
1974
3cb3b154
AW		 1975static void vtd_iommu_notify_started(MemoryRegion *iommu)
1976{
1977 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
1978
1979 hw_error("Device at bus %s addr %02x.%d requires iommu notifier which "
1980 "is currently not supported by intel-iommu emulation",
1981 vtd_as->bus->qbus.name, PCI_SLOT(vtd_as->devfn),
1982 PCI_FUNC(vtd_as->devfn));
1983}
1984
1da12ec4
LT		 1985static const VMStateDescription vtd_vmstate = {
1986 .name = "iommu-intel",
1987 .unmigratable = 1,
1988};
1989
1990static const MemoryRegionOps vtd_mem_ops = {
1991 .read = vtd_mem_read,
1992 .write = vtd_mem_write,
1993 .endianness = DEVICE_LITTLE_ENDIAN,
1994 .impl = {
1995 .min_access_size = 4,
1996 .max_access_size = 8,
1997 },
1998 .valid = {
1999 .min_access_size = 4,
2000 .max_access_size = 8,
2001 },
2002};
2003
2004static Property vtd_properties[] = {
2005 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
2006 DEFINE_PROP_END_OF_LIST(),
2007};
2008
651e4cef
PX		 2009/* Read IRTE entry with specific index */
2010static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
2011 VTD_IRTE *entry)
2012{
2013 dma_addr_t addr = 0x00;
2014
2015 addr = iommu->intr_root + index * sizeof(*entry);
2016 if (dma_memory_read(&address_space_memory, addr, entry,
2017 sizeof(*entry))) {
2018 VTD_DPRINTF(GENERAL, "error: fail to access IR root at 0x%"PRIx64
2019 " + %"PRIu16, iommu->intr_root, index);
2020 return -VTD_FR_IR_ROOT_INVAL;
2021 }
2022
2023 if (!entry->present) {
2024 VTD_DPRINTF(GENERAL, "error: present flag not set in IRTE"
2025 " entry index %u value 0x%"PRIx64 " 0x%"PRIx64,
2026 index, le64_to_cpu(entry->data[1]),
2027 le64_to_cpu(entry->data[0]));
2028 return -VTD_FR_IR_ENTRY_P;
2029 }
2030
2031 if (entry->__reserved_0 || entry->__reserved_1 || \
2032 entry->__reserved_2) {
2033 VTD_DPRINTF(GENERAL, "error: IRTE entry index %"PRIu16
2034 " reserved fields non-zero: 0x%"PRIx64 " 0x%"PRIx64,
2035 index, le64_to_cpu(entry->data[1]),
2036 le64_to_cpu(entry->data[0]));
2037 return -VTD_FR_IR_IRTE_RSVD;
2038 }
2039
2040 /*
2041 * TODO: Check Source-ID corresponds to SVT (Source Validation
2042 * Type) bits
2043 */
2044
2045 return 0;
2046}
2047
2048/* Fetch IRQ information of specific IR index */
2049static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, VTDIrq *irq)
2050{
09cd058a 2051 VTD_IRTE irte = {};
651e4cef
PX		 2052 int ret = 0;
2053
2054 ret = vtd_irte_get(iommu, index, &irte);
2055 if (ret) {
2056 return ret;
2057 }
2058
2059 irq->trigger_mode = irte.trigger_mode;
2060 irq->vector = irte.vector;
2061 irq->delivery_mode = irte.delivery_mode;
28589311
JK		 2062 irq->dest = le32_to_cpu(irte.dest_id);
2063 if (!iommu->intr_eime) {
651e4cef
PX		 2064#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2065#define VTD_IR_APIC_DEST_SHIFT (8)
28589311
JK		 2066 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
2067 VTD_IR_APIC_DEST_SHIFT;
2068 }
651e4cef
PX		 2069 irq->dest_mode = irte.dest_mode;
2070 irq->redir_hint = irte.redir_hint;
2071
2072 VTD_DPRINTF(IR, "remapping interrupt index %d: trig:%u,vec:%u,"
2073 "deliver:%u,dest:%u,dest_mode:%u", index,
2074 irq->trigger_mode, irq->vector, irq->delivery_mode,
2075 irq->dest, irq->dest_mode);
2076
2077 return 0;
2078}
2079
2080/* Generate one MSI message from VTDIrq info */
2081static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2082{
2083 VTD_MSIMessage msg = {};
2084
2085 /* Generate address bits */
2086 msg.dest_mode = irq->dest_mode;
2087 msg.redir_hint = irq->redir_hint;
2088 msg.dest = irq->dest;
2089 msg.__addr_head = cpu_to_le32(0xfee);
2090 /* Keep this from original MSI address bits */
2091 msg.__not_used = irq->msi_addr_last_bits;
2092
2093 /* Generate data bits */
2094 msg.vector = irq->vector;
2095 msg.delivery_mode = irq->delivery_mode;
2096 msg.level = 1;
2097 msg.trigger_mode = irq->trigger_mode;
2098
2099 msg_out->address = msg.msi_addr;
2100 msg_out->data = msg.msi_data;
2101}
2102
2103/* Interrupt remapping for MSI/MSI-X entry */
2104static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2105 MSIMessage *origin,
2106 MSIMessage *translated)
2107{
2108 int ret = 0;
2109 VTD_IR_MSIAddress addr;
2110 uint16_t index;
09cd058a 2111 VTDIrq irq = {};
651e4cef
PX		 2112
2113 assert(origin && translated);
2114
2115 if (!iommu || !iommu->intr_enabled) {
2116 goto do_not_translate;
2117 }
2118
2119 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
2120 VTD_DPRINTF(GENERAL, "error: MSI addr high 32 bits nonzero"
2121 " during interrupt remapping: 0x%"PRIx32,
2122 (uint32_t)((origin->address & VTD_MSI_ADDR_HI_MASK) >> \
2123 VTD_MSI_ADDR_HI_SHIFT));
2124 return -VTD_FR_IR_REQ_RSVD;
2125 }
2126
2127 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
2128 if (le16_to_cpu(addr.__head) != 0xfee) {
2129 VTD_DPRINTF(GENERAL, "error: MSI addr low 32 bits invalid: "
2130 "0x%"PRIx32, addr.data);
2131 return -VTD_FR_IR_REQ_RSVD;
2132 }
2133
2134 /* This is compatible mode. */
2135 if (addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
2136 goto do_not_translate;
2137 }
2138
2139 index = addr.index_h << 15 | le16_to_cpu(addr.index_l);
2140
2141#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2142#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2143
2144 if (addr.sub_valid) {
2145 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2146 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2147 }
2148
2149 ret = vtd_remap_irq_get(iommu, index, &irq);
2150 if (ret) {
2151 return ret;
2152 }
2153
2154 if (addr.sub_valid) {
2155 VTD_DPRINTF(IR, "received MSI interrupt");
2156 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
2157 VTD_DPRINTF(GENERAL, "error: MSI data bits non-zero for "
2158 "interrupt remappable entry: 0x%"PRIx32,
2159 origin->data);
2160 return -VTD_FR_IR_REQ_RSVD;
2161 }
2162 } else {
2163 uint8_t vector = origin->data & 0xff;
2164 VTD_DPRINTF(IR, "received IOAPIC interrupt");
2165 /* IOAPIC entry vector should be aligned with IRTE vector
2166 * (see vt-d spec 5.1.5.1). */
2167 if (vector != irq.vector) {
2168 VTD_DPRINTF(GENERAL, "IOAPIC vector inconsistent: "
2169 "entry: %d, IRTE: %d, index: %d",
2170 vector, irq.vector, index);
2171 }
2172 }
2173
2174 /*
2175 * We'd better keep the last two bits, assuming that guest OS
2176 * might modify it. Keep it does not hurt after all.
2177 */
2178 irq.msi_addr_last_bits = addr.__not_care;
2179
2180 /* Translate VTDIrq to MSI message */
2181 vtd_generate_msi_message(&irq, translated);
2182
2183 VTD_DPRINTF(IR, "mapping MSI 0x%"PRIx64":0x%"PRIx32 " -> "
2184 "0x%"PRIx64":0x%"PRIx32, origin->address, origin->data,
2185 translated->address, translated->data);
2186 return 0;
2187
2188do_not_translate:
2189 memcpy(translated, origin, sizeof(*origin));
2190 return 0;
2191}
2192
8b5ed7df
PX		 2193static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
2194 MSIMessage *dst, uint16_t sid)
2195{
2196 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), src, dst);
2197}
2198
651e4cef
PX		 2199static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2200 uint64_t *data, unsigned size,
2201 MemTxAttrs attrs)
2202{
2203 return MEMTX_OK;
2204}
2205
2206static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2207 uint64_t value, unsigned size,
2208 MemTxAttrs attrs)
2209{
2210 int ret = 0;
09cd058a 2211 MSIMessage from = {}, to = {};
651e4cef
PX		 2212
2213 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2214 from.data = (uint32_t) value;
2215
2216 ret = vtd_interrupt_remap_msi(opaque, &from, &to);
2217 if (ret) {
2218 /* TODO: report error */
2219 VTD_DPRINTF(GENERAL, "int remap fail for addr 0x%"PRIx64
2220 " data 0x%"PRIx32, from.address, from.data);
2221 /* Drop this interrupt */
2222 return MEMTX_ERROR;
2223 }
2224
2225 VTD_DPRINTF(IR, "delivering MSI 0x%"PRIx64":0x%"PRIx32
2226 " for device sid 0x%04x",
2227 to.address, to.data, sid);
2228
2229 if (dma_memory_write(&address_space_memory, to.address,
2230 &to.data, size)) {
2231 VTD_DPRINTF(GENERAL, "error: fail to write 0x%"PRIx64
2232 " value 0x%"PRIx32, to.address, to.data);
2233 }
2234
2235 return MEMTX_OK;
2236}
2237
2238static const MemoryRegionOps vtd_mem_ir_ops = {
2239 .read_with_attrs = vtd_mem_ir_read,
2240 .write_with_attrs = vtd_mem_ir_write,
2241 .endianness = DEVICE_LITTLE_ENDIAN,
2242 .impl = {
2243 .min_access_size = 4,
2244 .max_access_size = 4,
2245 },
2246 .valid = {
2247 .min_access_size = 4,
2248 .max_access_size = 4,
2249 },
2250};
7df953bd
KO		 2251
2252VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2253{
2254 uintptr_t key = (uintptr_t)bus;
2255 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2256 VTDAddressSpace *vtd_dev_as;
2257
2258 if (!vtd_bus) {
2259 /* No corresponding free() */
04af0e18
PX		 2260 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
2261 X86_IOMMU_PCI_DEVFN_MAX);
7df953bd
KO		 2262 vtd_bus->bus = bus;
2263 key = (uintptr_t)bus;
2264 g_hash_table_insert(s->vtd_as_by_busptr, &key, vtd_bus);
2265 }
2266
2267 vtd_dev_as = vtd_bus->dev_as[devfn];
2268
2269 if (!vtd_dev_as) {
2270 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2271
2272 vtd_dev_as->bus = bus;
2273 vtd_dev_as->devfn = (uint8_t)devfn;
2274 vtd_dev_as->iommu_state = s;
2275 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
2276 memory_region_init_iommu(&vtd_dev_as->iommu, OBJECT(s),
2277 &s->iommu_ops, "intel_iommu", UINT64_MAX);
651e4cef
PX		 2278 memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2279 &vtd_mem_ir_ops, s, "intel_iommu_ir",
2280 VTD_INTERRUPT_ADDR_SIZE);
2281 memory_region_add_subregion(&vtd_dev_as->iommu, VTD_INTERRUPT_ADDR_FIRST,
2282 &vtd_dev_as->iommu_ir);
7df953bd
KO		 2283 address_space_init(&vtd_dev_as->as,
2284 &vtd_dev_as->iommu, "intel_iommu");
2285 }
2286 return vtd_dev_as;
2287}
2288
1da12ec4
LT		 2289/* Do the initialization. It will also be called when reset, so pay
2290 * attention when adding new initialization stuff.
2291 */
2292static void vtd_init(IntelIOMMUState *s)
2293{
d54bd7f8
PX		 2294 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2295
1da12ec4
LT		 2296 memset(s->csr, 0, DMAR_REG_SIZE);
2297 memset(s->wmask, 0, DMAR_REG_SIZE);
2298 memset(s->w1cmask, 0, DMAR_REG_SIZE);
2299 memset(s->womask, 0, DMAR_REG_SIZE);
2300
2301 s->iommu_ops.translate = vtd_iommu_translate;
3cb3b154 2302 s->iommu_ops.notify_started = vtd_iommu_notify_started;
1da12ec4
LT		 2303 s->root = 0;
2304 s->root_extended = false;
2305 s->dmar_enabled = false;
2306 s->iq_head = 0;
2307 s->iq_tail = 0;
2308 s->iq = 0;
2309 s->iq_size = 0;
2310 s->qi_enabled = false;
2311 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2312 s->next_frcd_reg = 0;
2313 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MGAW |
d66b969b 2314 VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
ed7b8fbc 2315 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
1da12ec4 2316
d54bd7f8 2317 if (x86_iommu->intr_supported) {
28589311 2318 s->ecap |= VTD_ECAP_IR | VTD_ECAP_EIM;
d54bd7f8
PX		 2319 }
2320
d92fa2dc 2321 vtd_reset_context_cache(s);
b5a280c0 2322 vtd_reset_iotlb(s);
d92fa2dc 2323
1da12ec4
LT		 2324 /* Define registers with default values and bit semantics */
2325 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
2326 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
2327 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
2328 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
2329 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
2330 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
2331 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
2332 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
2333 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
2334
2335 /* Advanced Fault Logging not supported */
2336 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
2337 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2338 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
2339 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
2340
2341 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2342 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2343 */
2344 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
2345
2346 /* Treated as RO for implementations that PLMR and PHMR fields reported
2347 * as Clear in the CAP_REG.
2348 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2349 */
2350 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
2351
ed7b8fbc
LT		 2352 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
2353 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
2354 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
2355 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
2356 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2357 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
2358 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
2359 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2360 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
2361
1da12ec4
LT		 2362 /* IOTLB registers */
2363 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
2364 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
2365 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
2366
2367 /* Fault Recording Registers, 128-bit */
2368 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
2369 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
a5861439
PX		 2370
2371 /*
28589311 2372 * Interrupt remapping registers.
a5861439 2373 */
28589311 2374 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
1da12ec4
LT		 2375}
2376
2377/* Should not reset address_spaces when reset because devices will still use
2378 * the address space they got at first (won't ask the bus again).
2379 */
2380static void vtd_reset(DeviceState *dev)
2381{
2382 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2383
2384 VTD_DPRINTF(GENERAL, "");
2385 vtd_init(s);
2386}
2387
621d983a
MA		 2388static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
2389{
2390 IntelIOMMUState *s = opaque;
2391 VTDAddressSpace *vtd_as;
2392
04af0e18 2393 assert(0 <= devfn && devfn <= X86_IOMMU_PCI_DEVFN_MAX);
621d983a
MA		 2394
2395 vtd_as = vtd_find_add_as(s, bus, devfn);
2396 return &vtd_as->as;
2397}
2398
1da12ec4
LT		 2399static void vtd_realize(DeviceState *dev, Error **errp)
2400{
cb135f59
PX		 2401 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2402 PCIBus *bus = pcms->bus;
1da12ec4
LT		 2403 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2404
2405 VTD_DPRINTF(GENERAL, "");
7df953bd 2406 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
1da12ec4
LT		 2407 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
2408 "intel_iommu", DMAR_REG_SIZE);
2409 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
b5a280c0
LT		 2410 /* No corresponding destroy */
2411 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
2412 g_free, g_free);
7df953bd
KO		 2413 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
2414 g_free, g_free);
1da12ec4 2415 vtd_init(s);
621d983a
MA		 2416 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
2417 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
cb135f59
PX		 2418 /* Pseudo address space under root PCI bus. */
2419 pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
1da12ec4
LT		 2420}
2421
2422static void vtd_class_init(ObjectClass *klass, void *data)
2423{
2424 DeviceClass *dc = DEVICE_CLASS(klass);
1c7955c4 2425 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
1da12ec4
LT		 2426
2427 dc->reset = vtd_reset;
1da12ec4
LT		 2428 dc->vmsd = &vtd_vmstate;
2429 dc->props = vtd_properties;
621d983a 2430 dc->hotpluggable = false;
1c7955c4 2431 x86_class->realize = vtd_realize;
8b5ed7df 2432 x86_class->int_remap = vtd_int_remap;
1da12ec4
LT		 2433}
2434
2435static const TypeInfo vtd_info = {
2436 .name = TYPE_INTEL_IOMMU_DEVICE,
1c7955c4 2437 .parent = TYPE_X86_IOMMU_DEVICE,
1da12ec4
LT		 2438 .instance_size = sizeof(IntelIOMMUState),
2439 .class_init = vtd_class_init,
2440};
2441
2442static void vtd_register_types(void)
2443{
2444 VTD_DPRINTF(GENERAL, "");
2445 type_register_static(&vtd_info);
2446}
2447
2448type_init(vtd_register_types)
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