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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
d471bf3e | 26 | #include "qemu/units.h" |
83c9f4ca | 27 | #include "hw/hw.h" |
0d09e41a PB |
28 | #include "hw/i386/pc.h" |
29 | #include "hw/char/serial.h" | |
bb3d5ea8 | 30 | #include "hw/char/parallel.h" |
0d09e41a | 31 | #include "hw/i386/apic.h" |
54a40293 EH |
32 | #include "hw/i386/topology.h" |
33 | #include "sysemu/cpus.h" | |
0d09e41a | 34 | #include "hw/block/fdc.h" |
83c9f4ca PB |
35 | #include "hw/ide.h" |
36 | #include "hw/pci/pci.h" | |
2118196b | 37 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
38 | #include "hw/nvram/fw_cfg.h" |
39 | #include "hw/timer/hpet.h" | |
a2eb5c0c | 40 | #include "hw/firmware/smbios.h" |
83c9f4ca | 41 | #include "hw/loader.h" |
ca20cf32 | 42 | #include "elf.h" |
47b43a1f | 43 | #include "multiboot.h" |
0d09e41a | 44 | #include "hw/timer/mc146818rtc.h" |
55f613ac | 45 | #include "hw/dma/i8257.h" |
0d09e41a | 46 | #include "hw/timer/i8254.h" |
47973a2d | 47 | #include "hw/input/i8042.h" |
0d09e41a | 48 | #include "hw/audio/pcspk.h" |
83c9f4ca PB |
49 | #include "hw/pci/msi.h" |
50 | #include "hw/sysbus.h" | |
9c17d615 | 51 | #include "sysemu/sysemu.h" |
e35704ba | 52 | #include "sysemu/numa.h" |
9c17d615 | 53 | #include "sysemu/kvm.h" |
b1c12027 | 54 | #include "sysemu/qtest.h" |
1d31f66b | 55 | #include "kvm_i386.h" |
0d09e41a | 56 | #include "hw/xen/xen.h" |
a19cbfb3 | 57 | #include "ui/qemu-spice.h" |
022c62cb PB |
58 | #include "exec/memory.h" |
59 | #include "exec/address-spaces.h" | |
9c17d615 | 60 | #include "sysemu/arch_init.h" |
1de7afc9 | 61 | #include "qemu/bitmap.h" |
0c764a9d | 62 | #include "qemu/config-file.h" |
d49b6836 | 63 | #include "qemu/error-report.h" |
922a01a0 | 64 | #include "qemu/option.h" |
0445259b | 65 | #include "hw/acpi/acpi.h" |
5ff020b7 | 66 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 67 | #include "hw/boards.h" |
72c194f7 | 68 | #include "acpi-build.h" |
95bee274 | 69 | #include "hw/mem/pc-dimm.h" |
e688df6b | 70 | #include "qapi/error.h" |
9af23989 | 71 | #include "qapi/qapi-visit-common.h" |
bf1e8939 | 72 | #include "qapi/visitor.h" |
15eafc2e | 73 | #include "qom/cpu.h" |
1255166b | 74 | #include "hw/nmi.h" |
60c5e104 | 75 | #include "hw/i386/intel_iommu.h" |
489983d6 | 76 | #include "hw/net/ne2000-isa.h" |
80cabfad | 77 | |
471fd342 BS |
78 | /* debug PC/ISA interrupts */ |
79 | //#define DEBUG_IRQ | |
80 | ||
81 | #ifdef DEBUG_IRQ | |
82 | #define DPRINTF(fmt, ...) \ | |
83 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
84 | #else | |
85 | #define DPRINTF(fmt, ...) | |
86 | #endif | |
87 | ||
8a92ea2f | 88 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 89 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 90 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 91 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 92 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 93 | |
4c5b10b7 JS |
94 | #define E820_NR_ENTRIES 16 |
95 | ||
96 | struct e820_entry { | |
97 | uint64_t address; | |
98 | uint64_t length; | |
99 | uint32_t type; | |
541dc0d4 | 100 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
101 | |
102 | struct e820_table { | |
103 | uint32_t count; | |
104 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 105 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 106 | |
7d67110f GH |
107 | static struct e820_table e820_reserve; |
108 | static struct e820_entry *e820_table; | |
109 | static unsigned e820_entries; | |
dd703b99 | 110 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 111 | |
abd93cc7 MAL |
112 | GlobalProperty pc_compat_3_1[] = { |
113 | { | |
114 | .driver = "intel-iommu", | |
115 | .property = "dma-drain", | |
116 | .value = "off", | |
117 | }, | |
118 | }; | |
119 | const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); | |
120 | ||
ddb3235d MAL |
121 | GlobalProperty pc_compat_3_0[] = { |
122 | { | |
123 | .driver = TYPE_X86_CPU, | |
124 | .property = "x-hv-synic-kvm-only", | |
125 | .value = "on", | |
126 | },{ | |
127 | .driver = "Skylake-Server" "-" TYPE_X86_CPU, | |
128 | .property = "pku", | |
129 | .value = "off", | |
130 | },{ | |
131 | .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU, | |
132 | .property = "pku", | |
133 | .value = "off", | |
134 | }, | |
135 | }; | |
136 | const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); | |
137 | ||
0d47310b MAL |
138 | GlobalProperty pc_compat_2_12[] = { |
139 | { | |
140 | .driver = TYPE_X86_CPU, | |
141 | .property = "legacy-cache", | |
142 | .value = "on", | |
143 | },{ | |
144 | .driver = TYPE_X86_CPU, | |
145 | .property = "topoext", | |
146 | .value = "off", | |
147 | },{ | |
148 | .driver = "EPYC-" TYPE_X86_CPU, | |
149 | .property = "xlevel", | |
150 | .value = stringify(0x8000000a), | |
151 | },{ | |
152 | .driver = "EPYC-IBPB-" TYPE_X86_CPU, | |
153 | .property = "xlevel", | |
154 | .value = stringify(0x8000000a), | |
155 | }, | |
156 | }; | |
157 | const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); | |
158 | ||
43df70a9 MAL |
159 | GlobalProperty pc_compat_2_11[] = { |
160 | { | |
161 | .driver = TYPE_X86_CPU, | |
162 | .property = "x-migrate-smi-count", | |
163 | .value = "off", | |
164 | },{ | |
165 | .driver = "Skylake-Server" "-" TYPE_X86_CPU, | |
166 | .property = "clflushopt", | |
167 | .value = "off", | |
168 | }, | |
169 | }; | |
170 | const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); | |
171 | ||
503224f4 MAL |
172 | GlobalProperty pc_compat_2_10[] = { |
173 | { | |
174 | .driver = TYPE_X86_CPU, | |
175 | .property = "x-hv-max-vps", | |
176 | .value = "0x40", | |
177 | },{ | |
178 | .driver = "i440FX-pcihost", | |
179 | .property = "x-pci-hole64-fix", | |
180 | .value = "off", | |
181 | },{ | |
182 | .driver = "q35-pcihost", | |
183 | .property = "x-pci-hole64-fix", | |
184 | .value = "off", | |
185 | }, | |
186 | }; | |
187 | const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); | |
188 | ||
3e803152 MAL |
189 | GlobalProperty pc_compat_2_9[] = { |
190 | { | |
191 | .driver = "mch", | |
192 | .property = "extended-tseg-mbytes", | |
193 | .value = stringify(0), | |
194 | }, | |
195 | }; | |
196 | const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); | |
197 | ||
edc24ccd MAL |
198 | GlobalProperty pc_compat_2_8[] = { |
199 | { | |
200 | .driver = TYPE_X86_CPU, | |
201 | .property = "tcg-cpuid", | |
202 | .value = "off", | |
203 | }, | |
204 | { | |
205 | .driver = "kvmclock", | |
206 | .property = "x-mach-use-reliable-get-clock", | |
207 | .value = "off", | |
208 | }, | |
209 | { | |
210 | .driver = "ICH9-LPC", | |
211 | .property = "x-smi-broadcast", | |
212 | .value = "off", | |
213 | }, | |
214 | { | |
215 | .driver = TYPE_X86_CPU, | |
216 | .property = "vmware-cpuid-freq", | |
217 | .value = "off", | |
218 | }, | |
219 | { | |
220 | .driver = "Haswell-" TYPE_X86_CPU, | |
221 | .property = "stepping", | |
222 | .value = "1", | |
223 | }, | |
224 | }; | |
225 | const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); | |
226 | ||
5a995064 MAL |
227 | GlobalProperty pc_compat_2_7[] = { |
228 | { | |
229 | .driver = TYPE_X86_CPU, | |
230 | .property = "l3-cache", | |
231 | .value = "off", | |
232 | }, | |
233 | { | |
234 | .driver = TYPE_X86_CPU, | |
235 | .property = "full-cpuid-auto-level", | |
236 | .value = "off", | |
237 | }, | |
238 | { | |
239 | .driver = "Opteron_G3" "-" TYPE_X86_CPU, | |
240 | .property = "family", | |
241 | .value = "15", | |
242 | }, | |
243 | { | |
244 | .driver = "Opteron_G3" "-" TYPE_X86_CPU, | |
245 | .property = "model", | |
246 | .value = "6", | |
247 | }, | |
248 | { | |
249 | .driver = "Opteron_G3" "-" TYPE_X86_CPU, | |
250 | .property = "stepping", | |
251 | .value = "1", | |
252 | }, | |
253 | { | |
254 | .driver = "isa-pcspk", | |
255 | .property = "migrate", | |
256 | .value = "off", | |
257 | }, | |
258 | }; | |
259 | const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); | |
260 | ||
b881fbe9 | 261 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 262 | { |
b881fbe9 | 263 | GSIState *s = opaque; |
1452411b | 264 | |
b881fbe9 JK |
265 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
266 | if (n < ISA_NUM_IRQS) { | |
267 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 268 | } |
b881fbe9 | 269 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 270 | } |
1452411b | 271 | |
258711c6 JG |
272 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
273 | unsigned size) | |
80cabfad FB |
274 | { |
275 | } | |
276 | ||
c02e1eac JG |
277 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
278 | { | |
a6fc23e5 | 279 | return 0xffffffffffffffffULL; |
c02e1eac JG |
280 | } |
281 | ||
f929aad6 | 282 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 283 | static qemu_irq ferr_irq; |
8e78eb28 IY |
284 | |
285 | void pc_register_ferr_irq(qemu_irq irq) | |
286 | { | |
287 | ferr_irq = irq; | |
288 | } | |
289 | ||
f929aad6 FB |
290 | /* XXX: add IGNNE support */ |
291 | void cpu_set_ferr(CPUX86State *s) | |
292 | { | |
d537cf6c | 293 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
294 | } |
295 | ||
258711c6 JG |
296 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
297 | unsigned size) | |
f929aad6 | 298 | { |
d537cf6c | 299 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
300 | } |
301 | ||
c02e1eac JG |
302 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
303 | { | |
a6fc23e5 | 304 | return 0xffffffffffffffffULL; |
c02e1eac JG |
305 | } |
306 | ||
28ab0e2e | 307 | /* TSC handling */ |
28ab0e2e FB |
308 | uint64_t cpu_get_tsc(CPUX86State *env) |
309 | { | |
4a1418e0 | 310 | return cpu_get_ticks(); |
28ab0e2e FB |
311 | } |
312 | ||
3de388f6 | 313 | /* IRQ handling */ |
4a8fa5dc | 314 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 315 | { |
02e51483 | 316 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
317 | int intno; |
318 | ||
bb93e099 WL |
319 | if (!kvm_irqchip_in_kernel()) { |
320 | intno = apic_get_interrupt(cpu->apic_state); | |
321 | if (intno >= 0) { | |
322 | return intno; | |
323 | } | |
324 | /* read the irq from the PIC */ | |
325 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
326 | return -1; | |
327 | } | |
cf6d64bf | 328 | } |
0e21e12b | 329 | |
3de388f6 FB |
330 | intno = pic_read_irq(isa_pic); |
331 | return intno; | |
332 | } | |
333 | ||
d537cf6c | 334 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 335 | { |
182735ef AF |
336 | CPUState *cs = first_cpu; |
337 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 338 | |
471fd342 | 339 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
bb93e099 | 340 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 341 | CPU_FOREACH(cs) { |
182735ef | 342 | cpu = X86_CPU(cs); |
02e51483 CF |
343 | if (apic_accept_pic_intr(cpu->apic_state)) { |
344 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 345 | } |
d5529471 AJ |
346 | } |
347 | } else { | |
d8ed887b | 348 | if (level) { |
c3affe56 | 349 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
350 | } else { |
351 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
352 | } | |
a5b38b51 | 353 | } |
3de388f6 FB |
354 | } |
355 | ||
b0a21b53 FB |
356 | /* PC cmos mappings */ |
357 | ||
80cabfad FB |
358 | #define REG_EQUIPMENT_BYTE 0x14 |
359 | ||
bda05509 | 360 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
361 | { |
362 | int val; | |
363 | ||
364 | switch (fd0) { | |
2da44dd0 | 365 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
366 | /* 1.44 Mb 3"5 drive */ |
367 | val = 4; | |
368 | break; | |
2da44dd0 | 369 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
370 | /* 2.88 Mb 3"5 drive */ |
371 | val = 5; | |
372 | break; | |
2da44dd0 | 373 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
374 | /* 1.2 Mb 5"5 drive */ |
375 | val = 2; | |
376 | break; | |
2da44dd0 | 377 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
378 | default: |
379 | val = 0; | |
380 | break; | |
381 | } | |
382 | return val; | |
383 | } | |
384 | ||
9139046c MA |
385 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
386 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 387 | { |
ba6c2377 FB |
388 | rtc_set_memory(s, type_ofs, 47); |
389 | rtc_set_memory(s, info_ofs, cylinders); | |
390 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
391 | rtc_set_memory(s, info_ofs + 2, heads); | |
392 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
393 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
394 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
395 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
396 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
397 | rtc_set_memory(s, info_ofs + 8, sectors); | |
398 | } | |
399 | ||
6ac0e82d AZ |
400 | /* convert boot_device letter to something recognizable by the bios */ |
401 | static int boot_device2nibble(char boot_device) | |
402 | { | |
403 | switch(boot_device) { | |
404 | case 'a': | |
405 | case 'b': | |
406 | return 0x01; /* floppy boot */ | |
407 | case 'c': | |
408 | return 0x02; /* hard drive boot */ | |
409 | case 'd': | |
410 | return 0x03; /* CD-ROM boot */ | |
411 | case 'n': | |
412 | return 0x04; /* Network boot */ | |
413 | } | |
414 | return 0; | |
415 | } | |
416 | ||
ddcd5531 | 417 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
418 | { |
419 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
420 | int nbds, bds[3] = { 0, }; |
421 | int i; | |
422 | ||
423 | nbds = strlen(boot_device); | |
424 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
425 | error_setg(errp, "Too many boot devices for PC"); |
426 | return; | |
0ecdffbb AJ |
427 | } |
428 | for (i = 0; i < nbds; i++) { | |
429 | bds[i] = boot_device2nibble(boot_device[i]); | |
430 | if (bds[i] == 0) { | |
ddcd5531 GA |
431 | error_setg(errp, "Invalid boot device for PC: '%c'", |
432 | boot_device[i]); | |
433 | return; | |
0ecdffbb AJ |
434 | } |
435 | } | |
436 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 437 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
438 | } |
439 | ||
ddcd5531 | 440 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 441 | { |
ddcd5531 | 442 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
443 | } |
444 | ||
7444ca4e LE |
445 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
446 | { | |
447 | int val, nb, i; | |
2da44dd0 JS |
448 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
449 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
450 | |
451 | /* floppy type */ | |
452 | if (floppy) { | |
453 | for (i = 0; i < 2; i++) { | |
454 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
455 | } | |
456 | } | |
457 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
458 | cmos_get_fd_drive_type(fd_type[1]); | |
459 | rtc_set_memory(rtc_state, 0x10, val); | |
460 | ||
461 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
462 | nb = 0; | |
2da44dd0 | 463 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
464 | nb++; |
465 | } | |
2da44dd0 | 466 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
467 | nb++; |
468 | } | |
469 | switch (nb) { | |
470 | case 0: | |
471 | break; | |
472 | case 1: | |
473 | val |= 0x01; /* 1 drive, ready for boot */ | |
474 | break; | |
475 | case 2: | |
476 | val |= 0x41; /* 2 drives, ready for boot */ | |
477 | break; | |
478 | } | |
479 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
480 | } | |
481 | ||
c0897e0c MA |
482 | typedef struct pc_cmos_init_late_arg { |
483 | ISADevice *rtc_state; | |
9139046c | 484 | BusState *idebus[2]; |
c0897e0c MA |
485 | } pc_cmos_init_late_arg; |
486 | ||
b86f4613 LE |
487 | typedef struct check_fdc_state { |
488 | ISADevice *floppy; | |
489 | bool multiple; | |
490 | } CheckFdcState; | |
491 | ||
492 | static int check_fdc(Object *obj, void *opaque) | |
493 | { | |
494 | CheckFdcState *state = opaque; | |
495 | Object *fdc; | |
496 | uint32_t iobase; | |
497 | Error *local_err = NULL; | |
498 | ||
499 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
500 | if (!fdc) { | |
501 | return 0; | |
502 | } | |
503 | ||
1ea1572a | 504 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
505 | if (local_err || iobase != 0x3f0) { |
506 | error_free(local_err); | |
507 | return 0; | |
508 | } | |
509 | ||
510 | if (state->floppy) { | |
511 | state->multiple = true; | |
512 | } else { | |
513 | state->floppy = ISA_DEVICE(obj); | |
514 | } | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static const char * const fdc_container_path[] = { | |
519 | "/unattached", "/peripheral", "/peripheral-anon" | |
520 | }; | |
521 | ||
424e4a87 RK |
522 | /* |
523 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
524 | * and ACPI objects. | |
525 | */ | |
526 | ISADevice *pc_find_fdc0(void) | |
527 | { | |
528 | int i; | |
529 | Object *container; | |
530 | CheckFdcState state = { 0 }; | |
531 | ||
532 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
533 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
534 | object_child_foreach(container, check_fdc, &state); | |
535 | } | |
536 | ||
537 | if (state.multiple) { | |
3dc6f869 AF |
538 | warn_report("multiple floppy disk controllers with " |
539 | "iobase=0x3f0 have been found"); | |
433672b0 | 540 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 541 | "your intent"); |
424e4a87 RK |
542 | } |
543 | ||
544 | return state.floppy; | |
545 | } | |
546 | ||
c0897e0c MA |
547 | static void pc_cmos_init_late(void *opaque) |
548 | { | |
549 | pc_cmos_init_late_arg *arg = opaque; | |
550 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
551 | int16_t cylinders; |
552 | int8_t heads, sectors; | |
c0897e0c | 553 | int val; |
2adc99b2 | 554 | int i, trans; |
c0897e0c | 555 | |
9139046c | 556 | val = 0; |
272f0428 CP |
557 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
558 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
559 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
560 | val |= 0xf0; | |
561 | } | |
272f0428 CP |
562 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
563 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
564 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
565 | val |= 0x0f; | |
566 | } | |
567 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
568 | |
569 | val = 0; | |
570 | for (i = 0; i < 4; i++) { | |
9139046c MA |
571 | /* NOTE: ide_get_geometry() returns the physical |
572 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
573 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
574 | geometry can be different if a translation is done. */ | |
272f0428 CP |
575 | if (arg->idebus[i / 2] && |
576 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 577 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
578 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
579 | assert((trans & ~3) == 0); | |
580 | val |= trans << (i * 2); | |
c0897e0c MA |
581 | } |
582 | } | |
583 | rtc_set_memory(s, 0x39, val); | |
584 | ||
424e4a87 | 585 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 586 | |
c0897e0c MA |
587 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
588 | } | |
589 | ||
23d30407 | 590 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 591 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 592 | ISADevice *s) |
80cabfad | 593 | { |
7444ca4e | 594 | int val; |
c0897e0c | 595 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 596 | |
b0a21b53 | 597 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
598 | |
599 | /* memory size */ | |
e89001f7 | 600 | /* base memory (first MiB) */ |
d471bf3e | 601 | val = MIN(pcms->below_4g_mem_size / KiB, 640); |
333190eb FB |
602 | rtc_set_memory(s, 0x15, val); |
603 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 604 | /* extended memory (next 64MiB) */ |
d471bf3e PB |
605 | if (pcms->below_4g_mem_size > 1 * MiB) { |
606 | val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; | |
e89001f7 MA |
607 | } else { |
608 | val = 0; | |
609 | } | |
80cabfad FB |
610 | if (val > 65535) |
611 | val = 65535; | |
b0a21b53 FB |
612 | rtc_set_memory(s, 0x17, val); |
613 | rtc_set_memory(s, 0x18, val >> 8); | |
614 | rtc_set_memory(s, 0x30, val); | |
615 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 616 | /* memory between 16MiB and 4GiB */ |
d471bf3e PB |
617 | if (pcms->below_4g_mem_size > 16 * MiB) { |
618 | val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); | |
e89001f7 | 619 | } else { |
9da98861 | 620 | val = 0; |
e89001f7 | 621 | } |
80cabfad FB |
622 | if (val > 65535) |
623 | val = 65535; | |
b0a21b53 FB |
624 | rtc_set_memory(s, 0x34, val); |
625 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 626 | /* memory above 4GiB */ |
88076854 | 627 | val = pcms->above_4g_mem_size / 65536; |
e89001f7 MA |
628 | rtc_set_memory(s, 0x5b, val); |
629 | rtc_set_memory(s, 0x5c, val >> 8); | |
630 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 631 | |
23d30407 | 632 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 633 | TYPE_ISA_DEVICE, |
ec68007a | 634 | (Object **)&pcms->rtc, |
2d996150 | 635 | object_property_allow_set_link, |
265b578c | 636 | OBJ_PROP_LINK_STRONG, &error_abort); |
23d30407 | 637 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 638 | "rtc_state", &error_abort); |
298e01b6 | 639 | |
007b0657 | 640 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 641 | |
b0a21b53 | 642 | val = 0; |
b0a21b53 FB |
643 | val |= 0x02; /* FPU is there */ |
644 | val |= 0x04; /* PS/2 mouse installed */ | |
645 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
646 | ||
b86f4613 | 647 | /* hard drives and FDC */ |
c0897e0c | 648 | arg.rtc_state = s; |
9139046c MA |
649 | arg.idebus[0] = idebus0; |
650 | arg.idebus[1] = idebus1; | |
c0897e0c | 651 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
652 | } |
653 | ||
a0881c64 AF |
654 | #define TYPE_PORT92 "port92" |
655 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
656 | ||
4b78a802 BS |
657 | /* port 92 stuff: could be split off */ |
658 | typedef struct Port92State { | |
a0881c64 AF |
659 | ISADevice parent_obj; |
660 | ||
23af670e | 661 | MemoryRegion io; |
4b78a802 | 662 | uint8_t outport; |
d812b3d6 | 663 | qemu_irq a20_out; |
4b78a802 BS |
664 | } Port92State; |
665 | ||
93ef4192 AG |
666 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
667 | unsigned size) | |
4b78a802 BS |
668 | { |
669 | Port92State *s = opaque; | |
4700a316 | 670 | int oldval = s->outport; |
4b78a802 | 671 | |
c5539cb4 | 672 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 | 673 | s->outport = val; |
d812b3d6 | 674 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 675 | if ((val & 1) && !(oldval & 1)) { |
cf83f140 | 676 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
4b78a802 BS |
677 | } |
678 | } | |
679 | ||
93ef4192 AG |
680 | static uint64_t port92_read(void *opaque, hwaddr addr, |
681 | unsigned size) | |
4b78a802 BS |
682 | { |
683 | Port92State *s = opaque; | |
684 | uint32_t ret; | |
685 | ||
686 | ret = s->outport; | |
687 | DPRINTF("port92: read 0x%02x\n", ret); | |
688 | return ret; | |
689 | } | |
690 | ||
d80fe99d | 691 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 692 | { |
d80fe99d | 693 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
694 | } |
695 | ||
696 | static const VMStateDescription vmstate_port92_isa = { | |
697 | .name = "port92", | |
698 | .version_id = 1, | |
699 | .minimum_version_id = 1, | |
d49805ae | 700 | .fields = (VMStateField[]) { |
4b78a802 BS |
701 | VMSTATE_UINT8(outport, Port92State), |
702 | VMSTATE_END_OF_LIST() | |
703 | } | |
704 | }; | |
705 | ||
706 | static void port92_reset(DeviceState *d) | |
707 | { | |
a0881c64 | 708 | Port92State *s = PORT92(d); |
4b78a802 BS |
709 | |
710 | s->outport &= ~1; | |
711 | } | |
712 | ||
23af670e | 713 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
714 | .read = port92_read, |
715 | .write = port92_write, | |
716 | .impl = { | |
717 | .min_access_size = 1, | |
718 | .max_access_size = 1, | |
719 | }, | |
720 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
721 | }; |
722 | ||
db895a1e | 723 | static void port92_initfn(Object *obj) |
4b78a802 | 724 | { |
db895a1e | 725 | Port92State *s = PORT92(obj); |
4b78a802 | 726 | |
1437c94b | 727 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 728 | |
4b78a802 | 729 | s->outport = 0; |
d812b3d6 EV |
730 | |
731 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
732 | } |
733 | ||
734 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
735 | { | |
736 | ISADevice *isadev = ISA_DEVICE(dev); | |
737 | Port92State *s = PORT92(dev); | |
738 | ||
739 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
740 | } |
741 | ||
8f04ee08 AL |
742 | static void port92_class_initfn(ObjectClass *klass, void *data) |
743 | { | |
39bffca2 | 744 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 745 | |
db895a1e | 746 | dc->realize = port92_realizefn; |
39bffca2 AL |
747 | dc->reset = port92_reset; |
748 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
749 | /* |
750 | * Reason: unlike ordinary ISA devices, this one needs additional | |
751 | * wiring: its A20 output line needs to be wired up by | |
752 | * port92_init(). | |
753 | */ | |
e90f2a8c | 754 | dc->user_creatable = false; |
8f04ee08 AL |
755 | } |
756 | ||
8c43a6f0 | 757 | static const TypeInfo port92_info = { |
a0881c64 | 758 | .name = TYPE_PORT92, |
39bffca2 AL |
759 | .parent = TYPE_ISA_DEVICE, |
760 | .instance_size = sizeof(Port92State), | |
db895a1e | 761 | .instance_init = port92_initfn, |
39bffca2 | 762 | .class_init = port92_class_initfn, |
4b78a802 BS |
763 | }; |
764 | ||
83f7d43a | 765 | static void port92_register_types(void) |
4b78a802 | 766 | { |
39bffca2 | 767 | type_register_static(&port92_info); |
4b78a802 | 768 | } |
83f7d43a AF |
769 | |
770 | type_init(port92_register_types) | |
4b78a802 | 771 | |
956a3e6b | 772 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 773 | { |
cc36a7a2 | 774 | X86CPU *cpu = opaque; |
e1a23744 | 775 | |
956a3e6b | 776 | /* XXX: send to all CPUs ? */ |
4b78a802 | 777 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 778 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
779 | } |
780 | ||
4c5b10b7 JS |
781 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
782 | { | |
7d67110f | 783 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
784 | struct e820_entry *entry; |
785 | ||
7d67110f GH |
786 | if (type != E820_RAM) { |
787 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
788 | if (index >= E820_NR_ENTRIES) { | |
789 | return -EBUSY; | |
790 | } | |
791 | entry = &e820_reserve.entry[index++]; | |
792 | ||
793 | entry->address = cpu_to_le64(address); | |
794 | entry->length = cpu_to_le64(length); | |
795 | entry->type = cpu_to_le32(type); | |
796 | ||
797 | e820_reserve.count = cpu_to_le32(index); | |
798 | } | |
4c5b10b7 | 799 | |
7d67110f | 800 | /* new "etc/e820" file -- include ram too */ |
ab3ad07f | 801 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); |
7d67110f GH |
802 | e820_table[e820_entries].address = cpu_to_le64(address); |
803 | e820_table[e820_entries].length = cpu_to_le64(length); | |
804 | e820_table[e820_entries].type = cpu_to_le32(type); | |
805 | e820_entries++; | |
4c5b10b7 | 806 | |
7d67110f | 807 | return e820_entries; |
4c5b10b7 JS |
808 | } |
809 | ||
7bf8ef19 GS |
810 | int e820_get_num_entries(void) |
811 | { | |
812 | return e820_entries; | |
813 | } | |
814 | ||
815 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
816 | { | |
817 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
818 | *address = le64_to_cpu(e820_table[idx].address); | |
819 | *length = le64_to_cpu(e820_table[idx].length); | |
820 | return true; | |
821 | } | |
822 | return false; | |
823 | } | |
824 | ||
54a40293 EH |
825 | /* Enables contiguous-apic-ID mode, for compatibility */ |
826 | static bool compat_apic_id_mode; | |
827 | ||
828 | void enable_compat_apic_id_mode(void) | |
829 | { | |
830 | compat_apic_id_mode = true; | |
831 | } | |
832 | ||
833 | /* Calculates initial APIC ID for a specific CPU index | |
834 | * | |
835 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
836 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
837 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
838 | * all CPUs up to max_cpus. | |
839 | */ | |
840 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
841 | { | |
842 | uint32_t correct_id; | |
843 | static bool warned; | |
844 | ||
845 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
846 | if (compat_apic_id_mode) { | |
b1c12027 | 847 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { |
54a40293 EH |
848 | error_report("APIC IDs set in compatibility mode, " |
849 | "CPU topology won't match the configuration"); | |
850 | warned = true; | |
851 | } | |
852 | return cpu_index; | |
853 | } else { | |
854 | return correct_id; | |
855 | } | |
856 | } | |
857 | ||
f2098f48 | 858 | static void pc_build_smbios(PCMachineState *pcms) |
80cabfad | 859 | { |
c97294ec GS |
860 | uint8_t *smbios_tables, *smbios_anchor; |
861 | size_t smbios_tables_len, smbios_anchor_len; | |
89cc4a27 WH |
862 | struct smbios_phys_mem_area *mem_array; |
863 | unsigned i, array_count; | |
38690a1c IM |
864 | MachineState *ms = MACHINE(pcms); |
865 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
f2098f48 IM |
866 | |
867 | /* tell smbios about cpuid version and features */ | |
868 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
5fd0a9d4 WH |
869 | |
870 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); | |
871 | if (smbios_tables) { | |
f2098f48 | 872 | fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
5fd0a9d4 WH |
873 | smbios_tables, smbios_tables_len); |
874 | } | |
875 | ||
89cc4a27 WH |
876 | /* build the array of physical mem area from e820 table */ |
877 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
878 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
879 | uint64_t addr, len; | |
880 | ||
881 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
882 | mem_array[array_count].address = addr; | |
883 | mem_array[array_count].length = len; | |
884 | array_count++; | |
885 | } | |
886 | } | |
887 | smbios_get_tables(mem_array, array_count, | |
888 | &smbios_tables, &smbios_tables_len, | |
5fd0a9d4 | 889 | &smbios_anchor, &smbios_anchor_len); |
89cc4a27 WH |
890 | g_free(mem_array); |
891 | ||
5fd0a9d4 | 892 | if (smbios_anchor) { |
f2098f48 | 893 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", |
5fd0a9d4 | 894 | smbios_tables, smbios_tables_len); |
f2098f48 | 895 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", |
5fd0a9d4 WH |
896 | smbios_anchor, smbios_anchor_len); |
897 | } | |
898 | } | |
899 | ||
ebde2465 | 900 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) |
5fd0a9d4 WH |
901 | { |
902 | FWCfgState *fw_cfg; | |
11c2fd3e | 903 | uint64_t *numa_fw_cfg; |
ea265072 IM |
904 | int i; |
905 | const CPUArchIdList *cpus; | |
906 | MachineClass *mc = MACHINE_GET_CLASS(pcms); | |
3cce6243 | 907 | |
305ae888 | 908 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); |
e3cadac0 | 909 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
c886fc4c | 910 | |
1d934e89 EH |
911 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
912 | * | |
a3abd0f2 IM |
913 | * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for |
914 | * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, | |
915 | * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface | |
916 | * for CPU hotplug also uses APIC ID and not "CPU index". | |
917 | * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", | |
918 | * but the "limit to the APIC ID values SeaBIOS may see". | |
1d934e89 | 919 | * |
a3abd0f2 IM |
920 | * So for compatibility reasons with old BIOSes we are stuck with |
921 | * "etc/max-cpus" actually being apic_id_limit | |
1d934e89 | 922 | */ |
ebde2465 | 923 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); |
905fdcb5 | 924 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
925 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
926 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 927 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 928 | |
089da572 | 929 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
930 | &e820_reserve, sizeof(e820_reserve)); |
931 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
932 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 933 | |
089da572 | 934 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
935 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
936 | * of nodes, one word for each VCPU->node and one word for each node to | |
937 | * hold the amount of memory. | |
938 | */ | |
ebde2465 | 939 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); |
11c2fd3e | 940 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
ea265072 IM |
941 | cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); |
942 | for (i = 0; i < cpus->len; i++) { | |
943 | unsigned int apic_id = cpus->cpus[i].arch_id; | |
ebde2465 | 944 | assert(apic_id < pcms->apic_id_limit); |
d41f3e75 | 945 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); |
11c2fd3e AL |
946 | } |
947 | for (i = 0; i < nb_numa_nodes; i++) { | |
ebde2465 IM |
948 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = |
949 | cpu_to_le64(numa_info[i].node_mem); | |
11c2fd3e | 950 | } |
089da572 | 951 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
ebde2465 | 952 | (1 + pcms->apic_id_limit + nb_numa_nodes) * |
1d934e89 | 953 | sizeof(*numa_fw_cfg)); |
bf483392 AG |
954 | |
955 | return fw_cfg; | |
80cabfad FB |
956 | } |
957 | ||
642a4f96 TS |
958 | static long get_file_size(FILE *f) |
959 | { | |
960 | long where, size; | |
961 | ||
962 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
963 | ||
964 | where = ftell(f); | |
965 | fseek(f, 0, SEEK_END); | |
966 | size = ftell(f); | |
967 | fseek(f, where, SEEK_SET); | |
968 | ||
969 | return size; | |
970 | } | |
971 | ||
3cbeb524 AB |
972 | /* setup_data types */ |
973 | #define SETUP_NONE 0 | |
974 | #define SETUP_E820_EXT 1 | |
975 | #define SETUP_DTB 2 | |
976 | #define SETUP_PCI 3 | |
977 | #define SETUP_EFI 4 | |
978 | ||
979 | struct setup_data { | |
980 | uint64_t next; | |
981 | uint32_t type; | |
982 | uint32_t len; | |
983 | uint8_t data[0]; | |
984 | } __attribute__((packed)); | |
985 | ||
df1f79fd EH |
986 | static void load_linux(PCMachineState *pcms, |
987 | FWCfgState *fw_cfg) | |
642a4f96 TS |
988 | { |
989 | uint16_t protocol; | |
f3839fda | 990 | int setup_size, kernel_size, cmdline_size; |
3cbeb524 | 991 | int dtb_size, setup_data_offset; |
642a4f96 | 992 | uint32_t initrd_max; |
c24323dd | 993 | uint8_t header[8192], *setup, *kernel; |
a8170e5e | 994 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 995 | FILE *f; |
bf4e5d92 | 996 | char *vmode; |
df1f79fd | 997 | MachineState *machine = MACHINE(pcms); |
cd4040ec | 998 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
3cbeb524 | 999 | struct setup_data *setup_data; |
df1f79fd EH |
1000 | const char *kernel_filename = machine->kernel_filename; |
1001 | const char *initrd_filename = machine->initrd_filename; | |
3cbeb524 | 1002 | const char *dtb_filename = machine->dtb; |
df1f79fd | 1003 | const char *kernel_cmdline = machine->kernel_cmdline; |
642a4f96 TS |
1004 | |
1005 | /* Align to 16 bytes as a paranoia measure */ | |
1006 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
1007 | ||
1008 | /* load the kernel header */ | |
1009 | f = fopen(kernel_filename, "rb"); | |
1010 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
1011 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
1012 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
1013 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
1014 | kernel_filename, strerror(errno)); | |
1015 | exit(1); | |
642a4f96 TS |
1016 | } |
1017 | ||
1018 | /* kernel protocol version */ | |
bc4edd79 | 1019 | #if 0 |
642a4f96 | 1020 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 1021 | #endif |
0f9d76e5 LG |
1022 | if (ldl_p(header+0x202) == 0x53726448) { |
1023 | protocol = lduw_p(header+0x206); | |
1024 | } else { | |
1025 | /* This looks like a multiboot kernel. If it is, let's stop | |
1026 | treating it like a Linux kernel. */ | |
52001445 | 1027 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 1028 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 1029 | return; |
0f9d76e5 LG |
1030 | } |
1031 | protocol = 0; | |
f16408df | 1032 | } |
642a4f96 TS |
1033 | |
1034 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
1035 | /* Low kernel */ |
1036 | real_addr = 0x90000; | |
1037 | cmdline_addr = 0x9a000 - cmdline_size; | |
1038 | prot_addr = 0x10000; | |
642a4f96 | 1039 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
1040 | /* High but ancient kernel */ |
1041 | real_addr = 0x90000; | |
1042 | cmdline_addr = 0x9a000 - cmdline_size; | |
1043 | prot_addr = 0x100000; | |
642a4f96 | 1044 | } else { |
0f9d76e5 LG |
1045 | /* High and recent kernel */ |
1046 | real_addr = 0x10000; | |
1047 | cmdline_addr = 0x20000; | |
1048 | prot_addr = 0x100000; | |
642a4f96 TS |
1049 | } |
1050 | ||
bc4edd79 | 1051 | #if 0 |
642a4f96 | 1052 | fprintf(stderr, |
0f9d76e5 LG |
1053 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
1054 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
1055 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
1056 | real_addr, | |
1057 | cmdline_addr, | |
1058 | prot_addr); | |
bc4edd79 | 1059 | #endif |
642a4f96 TS |
1060 | |
1061 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
1062 | if (protocol >= 0x203) { |
1063 | initrd_max = ldl_p(header+0x22c); | |
1064 | } else { | |
1065 | initrd_max = 0x37ffffff; | |
1066 | } | |
642a4f96 | 1067 | |
cd4040ec EH |
1068 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { |
1069 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
927766c7 | 1070 | } |
642a4f96 | 1071 | |
57a46d05 AG |
1072 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
1073 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 1074 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
1075 | |
1076 | if (protocol >= 0x202) { | |
0f9d76e5 | 1077 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 1078 | } else { |
0f9d76e5 LG |
1079 | stw_p(header+0x20, 0xA33F); |
1080 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
1081 | } |
1082 | ||
bf4e5d92 PT |
1083 | /* handle vga= parameter */ |
1084 | vmode = strstr(kernel_cmdline, "vga="); | |
1085 | if (vmode) { | |
1086 | unsigned int video_mode; | |
1087 | /* skip "vga=" */ | |
1088 | vmode += 4; | |
1089 | if (!strncmp(vmode, "normal", 6)) { | |
1090 | video_mode = 0xffff; | |
1091 | } else if (!strncmp(vmode, "ext", 3)) { | |
1092 | video_mode = 0xfffe; | |
1093 | } else if (!strncmp(vmode, "ask", 3)) { | |
1094 | video_mode = 0xfffd; | |
1095 | } else { | |
1096 | video_mode = strtol(vmode, NULL, 0); | |
1097 | } | |
1098 | stw_p(header+0x1fa, video_mode); | |
1099 | } | |
1100 | ||
642a4f96 | 1101 | /* loader type */ |
5cbdb3a3 | 1102 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
1103 | If this code is substantially changed, you may want to consider |
1104 | incrementing the revision. */ | |
0f9d76e5 LG |
1105 | if (protocol >= 0x200) { |
1106 | header[0x210] = 0xB0; | |
1107 | } | |
642a4f96 TS |
1108 | /* heap */ |
1109 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
1110 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
1111 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
1112 | } |
1113 | ||
1114 | /* load initrd */ | |
1115 | if (initrd_filename) { | |
c24323dd PM |
1116 | gsize initrd_size; |
1117 | gchar *initrd_data; | |
1118 | GError *gerr = NULL; | |
1119 | ||
0f9d76e5 LG |
1120 | if (protocol < 0x200) { |
1121 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
1122 | exit(1); | |
1123 | } | |
642a4f96 | 1124 | |
c24323dd PM |
1125 | if (!g_file_get_contents(initrd_filename, &initrd_data, |
1126 | &initrd_size, &gerr)) { | |
7454e51d | 1127 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
c24323dd | 1128 | initrd_filename, gerr->message); |
d6fa4b77 | 1129 | exit(1); |
c24323dd PM |
1130 | } |
1131 | if (initrd_size >= initrd_max) { | |
f3839fda | 1132 | fprintf(stderr, "qemu: initrd is too large, cannot support." |
c24323dd PM |
1133 | "(max: %"PRIu32", need %"PRId64")\n", |
1134 | initrd_max, (uint64_t)initrd_size); | |
f3839fda | 1135 | exit(1); |
d6fa4b77 MK |
1136 | } |
1137 | ||
45a50b16 | 1138 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 1139 | |
57a46d05 AG |
1140 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
1141 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
1142 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 1143 | |
0f9d76e5 LG |
1144 | stl_p(header+0x218, initrd_addr); |
1145 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
1146 | } |
1147 | ||
45a50b16 | 1148 | /* load kernel and setup */ |
642a4f96 | 1149 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
1150 | if (setup_size == 0) { |
1151 | setup_size = 4; | |
1152 | } | |
642a4f96 | 1153 | setup_size = (setup_size+1)*512; |
ec5fd402 PB |
1154 | if (setup_size > kernel_size) { |
1155 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
1156 | exit(1); | |
1157 | } | |
45a50b16 | 1158 | kernel_size -= setup_size; |
642a4f96 | 1159 | |
7267c094 AL |
1160 | setup = g_malloc(setup_size); |
1161 | kernel = g_malloc(kernel_size); | |
45a50b16 | 1162 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
1163 | if (fread(setup, 1, setup_size, f) != setup_size) { |
1164 | fprintf(stderr, "fread() failed\n"); | |
1165 | exit(1); | |
1166 | } | |
1167 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1168 | fprintf(stderr, "fread() failed\n"); | |
1169 | exit(1); | |
1170 | } | |
642a4f96 | 1171 | fclose(f); |
3cbeb524 AB |
1172 | |
1173 | /* append dtb to kernel */ | |
1174 | if (dtb_filename) { | |
1175 | if (protocol < 0x209) { | |
1176 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1177 | exit(1); | |
1178 | } | |
1179 | ||
1180 | dtb_size = get_image_size(dtb_filename); | |
1181 | if (dtb_size <= 0) { | |
1182 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1183 | dtb_filename, strerror(errno)); | |
1184 | exit(1); | |
1185 | } | |
1186 | ||
1187 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1188 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1189 | kernel = g_realloc(kernel, kernel_size); | |
1190 | ||
1191 | stq_p(header+0x250, prot_addr + setup_data_offset); | |
1192 | ||
1193 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1194 | setup_data->next = 0; | |
1195 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1196 | setup_data->len = cpu_to_le32(dtb_size); | |
1197 | ||
1198 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1199 | } | |
1200 | ||
45a50b16 | 1201 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
1202 | |
1203 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1204 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1205 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1206 | ||
1207 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1208 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1209 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1210 | ||
98e753a6 IM |
1211 | option_rom[nb_option_roms].bootindex = 0; |
1212 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1213 | if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { | |
b2a575a1 | 1214 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; |
b2a575a1 | 1215 | } |
57a46d05 | 1216 | nb_option_roms++; |
642a4f96 TS |
1217 | } |
1218 | ||
b41a2cd1 FB |
1219 | #define NE2000_NB_MAX 6 |
1220 | ||
675d6f82 BS |
1221 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
1222 | 0x280, 0x380 }; | |
1223 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 1224 | |
48a18b3c | 1225 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
1226 | { |
1227 | static int nb_ne2k = 0; | |
1228 | ||
1229 | if (nb_ne2k == NE2000_NB_MAX) | |
1230 | return; | |
48a18b3c | 1231 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 1232 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
1233 | nb_ne2k++; |
1234 | } | |
1235 | ||
92a16d7a | 1236 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 1237 | { |
4917cf44 AF |
1238 | if (current_cpu) { |
1239 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 1240 | return cpu->apic_state; |
0e26b7b8 BS |
1241 | } else { |
1242 | return NULL; | |
1243 | } | |
1244 | } | |
1245 | ||
845773ab | 1246 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 1247 | { |
c3affe56 | 1248 | X86CPU *cpu = opaque; |
53b67b30 BS |
1249 | |
1250 | if (level) { | |
c3affe56 | 1251 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
1252 | } |
1253 | } | |
1254 | ||
074281d6 | 1255 | static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) |
31050930 | 1256 | { |
074281d6 | 1257 | Object *cpu = NULL; |
31050930 IM |
1258 | Error *local_err = NULL; |
1259 | ||
074281d6 | 1260 | cpu = object_new(typename); |
31050930 | 1261 | |
c7b4efb4 | 1262 | object_property_set_uint(cpu, apic_id, "apic-id", &local_err); |
074281d6 | 1263 | object_property_set_bool(cpu, true, "realized", &local_err); |
31050930 | 1264 | |
074281d6 | 1265 | object_unref(cpu); |
021c9d25 | 1266 | error_propagate(errp, local_err); |
31050930 IM |
1267 | } |
1268 | ||
c649983b IM |
1269 | void pc_hot_add_cpu(const int64_t id, Error **errp) |
1270 | { | |
38690a1c | 1271 | MachineState *ms = MACHINE(qdev_get_machine()); |
c649983b | 1272 | int64_t apic_id = x86_cpu_apic_id_from_index(id); |
0e3bd562 | 1273 | Error *local_err = NULL; |
c649983b | 1274 | |
8de433cb IM |
1275 | if (id < 0) { |
1276 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1277 | return; | |
1278 | } | |
1279 | ||
5ff020b7 EH |
1280 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1281 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1282 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1283 | id, apic_id); | |
1284 | return; | |
1285 | } | |
1286 | ||
311ca98d | 1287 | pc_new_cpu(ms->cpu_type, apic_id, &local_err); |
0e3bd562 AF |
1288 | if (local_err) { |
1289 | error_propagate(errp, local_err); | |
1290 | return; | |
1291 | } | |
c649983b IM |
1292 | } |
1293 | ||
4884b7bf | 1294 | void pc_cpus_init(PCMachineState *pcms) |
70166477 IY |
1295 | { |
1296 | int i; | |
c96a1c0b | 1297 | const CPUArchIdList *possible_cpus; |
311ca98d | 1298 | MachineState *ms = MACHINE(pcms); |
c96a1c0b | 1299 | MachineClass *mc = MACHINE_GET_CLASS(pcms); |
70166477 | 1300 | |
ebde2465 IM |
1301 | /* Calculates the limit to CPU APIC ID values |
1302 | * | |
1303 | * Limit for the APIC ID value, so that all | |
1304 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1305 | * | |
1306 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1307 | */ | |
1308 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
311ca98d | 1309 | possible_cpus = mc->possible_cpu_arch_ids(ms); |
c96a1c0b | 1310 | for (i = 0; i < smp_cpus; i++) { |
d342eb76 IM |
1311 | pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, |
1312 | &error_fatal); | |
70166477 IY |
1313 | } |
1314 | } | |
1315 | ||
217f1b4a HZ |
1316 | static void pc_build_feature_control_file(PCMachineState *pcms) |
1317 | { | |
38690a1c IM |
1318 | MachineState *ms = MACHINE(pcms); |
1319 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
217f1b4a HZ |
1320 | CPUX86State *env = &cpu->env; |
1321 | uint32_t unused, ecx, edx; | |
1322 | uint64_t feature_control_bits = 0; | |
1323 | uint64_t *val; | |
1324 | ||
1325 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); | |
1326 | if (ecx & CPUID_EXT_VMX) { | |
1327 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1328 | } | |
1329 | ||
1330 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == | |
1331 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && | |
1332 | (env->mcg_cap & MCG_LMCE_P)) { | |
1333 | feature_control_bits |= FEATURE_CONTROL_LMCE; | |
1334 | } | |
1335 | ||
1336 | if (!feature_control_bits) { | |
1337 | return; | |
1338 | } | |
1339 | ||
1340 | val = g_malloc(sizeof(*val)); | |
1341 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); | |
1342 | fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); | |
1343 | } | |
1344 | ||
e3cadac0 IM |
1345 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
1346 | { | |
1347 | if (cpus_count > 0xff) { | |
1348 | /* If the number of CPUs can't be represented in 8 bits, the | |
1349 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1350 | * to make old BIOSes fail more predictably. | |
1351 | */ | |
1352 | rtc_set_memory(rtc, 0x5f, 0); | |
1353 | } else { | |
1354 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1355 | } | |
1356 | } | |
1357 | ||
3459a625 | 1358 | static |
9ebeed0c | 1359 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1360 | { |
9ebeed0c EH |
1361 | PCMachineState *pcms = container_of(notifier, |
1362 | PCMachineState, machine_done); | |
1363 | PCIBus *bus = pcms->bus; | |
2118196b | 1364 | |
ba157b69 | 1365 | /* set the number of CPUs */ |
e3cadac0 | 1366 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); |
ba157b69 | 1367 | |
2118196b MA |
1368 | if (bus) { |
1369 | int extra_hosts = 0; | |
1370 | ||
1371 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1372 | /* look for expander root buses */ | |
1373 | if (pci_bus_is_root(bus)) { | |
1374 | extra_hosts++; | |
1375 | } | |
1376 | } | |
f264d360 | 1377 | if (extra_hosts && pcms->fw_cfg) { |
2118196b MA |
1378 | uint64_t *val = g_malloc(sizeof(*val)); |
1379 | *val = cpu_to_le64(extra_hosts); | |
f264d360 | 1380 | fw_cfg_add_file(pcms->fw_cfg, |
2118196b MA |
1381 | "etc/extra-pci-roots", val, sizeof(*val)); |
1382 | } | |
1383 | } | |
1384 | ||
bb292f5a | 1385 | acpi_setup(); |
6d42eefa | 1386 | if (pcms->fw_cfg) { |
f2098f48 | 1387 | pc_build_smbios(pcms); |
217f1b4a | 1388 | pc_build_feature_control_file(pcms); |
e3cadac0 IM |
1389 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
1390 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
6d42eefa | 1391 | } |
60c5e104 | 1392 | |
1a26f466 | 1393 | if (pcms->apic_id_limit > 255 && !xen_enabled()) { |
60c5e104 IM |
1394 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); |
1395 | ||
a924b3d8 | 1396 | if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || |
60c5e104 IM |
1397 | iommu->intr_eim != ON_OFF_AUTO_ON) { |
1398 | error_report("current -smp configuration requires " | |
1399 | "Extended Interrupt Mode enabled. " | |
1400 | "You can add an IOMMU using: " | |
1401 | "-device intel-iommu,intremap=on,eim=on"); | |
1402 | exit(EXIT_FAILURE); | |
1403 | } | |
1404 | } | |
3459a625 MT |
1405 | } |
1406 | ||
e4e8ba04 | 1407 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1408 | { |
1f3aba37 | 1409 | int i; |
b20c9bd5 | 1410 | |
dd4c2f01 EH |
1411 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); |
1412 | pcms->numa_nodes = nb_numa_nodes; | |
1413 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1414 | sizeof *pcms->node_mem); | |
8c85901e | 1415 | for (i = 0; i < nb_numa_nodes; i++) { |
dd4c2f01 | 1416 | pcms->node_mem[i] = numa_info[i].node_mem; |
8c85901e WG |
1417 | } |
1418 | ||
9ebeed0c EH |
1419 | pcms->machine_done.notify = pc_machine_done; |
1420 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1421 | } |
1422 | ||
83d08f26 MT |
1423 | /* setup pci memory address space mapping into system address space */ |
1424 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1425 | MemoryRegion *pci_address_space) | |
39848901 | 1426 | { |
83d08f26 MT |
1427 | /* Set to lower priority than RAM */ |
1428 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1429 | pci_address_space, -1); | |
39848901 IM |
1430 | } |
1431 | ||
f7e4dd6c GH |
1432 | void pc_acpi_init(const char *default_dsdt) |
1433 | { | |
c5a98cf3 | 1434 | char *filename; |
f7e4dd6c GH |
1435 | |
1436 | if (acpi_tables != NULL) { | |
1437 | /* manually set via -acpitable, leave it alone */ | |
1438 | return; | |
1439 | } | |
1440 | ||
1441 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1442 | if (filename == NULL) { | |
2ab4b135 | 1443 | warn_report("failed to find %s", default_dsdt); |
c5a98cf3 | 1444 | } else { |
5bdb59a2 MA |
1445 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, |
1446 | &error_abort); | |
c5a98cf3 | 1447 | Error *err = NULL; |
f7e4dd6c | 1448 | |
5bdb59a2 | 1449 | qemu_opt_set(opts, "file", filename, &error_abort); |
0c764a9d | 1450 | |
1a4b2666 | 1451 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1452 | if (err) { |
88f83f35 | 1453 | warn_reportf_err(err, "failed to load %s: ", filename); |
c5a98cf3 | 1454 | } |
c5a98cf3 | 1455 | g_free(filename); |
f7e4dd6c | 1456 | } |
f7e4dd6c GH |
1457 | } |
1458 | ||
7bc35e0f | 1459 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1460 | { |
1461 | int i; | |
1462 | FWCfgState *fw_cfg; | |
1463 | ||
df1f79fd | 1464 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1465 | |
305ae888 | 1466 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
e3cadac0 | 1467 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
b33a5bbf CL |
1468 | rom_set_fw(fw_cfg); |
1469 | ||
df1f79fd | 1470 | load_linux(pcms, fw_cfg); |
b33a5bbf CL |
1471 | for (i = 0; i < nb_option_roms; i++) { |
1472 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1473 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
b33a5bbf CL |
1474 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1475 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1476 | } | |
f264d360 | 1477 | pcms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1478 | } |
1479 | ||
5934e216 EH |
1480 | void pc_memory_init(PCMachineState *pcms, |
1481 | MemoryRegion *system_memory, | |
1482 | MemoryRegion *rom_memory, | |
1483 | MemoryRegion **ram_memory) | |
80cabfad | 1484 | { |
cbc5b5f3 JJ |
1485 | int linux_boot, i; |
1486 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1487 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1488 | FWCfgState *fw_cfg; |
62b160c0 | 1489 | MachineState *machine = MACHINE(pcms); |
16a9e8a5 | 1490 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
d592d303 | 1491 | |
c8d163bc EH |
1492 | assert(machine->ram_size == pcms->below_4g_mem_size + |
1493 | pcms->above_4g_mem_size); | |
9521d42b PB |
1494 | |
1495 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1496 | |
00cb2a99 | 1497 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1498 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1499 | * with older qemus that used qemu_ram_alloc(). |
1500 | */ | |
7267c094 | 1501 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1502 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1503 | machine->ram_size); | |
ae0a5466 | 1504 | *ram_memory = ram; |
7267c094 | 1505 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1506 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
c8d163bc | 1507 | 0, pcms->below_4g_mem_size); |
00cb2a99 | 1508 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
c8d163bc EH |
1509 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); |
1510 | if (pcms->above_4g_mem_size > 0) { | |
7267c094 | 1511 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1512 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
c8d163bc EH |
1513 | pcms->below_4g_mem_size, |
1514 | pcms->above_4g_mem_size); | |
00cb2a99 AK |
1515 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1516 | ram_above_4g); | |
c8d163bc | 1517 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1518 | } |
82b36dc3 | 1519 | |
bb292f5a | 1520 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1521 | (machine->ram_slots || |
9521d42b | 1522 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1523 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1524 | ||
1525 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1526 | mc->name); | |
1527 | exit(EXIT_FAILURE); | |
1528 | } | |
1529 | ||
b0c14ec4 DH |
1530 | /* always allocate the device memory information */ |
1531 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
1532 | ||
f2ffbe2b | 1533 | /* initialize device memory address space */ |
bb292f5a | 1534 | if (pcmc->has_reserved_memory && |
9521d42b | 1535 | (machine->ram_size < machine->maxram_size)) { |
f2ffbe2b | 1536 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
619d11e4 | 1537 | |
a0cc8856 IM |
1538 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1539 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1540 | machine->ram_slots); | |
1541 | exit(EXIT_FAILURE); | |
1542 | } | |
1543 | ||
f2c38522 PK |
1544 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1545 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1546 | error_report("maximum memory size must by aligned to multiple of " | |
1547 | "%d bytes", TARGET_PAGE_SIZE); | |
1548 | exit(EXIT_FAILURE); | |
1549 | } | |
1550 | ||
b0c14ec4 | 1551 | machine->device_memory->base = |
d471bf3e | 1552 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); |
619d11e4 | 1553 | |
16a9e8a5 | 1554 | if (pcmc->enforce_aligned_dimm) { |
f2ffbe2b | 1555 | /* size device region assuming 1G page max alignment per slot */ |
d471bf3e | 1556 | device_mem_size += (1 * GiB) * machine->ram_slots; |
085f8e88 IM |
1557 | } |
1558 | ||
f2ffbe2b DH |
1559 | if ((machine->device_memory->base + device_mem_size) < |
1560 | device_mem_size) { | |
619d11e4 IM |
1561 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, |
1562 | machine->maxram_size); | |
1563 | exit(EXIT_FAILURE); | |
1564 | } | |
1565 | ||
b0c14ec4 | 1566 | memory_region_init(&machine->device_memory->mr, OBJECT(pcms), |
f2ffbe2b | 1567 | "device-memory", device_mem_size); |
b0c14ec4 DH |
1568 | memory_region_add_subregion(system_memory, machine->device_memory->base, |
1569 | &machine->device_memory->mr); | |
619d11e4 | 1570 | } |
cbc5b5f3 JJ |
1571 | |
1572 | /* Initialize PC system firmware */ | |
5db3f0de | 1573 | pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); |
00cb2a99 | 1574 | |
7267c094 | 1575 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1576 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1577 | &error_fatal); |
208fa0e4 IM |
1578 | if (pcmc->pci_enabled) { |
1579 | memory_region_set_readonly(option_rom_mr, true); | |
1580 | } | |
4463aee6 | 1581 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1582 | PC_ROM_MIN_VGA, |
1583 | option_rom_mr, | |
1584 | 1); | |
f753ff16 | 1585 | |
ebde2465 | 1586 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); |
c886fc4c | 1587 | |
8832cb80 | 1588 | rom_set_fw(fw_cfg); |
1d108d97 | 1589 | |
b0c14ec4 | 1590 | if (pcmc->has_reserved_memory && machine->device_memory->base) { |
de268e13 | 1591 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 | 1592 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
b0c14ec4 | 1593 | uint64_t res_mem_end = machine->device_memory->base; |
2f8b5008 IM |
1594 | |
1595 | if (!pcmc->broken_reserved_end) { | |
b0c14ec4 | 1596 | res_mem_end += memory_region_size(&machine->device_memory->mr); |
2f8b5008 | 1597 | } |
d471bf3e | 1598 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); |
de268e13 IM |
1599 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1600 | } | |
1601 | ||
f753ff16 | 1602 | if (linux_boot) { |
df1f79fd | 1603 | load_linux(pcms, fw_cfg); |
f753ff16 PB |
1604 | } |
1605 | ||
1606 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1607 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1608 | } |
f264d360 | 1609 | pcms->fw_cfg = fw_cfg; |
cb135f59 PX |
1610 | |
1611 | /* Init default IOAPIC address space */ | |
1612 | pcms->ioapic_as = &address_space_memory; | |
3d53f5c3 IY |
1613 | } |
1614 | ||
9fa99d25 MA |
1615 | /* |
1616 | * The 64bit pci hole starts after "above 4G RAM" and | |
1617 | * potentially the space reserved for memory hotplug. | |
1618 | */ | |
1619 | uint64_t pc_pci_hole64_start(void) | |
1620 | { | |
1621 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1622 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
b0c14ec4 | 1623 | MachineState *ms = MACHINE(pcms); |
9fa99d25 MA |
1624 | uint64_t hole64_start = 0; |
1625 | ||
b0c14ec4 DH |
1626 | if (pcmc->has_reserved_memory && ms->device_memory->base) { |
1627 | hole64_start = ms->device_memory->base; | |
9fa99d25 | 1628 | if (!pcmc->broken_reserved_end) { |
b0c14ec4 | 1629 | hole64_start += memory_region_size(&ms->device_memory->mr); |
9fa99d25 MA |
1630 | } |
1631 | } else { | |
1632 | hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; | |
1633 | } | |
1634 | ||
d471bf3e | 1635 | return ROUND_UP(hole64_start, 1 * GiB); |
9fa99d25 MA |
1636 | } |
1637 | ||
0b0cc076 | 1638 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1639 | { |
0b0cc076 | 1640 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1641 | } |
1642 | ||
48a18b3c | 1643 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1644 | { |
ad6d45fa AL |
1645 | DeviceState *dev = NULL; |
1646 | ||
bab47d9a | 1647 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1648 | if (pci_bus) { |
1649 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1650 | dev = pcidev ? &pcidev->qdev : NULL; | |
1651 | } else if (isa_bus) { | |
1652 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1653 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1654 | } |
bab47d9a | 1655 | rom_reset_order_override(); |
ad6d45fa | 1656 | return dev; |
765d7908 IY |
1657 | } |
1658 | ||
258711c6 JG |
1659 | static const MemoryRegionOps ioport80_io_ops = { |
1660 | .write = ioport80_write, | |
c02e1eac | 1661 | .read = ioport80_read, |
258711c6 JG |
1662 | .endianness = DEVICE_NATIVE_ENDIAN, |
1663 | .impl = { | |
1664 | .min_access_size = 1, | |
1665 | .max_access_size = 1, | |
1666 | }, | |
1667 | }; | |
1668 | ||
1669 | static const MemoryRegionOps ioportF0_io_ops = { | |
1670 | .write = ioportF0_write, | |
c02e1eac | 1671 | .read = ioportF0_read, |
258711c6 JG |
1672 | .endianness = DEVICE_NATIVE_ENDIAN, |
1673 | .impl = { | |
1674 | .min_access_size = 1, | |
1675 | .max_access_size = 1, | |
1676 | }, | |
1677 | }; | |
1678 | ||
ac64273c PMD |
1679 | static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) |
1680 | { | |
1681 | int i; | |
1682 | DriveInfo *fd[MAX_FD]; | |
1683 | qemu_irq *a20_line; | |
1684 | ISADevice *i8042, *port92, *vmmouse; | |
1685 | ||
def337ff | 1686 | serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); |
ac64273c PMD |
1687 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
1688 | ||
1689 | for (i = 0; i < MAX_FD; i++) { | |
1690 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
1691 | create_fdctrl |= !!fd[i]; | |
1692 | } | |
1693 | if (create_fdctrl) { | |
1694 | fdctrl_init_isa(isa_bus, fd); | |
1695 | } | |
1696 | ||
1697 | i8042 = isa_create_simple(isa_bus, "i8042"); | |
1698 | if (!no_vmport) { | |
1699 | vmport_init(isa_bus); | |
1700 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1701 | } else { | |
1702 | vmmouse = NULL; | |
1703 | } | |
1704 | if (vmmouse) { | |
1705 | DeviceState *dev = DEVICE(vmmouse); | |
1706 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1707 | qdev_init_nofail(dev); | |
1708 | } | |
1709 | port92 = isa_create_simple(isa_bus, "port92"); | |
1710 | ||
1711 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); | |
1712 | i8042_setup_a20_line(i8042, a20_line[0]); | |
1713 | port92_init(port92, a20_line[1]); | |
1714 | g_free(a20_line); | |
1715 | } | |
1716 | ||
48a18b3c | 1717 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1718 | ISADevice **rtc_state, |
fd53c87c | 1719 | bool create_fdctrl, |
7a10ef51 | 1720 | bool no_vmport, |
feddd2fd | 1721 | bool has_pit, |
3a87d009 | 1722 | uint32_t hpet_irqs) |
ffe513da IY |
1723 | { |
1724 | int i; | |
ce967e2f JK |
1725 | DeviceState *hpet = NULL; |
1726 | int pit_isa_irq = 0; | |
1727 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1728 | qemu_irq rtc_irq = NULL; |
ac64273c | 1729 | ISADevice *pit = NULL; |
258711c6 JG |
1730 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1731 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1732 | |
2c9b15ca | 1733 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1734 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1735 | |
2c9b15ca | 1736 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1737 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1738 | |
5d17c0d2 JK |
1739 | /* |
1740 | * Check if an HPET shall be created. | |
1741 | * | |
1742 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1743 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1744 | */ | |
1745 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1746 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1747 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1748 | if (hpet) { |
7a10ef51 LPF |
1749 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1750 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1751 | * IRQ8 and IRQ2. | |
1752 | */ | |
5d7fb0f2 | 1753 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
7a10ef51 LPF |
1754 | HPET_INTCAP, NULL); |
1755 | if (!compat) { | |
1756 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1757 | } | |
1758 | qdev_init_nofail(hpet); | |
1759 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1760 | ||
b881fbe9 | 1761 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1762 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1763 | } |
ce967e2f JK |
1764 | pit_isa_irq = -1; |
1765 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1766 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1767 | } |
ffe513da | 1768 | } |
6c646a11 | 1769 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1770 | |
1771 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1772 | ||
feddd2fd | 1773 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1774 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1775 | pit = kvm_pit_init(isa_bus, 0x40); |
1776 | } else { | |
acf695ec | 1777 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1778 | } |
1779 | if (hpet) { | |
1780 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1781 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1782 | } |
1783 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1784 | } |
ffe513da | 1785 | |
55f613ac | 1786 | i8257_dma_init(isa_bus, 0); |
ffe513da | 1787 | |
ac64273c PMD |
1788 | /* Super I/O */ |
1789 | pc_superio_init(isa_bus, create_fdctrl, no_vmport); | |
ffe513da IY |
1790 | } |
1791 | ||
4b9c264b | 1792 | void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) |
9011a1a7 IY |
1793 | { |
1794 | int i; | |
1795 | ||
bab47d9a | 1796 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1797 | for (i = 0; i < nb_nics; i++) { |
1798 | NICInfo *nd = &nd_table[i]; | |
4b9c264b | 1799 | const char *model = nd->model ? nd->model : pcmc->default_nic_model; |
9011a1a7 | 1800 | |
4b9c264b | 1801 | if (g_str_equal(model, "ne2k_isa")) { |
9011a1a7 IY |
1802 | pc_init_ne2k_isa(isa_bus, nd); |
1803 | } else { | |
4b9c264b | 1804 | pci_nic_init_nofail(nd, pci_bus, model, NULL); |
9011a1a7 IY |
1805 | } |
1806 | } | |
bab47d9a | 1807 | rom_reset_order_override(); |
9011a1a7 IY |
1808 | } |
1809 | ||
a39e3564 JB |
1810 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) |
1811 | { | |
1812 | DeviceState *dev; | |
1813 | SysBusDevice *d; | |
1814 | unsigned int i; | |
1815 | ||
15eafc2e | 1816 | if (kvm_ioapic_in_kernel()) { |
a39e3564 JB |
1817 | dev = qdev_create(NULL, "kvm-ioapic"); |
1818 | } else { | |
1819 | dev = qdev_create(NULL, "ioapic"); | |
1820 | } | |
1821 | if (parent_name) { | |
1822 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1823 | "ioapic", OBJECT(dev), NULL); | |
1824 | } | |
1825 | qdev_init_nofail(dev); | |
1356b98d | 1826 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1827 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1828 | |
1829 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1830 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1831 | } | |
1832 | } | |
d5747cac | 1833 | |
d468115b DH |
1834 | static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
1835 | Error **errp) | |
1836 | { | |
1837 | const PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
b0e62443 | 1838 | const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
d468115b | 1839 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
b0e62443 | 1840 | const uint64_t legacy_align = TARGET_PAGE_SIZE; |
d468115b DH |
1841 | |
1842 | /* | |
1843 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1844 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1845 | * addition to cover this case. | |
1846 | */ | |
1847 | if (!pcms->acpi_dev || !acpi_enabled) { | |
1848 | error_setg(errp, | |
1849 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); | |
1850 | return; | |
1851 | } | |
1852 | ||
1853 | if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) { | |
1854 | error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); | |
1855 | return; | |
1856 | } | |
8f1ffe5b | 1857 | |
fd3416f5 | 1858 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), |
b0e62443 | 1859 | pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); |
d468115b DH |
1860 | } |
1861 | ||
bb6e2f7a DH |
1862 | static void pc_memory_plug(HotplugHandler *hotplug_dev, |
1863 | DeviceState *dev, Error **errp) | |
95bee274 | 1864 | { |
3fbcdc27 | 1865 | HotplugHandlerClass *hhc; |
95bee274 IM |
1866 | Error *local_err = NULL; |
1867 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
7f3cf2d6 | 1868 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1869 | |
fd3416f5 | 1870 | pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); |
43bbb49e | 1871 | if (local_err) { |
b8865591 IM |
1872 | goto out; |
1873 | } | |
1874 | ||
7f3cf2d6 | 1875 | if (is_nvdimm) { |
284197e4 | 1876 | nvdimm_plug(&pcms->acpi_nvdimm_state); |
c7f8d0f3 XG |
1877 | } |
1878 | ||
3fbcdc27 | 1879 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
8e23184b | 1880 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1881 | out: |
1882 | error_propagate(errp, local_err); | |
1883 | } | |
1884 | ||
bb6e2f7a DH |
1885 | static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, |
1886 | DeviceState *dev, Error **errp) | |
64fec58e TC |
1887 | { |
1888 | HotplugHandlerClass *hhc; | |
1889 | Error *local_err = NULL; | |
1890 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1891 | ||
8cd91ace HZ |
1892 | /* |
1893 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1894 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1895 | * addition to cover this case. | |
1896 | */ | |
1897 | if (!pcms->acpi_dev || !acpi_enabled) { | |
64fec58e | 1898 | error_setg(&local_err, |
8cd91ace | 1899 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
64fec58e TC |
1900 | goto out; |
1901 | } | |
1902 | ||
b097cc52 XG |
1903 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1904 | error_setg(&local_err, | |
1905 | "nvdimm device hot unplug is not supported yet."); | |
1906 | goto out; | |
1907 | } | |
1908 | ||
64fec58e TC |
1909 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1910 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1911 | ||
1912 | out: | |
1913 | error_propagate(errp, local_err); | |
1914 | } | |
1915 | ||
bb6e2f7a DH |
1916 | static void pc_memory_unplug(HotplugHandler *hotplug_dev, |
1917 | DeviceState *dev, Error **errp) | |
f7d3e29d TC |
1918 | { |
1919 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
f7d3e29d TC |
1920 | HotplugHandlerClass *hhc; |
1921 | Error *local_err = NULL; | |
1922 | ||
1923 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1924 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1925 | ||
1926 | if (local_err) { | |
1927 | goto out; | |
1928 | } | |
1929 | ||
fd3416f5 | 1930 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); |
f7d3e29d TC |
1931 | object_unparent(OBJECT(dev)); |
1932 | ||
1933 | out: | |
1934 | error_propagate(errp, local_err); | |
1935 | } | |
1936 | ||
3811ef14 IM |
1937 | static int pc_apic_cmp(const void *a, const void *b) |
1938 | { | |
1939 | CPUArchId *apic_a = (CPUArchId *)a; | |
1940 | CPUArchId *apic_b = (CPUArchId *)b; | |
1941 | ||
1942 | return apic_a->arch_id - apic_b->arch_id; | |
1943 | } | |
1944 | ||
7baef5cf | 1945 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1946 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1947 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1948 | */ |
1ea69c0e | 1949 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1950 | { |
7baef5cf IM |
1951 | CPUArchId apic_id, *found_cpu; |
1952 | ||
1ea69c0e | 1953 | apic_id.arch_id = id; |
38690a1c IM |
1954 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1955 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1956 | pc_apic_cmp); |
1957 | if (found_cpu && idx) { | |
38690a1c | 1958 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1959 | } |
1960 | return found_cpu; | |
1961 | } | |
1962 | ||
5279569e GZ |
1963 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1964 | DeviceState *dev, Error **errp) | |
1965 | { | |
7baef5cf | 1966 | CPUArchId *found_cpu; |
5279569e GZ |
1967 | HotplugHandlerClass *hhc; |
1968 | Error *local_err = NULL; | |
1ea69c0e | 1969 | X86CPU *cpu = X86_CPU(dev); |
5279569e GZ |
1970 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1971 | ||
a44a49db IM |
1972 | if (pcms->acpi_dev) { |
1973 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1974 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1975 | if (local_err) { | |
1976 | goto out; | |
1977 | } | |
5279569e GZ |
1978 | } |
1979 | ||
e3cadac0 IM |
1980 | /* increment the number of CPUs */ |
1981 | pcms->boot_cpus++; | |
26ef65be | 1982 | if (pcms->rtc) { |
e3cadac0 | 1983 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); |
26ef65be IM |
1984 | } |
1985 | if (pcms->fw_cfg) { | |
e3cadac0 | 1986 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
2d996150 GZ |
1987 | } |
1988 | ||
1ea69c0e | 1989 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1990 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1991 | out: |
1992 | error_propagate(errp, local_err); | |
1993 | } | |
8872c25a IM |
1994 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1995 | DeviceState *dev, Error **errp) | |
1996 | { | |
73360e27 | 1997 | int idx = -1; |
8872c25a IM |
1998 | HotplugHandlerClass *hhc; |
1999 | Error *local_err = NULL; | |
1ea69c0e | 2000 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
2001 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
2002 | ||
75ba2ddb IM |
2003 | if (!pcms->acpi_dev) { |
2004 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
2005 | goto out; | |
2006 | } | |
2007 | ||
1ea69c0e | 2008 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
2009 | assert(idx != -1); |
2010 | if (idx == 0) { | |
2011 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
2012 | goto out; | |
2013 | } | |
2014 | ||
8872c25a IM |
2015 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
2016 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2017 | ||
2018 | if (local_err) { | |
2019 | goto out; | |
2020 | } | |
2021 | ||
2022 | out: | |
2023 | error_propagate(errp, local_err); | |
2024 | ||
2025 | } | |
2026 | ||
2027 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
2028 | DeviceState *dev, Error **errp) | |
2029 | { | |
8fe6374e | 2030 | CPUArchId *found_cpu; |
8872c25a IM |
2031 | HotplugHandlerClass *hhc; |
2032 | Error *local_err = NULL; | |
1ea69c0e | 2033 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
2034 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
2035 | ||
2036 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
2037 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
2038 | ||
2039 | if (local_err) { | |
2040 | goto out; | |
2041 | } | |
2042 | ||
1ea69c0e | 2043 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e IM |
2044 | found_cpu->cpu = NULL; |
2045 | object_unparent(OBJECT(dev)); | |
8872c25a | 2046 | |
e3cadac0 IM |
2047 | /* decrement the number of CPUs */ |
2048 | pcms->boot_cpus--; | |
2049 | /* Update the number of CPUs in CMOS */ | |
2050 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
2051 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
8872c25a IM |
2052 | out: |
2053 | error_propagate(errp, local_err); | |
2054 | } | |
5279569e | 2055 | |
4ec60c76 IM |
2056 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
2057 | DeviceState *dev, Error **errp) | |
2058 | { | |
2059 | int idx; | |
a15d2728 | 2060 | CPUState *cs; |
e8f7b83e | 2061 | CPUArchId *cpu_slot; |
d89c2b8b | 2062 | X86CPUTopoInfo topo; |
4ec60c76 | 2063 | X86CPU *cpu = X86_CPU(dev); |
6970c5ff | 2064 | MachineState *ms = MACHINE(hotplug_dev); |
4ec60c76 | 2065 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
4ec60c76 | 2066 | |
6970c5ff IM |
2067 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { |
2068 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
2069 | ms->cpu_type); | |
2070 | return; | |
2071 | } | |
2072 | ||
e8f7b83e IM |
2073 | /* if APIC ID is not set, set it based on socket/core/thread properties */ |
2074 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
2075 | int max_socket = (max_cpus - 1) / smp_threads / smp_cores; | |
2076 | ||
2077 | if (cpu->socket_id < 0) { | |
2078 | error_setg(errp, "CPU socket-id is not set"); | |
2079 | return; | |
2080 | } else if (cpu->socket_id > max_socket) { | |
2081 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
2082 | cpu->socket_id, max_socket); | |
2083 | return; | |
2084 | } | |
2085 | if (cpu->core_id < 0) { | |
2086 | error_setg(errp, "CPU core-id is not set"); | |
2087 | return; | |
2088 | } else if (cpu->core_id > (smp_cores - 1)) { | |
2089 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
2090 | cpu->core_id, smp_cores - 1); | |
2091 | return; | |
2092 | } | |
2093 | if (cpu->thread_id < 0) { | |
2094 | error_setg(errp, "CPU thread-id is not set"); | |
2095 | return; | |
2096 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
2097 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
2098 | cpu->thread_id, smp_threads - 1); | |
2099 | return; | |
2100 | } | |
2101 | ||
2102 | topo.pkg_id = cpu->socket_id; | |
2103 | topo.core_id = cpu->core_id; | |
2104 | topo.smt_id = cpu->thread_id; | |
2105 | cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); | |
2106 | } | |
2107 | ||
1ea69c0e | 2108 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 2109 | if (!cpu_slot) { |
38690a1c IM |
2110 | MachineState *ms = MACHINE(pcms); |
2111 | ||
e8f7b83e IM |
2112 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); |
2113 | error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" | |
2114 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
2115 | topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, | |
38690a1c | 2116 | ms->possible_cpus->len - 1); |
4ec60c76 IM |
2117 | return; |
2118 | } | |
2119 | ||
2120 | if (cpu_slot->cpu) { | |
2121 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
2122 | idx, cpu->apic_id); | |
2123 | return; | |
2124 | } | |
d89c2b8b IM |
2125 | |
2126 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 2127 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
2128 | */ |
2129 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
2130 | * once -smp refactoring is complete and there will be CPU private | |
2131 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
2132 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
2133 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
2134 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
2135 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
2136 | return; | |
2137 | } | |
2138 | cpu->socket_id = topo.pkg_id; | |
2139 | ||
2140 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
2141 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
2142 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
2143 | return; | |
2144 | } | |
2145 | cpu->core_id = topo.core_id; | |
2146 | ||
2147 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
2148 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
2149 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
2150 | return; | |
2151 | } | |
2152 | cpu->thread_id = topo.smt_id; | |
a15d2728 | 2153 | |
e9688fab RK |
2154 | if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) { |
2155 | error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); | |
2156 | return; | |
2157 | } | |
2158 | ||
a15d2728 IM |
2159 | cs = CPU(cpu); |
2160 | cs->cpu_index = idx; | |
93b2a8cb | 2161 | |
a0ceb640 | 2162 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
4ec60c76 IM |
2163 | } |
2164 | ||
2165 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
2166 | DeviceState *dev, Error **errp) | |
2167 | { | |
d468115b DH |
2168 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2169 | pc_memory_pre_plug(hotplug_dev, dev, errp); | |
2170 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
4ec60c76 IM |
2171 | pc_cpu_pre_plug(hotplug_dev, dev, errp); |
2172 | } | |
2173 | } | |
2174 | ||
95bee274 IM |
2175 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
2176 | DeviceState *dev, Error **errp) | |
2177 | { | |
2178 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
bb6e2f7a | 2179 | pc_memory_plug(hotplug_dev, dev, errp); |
5279569e GZ |
2180 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2181 | pc_cpu_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
2182 | } |
2183 | } | |
2184 | ||
d9c5c5b8 TC |
2185 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
2186 | DeviceState *dev, Error **errp) | |
2187 | { | |
64fec58e | 2188 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 2189 | pc_memory_unplug_request(hotplug_dev, dev, errp); |
8872c25a IM |
2190 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2191 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
64fec58e TC |
2192 | } else { |
2193 | error_setg(errp, "acpi: device unplug request for not supported device" | |
2194 | " type: %s", object_get_typename(OBJECT(dev))); | |
2195 | } | |
d9c5c5b8 TC |
2196 | } |
2197 | ||
232391c1 TC |
2198 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
2199 | DeviceState *dev, Error **errp) | |
2200 | { | |
f7d3e29d | 2201 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
bb6e2f7a | 2202 | pc_memory_unplug(hotplug_dev, dev, errp); |
8872c25a IM |
2203 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2204 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
f7d3e29d TC |
2205 | } else { |
2206 | error_setg(errp, "acpi: device unplug for not supported device" | |
2207 | " type: %s", object_get_typename(OBJECT(dev))); | |
2208 | } | |
232391c1 TC |
2209 | } |
2210 | ||
95bee274 IM |
2211 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, |
2212 | DeviceState *dev) | |
2213 | { | |
5279569e GZ |
2214 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2215 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
95bee274 IM |
2216 | return HOTPLUG_HANDLER(machine); |
2217 | } | |
2218 | ||
38aefb57 | 2219 | return NULL; |
95bee274 IM |
2220 | } |
2221 | ||
bf1e8939 | 2222 | static void |
f2ffbe2b DH |
2223 | pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, |
2224 | const char *name, void *opaque, | |
2225 | Error **errp) | |
bf1e8939 | 2226 | { |
b0c14ec4 DH |
2227 | MachineState *ms = MACHINE(obj); |
2228 | int64_t value = memory_region_size(&ms->device_memory->mr); | |
bf1e8939 | 2229 | |
51e72bc1 | 2230 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2231 | } |
2232 | ||
c87b1520 | 2233 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
d7bce999 EB |
2234 | const char *name, void *opaque, |
2235 | Error **errp) | |
c87b1520 DS |
2236 | { |
2237 | PCMachineState *pcms = PC_MACHINE(obj); | |
2238 | uint64_t value = pcms->max_ram_below_4g; | |
2239 | ||
51e72bc1 | 2240 | visit_type_size(v, name, &value, errp); |
c87b1520 DS |
2241 | } |
2242 | ||
2243 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
d7bce999 EB |
2244 | const char *name, void *opaque, |
2245 | Error **errp) | |
c87b1520 DS |
2246 | { |
2247 | PCMachineState *pcms = PC_MACHINE(obj); | |
2248 | Error *error = NULL; | |
2249 | uint64_t value; | |
2250 | ||
51e72bc1 | 2251 | visit_type_size(v, name, &value, &error); |
c87b1520 DS |
2252 | if (error) { |
2253 | error_propagate(errp, error); | |
2254 | return; | |
2255 | } | |
d471bf3e | 2256 | if (value > 4 * GiB) { |
455b0fde EB |
2257 | error_setg(&error, |
2258 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2259 | "' expects size less than or equal to 4G", value); | |
c87b1520 DS |
2260 | error_propagate(errp, error); |
2261 | return; | |
2262 | } | |
2263 | ||
d471bf3e | 2264 | if (value < 1 * MiB) { |
9e5d2c52 AF |
2265 | warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," |
2266 | "BIOS may not work with less than 1MiB", value); | |
c87b1520 DS |
2267 | } |
2268 | ||
2269 | pcms->max_ram_below_4g = value; | |
2270 | } | |
2271 | ||
d7bce999 EB |
2272 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2273 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2274 | { |
2275 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2276 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2277 | |
51e72bc1 | 2278 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2279 | } |
2280 | ||
d7bce999 EB |
2281 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2282 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2283 | { |
2284 | PCMachineState *pcms = PC_MACHINE(obj); | |
2285 | ||
51e72bc1 | 2286 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2287 | } |
2288 | ||
355023f2 PB |
2289 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) |
2290 | { | |
2291 | bool smm_available = false; | |
2292 | ||
2293 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2294 | return false; | |
2295 | } | |
2296 | ||
2297 | if (tcg_enabled() || qtest_enabled()) { | |
2298 | smm_available = true; | |
2299 | } else if (kvm_enabled()) { | |
2300 | smm_available = kvm_has_smm(); | |
2301 | } | |
2302 | ||
2303 | if (smm_available) { | |
2304 | return true; | |
2305 | } | |
2306 | ||
2307 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2308 | error_report("System Management Mode not supported by this hypervisor."); | |
2309 | exit(1); | |
2310 | } | |
2311 | return false; | |
2312 | } | |
2313 | ||
d7bce999 EB |
2314 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, |
2315 | void *opaque, Error **errp) | |
355023f2 PB |
2316 | { |
2317 | PCMachineState *pcms = PC_MACHINE(obj); | |
2318 | OnOffAuto smm = pcms->smm; | |
2319 | ||
51e72bc1 | 2320 | visit_type_OnOffAuto(v, name, &smm, errp); |
355023f2 PB |
2321 | } |
2322 | ||
d7bce999 EB |
2323 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, |
2324 | void *opaque, Error **errp) | |
355023f2 PB |
2325 | { |
2326 | PCMachineState *pcms = PC_MACHINE(obj); | |
2327 | ||
51e72bc1 | 2328 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); |
355023f2 PB |
2329 | } |
2330 | ||
87252e1b XG |
2331 | static bool pc_machine_get_nvdimm(Object *obj, Error **errp) |
2332 | { | |
2333 | PCMachineState *pcms = PC_MACHINE(obj); | |
2334 | ||
5fe79386 | 2335 | return pcms->acpi_nvdimm_state.is_enabled; |
87252e1b XG |
2336 | } |
2337 | ||
2338 | static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
2339 | { | |
2340 | PCMachineState *pcms = PC_MACHINE(obj); | |
2341 | ||
5fe79386 | 2342 | pcms->acpi_nvdimm_state.is_enabled = value; |
87252e1b XG |
2343 | } |
2344 | ||
11c39b5c | 2345 | static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp) |
9ab3aad2 RZ |
2346 | { |
2347 | PCMachineState *pcms = PC_MACHINE(obj); | |
9ab3aad2 | 2348 | |
11c39b5c | 2349 | return g_strdup(pcms->acpi_nvdimm_state.persistence_string); |
9ab3aad2 RZ |
2350 | } |
2351 | ||
11c39b5c | 2352 | static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value, |
9ab3aad2 RZ |
2353 | Error **errp) |
2354 | { | |
2355 | PCMachineState *pcms = PC_MACHINE(obj); | |
11c39b5c RZ |
2356 | AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state; |
2357 | ||
2358 | if (strcmp(value, "cpu") == 0) | |
2359 | nvdimm_state->persistence = 3; | |
2360 | else if (strcmp(value, "mem-ctrl") == 0) | |
2361 | nvdimm_state->persistence = 2; | |
2362 | else { | |
d319e05d MA |
2363 | error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", |
2364 | value); | |
2365 | return; | |
9ab3aad2 RZ |
2366 | } |
2367 | ||
11c39b5c RZ |
2368 | g_free(nvdimm_state->persistence_string); |
2369 | nvdimm_state->persistence_string = g_strdup(value); | |
9ab3aad2 RZ |
2370 | } |
2371 | ||
be232eb0 CP |
2372 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
2373 | { | |
2374 | PCMachineState *pcms = PC_MACHINE(obj); | |
2375 | ||
f5878b03 | 2376 | return pcms->smbus_enabled; |
be232eb0 CP |
2377 | } |
2378 | ||
2379 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2380 | { | |
2381 | PCMachineState *pcms = PC_MACHINE(obj); | |
2382 | ||
f5878b03 | 2383 | pcms->smbus_enabled = value; |
be232eb0 CP |
2384 | } |
2385 | ||
272f0428 CP |
2386 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
2387 | { | |
2388 | PCMachineState *pcms = PC_MACHINE(obj); | |
2389 | ||
f5878b03 | 2390 | return pcms->sata_enabled; |
272f0428 CP |
2391 | } |
2392 | ||
2393 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2394 | { | |
2395 | PCMachineState *pcms = PC_MACHINE(obj); | |
2396 | ||
f5878b03 | 2397 | pcms->sata_enabled = value; |
272f0428 CP |
2398 | } |
2399 | ||
feddd2fd CP |
2400 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
2401 | { | |
2402 | PCMachineState *pcms = PC_MACHINE(obj); | |
2403 | ||
f5878b03 | 2404 | return pcms->pit_enabled; |
feddd2fd CP |
2405 | } |
2406 | ||
2407 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2408 | { | |
2409 | PCMachineState *pcms = PC_MACHINE(obj); | |
2410 | ||
f5878b03 | 2411 | pcms->pit_enabled = value; |
feddd2fd CP |
2412 | } |
2413 | ||
bf1e8939 IM |
2414 | static void pc_machine_initfn(Object *obj) |
2415 | { | |
c87b1520 DS |
2416 | PCMachineState *pcms = PC_MACHINE(obj); |
2417 | ||
5ec7d098 | 2418 | pcms->max_ram_below_4g = 0; /* use default */ |
355023f2 | 2419 | pcms->smm = ON_OFF_AUTO_AUTO; |
d1048bef | 2420 | pcms->vmport = ON_OFF_AUTO_AUTO; |
87252e1b | 2421 | /* nvdimm is disabled on default. */ |
5fe79386 | 2422 | pcms->acpi_nvdimm_state.is_enabled = false; |
021746c1 WL |
2423 | /* acpi build is enabled by default if machine supports it */ |
2424 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
f5878b03 CM |
2425 | pcms->smbus_enabled = true; |
2426 | pcms->sata_enabled = true; | |
2427 | pcms->pit_enabled = true; | |
bf1e8939 IM |
2428 | } |
2429 | ||
ae50c55a ZG |
2430 | static void pc_machine_reset(void) |
2431 | { | |
2432 | CPUState *cs; | |
2433 | X86CPU *cpu; | |
2434 | ||
2435 | qemu_devices_reset(); | |
2436 | ||
2437 | /* Reset APIC after devices have been reset to cancel | |
2438 | * any changes that qemu_devices_reset() might have done. | |
2439 | */ | |
2440 | CPU_FOREACH(cs) { | |
2441 | cpu = X86_CPU(cs); | |
2442 | ||
2443 | if (cpu->apic_state) { | |
2444 | device_reset(cpu->apic_state); | |
2445 | } | |
2446 | } | |
2447 | } | |
2448 | ||
ea089eeb IM |
2449 | static CpuInstanceProperties |
2450 | pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
fb43b73b | 2451 | { |
ea089eeb IM |
2452 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
2453 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
2454 | ||
2455 | assert(cpu_index < possible_cpus->len); | |
2456 | return possible_cpus->cpus[cpu_index].props; | |
fb43b73b IM |
2457 | } |
2458 | ||
79e07936 IM |
2459 | static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) |
2460 | { | |
2461 | X86CPUTopoInfo topo; | |
2462 | ||
2463 | assert(idx < ms->possible_cpus->len); | |
2464 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, | |
2465 | smp_cores, smp_threads, &topo); | |
2466 | return topo.pkg_id % nb_numa_nodes; | |
2467 | } | |
2468 | ||
c96a1c0b | 2469 | static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) |
3811ef14 | 2470 | { |
c96a1c0b IM |
2471 | int i; |
2472 | ||
2473 | if (ms->possible_cpus) { | |
2474 | /* | |
2475 | * make sure that max_cpus hasn't changed since the first use, i.e. | |
2476 | * -smp hasn't been parsed after it | |
2477 | */ | |
2478 | assert(ms->possible_cpus->len == max_cpus); | |
2479 | return ms->possible_cpus; | |
2480 | } | |
2481 | ||
2482 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
2483 | sizeof(CPUArchId) * max_cpus); | |
2484 | ms->possible_cpus->len = max_cpus; | |
2485 | for (i = 0; i < ms->possible_cpus->len; i++) { | |
c67ae933 IM |
2486 | X86CPUTopoInfo topo; |
2487 | ||
d342eb76 | 2488 | ms->possible_cpus->cpus[i].type = ms->cpu_type; |
f2d672c2 | 2489 | ms->possible_cpus->cpus[i].vcpus_count = 1; |
c96a1c0b | 2490 | ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); |
c67ae933 IM |
2491 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, |
2492 | smp_cores, smp_threads, &topo); | |
2493 | ms->possible_cpus->cpus[i].props.has_socket_id = true; | |
2494 | ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; | |
2495 | ms->possible_cpus->cpus[i].props.has_core_id = true; | |
2496 | ms->possible_cpus->cpus[i].props.core_id = topo.core_id; | |
2497 | ms->possible_cpus->cpus[i].props.has_thread_id = true; | |
2498 | ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; | |
c96a1c0b IM |
2499 | } |
2500 | return ms->possible_cpus; | |
3811ef14 IM |
2501 | } |
2502 | ||
1255166b BD |
2503 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) |
2504 | { | |
2505 | /* cpu index isn't used */ | |
2506 | CPUState *cs; | |
2507 | ||
2508 | CPU_FOREACH(cs) { | |
2509 | X86CPU *cpu = X86_CPU(cs); | |
2510 | ||
2511 | if (!cpu->apic_state) { | |
2512 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2513 | } else { | |
2514 | apic_deliver_nmi(cpu->apic_state); | |
2515 | } | |
2516 | } | |
2517 | } | |
2518 | ||
95bee274 IM |
2519 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2520 | { | |
2521 | MachineClass *mc = MACHINE_CLASS(oc); | |
2522 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2523 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1255166b | 2524 | NMIClass *nc = NMI_CLASS(oc); |
95bee274 | 2525 | |
7102fa70 EH |
2526 | pcmc->pci_enabled = true; |
2527 | pcmc->has_acpi_build = true; | |
2528 | pcmc->rsdp_in_ram = true; | |
2529 | pcmc->smbios_defaults = true; | |
2530 | pcmc->smbios_uuid_encoded = true; | |
2531 | pcmc->gigabyte_align = true; | |
2532 | pcmc->has_reserved_memory = true; | |
2533 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2534 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2535 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2536 | * to be used at the moment, 32K should be enough for a while. */ | |
2537 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
36f96c4b | 2538 | pcmc->save_tsc_khz = true; |
98e753a6 | 2539 | pcmc->linuxboot_dma_enabled = true; |
debbdc00 | 2540 | assert(!mc->get_hotplug_handler); |
95bee274 | 2541 | mc->get_hotplug_handler = pc_get_hotpug_handler; |
ea089eeb | 2542 | mc->cpu_index_to_instance_props = pc_cpu_index_to_props; |
79e07936 | 2543 | mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; |
3811ef14 | 2544 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; |
7b8be49d | 2545 | mc->auto_enable_numa_with_memhp = true; |
c5514d0e | 2546 | mc->has_hotpluggable_cpus = true; |
41742767 | 2547 | mc->default_boot_order = "cad"; |
4458fb3a | 2548 | mc->hot_add_cpu = pc_hot_add_cpu; |
2059839b | 2549 | mc->block_default_type = IF_IDE; |
4458fb3a | 2550 | mc->max_cpus = 255; |
ae50c55a | 2551 | mc->reset = pc_machine_reset; |
4ec60c76 | 2552 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2553 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2554 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2555 | hc->unplug = pc_machine_device_unplug_cb; |
1255166b | 2556 | nc->nmi_monitor_handler = x86_nmi; |
311ca98d | 2557 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
0efc257d | 2558 | |
f2ffbe2b DH |
2559 | object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", |
2560 | pc_machine_get_device_memory_region_size, NULL, | |
0efc257d EH |
2561 | NULL, NULL, &error_abort); |
2562 | ||
2563 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2564 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
2565 | NULL, NULL, &error_abort); | |
2566 | ||
2567 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2568 | "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); | |
2569 | ||
2570 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", | |
2571 | pc_machine_get_smm, pc_machine_set_smm, | |
2572 | NULL, NULL, &error_abort); | |
2573 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2574 | "Enable SMM (pc & q35)", &error_abort); | |
2575 | ||
2576 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2577 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2578 | NULL, NULL, &error_abort); | |
2579 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2580 | "Enable vmport (pc & q35)", &error_abort); | |
2581 | ||
2582 | object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, | |
2583 | pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); | |
be232eb0 | 2584 | |
11c39b5c RZ |
2585 | object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST, |
2586 | pc_machine_get_nvdimm_persistence, | |
2587 | pc_machine_set_nvdimm_persistence, &error_abort); | |
9ab3aad2 | 2588 | |
be232eb0 CP |
2589 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, |
2590 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
2591 | |
2592 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2593 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
2594 | |
2595 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2596 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
2597 | } |
2598 | ||
d5747cac IM |
2599 | static const TypeInfo pc_machine_info = { |
2600 | .name = TYPE_PC_MACHINE, | |
2601 | .parent = TYPE_MACHINE, | |
2602 | .abstract = true, | |
2603 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2604 | .instance_init = pc_machine_initfn, |
d5747cac | 2605 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2606 | .class_init = pc_machine_class_init, |
2607 | .interfaces = (InterfaceInfo[]) { | |
2608 | { TYPE_HOTPLUG_HANDLER }, | |
1255166b | 2609 | { TYPE_NMI }, |
95bee274 IM |
2610 | { } |
2611 | }, | |
d5747cac IM |
2612 | }; |
2613 | ||
2614 | static void pc_machine_register_types(void) | |
2615 | { | |
2616 | type_register_static(&pc_machine_info); | |
2617 | } | |
2618 | ||
2619 | type_init(pc_machine_register_types) |