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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
0d09e41a PB |
26 | #include "hw/i386/pc.h" |
27 | #include "hw/char/serial.h" | |
28 | #include "hw/i386/apic.h" | |
54a40293 EH |
29 | #include "hw/i386/topology.h" |
30 | #include "sysemu/cpus.h" | |
0d09e41a | 31 | #include "hw/block/fdc.h" |
83c9f4ca PB |
32 | #include "hw/ide.h" |
33 | #include "hw/pci/pci.h" | |
2118196b | 34 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
35 | #include "hw/nvram/fw_cfg.h" |
36 | #include "hw/timer/hpet.h" | |
60d8f328 | 37 | #include "hw/smbios/smbios.h" |
83c9f4ca | 38 | #include "hw/loader.h" |
ca20cf32 | 39 | #include "elf.h" |
47b43a1f | 40 | #include "multiboot.h" |
0d09e41a PB |
41 | #include "hw/timer/mc146818rtc.h" |
42 | #include "hw/timer/i8254.h" | |
43 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
44 | #include "hw/pci/msi.h" |
45 | #include "hw/sysbus.h" | |
9c17d615 | 46 | #include "sysemu/sysemu.h" |
e35704ba | 47 | #include "sysemu/numa.h" |
9c17d615 | 48 | #include "sysemu/kvm.h" |
b1c12027 | 49 | #include "sysemu/qtest.h" |
1d31f66b | 50 | #include "kvm_i386.h" |
0d09e41a | 51 | #include "hw/xen/xen.h" |
4be74634 | 52 | #include "sysemu/block-backend.h" |
0d09e41a | 53 | #include "hw/block/block.h" |
a19cbfb3 | 54 | #include "ui/qemu-spice.h" |
022c62cb PB |
55 | #include "exec/memory.h" |
56 | #include "exec/address-spaces.h" | |
9c17d615 | 57 | #include "sysemu/arch_init.h" |
1de7afc9 | 58 | #include "qemu/bitmap.h" |
0c764a9d | 59 | #include "qemu/config-file.h" |
d49b6836 | 60 | #include "qemu/error-report.h" |
0445259b | 61 | #include "hw/acpi/acpi.h" |
5ff020b7 | 62 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 63 | #include "hw/boards.h" |
39848901 | 64 | #include "hw/pci/pci_host.h" |
72c194f7 | 65 | #include "acpi-build.h" |
95bee274 | 66 | #include "hw/mem/pc-dimm.h" |
bf1e8939 | 67 | #include "qapi/visitor.h" |
d1048bef | 68 | #include "qapi-visit.h" |
15eafc2e | 69 | #include "qom/cpu.h" |
1255166b | 70 | #include "hw/nmi.h" |
60c5e104 | 71 | #include "hw/i386/intel_iommu.h" |
80cabfad | 72 | |
471fd342 BS |
73 | /* debug PC/ISA interrupts */ |
74 | //#define DEBUG_IRQ | |
75 | ||
76 | #ifdef DEBUG_IRQ | |
77 | #define DPRINTF(fmt, ...) \ | |
78 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
79 | #else | |
80 | #define DPRINTF(fmt, ...) | |
81 | #endif | |
82 | ||
8a92ea2f | 83 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 84 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 85 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 86 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 87 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 88 | |
4c5b10b7 JS |
89 | #define E820_NR_ENTRIES 16 |
90 | ||
91 | struct e820_entry { | |
92 | uint64_t address; | |
93 | uint64_t length; | |
94 | uint32_t type; | |
541dc0d4 | 95 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
96 | |
97 | struct e820_table { | |
98 | uint32_t count; | |
99 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 100 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 101 | |
7d67110f GH |
102 | static struct e820_table e820_reserve; |
103 | static struct e820_entry *e820_table; | |
104 | static unsigned e820_entries; | |
dd703b99 | 105 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 106 | |
b881fbe9 | 107 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 108 | { |
b881fbe9 | 109 | GSIState *s = opaque; |
1452411b | 110 | |
b881fbe9 JK |
111 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
112 | if (n < ISA_NUM_IRQS) { | |
113 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 114 | } |
b881fbe9 | 115 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 116 | } |
1452411b | 117 | |
258711c6 JG |
118 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
119 | unsigned size) | |
80cabfad FB |
120 | { |
121 | } | |
122 | ||
c02e1eac JG |
123 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
124 | { | |
a6fc23e5 | 125 | return 0xffffffffffffffffULL; |
c02e1eac JG |
126 | } |
127 | ||
f929aad6 | 128 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 129 | static qemu_irq ferr_irq; |
8e78eb28 IY |
130 | |
131 | void pc_register_ferr_irq(qemu_irq irq) | |
132 | { | |
133 | ferr_irq = irq; | |
134 | } | |
135 | ||
f929aad6 FB |
136 | /* XXX: add IGNNE support */ |
137 | void cpu_set_ferr(CPUX86State *s) | |
138 | { | |
d537cf6c | 139 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
140 | } |
141 | ||
258711c6 JG |
142 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
143 | unsigned size) | |
f929aad6 | 144 | { |
d537cf6c | 145 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
146 | } |
147 | ||
c02e1eac JG |
148 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
149 | { | |
a6fc23e5 | 150 | return 0xffffffffffffffffULL; |
c02e1eac JG |
151 | } |
152 | ||
28ab0e2e | 153 | /* TSC handling */ |
28ab0e2e FB |
154 | uint64_t cpu_get_tsc(CPUX86State *env) |
155 | { | |
4a1418e0 | 156 | return cpu_get_ticks(); |
28ab0e2e FB |
157 | } |
158 | ||
3de388f6 | 159 | /* IRQ handling */ |
4a8fa5dc | 160 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 161 | { |
02e51483 | 162 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
163 | int intno; |
164 | ||
bb93e099 WL |
165 | if (!kvm_irqchip_in_kernel()) { |
166 | intno = apic_get_interrupt(cpu->apic_state); | |
167 | if (intno >= 0) { | |
168 | return intno; | |
169 | } | |
170 | /* read the irq from the PIC */ | |
171 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
172 | return -1; | |
173 | } | |
cf6d64bf | 174 | } |
0e21e12b | 175 | |
3de388f6 FB |
176 | intno = pic_read_irq(isa_pic); |
177 | return intno; | |
178 | } | |
179 | ||
d537cf6c | 180 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 181 | { |
182735ef AF |
182 | CPUState *cs = first_cpu; |
183 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 184 | |
471fd342 | 185 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
bb93e099 | 186 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 187 | CPU_FOREACH(cs) { |
182735ef | 188 | cpu = X86_CPU(cs); |
02e51483 CF |
189 | if (apic_accept_pic_intr(cpu->apic_state)) { |
190 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 191 | } |
d5529471 AJ |
192 | } |
193 | } else { | |
d8ed887b | 194 | if (level) { |
c3affe56 | 195 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
196 | } else { |
197 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
198 | } | |
a5b38b51 | 199 | } |
3de388f6 FB |
200 | } |
201 | ||
b0a21b53 FB |
202 | /* PC cmos mappings */ |
203 | ||
80cabfad FB |
204 | #define REG_EQUIPMENT_BYTE 0x14 |
205 | ||
bda05509 | 206 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
207 | { |
208 | int val; | |
209 | ||
210 | switch (fd0) { | |
2da44dd0 | 211 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
212 | /* 1.44 Mb 3"5 drive */ |
213 | val = 4; | |
214 | break; | |
2da44dd0 | 215 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
216 | /* 2.88 Mb 3"5 drive */ |
217 | val = 5; | |
218 | break; | |
2da44dd0 | 219 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
220 | /* 1.2 Mb 5"5 drive */ |
221 | val = 2; | |
222 | break; | |
2da44dd0 | 223 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
224 | default: |
225 | val = 0; | |
226 | break; | |
227 | } | |
228 | return val; | |
229 | } | |
230 | ||
9139046c MA |
231 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
232 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 233 | { |
ba6c2377 FB |
234 | rtc_set_memory(s, type_ofs, 47); |
235 | rtc_set_memory(s, info_ofs, cylinders); | |
236 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
237 | rtc_set_memory(s, info_ofs + 2, heads); | |
238 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
239 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
240 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
241 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
242 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
243 | rtc_set_memory(s, info_ofs + 8, sectors); | |
244 | } | |
245 | ||
6ac0e82d AZ |
246 | /* convert boot_device letter to something recognizable by the bios */ |
247 | static int boot_device2nibble(char boot_device) | |
248 | { | |
249 | switch(boot_device) { | |
250 | case 'a': | |
251 | case 'b': | |
252 | return 0x01; /* floppy boot */ | |
253 | case 'c': | |
254 | return 0x02; /* hard drive boot */ | |
255 | case 'd': | |
256 | return 0x03; /* CD-ROM boot */ | |
257 | case 'n': | |
258 | return 0x04; /* Network boot */ | |
259 | } | |
260 | return 0; | |
261 | } | |
262 | ||
ddcd5531 | 263 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
264 | { |
265 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
266 | int nbds, bds[3] = { 0, }; |
267 | int i; | |
268 | ||
269 | nbds = strlen(boot_device); | |
270 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
271 | error_setg(errp, "Too many boot devices for PC"); |
272 | return; | |
0ecdffbb AJ |
273 | } |
274 | for (i = 0; i < nbds; i++) { | |
275 | bds[i] = boot_device2nibble(boot_device[i]); | |
276 | if (bds[i] == 0) { | |
ddcd5531 GA |
277 | error_setg(errp, "Invalid boot device for PC: '%c'", |
278 | boot_device[i]); | |
279 | return; | |
0ecdffbb AJ |
280 | } |
281 | } | |
282 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 283 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
284 | } |
285 | ||
ddcd5531 | 286 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 287 | { |
ddcd5531 | 288 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
289 | } |
290 | ||
7444ca4e LE |
291 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
292 | { | |
293 | int val, nb, i; | |
2da44dd0 JS |
294 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
295 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
296 | |
297 | /* floppy type */ | |
298 | if (floppy) { | |
299 | for (i = 0; i < 2; i++) { | |
300 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
301 | } | |
302 | } | |
303 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
304 | cmos_get_fd_drive_type(fd_type[1]); | |
305 | rtc_set_memory(rtc_state, 0x10, val); | |
306 | ||
307 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
308 | nb = 0; | |
2da44dd0 | 309 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
310 | nb++; |
311 | } | |
2da44dd0 | 312 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
313 | nb++; |
314 | } | |
315 | switch (nb) { | |
316 | case 0: | |
317 | break; | |
318 | case 1: | |
319 | val |= 0x01; /* 1 drive, ready for boot */ | |
320 | break; | |
321 | case 2: | |
322 | val |= 0x41; /* 2 drives, ready for boot */ | |
323 | break; | |
324 | } | |
325 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
326 | } | |
327 | ||
c0897e0c MA |
328 | typedef struct pc_cmos_init_late_arg { |
329 | ISADevice *rtc_state; | |
9139046c | 330 | BusState *idebus[2]; |
c0897e0c MA |
331 | } pc_cmos_init_late_arg; |
332 | ||
b86f4613 LE |
333 | typedef struct check_fdc_state { |
334 | ISADevice *floppy; | |
335 | bool multiple; | |
336 | } CheckFdcState; | |
337 | ||
338 | static int check_fdc(Object *obj, void *opaque) | |
339 | { | |
340 | CheckFdcState *state = opaque; | |
341 | Object *fdc; | |
342 | uint32_t iobase; | |
343 | Error *local_err = NULL; | |
344 | ||
345 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
346 | if (!fdc) { | |
347 | return 0; | |
348 | } | |
349 | ||
350 | iobase = object_property_get_int(obj, "iobase", &local_err); | |
351 | if (local_err || iobase != 0x3f0) { | |
352 | error_free(local_err); | |
353 | return 0; | |
354 | } | |
355 | ||
356 | if (state->floppy) { | |
357 | state->multiple = true; | |
358 | } else { | |
359 | state->floppy = ISA_DEVICE(obj); | |
360 | } | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static const char * const fdc_container_path[] = { | |
365 | "/unattached", "/peripheral", "/peripheral-anon" | |
366 | }; | |
367 | ||
424e4a87 RK |
368 | /* |
369 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
370 | * and ACPI objects. | |
371 | */ | |
372 | ISADevice *pc_find_fdc0(void) | |
373 | { | |
374 | int i; | |
375 | Object *container; | |
376 | CheckFdcState state = { 0 }; | |
377 | ||
378 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
379 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
380 | object_child_foreach(container, check_fdc, &state); | |
381 | } | |
382 | ||
383 | if (state.multiple) { | |
384 | error_report("warning: multiple floppy disk controllers with " | |
433672b0 MA |
385 | "iobase=0x3f0 have been found"); |
386 | error_printf("the one being picked for CMOS setup might not reflect " | |
7ea7d36e | 387 | "your intent\n"); |
424e4a87 RK |
388 | } |
389 | ||
390 | return state.floppy; | |
391 | } | |
392 | ||
c0897e0c MA |
393 | static void pc_cmos_init_late(void *opaque) |
394 | { | |
395 | pc_cmos_init_late_arg *arg = opaque; | |
396 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
397 | int16_t cylinders; |
398 | int8_t heads, sectors; | |
c0897e0c | 399 | int val; |
2adc99b2 | 400 | int i, trans; |
c0897e0c | 401 | |
9139046c | 402 | val = 0; |
272f0428 CP |
403 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
404 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
405 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
406 | val |= 0xf0; | |
407 | } | |
272f0428 CP |
408 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
409 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
410 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
411 | val |= 0x0f; | |
412 | } | |
413 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
414 | |
415 | val = 0; | |
416 | for (i = 0; i < 4; i++) { | |
9139046c MA |
417 | /* NOTE: ide_get_geometry() returns the physical |
418 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
419 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
420 | geometry can be different if a translation is done. */ | |
272f0428 CP |
421 | if (arg->idebus[i / 2] && |
422 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 423 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
424 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
425 | assert((trans & ~3) == 0); | |
426 | val |= trans << (i * 2); | |
c0897e0c MA |
427 | } |
428 | } | |
429 | rtc_set_memory(s, 0x39, val); | |
430 | ||
424e4a87 | 431 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 432 | |
c0897e0c MA |
433 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
434 | } | |
435 | ||
23d30407 | 436 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 437 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 438 | ISADevice *s) |
80cabfad | 439 | { |
7444ca4e | 440 | int val; |
c0897e0c | 441 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 442 | |
b0a21b53 | 443 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
444 | |
445 | /* memory size */ | |
e89001f7 | 446 | /* base memory (first MiB) */ |
88076854 | 447 | val = MIN(pcms->below_4g_mem_size / 1024, 640); |
333190eb FB |
448 | rtc_set_memory(s, 0x15, val); |
449 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 450 | /* extended memory (next 64MiB) */ |
88076854 EH |
451 | if (pcms->below_4g_mem_size > 1024 * 1024) { |
452 | val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; | |
e89001f7 MA |
453 | } else { |
454 | val = 0; | |
455 | } | |
80cabfad FB |
456 | if (val > 65535) |
457 | val = 65535; | |
b0a21b53 FB |
458 | rtc_set_memory(s, 0x17, val); |
459 | rtc_set_memory(s, 0x18, val >> 8); | |
460 | rtc_set_memory(s, 0x30, val); | |
461 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 462 | /* memory between 16MiB and 4GiB */ |
88076854 EH |
463 | if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { |
464 | val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; | |
e89001f7 | 465 | } else { |
9da98861 | 466 | val = 0; |
e89001f7 | 467 | } |
80cabfad FB |
468 | if (val > 65535) |
469 | val = 65535; | |
b0a21b53 FB |
470 | rtc_set_memory(s, 0x34, val); |
471 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 472 | /* memory above 4GiB */ |
88076854 | 473 | val = pcms->above_4g_mem_size / 65536; |
e89001f7 MA |
474 | rtc_set_memory(s, 0x5b, val); |
475 | rtc_set_memory(s, 0x5c, val >> 8); | |
476 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 477 | |
23d30407 | 478 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 479 | TYPE_ISA_DEVICE, |
ec68007a | 480 | (Object **)&pcms->rtc, |
2d996150 GZ |
481 | object_property_allow_set_link, |
482 | OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | |
23d30407 | 483 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 484 | "rtc_state", &error_abort); |
298e01b6 | 485 | |
007b0657 | 486 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 487 | |
b0a21b53 | 488 | val = 0; |
b0a21b53 FB |
489 | val |= 0x02; /* FPU is there */ |
490 | val |= 0x04; /* PS/2 mouse installed */ | |
491 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
492 | ||
b86f4613 | 493 | /* hard drives and FDC */ |
c0897e0c | 494 | arg.rtc_state = s; |
9139046c MA |
495 | arg.idebus[0] = idebus0; |
496 | arg.idebus[1] = idebus1; | |
c0897e0c | 497 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
498 | } |
499 | ||
a0881c64 AF |
500 | #define TYPE_PORT92 "port92" |
501 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
502 | ||
4b78a802 BS |
503 | /* port 92 stuff: could be split off */ |
504 | typedef struct Port92State { | |
a0881c64 AF |
505 | ISADevice parent_obj; |
506 | ||
23af670e | 507 | MemoryRegion io; |
4b78a802 | 508 | uint8_t outport; |
d812b3d6 | 509 | qemu_irq a20_out; |
4b78a802 BS |
510 | } Port92State; |
511 | ||
93ef4192 AG |
512 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
513 | unsigned size) | |
4b78a802 BS |
514 | { |
515 | Port92State *s = opaque; | |
4700a316 | 516 | int oldval = s->outport; |
4b78a802 | 517 | |
c5539cb4 | 518 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 | 519 | s->outport = val; |
d812b3d6 | 520 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 521 | if ((val & 1) && !(oldval & 1)) { |
cf83f140 | 522 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
4b78a802 BS |
523 | } |
524 | } | |
525 | ||
93ef4192 AG |
526 | static uint64_t port92_read(void *opaque, hwaddr addr, |
527 | unsigned size) | |
4b78a802 BS |
528 | { |
529 | Port92State *s = opaque; | |
530 | uint32_t ret; | |
531 | ||
532 | ret = s->outport; | |
533 | DPRINTF("port92: read 0x%02x\n", ret); | |
534 | return ret; | |
535 | } | |
536 | ||
d80fe99d | 537 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 538 | { |
d80fe99d | 539 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
540 | } |
541 | ||
542 | static const VMStateDescription vmstate_port92_isa = { | |
543 | .name = "port92", | |
544 | .version_id = 1, | |
545 | .minimum_version_id = 1, | |
d49805ae | 546 | .fields = (VMStateField[]) { |
4b78a802 BS |
547 | VMSTATE_UINT8(outport, Port92State), |
548 | VMSTATE_END_OF_LIST() | |
549 | } | |
550 | }; | |
551 | ||
552 | static void port92_reset(DeviceState *d) | |
553 | { | |
a0881c64 | 554 | Port92State *s = PORT92(d); |
4b78a802 BS |
555 | |
556 | s->outport &= ~1; | |
557 | } | |
558 | ||
23af670e | 559 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
560 | .read = port92_read, |
561 | .write = port92_write, | |
562 | .impl = { | |
563 | .min_access_size = 1, | |
564 | .max_access_size = 1, | |
565 | }, | |
566 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
567 | }; |
568 | ||
db895a1e | 569 | static void port92_initfn(Object *obj) |
4b78a802 | 570 | { |
db895a1e | 571 | Port92State *s = PORT92(obj); |
4b78a802 | 572 | |
1437c94b | 573 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 574 | |
4b78a802 | 575 | s->outport = 0; |
d812b3d6 EV |
576 | |
577 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
578 | } |
579 | ||
580 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
581 | { | |
582 | ISADevice *isadev = ISA_DEVICE(dev); | |
583 | Port92State *s = PORT92(dev); | |
584 | ||
585 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
586 | } |
587 | ||
8f04ee08 AL |
588 | static void port92_class_initfn(ObjectClass *klass, void *data) |
589 | { | |
39bffca2 | 590 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 591 | |
db895a1e | 592 | dc->realize = port92_realizefn; |
39bffca2 AL |
593 | dc->reset = port92_reset; |
594 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
595 | /* |
596 | * Reason: unlike ordinary ISA devices, this one needs additional | |
597 | * wiring: its A20 output line needs to be wired up by | |
598 | * port92_init(). | |
599 | */ | |
e90f2a8c | 600 | dc->user_creatable = false; |
8f04ee08 AL |
601 | } |
602 | ||
8c43a6f0 | 603 | static const TypeInfo port92_info = { |
a0881c64 | 604 | .name = TYPE_PORT92, |
39bffca2 AL |
605 | .parent = TYPE_ISA_DEVICE, |
606 | .instance_size = sizeof(Port92State), | |
db895a1e | 607 | .instance_init = port92_initfn, |
39bffca2 | 608 | .class_init = port92_class_initfn, |
4b78a802 BS |
609 | }; |
610 | ||
83f7d43a | 611 | static void port92_register_types(void) |
4b78a802 | 612 | { |
39bffca2 | 613 | type_register_static(&port92_info); |
4b78a802 | 614 | } |
83f7d43a AF |
615 | |
616 | type_init(port92_register_types) | |
4b78a802 | 617 | |
956a3e6b | 618 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 619 | { |
cc36a7a2 | 620 | X86CPU *cpu = opaque; |
e1a23744 | 621 | |
956a3e6b | 622 | /* XXX: send to all CPUs ? */ |
4b78a802 | 623 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 624 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
625 | } |
626 | ||
4c5b10b7 JS |
627 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
628 | { | |
7d67110f | 629 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
630 | struct e820_entry *entry; |
631 | ||
7d67110f GH |
632 | if (type != E820_RAM) { |
633 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
634 | if (index >= E820_NR_ENTRIES) { | |
635 | return -EBUSY; | |
636 | } | |
637 | entry = &e820_reserve.entry[index++]; | |
638 | ||
639 | entry->address = cpu_to_le64(address); | |
640 | entry->length = cpu_to_le64(length); | |
641 | entry->type = cpu_to_le32(type); | |
642 | ||
643 | e820_reserve.count = cpu_to_le32(index); | |
644 | } | |
4c5b10b7 | 645 | |
7d67110f | 646 | /* new "etc/e820" file -- include ram too */ |
ab3ad07f | 647 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); |
7d67110f GH |
648 | e820_table[e820_entries].address = cpu_to_le64(address); |
649 | e820_table[e820_entries].length = cpu_to_le64(length); | |
650 | e820_table[e820_entries].type = cpu_to_le32(type); | |
651 | e820_entries++; | |
4c5b10b7 | 652 | |
7d67110f | 653 | return e820_entries; |
4c5b10b7 JS |
654 | } |
655 | ||
7bf8ef19 GS |
656 | int e820_get_num_entries(void) |
657 | { | |
658 | return e820_entries; | |
659 | } | |
660 | ||
661 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
662 | { | |
663 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
664 | *address = le64_to_cpu(e820_table[idx].address); | |
665 | *length = le64_to_cpu(e820_table[idx].length); | |
666 | return true; | |
667 | } | |
668 | return false; | |
669 | } | |
670 | ||
54a40293 EH |
671 | /* Enables contiguous-apic-ID mode, for compatibility */ |
672 | static bool compat_apic_id_mode; | |
673 | ||
674 | void enable_compat_apic_id_mode(void) | |
675 | { | |
676 | compat_apic_id_mode = true; | |
677 | } | |
678 | ||
679 | /* Calculates initial APIC ID for a specific CPU index | |
680 | * | |
681 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
682 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
683 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
684 | * all CPUs up to max_cpus. | |
685 | */ | |
686 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
687 | { | |
688 | uint32_t correct_id; | |
689 | static bool warned; | |
690 | ||
691 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
692 | if (compat_apic_id_mode) { | |
b1c12027 | 693 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { |
54a40293 EH |
694 | error_report("APIC IDs set in compatibility mode, " |
695 | "CPU topology won't match the configuration"); | |
696 | warned = true; | |
697 | } | |
698 | return cpu_index; | |
699 | } else { | |
700 | return correct_id; | |
701 | } | |
702 | } | |
703 | ||
f2098f48 | 704 | static void pc_build_smbios(PCMachineState *pcms) |
80cabfad | 705 | { |
c97294ec GS |
706 | uint8_t *smbios_tables, *smbios_anchor; |
707 | size_t smbios_tables_len, smbios_anchor_len; | |
89cc4a27 WH |
708 | struct smbios_phys_mem_area *mem_array; |
709 | unsigned i, array_count; | |
38690a1c IM |
710 | MachineState *ms = MACHINE(pcms); |
711 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
f2098f48 IM |
712 | |
713 | /* tell smbios about cpuid version and features */ | |
714 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
5fd0a9d4 WH |
715 | |
716 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); | |
717 | if (smbios_tables) { | |
f2098f48 | 718 | fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
5fd0a9d4 WH |
719 | smbios_tables, smbios_tables_len); |
720 | } | |
721 | ||
89cc4a27 WH |
722 | /* build the array of physical mem area from e820 table */ |
723 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
724 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
725 | uint64_t addr, len; | |
726 | ||
727 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
728 | mem_array[array_count].address = addr; | |
729 | mem_array[array_count].length = len; | |
730 | array_count++; | |
731 | } | |
732 | } | |
733 | smbios_get_tables(mem_array, array_count, | |
734 | &smbios_tables, &smbios_tables_len, | |
5fd0a9d4 | 735 | &smbios_anchor, &smbios_anchor_len); |
89cc4a27 WH |
736 | g_free(mem_array); |
737 | ||
5fd0a9d4 | 738 | if (smbios_anchor) { |
f2098f48 | 739 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", |
5fd0a9d4 | 740 | smbios_tables, smbios_tables_len); |
f2098f48 | 741 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", |
5fd0a9d4 WH |
742 | smbios_anchor, smbios_anchor_len); |
743 | } | |
744 | } | |
745 | ||
ebde2465 | 746 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) |
5fd0a9d4 WH |
747 | { |
748 | FWCfgState *fw_cfg; | |
11c2fd3e | 749 | uint64_t *numa_fw_cfg; |
ea265072 IM |
750 | int i; |
751 | const CPUArchIdList *cpus; | |
752 | MachineClass *mc = MACHINE_GET_CLASS(pcms); | |
3cce6243 | 753 | |
305ae888 | 754 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); |
e3cadac0 | 755 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
c886fc4c | 756 | |
1d934e89 EH |
757 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
758 | * | |
a3abd0f2 IM |
759 | * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for |
760 | * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, | |
761 | * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface | |
762 | * for CPU hotplug also uses APIC ID and not "CPU index". | |
763 | * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", | |
764 | * but the "limit to the APIC ID values SeaBIOS may see". | |
1d934e89 | 765 | * |
a3abd0f2 IM |
766 | * So for compatibility reasons with old BIOSes we are stuck with |
767 | * "etc/max-cpus" actually being apic_id_limit | |
1d934e89 | 768 | */ |
ebde2465 | 769 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); |
905fdcb5 | 770 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
771 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
772 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 773 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 774 | |
089da572 | 775 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
776 | &e820_reserve, sizeof(e820_reserve)); |
777 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
778 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 779 | |
089da572 | 780 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
781 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
782 | * of nodes, one word for each VCPU->node and one word for each node to | |
783 | * hold the amount of memory. | |
784 | */ | |
ebde2465 | 785 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); |
11c2fd3e | 786 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
ea265072 IM |
787 | cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); |
788 | for (i = 0; i < cpus->len; i++) { | |
789 | unsigned int apic_id = cpus->cpus[i].arch_id; | |
ebde2465 | 790 | assert(apic_id < pcms->apic_id_limit); |
ea265072 IM |
791 | if (cpus->cpus[i].props.has_node_id) { |
792 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); | |
11c2fd3e AL |
793 | } |
794 | } | |
795 | for (i = 0; i < nb_numa_nodes; i++) { | |
ebde2465 IM |
796 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = |
797 | cpu_to_le64(numa_info[i].node_mem); | |
11c2fd3e | 798 | } |
089da572 | 799 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
ebde2465 | 800 | (1 + pcms->apic_id_limit + nb_numa_nodes) * |
1d934e89 | 801 | sizeof(*numa_fw_cfg)); |
bf483392 AG |
802 | |
803 | return fw_cfg; | |
80cabfad FB |
804 | } |
805 | ||
642a4f96 TS |
806 | static long get_file_size(FILE *f) |
807 | { | |
808 | long where, size; | |
809 | ||
810 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
811 | ||
812 | where = ftell(f); | |
813 | fseek(f, 0, SEEK_END); | |
814 | size = ftell(f); | |
815 | fseek(f, where, SEEK_SET); | |
816 | ||
817 | return size; | |
818 | } | |
819 | ||
3cbeb524 AB |
820 | /* setup_data types */ |
821 | #define SETUP_NONE 0 | |
822 | #define SETUP_E820_EXT 1 | |
823 | #define SETUP_DTB 2 | |
824 | #define SETUP_PCI 3 | |
825 | #define SETUP_EFI 4 | |
826 | ||
827 | struct setup_data { | |
828 | uint64_t next; | |
829 | uint32_t type; | |
830 | uint32_t len; | |
831 | uint8_t data[0]; | |
832 | } __attribute__((packed)); | |
833 | ||
df1f79fd EH |
834 | static void load_linux(PCMachineState *pcms, |
835 | FWCfgState *fw_cfg) | |
642a4f96 TS |
836 | { |
837 | uint16_t protocol; | |
5cea8590 | 838 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
3cbeb524 | 839 | int dtb_size, setup_data_offset; |
642a4f96 | 840 | uint32_t initrd_max; |
57a46d05 | 841 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 842 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 843 | FILE *f; |
bf4e5d92 | 844 | char *vmode; |
df1f79fd | 845 | MachineState *machine = MACHINE(pcms); |
cd4040ec | 846 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
3cbeb524 | 847 | struct setup_data *setup_data; |
df1f79fd EH |
848 | const char *kernel_filename = machine->kernel_filename; |
849 | const char *initrd_filename = machine->initrd_filename; | |
3cbeb524 | 850 | const char *dtb_filename = machine->dtb; |
df1f79fd | 851 | const char *kernel_cmdline = machine->kernel_cmdline; |
642a4f96 TS |
852 | |
853 | /* Align to 16 bytes as a paranoia measure */ | |
854 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
855 | ||
856 | /* load the kernel header */ | |
857 | f = fopen(kernel_filename, "rb"); | |
858 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
859 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
860 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
861 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
862 | kernel_filename, strerror(errno)); | |
863 | exit(1); | |
642a4f96 TS |
864 | } |
865 | ||
866 | /* kernel protocol version */ | |
bc4edd79 | 867 | #if 0 |
642a4f96 | 868 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 869 | #endif |
0f9d76e5 LG |
870 | if (ldl_p(header+0x202) == 0x53726448) { |
871 | protocol = lduw_p(header+0x206); | |
872 | } else { | |
873 | /* This looks like a multiboot kernel. If it is, let's stop | |
874 | treating it like a Linux kernel. */ | |
52001445 | 875 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 876 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 877 | return; |
0f9d76e5 LG |
878 | } |
879 | protocol = 0; | |
f16408df | 880 | } |
642a4f96 TS |
881 | |
882 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
883 | /* Low kernel */ |
884 | real_addr = 0x90000; | |
885 | cmdline_addr = 0x9a000 - cmdline_size; | |
886 | prot_addr = 0x10000; | |
642a4f96 | 887 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
888 | /* High but ancient kernel */ |
889 | real_addr = 0x90000; | |
890 | cmdline_addr = 0x9a000 - cmdline_size; | |
891 | prot_addr = 0x100000; | |
642a4f96 | 892 | } else { |
0f9d76e5 LG |
893 | /* High and recent kernel */ |
894 | real_addr = 0x10000; | |
895 | cmdline_addr = 0x20000; | |
896 | prot_addr = 0x100000; | |
642a4f96 TS |
897 | } |
898 | ||
bc4edd79 | 899 | #if 0 |
642a4f96 | 900 | fprintf(stderr, |
0f9d76e5 LG |
901 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
902 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
903 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
904 | real_addr, | |
905 | cmdline_addr, | |
906 | prot_addr); | |
bc4edd79 | 907 | #endif |
642a4f96 TS |
908 | |
909 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
910 | if (protocol >= 0x203) { |
911 | initrd_max = ldl_p(header+0x22c); | |
912 | } else { | |
913 | initrd_max = 0x37ffffff; | |
914 | } | |
642a4f96 | 915 | |
cd4040ec EH |
916 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { |
917 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
927766c7 | 918 | } |
642a4f96 | 919 | |
57a46d05 AG |
920 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
921 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 922 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
923 | |
924 | if (protocol >= 0x202) { | |
0f9d76e5 | 925 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 926 | } else { |
0f9d76e5 LG |
927 | stw_p(header+0x20, 0xA33F); |
928 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
929 | } |
930 | ||
bf4e5d92 PT |
931 | /* handle vga= parameter */ |
932 | vmode = strstr(kernel_cmdline, "vga="); | |
933 | if (vmode) { | |
934 | unsigned int video_mode; | |
935 | /* skip "vga=" */ | |
936 | vmode += 4; | |
937 | if (!strncmp(vmode, "normal", 6)) { | |
938 | video_mode = 0xffff; | |
939 | } else if (!strncmp(vmode, "ext", 3)) { | |
940 | video_mode = 0xfffe; | |
941 | } else if (!strncmp(vmode, "ask", 3)) { | |
942 | video_mode = 0xfffd; | |
943 | } else { | |
944 | video_mode = strtol(vmode, NULL, 0); | |
945 | } | |
946 | stw_p(header+0x1fa, video_mode); | |
947 | } | |
948 | ||
642a4f96 | 949 | /* loader type */ |
5cbdb3a3 | 950 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
951 | If this code is substantially changed, you may want to consider |
952 | incrementing the revision. */ | |
0f9d76e5 LG |
953 | if (protocol >= 0x200) { |
954 | header[0x210] = 0xB0; | |
955 | } | |
642a4f96 TS |
956 | /* heap */ |
957 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
958 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
959 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
960 | } |
961 | ||
962 | /* load initrd */ | |
963 | if (initrd_filename) { | |
0f9d76e5 LG |
964 | if (protocol < 0x200) { |
965 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
966 | exit(1); | |
967 | } | |
642a4f96 | 968 | |
0f9d76e5 | 969 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 | 970 | if (initrd_size < 0) { |
7454e51d MT |
971 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
972 | initrd_filename, strerror(errno)); | |
d6fa4b77 MK |
973 | exit(1); |
974 | } | |
975 | ||
45a50b16 | 976 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 977 | |
7267c094 | 978 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
979 | load_image(initrd_filename, initrd_data); |
980 | ||
981 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
982 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
983 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 984 | |
0f9d76e5 LG |
985 | stl_p(header+0x218, initrd_addr); |
986 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
987 | } |
988 | ||
45a50b16 | 989 | /* load kernel and setup */ |
642a4f96 | 990 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
991 | if (setup_size == 0) { |
992 | setup_size = 4; | |
993 | } | |
642a4f96 | 994 | setup_size = (setup_size+1)*512; |
ec5fd402 PB |
995 | if (setup_size > kernel_size) { |
996 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
997 | exit(1); | |
998 | } | |
45a50b16 | 999 | kernel_size -= setup_size; |
642a4f96 | 1000 | |
7267c094 AL |
1001 | setup = g_malloc(setup_size); |
1002 | kernel = g_malloc(kernel_size); | |
45a50b16 | 1003 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
1004 | if (fread(setup, 1, setup_size, f) != setup_size) { |
1005 | fprintf(stderr, "fread() failed\n"); | |
1006 | exit(1); | |
1007 | } | |
1008 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1009 | fprintf(stderr, "fread() failed\n"); | |
1010 | exit(1); | |
1011 | } | |
642a4f96 | 1012 | fclose(f); |
3cbeb524 AB |
1013 | |
1014 | /* append dtb to kernel */ | |
1015 | if (dtb_filename) { | |
1016 | if (protocol < 0x209) { | |
1017 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1018 | exit(1); | |
1019 | } | |
1020 | ||
1021 | dtb_size = get_image_size(dtb_filename); | |
1022 | if (dtb_size <= 0) { | |
1023 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1024 | dtb_filename, strerror(errno)); | |
1025 | exit(1); | |
1026 | } | |
1027 | ||
1028 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1029 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1030 | kernel = g_realloc(kernel, kernel_size); | |
1031 | ||
1032 | stq_p(header+0x250, prot_addr + setup_data_offset); | |
1033 | ||
1034 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1035 | setup_data->next = 0; | |
1036 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1037 | setup_data->len = cpu_to_le32(dtb_size); | |
1038 | ||
1039 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1040 | } | |
1041 | ||
45a50b16 | 1042 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
1043 | |
1044 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1045 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1046 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1047 | ||
1048 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1049 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1050 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1051 | ||
98e753a6 IM |
1052 | option_rom[nb_option_roms].bootindex = 0; |
1053 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1054 | if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { | |
b2a575a1 | 1055 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; |
b2a575a1 | 1056 | } |
57a46d05 | 1057 | nb_option_roms++; |
642a4f96 TS |
1058 | } |
1059 | ||
b41a2cd1 FB |
1060 | #define NE2000_NB_MAX 6 |
1061 | ||
675d6f82 BS |
1062 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
1063 | 0x280, 0x380 }; | |
1064 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 1065 | |
48a18b3c | 1066 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
1067 | { |
1068 | static int nb_ne2k = 0; | |
1069 | ||
1070 | if (nb_ne2k == NE2000_NB_MAX) | |
1071 | return; | |
48a18b3c | 1072 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 1073 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
1074 | nb_ne2k++; |
1075 | } | |
1076 | ||
92a16d7a | 1077 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 1078 | { |
4917cf44 AF |
1079 | if (current_cpu) { |
1080 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 1081 | return cpu->apic_state; |
0e26b7b8 BS |
1082 | } else { |
1083 | return NULL; | |
1084 | } | |
1085 | } | |
1086 | ||
845773ab | 1087 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 1088 | { |
c3affe56 | 1089 | X86CPU *cpu = opaque; |
53b67b30 BS |
1090 | |
1091 | if (level) { | |
c3affe56 | 1092 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
1093 | } |
1094 | } | |
1095 | ||
074281d6 | 1096 | static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) |
31050930 | 1097 | { |
074281d6 | 1098 | Object *cpu = NULL; |
31050930 IM |
1099 | Error *local_err = NULL; |
1100 | ||
074281d6 | 1101 | cpu = object_new(typename); |
31050930 | 1102 | |
074281d6 IM |
1103 | object_property_set_int(cpu, apic_id, "apic-id", &local_err); |
1104 | object_property_set_bool(cpu, true, "realized", &local_err); | |
31050930 | 1105 | |
074281d6 | 1106 | object_unref(cpu); |
021c9d25 | 1107 | error_propagate(errp, local_err); |
31050930 IM |
1108 | } |
1109 | ||
c649983b IM |
1110 | void pc_hot_add_cpu(const int64_t id, Error **errp) |
1111 | { | |
6aff24c6 | 1112 | ObjectClass *oc; |
38690a1c | 1113 | MachineState *ms = MACHINE(qdev_get_machine()); |
c649983b | 1114 | int64_t apic_id = x86_cpu_apic_id_from_index(id); |
0e3bd562 | 1115 | Error *local_err = NULL; |
c649983b | 1116 | |
8de433cb IM |
1117 | if (id < 0) { |
1118 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1119 | return; | |
1120 | } | |
1121 | ||
5ff020b7 EH |
1122 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1123 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1124 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1125 | id, apic_id); | |
1126 | return; | |
1127 | } | |
1128 | ||
38690a1c IM |
1129 | assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */ |
1130 | oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu)); | |
074281d6 | 1131 | pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); |
0e3bd562 AF |
1132 | if (local_err) { |
1133 | error_propagate(errp, local_err); | |
1134 | return; | |
1135 | } | |
c649983b IM |
1136 | } |
1137 | ||
4884b7bf | 1138 | void pc_cpus_init(PCMachineState *pcms) |
70166477 IY |
1139 | { |
1140 | int i; | |
6aff24c6 IM |
1141 | CPUClass *cc; |
1142 | ObjectClass *oc; | |
1143 | const char *typename; | |
1144 | gchar **model_pieces; | |
c96a1c0b | 1145 | const CPUArchIdList *possible_cpus; |
4884b7bf | 1146 | MachineState *machine = MACHINE(pcms); |
c96a1c0b | 1147 | MachineClass *mc = MACHINE_GET_CLASS(pcms); |
70166477 IY |
1148 | |
1149 | /* init CPUs */ | |
4884b7bf | 1150 | if (machine->cpu_model == NULL) { |
70166477 | 1151 | #ifdef TARGET_X86_64 |
4884b7bf | 1152 | machine->cpu_model = "qemu64"; |
70166477 | 1153 | #else |
4884b7bf | 1154 | machine->cpu_model = "qemu32"; |
70166477 IY |
1155 | #endif |
1156 | } | |
1157 | ||
6aff24c6 IM |
1158 | model_pieces = g_strsplit(machine->cpu_model, ",", 2); |
1159 | if (!model_pieces[0]) { | |
1160 | error_report("Invalid/empty CPU model name"); | |
1161 | exit(1); | |
1162 | } | |
1163 | ||
1164 | oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); | |
1165 | if (oc == NULL) { | |
1166 | error_report("Unable to find CPU definition: %s", model_pieces[0]); | |
1167 | exit(1); | |
1168 | } | |
1169 | typename = object_class_get_name(oc); | |
1170 | cc = CPU_CLASS(oc); | |
1171 | cc->parse_features(typename, model_pieces[1], &error_fatal); | |
1172 | g_strfreev(model_pieces); | |
1173 | ||
ebde2465 IM |
1174 | /* Calculates the limit to CPU APIC ID values |
1175 | * | |
1176 | * Limit for the APIC ID value, so that all | |
1177 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1178 | * | |
1179 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1180 | */ | |
1181 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
c96a1c0b IM |
1182 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
1183 | for (i = 0; i < smp_cpus; i++) { | |
1184 | pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal); | |
70166477 IY |
1185 | } |
1186 | } | |
1187 | ||
217f1b4a HZ |
1188 | static void pc_build_feature_control_file(PCMachineState *pcms) |
1189 | { | |
38690a1c IM |
1190 | MachineState *ms = MACHINE(pcms); |
1191 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
217f1b4a HZ |
1192 | CPUX86State *env = &cpu->env; |
1193 | uint32_t unused, ecx, edx; | |
1194 | uint64_t feature_control_bits = 0; | |
1195 | uint64_t *val; | |
1196 | ||
1197 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); | |
1198 | if (ecx & CPUID_EXT_VMX) { | |
1199 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1200 | } | |
1201 | ||
1202 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == | |
1203 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && | |
1204 | (env->mcg_cap & MCG_LMCE_P)) { | |
1205 | feature_control_bits |= FEATURE_CONTROL_LMCE; | |
1206 | } | |
1207 | ||
1208 | if (!feature_control_bits) { | |
1209 | return; | |
1210 | } | |
1211 | ||
1212 | val = g_malloc(sizeof(*val)); | |
1213 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); | |
1214 | fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); | |
1215 | } | |
1216 | ||
e3cadac0 IM |
1217 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
1218 | { | |
1219 | if (cpus_count > 0xff) { | |
1220 | /* If the number of CPUs can't be represented in 8 bits, the | |
1221 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1222 | * to make old BIOSes fail more predictably. | |
1223 | */ | |
1224 | rtc_set_memory(rtc, 0x5f, 0); | |
1225 | } else { | |
1226 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1227 | } | |
1228 | } | |
1229 | ||
3459a625 | 1230 | static |
9ebeed0c | 1231 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1232 | { |
9ebeed0c EH |
1233 | PCMachineState *pcms = container_of(notifier, |
1234 | PCMachineState, machine_done); | |
1235 | PCIBus *bus = pcms->bus; | |
2118196b | 1236 | |
ba157b69 | 1237 | /* set the number of CPUs */ |
e3cadac0 | 1238 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); |
ba157b69 | 1239 | |
2118196b MA |
1240 | if (bus) { |
1241 | int extra_hosts = 0; | |
1242 | ||
1243 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1244 | /* look for expander root buses */ | |
1245 | if (pci_bus_is_root(bus)) { | |
1246 | extra_hosts++; | |
1247 | } | |
1248 | } | |
f264d360 | 1249 | if (extra_hosts && pcms->fw_cfg) { |
2118196b MA |
1250 | uint64_t *val = g_malloc(sizeof(*val)); |
1251 | *val = cpu_to_le64(extra_hosts); | |
f264d360 | 1252 | fw_cfg_add_file(pcms->fw_cfg, |
2118196b MA |
1253 | "etc/extra-pci-roots", val, sizeof(*val)); |
1254 | } | |
1255 | } | |
1256 | ||
bb292f5a | 1257 | acpi_setup(); |
6d42eefa | 1258 | if (pcms->fw_cfg) { |
f2098f48 | 1259 | pc_build_smbios(pcms); |
217f1b4a | 1260 | pc_build_feature_control_file(pcms); |
e3cadac0 IM |
1261 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
1262 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
6d42eefa | 1263 | } |
60c5e104 IM |
1264 | |
1265 | if (pcms->apic_id_limit > 255) { | |
1266 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); | |
1267 | ||
1268 | if (!iommu || !iommu->x86_iommu.intr_supported || | |
1269 | iommu->intr_eim != ON_OFF_AUTO_ON) { | |
1270 | error_report("current -smp configuration requires " | |
1271 | "Extended Interrupt Mode enabled. " | |
1272 | "You can add an IOMMU using: " | |
1273 | "-device intel-iommu,intremap=on,eim=on"); | |
1274 | exit(EXIT_FAILURE); | |
1275 | } | |
1276 | } | |
3459a625 MT |
1277 | } |
1278 | ||
e4e8ba04 | 1279 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1280 | { |
1f3aba37 | 1281 | int i; |
b20c9bd5 | 1282 | |
dd4c2f01 EH |
1283 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); |
1284 | pcms->numa_nodes = nb_numa_nodes; | |
1285 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1286 | sizeof *pcms->node_mem); | |
8c85901e | 1287 | for (i = 0; i < nb_numa_nodes; i++) { |
dd4c2f01 | 1288 | pcms->node_mem[i] = numa_info[i].node_mem; |
8c85901e WG |
1289 | } |
1290 | ||
9ebeed0c EH |
1291 | pcms->machine_done.notify = pc_machine_done; |
1292 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1293 | } |
1294 | ||
83d08f26 MT |
1295 | /* setup pci memory address space mapping into system address space */ |
1296 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1297 | MemoryRegion *pci_address_space) | |
39848901 | 1298 | { |
83d08f26 MT |
1299 | /* Set to lower priority than RAM */ |
1300 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1301 | pci_address_space, -1); | |
39848901 IM |
1302 | } |
1303 | ||
f7e4dd6c GH |
1304 | void pc_acpi_init(const char *default_dsdt) |
1305 | { | |
c5a98cf3 | 1306 | char *filename; |
f7e4dd6c GH |
1307 | |
1308 | if (acpi_tables != NULL) { | |
1309 | /* manually set via -acpitable, leave it alone */ | |
1310 | return; | |
1311 | } | |
1312 | ||
1313 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1314 | if (filename == NULL) { | |
1315 | fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); | |
c5a98cf3 | 1316 | } else { |
5bdb59a2 MA |
1317 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, |
1318 | &error_abort); | |
c5a98cf3 | 1319 | Error *err = NULL; |
f7e4dd6c | 1320 | |
5bdb59a2 | 1321 | qemu_opt_set(opts, "file", filename, &error_abort); |
0c764a9d | 1322 | |
1a4b2666 | 1323 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1324 | if (err) { |
c29b77f9 MA |
1325 | error_reportf_err(err, "WARNING: failed to load %s: ", |
1326 | filename); | |
c5a98cf3 | 1327 | } |
c5a98cf3 | 1328 | g_free(filename); |
f7e4dd6c | 1329 | } |
f7e4dd6c GH |
1330 | } |
1331 | ||
7bc35e0f | 1332 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1333 | { |
1334 | int i; | |
1335 | FWCfgState *fw_cfg; | |
1336 | ||
df1f79fd | 1337 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1338 | |
305ae888 | 1339 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
e3cadac0 | 1340 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
b33a5bbf CL |
1341 | rom_set_fw(fw_cfg); |
1342 | ||
df1f79fd | 1343 | load_linux(pcms, fw_cfg); |
b33a5bbf CL |
1344 | for (i = 0; i < nb_option_roms; i++) { |
1345 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1346 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
b33a5bbf CL |
1347 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1348 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1349 | } | |
f264d360 | 1350 | pcms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1351 | } |
1352 | ||
5934e216 EH |
1353 | void pc_memory_init(PCMachineState *pcms, |
1354 | MemoryRegion *system_memory, | |
1355 | MemoryRegion *rom_memory, | |
1356 | MemoryRegion **ram_memory) | |
80cabfad | 1357 | { |
cbc5b5f3 JJ |
1358 | int linux_boot, i; |
1359 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1360 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1361 | FWCfgState *fw_cfg; |
62b160c0 | 1362 | MachineState *machine = MACHINE(pcms); |
16a9e8a5 | 1363 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
d592d303 | 1364 | |
c8d163bc EH |
1365 | assert(machine->ram_size == pcms->below_4g_mem_size + |
1366 | pcms->above_4g_mem_size); | |
9521d42b PB |
1367 | |
1368 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1369 | |
00cb2a99 | 1370 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1371 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1372 | * with older qemus that used qemu_ram_alloc(). |
1373 | */ | |
7267c094 | 1374 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1375 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1376 | machine->ram_size); | |
ae0a5466 | 1377 | *ram_memory = ram; |
7267c094 | 1378 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1379 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
c8d163bc | 1380 | 0, pcms->below_4g_mem_size); |
00cb2a99 | 1381 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
c8d163bc EH |
1382 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); |
1383 | if (pcms->above_4g_mem_size > 0) { | |
7267c094 | 1384 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1385 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
c8d163bc EH |
1386 | pcms->below_4g_mem_size, |
1387 | pcms->above_4g_mem_size); | |
00cb2a99 AK |
1388 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1389 | ram_above_4g); | |
c8d163bc | 1390 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1391 | } |
82b36dc3 | 1392 | |
bb292f5a | 1393 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1394 | (machine->ram_slots || |
9521d42b | 1395 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1396 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1397 | ||
1398 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1399 | mc->name); | |
1400 | exit(EXIT_FAILURE); | |
1401 | } | |
1402 | ||
619d11e4 | 1403 | /* initialize hotplug memory address space */ |
bb292f5a | 1404 | if (pcmc->has_reserved_memory && |
9521d42b | 1405 | (machine->ram_size < machine->maxram_size)) { |
619d11e4 | 1406 | ram_addr_t hotplug_mem_size = |
9521d42b | 1407 | machine->maxram_size - machine->ram_size; |
619d11e4 | 1408 | |
a0cc8856 IM |
1409 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1410 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1411 | machine->ram_slots); | |
1412 | exit(EXIT_FAILURE); | |
1413 | } | |
1414 | ||
f2c38522 PK |
1415 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1416 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1417 | error_report("maximum memory size must by aligned to multiple of " | |
1418 | "%d bytes", TARGET_PAGE_SIZE); | |
1419 | exit(EXIT_FAILURE); | |
1420 | } | |
1421 | ||
a7d69ff1 | 1422 | pcms->hotplug_memory.base = |
c8d163bc | 1423 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); |
619d11e4 | 1424 | |
16a9e8a5 | 1425 | if (pcmc->enforce_aligned_dimm) { |
085f8e88 IM |
1426 | /* size hotplug region assuming 1G page max alignment per slot */ |
1427 | hotplug_mem_size += (1ULL << 30) * machine->ram_slots; | |
1428 | } | |
1429 | ||
a7d69ff1 | 1430 | if ((pcms->hotplug_memory.base + hotplug_mem_size) < |
619d11e4 IM |
1431 | hotplug_mem_size) { |
1432 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1433 | machine->maxram_size); | |
1434 | exit(EXIT_FAILURE); | |
1435 | } | |
1436 | ||
a7d69ff1 | 1437 | memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), |
619d11e4 | 1438 | "hotplug-memory", hotplug_mem_size); |
a7d69ff1 BR |
1439 | memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, |
1440 | &pcms->hotplug_memory.mr); | |
619d11e4 | 1441 | } |
cbc5b5f3 JJ |
1442 | |
1443 | /* Initialize PC system firmware */ | |
5db3f0de | 1444 | pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); |
00cb2a99 | 1445 | |
7267c094 | 1446 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
49946538 | 1447 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1448 | &error_fatal); |
c5705a77 | 1449 | vmstate_register_ram_global(option_rom_mr); |
4463aee6 | 1450 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1451 | PC_ROM_MIN_VGA, |
1452 | option_rom_mr, | |
1453 | 1); | |
f753ff16 | 1454 | |
ebde2465 | 1455 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); |
c886fc4c | 1456 | |
8832cb80 | 1457 | rom_set_fw(fw_cfg); |
1d108d97 | 1458 | |
bb292f5a | 1459 | if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { |
de268e13 | 1460 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 IM |
1461 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
1462 | uint64_t res_mem_end = pcms->hotplug_memory.base; | |
1463 | ||
1464 | if (!pcmc->broken_reserved_end) { | |
1465 | res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); | |
1466 | } | |
3385e8e2 | 1467 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); |
de268e13 IM |
1468 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1469 | } | |
1470 | ||
f753ff16 | 1471 | if (linux_boot) { |
df1f79fd | 1472 | load_linux(pcms, fw_cfg); |
f753ff16 PB |
1473 | } |
1474 | ||
1475 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1476 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1477 | } |
f264d360 | 1478 | pcms->fw_cfg = fw_cfg; |
cb135f59 PX |
1479 | |
1480 | /* Init default IOAPIC address space */ | |
1481 | pcms->ioapic_as = &address_space_memory; | |
3d53f5c3 IY |
1482 | } |
1483 | ||
0b0cc076 | 1484 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1485 | { |
0b0cc076 | 1486 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1487 | } |
1488 | ||
48a18b3c | 1489 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1490 | { |
ad6d45fa AL |
1491 | DeviceState *dev = NULL; |
1492 | ||
bab47d9a | 1493 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1494 | if (pci_bus) { |
1495 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1496 | dev = pcidev ? &pcidev->qdev : NULL; | |
1497 | } else if (isa_bus) { | |
1498 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1499 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1500 | } |
bab47d9a | 1501 | rom_reset_order_override(); |
ad6d45fa | 1502 | return dev; |
765d7908 IY |
1503 | } |
1504 | ||
258711c6 JG |
1505 | static const MemoryRegionOps ioport80_io_ops = { |
1506 | .write = ioport80_write, | |
c02e1eac | 1507 | .read = ioport80_read, |
258711c6 JG |
1508 | .endianness = DEVICE_NATIVE_ENDIAN, |
1509 | .impl = { | |
1510 | .min_access_size = 1, | |
1511 | .max_access_size = 1, | |
1512 | }, | |
1513 | }; | |
1514 | ||
1515 | static const MemoryRegionOps ioportF0_io_ops = { | |
1516 | .write = ioportF0_write, | |
c02e1eac | 1517 | .read = ioportF0_read, |
258711c6 JG |
1518 | .endianness = DEVICE_NATIVE_ENDIAN, |
1519 | .impl = { | |
1520 | .min_access_size = 1, | |
1521 | .max_access_size = 1, | |
1522 | }, | |
1523 | }; | |
1524 | ||
48a18b3c | 1525 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1526 | ISADevice **rtc_state, |
fd53c87c | 1527 | bool create_fdctrl, |
7a10ef51 | 1528 | bool no_vmport, |
feddd2fd | 1529 | bool has_pit, |
3a87d009 | 1530 | uint32_t hpet_irqs) |
ffe513da IY |
1531 | { |
1532 | int i; | |
1533 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1534 | DeviceState *hpet = NULL; |
1535 | int pit_isa_irq = 0; | |
1536 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1537 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1538 | qemu_irq *a20_line; |
c2d8d311 | 1539 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
258711c6 JG |
1540 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1541 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1542 | |
2c9b15ca | 1543 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1544 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1545 | |
2c9b15ca | 1546 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1547 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1548 | |
5d17c0d2 JK |
1549 | /* |
1550 | * Check if an HPET shall be created. | |
1551 | * | |
1552 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1553 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1554 | */ | |
1555 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1556 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1557 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1558 | if (hpet) { |
7a10ef51 LPF |
1559 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1560 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1561 | * IRQ8 and IRQ2. | |
1562 | */ | |
1563 | uint8_t compat = object_property_get_int(OBJECT(hpet), | |
1564 | HPET_INTCAP, NULL); | |
1565 | if (!compat) { | |
1566 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1567 | } | |
1568 | qdev_init_nofail(hpet); | |
1569 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1570 | ||
b881fbe9 | 1571 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1572 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1573 | } |
ce967e2f JK |
1574 | pit_isa_irq = -1; |
1575 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1576 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1577 | } |
ffe513da | 1578 | } |
48a18b3c | 1579 | *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1580 | |
1581 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1582 | ||
feddd2fd | 1583 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1584 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1585 | pit = kvm_pit_init(isa_bus, 0x40); |
1586 | } else { | |
1587 | pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); | |
1588 | } | |
1589 | if (hpet) { | |
1590 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1591 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1592 | } |
1593 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1594 | } |
ffe513da | 1595 | |
4496dc49 | 1596 | serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); |
07dc7880 | 1597 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
ffe513da | 1598 | |
182735ef | 1599 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1600 | i8042 = isa_create_simple(isa_bus, "i8042"); |
d80fe99d | 1601 | i8042_setup_a20_line(i8042, a20_line[0]); |
1611977c | 1602 | if (!no_vmport) { |
48a18b3c HP |
1603 | vmport_init(isa_bus); |
1604 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1605 | } else { |
1606 | vmmouse = NULL; | |
1607 | } | |
86d86414 | 1608 | if (vmmouse) { |
4a17cc4f AF |
1609 | DeviceState *dev = DEVICE(vmmouse); |
1610 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1611 | qdev_init_nofail(dev); | |
86d86414 | 1612 | } |
48a18b3c | 1613 | port92 = isa_create_simple(isa_bus, "port92"); |
d80fe99d | 1614 | port92_init(port92, a20_line[1]); |
ac64c5fd | 1615 | g_free(a20_line); |
956a3e6b | 1616 | |
57146941 | 1617 | DMA_init(isa_bus, 0); |
ffe513da IY |
1618 | |
1619 | for(i = 0; i < MAX_FD; i++) { | |
1620 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
936a7c1c | 1621 | create_fdctrl |= !!fd[i]; |
ffe513da | 1622 | } |
220a8846 LE |
1623 | if (create_fdctrl) { |
1624 | fdctrl_init_isa(isa_bus, fd); | |
1625 | } | |
ffe513da IY |
1626 | } |
1627 | ||
9011a1a7 IY |
1628 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1629 | { | |
1630 | int i; | |
1631 | ||
bab47d9a | 1632 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1633 | for (i = 0; i < nb_nics; i++) { |
1634 | NICInfo *nd = &nd_table[i]; | |
1635 | ||
1636 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1637 | pc_init_ne2k_isa(isa_bus, nd); | |
1638 | } else { | |
29b358f9 | 1639 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); |
9011a1a7 IY |
1640 | } |
1641 | } | |
bab47d9a | 1642 | rom_reset_order_override(); |
9011a1a7 IY |
1643 | } |
1644 | ||
845773ab | 1645 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1646 | { |
1647 | int max_bus; | |
1648 | int bus; | |
1649 | ||
f778a82f | 1650 | /* Note: if=scsi is deprecated with PC machine types */ |
e3a5cf42 IY |
1651 | max_bus = drive_get_max_bus(IF_SCSI); |
1652 | for (bus = 0; bus <= max_bus; bus++) { | |
f778a82f MA |
1653 | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1654 | /* | |
1655 | * By not creating frontends here, we make | |
1656 | * scsi_legacy_handle_cmdline() create them, and warn that | |
1657 | * this usage is deprecated. | |
1658 | */ | |
e3a5cf42 IY |
1659 | } |
1660 | } | |
a39e3564 JB |
1661 | |
1662 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1663 | { | |
1664 | DeviceState *dev; | |
1665 | SysBusDevice *d; | |
1666 | unsigned int i; | |
1667 | ||
15eafc2e | 1668 | if (kvm_ioapic_in_kernel()) { |
a39e3564 JB |
1669 | dev = qdev_create(NULL, "kvm-ioapic"); |
1670 | } else { | |
1671 | dev = qdev_create(NULL, "ioapic"); | |
1672 | } | |
1673 | if (parent_name) { | |
1674 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1675 | "ioapic", OBJECT(dev), NULL); | |
1676 | } | |
1677 | qdev_init_nofail(dev); | |
1356b98d | 1678 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1679 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1680 | |
1681 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1682 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1683 | } | |
1684 | } | |
d5747cac | 1685 | |
95bee274 IM |
1686 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, |
1687 | DeviceState *dev, Error **errp) | |
1688 | { | |
3fbcdc27 | 1689 | HotplugHandlerClass *hhc; |
95bee274 IM |
1690 | Error *local_err = NULL; |
1691 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
16a9e8a5 | 1692 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
95bee274 IM |
1693 | PCDIMMDevice *dimm = PC_DIMM(dev); |
1694 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1695 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
92a37a04 | 1696 | uint64_t align = TARGET_PAGE_SIZE; |
95bee274 | 1697 | |
16a9e8a5 | 1698 | if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { |
91aa70ab IM |
1699 | align = memory_region_get_alignment(mr); |
1700 | } | |
1701 | ||
3fbcdc27 IM |
1702 | if (!pcms->acpi_dev) { |
1703 | error_setg(&local_err, | |
1704 | "memory hotplug is not enabled: missing acpi device"); | |
1705 | goto out; | |
1706 | } | |
1707 | ||
d6a9b0b8 | 1708 | pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); |
43bbb49e | 1709 | if (local_err) { |
b8865591 IM |
1710 | goto out; |
1711 | } | |
1712 | ||
c7f8d0f3 | 1713 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
e987c37a HZ |
1714 | if (!pcms->acpi_nvdimm_state.is_enabled) { |
1715 | error_setg(&local_err, | |
1716 | "nvdimm is not enabled: missing 'nvdimm' in '-M'"); | |
1717 | goto out; | |
1718 | } | |
284197e4 | 1719 | nvdimm_plug(&pcms->acpi_nvdimm_state); |
c7f8d0f3 XG |
1720 | } |
1721 | ||
3fbcdc27 | 1722 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
8e23184b | 1723 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1724 | out: |
1725 | error_propagate(errp, local_err); | |
1726 | } | |
1727 | ||
64fec58e TC |
1728 | static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, |
1729 | DeviceState *dev, Error **errp) | |
1730 | { | |
1731 | HotplugHandlerClass *hhc; | |
1732 | Error *local_err = NULL; | |
1733 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1734 | ||
1735 | if (!pcms->acpi_dev) { | |
1736 | error_setg(&local_err, | |
1737 | "memory hotplug is not enabled: missing acpi device"); | |
1738 | goto out; | |
1739 | } | |
1740 | ||
b097cc52 XG |
1741 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1742 | error_setg(&local_err, | |
1743 | "nvdimm device hot unplug is not supported yet."); | |
1744 | goto out; | |
1745 | } | |
1746 | ||
64fec58e TC |
1747 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1748 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1749 | ||
1750 | out: | |
1751 | error_propagate(errp, local_err); | |
1752 | } | |
1753 | ||
f7d3e29d TC |
1754 | static void pc_dimm_unplug(HotplugHandler *hotplug_dev, |
1755 | DeviceState *dev, Error **errp) | |
1756 | { | |
1757 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1758 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
1759 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
1760 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
1761 | HotplugHandlerClass *hhc; | |
1762 | Error *local_err = NULL; | |
1763 | ||
1764 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1765 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1766 | ||
1767 | if (local_err) { | |
1768 | goto out; | |
1769 | } | |
1770 | ||
43bbb49e | 1771 | pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); |
f7d3e29d TC |
1772 | object_unparent(OBJECT(dev)); |
1773 | ||
1774 | out: | |
1775 | error_propagate(errp, local_err); | |
1776 | } | |
1777 | ||
3811ef14 IM |
1778 | static int pc_apic_cmp(const void *a, const void *b) |
1779 | { | |
1780 | CPUArchId *apic_a = (CPUArchId *)a; | |
1781 | CPUArchId *apic_b = (CPUArchId *)b; | |
1782 | ||
1783 | return apic_a->arch_id - apic_b->arch_id; | |
1784 | } | |
1785 | ||
7baef5cf | 1786 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1787 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1788 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1789 | */ |
1ea69c0e | 1790 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1791 | { |
7baef5cf IM |
1792 | CPUArchId apic_id, *found_cpu; |
1793 | ||
1ea69c0e | 1794 | apic_id.arch_id = id; |
38690a1c IM |
1795 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1796 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1797 | pc_apic_cmp); |
1798 | if (found_cpu && idx) { | |
38690a1c | 1799 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1800 | } |
1801 | return found_cpu; | |
1802 | } | |
1803 | ||
5279569e GZ |
1804 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1805 | DeviceState *dev, Error **errp) | |
1806 | { | |
7baef5cf | 1807 | CPUArchId *found_cpu; |
5279569e GZ |
1808 | HotplugHandlerClass *hhc; |
1809 | Error *local_err = NULL; | |
1ea69c0e | 1810 | X86CPU *cpu = X86_CPU(dev); |
5279569e GZ |
1811 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1812 | ||
a44a49db IM |
1813 | if (pcms->acpi_dev) { |
1814 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1815 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1816 | if (local_err) { | |
1817 | goto out; | |
1818 | } | |
5279569e GZ |
1819 | } |
1820 | ||
e3cadac0 IM |
1821 | /* increment the number of CPUs */ |
1822 | pcms->boot_cpus++; | |
26ef65be | 1823 | if (pcms->rtc) { |
e3cadac0 | 1824 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); |
26ef65be IM |
1825 | } |
1826 | if (pcms->fw_cfg) { | |
e3cadac0 | 1827 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
2d996150 GZ |
1828 | } |
1829 | ||
1ea69c0e | 1830 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1831 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1832 | out: |
1833 | error_propagate(errp, local_err); | |
1834 | } | |
8872c25a IM |
1835 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1836 | DeviceState *dev, Error **errp) | |
1837 | { | |
73360e27 | 1838 | int idx = -1; |
8872c25a IM |
1839 | HotplugHandlerClass *hhc; |
1840 | Error *local_err = NULL; | |
1ea69c0e | 1841 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1842 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1843 | ||
1ea69c0e | 1844 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
1845 | assert(idx != -1); |
1846 | if (idx == 0) { | |
1847 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1848 | goto out; | |
1849 | } | |
1850 | ||
8872c25a IM |
1851 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1852 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1853 | ||
1854 | if (local_err) { | |
1855 | goto out; | |
1856 | } | |
1857 | ||
1858 | out: | |
1859 | error_propagate(errp, local_err); | |
1860 | ||
1861 | } | |
1862 | ||
1863 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1864 | DeviceState *dev, Error **errp) | |
1865 | { | |
8fe6374e | 1866 | CPUArchId *found_cpu; |
8872c25a IM |
1867 | HotplugHandlerClass *hhc; |
1868 | Error *local_err = NULL; | |
1ea69c0e | 1869 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1870 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1871 | ||
1872 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1873 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1874 | ||
1875 | if (local_err) { | |
1876 | goto out; | |
1877 | } | |
1878 | ||
1ea69c0e | 1879 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e IM |
1880 | found_cpu->cpu = NULL; |
1881 | object_unparent(OBJECT(dev)); | |
8872c25a | 1882 | |
e3cadac0 IM |
1883 | /* decrement the number of CPUs */ |
1884 | pcms->boot_cpus--; | |
1885 | /* Update the number of CPUs in CMOS */ | |
1886 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
1887 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
8872c25a IM |
1888 | out: |
1889 | error_propagate(errp, local_err); | |
1890 | } | |
5279569e | 1891 | |
4ec60c76 IM |
1892 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1893 | DeviceState *dev, Error **errp) | |
1894 | { | |
1895 | int idx; | |
93b2a8cb | 1896 | int node_id; |
a15d2728 | 1897 | CPUState *cs; |
e8f7b83e | 1898 | CPUArchId *cpu_slot; |
d89c2b8b | 1899 | X86CPUTopoInfo topo; |
4ec60c76 IM |
1900 | X86CPU *cpu = X86_CPU(dev); |
1901 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
4ec60c76 | 1902 | |
e8f7b83e IM |
1903 | /* if APIC ID is not set, set it based on socket/core/thread properties */ |
1904 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
1905 | int max_socket = (max_cpus - 1) / smp_threads / smp_cores; | |
1906 | ||
1907 | if (cpu->socket_id < 0) { | |
1908 | error_setg(errp, "CPU socket-id is not set"); | |
1909 | return; | |
1910 | } else if (cpu->socket_id > max_socket) { | |
1911 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1912 | cpu->socket_id, max_socket); | |
1913 | return; | |
1914 | } | |
1915 | if (cpu->core_id < 0) { | |
1916 | error_setg(errp, "CPU core-id is not set"); | |
1917 | return; | |
1918 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1919 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1920 | cpu->core_id, smp_cores - 1); | |
1921 | return; | |
1922 | } | |
1923 | if (cpu->thread_id < 0) { | |
1924 | error_setg(errp, "CPU thread-id is not set"); | |
1925 | return; | |
1926 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1927 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1928 | cpu->thread_id, smp_threads - 1); | |
1929 | return; | |
1930 | } | |
1931 | ||
1932 | topo.pkg_id = cpu->socket_id; | |
1933 | topo.core_id = cpu->core_id; | |
1934 | topo.smt_id = cpu->thread_id; | |
1935 | cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); | |
1936 | } | |
1937 | ||
1ea69c0e | 1938 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 1939 | if (!cpu_slot) { |
38690a1c IM |
1940 | MachineState *ms = MACHINE(pcms); |
1941 | ||
e8f7b83e IM |
1942 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); |
1943 | error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" | |
1944 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1945 | topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, | |
38690a1c | 1946 | ms->possible_cpus->len - 1); |
4ec60c76 IM |
1947 | return; |
1948 | } | |
1949 | ||
1950 | if (cpu_slot->cpu) { | |
1951 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1952 | idx, cpu->apic_id); | |
1953 | return; | |
1954 | } | |
d89c2b8b IM |
1955 | |
1956 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 1957 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
1958 | */ |
1959 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1960 | * once -smp refactoring is complete and there will be CPU private | |
1961 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
1962 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
1963 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
1964 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1965 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1966 | return; | |
1967 | } | |
1968 | cpu->socket_id = topo.pkg_id; | |
1969 | ||
1970 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
1971 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1972 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1973 | return; | |
1974 | } | |
1975 | cpu->core_id = topo.core_id; | |
1976 | ||
1977 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
1978 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
1979 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
1980 | return; | |
1981 | } | |
1982 | cpu->thread_id = topo.smt_id; | |
a15d2728 IM |
1983 | |
1984 | cs = CPU(cpu); | |
1985 | cs->cpu_index = idx; | |
93b2a8cb | 1986 | |
ea265072 IM |
1987 | node_id = cpu_slot->props.node_id; |
1988 | if (!cpu_slot->props.has_node_id) { | |
93b2a8cb IM |
1989 | /* by default CPUState::numa_node was 0 if it's not set via CLI |
1990 | * keep it this way for now but in future we probably should | |
1991 | * refuse to start up with incomplete numa mapping */ | |
1992 | node_id = 0; | |
1993 | } | |
1994 | if (cs->numa_node == CPU_UNSET_NUMA_NODE_ID) { | |
1995 | cs->numa_node = node_id; | |
1996 | } else if (cs->numa_node != node_id) { | |
1997 | error_setg(errp, "node-id %d must match numa node specified" | |
1998 | "with -numa option for cpu-index %d", | |
1999 | cs->numa_node, cs->cpu_index); | |
2000 | return; | |
2001 | } | |
4ec60c76 IM |
2002 | } |
2003 | ||
2004 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
2005 | DeviceState *dev, Error **errp) | |
2006 | { | |
2007 | if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2008 | pc_cpu_pre_plug(hotplug_dev, dev, errp); | |
2009 | } | |
2010 | } | |
2011 | ||
95bee274 IM |
2012 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
2013 | DeviceState *dev, Error **errp) | |
2014 | { | |
2015 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2016 | pc_dimm_plug(hotplug_dev, dev, errp); | |
5279569e GZ |
2017 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2018 | pc_cpu_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
2019 | } |
2020 | } | |
2021 | ||
d9c5c5b8 TC |
2022 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
2023 | DeviceState *dev, Error **errp) | |
2024 | { | |
64fec58e TC |
2025 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2026 | pc_dimm_unplug_request(hotplug_dev, dev, errp); | |
8872c25a IM |
2027 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2028 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
64fec58e TC |
2029 | } else { |
2030 | error_setg(errp, "acpi: device unplug request for not supported device" | |
2031 | " type: %s", object_get_typename(OBJECT(dev))); | |
2032 | } | |
d9c5c5b8 TC |
2033 | } |
2034 | ||
232391c1 TC |
2035 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
2036 | DeviceState *dev, Error **errp) | |
2037 | { | |
f7d3e29d TC |
2038 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2039 | pc_dimm_unplug(hotplug_dev, dev, errp); | |
8872c25a IM |
2040 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2041 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
f7d3e29d TC |
2042 | } else { |
2043 | error_setg(errp, "acpi: device unplug for not supported device" | |
2044 | " type: %s", object_get_typename(OBJECT(dev))); | |
2045 | } | |
232391c1 TC |
2046 | } |
2047 | ||
95bee274 IM |
2048 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, |
2049 | DeviceState *dev) | |
2050 | { | |
2051 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
2052 | ||
5279569e GZ |
2053 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2054 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
95bee274 IM |
2055 | return HOTPLUG_HANDLER(machine); |
2056 | } | |
2057 | ||
2058 | return pcmc->get_hotplug_handler ? | |
2059 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
2060 | } | |
2061 | ||
bf1e8939 | 2062 | static void |
d7bce999 EB |
2063 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, |
2064 | const char *name, void *opaque, | |
2065 | Error **errp) | |
bf1e8939 IM |
2066 | { |
2067 | PCMachineState *pcms = PC_MACHINE(obj); | |
a7d69ff1 | 2068 | int64_t value = memory_region_size(&pcms->hotplug_memory.mr); |
bf1e8939 | 2069 | |
51e72bc1 | 2070 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2071 | } |
2072 | ||
c87b1520 | 2073 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
d7bce999 EB |
2074 | const char *name, void *opaque, |
2075 | Error **errp) | |
c87b1520 DS |
2076 | { |
2077 | PCMachineState *pcms = PC_MACHINE(obj); | |
2078 | uint64_t value = pcms->max_ram_below_4g; | |
2079 | ||
51e72bc1 | 2080 | visit_type_size(v, name, &value, errp); |
c87b1520 DS |
2081 | } |
2082 | ||
2083 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
d7bce999 EB |
2084 | const char *name, void *opaque, |
2085 | Error **errp) | |
c87b1520 DS |
2086 | { |
2087 | PCMachineState *pcms = PC_MACHINE(obj); | |
2088 | Error *error = NULL; | |
2089 | uint64_t value; | |
2090 | ||
51e72bc1 | 2091 | visit_type_size(v, name, &value, &error); |
c87b1520 DS |
2092 | if (error) { |
2093 | error_propagate(errp, error); | |
2094 | return; | |
2095 | } | |
2096 | if (value > (1ULL << 32)) { | |
455b0fde EB |
2097 | error_setg(&error, |
2098 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2099 | "' expects size less than or equal to 4G", value); | |
c87b1520 DS |
2100 | error_propagate(errp, error); |
2101 | return; | |
2102 | } | |
2103 | ||
2104 | if (value < (1ULL << 20)) { | |
2105 | error_report("Warning: small max_ram_below_4g(%"PRIu64 | |
2106 | ") less than 1M. BIOS may not work..", | |
2107 | value); | |
2108 | } | |
2109 | ||
2110 | pcms->max_ram_below_4g = value; | |
2111 | } | |
2112 | ||
d7bce999 EB |
2113 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2114 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2115 | { |
2116 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2117 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2118 | |
51e72bc1 | 2119 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2120 | } |
2121 | ||
d7bce999 EB |
2122 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2123 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2124 | { |
2125 | PCMachineState *pcms = PC_MACHINE(obj); | |
2126 | ||
51e72bc1 | 2127 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2128 | } |
2129 | ||
355023f2 PB |
2130 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) |
2131 | { | |
2132 | bool smm_available = false; | |
2133 | ||
2134 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2135 | return false; | |
2136 | } | |
2137 | ||
2138 | if (tcg_enabled() || qtest_enabled()) { | |
2139 | smm_available = true; | |
2140 | } else if (kvm_enabled()) { | |
2141 | smm_available = kvm_has_smm(); | |
2142 | } | |
2143 | ||
2144 | if (smm_available) { | |
2145 | return true; | |
2146 | } | |
2147 | ||
2148 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2149 | error_report("System Management Mode not supported by this hypervisor."); | |
2150 | exit(1); | |
2151 | } | |
2152 | return false; | |
2153 | } | |
2154 | ||
d7bce999 EB |
2155 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, |
2156 | void *opaque, Error **errp) | |
355023f2 PB |
2157 | { |
2158 | PCMachineState *pcms = PC_MACHINE(obj); | |
2159 | OnOffAuto smm = pcms->smm; | |
2160 | ||
51e72bc1 | 2161 | visit_type_OnOffAuto(v, name, &smm, errp); |
355023f2 PB |
2162 | } |
2163 | ||
d7bce999 EB |
2164 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, |
2165 | void *opaque, Error **errp) | |
355023f2 PB |
2166 | { |
2167 | PCMachineState *pcms = PC_MACHINE(obj); | |
2168 | ||
51e72bc1 | 2169 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); |
355023f2 PB |
2170 | } |
2171 | ||
87252e1b XG |
2172 | static bool pc_machine_get_nvdimm(Object *obj, Error **errp) |
2173 | { | |
2174 | PCMachineState *pcms = PC_MACHINE(obj); | |
2175 | ||
5fe79386 | 2176 | return pcms->acpi_nvdimm_state.is_enabled; |
87252e1b XG |
2177 | } |
2178 | ||
2179 | static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
2180 | { | |
2181 | PCMachineState *pcms = PC_MACHINE(obj); | |
2182 | ||
5fe79386 | 2183 | pcms->acpi_nvdimm_state.is_enabled = value; |
87252e1b XG |
2184 | } |
2185 | ||
be232eb0 CP |
2186 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
2187 | { | |
2188 | PCMachineState *pcms = PC_MACHINE(obj); | |
2189 | ||
2190 | return pcms->smbus; | |
2191 | } | |
2192 | ||
2193 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2194 | { | |
2195 | PCMachineState *pcms = PC_MACHINE(obj); | |
2196 | ||
2197 | pcms->smbus = value; | |
2198 | } | |
2199 | ||
272f0428 CP |
2200 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
2201 | { | |
2202 | PCMachineState *pcms = PC_MACHINE(obj); | |
2203 | ||
2204 | return pcms->sata; | |
2205 | } | |
2206 | ||
2207 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2208 | { | |
2209 | PCMachineState *pcms = PC_MACHINE(obj); | |
2210 | ||
2211 | pcms->sata = value; | |
2212 | } | |
2213 | ||
feddd2fd CP |
2214 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
2215 | { | |
2216 | PCMachineState *pcms = PC_MACHINE(obj); | |
2217 | ||
2218 | return pcms->pit; | |
2219 | } | |
2220 | ||
2221 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2222 | { | |
2223 | PCMachineState *pcms = PC_MACHINE(obj); | |
2224 | ||
2225 | pcms->pit = value; | |
2226 | } | |
2227 | ||
bf1e8939 IM |
2228 | static void pc_machine_initfn(Object *obj) |
2229 | { | |
c87b1520 DS |
2230 | PCMachineState *pcms = PC_MACHINE(obj); |
2231 | ||
5ec7d098 | 2232 | pcms->max_ram_below_4g = 0; /* use default */ |
355023f2 | 2233 | pcms->smm = ON_OFF_AUTO_AUTO; |
d1048bef | 2234 | pcms->vmport = ON_OFF_AUTO_AUTO; |
87252e1b | 2235 | /* nvdimm is disabled on default. */ |
5fe79386 | 2236 | pcms->acpi_nvdimm_state.is_enabled = false; |
021746c1 WL |
2237 | /* acpi build is enabled by default if machine supports it */ |
2238 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
be232eb0 | 2239 | pcms->smbus = true; |
272f0428 | 2240 | pcms->sata = true; |
feddd2fd | 2241 | pcms->pit = true; |
bf1e8939 IM |
2242 | } |
2243 | ||
ae50c55a ZG |
2244 | static void pc_machine_reset(void) |
2245 | { | |
2246 | CPUState *cs; | |
2247 | X86CPU *cpu; | |
2248 | ||
2249 | qemu_devices_reset(); | |
2250 | ||
2251 | /* Reset APIC after devices have been reset to cancel | |
2252 | * any changes that qemu_devices_reset() might have done. | |
2253 | */ | |
2254 | CPU_FOREACH(cs) { | |
2255 | cpu = X86_CPU(cs); | |
2256 | ||
2257 | if (cpu->apic_state) { | |
2258 | device_reset(cpu->apic_state); | |
2259 | } | |
2260 | } | |
2261 | } | |
2262 | ||
ea089eeb IM |
2263 | static CpuInstanceProperties |
2264 | pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
fb43b73b | 2265 | { |
ea089eeb IM |
2266 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
2267 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
2268 | ||
2269 | assert(cpu_index < possible_cpus->len); | |
2270 | return possible_cpus->cpus[cpu_index].props; | |
fb43b73b IM |
2271 | } |
2272 | ||
c96a1c0b | 2273 | static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) |
3811ef14 | 2274 | { |
c96a1c0b IM |
2275 | int i; |
2276 | ||
2277 | if (ms->possible_cpus) { | |
2278 | /* | |
2279 | * make sure that max_cpus hasn't changed since the first use, i.e. | |
2280 | * -smp hasn't been parsed after it | |
2281 | */ | |
2282 | assert(ms->possible_cpus->len == max_cpus); | |
2283 | return ms->possible_cpus; | |
2284 | } | |
2285 | ||
2286 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
2287 | sizeof(CPUArchId) * max_cpus); | |
2288 | ms->possible_cpus->len = max_cpus; | |
2289 | for (i = 0; i < ms->possible_cpus->len; i++) { | |
c67ae933 IM |
2290 | X86CPUTopoInfo topo; |
2291 | ||
f2d672c2 | 2292 | ms->possible_cpus->cpus[i].vcpus_count = 1; |
c96a1c0b | 2293 | ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); |
c67ae933 IM |
2294 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, |
2295 | smp_cores, smp_threads, &topo); | |
2296 | ms->possible_cpus->cpus[i].props.has_socket_id = true; | |
2297 | ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; | |
2298 | ms->possible_cpus->cpus[i].props.has_core_id = true; | |
2299 | ms->possible_cpus->cpus[i].props.core_id = topo.core_id; | |
2300 | ms->possible_cpus->cpus[i].props.has_thread_id = true; | |
2301 | ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; | |
ea089eeb IM |
2302 | |
2303 | /* default distribution of CPUs over NUMA nodes */ | |
2304 | if (nb_numa_nodes) { | |
2305 | /* preset values but do not enable them i.e. 'has_node_id = false', | |
2306 | * numa init code will enable them later if manual mapping wasn't | |
2307 | * present on CLI */ | |
2308 | ms->possible_cpus->cpus[i].props.node_id = | |
2309 | topo.pkg_id % nb_numa_nodes; | |
2310 | } | |
c96a1c0b IM |
2311 | } |
2312 | return ms->possible_cpus; | |
3811ef14 IM |
2313 | } |
2314 | ||
1255166b BD |
2315 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) |
2316 | { | |
2317 | /* cpu index isn't used */ | |
2318 | CPUState *cs; | |
2319 | ||
2320 | CPU_FOREACH(cs) { | |
2321 | X86CPU *cpu = X86_CPU(cs); | |
2322 | ||
2323 | if (!cpu->apic_state) { | |
2324 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2325 | } else { | |
2326 | apic_deliver_nmi(cpu->apic_state); | |
2327 | } | |
2328 | } | |
2329 | } | |
2330 | ||
95bee274 IM |
2331 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2332 | { | |
2333 | MachineClass *mc = MACHINE_CLASS(oc); | |
2334 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2335 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1255166b | 2336 | NMIClass *nc = NMI_CLASS(oc); |
95bee274 IM |
2337 | |
2338 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
7102fa70 EH |
2339 | pcmc->pci_enabled = true; |
2340 | pcmc->has_acpi_build = true; | |
2341 | pcmc->rsdp_in_ram = true; | |
2342 | pcmc->smbios_defaults = true; | |
2343 | pcmc->smbios_uuid_encoded = true; | |
2344 | pcmc->gigabyte_align = true; | |
2345 | pcmc->has_reserved_memory = true; | |
2346 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2347 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2348 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2349 | * to be used at the moment, 32K should be enough for a while. */ | |
2350 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
36f96c4b | 2351 | pcmc->save_tsc_khz = true; |
98e753a6 | 2352 | pcmc->linuxboot_dma_enabled = true; |
95bee274 | 2353 | mc->get_hotplug_handler = pc_get_hotpug_handler; |
ea089eeb | 2354 | mc->cpu_index_to_instance_props = pc_cpu_index_to_props; |
3811ef14 | 2355 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; |
c5514d0e | 2356 | mc->has_hotpluggable_cpus = true; |
41742767 | 2357 | mc->default_boot_order = "cad"; |
4458fb3a | 2358 | mc->hot_add_cpu = pc_hot_add_cpu; |
2059839b | 2359 | mc->block_default_type = IF_IDE; |
4458fb3a | 2360 | mc->max_cpus = 255; |
ae50c55a | 2361 | mc->reset = pc_machine_reset; |
4ec60c76 | 2362 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2363 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2364 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2365 | hc->unplug = pc_machine_device_unplug_cb; |
1255166b | 2366 | nc->nmi_monitor_handler = x86_nmi; |
0efc257d EH |
2367 | |
2368 | object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", | |
2369 | pc_machine_get_hotplug_memory_region_size, NULL, | |
2370 | NULL, NULL, &error_abort); | |
2371 | ||
2372 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2373 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
2374 | NULL, NULL, &error_abort); | |
2375 | ||
2376 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2377 | "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); | |
2378 | ||
2379 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", | |
2380 | pc_machine_get_smm, pc_machine_set_smm, | |
2381 | NULL, NULL, &error_abort); | |
2382 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2383 | "Enable SMM (pc & q35)", &error_abort); | |
2384 | ||
2385 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2386 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2387 | NULL, NULL, &error_abort); | |
2388 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2389 | "Enable vmport (pc & q35)", &error_abort); | |
2390 | ||
2391 | object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, | |
2392 | pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); | |
be232eb0 CP |
2393 | |
2394 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, | |
2395 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
2396 | |
2397 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2398 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
2399 | |
2400 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2401 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
2402 | } |
2403 | ||
d5747cac IM |
2404 | static const TypeInfo pc_machine_info = { |
2405 | .name = TYPE_PC_MACHINE, | |
2406 | .parent = TYPE_MACHINE, | |
2407 | .abstract = true, | |
2408 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2409 | .instance_init = pc_machine_initfn, |
d5747cac | 2410 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2411 | .class_init = pc_machine_class_init, |
2412 | .interfaces = (InterfaceInfo[]) { | |
2413 | { TYPE_HOTPLUG_HANDLER }, | |
1255166b | 2414 | { TYPE_NMI }, |
95bee274 IM |
2415 | { } |
2416 | }, | |
d5747cac IM |
2417 | }; |
2418 | ||
2419 | static void pc_machine_register_types(void) | |
2420 | { | |
2421 | type_register_static(&pc_machine_info); | |
2422 | } | |
2423 | ||
2424 | type_init(pc_machine_register_types) |