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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC System Emulator | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
83c9f4ca | 26 | #include "hw/hw.h" |
0d09e41a PB |
27 | #include "hw/i386/pc.h" |
28 | #include "hw/char/serial.h" | |
29 | #include "hw/i386/apic.h" | |
54a40293 EH |
30 | #include "hw/i386/topology.h" |
31 | #include "sysemu/cpus.h" | |
0d09e41a | 32 | #include "hw/block/fdc.h" |
83c9f4ca PB |
33 | #include "hw/ide.h" |
34 | #include "hw/pci/pci.h" | |
2118196b | 35 | #include "hw/pci/pci_bus.h" |
0d09e41a PB |
36 | #include "hw/nvram/fw_cfg.h" |
37 | #include "hw/timer/hpet.h" | |
60d8f328 | 38 | #include "hw/smbios/smbios.h" |
83c9f4ca | 39 | #include "hw/loader.h" |
ca20cf32 | 40 | #include "elf.h" |
47b43a1f | 41 | #include "multiboot.h" |
0d09e41a PB |
42 | #include "hw/timer/mc146818rtc.h" |
43 | #include "hw/timer/i8254.h" | |
44 | #include "hw/audio/pcspk.h" | |
83c9f4ca PB |
45 | #include "hw/pci/msi.h" |
46 | #include "hw/sysbus.h" | |
9c17d615 | 47 | #include "sysemu/sysemu.h" |
e35704ba | 48 | #include "sysemu/numa.h" |
9c17d615 | 49 | #include "sysemu/kvm.h" |
b1c12027 | 50 | #include "sysemu/qtest.h" |
1d31f66b | 51 | #include "kvm_i386.h" |
0d09e41a | 52 | #include "hw/xen/xen.h" |
4be74634 | 53 | #include "sysemu/block-backend.h" |
0d09e41a | 54 | #include "hw/block/block.h" |
a19cbfb3 | 55 | #include "ui/qemu-spice.h" |
022c62cb PB |
56 | #include "exec/memory.h" |
57 | #include "exec/address-spaces.h" | |
9c17d615 | 58 | #include "sysemu/arch_init.h" |
1de7afc9 | 59 | #include "qemu/bitmap.h" |
0c764a9d | 60 | #include "qemu/config-file.h" |
d49b6836 | 61 | #include "qemu/error-report.h" |
0445259b | 62 | #include "hw/acpi/acpi.h" |
5ff020b7 | 63 | #include "hw/acpi/cpu_hotplug.h" |
c649983b | 64 | #include "hw/boards.h" |
39848901 | 65 | #include "hw/pci/pci_host.h" |
72c194f7 | 66 | #include "acpi-build.h" |
95bee274 | 67 | #include "hw/mem/pc-dimm.h" |
e688df6b | 68 | #include "qapi/error.h" |
bf1e8939 | 69 | #include "qapi/visitor.h" |
d1048bef | 70 | #include "qapi-visit.h" |
15eafc2e | 71 | #include "qom/cpu.h" |
1255166b | 72 | #include "hw/nmi.h" |
60c5e104 | 73 | #include "hw/i386/intel_iommu.h" |
489983d6 | 74 | #include "hw/net/ne2000-isa.h" |
80cabfad | 75 | |
471fd342 BS |
76 | /* debug PC/ISA interrupts */ |
77 | //#define DEBUG_IRQ | |
78 | ||
79 | #ifdef DEBUG_IRQ | |
80 | #define DPRINTF(fmt, ...) \ | |
81 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
82 | #else | |
83 | #define DPRINTF(fmt, ...) | |
84 | #endif | |
85 | ||
8a92ea2f | 86 | #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
b6f6e3d3 | 87 | #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
6b35e7bf | 88 | #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
4c5b10b7 | 89 | #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
40ac17cd | 90 | #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
80cabfad | 91 | |
4c5b10b7 JS |
92 | #define E820_NR_ENTRIES 16 |
93 | ||
94 | struct e820_entry { | |
95 | uint64_t address; | |
96 | uint64_t length; | |
97 | uint32_t type; | |
541dc0d4 | 98 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 JS |
99 | |
100 | struct e820_table { | |
101 | uint32_t count; | |
102 | struct e820_entry entry[E820_NR_ENTRIES]; | |
541dc0d4 | 103 | } QEMU_PACKED __attribute((__aligned__(4))); |
4c5b10b7 | 104 | |
7d67110f GH |
105 | static struct e820_table e820_reserve; |
106 | static struct e820_entry *e820_table; | |
107 | static unsigned e820_entries; | |
dd703b99 | 108 | struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; |
4c5b10b7 | 109 | |
b881fbe9 | 110 | void gsi_handler(void *opaque, int n, int level) |
1452411b | 111 | { |
b881fbe9 | 112 | GSIState *s = opaque; |
1452411b | 113 | |
b881fbe9 JK |
114 | DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); |
115 | if (n < ISA_NUM_IRQS) { | |
116 | qemu_set_irq(s->i8259_irq[n], level); | |
1632dc6a | 117 | } |
b881fbe9 | 118 | qemu_set_irq(s->ioapic_irq[n], level); |
2e9947d2 | 119 | } |
1452411b | 120 | |
258711c6 JG |
121 | static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, |
122 | unsigned size) | |
80cabfad FB |
123 | { |
124 | } | |
125 | ||
c02e1eac JG |
126 | static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) |
127 | { | |
a6fc23e5 | 128 | return 0xffffffffffffffffULL; |
c02e1eac JG |
129 | } |
130 | ||
f929aad6 | 131 | /* MSDOS compatibility mode FPU exception support */ |
d537cf6c | 132 | static qemu_irq ferr_irq; |
8e78eb28 IY |
133 | |
134 | void pc_register_ferr_irq(qemu_irq irq) | |
135 | { | |
136 | ferr_irq = irq; | |
137 | } | |
138 | ||
f929aad6 FB |
139 | /* XXX: add IGNNE support */ |
140 | void cpu_set_ferr(CPUX86State *s) | |
141 | { | |
d537cf6c | 142 | qemu_irq_raise(ferr_irq); |
f929aad6 FB |
143 | } |
144 | ||
258711c6 JG |
145 | static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, |
146 | unsigned size) | |
f929aad6 | 147 | { |
d537cf6c | 148 | qemu_irq_lower(ferr_irq); |
f929aad6 FB |
149 | } |
150 | ||
c02e1eac JG |
151 | static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) |
152 | { | |
a6fc23e5 | 153 | return 0xffffffffffffffffULL; |
c02e1eac JG |
154 | } |
155 | ||
28ab0e2e | 156 | /* TSC handling */ |
28ab0e2e FB |
157 | uint64_t cpu_get_tsc(CPUX86State *env) |
158 | { | |
4a1418e0 | 159 | return cpu_get_ticks(); |
28ab0e2e FB |
160 | } |
161 | ||
3de388f6 | 162 | /* IRQ handling */ |
4a8fa5dc | 163 | int cpu_get_pic_interrupt(CPUX86State *env) |
3de388f6 | 164 | { |
02e51483 | 165 | X86CPU *cpu = x86_env_get_cpu(env); |
3de388f6 FB |
166 | int intno; |
167 | ||
bb93e099 WL |
168 | if (!kvm_irqchip_in_kernel()) { |
169 | intno = apic_get_interrupt(cpu->apic_state); | |
170 | if (intno >= 0) { | |
171 | return intno; | |
172 | } | |
173 | /* read the irq from the PIC */ | |
174 | if (!apic_accept_pic_intr(cpu->apic_state)) { | |
175 | return -1; | |
176 | } | |
cf6d64bf | 177 | } |
0e21e12b | 178 | |
3de388f6 FB |
179 | intno = pic_read_irq(isa_pic); |
180 | return intno; | |
181 | } | |
182 | ||
d537cf6c | 183 | static void pic_irq_request(void *opaque, int irq, int level) |
3de388f6 | 184 | { |
182735ef AF |
185 | CPUState *cs = first_cpu; |
186 | X86CPU *cpu = X86_CPU(cs); | |
a5b38b51 | 187 | |
471fd342 | 188 | DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
bb93e099 | 189 | if (cpu->apic_state && !kvm_irqchip_in_kernel()) { |
bdc44640 | 190 | CPU_FOREACH(cs) { |
182735ef | 191 | cpu = X86_CPU(cs); |
02e51483 CF |
192 | if (apic_accept_pic_intr(cpu->apic_state)) { |
193 | apic_deliver_pic_intr(cpu->apic_state, level); | |
cf6d64bf | 194 | } |
d5529471 AJ |
195 | } |
196 | } else { | |
d8ed887b | 197 | if (level) { |
c3affe56 | 198 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
d8ed887b AF |
199 | } else { |
200 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
201 | } | |
a5b38b51 | 202 | } |
3de388f6 FB |
203 | } |
204 | ||
b0a21b53 FB |
205 | /* PC cmos mappings */ |
206 | ||
80cabfad FB |
207 | #define REG_EQUIPMENT_BYTE 0x14 |
208 | ||
bda05509 | 209 | int cmos_get_fd_drive_type(FloppyDriveType fd0) |
777428f2 FB |
210 | { |
211 | int val; | |
212 | ||
213 | switch (fd0) { | |
2da44dd0 | 214 | case FLOPPY_DRIVE_TYPE_144: |
777428f2 FB |
215 | /* 1.44 Mb 3"5 drive */ |
216 | val = 4; | |
217 | break; | |
2da44dd0 | 218 | case FLOPPY_DRIVE_TYPE_288: |
777428f2 FB |
219 | /* 2.88 Mb 3"5 drive */ |
220 | val = 5; | |
221 | break; | |
2da44dd0 | 222 | case FLOPPY_DRIVE_TYPE_120: |
777428f2 FB |
223 | /* 1.2 Mb 5"5 drive */ |
224 | val = 2; | |
225 | break; | |
2da44dd0 | 226 | case FLOPPY_DRIVE_TYPE_NONE: |
777428f2 FB |
227 | default: |
228 | val = 0; | |
229 | break; | |
230 | } | |
231 | return val; | |
232 | } | |
233 | ||
9139046c MA |
234 | static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, |
235 | int16_t cylinders, int8_t heads, int8_t sectors) | |
ba6c2377 | 236 | { |
ba6c2377 FB |
237 | rtc_set_memory(s, type_ofs, 47); |
238 | rtc_set_memory(s, info_ofs, cylinders); | |
239 | rtc_set_memory(s, info_ofs + 1, cylinders >> 8); | |
240 | rtc_set_memory(s, info_ofs + 2, heads); | |
241 | rtc_set_memory(s, info_ofs + 3, 0xff); | |
242 | rtc_set_memory(s, info_ofs + 4, 0xff); | |
243 | rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); | |
244 | rtc_set_memory(s, info_ofs + 6, cylinders); | |
245 | rtc_set_memory(s, info_ofs + 7, cylinders >> 8); | |
246 | rtc_set_memory(s, info_ofs + 8, sectors); | |
247 | } | |
248 | ||
6ac0e82d AZ |
249 | /* convert boot_device letter to something recognizable by the bios */ |
250 | static int boot_device2nibble(char boot_device) | |
251 | { | |
252 | switch(boot_device) { | |
253 | case 'a': | |
254 | case 'b': | |
255 | return 0x01; /* floppy boot */ | |
256 | case 'c': | |
257 | return 0x02; /* hard drive boot */ | |
258 | case 'd': | |
259 | return 0x03; /* CD-ROM boot */ | |
260 | case 'n': | |
261 | return 0x04; /* Network boot */ | |
262 | } | |
263 | return 0; | |
264 | } | |
265 | ||
ddcd5531 | 266 | static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) |
0ecdffbb AJ |
267 | { |
268 | #define PC_MAX_BOOT_DEVICES 3 | |
0ecdffbb AJ |
269 | int nbds, bds[3] = { 0, }; |
270 | int i; | |
271 | ||
272 | nbds = strlen(boot_device); | |
273 | if (nbds > PC_MAX_BOOT_DEVICES) { | |
ddcd5531 GA |
274 | error_setg(errp, "Too many boot devices for PC"); |
275 | return; | |
0ecdffbb AJ |
276 | } |
277 | for (i = 0; i < nbds; i++) { | |
278 | bds[i] = boot_device2nibble(boot_device[i]); | |
279 | if (bds[i] == 0) { | |
ddcd5531 GA |
280 | error_setg(errp, "Invalid boot device for PC: '%c'", |
281 | boot_device[i]); | |
282 | return; | |
0ecdffbb AJ |
283 | } |
284 | } | |
285 | rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); | |
d9346e81 | 286 | rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
0ecdffbb AJ |
287 | } |
288 | ||
ddcd5531 | 289 | static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) |
d9346e81 | 290 | { |
ddcd5531 | 291 | set_boot_dev(opaque, boot_device, errp); |
d9346e81 MA |
292 | } |
293 | ||
7444ca4e LE |
294 | static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) |
295 | { | |
296 | int val, nb, i; | |
2da44dd0 JS |
297 | FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, |
298 | FLOPPY_DRIVE_TYPE_NONE }; | |
7444ca4e LE |
299 | |
300 | /* floppy type */ | |
301 | if (floppy) { | |
302 | for (i = 0; i < 2; i++) { | |
303 | fd_type[i] = isa_fdc_get_drive_type(floppy, i); | |
304 | } | |
305 | } | |
306 | val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | | |
307 | cmos_get_fd_drive_type(fd_type[1]); | |
308 | rtc_set_memory(rtc_state, 0x10, val); | |
309 | ||
310 | val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); | |
311 | nb = 0; | |
2da44dd0 | 312 | if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
313 | nb++; |
314 | } | |
2da44dd0 | 315 | if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { |
7444ca4e LE |
316 | nb++; |
317 | } | |
318 | switch (nb) { | |
319 | case 0: | |
320 | break; | |
321 | case 1: | |
322 | val |= 0x01; /* 1 drive, ready for boot */ | |
323 | break; | |
324 | case 2: | |
325 | val |= 0x41; /* 2 drives, ready for boot */ | |
326 | break; | |
327 | } | |
328 | rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); | |
329 | } | |
330 | ||
c0897e0c MA |
331 | typedef struct pc_cmos_init_late_arg { |
332 | ISADevice *rtc_state; | |
9139046c | 333 | BusState *idebus[2]; |
c0897e0c MA |
334 | } pc_cmos_init_late_arg; |
335 | ||
b86f4613 LE |
336 | typedef struct check_fdc_state { |
337 | ISADevice *floppy; | |
338 | bool multiple; | |
339 | } CheckFdcState; | |
340 | ||
341 | static int check_fdc(Object *obj, void *opaque) | |
342 | { | |
343 | CheckFdcState *state = opaque; | |
344 | Object *fdc; | |
345 | uint32_t iobase; | |
346 | Error *local_err = NULL; | |
347 | ||
348 | fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); | |
349 | if (!fdc) { | |
350 | return 0; | |
351 | } | |
352 | ||
1ea1572a | 353 | iobase = object_property_get_uint(obj, "iobase", &local_err); |
b86f4613 LE |
354 | if (local_err || iobase != 0x3f0) { |
355 | error_free(local_err); | |
356 | return 0; | |
357 | } | |
358 | ||
359 | if (state->floppy) { | |
360 | state->multiple = true; | |
361 | } else { | |
362 | state->floppy = ISA_DEVICE(obj); | |
363 | } | |
364 | return 0; | |
365 | } | |
366 | ||
367 | static const char * const fdc_container_path[] = { | |
368 | "/unattached", "/peripheral", "/peripheral-anon" | |
369 | }; | |
370 | ||
424e4a87 RK |
371 | /* |
372 | * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers | |
373 | * and ACPI objects. | |
374 | */ | |
375 | ISADevice *pc_find_fdc0(void) | |
376 | { | |
377 | int i; | |
378 | Object *container; | |
379 | CheckFdcState state = { 0 }; | |
380 | ||
381 | for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { | |
382 | container = container_get(qdev_get_machine(), fdc_container_path[i]); | |
383 | object_child_foreach(container, check_fdc, &state); | |
384 | } | |
385 | ||
386 | if (state.multiple) { | |
3dc6f869 AF |
387 | warn_report("multiple floppy disk controllers with " |
388 | "iobase=0x3f0 have been found"); | |
433672b0 | 389 | error_printf("the one being picked for CMOS setup might not reflect " |
9e5d2c52 | 390 | "your intent"); |
424e4a87 RK |
391 | } |
392 | ||
393 | return state.floppy; | |
394 | } | |
395 | ||
c0897e0c MA |
396 | static void pc_cmos_init_late(void *opaque) |
397 | { | |
398 | pc_cmos_init_late_arg *arg = opaque; | |
399 | ISADevice *s = arg->rtc_state; | |
9139046c MA |
400 | int16_t cylinders; |
401 | int8_t heads, sectors; | |
c0897e0c | 402 | int val; |
2adc99b2 | 403 | int i, trans; |
c0897e0c | 404 | |
9139046c | 405 | val = 0; |
272f0428 CP |
406 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, |
407 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
408 | cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); |
409 | val |= 0xf0; | |
410 | } | |
272f0428 CP |
411 | if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, |
412 | &cylinders, &heads, §ors) >= 0) { | |
9139046c MA |
413 | cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); |
414 | val |= 0x0f; | |
415 | } | |
416 | rtc_set_memory(s, 0x12, val); | |
c0897e0c MA |
417 | |
418 | val = 0; | |
419 | for (i = 0; i < 4; i++) { | |
9139046c MA |
420 | /* NOTE: ide_get_geometry() returns the physical |
421 | geometry. It is always such that: 1 <= sects <= 63, 1 | |
422 | <= heads <= 16, 1 <= cylinders <= 16383. The BIOS | |
423 | geometry can be different if a translation is done. */ | |
272f0428 CP |
424 | if (arg->idebus[i / 2] && |
425 | ide_get_geometry(arg->idebus[i / 2], i % 2, | |
9139046c | 426 | &cylinders, &heads, §ors) >= 0) { |
2adc99b2 MA |
427 | trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; |
428 | assert((trans & ~3) == 0); | |
429 | val |= trans << (i * 2); | |
c0897e0c MA |
430 | } |
431 | } | |
432 | rtc_set_memory(s, 0x39, val); | |
433 | ||
424e4a87 | 434 | pc_cmos_init_floppy(s, pc_find_fdc0()); |
b86f4613 | 435 | |
c0897e0c MA |
436 | qemu_unregister_reset(pc_cmos_init_late, opaque); |
437 | } | |
438 | ||
23d30407 | 439 | void pc_cmos_init(PCMachineState *pcms, |
220a8846 | 440 | BusState *idebus0, BusState *idebus1, |
63ffb564 | 441 | ISADevice *s) |
80cabfad | 442 | { |
7444ca4e | 443 | int val; |
c0897e0c | 444 | static pc_cmos_init_late_arg arg; |
b0a21b53 | 445 | |
b0a21b53 | 446 | /* various important CMOS locations needed by PC/Bochs bios */ |
80cabfad FB |
447 | |
448 | /* memory size */ | |
e89001f7 | 449 | /* base memory (first MiB) */ |
88076854 | 450 | val = MIN(pcms->below_4g_mem_size / 1024, 640); |
333190eb FB |
451 | rtc_set_memory(s, 0x15, val); |
452 | rtc_set_memory(s, 0x16, val >> 8); | |
e89001f7 | 453 | /* extended memory (next 64MiB) */ |
88076854 EH |
454 | if (pcms->below_4g_mem_size > 1024 * 1024) { |
455 | val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; | |
e89001f7 MA |
456 | } else { |
457 | val = 0; | |
458 | } | |
80cabfad FB |
459 | if (val > 65535) |
460 | val = 65535; | |
b0a21b53 FB |
461 | rtc_set_memory(s, 0x17, val); |
462 | rtc_set_memory(s, 0x18, val >> 8); | |
463 | rtc_set_memory(s, 0x30, val); | |
464 | rtc_set_memory(s, 0x31, val >> 8); | |
e89001f7 | 465 | /* memory between 16MiB and 4GiB */ |
88076854 EH |
466 | if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { |
467 | val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; | |
e89001f7 | 468 | } else { |
9da98861 | 469 | val = 0; |
e89001f7 | 470 | } |
80cabfad FB |
471 | if (val > 65535) |
472 | val = 65535; | |
b0a21b53 FB |
473 | rtc_set_memory(s, 0x34, val); |
474 | rtc_set_memory(s, 0x35, val >> 8); | |
e89001f7 | 475 | /* memory above 4GiB */ |
88076854 | 476 | val = pcms->above_4g_mem_size / 65536; |
e89001f7 MA |
477 | rtc_set_memory(s, 0x5b, val); |
478 | rtc_set_memory(s, 0x5c, val >> 8); | |
479 | rtc_set_memory(s, 0x5d, val >> 16); | |
3b46e624 | 480 | |
23d30407 | 481 | object_property_add_link(OBJECT(pcms), "rtc_state", |
2d996150 | 482 | TYPE_ISA_DEVICE, |
ec68007a | 483 | (Object **)&pcms->rtc, |
2d996150 GZ |
484 | object_property_allow_set_link, |
485 | OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); | |
23d30407 | 486 | object_property_set_link(OBJECT(pcms), OBJECT(s), |
2d996150 | 487 | "rtc_state", &error_abort); |
298e01b6 | 488 | |
007b0657 | 489 | set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); |
80cabfad | 490 | |
b0a21b53 | 491 | val = 0; |
b0a21b53 FB |
492 | val |= 0x02; /* FPU is there */ |
493 | val |= 0x04; /* PS/2 mouse installed */ | |
494 | rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); | |
495 | ||
b86f4613 | 496 | /* hard drives and FDC */ |
c0897e0c | 497 | arg.rtc_state = s; |
9139046c MA |
498 | arg.idebus[0] = idebus0; |
499 | arg.idebus[1] = idebus1; | |
c0897e0c | 500 | qemu_register_reset(pc_cmos_init_late, &arg); |
80cabfad FB |
501 | } |
502 | ||
a0881c64 AF |
503 | #define TYPE_PORT92 "port92" |
504 | #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) | |
505 | ||
4b78a802 BS |
506 | /* port 92 stuff: could be split off */ |
507 | typedef struct Port92State { | |
a0881c64 AF |
508 | ISADevice parent_obj; |
509 | ||
23af670e | 510 | MemoryRegion io; |
4b78a802 | 511 | uint8_t outport; |
d812b3d6 | 512 | qemu_irq a20_out; |
4b78a802 BS |
513 | } Port92State; |
514 | ||
93ef4192 AG |
515 | static void port92_write(void *opaque, hwaddr addr, uint64_t val, |
516 | unsigned size) | |
4b78a802 BS |
517 | { |
518 | Port92State *s = opaque; | |
4700a316 | 519 | int oldval = s->outport; |
4b78a802 | 520 | |
c5539cb4 | 521 | DPRINTF("port92: write 0x%02" PRIx64 "\n", val); |
4b78a802 | 522 | s->outport = val; |
d812b3d6 | 523 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
4700a316 | 524 | if ((val & 1) && !(oldval & 1)) { |
cf83f140 | 525 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
4b78a802 BS |
526 | } |
527 | } | |
528 | ||
93ef4192 AG |
529 | static uint64_t port92_read(void *opaque, hwaddr addr, |
530 | unsigned size) | |
4b78a802 BS |
531 | { |
532 | Port92State *s = opaque; | |
533 | uint32_t ret; | |
534 | ||
535 | ret = s->outport; | |
536 | DPRINTF("port92: read 0x%02x\n", ret); | |
537 | return ret; | |
538 | } | |
539 | ||
d80fe99d | 540 | static void port92_init(ISADevice *dev, qemu_irq a20_out) |
4b78a802 | 541 | { |
d80fe99d | 542 | qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); |
4b78a802 BS |
543 | } |
544 | ||
545 | static const VMStateDescription vmstate_port92_isa = { | |
546 | .name = "port92", | |
547 | .version_id = 1, | |
548 | .minimum_version_id = 1, | |
d49805ae | 549 | .fields = (VMStateField[]) { |
4b78a802 BS |
550 | VMSTATE_UINT8(outport, Port92State), |
551 | VMSTATE_END_OF_LIST() | |
552 | } | |
553 | }; | |
554 | ||
555 | static void port92_reset(DeviceState *d) | |
556 | { | |
a0881c64 | 557 | Port92State *s = PORT92(d); |
4b78a802 BS |
558 | |
559 | s->outport &= ~1; | |
560 | } | |
561 | ||
23af670e | 562 | static const MemoryRegionOps port92_ops = { |
93ef4192 AG |
563 | .read = port92_read, |
564 | .write = port92_write, | |
565 | .impl = { | |
566 | .min_access_size = 1, | |
567 | .max_access_size = 1, | |
568 | }, | |
569 | .endianness = DEVICE_LITTLE_ENDIAN, | |
23af670e RH |
570 | }; |
571 | ||
db895a1e | 572 | static void port92_initfn(Object *obj) |
4b78a802 | 573 | { |
db895a1e | 574 | Port92State *s = PORT92(obj); |
4b78a802 | 575 | |
1437c94b | 576 | memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); |
23af670e | 577 | |
4b78a802 | 578 | s->outport = 0; |
d812b3d6 EV |
579 | |
580 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); | |
db895a1e AF |
581 | } |
582 | ||
583 | static void port92_realizefn(DeviceState *dev, Error **errp) | |
584 | { | |
585 | ISADevice *isadev = ISA_DEVICE(dev); | |
586 | Port92State *s = PORT92(dev); | |
587 | ||
588 | isa_register_ioport(isadev, &s->io, 0x92); | |
4b78a802 BS |
589 | } |
590 | ||
8f04ee08 AL |
591 | static void port92_class_initfn(ObjectClass *klass, void *data) |
592 | { | |
39bffca2 | 593 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e | 594 | |
db895a1e | 595 | dc->realize = port92_realizefn; |
39bffca2 AL |
596 | dc->reset = port92_reset; |
597 | dc->vmsd = &vmstate_port92_isa; | |
f3b17640 MA |
598 | /* |
599 | * Reason: unlike ordinary ISA devices, this one needs additional | |
600 | * wiring: its A20 output line needs to be wired up by | |
601 | * port92_init(). | |
602 | */ | |
e90f2a8c | 603 | dc->user_creatable = false; |
8f04ee08 AL |
604 | } |
605 | ||
8c43a6f0 | 606 | static const TypeInfo port92_info = { |
a0881c64 | 607 | .name = TYPE_PORT92, |
39bffca2 AL |
608 | .parent = TYPE_ISA_DEVICE, |
609 | .instance_size = sizeof(Port92State), | |
db895a1e | 610 | .instance_init = port92_initfn, |
39bffca2 | 611 | .class_init = port92_class_initfn, |
4b78a802 BS |
612 | }; |
613 | ||
83f7d43a | 614 | static void port92_register_types(void) |
4b78a802 | 615 | { |
39bffca2 | 616 | type_register_static(&port92_info); |
4b78a802 | 617 | } |
83f7d43a AF |
618 | |
619 | type_init(port92_register_types) | |
4b78a802 | 620 | |
956a3e6b | 621 | static void handle_a20_line_change(void *opaque, int irq, int level) |
59b8ad81 | 622 | { |
cc36a7a2 | 623 | X86CPU *cpu = opaque; |
e1a23744 | 624 | |
956a3e6b | 625 | /* XXX: send to all CPUs ? */ |
4b78a802 | 626 | /* XXX: add logic to handle multiple A20 line sources */ |
cc36a7a2 | 627 | x86_cpu_set_a20(cpu, level); |
e1a23744 FB |
628 | } |
629 | ||
4c5b10b7 JS |
630 | int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) |
631 | { | |
7d67110f | 632 | int index = le32_to_cpu(e820_reserve.count); |
4c5b10b7 JS |
633 | struct e820_entry *entry; |
634 | ||
7d67110f GH |
635 | if (type != E820_RAM) { |
636 | /* old FW_CFG_E820_TABLE entry -- reservations only */ | |
637 | if (index >= E820_NR_ENTRIES) { | |
638 | return -EBUSY; | |
639 | } | |
640 | entry = &e820_reserve.entry[index++]; | |
641 | ||
642 | entry->address = cpu_to_le64(address); | |
643 | entry->length = cpu_to_le64(length); | |
644 | entry->type = cpu_to_le32(type); | |
645 | ||
646 | e820_reserve.count = cpu_to_le32(index); | |
647 | } | |
4c5b10b7 | 648 | |
7d67110f | 649 | /* new "etc/e820" file -- include ram too */ |
ab3ad07f | 650 | e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); |
7d67110f GH |
651 | e820_table[e820_entries].address = cpu_to_le64(address); |
652 | e820_table[e820_entries].length = cpu_to_le64(length); | |
653 | e820_table[e820_entries].type = cpu_to_le32(type); | |
654 | e820_entries++; | |
4c5b10b7 | 655 | |
7d67110f | 656 | return e820_entries; |
4c5b10b7 JS |
657 | } |
658 | ||
7bf8ef19 GS |
659 | int e820_get_num_entries(void) |
660 | { | |
661 | return e820_entries; | |
662 | } | |
663 | ||
664 | bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) | |
665 | { | |
666 | if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { | |
667 | *address = le64_to_cpu(e820_table[idx].address); | |
668 | *length = le64_to_cpu(e820_table[idx].length); | |
669 | return true; | |
670 | } | |
671 | return false; | |
672 | } | |
673 | ||
54a40293 EH |
674 | /* Enables contiguous-apic-ID mode, for compatibility */ |
675 | static bool compat_apic_id_mode; | |
676 | ||
677 | void enable_compat_apic_id_mode(void) | |
678 | { | |
679 | compat_apic_id_mode = true; | |
680 | } | |
681 | ||
682 | /* Calculates initial APIC ID for a specific CPU index | |
683 | * | |
684 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
685 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
686 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
687 | * all CPUs up to max_cpus. | |
688 | */ | |
689 | static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
690 | { | |
691 | uint32_t correct_id; | |
692 | static bool warned; | |
693 | ||
694 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
695 | if (compat_apic_id_mode) { | |
b1c12027 | 696 | if (cpu_index != correct_id && !warned && !qtest_enabled()) { |
54a40293 EH |
697 | error_report("APIC IDs set in compatibility mode, " |
698 | "CPU topology won't match the configuration"); | |
699 | warned = true; | |
700 | } | |
701 | return cpu_index; | |
702 | } else { | |
703 | return correct_id; | |
704 | } | |
705 | } | |
706 | ||
f2098f48 | 707 | static void pc_build_smbios(PCMachineState *pcms) |
80cabfad | 708 | { |
c97294ec GS |
709 | uint8_t *smbios_tables, *smbios_anchor; |
710 | size_t smbios_tables_len, smbios_anchor_len; | |
89cc4a27 WH |
711 | struct smbios_phys_mem_area *mem_array; |
712 | unsigned i, array_count; | |
38690a1c IM |
713 | MachineState *ms = MACHINE(pcms); |
714 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
f2098f48 IM |
715 | |
716 | /* tell smbios about cpuid version and features */ | |
717 | smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); | |
5fd0a9d4 WH |
718 | |
719 | smbios_tables = smbios_get_table_legacy(&smbios_tables_len); | |
720 | if (smbios_tables) { | |
f2098f48 | 721 | fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
5fd0a9d4 WH |
722 | smbios_tables, smbios_tables_len); |
723 | } | |
724 | ||
89cc4a27 WH |
725 | /* build the array of physical mem area from e820 table */ |
726 | mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); | |
727 | for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { | |
728 | uint64_t addr, len; | |
729 | ||
730 | if (e820_get_entry(i, E820_RAM, &addr, &len)) { | |
731 | mem_array[array_count].address = addr; | |
732 | mem_array[array_count].length = len; | |
733 | array_count++; | |
734 | } | |
735 | } | |
736 | smbios_get_tables(mem_array, array_count, | |
737 | &smbios_tables, &smbios_tables_len, | |
5fd0a9d4 | 738 | &smbios_anchor, &smbios_anchor_len); |
89cc4a27 WH |
739 | g_free(mem_array); |
740 | ||
5fd0a9d4 | 741 | if (smbios_anchor) { |
f2098f48 | 742 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", |
5fd0a9d4 | 743 | smbios_tables, smbios_tables_len); |
f2098f48 | 744 | fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", |
5fd0a9d4 WH |
745 | smbios_anchor, smbios_anchor_len); |
746 | } | |
747 | } | |
748 | ||
ebde2465 | 749 | static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) |
5fd0a9d4 WH |
750 | { |
751 | FWCfgState *fw_cfg; | |
11c2fd3e | 752 | uint64_t *numa_fw_cfg; |
ea265072 IM |
753 | int i; |
754 | const CPUArchIdList *cpus; | |
755 | MachineClass *mc = MACHINE_GET_CLASS(pcms); | |
3cce6243 | 756 | |
305ae888 | 757 | fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); |
e3cadac0 | 758 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
c886fc4c | 759 | |
1d934e89 EH |
760 | /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: |
761 | * | |
a3abd0f2 IM |
762 | * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for |
763 | * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, | |
764 | * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface | |
765 | * for CPU hotplug also uses APIC ID and not "CPU index". | |
766 | * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", | |
767 | * but the "limit to the APIC ID values SeaBIOS may see". | |
1d934e89 | 768 | * |
a3abd0f2 IM |
769 | * So for compatibility reasons with old BIOSes we are stuck with |
770 | * "etc/max-cpus" actually being apic_id_limit | |
1d934e89 | 771 | */ |
ebde2465 | 772 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); |
905fdcb5 | 773 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
089da572 MA |
774 | fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, |
775 | acpi_tables, acpi_tables_len); | |
9b5b76d4 | 776 | fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); |
b6f6e3d3 | 777 | |
089da572 | 778 | fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, |
7d67110f GH |
779 | &e820_reserve, sizeof(e820_reserve)); |
780 | fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, | |
781 | sizeof(struct e820_entry) * e820_entries); | |
11c2fd3e | 782 | |
089da572 | 783 | fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); |
11c2fd3e AL |
784 | /* allocate memory for the NUMA channel: one (64bit) word for the number |
785 | * of nodes, one word for each VCPU->node and one word for each node to | |
786 | * hold the amount of memory. | |
787 | */ | |
ebde2465 | 788 | numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); |
11c2fd3e | 789 | numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); |
ea265072 IM |
790 | cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); |
791 | for (i = 0; i < cpus->len; i++) { | |
792 | unsigned int apic_id = cpus->cpus[i].arch_id; | |
ebde2465 | 793 | assert(apic_id < pcms->apic_id_limit); |
d41f3e75 | 794 | numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); |
11c2fd3e AL |
795 | } |
796 | for (i = 0; i < nb_numa_nodes; i++) { | |
ebde2465 IM |
797 | numa_fw_cfg[pcms->apic_id_limit + 1 + i] = |
798 | cpu_to_le64(numa_info[i].node_mem); | |
11c2fd3e | 799 | } |
089da572 | 800 | fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, |
ebde2465 | 801 | (1 + pcms->apic_id_limit + nb_numa_nodes) * |
1d934e89 | 802 | sizeof(*numa_fw_cfg)); |
bf483392 AG |
803 | |
804 | return fw_cfg; | |
80cabfad FB |
805 | } |
806 | ||
642a4f96 TS |
807 | static long get_file_size(FILE *f) |
808 | { | |
809 | long where, size; | |
810 | ||
811 | /* XXX: on Unix systems, using fstat() probably makes more sense */ | |
812 | ||
813 | where = ftell(f); | |
814 | fseek(f, 0, SEEK_END); | |
815 | size = ftell(f); | |
816 | fseek(f, where, SEEK_SET); | |
817 | ||
818 | return size; | |
819 | } | |
820 | ||
3cbeb524 AB |
821 | /* setup_data types */ |
822 | #define SETUP_NONE 0 | |
823 | #define SETUP_E820_EXT 1 | |
824 | #define SETUP_DTB 2 | |
825 | #define SETUP_PCI 3 | |
826 | #define SETUP_EFI 4 | |
827 | ||
828 | struct setup_data { | |
829 | uint64_t next; | |
830 | uint32_t type; | |
831 | uint32_t len; | |
832 | uint8_t data[0]; | |
833 | } __attribute__((packed)); | |
834 | ||
df1f79fd EH |
835 | static void load_linux(PCMachineState *pcms, |
836 | FWCfgState *fw_cfg) | |
642a4f96 TS |
837 | { |
838 | uint16_t protocol; | |
5cea8590 | 839 | int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
3cbeb524 | 840 | int dtb_size, setup_data_offset; |
642a4f96 | 841 | uint32_t initrd_max; |
57a46d05 | 842 | uint8_t header[8192], *setup, *kernel, *initrd_data; |
a8170e5e | 843 | hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; |
45a50b16 | 844 | FILE *f; |
bf4e5d92 | 845 | char *vmode; |
df1f79fd | 846 | MachineState *machine = MACHINE(pcms); |
cd4040ec | 847 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
3cbeb524 | 848 | struct setup_data *setup_data; |
df1f79fd EH |
849 | const char *kernel_filename = machine->kernel_filename; |
850 | const char *initrd_filename = machine->initrd_filename; | |
3cbeb524 | 851 | const char *dtb_filename = machine->dtb; |
df1f79fd | 852 | const char *kernel_cmdline = machine->kernel_cmdline; |
642a4f96 TS |
853 | |
854 | /* Align to 16 bytes as a paranoia measure */ | |
855 | cmdline_size = (strlen(kernel_cmdline)+16) & ~15; | |
856 | ||
857 | /* load the kernel header */ | |
858 | f = fopen(kernel_filename, "rb"); | |
859 | if (!f || !(kernel_size = get_file_size(f)) || | |
0f9d76e5 LG |
860 | fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != |
861 | MIN(ARRAY_SIZE(header), kernel_size)) { | |
862 | fprintf(stderr, "qemu: could not load kernel '%s': %s\n", | |
863 | kernel_filename, strerror(errno)); | |
864 | exit(1); | |
642a4f96 TS |
865 | } |
866 | ||
867 | /* kernel protocol version */ | |
bc4edd79 | 868 | #if 0 |
642a4f96 | 869 | fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); |
bc4edd79 | 870 | #endif |
0f9d76e5 LG |
871 | if (ldl_p(header+0x202) == 0x53726448) { |
872 | protocol = lduw_p(header+0x206); | |
873 | } else { | |
874 | /* This looks like a multiboot kernel. If it is, let's stop | |
875 | treating it like a Linux kernel. */ | |
52001445 | 876 | if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, |
0f9d76e5 | 877 | kernel_cmdline, kernel_size, header)) { |
82663ee2 | 878 | return; |
0f9d76e5 LG |
879 | } |
880 | protocol = 0; | |
f16408df | 881 | } |
642a4f96 TS |
882 | |
883 | if (protocol < 0x200 || !(header[0x211] & 0x01)) { | |
0f9d76e5 LG |
884 | /* Low kernel */ |
885 | real_addr = 0x90000; | |
886 | cmdline_addr = 0x9a000 - cmdline_size; | |
887 | prot_addr = 0x10000; | |
642a4f96 | 888 | } else if (protocol < 0x202) { |
0f9d76e5 LG |
889 | /* High but ancient kernel */ |
890 | real_addr = 0x90000; | |
891 | cmdline_addr = 0x9a000 - cmdline_size; | |
892 | prot_addr = 0x100000; | |
642a4f96 | 893 | } else { |
0f9d76e5 LG |
894 | /* High and recent kernel */ |
895 | real_addr = 0x10000; | |
896 | cmdline_addr = 0x20000; | |
897 | prot_addr = 0x100000; | |
642a4f96 TS |
898 | } |
899 | ||
bc4edd79 | 900 | #if 0 |
642a4f96 | 901 | fprintf(stderr, |
0f9d76e5 LG |
902 | "qemu: real_addr = 0x" TARGET_FMT_plx "\n" |
903 | "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" | |
904 | "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", | |
905 | real_addr, | |
906 | cmdline_addr, | |
907 | prot_addr); | |
bc4edd79 | 908 | #endif |
642a4f96 TS |
909 | |
910 | /* highest address for loading the initrd */ | |
0f9d76e5 LG |
911 | if (protocol >= 0x203) { |
912 | initrd_max = ldl_p(header+0x22c); | |
913 | } else { | |
914 | initrd_max = 0x37ffffff; | |
915 | } | |
642a4f96 | 916 | |
cd4040ec EH |
917 | if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { |
918 | initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; | |
927766c7 | 919 | } |
642a4f96 | 920 | |
57a46d05 AG |
921 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
922 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); | |
96f80586 | 923 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
642a4f96 TS |
924 | |
925 | if (protocol >= 0x202) { | |
0f9d76e5 | 926 | stl_p(header+0x228, cmdline_addr); |
642a4f96 | 927 | } else { |
0f9d76e5 LG |
928 | stw_p(header+0x20, 0xA33F); |
929 | stw_p(header+0x22, cmdline_addr-real_addr); | |
642a4f96 TS |
930 | } |
931 | ||
bf4e5d92 PT |
932 | /* handle vga= parameter */ |
933 | vmode = strstr(kernel_cmdline, "vga="); | |
934 | if (vmode) { | |
935 | unsigned int video_mode; | |
936 | /* skip "vga=" */ | |
937 | vmode += 4; | |
938 | if (!strncmp(vmode, "normal", 6)) { | |
939 | video_mode = 0xffff; | |
940 | } else if (!strncmp(vmode, "ext", 3)) { | |
941 | video_mode = 0xfffe; | |
942 | } else if (!strncmp(vmode, "ask", 3)) { | |
943 | video_mode = 0xfffd; | |
944 | } else { | |
945 | video_mode = strtol(vmode, NULL, 0); | |
946 | } | |
947 | stw_p(header+0x1fa, video_mode); | |
948 | } | |
949 | ||
642a4f96 | 950 | /* loader type */ |
5cbdb3a3 | 951 | /* High nybble = B reserved for QEMU; low nybble is revision number. |
642a4f96 TS |
952 | If this code is substantially changed, you may want to consider |
953 | incrementing the revision. */ | |
0f9d76e5 LG |
954 | if (protocol >= 0x200) { |
955 | header[0x210] = 0xB0; | |
956 | } | |
642a4f96 TS |
957 | /* heap */ |
958 | if (protocol >= 0x201) { | |
0f9d76e5 LG |
959 | header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
960 | stw_p(header+0x224, cmdline_addr-real_addr-0x200); | |
642a4f96 TS |
961 | } |
962 | ||
963 | /* load initrd */ | |
964 | if (initrd_filename) { | |
0f9d76e5 LG |
965 | if (protocol < 0x200) { |
966 | fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); | |
967 | exit(1); | |
968 | } | |
642a4f96 | 969 | |
0f9d76e5 | 970 | initrd_size = get_image_size(initrd_filename); |
d6fa4b77 | 971 | if (initrd_size < 0) { |
7454e51d MT |
972 | fprintf(stderr, "qemu: error reading initrd %s: %s\n", |
973 | initrd_filename, strerror(errno)); | |
d6fa4b77 MK |
974 | exit(1); |
975 | } | |
976 | ||
45a50b16 | 977 | initrd_addr = (initrd_max-initrd_size) & ~4095; |
57a46d05 | 978 | |
7267c094 | 979 | initrd_data = g_malloc(initrd_size); |
57a46d05 AG |
980 | load_image(initrd_filename, initrd_data); |
981 | ||
982 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); | |
983 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
984 | fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); | |
642a4f96 | 985 | |
0f9d76e5 LG |
986 | stl_p(header+0x218, initrd_addr); |
987 | stl_p(header+0x21c, initrd_size); | |
642a4f96 TS |
988 | } |
989 | ||
45a50b16 | 990 | /* load kernel and setup */ |
642a4f96 | 991 | setup_size = header[0x1f1]; |
0f9d76e5 LG |
992 | if (setup_size == 0) { |
993 | setup_size = 4; | |
994 | } | |
642a4f96 | 995 | setup_size = (setup_size+1)*512; |
ec5fd402 PB |
996 | if (setup_size > kernel_size) { |
997 | fprintf(stderr, "qemu: invalid kernel header\n"); | |
998 | exit(1); | |
999 | } | |
45a50b16 | 1000 | kernel_size -= setup_size; |
642a4f96 | 1001 | |
7267c094 AL |
1002 | setup = g_malloc(setup_size); |
1003 | kernel = g_malloc(kernel_size); | |
45a50b16 | 1004 | fseek(f, 0, SEEK_SET); |
5a41ecc5 KS |
1005 | if (fread(setup, 1, setup_size, f) != setup_size) { |
1006 | fprintf(stderr, "fread() failed\n"); | |
1007 | exit(1); | |
1008 | } | |
1009 | if (fread(kernel, 1, kernel_size, f) != kernel_size) { | |
1010 | fprintf(stderr, "fread() failed\n"); | |
1011 | exit(1); | |
1012 | } | |
642a4f96 | 1013 | fclose(f); |
3cbeb524 AB |
1014 | |
1015 | /* append dtb to kernel */ | |
1016 | if (dtb_filename) { | |
1017 | if (protocol < 0x209) { | |
1018 | fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); | |
1019 | exit(1); | |
1020 | } | |
1021 | ||
1022 | dtb_size = get_image_size(dtb_filename); | |
1023 | if (dtb_size <= 0) { | |
1024 | fprintf(stderr, "qemu: error reading dtb %s: %s\n", | |
1025 | dtb_filename, strerror(errno)); | |
1026 | exit(1); | |
1027 | } | |
1028 | ||
1029 | setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); | |
1030 | kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; | |
1031 | kernel = g_realloc(kernel, kernel_size); | |
1032 | ||
1033 | stq_p(header+0x250, prot_addr + setup_data_offset); | |
1034 | ||
1035 | setup_data = (struct setup_data *)(kernel + setup_data_offset); | |
1036 | setup_data->next = 0; | |
1037 | setup_data->type = cpu_to_le32(SETUP_DTB); | |
1038 | setup_data->len = cpu_to_le32(dtb_size); | |
1039 | ||
1040 | load_image_size(dtb_filename, setup_data->data, dtb_size); | |
1041 | } | |
1042 | ||
45a50b16 | 1043 | memcpy(setup, header, MIN(sizeof(header), setup_size)); |
57a46d05 AG |
1044 | |
1045 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); | |
1046 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1047 | fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); | |
1048 | ||
1049 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); | |
1050 | fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); | |
1051 | fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); | |
1052 | ||
98e753a6 IM |
1053 | option_rom[nb_option_roms].bootindex = 0; |
1054 | option_rom[nb_option_roms].name = "linuxboot.bin"; | |
1055 | if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { | |
b2a575a1 | 1056 | option_rom[nb_option_roms].name = "linuxboot_dma.bin"; |
b2a575a1 | 1057 | } |
57a46d05 | 1058 | nb_option_roms++; |
642a4f96 TS |
1059 | } |
1060 | ||
b41a2cd1 FB |
1061 | #define NE2000_NB_MAX 6 |
1062 | ||
675d6f82 BS |
1063 | static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
1064 | 0x280, 0x380 }; | |
1065 | static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
b41a2cd1 | 1066 | |
48a18b3c | 1067 | void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) |
a41b2ff2 PB |
1068 | { |
1069 | static int nb_ne2k = 0; | |
1070 | ||
1071 | if (nb_ne2k == NE2000_NB_MAX) | |
1072 | return; | |
48a18b3c | 1073 | isa_ne2000_init(bus, ne2000_io[nb_ne2k], |
9453c5bc | 1074 | ne2000_irq[nb_ne2k], nd); |
a41b2ff2 PB |
1075 | nb_ne2k++; |
1076 | } | |
1077 | ||
92a16d7a | 1078 | DeviceState *cpu_get_current_apic(void) |
0e26b7b8 | 1079 | { |
4917cf44 AF |
1080 | if (current_cpu) { |
1081 | X86CPU *cpu = X86_CPU(current_cpu); | |
02e51483 | 1082 | return cpu->apic_state; |
0e26b7b8 BS |
1083 | } else { |
1084 | return NULL; | |
1085 | } | |
1086 | } | |
1087 | ||
845773ab | 1088 | void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
53b67b30 | 1089 | { |
c3affe56 | 1090 | X86CPU *cpu = opaque; |
53b67b30 BS |
1091 | |
1092 | if (level) { | |
c3affe56 | 1093 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); |
53b67b30 BS |
1094 | } |
1095 | } | |
1096 | ||
074281d6 | 1097 | static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) |
31050930 | 1098 | { |
074281d6 | 1099 | Object *cpu = NULL; |
31050930 IM |
1100 | Error *local_err = NULL; |
1101 | ||
074281d6 | 1102 | cpu = object_new(typename); |
31050930 | 1103 | |
c7b4efb4 | 1104 | object_property_set_uint(cpu, apic_id, "apic-id", &local_err); |
074281d6 | 1105 | object_property_set_bool(cpu, true, "realized", &local_err); |
31050930 | 1106 | |
074281d6 | 1107 | object_unref(cpu); |
021c9d25 | 1108 | error_propagate(errp, local_err); |
31050930 IM |
1109 | } |
1110 | ||
c649983b IM |
1111 | void pc_hot_add_cpu(const int64_t id, Error **errp) |
1112 | { | |
38690a1c | 1113 | MachineState *ms = MACHINE(qdev_get_machine()); |
c649983b | 1114 | int64_t apic_id = x86_cpu_apic_id_from_index(id); |
0e3bd562 | 1115 | Error *local_err = NULL; |
c649983b | 1116 | |
8de433cb IM |
1117 | if (id < 0) { |
1118 | error_setg(errp, "Invalid CPU id: %" PRIi64, id); | |
1119 | return; | |
1120 | } | |
1121 | ||
5ff020b7 EH |
1122 | if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { |
1123 | error_setg(errp, "Unable to add CPU: %" PRIi64 | |
1124 | ", resulting APIC ID (%" PRIi64 ") is too large", | |
1125 | id, apic_id); | |
1126 | return; | |
1127 | } | |
1128 | ||
311ca98d | 1129 | pc_new_cpu(ms->cpu_type, apic_id, &local_err); |
0e3bd562 AF |
1130 | if (local_err) { |
1131 | error_propagate(errp, local_err); | |
1132 | return; | |
1133 | } | |
c649983b IM |
1134 | } |
1135 | ||
4884b7bf | 1136 | void pc_cpus_init(PCMachineState *pcms) |
70166477 IY |
1137 | { |
1138 | int i; | |
c96a1c0b | 1139 | const CPUArchIdList *possible_cpus; |
311ca98d | 1140 | MachineState *ms = MACHINE(pcms); |
c96a1c0b | 1141 | MachineClass *mc = MACHINE_GET_CLASS(pcms); |
70166477 | 1142 | |
ebde2465 IM |
1143 | /* Calculates the limit to CPU APIC ID values |
1144 | * | |
1145 | * Limit for the APIC ID value, so that all | |
1146 | * CPU APIC IDs are < pcms->apic_id_limit. | |
1147 | * | |
1148 | * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). | |
1149 | */ | |
1150 | pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; | |
311ca98d | 1151 | possible_cpus = mc->possible_cpu_arch_ids(ms); |
c96a1c0b | 1152 | for (i = 0; i < smp_cpus; i++) { |
d342eb76 IM |
1153 | pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, |
1154 | &error_fatal); | |
70166477 IY |
1155 | } |
1156 | } | |
1157 | ||
217f1b4a HZ |
1158 | static void pc_build_feature_control_file(PCMachineState *pcms) |
1159 | { | |
38690a1c IM |
1160 | MachineState *ms = MACHINE(pcms); |
1161 | X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); | |
217f1b4a HZ |
1162 | CPUX86State *env = &cpu->env; |
1163 | uint32_t unused, ecx, edx; | |
1164 | uint64_t feature_control_bits = 0; | |
1165 | uint64_t *val; | |
1166 | ||
1167 | cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); | |
1168 | if (ecx & CPUID_EXT_VMX) { | |
1169 | feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1170 | } | |
1171 | ||
1172 | if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == | |
1173 | (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && | |
1174 | (env->mcg_cap & MCG_LMCE_P)) { | |
1175 | feature_control_bits |= FEATURE_CONTROL_LMCE; | |
1176 | } | |
1177 | ||
1178 | if (!feature_control_bits) { | |
1179 | return; | |
1180 | } | |
1181 | ||
1182 | val = g_malloc(sizeof(*val)); | |
1183 | *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); | |
1184 | fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); | |
1185 | } | |
1186 | ||
e3cadac0 IM |
1187 | static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) |
1188 | { | |
1189 | if (cpus_count > 0xff) { | |
1190 | /* If the number of CPUs can't be represented in 8 bits, the | |
1191 | * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just | |
1192 | * to make old BIOSes fail more predictably. | |
1193 | */ | |
1194 | rtc_set_memory(rtc, 0x5f, 0); | |
1195 | } else { | |
1196 | rtc_set_memory(rtc, 0x5f, cpus_count - 1); | |
1197 | } | |
1198 | } | |
1199 | ||
3459a625 | 1200 | static |
9ebeed0c | 1201 | void pc_machine_done(Notifier *notifier, void *data) |
3459a625 | 1202 | { |
9ebeed0c EH |
1203 | PCMachineState *pcms = container_of(notifier, |
1204 | PCMachineState, machine_done); | |
1205 | PCIBus *bus = pcms->bus; | |
2118196b | 1206 | |
ba157b69 | 1207 | /* set the number of CPUs */ |
e3cadac0 | 1208 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); |
ba157b69 | 1209 | |
2118196b MA |
1210 | if (bus) { |
1211 | int extra_hosts = 0; | |
1212 | ||
1213 | QLIST_FOREACH(bus, &bus->child, sibling) { | |
1214 | /* look for expander root buses */ | |
1215 | if (pci_bus_is_root(bus)) { | |
1216 | extra_hosts++; | |
1217 | } | |
1218 | } | |
f264d360 | 1219 | if (extra_hosts && pcms->fw_cfg) { |
2118196b MA |
1220 | uint64_t *val = g_malloc(sizeof(*val)); |
1221 | *val = cpu_to_le64(extra_hosts); | |
f264d360 | 1222 | fw_cfg_add_file(pcms->fw_cfg, |
2118196b MA |
1223 | "etc/extra-pci-roots", val, sizeof(*val)); |
1224 | } | |
1225 | } | |
1226 | ||
bb292f5a | 1227 | acpi_setup(); |
6d42eefa | 1228 | if (pcms->fw_cfg) { |
f2098f48 | 1229 | pc_build_smbios(pcms); |
217f1b4a | 1230 | pc_build_feature_control_file(pcms); |
e3cadac0 IM |
1231 | /* update FW_CFG_NB_CPUS to account for -device added CPUs */ |
1232 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
6d42eefa | 1233 | } |
60c5e104 | 1234 | |
1a26f466 | 1235 | if (pcms->apic_id_limit > 255 && !xen_enabled()) { |
60c5e104 IM |
1236 | IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); |
1237 | ||
1238 | if (!iommu || !iommu->x86_iommu.intr_supported || | |
1239 | iommu->intr_eim != ON_OFF_AUTO_ON) { | |
1240 | error_report("current -smp configuration requires " | |
1241 | "Extended Interrupt Mode enabled. " | |
1242 | "You can add an IOMMU using: " | |
1243 | "-device intel-iommu,intremap=on,eim=on"); | |
1244 | exit(EXIT_FAILURE); | |
1245 | } | |
1246 | } | |
3459a625 MT |
1247 | } |
1248 | ||
e4e8ba04 | 1249 | void pc_guest_info_init(PCMachineState *pcms) |
3459a625 | 1250 | { |
1f3aba37 | 1251 | int i; |
b20c9bd5 | 1252 | |
dd4c2f01 EH |
1253 | pcms->apic_xrupt_override = kvm_allows_irq0_override(); |
1254 | pcms->numa_nodes = nb_numa_nodes; | |
1255 | pcms->node_mem = g_malloc0(pcms->numa_nodes * | |
1256 | sizeof *pcms->node_mem); | |
8c85901e | 1257 | for (i = 0; i < nb_numa_nodes; i++) { |
dd4c2f01 | 1258 | pcms->node_mem[i] = numa_info[i].node_mem; |
8c85901e WG |
1259 | } |
1260 | ||
9ebeed0c EH |
1261 | pcms->machine_done.notify = pc_machine_done; |
1262 | qemu_add_machine_init_done_notifier(&pcms->machine_done); | |
3459a625 MT |
1263 | } |
1264 | ||
83d08f26 MT |
1265 | /* setup pci memory address space mapping into system address space */ |
1266 | void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, | |
1267 | MemoryRegion *pci_address_space) | |
39848901 | 1268 | { |
83d08f26 MT |
1269 | /* Set to lower priority than RAM */ |
1270 | memory_region_add_subregion_overlap(system_memory, 0x0, | |
1271 | pci_address_space, -1); | |
39848901 IM |
1272 | } |
1273 | ||
f7e4dd6c GH |
1274 | void pc_acpi_init(const char *default_dsdt) |
1275 | { | |
c5a98cf3 | 1276 | char *filename; |
f7e4dd6c GH |
1277 | |
1278 | if (acpi_tables != NULL) { | |
1279 | /* manually set via -acpitable, leave it alone */ | |
1280 | return; | |
1281 | } | |
1282 | ||
1283 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); | |
1284 | if (filename == NULL) { | |
2ab4b135 | 1285 | warn_report("failed to find %s", default_dsdt); |
c5a98cf3 | 1286 | } else { |
5bdb59a2 MA |
1287 | QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, |
1288 | &error_abort); | |
c5a98cf3 | 1289 | Error *err = NULL; |
f7e4dd6c | 1290 | |
5bdb59a2 | 1291 | qemu_opt_set(opts, "file", filename, &error_abort); |
0c764a9d | 1292 | |
1a4b2666 | 1293 | acpi_table_add_builtin(opts, &err); |
c5a98cf3 | 1294 | if (err) { |
88f83f35 | 1295 | warn_reportf_err(err, "failed to load %s: ", filename); |
c5a98cf3 | 1296 | } |
c5a98cf3 | 1297 | g_free(filename); |
f7e4dd6c | 1298 | } |
f7e4dd6c GH |
1299 | } |
1300 | ||
7bc35e0f | 1301 | void xen_load_linux(PCMachineState *pcms) |
b33a5bbf CL |
1302 | { |
1303 | int i; | |
1304 | FWCfgState *fw_cfg; | |
1305 | ||
df1f79fd | 1306 | assert(MACHINE(pcms)->kernel_filename != NULL); |
b33a5bbf | 1307 | |
305ae888 | 1308 | fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); |
e3cadac0 | 1309 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
b33a5bbf CL |
1310 | rom_set_fw(fw_cfg); |
1311 | ||
df1f79fd | 1312 | load_linux(pcms, fw_cfg); |
b33a5bbf CL |
1313 | for (i = 0; i < nb_option_roms; i++) { |
1314 | assert(!strcmp(option_rom[i].name, "linuxboot.bin") || | |
b2a575a1 | 1315 | !strcmp(option_rom[i].name, "linuxboot_dma.bin") || |
b33a5bbf CL |
1316 | !strcmp(option_rom[i].name, "multiboot.bin")); |
1317 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); | |
1318 | } | |
f264d360 | 1319 | pcms->fw_cfg = fw_cfg; |
b33a5bbf CL |
1320 | } |
1321 | ||
5934e216 EH |
1322 | void pc_memory_init(PCMachineState *pcms, |
1323 | MemoryRegion *system_memory, | |
1324 | MemoryRegion *rom_memory, | |
1325 | MemoryRegion **ram_memory) | |
80cabfad | 1326 | { |
cbc5b5f3 JJ |
1327 | int linux_boot, i; |
1328 | MemoryRegion *ram, *option_rom_mr; | |
00cb2a99 | 1329 | MemoryRegion *ram_below_4g, *ram_above_4g; |
a88b362c | 1330 | FWCfgState *fw_cfg; |
62b160c0 | 1331 | MachineState *machine = MACHINE(pcms); |
16a9e8a5 | 1332 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
d592d303 | 1333 | |
c8d163bc EH |
1334 | assert(machine->ram_size == pcms->below_4g_mem_size + |
1335 | pcms->above_4g_mem_size); | |
9521d42b PB |
1336 | |
1337 | linux_boot = (machine->kernel_filename != NULL); | |
80cabfad | 1338 | |
00cb2a99 | 1339 | /* Allocate RAM. We allocate it as a single memory region and use |
66a0a2cb | 1340 | * aliases to address portions of it, mostly for backwards compatibility |
00cb2a99 AK |
1341 | * with older qemus that used qemu_ram_alloc(). |
1342 | */ | |
7267c094 | 1343 | ram = g_malloc(sizeof(*ram)); |
9521d42b PB |
1344 | memory_region_allocate_system_memory(ram, NULL, "pc.ram", |
1345 | machine->ram_size); | |
ae0a5466 | 1346 | *ram_memory = ram; |
7267c094 | 1347 | ram_below_4g = g_malloc(sizeof(*ram_below_4g)); |
2c9b15ca | 1348 | memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, |
c8d163bc | 1349 | 0, pcms->below_4g_mem_size); |
00cb2a99 | 1350 | memory_region_add_subregion(system_memory, 0, ram_below_4g); |
c8d163bc EH |
1351 | e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); |
1352 | if (pcms->above_4g_mem_size > 0) { | |
7267c094 | 1353 | ram_above_4g = g_malloc(sizeof(*ram_above_4g)); |
2c9b15ca | 1354 | memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |
c8d163bc EH |
1355 | pcms->below_4g_mem_size, |
1356 | pcms->above_4g_mem_size); | |
00cb2a99 AK |
1357 | memory_region_add_subregion(system_memory, 0x100000000ULL, |
1358 | ram_above_4g); | |
c8d163bc | 1359 | e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); |
bbe80adf | 1360 | } |
82b36dc3 | 1361 | |
bb292f5a | 1362 | if (!pcmc->has_reserved_memory && |
ca8336f3 | 1363 | (machine->ram_slots || |
9521d42b | 1364 | (machine->maxram_size > machine->ram_size))) { |
ca8336f3 IM |
1365 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1366 | ||
1367 | error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", | |
1368 | mc->name); | |
1369 | exit(EXIT_FAILURE); | |
1370 | } | |
1371 | ||
619d11e4 | 1372 | /* initialize hotplug memory address space */ |
bb292f5a | 1373 | if (pcmc->has_reserved_memory && |
9521d42b | 1374 | (machine->ram_size < machine->maxram_size)) { |
619d11e4 | 1375 | ram_addr_t hotplug_mem_size = |
9521d42b | 1376 | machine->maxram_size - machine->ram_size; |
619d11e4 | 1377 | |
a0cc8856 IM |
1378 | if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1379 | error_report("unsupported amount of memory slots: %"PRIu64, | |
1380 | machine->ram_slots); | |
1381 | exit(EXIT_FAILURE); | |
1382 | } | |
1383 | ||
f2c38522 PK |
1384 | if (QEMU_ALIGN_UP(machine->maxram_size, |
1385 | TARGET_PAGE_SIZE) != machine->maxram_size) { | |
1386 | error_report("maximum memory size must by aligned to multiple of " | |
1387 | "%d bytes", TARGET_PAGE_SIZE); | |
1388 | exit(EXIT_FAILURE); | |
1389 | } | |
1390 | ||
a7d69ff1 | 1391 | pcms->hotplug_memory.base = |
c8d163bc | 1392 | ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); |
619d11e4 | 1393 | |
16a9e8a5 | 1394 | if (pcmc->enforce_aligned_dimm) { |
085f8e88 IM |
1395 | /* size hotplug region assuming 1G page max alignment per slot */ |
1396 | hotplug_mem_size += (1ULL << 30) * machine->ram_slots; | |
1397 | } | |
1398 | ||
a7d69ff1 | 1399 | if ((pcms->hotplug_memory.base + hotplug_mem_size) < |
619d11e4 IM |
1400 | hotplug_mem_size) { |
1401 | error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, | |
1402 | machine->maxram_size); | |
1403 | exit(EXIT_FAILURE); | |
1404 | } | |
1405 | ||
a7d69ff1 | 1406 | memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), |
619d11e4 | 1407 | "hotplug-memory", hotplug_mem_size); |
a7d69ff1 BR |
1408 | memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, |
1409 | &pcms->hotplug_memory.mr); | |
619d11e4 | 1410 | } |
cbc5b5f3 JJ |
1411 | |
1412 | /* Initialize PC system firmware */ | |
5db3f0de | 1413 | pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); |
00cb2a99 | 1414 | |
7267c094 | 1415 | option_rom_mr = g_malloc(sizeof(*option_rom_mr)); |
98a99ce0 | 1416 | memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, |
f8ed85ac | 1417 | &error_fatal); |
208fa0e4 IM |
1418 | if (pcmc->pci_enabled) { |
1419 | memory_region_set_readonly(option_rom_mr, true); | |
1420 | } | |
4463aee6 | 1421 | memory_region_add_subregion_overlap(rom_memory, |
00cb2a99 AK |
1422 | PC_ROM_MIN_VGA, |
1423 | option_rom_mr, | |
1424 | 1); | |
f753ff16 | 1425 | |
ebde2465 | 1426 | fw_cfg = bochs_bios_init(&address_space_memory, pcms); |
c886fc4c | 1427 | |
8832cb80 | 1428 | rom_set_fw(fw_cfg); |
1d108d97 | 1429 | |
bb292f5a | 1430 | if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { |
de268e13 | 1431 | uint64_t *val = g_malloc(sizeof(*val)); |
2f8b5008 IM |
1432 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
1433 | uint64_t res_mem_end = pcms->hotplug_memory.base; | |
1434 | ||
1435 | if (!pcmc->broken_reserved_end) { | |
1436 | res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); | |
1437 | } | |
3385e8e2 | 1438 | *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); |
de268e13 IM |
1439 | fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); |
1440 | } | |
1441 | ||
f753ff16 | 1442 | if (linux_boot) { |
df1f79fd | 1443 | load_linux(pcms, fw_cfg); |
f753ff16 PB |
1444 | } |
1445 | ||
1446 | for (i = 0; i < nb_option_roms; i++) { | |
2e55e842 | 1447 | rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
406c8df3 | 1448 | } |
f264d360 | 1449 | pcms->fw_cfg = fw_cfg; |
cb135f59 PX |
1450 | |
1451 | /* Init default IOAPIC address space */ | |
1452 | pcms->ioapic_as = &address_space_memory; | |
3d53f5c3 IY |
1453 | } |
1454 | ||
9fa99d25 MA |
1455 | /* |
1456 | * The 64bit pci hole starts after "above 4G RAM" and | |
1457 | * potentially the space reserved for memory hotplug. | |
1458 | */ | |
1459 | uint64_t pc_pci_hole64_start(void) | |
1460 | { | |
1461 | PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); | |
1462 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); | |
1463 | uint64_t hole64_start = 0; | |
1464 | ||
1465 | if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { | |
1466 | hole64_start = pcms->hotplug_memory.base; | |
1467 | if (!pcmc->broken_reserved_end) { | |
1468 | hole64_start += memory_region_size(&pcms->hotplug_memory.mr); | |
1469 | } | |
1470 | } else { | |
1471 | hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; | |
1472 | } | |
1473 | ||
1474 | return ROUND_UP(hole64_start, 1ULL << 30); | |
1475 | } | |
1476 | ||
0b0cc076 | 1477 | qemu_irq pc_allocate_cpu_irq(void) |
845773ab | 1478 | { |
0b0cc076 | 1479 | return qemu_allocate_irq(pic_irq_request, NULL, 0); |
845773ab IY |
1480 | } |
1481 | ||
48a18b3c | 1482 | DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) |
765d7908 | 1483 | { |
ad6d45fa AL |
1484 | DeviceState *dev = NULL; |
1485 | ||
bab47d9a | 1486 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); |
16094b75 AJ |
1487 | if (pci_bus) { |
1488 | PCIDevice *pcidev = pci_vga_init(pci_bus); | |
1489 | dev = pcidev ? &pcidev->qdev : NULL; | |
1490 | } else if (isa_bus) { | |
1491 | ISADevice *isadev = isa_vga_init(isa_bus); | |
4a17cc4f | 1492 | dev = isadev ? DEVICE(isadev) : NULL; |
765d7908 | 1493 | } |
bab47d9a | 1494 | rom_reset_order_override(); |
ad6d45fa | 1495 | return dev; |
765d7908 IY |
1496 | } |
1497 | ||
258711c6 JG |
1498 | static const MemoryRegionOps ioport80_io_ops = { |
1499 | .write = ioport80_write, | |
c02e1eac | 1500 | .read = ioport80_read, |
258711c6 JG |
1501 | .endianness = DEVICE_NATIVE_ENDIAN, |
1502 | .impl = { | |
1503 | .min_access_size = 1, | |
1504 | .max_access_size = 1, | |
1505 | }, | |
1506 | }; | |
1507 | ||
1508 | static const MemoryRegionOps ioportF0_io_ops = { | |
1509 | .write = ioportF0_write, | |
c02e1eac | 1510 | .read = ioportF0_read, |
258711c6 JG |
1511 | .endianness = DEVICE_NATIVE_ENDIAN, |
1512 | .impl = { | |
1513 | .min_access_size = 1, | |
1514 | .max_access_size = 1, | |
1515 | }, | |
1516 | }; | |
1517 | ||
48a18b3c | 1518 | void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, |
1611977c | 1519 | ISADevice **rtc_state, |
fd53c87c | 1520 | bool create_fdctrl, |
7a10ef51 | 1521 | bool no_vmport, |
feddd2fd | 1522 | bool has_pit, |
3a87d009 | 1523 | uint32_t hpet_irqs) |
ffe513da IY |
1524 | { |
1525 | int i; | |
1526 | DriveInfo *fd[MAX_FD]; | |
ce967e2f JK |
1527 | DeviceState *hpet = NULL; |
1528 | int pit_isa_irq = 0; | |
1529 | qemu_irq pit_alt_irq = NULL; | |
7d932dfd | 1530 | qemu_irq rtc_irq = NULL; |
956a3e6b | 1531 | qemu_irq *a20_line; |
c2d8d311 | 1532 | ISADevice *i8042, *port92, *vmmouse, *pit = NULL; |
258711c6 JG |
1533 | MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); |
1534 | MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); | |
ffe513da | 1535 | |
2c9b15ca | 1536 | memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); |
258711c6 | 1537 | memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); |
ffe513da | 1538 | |
2c9b15ca | 1539 | memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); |
258711c6 | 1540 | memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); |
ffe513da | 1541 | |
5d17c0d2 JK |
1542 | /* |
1543 | * Check if an HPET shall be created. | |
1544 | * | |
1545 | * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT | |
1546 | * when the HPET wants to take over. Thus we have to disable the latter. | |
1547 | */ | |
1548 | if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { | |
7a10ef51 | 1549 | /* In order to set property, here not using sysbus_try_create_simple */ |
51116102 | 1550 | hpet = qdev_try_create(NULL, TYPE_HPET); |
dd703b99 | 1551 | if (hpet) { |
7a10ef51 LPF |
1552 | /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 |
1553 | * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, | |
1554 | * IRQ8 and IRQ2. | |
1555 | */ | |
5d7fb0f2 | 1556 | uint8_t compat = object_property_get_uint(OBJECT(hpet), |
7a10ef51 LPF |
1557 | HPET_INTCAP, NULL); |
1558 | if (!compat) { | |
1559 | qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); | |
1560 | } | |
1561 | qdev_init_nofail(hpet); | |
1562 | sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); | |
1563 | ||
b881fbe9 | 1564 | for (i = 0; i < GSI_NUM_PINS; i++) { |
1356b98d | 1565 | sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); |
dd703b99 | 1566 | } |
ce967e2f JK |
1567 | pit_isa_irq = -1; |
1568 | pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); | |
1569 | rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); | |
822557eb | 1570 | } |
ffe513da | 1571 | } |
6c646a11 | 1572 | *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); |
7d932dfd JK |
1573 | |
1574 | qemu_register_boot_set(pc_boot_set, *rtc_state); | |
1575 | ||
feddd2fd | 1576 | if (!xen_enabled() && has_pit) { |
15eafc2e | 1577 | if (kvm_pit_in_kernel()) { |
c2d8d311 SS |
1578 | pit = kvm_pit_init(isa_bus, 0x40); |
1579 | } else { | |
acf695ec | 1580 | pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); |
c2d8d311 SS |
1581 | } |
1582 | if (hpet) { | |
1583 | /* connect PIT to output control line of the HPET */ | |
4a17cc4f | 1584 | qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); |
c2d8d311 SS |
1585 | } |
1586 | pcspk_init(isa_bus, pit); | |
ce967e2f | 1587 | } |
ffe513da | 1588 | |
4496dc49 | 1589 | serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); |
07dc7880 | 1590 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
ffe513da | 1591 | |
182735ef | 1592 | a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); |
48a18b3c | 1593 | i8042 = isa_create_simple(isa_bus, "i8042"); |
d80fe99d | 1594 | i8042_setup_a20_line(i8042, a20_line[0]); |
1611977c | 1595 | if (!no_vmport) { |
48a18b3c HP |
1596 | vmport_init(isa_bus); |
1597 | vmmouse = isa_try_create(isa_bus, "vmmouse"); | |
1611977c AP |
1598 | } else { |
1599 | vmmouse = NULL; | |
1600 | } | |
86d86414 | 1601 | if (vmmouse) { |
4a17cc4f AF |
1602 | DeviceState *dev = DEVICE(vmmouse); |
1603 | qdev_prop_set_ptr(dev, "ps2_mouse", i8042); | |
1604 | qdev_init_nofail(dev); | |
86d86414 | 1605 | } |
48a18b3c | 1606 | port92 = isa_create_simple(isa_bus, "port92"); |
d80fe99d | 1607 | port92_init(port92, a20_line[1]); |
ac64c5fd | 1608 | g_free(a20_line); |
956a3e6b | 1609 | |
57146941 | 1610 | DMA_init(isa_bus, 0); |
ffe513da IY |
1611 | |
1612 | for(i = 0; i < MAX_FD; i++) { | |
1613 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
936a7c1c | 1614 | create_fdctrl |= !!fd[i]; |
ffe513da | 1615 | } |
220a8846 LE |
1616 | if (create_fdctrl) { |
1617 | fdctrl_init_isa(isa_bus, fd); | |
1618 | } | |
ffe513da IY |
1619 | } |
1620 | ||
9011a1a7 IY |
1621 | void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) |
1622 | { | |
1623 | int i; | |
1624 | ||
bab47d9a | 1625 | rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); |
9011a1a7 IY |
1626 | for (i = 0; i < nb_nics; i++) { |
1627 | NICInfo *nd = &nd_table[i]; | |
1628 | ||
1629 | if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { | |
1630 | pc_init_ne2k_isa(isa_bus, nd); | |
1631 | } else { | |
29b358f9 | 1632 | pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); |
9011a1a7 IY |
1633 | } |
1634 | } | |
bab47d9a | 1635 | rom_reset_order_override(); |
9011a1a7 IY |
1636 | } |
1637 | ||
845773ab | 1638 | void pc_pci_device_init(PCIBus *pci_bus) |
e3a5cf42 IY |
1639 | { |
1640 | int max_bus; | |
1641 | int bus; | |
1642 | ||
f778a82f | 1643 | /* Note: if=scsi is deprecated with PC machine types */ |
e3a5cf42 IY |
1644 | max_bus = drive_get_max_bus(IF_SCSI); |
1645 | for (bus = 0; bus <= max_bus; bus++) { | |
f778a82f MA |
1646 | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1647 | /* | |
1648 | * By not creating frontends here, we make | |
1649 | * scsi_legacy_handle_cmdline() create them, and warn that | |
1650 | * this usage is deprecated. | |
1651 | */ | |
e3a5cf42 IY |
1652 | } |
1653 | } | |
a39e3564 JB |
1654 | |
1655 | void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) | |
1656 | { | |
1657 | DeviceState *dev; | |
1658 | SysBusDevice *d; | |
1659 | unsigned int i; | |
1660 | ||
15eafc2e | 1661 | if (kvm_ioapic_in_kernel()) { |
a39e3564 JB |
1662 | dev = qdev_create(NULL, "kvm-ioapic"); |
1663 | } else { | |
1664 | dev = qdev_create(NULL, "ioapic"); | |
1665 | } | |
1666 | if (parent_name) { | |
1667 | object_property_add_child(object_resolve_path(parent_name, NULL), | |
1668 | "ioapic", OBJECT(dev), NULL); | |
1669 | } | |
1670 | qdev_init_nofail(dev); | |
1356b98d | 1671 | d = SYS_BUS_DEVICE(dev); |
3a4a4697 | 1672 | sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); |
a39e3564 JB |
1673 | |
1674 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
1675 | gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); | |
1676 | } | |
1677 | } | |
d5747cac | 1678 | |
95bee274 IM |
1679 | static void pc_dimm_plug(HotplugHandler *hotplug_dev, |
1680 | DeviceState *dev, Error **errp) | |
1681 | { | |
3fbcdc27 | 1682 | HotplugHandlerClass *hhc; |
95bee274 IM |
1683 | Error *local_err = NULL; |
1684 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
16a9e8a5 | 1685 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); |
95bee274 IM |
1686 | PCDIMMDevice *dimm = PC_DIMM(dev); |
1687 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 1688 | MemoryRegion *mr; |
92a37a04 | 1689 | uint64_t align = TARGET_PAGE_SIZE; |
7f3cf2d6 | 1690 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
95bee274 | 1691 | |
04790978 TH |
1692 | mr = ddc->get_memory_region(dimm, &local_err); |
1693 | if (local_err) { | |
1694 | goto out; | |
1695 | } | |
1696 | ||
16a9e8a5 | 1697 | if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { |
91aa70ab IM |
1698 | align = memory_region_get_alignment(mr); |
1699 | } | |
1700 | ||
8cd91ace HZ |
1701 | /* |
1702 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1703 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1704 | * addition to cover this case. | |
1705 | */ | |
1706 | if (!pcms->acpi_dev || !acpi_enabled) { | |
3fbcdc27 | 1707 | error_setg(&local_err, |
8cd91ace | 1708 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
3fbcdc27 IM |
1709 | goto out; |
1710 | } | |
1711 | ||
7f3cf2d6 SH |
1712 | if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) { |
1713 | error_setg(&local_err, | |
1714 | "nvdimm is not enabled: missing 'nvdimm' in '-M'"); | |
1715 | goto out; | |
1716 | } | |
1717 | ||
d6a9b0b8 | 1718 | pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); |
43bbb49e | 1719 | if (local_err) { |
b8865591 IM |
1720 | goto out; |
1721 | } | |
1722 | ||
7f3cf2d6 | 1723 | if (is_nvdimm) { |
284197e4 | 1724 | nvdimm_plug(&pcms->acpi_nvdimm_state); |
c7f8d0f3 XG |
1725 | } |
1726 | ||
3fbcdc27 | 1727 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
8e23184b | 1728 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); |
95bee274 IM |
1729 | out: |
1730 | error_propagate(errp, local_err); | |
1731 | } | |
1732 | ||
64fec58e TC |
1733 | static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, |
1734 | DeviceState *dev, Error **errp) | |
1735 | { | |
1736 | HotplugHandlerClass *hhc; | |
1737 | Error *local_err = NULL; | |
1738 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1739 | ||
8cd91ace HZ |
1740 | /* |
1741 | * When -no-acpi is used with Q35 machine type, no ACPI is built, | |
1742 | * but pcms->acpi_dev is still created. Check !acpi_enabled in | |
1743 | * addition to cover this case. | |
1744 | */ | |
1745 | if (!pcms->acpi_dev || !acpi_enabled) { | |
64fec58e | 1746 | error_setg(&local_err, |
8cd91ace | 1747 | "memory hotplug is not enabled: missing acpi device or acpi disabled"); |
64fec58e TC |
1748 | goto out; |
1749 | } | |
1750 | ||
b097cc52 XG |
1751 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
1752 | error_setg(&local_err, | |
1753 | "nvdimm device hot unplug is not supported yet."); | |
1754 | goto out; | |
1755 | } | |
1756 | ||
64fec58e TC |
1757 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1758 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1759 | ||
1760 | out: | |
1761 | error_propagate(errp, local_err); | |
1762 | } | |
1763 | ||
f7d3e29d TC |
1764 | static void pc_dimm_unplug(HotplugHandler *hotplug_dev, |
1765 | DeviceState *dev, Error **errp) | |
1766 | { | |
1767 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); | |
1768 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
1769 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
04790978 | 1770 | MemoryRegion *mr; |
f7d3e29d TC |
1771 | HotplugHandlerClass *hhc; |
1772 | Error *local_err = NULL; | |
1773 | ||
04790978 TH |
1774 | mr = ddc->get_memory_region(dimm, &local_err); |
1775 | if (local_err) { | |
1776 | goto out; | |
1777 | } | |
1778 | ||
f7d3e29d TC |
1779 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1780 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1781 | ||
1782 | if (local_err) { | |
1783 | goto out; | |
1784 | } | |
1785 | ||
43bbb49e | 1786 | pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); |
f7d3e29d TC |
1787 | object_unparent(OBJECT(dev)); |
1788 | ||
1789 | out: | |
1790 | error_propagate(errp, local_err); | |
1791 | } | |
1792 | ||
3811ef14 IM |
1793 | static int pc_apic_cmp(const void *a, const void *b) |
1794 | { | |
1795 | CPUArchId *apic_a = (CPUArchId *)a; | |
1796 | CPUArchId *apic_b = (CPUArchId *)b; | |
1797 | ||
1798 | return apic_a->arch_id - apic_b->arch_id; | |
1799 | } | |
1800 | ||
7baef5cf | 1801 | /* returns pointer to CPUArchId descriptor that matches CPU's apic_id |
38690a1c | 1802 | * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no |
b12227af | 1803 | * entry corresponding to CPU's apic_id returns NULL. |
7baef5cf | 1804 | */ |
1ea69c0e | 1805 | static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) |
7baef5cf | 1806 | { |
7baef5cf IM |
1807 | CPUArchId apic_id, *found_cpu; |
1808 | ||
1ea69c0e | 1809 | apic_id.arch_id = id; |
38690a1c IM |
1810 | found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, |
1811 | ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), | |
7baef5cf IM |
1812 | pc_apic_cmp); |
1813 | if (found_cpu && idx) { | |
38690a1c | 1814 | *idx = found_cpu - ms->possible_cpus->cpus; |
7baef5cf IM |
1815 | } |
1816 | return found_cpu; | |
1817 | } | |
1818 | ||
5279569e GZ |
1819 | static void pc_cpu_plug(HotplugHandler *hotplug_dev, |
1820 | DeviceState *dev, Error **errp) | |
1821 | { | |
7baef5cf | 1822 | CPUArchId *found_cpu; |
5279569e GZ |
1823 | HotplugHandlerClass *hhc; |
1824 | Error *local_err = NULL; | |
1ea69c0e | 1825 | X86CPU *cpu = X86_CPU(dev); |
5279569e GZ |
1826 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1827 | ||
a44a49db IM |
1828 | if (pcms->acpi_dev) { |
1829 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1830 | hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1831 | if (local_err) { | |
1832 | goto out; | |
1833 | } | |
5279569e GZ |
1834 | } |
1835 | ||
e3cadac0 IM |
1836 | /* increment the number of CPUs */ |
1837 | pcms->boot_cpus++; | |
26ef65be | 1838 | if (pcms->rtc) { |
e3cadac0 | 1839 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); |
26ef65be IM |
1840 | } |
1841 | if (pcms->fw_cfg) { | |
e3cadac0 | 1842 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); |
2d996150 GZ |
1843 | } |
1844 | ||
1ea69c0e | 1845 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8aba3842 | 1846 | found_cpu->cpu = OBJECT(dev); |
5279569e GZ |
1847 | out: |
1848 | error_propagate(errp, local_err); | |
1849 | } | |
8872c25a IM |
1850 | static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
1851 | DeviceState *dev, Error **errp) | |
1852 | { | |
73360e27 | 1853 | int idx = -1; |
8872c25a IM |
1854 | HotplugHandlerClass *hhc; |
1855 | Error *local_err = NULL; | |
1ea69c0e | 1856 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1857 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1858 | ||
75ba2ddb IM |
1859 | if (!pcms->acpi_dev) { |
1860 | error_setg(&local_err, "CPU hot unplug not supported without ACPI"); | |
1861 | goto out; | |
1862 | } | |
1863 | ||
1ea69c0e | 1864 | pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
73360e27 IM |
1865 | assert(idx != -1); |
1866 | if (idx == 0) { | |
1867 | error_setg(&local_err, "Boot CPU is unpluggable"); | |
1868 | goto out; | |
1869 | } | |
1870 | ||
8872c25a IM |
1871 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); |
1872 | hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1873 | ||
1874 | if (local_err) { | |
1875 | goto out; | |
1876 | } | |
1877 | ||
1878 | out: | |
1879 | error_propagate(errp, local_err); | |
1880 | ||
1881 | } | |
1882 | ||
1883 | static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, | |
1884 | DeviceState *dev, Error **errp) | |
1885 | { | |
8fe6374e | 1886 | CPUArchId *found_cpu; |
8872c25a IM |
1887 | HotplugHandlerClass *hhc; |
1888 | Error *local_err = NULL; | |
1ea69c0e | 1889 | X86CPU *cpu = X86_CPU(dev); |
8872c25a IM |
1890 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
1891 | ||
1892 | hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); | |
1893 | hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); | |
1894 | ||
1895 | if (local_err) { | |
1896 | goto out; | |
1897 | } | |
1898 | ||
1ea69c0e | 1899 | found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); |
8fe6374e IM |
1900 | found_cpu->cpu = NULL; |
1901 | object_unparent(OBJECT(dev)); | |
8872c25a | 1902 | |
e3cadac0 IM |
1903 | /* decrement the number of CPUs */ |
1904 | pcms->boot_cpus--; | |
1905 | /* Update the number of CPUs in CMOS */ | |
1906 | rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); | |
1907 | fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); | |
8872c25a IM |
1908 | out: |
1909 | error_propagate(errp, local_err); | |
1910 | } | |
5279569e | 1911 | |
4ec60c76 IM |
1912 | static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, |
1913 | DeviceState *dev, Error **errp) | |
1914 | { | |
1915 | int idx; | |
a15d2728 | 1916 | CPUState *cs; |
e8f7b83e | 1917 | CPUArchId *cpu_slot; |
d89c2b8b | 1918 | X86CPUTopoInfo topo; |
4ec60c76 | 1919 | X86CPU *cpu = X86_CPU(dev); |
6970c5ff | 1920 | MachineState *ms = MACHINE(hotplug_dev); |
4ec60c76 | 1921 | PCMachineState *pcms = PC_MACHINE(hotplug_dev); |
4ec60c76 | 1922 | |
6970c5ff IM |
1923 | if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { |
1924 | error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", | |
1925 | ms->cpu_type); | |
1926 | return; | |
1927 | } | |
1928 | ||
e8f7b83e IM |
1929 | /* if APIC ID is not set, set it based on socket/core/thread properties */ |
1930 | if (cpu->apic_id == UNASSIGNED_APIC_ID) { | |
1931 | int max_socket = (max_cpus - 1) / smp_threads / smp_cores; | |
1932 | ||
1933 | if (cpu->socket_id < 0) { | |
1934 | error_setg(errp, "CPU socket-id is not set"); | |
1935 | return; | |
1936 | } else if (cpu->socket_id > max_socket) { | |
1937 | error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", | |
1938 | cpu->socket_id, max_socket); | |
1939 | return; | |
1940 | } | |
1941 | if (cpu->core_id < 0) { | |
1942 | error_setg(errp, "CPU core-id is not set"); | |
1943 | return; | |
1944 | } else if (cpu->core_id > (smp_cores - 1)) { | |
1945 | error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", | |
1946 | cpu->core_id, smp_cores - 1); | |
1947 | return; | |
1948 | } | |
1949 | if (cpu->thread_id < 0) { | |
1950 | error_setg(errp, "CPU thread-id is not set"); | |
1951 | return; | |
1952 | } else if (cpu->thread_id > (smp_threads - 1)) { | |
1953 | error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", | |
1954 | cpu->thread_id, smp_threads - 1); | |
1955 | return; | |
1956 | } | |
1957 | ||
1958 | topo.pkg_id = cpu->socket_id; | |
1959 | topo.core_id = cpu->core_id; | |
1960 | topo.smt_id = cpu->thread_id; | |
1961 | cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); | |
1962 | } | |
1963 | ||
1ea69c0e | 1964 | cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); |
4ec60c76 | 1965 | if (!cpu_slot) { |
38690a1c IM |
1966 | MachineState *ms = MACHINE(pcms); |
1967 | ||
e8f7b83e IM |
1968 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); |
1969 | error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" | |
1970 | " APIC ID %" PRIu32 ", valid index range 0:%d", | |
1971 | topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, | |
38690a1c | 1972 | ms->possible_cpus->len - 1); |
4ec60c76 IM |
1973 | return; |
1974 | } | |
1975 | ||
1976 | if (cpu_slot->cpu) { | |
1977 | error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", | |
1978 | idx, cpu->apic_id); | |
1979 | return; | |
1980 | } | |
d89c2b8b IM |
1981 | |
1982 | /* if 'address' properties socket-id/core-id/thread-id are not set, set them | |
c5514d0e | 1983 | * so that machine_query_hotpluggable_cpus would show correct values |
d89c2b8b IM |
1984 | */ |
1985 | /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() | |
1986 | * once -smp refactoring is complete and there will be CPU private | |
1987 | * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ | |
1988 | x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); | |
1989 | if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { | |
1990 | error_setg(errp, "property socket-id: %u doesn't match set apic-id:" | |
1991 | " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); | |
1992 | return; | |
1993 | } | |
1994 | cpu->socket_id = topo.pkg_id; | |
1995 | ||
1996 | if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { | |
1997 | error_setg(errp, "property core-id: %u doesn't match set apic-id:" | |
1998 | " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); | |
1999 | return; | |
2000 | } | |
2001 | cpu->core_id = topo.core_id; | |
2002 | ||
2003 | if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { | |
2004 | error_setg(errp, "property thread-id: %u doesn't match set apic-id:" | |
2005 | " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); | |
2006 | return; | |
2007 | } | |
2008 | cpu->thread_id = topo.smt_id; | |
a15d2728 IM |
2009 | |
2010 | cs = CPU(cpu); | |
2011 | cs->cpu_index = idx; | |
93b2a8cb | 2012 | |
a0ceb640 | 2013 | numa_cpu_pre_plug(cpu_slot, dev, errp); |
4ec60c76 IM |
2014 | } |
2015 | ||
2016 | static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
2017 | DeviceState *dev, Error **errp) | |
2018 | { | |
2019 | if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
2020 | pc_cpu_pre_plug(hotplug_dev, dev, errp); | |
2021 | } | |
2022 | } | |
2023 | ||
95bee274 IM |
2024 | static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
2025 | DeviceState *dev, Error **errp) | |
2026 | { | |
2027 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2028 | pc_dimm_plug(hotplug_dev, dev, errp); | |
5279569e GZ |
2029 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2030 | pc_cpu_plug(hotplug_dev, dev, errp); | |
95bee274 IM |
2031 | } |
2032 | } | |
2033 | ||
d9c5c5b8 TC |
2034 | static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
2035 | DeviceState *dev, Error **errp) | |
2036 | { | |
64fec58e TC |
2037 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2038 | pc_dimm_unplug_request(hotplug_dev, dev, errp); | |
8872c25a IM |
2039 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2040 | pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); | |
64fec58e TC |
2041 | } else { |
2042 | error_setg(errp, "acpi: device unplug request for not supported device" | |
2043 | " type: %s", object_get_typename(OBJECT(dev))); | |
2044 | } | |
d9c5c5b8 TC |
2045 | } |
2046 | ||
232391c1 TC |
2047 | static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, |
2048 | DeviceState *dev, Error **errp) | |
2049 | { | |
f7d3e29d TC |
2050 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2051 | pc_dimm_unplug(hotplug_dev, dev, errp); | |
8872c25a IM |
2052 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
2053 | pc_cpu_unplug_cb(hotplug_dev, dev, errp); | |
f7d3e29d TC |
2054 | } else { |
2055 | error_setg(errp, "acpi: device unplug for not supported device" | |
2056 | " type: %s", object_get_typename(OBJECT(dev))); | |
2057 | } | |
232391c1 TC |
2058 | } |
2059 | ||
95bee274 IM |
2060 | static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, |
2061 | DeviceState *dev) | |
2062 | { | |
2063 | PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); | |
2064 | ||
5279569e GZ |
2065 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2066 | object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { | |
95bee274 IM |
2067 | return HOTPLUG_HANDLER(machine); |
2068 | } | |
2069 | ||
2070 | return pcmc->get_hotplug_handler ? | |
2071 | pcmc->get_hotplug_handler(machine, dev) : NULL; | |
2072 | } | |
2073 | ||
bf1e8939 | 2074 | static void |
d7bce999 EB |
2075 | pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, |
2076 | const char *name, void *opaque, | |
2077 | Error **errp) | |
bf1e8939 IM |
2078 | { |
2079 | PCMachineState *pcms = PC_MACHINE(obj); | |
a7d69ff1 | 2080 | int64_t value = memory_region_size(&pcms->hotplug_memory.mr); |
bf1e8939 | 2081 | |
51e72bc1 | 2082 | visit_type_int(v, name, &value, errp); |
bf1e8939 IM |
2083 | } |
2084 | ||
c87b1520 | 2085 | static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, |
d7bce999 EB |
2086 | const char *name, void *opaque, |
2087 | Error **errp) | |
c87b1520 DS |
2088 | { |
2089 | PCMachineState *pcms = PC_MACHINE(obj); | |
2090 | uint64_t value = pcms->max_ram_below_4g; | |
2091 | ||
51e72bc1 | 2092 | visit_type_size(v, name, &value, errp); |
c87b1520 DS |
2093 | } |
2094 | ||
2095 | static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, | |
d7bce999 EB |
2096 | const char *name, void *opaque, |
2097 | Error **errp) | |
c87b1520 DS |
2098 | { |
2099 | PCMachineState *pcms = PC_MACHINE(obj); | |
2100 | Error *error = NULL; | |
2101 | uint64_t value; | |
2102 | ||
51e72bc1 | 2103 | visit_type_size(v, name, &value, &error); |
c87b1520 DS |
2104 | if (error) { |
2105 | error_propagate(errp, error); | |
2106 | return; | |
2107 | } | |
2108 | if (value > (1ULL << 32)) { | |
455b0fde EB |
2109 | error_setg(&error, |
2110 | "Machine option 'max-ram-below-4g=%"PRIu64 | |
2111 | "' expects size less than or equal to 4G", value); | |
c87b1520 DS |
2112 | error_propagate(errp, error); |
2113 | return; | |
2114 | } | |
2115 | ||
2116 | if (value < (1ULL << 20)) { | |
9e5d2c52 AF |
2117 | warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," |
2118 | "BIOS may not work with less than 1MiB", value); | |
c87b1520 DS |
2119 | } |
2120 | ||
2121 | pcms->max_ram_below_4g = value; | |
2122 | } | |
2123 | ||
d7bce999 EB |
2124 | static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, |
2125 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2126 | { |
2127 | PCMachineState *pcms = PC_MACHINE(obj); | |
d1048bef | 2128 | OnOffAuto vmport = pcms->vmport; |
9b23cfb7 | 2129 | |
51e72bc1 | 2130 | visit_type_OnOffAuto(v, name, &vmport, errp); |
9b23cfb7 DDAG |
2131 | } |
2132 | ||
d7bce999 EB |
2133 | static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, |
2134 | void *opaque, Error **errp) | |
9b23cfb7 DDAG |
2135 | { |
2136 | PCMachineState *pcms = PC_MACHINE(obj); | |
2137 | ||
51e72bc1 | 2138 | visit_type_OnOffAuto(v, name, &pcms->vmport, errp); |
9b23cfb7 DDAG |
2139 | } |
2140 | ||
355023f2 PB |
2141 | bool pc_machine_is_smm_enabled(PCMachineState *pcms) |
2142 | { | |
2143 | bool smm_available = false; | |
2144 | ||
2145 | if (pcms->smm == ON_OFF_AUTO_OFF) { | |
2146 | return false; | |
2147 | } | |
2148 | ||
2149 | if (tcg_enabled() || qtest_enabled()) { | |
2150 | smm_available = true; | |
2151 | } else if (kvm_enabled()) { | |
2152 | smm_available = kvm_has_smm(); | |
2153 | } | |
2154 | ||
2155 | if (smm_available) { | |
2156 | return true; | |
2157 | } | |
2158 | ||
2159 | if (pcms->smm == ON_OFF_AUTO_ON) { | |
2160 | error_report("System Management Mode not supported by this hypervisor."); | |
2161 | exit(1); | |
2162 | } | |
2163 | return false; | |
2164 | } | |
2165 | ||
d7bce999 EB |
2166 | static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, |
2167 | void *opaque, Error **errp) | |
355023f2 PB |
2168 | { |
2169 | PCMachineState *pcms = PC_MACHINE(obj); | |
2170 | OnOffAuto smm = pcms->smm; | |
2171 | ||
51e72bc1 | 2172 | visit_type_OnOffAuto(v, name, &smm, errp); |
355023f2 PB |
2173 | } |
2174 | ||
d7bce999 EB |
2175 | static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, |
2176 | void *opaque, Error **errp) | |
355023f2 PB |
2177 | { |
2178 | PCMachineState *pcms = PC_MACHINE(obj); | |
2179 | ||
51e72bc1 | 2180 | visit_type_OnOffAuto(v, name, &pcms->smm, errp); |
355023f2 PB |
2181 | } |
2182 | ||
87252e1b XG |
2183 | static bool pc_machine_get_nvdimm(Object *obj, Error **errp) |
2184 | { | |
2185 | PCMachineState *pcms = PC_MACHINE(obj); | |
2186 | ||
5fe79386 | 2187 | return pcms->acpi_nvdimm_state.is_enabled; |
87252e1b XG |
2188 | } |
2189 | ||
2190 | static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
2191 | { | |
2192 | PCMachineState *pcms = PC_MACHINE(obj); | |
2193 | ||
5fe79386 | 2194 | pcms->acpi_nvdimm_state.is_enabled = value; |
87252e1b XG |
2195 | } |
2196 | ||
be232eb0 CP |
2197 | static bool pc_machine_get_smbus(Object *obj, Error **errp) |
2198 | { | |
2199 | PCMachineState *pcms = PC_MACHINE(obj); | |
2200 | ||
2201 | return pcms->smbus; | |
2202 | } | |
2203 | ||
2204 | static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) | |
2205 | { | |
2206 | PCMachineState *pcms = PC_MACHINE(obj); | |
2207 | ||
2208 | pcms->smbus = value; | |
2209 | } | |
2210 | ||
272f0428 CP |
2211 | static bool pc_machine_get_sata(Object *obj, Error **errp) |
2212 | { | |
2213 | PCMachineState *pcms = PC_MACHINE(obj); | |
2214 | ||
2215 | return pcms->sata; | |
2216 | } | |
2217 | ||
2218 | static void pc_machine_set_sata(Object *obj, bool value, Error **errp) | |
2219 | { | |
2220 | PCMachineState *pcms = PC_MACHINE(obj); | |
2221 | ||
2222 | pcms->sata = value; | |
2223 | } | |
2224 | ||
feddd2fd CP |
2225 | static bool pc_machine_get_pit(Object *obj, Error **errp) |
2226 | { | |
2227 | PCMachineState *pcms = PC_MACHINE(obj); | |
2228 | ||
2229 | return pcms->pit; | |
2230 | } | |
2231 | ||
2232 | static void pc_machine_set_pit(Object *obj, bool value, Error **errp) | |
2233 | { | |
2234 | PCMachineState *pcms = PC_MACHINE(obj); | |
2235 | ||
2236 | pcms->pit = value; | |
2237 | } | |
2238 | ||
bf1e8939 IM |
2239 | static void pc_machine_initfn(Object *obj) |
2240 | { | |
c87b1520 DS |
2241 | PCMachineState *pcms = PC_MACHINE(obj); |
2242 | ||
5ec7d098 | 2243 | pcms->max_ram_below_4g = 0; /* use default */ |
355023f2 | 2244 | pcms->smm = ON_OFF_AUTO_AUTO; |
d1048bef | 2245 | pcms->vmport = ON_OFF_AUTO_AUTO; |
87252e1b | 2246 | /* nvdimm is disabled on default. */ |
5fe79386 | 2247 | pcms->acpi_nvdimm_state.is_enabled = false; |
021746c1 WL |
2248 | /* acpi build is enabled by default if machine supports it */ |
2249 | pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; | |
be232eb0 | 2250 | pcms->smbus = true; |
272f0428 | 2251 | pcms->sata = true; |
feddd2fd | 2252 | pcms->pit = true; |
bf1e8939 IM |
2253 | } |
2254 | ||
ae50c55a ZG |
2255 | static void pc_machine_reset(void) |
2256 | { | |
2257 | CPUState *cs; | |
2258 | X86CPU *cpu; | |
2259 | ||
2260 | qemu_devices_reset(); | |
2261 | ||
2262 | /* Reset APIC after devices have been reset to cancel | |
2263 | * any changes that qemu_devices_reset() might have done. | |
2264 | */ | |
2265 | CPU_FOREACH(cs) { | |
2266 | cpu = X86_CPU(cs); | |
2267 | ||
2268 | if (cpu->apic_state) { | |
2269 | device_reset(cpu->apic_state); | |
2270 | } | |
2271 | } | |
2272 | } | |
2273 | ||
ea089eeb IM |
2274 | static CpuInstanceProperties |
2275 | pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
fb43b73b | 2276 | { |
ea089eeb IM |
2277 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
2278 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
2279 | ||
2280 | assert(cpu_index < possible_cpus->len); | |
2281 | return possible_cpus->cpus[cpu_index].props; | |
fb43b73b IM |
2282 | } |
2283 | ||
79e07936 IM |
2284 | static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) |
2285 | { | |
2286 | X86CPUTopoInfo topo; | |
2287 | ||
2288 | assert(idx < ms->possible_cpus->len); | |
2289 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, | |
2290 | smp_cores, smp_threads, &topo); | |
2291 | return topo.pkg_id % nb_numa_nodes; | |
2292 | } | |
2293 | ||
c96a1c0b | 2294 | static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) |
3811ef14 | 2295 | { |
c96a1c0b IM |
2296 | int i; |
2297 | ||
2298 | if (ms->possible_cpus) { | |
2299 | /* | |
2300 | * make sure that max_cpus hasn't changed since the first use, i.e. | |
2301 | * -smp hasn't been parsed after it | |
2302 | */ | |
2303 | assert(ms->possible_cpus->len == max_cpus); | |
2304 | return ms->possible_cpus; | |
2305 | } | |
2306 | ||
2307 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
2308 | sizeof(CPUArchId) * max_cpus); | |
2309 | ms->possible_cpus->len = max_cpus; | |
2310 | for (i = 0; i < ms->possible_cpus->len; i++) { | |
c67ae933 IM |
2311 | X86CPUTopoInfo topo; |
2312 | ||
d342eb76 | 2313 | ms->possible_cpus->cpus[i].type = ms->cpu_type; |
f2d672c2 | 2314 | ms->possible_cpus->cpus[i].vcpus_count = 1; |
c96a1c0b | 2315 | ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); |
c67ae933 IM |
2316 | x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, |
2317 | smp_cores, smp_threads, &topo); | |
2318 | ms->possible_cpus->cpus[i].props.has_socket_id = true; | |
2319 | ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; | |
2320 | ms->possible_cpus->cpus[i].props.has_core_id = true; | |
2321 | ms->possible_cpus->cpus[i].props.core_id = topo.core_id; | |
2322 | ms->possible_cpus->cpus[i].props.has_thread_id = true; | |
2323 | ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; | |
c96a1c0b IM |
2324 | } |
2325 | return ms->possible_cpus; | |
3811ef14 IM |
2326 | } |
2327 | ||
1255166b BD |
2328 | static void x86_nmi(NMIState *n, int cpu_index, Error **errp) |
2329 | { | |
2330 | /* cpu index isn't used */ | |
2331 | CPUState *cs; | |
2332 | ||
2333 | CPU_FOREACH(cs) { | |
2334 | X86CPU *cpu = X86_CPU(cs); | |
2335 | ||
2336 | if (!cpu->apic_state) { | |
2337 | cpu_interrupt(cs, CPU_INTERRUPT_NMI); | |
2338 | } else { | |
2339 | apic_deliver_nmi(cpu->apic_state); | |
2340 | } | |
2341 | } | |
2342 | } | |
2343 | ||
95bee274 IM |
2344 | static void pc_machine_class_init(ObjectClass *oc, void *data) |
2345 | { | |
2346 | MachineClass *mc = MACHINE_CLASS(oc); | |
2347 | PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); | |
2348 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); | |
1255166b | 2349 | NMIClass *nc = NMI_CLASS(oc); |
95bee274 IM |
2350 | |
2351 | pcmc->get_hotplug_handler = mc->get_hotplug_handler; | |
7102fa70 EH |
2352 | pcmc->pci_enabled = true; |
2353 | pcmc->has_acpi_build = true; | |
2354 | pcmc->rsdp_in_ram = true; | |
2355 | pcmc->smbios_defaults = true; | |
2356 | pcmc->smbios_uuid_encoded = true; | |
2357 | pcmc->gigabyte_align = true; | |
2358 | pcmc->has_reserved_memory = true; | |
2359 | pcmc->kvmclock_enabled = true; | |
16a9e8a5 | 2360 | pcmc->enforce_aligned_dimm = true; |
cd4040ec EH |
2361 | /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported |
2362 | * to be used at the moment, 32K should be enough for a while. */ | |
2363 | pcmc->acpi_data_size = 0x20000 + 0x8000; | |
36f96c4b | 2364 | pcmc->save_tsc_khz = true; |
98e753a6 | 2365 | pcmc->linuxboot_dma_enabled = true; |
95bee274 | 2366 | mc->get_hotplug_handler = pc_get_hotpug_handler; |
ea089eeb | 2367 | mc->cpu_index_to_instance_props = pc_cpu_index_to_props; |
79e07936 | 2368 | mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; |
3811ef14 | 2369 | mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; |
7b8be49d | 2370 | mc->auto_enable_numa_with_memhp = true; |
c5514d0e | 2371 | mc->has_hotpluggable_cpus = true; |
41742767 | 2372 | mc->default_boot_order = "cad"; |
4458fb3a | 2373 | mc->hot_add_cpu = pc_hot_add_cpu; |
2059839b | 2374 | mc->block_default_type = IF_IDE; |
4458fb3a | 2375 | mc->max_cpus = 255; |
ae50c55a | 2376 | mc->reset = pc_machine_reset; |
4ec60c76 | 2377 | hc->pre_plug = pc_machine_device_pre_plug_cb; |
95bee274 | 2378 | hc->plug = pc_machine_device_plug_cb; |
d9c5c5b8 | 2379 | hc->unplug_request = pc_machine_device_unplug_request_cb; |
232391c1 | 2380 | hc->unplug = pc_machine_device_unplug_cb; |
1255166b | 2381 | nc->nmi_monitor_handler = x86_nmi; |
311ca98d | 2382 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; |
0efc257d EH |
2383 | |
2384 | object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", | |
2385 | pc_machine_get_hotplug_memory_region_size, NULL, | |
2386 | NULL, NULL, &error_abort); | |
2387 | ||
2388 | object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", | |
2389 | pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, | |
2390 | NULL, NULL, &error_abort); | |
2391 | ||
2392 | object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, | |
2393 | "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); | |
2394 | ||
2395 | object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", | |
2396 | pc_machine_get_smm, pc_machine_set_smm, | |
2397 | NULL, NULL, &error_abort); | |
2398 | object_class_property_set_description(oc, PC_MACHINE_SMM, | |
2399 | "Enable SMM (pc & q35)", &error_abort); | |
2400 | ||
2401 | object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", | |
2402 | pc_machine_get_vmport, pc_machine_set_vmport, | |
2403 | NULL, NULL, &error_abort); | |
2404 | object_class_property_set_description(oc, PC_MACHINE_VMPORT, | |
2405 | "Enable vmport (pc & q35)", &error_abort); | |
2406 | ||
2407 | object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, | |
2408 | pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); | |
be232eb0 CP |
2409 | |
2410 | object_class_property_add_bool(oc, PC_MACHINE_SMBUS, | |
2411 | pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); | |
272f0428 CP |
2412 | |
2413 | object_class_property_add_bool(oc, PC_MACHINE_SATA, | |
2414 | pc_machine_get_sata, pc_machine_set_sata, &error_abort); | |
feddd2fd CP |
2415 | |
2416 | object_class_property_add_bool(oc, PC_MACHINE_PIT, | |
2417 | pc_machine_get_pit, pc_machine_set_pit, &error_abort); | |
95bee274 IM |
2418 | } |
2419 | ||
d5747cac IM |
2420 | static const TypeInfo pc_machine_info = { |
2421 | .name = TYPE_PC_MACHINE, | |
2422 | .parent = TYPE_MACHINE, | |
2423 | .abstract = true, | |
2424 | .instance_size = sizeof(PCMachineState), | |
bf1e8939 | 2425 | .instance_init = pc_machine_initfn, |
d5747cac | 2426 | .class_size = sizeof(PCMachineClass), |
95bee274 IM |
2427 | .class_init = pc_machine_class_init, |
2428 | .interfaces = (InterfaceInfo[]) { | |
2429 | { TYPE_HOTPLUG_HANDLER }, | |
1255166b | 2430 | { TYPE_NMI }, |
95bee274 IM |
2431 | { } |
2432 | }, | |
d5747cac IM |
2433 | }; |
2434 | ||
2435 | static void pc_machine_register_types(void) | |
2436 | { | |
2437 | type_register_static(&pc_machine_info); | |
2438 | } | |
2439 | ||
2440 | type_init(pc_machine_register_types) |