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Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
[qemu.git] / hw / ide / core.c
CommitLineData
5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787 25#include <hw/hw.h>
0d09e41a 26#include <hw/i386/pc.h>
a2cb15b0 27#include <hw/pci/pci.h>
0d09e41a 28#include <hw/isa/isa.h>
1de7afc9
PB		 29#include "qemu/error-report.h"
30#include "qemu/timer.h"
9c17d615
PB		 31#include "sysemu/sysemu.h"
32#include "sysemu/dma.h"
0d09e41a 33#include "hw/block/block.h"
9c17d615 34#include "sysemu/blockdev.h"
59f2a787
GH		 35
36#include <hw/ide/internal.h>
e8b54394 37
b93af93d
BW		 38/* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
5391d806
FB		 78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
d353fb72 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 83
94458802
FB		 84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
5391d806
FB		 89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
67b915a5 91 put_le16(p + 0, 0x0040);
5fafdf24 92 put_le16(p + 1, s->cylinders);
67b915a5
FB		 93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 96 put_le16(p + 6, s->sectors);
fa879c64 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
47c06340 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 103#if MAX_MULT_SECTORS > 1
67b915a5 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 105#endif
67b915a5 106 put_le16(p + 48, 1); /* dword I/O */
94458802 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
5391d806 114 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
5391d806 117 if (s->mult_sectors)
67b915a5
FB		 118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 123 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
d353fb72
CH		 128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
ccf0fd8b
RE		 131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
94458802
FB		 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
145 if (s->wwn) {
146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
147 } else {
148 put_le16(p + 84, (1 << 14) | 0);
149 }
e900a7b7
CH		 150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
151 if (bdrv_enable_write_cache(s->bs))
152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
153 else
154 put_le16(p + 85, (1 << 14) | 1);
c2ff060f 155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
158 if (s->wwn) {
159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
160 } else {
161 put_le16(p + 87, (1 << 14) | 0);
162 }
94458802
FB		 163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
164 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 165 put_le16(p + 100, s->nb_sectors);
166 put_le16(p + 101, s->nb_sectors >> 16);
167 put_le16(p + 102, s->nb_sectors >> 32);
168 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 169
57dac7ef
MA		 170 if (dev && dev->conf.physical_block_size)
171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 172 if (s->wwn) {
173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
174 put_le16(p + 108, s->wwn >> 48);
175 put_le16(p + 109, s->wwn >> 32);
176 put_le16(p + 110, s->wwn >> 16);
177 put_le16(p + 111, s->wwn);
178 }
d353fb72
CH		 179 if (dev && dev->conf.discard_granularity) {
180 put_le16(p + 169, 1); /* TRIM support */
181 }
94458802
FB		 182
183 memcpy(s->identify_data, p, sizeof(s->identify_data));
184 s->identify_set = 1;
5391d806
FB		 185}
186
187static void ide_atapi_identify(IDEState *s)
188{
189 uint16_t *p;
190
94458802
FB		 191 if (s->identify_set) {
192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
193 return;
194 }
195
5391d806
FB		 196 memset(s->io_buffer, 0, 512);
197 p = (uint16_t *)s->io_buffer;
198 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 201 put_le16(p + 20, 3); /* buffer type */
202 put_le16(p + 21, 512); /* cache size in sectors */
203 put_le16(p + 22, 4); /* ecc bytes */
47c06340 204 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 207#ifdef USE_DMA_CDROM
208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 210 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 211 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 212#else
67b915a5
FB		 213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 216#endif
79d1d331 217 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 222
67b915a5
FB		 223 put_le16(p + 71, 30); /* in ns */
224 put_le16(p + 72, 30); /* in ns */
5391d806 225
1bdaa28d
AG		 226 if (s->ncq_queues) {
227 put_le16(p + 75, s->ncq_queues - 1);
228 /* NCQ supported */
229 put_le16(p + 76, (1 << 8));
230 }
231
67b915a5 232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 233#ifdef USE_DMA_CDROM
234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
235#endif
94458802
FB		 236 memcpy(s->identify_data, p, sizeof(s->identify_data));
237 s->identify_set = 1;
5391d806
FB		 238}
239
201a51fc
AZ		 240static void ide_cfata_identify(IDEState *s)
241{
242 uint16_t *p;
243 uint32_t cur_sec;
201a51fc
AZ		 244
245 p = (uint16_t *) s->identify_data;
246 if (s->identify_set)
247 goto fill_buffer;
248
249 memset(p, 0, sizeof(s->identify_data));
250
251 cur_sec = s->cylinders * s->heads * s->sectors;
252
253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
254 put_le16(p + 1, s->cylinders); /* Default cylinders */
255 put_le16(p + 3, s->heads); /* Default heads */
256 put_le16(p + 6, s->sectors); /* Default sectors per track */
257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 260 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 263#if MAX_MULT_SECTORS > 1
264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
265#else
266 put_le16(p + 47, 0x0000);
267#endif
268 put_le16(p + 49, 0x0f00); /* Capabilities */
269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
271 put_le16(p + 53, 0x0003); /* Translation params valid */
272 put_le16(p + 54, s->cylinders); /* Current cylinders */
273 put_le16(p + 55, s->heads); /* Current heads */
274 put_le16(p + 56, s->sectors); /* Current sectors */
275 put_le16(p + 57, cur_sec); /* Current capacity */
276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
277 if (s->mult_sectors) /* Multiple sector setting */
278 put_le16(p + 59, 0x100 | s->mult_sectors);
279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
286 put_le16(p + 82, 0x400c); /* Command Set supported */
287 put_le16(p + 83, 0x7068); /* Command Set supported */
288 put_le16(p + 84, 0x4000); /* Features supported */
289 put_le16(p + 85, 0x000c); /* Command Set enabled */
290 put_le16(p + 86, 0x7044); /* Command Set enabled */
291 put_le16(p + 87, 0x4000); /* Features enabled */
292 put_le16(p + 91, 0x4060); /* Current APM level */
293 put_le16(p + 129, 0x0002); /* Current features option */
294 put_le16(p + 130, 0x0005); /* Reassigned sectors */
295 put_le16(p + 131, 0x0001); /* Initial power mode */
296 put_le16(p + 132, 0x0000); /* User signature */
297 put_le16(p + 160, 0x8100); /* Power requirement */
298 put_le16(p + 161, 0x8001); /* CF command set */
299
300 s->identify_set = 1;
301
302fill_buffer:
303 memcpy(s->io_buffer, p, sizeof(s->identify_data));
304}
305
5391d806
FB		 306static void ide_set_signature(IDEState *s)
307{
308 s->select &= 0xf0; /* clear head */
309 /* put signature */
310 s->nsector = 1;
311 s->sector = 1;
cd8722bb 312 if (s->drive_kind == IDE_CD) {
5391d806
FB		 313 s->lcyl = 0x14;
314 s->hcyl = 0xeb;
315 } else if (s->bs) {
316 s->lcyl = 0;
317 s->hcyl = 0;
318 } else {
319 s->lcyl = 0xff;
320 s->hcyl = 0xff;
321 }
322}
323
d353fb72
CH		 324typedef struct TrimAIOCB {
325 BlockDriverAIOCB common;
326 QEMUBH *bh;
327 int ret;
501378c3
PB		 328 QEMUIOVector *qiov;
329 BlockDriverAIOCB *aiocb;
330 int i, j;
d353fb72
CH		 331} TrimAIOCB;
332
333static void trim_aio_cancel(BlockDriverAIOCB *acb)
334{
335 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
336
501378c3
PB		 337 /* Exit the loop in case bdrv_aio_cancel calls ide_issue_trim_cb again. */
338 iocb->j = iocb->qiov->niov - 1;
339 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
340
341 /* Tell ide_issue_trim_cb not to trigger the completion, too. */
d353fb72
CH		 342 qemu_bh_delete(iocb->bh);
343 iocb->bh = NULL;
501378c3
PB		 344
345 if (iocb->aiocb) {
346 bdrv_aio_cancel(iocb->aiocb);
347 }
d353fb72
CH		 348 qemu_aio_release(iocb);
349}
350
d7331bed 351static const AIOCBInfo trim_aiocb_info = {
d353fb72
CH		 352 .aiocb_size = sizeof(TrimAIOCB),
353 .cancel = trim_aio_cancel,
354};
355
356static void ide_trim_bh_cb(void *opaque)
357{
358 TrimAIOCB *iocb = opaque;
359
360 iocb->common.cb(iocb->common.opaque, iocb->ret);
361
362 qemu_bh_delete(iocb->bh);
363 iocb->bh = NULL;
d353fb72
CH		 364 qemu_aio_release(iocb);
365}
366
501378c3
PB		 367static void ide_issue_trim_cb(void *opaque, int ret)
368{
369 TrimAIOCB *iocb = opaque;
370 if (ret >= 0) {
371 while (iocb->j < iocb->qiov->niov) {
372 int j = iocb->j;
373 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
374 int i = iocb->i;
375 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
376
377 /* 6-byte LBA + 2-byte range per entry */
378 uint64_t entry = le64_to_cpu(buffer[i]);
379 uint64_t sector = entry & 0x0000ffffffffffffULL;
380 uint16_t count = entry >> 48;
381
382 if (count == 0) {
383 continue;
384 }
385
386 /* Got an entry! Submit and exit. */
387 iocb->aiocb = bdrv_aio_discard(iocb->common.bs, sector, count,
388 ide_issue_trim_cb, opaque);
389 return;
390 }
391
392 iocb->j++;
393 iocb->i = -1;
394 }
395 } else {
396 iocb->ret = ret;
397 }
398
399 iocb->aiocb = NULL;
400 if (iocb->bh) {
401 qemu_bh_schedule(iocb->bh);
402 }
403}
404
d353fb72
CH		 405BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
406 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
407 BlockDriverCompletionFunc *cb, void *opaque)
408{
409 TrimAIOCB *iocb;
d353fb72 410
d7331bed 411 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
d353fb72
CH		 412 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
413 iocb->ret = 0;
501378c3
PB		 414 iocb->qiov = qiov;
415 iocb->i = -1;
416 iocb->j = 0;
417 ide_issue_trim_cb(iocb, 0);
d353fb72
CH		 418 return &iocb->common;
419}
420
5391d806
FB		 421static inline void ide_abort_command(IDEState *s)
422{
423 s->status = READY_STAT | ERR_STAT;
424 s->error = ABRT_ERR;
425}
426
5391d806 427/* prepare data transfer and tell what to do after */
33231e0e
KW		 428void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
429 EndTransferFunc *end_transfer_func)
5391d806
FB		 430{
431 s->end_transfer_func = end_transfer_func;
432 s->data_ptr = buf;
433 s->data_end = buf + size;
40a6238a 434 if (!(s->status & ERR_STAT)) {
7603d156 435 s->status |= DRQ_STAT;
40a6238a
AG		 436 }
437 s->bus->dma->ops->start_transfer(s->bus->dma);
5391d806
FB		 438}
439
33231e0e 440void ide_transfer_stop(IDEState *s)
5391d806
FB		 441{
442 s->end_transfer_func = ide_transfer_stop;
443 s->data_ptr = s->io_buffer;
444 s->data_end = s->io_buffer;
445 s->status &= ~DRQ_STAT;
446}
447
356721ae 448int64_t ide_get_sector(IDEState *s)
5391d806
FB		 449{
450 int64_t sector_num;
451 if (s->select & 0x40) {
452 /* lba */
c2ff060f
FB		 453 if (!s->lba48) {
454 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
455 (s->lcyl << 8) | s->sector;
456 } else {
457 sector_num = ((int64_t)s->hob_hcyl << 40) |
458 ((int64_t) s->hob_lcyl << 32) |
459 ((int64_t) s->hob_sector << 24) |
460 ((int64_t) s->hcyl << 16) |
461 ((int64_t) s->lcyl << 8) | s->sector;
462 }
5391d806
FB		 463 } else {
464 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 465 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 466 }
467 return sector_num;
468}
469
356721ae 470void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 471{
472 unsigned int cyl, r;
473 if (s->select & 0x40) {
c2ff060f
FB		 474 if (!s->lba48) {
475 s->select = (s->select & 0xf0) | (sector_num >> 24);
476 s->hcyl = (sector_num >> 16);
477 s->lcyl = (sector_num >> 8);
478 s->sector = (sector_num);
479 } else {
480 s->sector = sector_num;
481 s->lcyl = sector_num >> 8;
482 s->hcyl = sector_num >> 16;
483 s->hob_sector = sector_num >> 24;
484 s->hob_lcyl = sector_num >> 32;
485 s->hob_hcyl = sector_num >> 40;
486 }
5391d806
FB		 487 } else {
488 cyl = sector_num / (s->heads * s->sectors);
489 r = sector_num % (s->heads * s->sectors);
490 s->hcyl = cyl >> 8;
491 s->lcyl = cyl;
1b8eb456 492 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 493 s->sector = (r % s->sectors) + 1;
494 }
495}
496
e162cfb0
AZ		 497static void ide_rw_error(IDEState *s) {
498 ide_abort_command(s);
9cdd03a7 499 ide_set_irq(s->bus);
e162cfb0
AZ		 500}
501
bef0fd59
SH		 502static void ide_sector_read_cb(void *opaque, int ret)
503{
504 IDEState *s = opaque;
505 int n;
506
507 s->pio_aiocb = NULL;
508 s->status &= ~BUSY_STAT;
509
510 bdrv_acct_done(s->bs, &s->acct);
511 if (ret != 0) {
512 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
513 BM_STATUS_RETRY_READ)) {
514 return;
515 }
516 }
517
518 n = s->nsector;
519 if (n > s->req_nb_sectors) {
520 n = s->req_nb_sectors;
521 }
522
523 /* Allow the guest to read the io_buffer */
524 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
525
526 ide_set_irq(s->bus);
527
528 ide_set_sector(s, ide_get_sector(s) + n);
529 s->nsector -= n;
530}
531
40a6238a 532void ide_sector_read(IDEState *s)
5391d806
FB		 533{
534 int64_t sector_num;
bef0fd59 535 int n;
5391d806
FB		 536
537 s->status = READY_STAT | SEEK_STAT;
a136e5a8 538 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 539 sector_num = ide_get_sector(s);
540 n = s->nsector;
bef0fd59 541
5391d806 542 if (n == 0) {
5391d806 543 ide_transfer_stop(s);
bef0fd59
SH		 544 return;
545 }
546
547 s->status |= BUSY_STAT;
548
549 if (n > s->req_nb_sectors) {
550 n = s->req_nb_sectors;
551 }
552
5391d806 553#if defined(DEBUG_IDE)
bef0fd59 554 printf("sector=%" PRId64 "\n", sector_num);
5391d806 555#endif
a597e79c 556
bef0fd59
SH		 557 s->iov.iov_base = s->io_buffer;
558 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
559 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
560
561 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
562 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
563 ide_sector_read_cb, s);
5391d806
FB		 564}
565
b61744b3 566static void dma_buf_commit(IDEState *s)
7aea4412 567{
1fb8648d 568 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 569}
570
a62eaa26
KW		 571static void ide_async_cmd_done(IDEState *s)
572{
573 if (s->bus->dma->ops->async_cmd_done) {
574 s->bus->dma->ops->async_cmd_done(s->bus->dma);
575 }
576}
577
33231e0e 578void ide_set_inactive(IDEState *s)
8337606d 579{
40a6238a
AG		 580 s->bus->dma->aiocb = NULL;
581 s->bus->dma->ops->set_inactive(s->bus->dma);
a62eaa26 582 ide_async_cmd_done(s);
8337606d
KW		 583}
584
356721ae 585void ide_dma_error(IDEState *s)
e162cfb0
AZ		 586{
587 ide_transfer_stop(s);
588 s->error = ABRT_ERR;
589 s->status = READY_STAT | ERR_STAT;
40a6238a 590 ide_set_inactive(s);
9cdd03a7 591 ide_set_irq(s->bus);
e162cfb0
AZ		 592}
593
ce4b6522 594static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 595{
1ceee0d5 596 bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
3e1caa5f 597 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
428c5705 598
3e1caa5f 599 if (action == BDRV_ACTION_STOP) {
40a6238a 600 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 601 s->bus->error_status = op;
3e1caa5f 602 } else if (action == BDRV_ACTION_REPORT) {
ce4b6522 603 if (op & BM_STATUS_DMA_RETRY) {
b61744b3 604 dma_buf_commit(s);
428c5705 605 ide_dma_error(s);
7aea4412 606 } else {
428c5705 607 ide_rw_error(s);
7aea4412 608 }
428c5705 609 }
3e1caa5f
PB		 610 bdrv_error_action(s->bs, action, is_read, error);
611 return action != BDRV_ACTION_IGNORE;
428c5705
AL		 612}
613
cd369c46 614void ide_dma_cb(void *opaque, int ret)
98087450 615{
40a6238a 616 IDEState *s = opaque;
8ccad811
FB		 617 int n;
618 int64_t sector_num;
038268e2 619 bool stay_active = false;
8ccad811 620
e162cfb0 621 if (ret < 0) {
cd369c46
CH		 622 int op = BM_STATUS_DMA_RETRY;
623
4e1e0051 624 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 625 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 626 else if (s->dma_cmd == IDE_DMA_TRIM)
627 op |= BM_STATUS_RETRY_TRIM;
628
cd369c46 629 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 630 return;
631 }
e162cfb0
AZ		 632 }
633
8ccad811 634 n = s->io_buffer_size >> 9;
038268e2
KW		 635 if (n > s->nsector) {
636 /* The PRDs were longer than needed for this request. Shorten them so
637 * we don't get a negative remainder. The Active bit must remain set
638 * after the request completes. */
639 n = s->nsector;
640 stay_active = true;
641 }
642
8ccad811
FB		 643 sector_num = ide_get_sector(s);
644 if (n > 0) {
b61744b3 645 dma_buf_commit(s);
8ccad811
FB		 646 sector_num += n;
647 ide_set_sector(s, sector_num);
648 s->nsector -= n;
8ccad811
FB		 649 }
650
651 /* end of transfer ? */
652 if (s->nsector == 0) {
98087450 653 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 654 ide_set_irq(s->bus);
cd369c46 655 goto eot;
98087450 656 }
8ccad811
FB		 657
658 /* launch next transfer */
659 n = s->nsector;
596bb44d 660 s->io_buffer_index = 0;
8ccad811 661 s->io_buffer_size = n * 512;
4e1e0051 662 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 663 /* The PRDs were too short. Reset the Active bit, but don't raise an
664 * interrupt. */
72bcca73 665 s->status = READY_STAT | SEEK_STAT;
7aea4412 666 goto eot;
69c38b8f 667 }
cd369c46 668
8ccad811 669#ifdef DEBUG_AIO
4e1e0051
CH		 670 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
671 sector_num, n, s->dma_cmd);
8ccad811 672#endif
cd369c46 673
4e1e0051
CH		 674 switch (s->dma_cmd) {
675 case IDE_DMA_READ:
cd369c46
CH		 676 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
677 ide_dma_cb, s);
4e1e0051
CH		 678 break;
679 case IDE_DMA_WRITE:
cd369c46
CH		 680 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
681 ide_dma_cb, s);
4e1e0051 682 break;
d353fb72
CH		 683 case IDE_DMA_TRIM:
684 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
43cf8ae6
DG		 685 ide_issue_trim, ide_dma_cb, s,
686 DMA_DIRECTION_TO_DEVICE);
d353fb72 687 break;
cd369c46 688 }
cd369c46
CH		 689 return;
690
691eot:
a597e79c
CH		 692 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
693 bdrv_acct_done(s->bs, &s->acct);
694 }
695 ide_set_inactive(s);
038268e2
KW		 696 if (stay_active) {
697 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
698 }
98087450
FB		 699}
700
4e1e0051 701static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 702{
8ccad811 703 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 704 s->io_buffer_index = 0;
705 s->io_buffer_size = 0;
4e1e0051 706 s->dma_cmd = dma_cmd;
a597e79c
CH		 707
708 switch (dma_cmd) {
709 case IDE_DMA_READ:
710 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
711 BDRV_ACCT_READ);
712 break;
713 case IDE_DMA_WRITE:
714 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
715 BDRV_ACCT_WRITE);
716 break;
717 default:
718 break;
719 }
720
cd369c46 721 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 722}
723
a09db21f
FB		 724static void ide_sector_write_timer_cb(void *opaque)
725{
726 IDEState *s = opaque;
9cdd03a7 727 ide_set_irq(s->bus);
a09db21f
FB		 728}
729
e82dabd8 730static void ide_sector_write_cb(void *opaque, int ret)
5391d806 731{
e82dabd8
SH		 732 IDEState *s = opaque;
733 int n;
a597e79c 734
a597e79c 735 bdrv_acct_done(s->bs, &s->acct);
428c5705 736
e82dabd8
SH		 737 s->pio_aiocb = NULL;
738 s->status &= ~BUSY_STAT;
739
e162cfb0 740 if (ret != 0) {
e82dabd8 741 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
428c5705 742 return;
e82dabd8 743 }
e162cfb0
AZ		 744 }
745
e82dabd8
SH		 746 n = s->nsector;
747 if (n > s->req_nb_sectors) {
748 n = s->req_nb_sectors;
749 }
5391d806
FB		 750 s->nsector -= n;
751 if (s->nsector == 0) {
292eef5a 752 /* no more sectors to write */
5391d806
FB		 753 ide_transfer_stop(s);
754 } else {
e82dabd8
SH		 755 int n1 = s->nsector;
756 if (n1 > s->req_nb_sectors) {
5391d806 757 n1 = s->req_nb_sectors;
e82dabd8
SH		 758 }
759 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
760 ide_sector_write);
5391d806 761 }
e82dabd8 762 ide_set_sector(s, ide_get_sector(s) + n);
3b46e624 763
31c2a146
TS		 764 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
765 /* It seems there is a bug in the Windows 2000 installer HDD
766 IDE driver which fills the disk with empty logs when the
767 IDE write IRQ comes too early. This hack tries to correct
768 that at the expense of slower write performances. Use this
769 option _only_ to install Windows 2000. You must disable it
770 for normal use. */
f7736b91 771 qemu_mod_timer(s->sector_write_timer,
74475455 772 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
f7736b91 773 } else {
9cdd03a7 774 ide_set_irq(s->bus);
31c2a146 775 }
5391d806
FB		 776}
777
e82dabd8
SH		 778void ide_sector_write(IDEState *s)
779{
780 int64_t sector_num;
781 int n;
782
783 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
784 sector_num = ide_get_sector(s);
785#if defined(DEBUG_IDE)
786 printf("sector=%" PRId64 "\n", sector_num);
787#endif
788 n = s->nsector;
789 if (n > s->req_nb_sectors) {
790 n = s->req_nb_sectors;
791 }
792
793 s->iov.iov_base = s->io_buffer;
794 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
795 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
796
797 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
798 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
799 ide_sector_write_cb, s);
800}
801
b0484ae4
CH		 802static void ide_flush_cb(void *opaque, int ret)
803{
804 IDEState *s = opaque;
805
e2bcadad
KW		 806 if (ret < 0) {
807 /* XXX: What sector number to set here? */
808 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
809 return;
810 }
811 }
b0484ae4 812
a597e79c 813 bdrv_acct_done(s->bs, &s->acct);
b0484ae4 814 s->status = READY_STAT | SEEK_STAT;
a62eaa26 815 ide_async_cmd_done(s);
b0484ae4
CH		 816 ide_set_irq(s->bus);
817}
818
40a6238a 819void ide_flush_cache(IDEState *s)
6bcb1a79 820{
b2df7531 821 if (s->bs == NULL) {
6bcb1a79 822 ide_flush_cb(s, 0);
b2df7531
KW		 823 return;
824 }
825
f68ec837 826 s->status |= BUSY_STAT;
a597e79c 827 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
ad54ae80 828 bdrv_aio_flush(s->bs, ide_flush_cb, s);
6bcb1a79
KW		 829}
830
201a51fc
AZ		 831static void ide_cfata_metadata_inquiry(IDEState *s)
832{
833 uint16_t *p;
834 uint32_t spd;
835
836 p = (uint16_t *) s->io_buffer;
837 memset(p, 0, 0x200);
838 spd = ((s->mdata_size - 1) >> 9) + 1;
839
840 put_le16(p + 0, 0x0001); /* Data format revision */
841 put_le16(p + 1, 0x0000); /* Media property: silicon */
842 put_le16(p + 2, s->media_changed); /* Media status */
843 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
844 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
845 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
846 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
847}
848
849static void ide_cfata_metadata_read(IDEState *s)
850{
851 uint16_t *p;
852
853 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
854 s->status = ERR_STAT;
855 s->error = ABRT_ERR;
856 return;
857 }
858
859 p = (uint16_t *) s->io_buffer;
860 memset(p, 0, 0x200);
861
862 put_le16(p + 0, s->media_changed); /* Media status */
863 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
864 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
865 s->nsector << 9), 0x200 - 2));
866}
867
868static void ide_cfata_metadata_write(IDEState *s)
869{
870 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
871 s->status = ERR_STAT;
872 s->error = ABRT_ERR;
873 return;
874 }
875
876 s->media_changed = 0;
877
878 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
879 s->io_buffer + 2,
880 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
881 s->nsector << 9), 0x200 - 2));
882}
883
bd491d6a 884/* called when the inserted state of the media has changed */
7d4b4ba5 885static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 886{
887 IDEState *s = opaque;
96b8f136 888 uint64_t nb_sectors;
bd491d6a 889
25ad22bc 890 s->tray_open = !load;
bd491d6a
TS		 891 bdrv_get_geometry(s->bs, &nb_sectors);
892 s->nb_sectors = nb_sectors;
9118e7f0 893
4b9b7092
AS		 894 /*
895 * First indicate to the guest that a CD has been removed. That's
896 * done on the next command the guest sends us.
897 *
67cc61e4 898 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 899 * detect a new CD in the drive. See ide_atapi_cmd() for details.
900 */
93c8cfd9 901 s->cdrom_changed = 1;
996faf1a 902 s->events.new_media = true;
2df0a3a3
PB		 903 s->events.eject_request = false;
904 ide_set_irq(s->bus);
905}
906
907static void ide_cd_eject_request_cb(void *opaque, bool force)
908{
909 IDEState *s = opaque;
910
911 s->events.eject_request = true;
912 if (force) {
913 s->tray_locked = false;
914 }
9cdd03a7 915 ide_set_irq(s->bus);
bd491d6a
TS		 916}
917
c2ff060f
FB		 918static void ide_cmd_lba48_transform(IDEState *s, int lba48)
919{
920 s->lba48 = lba48;
921
922 /* handle the 'magic' 0 nsector count conversion here. to avoid
923 * fiddling with the rest of the read logic, we just store the
924 * full sector count in ->nsector and ignore ->hob_nsector from now
925 */
926 if (!s->lba48) {
927 if (!s->nsector)
928 s->nsector = 256;
929 } else {
930 if (!s->nsector && !s->hob_nsector)
931 s->nsector = 65536;
932 else {
933 int lo = s->nsector;
934 int hi = s->hob_nsector;
935
936 s->nsector = (hi << 8) | lo;
937 }
938 }
939}
940
bcbdc4d3 941static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 942{
943 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 944 bus->ifs[0].select &= ~(1 << 7);
945 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 946}
947
356721ae 948void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 949{
bcbdc4d3 950 IDEBus *bus = opaque;
5391d806
FB		 951
952#ifdef DEBUG_IDE
953 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
954#endif
c2ff060f 955
5391d806 956 addr &= 7;
fcdd25ab
AL		 957
958 /* ignore writes to command block while busy with previous command */
bcbdc4d3 959 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 960 return;
961
5391d806
FB		 962 switch(addr) {
963 case 0:
964 break;
965 case 1:
bcbdc4d3 966 ide_clear_hob(bus);
c45c3d00 967 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 968 bus->ifs[0].hob_feature = bus->ifs[0].feature;
969 bus->ifs[1].hob_feature = bus->ifs[1].feature;
970 bus->ifs[0].feature = val;
971 bus->ifs[1].feature = val;
5391d806
FB		 972 break;
973 case 2:
bcbdc4d3
GH		 974 ide_clear_hob(bus);
975 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
976 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
977 bus->ifs[0].nsector = val;
978 bus->ifs[1].nsector = val;
5391d806
FB		 979 break;
980 case 3:
bcbdc4d3
GH		 981 ide_clear_hob(bus);
982 bus->ifs[0].hob_sector = bus->ifs[0].sector;
983 bus->ifs[1].hob_sector = bus->ifs[1].sector;
984 bus->ifs[0].sector = val;
985 bus->ifs[1].sector = val;
5391d806
FB		 986 break;
987 case 4:
bcbdc4d3
GH		 988 ide_clear_hob(bus);
989 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
990 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
991 bus->ifs[0].lcyl = val;
992 bus->ifs[1].lcyl = val;
5391d806
FB		 993 break;
994 case 5:
bcbdc4d3
GH		 995 ide_clear_hob(bus);
996 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
997 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
998 bus->ifs[0].hcyl = val;
999 bus->ifs[1].hcyl = val;
5391d806
FB		 1000 break;
1001 case 6:
c2ff060f 1002 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 1003 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1004 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 1005 /* select drive */
bcbdc4d3 1006 bus->unit = (val >> 4) & 1;
5391d806
FB		 1007 break;
1008 default:
1009 case 7:
1010 /* command */
7cff87ff
AG		 1011 ide_exec_cmd(bus, val);
1012 break;
1013 }
1014}
1015
b300337e
KW		 1016static bool cmd_nop(IDEState *s, uint8_t cmd)
1017{
1018 return true;
1019}
1020
4286434c
KW		 1021static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1022{
1023 switch (s->feature) {
1024 case DSM_TRIM:
1025 if (s->bs) {
1026 ide_sector_start_dma(s, IDE_DMA_TRIM);
1027 return false;
1028 }
1029 break;
1030 }
1031
1032 ide_abort_command(s);
1033 return true;
1034}
1035
1c66869a
KW		 1036static bool cmd_identify(IDEState *s, uint8_t cmd)
1037{
1038 if (s->bs && s->drive_kind != IDE_CD) {
1039 if (s->drive_kind != IDE_CFATA) {
1040 ide_identify(s);
1041 } else {
1042 ide_cfata_identify(s);
1043 }
1044 s->status = READY_STAT | SEEK_STAT;
1045 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1046 ide_set_irq(s->bus);
1047 return false;
1048 } else {
1049 if (s->drive_kind == IDE_CD) {
1050 ide_set_signature(s);
1051 }
1052 ide_abort_command(s);
1053 }
1054
1055 return true;
1056}
1057
413860cf
KW		 1058static bool cmd_verify(IDEState *s, uint8_t cmd)
1059{
1060 bool lba48 = (cmd == WIN_VERIFY_EXT);
1061
1062 /* do sector number check ? */
1063 ide_cmd_lba48_transform(s, lba48);
1064
1065 return true;
1066}
1067
adf3a2c4
KW		 1068static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1069{
1070 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1071 /* Disable Read and Write Multiple */
1072 s->mult_sectors = 0;
1073 } else if ((s->nsector & 0xff) != 0 &&
1074 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1075 (s->nsector & (s->nsector - 1)) != 0)) {
1076 ide_abort_command(s);
1077 } else {
1078 s->mult_sectors = s->nsector & 0xff;
1079 }
1080
1081 return true;
1082}
1083
1084static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1085{
1086 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1087
1088 if (!s->bs || !s->mult_sectors) {
1089 ide_abort_command(s);
1090 return true;
1091 }
1092
1093 ide_cmd_lba48_transform(s, lba48);
1094 s->req_nb_sectors = s->mult_sectors;
1095 ide_sector_read(s);
1096 return false;
1097}
1098
1099static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1100{
1101 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1102 int n;
1103
1104 if (!s->bs || !s->mult_sectors) {
1105 ide_abort_command(s);
1106 return true;
1107 }
1108
1109 ide_cmd_lba48_transform(s, lba48);
1110
1111 s->req_nb_sectors = s->mult_sectors;
1112 n = MIN(s->nsector, s->req_nb_sectors);
1113
1114 s->status = SEEK_STAT | READY_STAT;
1115 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1116
1117 s->media_changed = 1;
1118
1119 return false;
1120}
1121
0e6498ed
KW		 1122static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1123{
1124 bool lba48 = (cmd == WIN_READ_EXT);
1125
1126 if (s->drive_kind == IDE_CD) {
1127 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1128 ide_abort_command(s);
1129 return true;
1130 }
1131
1132 if (!s->bs) {
1133 ide_abort_command(s);
1134 return true;
1135 }
1136
1137 ide_cmd_lba48_transform(s, lba48);
1138 s->req_nb_sectors = 1;
1139 ide_sector_read(s);
1140
1141 return false;
1142}
1143
1144static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1145{
1146 bool lba48 = (cmd == WIN_WRITE_EXT);
1147
1148 if (!s->bs) {
1149 ide_abort_command(s);
1150 return true;
1151 }
1152
1153 ide_cmd_lba48_transform(s, lba48);
1154
1155 s->req_nb_sectors = 1;
1156 s->status = SEEK_STAT | READY_STAT;
1157 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1158
1159 s->media_changed = 1;
1160
1161 return false;
1162}
1163
92a6a6f6
KW		 1164static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1165{
1166 bool lba48 = (cmd == WIN_READDMA_EXT);
1167
1168 if (!s->bs) {
1169 ide_abort_command(s);
1170 return true;
1171 }
1172
1173 ide_cmd_lba48_transform(s, lba48);
1174 ide_sector_start_dma(s, IDE_DMA_READ);
1175
1176 return false;
1177}
1178
1179static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1180{
1181 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1182
1183 if (!s->bs) {
1184 ide_abort_command(s);
1185 return true;
1186 }
1187
1188 ide_cmd_lba48_transform(s, lba48);
1189 ide_sector_start_dma(s, IDE_DMA_WRITE);
1190
1191 s->media_changed = 1;
1192
1193 return false;
1194}
1195
9afce429
KW		 1196static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1197{
1198 ide_flush_cache(s);
1199 return false;
1200}
1201
61fdda37
KW		 1202static bool cmd_seek(IDEState *s, uint8_t cmd)
1203{
1204 /* XXX: Check that seek is within bounds */
1205 return true;
1206}
1207
63a82e6a
KW		 1208static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1209{
1210 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1211
1212 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1213 if (s->nb_sectors == 0) {
1214 ide_abort_command(s);
1215 return true;
1216 }
1217
1218 ide_cmd_lba48_transform(s, lba48);
1219 ide_set_sector(s, s->nb_sectors - 1);
1220
1221 return true;
1222}
1223
785f6320
KW		 1224static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1225{
1226 s->nsector = 0xff; /* device active or idle */
1227 return true;
1228}
1229
ee03398c
KW		 1230static bool cmd_set_features(IDEState *s, uint8_t cmd)
1231{
1232 uint16_t *identify_data;
1233
1234 if (!s->bs) {
1235 ide_abort_command(s);
1236 return true;
1237 }
1238
1239 /* XXX: valid for CDROM ? */
1240 switch (s->feature) {
1241 case 0x02: /* write cache enable */
1242 bdrv_set_enable_write_cache(s->bs, true);
1243 identify_data = (uint16_t *)s->identify_data;
1244 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1245 return true;
1246 case 0x82: /* write cache disable */
1247 bdrv_set_enable_write_cache(s->bs, false);
1248 identify_data = (uint16_t *)s->identify_data;
1249 put_le16(identify_data + 85, (1 << 14) | 1);
1250 ide_flush_cache(s);
1251 return false;
1252 case 0xcc: /* reverting to power-on defaults enable */
1253 case 0x66: /* reverting to power-on defaults disable */
1254 case 0xaa: /* read look-ahead enable */
1255 case 0x55: /* read look-ahead disable */
1256 case 0x05: /* set advanced power management mode */
1257 case 0x85: /* disable advanced power management mode */
1258 case 0x69: /* NOP */
1259 case 0x67: /* NOP */
1260 case 0x96: /* NOP */
1261 case 0x9a: /* NOP */
1262 case 0x42: /* enable Automatic Acoustic Mode */
1263 case 0xc2: /* disable Automatic Acoustic Mode */
1264 return true;
1265 case 0x03: /* set transfer mode */
1266 {
1267 uint8_t val = s->nsector & 0x07;
1268 identify_data = (uint16_t *)s->identify_data;
1269
1270 switch (s->nsector >> 3) {
1271 case 0x00: /* pio default */
1272 case 0x01: /* pio mode */
1273 put_le16(identify_data + 62, 0x07);
1274 put_le16(identify_data + 63, 0x07);
1275 put_le16(identify_data + 88, 0x3f);
1276 break;
1277 case 0x02: /* sigle word dma mode*/
1278 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1279 put_le16(identify_data + 63, 0x07);
1280 put_le16(identify_data + 88, 0x3f);
1281 break;
1282 case 0x04: /* mdma mode */
1283 put_le16(identify_data + 62, 0x07);
1284 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1285 put_le16(identify_data + 88, 0x3f);
1286 break;
1287 case 0x08: /* udma mode */
1288 put_le16(identify_data + 62, 0x07);
1289 put_le16(identify_data + 63, 0x07);
1290 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1291 break;
1292 default:
1293 goto abort_cmd;
1294 }
1295 return true;
1296 }
1297 }
1298
1299abort_cmd:
1300 ide_abort_command(s);
1301 return true;
1302}
1303
ee425c78
KW		 1304
1305/*** ATAPI commands ***/
1306
1307static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1308{
1309 ide_atapi_identify(s);
1310 s->status = READY_STAT | SEEK_STAT;
1311 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1312 ide_set_irq(s->bus);
1313 return false;
1314}
1315
1316static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1317{
1318 ide_set_signature(s);
1319
1320 if (s->drive_kind == IDE_CD) {
1321 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1322 * devices to return a clear status register
1323 * with READY_STAT *not* set. */
1324 } else {
1325 s->status = READY_STAT | SEEK_STAT;
1326 /* The bits of the error register are not as usual for this command!
1327 * They are part of the regular output (this is why ERR_STAT isn't set)
1328 * Device 0 passed, Device 1 passed or not present. */
1329 s->error = 0x01;
1330 ide_set_irq(s->bus);
1331 }
1332
1333 return false;
1334}
1335
1336static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1337{
1338 ide_set_signature(s);
1339 s->status = 0x00; /* NOTE: READY is _not_ set */
1340 s->error = 0x01;
1341
1342 return false;
1343}
1344
1345static bool cmd_packet(IDEState *s, uint8_t cmd)
1346{
1347 /* overlapping commands not supported */
1348 if (s->feature & 0x02) {
1349 ide_abort_command(s);
1350 return true;
1351 }
1352
1353 s->status = READY_STAT | SEEK_STAT;
1354 s->atapi_dma = s->feature & 1;
1355 s->nsector = 1;
1356 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1357 ide_atapi_cmd);
1358 return false;
1359}
1360
6b1dd744
KW		 1361
1362/*** CF-ATA commands ***/
1363
1364static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1365{
1366 s->error = 0x09; /* miscellaneous error */
1367 s->status = READY_STAT | SEEK_STAT;
1368 ide_set_irq(s->bus);
1369
1370 return false;
1371}
1372
1373static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1374{
1375 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1376 * required for Windows 8 to work with AHCI */
1377
1378 if (cmd == CFA_WEAR_LEVEL) {
1379 s->nsector = 0;
1380 }
1381
1382 if (cmd == CFA_ERASE_SECTORS) {
1383 s->media_changed = 1;
1384 }
1385
1386 return true;
1387}
1388
1389static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1390{
1391 s->status = READY_STAT | SEEK_STAT;
1392
1393 memset(s->io_buffer, 0, 0x200);
1394 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1395 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1396 s->io_buffer[0x02] = s->select; /* Head */
1397 s->io_buffer[0x03] = s->sector; /* Sector */
1398 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1399 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1400 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1401 s->io_buffer[0x13] = 0x00; /* Erase flag */
1402 s->io_buffer[0x18] = 0x00; /* Hot count */
1403 s->io_buffer[0x19] = 0x00; /* Hot count */
1404 s->io_buffer[0x1a] = 0x01; /* Hot count */
1405
1406 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1407 ide_set_irq(s->bus);
1408
1409 return false;
1410}
1411
1412static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1413{
1414 switch (s->feature) {
1415 case 0x02: /* Inquiry Metadata Storage */
1416 ide_cfata_metadata_inquiry(s);
1417 break;
1418 case 0x03: /* Read Metadata Storage */
1419 ide_cfata_metadata_read(s);
1420 break;
1421 case 0x04: /* Write Metadata Storage */
1422 ide_cfata_metadata_write(s);
1423 break;
1424 default:
1425 ide_abort_command(s);
1426 return true;
1427 }
1428
1429 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1430 s->status = 0x00; /* NOTE: READY is _not_ set */
1431 ide_set_irq(s->bus);
1432
1433 return false;
1434}
1435
1436static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1437{
1438 switch (s->feature) {
1439 case 0x01: /* sense temperature in device */
1440 s->nsector = 0x50; /* +20 C */
1441 break;
1442 default:
1443 ide_abort_command(s);
1444 return true;
1445 }
1446
1447 return true;
1448}
1449
ff352677
KW		 1450
1451/*** SMART commands ***/
1452
1453static bool cmd_smart(IDEState *s, uint8_t cmd)
1454{
1455 int n;
1456
1457 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1458 goto abort_cmd;
1459 }
1460
1461 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1462 goto abort_cmd;
1463 }
1464
1465 switch (s->feature) {
1466 case SMART_DISABLE:
1467 s->smart_enabled = 0;
1468 return true;
1469
1470 case SMART_ENABLE:
1471 s->smart_enabled = 1;
1472 return true;
1473
1474 case SMART_ATTR_AUTOSAVE:
1475 switch (s->sector) {
1476 case 0x00:
1477 s->smart_autosave = 0;
1478 break;
1479 case 0xf1:
1480 s->smart_autosave = 1;
1481 break;
1482 default:
1483 goto abort_cmd;
1484 }
1485 return true;
1486
1487 case SMART_STATUS:
1488 if (!s->smart_errors) {
1489 s->hcyl = 0xc2;
1490 s->lcyl = 0x4f;
1491 } else {
1492 s->hcyl = 0x2c;
1493 s->lcyl = 0xf4;
1494 }
1495 return true;
1496
1497 case SMART_READ_THRESH:
1498 memset(s->io_buffer, 0, 0x200);
1499 s->io_buffer[0] = 0x01; /* smart struct version */
1500
1501 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1502 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1503 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1504 }
1505
1506 /* checksum */
1507 for (n = 0; n < 511; n++) {
1508 s->io_buffer[511] += s->io_buffer[n];
1509 }
1510 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1511
1512 s->status = READY_STAT | SEEK_STAT;
1513 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1514 ide_set_irq(s->bus);
1515 return false;
1516
1517 case SMART_READ_DATA:
1518 memset(s->io_buffer, 0, 0x200);
1519 s->io_buffer[0] = 0x01; /* smart struct version */
1520
1521 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1522 int i;
1523 for (i = 0; i < 11; i++) {
1524 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1525 }
1526 }
1527
1528 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1529 if (s->smart_selftest_count == 0) {
1530 s->io_buffer[363] = 0;
1531 } else {
1532 s->io_buffer[363] =
1533 s->smart_selftest_data[3 +
1534 (s->smart_selftest_count - 1) *
1535 24];
1536 }
1537 s->io_buffer[364] = 0x20;
1538 s->io_buffer[365] = 0x01;
1539 /* offline data collection capacity: execute + self-test*/
1540 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1541 s->io_buffer[368] = 0x03; /* smart capability (1) */
1542 s->io_buffer[369] = 0x00; /* smart capability (2) */
1543 s->io_buffer[370] = 0x01; /* error logging supported */
1544 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1545 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1546 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1547
1548 for (n = 0; n < 511; n++) {
1549 s->io_buffer[511] += s->io_buffer[n];
1550 }
1551 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1552
1553 s->status = READY_STAT | SEEK_STAT;
1554 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1555 ide_set_irq(s->bus);
1556 return false;
1557
1558 case SMART_READ_LOG:
1559 switch (s->sector) {
1560 case 0x01: /* summary smart error log */
1561 memset(s->io_buffer, 0, 0x200);
1562 s->io_buffer[0] = 0x01;
1563 s->io_buffer[1] = 0x00; /* no error entries */
1564 s->io_buffer[452] = s->smart_errors & 0xff;
1565 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1566
1567 for (n = 0; n < 511; n++) {
1568 s->io_buffer[511] += s->io_buffer[n];
1569 }
1570 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1571 break;
1572 case 0x06: /* smart self test log */
1573 memset(s->io_buffer, 0, 0x200);
1574 s->io_buffer[0] = 0x01;
1575 if (s->smart_selftest_count == 0) {
1576 s->io_buffer[508] = 0;
1577 } else {
1578 s->io_buffer[508] = s->smart_selftest_count;
1579 for (n = 2; n < 506; n++) {
1580 s->io_buffer[n] = s->smart_selftest_data[n];
1581 }
1582 }
1583
1584 for (n = 0; n < 511; n++) {
1585 s->io_buffer[511] += s->io_buffer[n];
1586 }
1587 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1588 break;
1589 default:
1590 goto abort_cmd;
1591 }
1592 s->status = READY_STAT | SEEK_STAT;
1593 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1594 ide_set_irq(s->bus);
1595 return false;
1596
1597 case SMART_EXECUTE_OFFLINE:
1598 switch (s->sector) {
1599 case 0: /* off-line routine */
1600 case 1: /* short self test */
1601 case 2: /* extended self test */
1602 s->smart_selftest_count++;
1603 if (s->smart_selftest_count > 21) {
1604 s->smart_selftest_count = 0;
1605 }
1606 n = 2 + (s->smart_selftest_count - 1) * 24;
1607 s->smart_selftest_data[n] = s->sector;
1608 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1609 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1610 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1611 break;
1612 default:
1613 goto abort_cmd;
1614 }
1615 return true;
1616 }
1617
1618abort_cmd:
1619 ide_abort_command(s);
1620 return true;
1621}
1622
844505b1
MA		 1623#define HD_OK (1u << IDE_HD)
1624#define CD_OK (1u << IDE_CD)
1625#define CFA_OK (1u << IDE_CFATA)
1626#define HD_CFA_OK (HD_OK | CFA_OK)
1627#define ALL_OK (HD_OK | CD_OK | CFA_OK)
1628
a0436e92
KW		 1629/* Set the Disk Seek Completed status bit during completion */
1630#define SET_DSC (1u << 8)
1631
844505b1 1632/* See ACS-2 T13/2015-D Table B.2 Command codes */
a0436e92
KW		 1633static const struct {
1634 /* Returns true if the completion code should be run */
1635 bool (*handler)(IDEState *s, uint8_t cmd);
1636 int flags;
1637} ide_cmd_table[0x100] = {
844505b1 1638 /* NOP not implemented, mandatory for CD */
6b1dd744 1639 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
4286434c 1640 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
ee425c78 1641 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
b300337e 1642 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
0e6498ed
KW		 1643 [WIN_READ] = { cmd_read_pio, ALL_OK },
1644 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1645 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
92a6a6f6 1646 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
63a82e6a 1647 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
adf3a2c4 1648 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
0e6498ed
KW		 1649 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1650 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1651 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
92a6a6f6 1652 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
0e6498ed 1653 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
adf3a2c4 1654 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
0e6498ed 1655 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
413860cf
KW		 1656 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1657 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1658 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
61fdda37 1659 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
6b1dd744 1660 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
ee425c78 1661 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
b300337e
KW		 1662 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1663 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1664 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1665 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1666 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
785f6320 1667 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1668 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
ee425c78
KW		 1669 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1670 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
ff352677 1671 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
6b1dd744
KW		 1672 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1673 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
adf3a2c4
KW		 1674 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1675 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1676 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
92a6a6f6
KW		 1677 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1678 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1679 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1680 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
adf3a2c4 1681 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
b300337e
KW		 1682 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1683 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1684 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1685 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
785f6320 1686 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
b300337e 1687 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
9afce429
KW		 1688 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1689 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1c66869a 1690 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
ee03398c 1691 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
6b1dd744
KW		 1692 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1693 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
63a82e6a 1694 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
844505b1
MA		 1695};
1696
1697static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1698{
1699 return cmd < ARRAY_SIZE(ide_cmd_table)
a0436e92 1700 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
844505b1 1701}
7cff87ff
AG		 1702
1703void ide_exec_cmd(IDEBus *bus, uint32_t val)
1704{
1705 IDEState *s;
dfe1ea8f 1706 bool complete;
7cff87ff 1707
5391d806 1708#if defined(DEBUG_IDE)
6ef2ba5e 1709 printf("ide: CMD=%02x\n", val);
5391d806 1710#endif
6ef2ba5e 1711 s = idebus_active_if(bus);
66a0a2cb 1712 /* ignore commands to non existent slave */
6ef2ba5e
AG		 1713 if (s != bus->ifs && !s->bs)
1714 return;
c2ff060f 1715
6ef2ba5e
AG		 1716 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1717 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1718 return;
fcdd25ab 1719
844505b1 1720 if (!ide_cmd_permitted(s, val)) {
dfe1ea8f
KW		 1721 ide_abort_command(s);
1722 ide_set_irq(s->bus);
1723 return;
844505b1
MA		 1724 }
1725
dfe1ea8f
KW		 1726 s->status = READY_STAT | BUSY_STAT;
1727 s->error = 0;
a0436e92 1728
dfe1ea8f
KW		 1729 complete = ide_cmd_table[val].handler(s, val);
1730 if (complete) {
1731 s->status &= ~BUSY_STAT;
1732 assert(!!s->error == !!(s->status & ERR_STAT));
a0436e92 1733
dfe1ea8f
KW		 1734 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1735 s->status |= SEEK_STAT;
a0436e92
KW		 1736 }
1737
6ef2ba5e 1738 ide_set_irq(s->bus);
6ef2ba5e 1739 }
5391d806
FB		 1740}
1741
356721ae 1742uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1743{
bcbdc4d3
GH		 1744 IDEBus *bus = opaque;
1745 IDEState *s = idebus_active_if(bus);
5391d806 1746 uint32_t addr;
c2ff060f 1747 int ret, hob;
5391d806
FB		 1748
1749 addr = addr1 & 7;
c2ff060f
FB		 1750 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1751 //hob = s->select & (1 << 7);
1752 hob = 0;
5391d806
FB		 1753 switch(addr) {
1754 case 0:
1755 ret = 0xff;
1756 break;
1757 case 1:
bcbdc4d3
GH		 1758 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1759 (s != bus->ifs && !s->bs))
c45c3d00 1760 ret = 0;
c2ff060f 1761 else if (!hob)
c45c3d00 1762 ret = s->error;
c2ff060f
FB		 1763 else
1764 ret = s->hob_feature;
5391d806
FB		 1765 break;
1766 case 2:
bcbdc4d3 1767 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1768 ret = 0;
c2ff060f 1769 else if (!hob)
c45c3d00 1770 ret = s->nsector & 0xff;
c2ff060f
FB		 1771 else
1772 ret = s->hob_nsector;
5391d806
FB		 1773 break;
1774 case 3:
bcbdc4d3 1775 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1776 ret = 0;
c2ff060f 1777 else if (!hob)
c45c3d00 1778 ret = s->sector;
c2ff060f
FB		 1779 else
1780 ret = s->hob_sector;
5391d806
FB		 1781 break;
1782 case 4:
bcbdc4d3 1783 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1784 ret = 0;
c2ff060f 1785 else if (!hob)
c45c3d00 1786 ret = s->lcyl;
c2ff060f
FB		 1787 else
1788 ret = s->hob_lcyl;
5391d806
FB		 1789 break;
1790 case 5:
bcbdc4d3 1791 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1792 ret = 0;
c2ff060f 1793 else if (!hob)
c45c3d00 1794 ret = s->hcyl;
c2ff060f
FB		 1795 else
1796 ret = s->hob_hcyl;
5391d806
FB		 1797 break;
1798 case 6:
bcbdc4d3 1799 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1800 ret = 0;
1801 else
7ae98627 1802 ret = s->select;
5391d806
FB		 1803 break;
1804 default:
1805 case 7:
bcbdc4d3
GH		 1806 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1807 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1808 ret = 0;
1809 else
1810 ret = s->status;
9cdd03a7 1811 qemu_irq_lower(bus->irq);
5391d806
FB		 1812 break;
1813 }
1814#ifdef DEBUG_IDE
1815 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1816#endif
1817 return ret;
1818}
1819
356721ae 1820uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1821{
bcbdc4d3
GH		 1822 IDEBus *bus = opaque;
1823 IDEState *s = idebus_active_if(bus);
5391d806 1824 int ret;
7ae98627 1825
bcbdc4d3
GH		 1826 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1827 (s != bus->ifs && !s->bs))
7ae98627
FB		 1828 ret = 0;
1829 else
1830 ret = s->status;
5391d806
FB		 1831#ifdef DEBUG_IDE
1832 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1833#endif
1834 return ret;
1835}
1836
356721ae 1837void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1838{
bcbdc4d3 1839 IDEBus *bus = opaque;
5391d806
FB		 1840 IDEState *s;
1841 int i;
1842
1843#ifdef DEBUG_IDE
1844 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1845#endif
1846 /* common for both drives */
9cdd03a7 1847 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1848 (val & IDE_CMD_RESET)) {
1849 /* reset low to high */
1850 for(i = 0;i < 2; i++) {
bcbdc4d3 1851 s = &bus->ifs[i];
5391d806
FB		 1852 s->status = BUSY_STAT | SEEK_STAT;
1853 s->error = 0x01;
1854 }
9cdd03a7 1855 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1856 !(val & IDE_CMD_RESET)) {
1857 /* high to low */
1858 for(i = 0;i < 2; i++) {
bcbdc4d3 1859 s = &bus->ifs[i];
cd8722bb 1860 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1861 s->status = 0x00; /* NOTE: READY is _not_ set */
1862 else
56bf1d37 1863 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1864 ide_set_signature(s);
1865 }
1866 }
1867
9cdd03a7 1868 bus->cmd = val;
5391d806
FB		 1869}
1870
40c4ed3f
KW		 1871/*
1872 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1873 * transferred from the device to the guest), false if it's a PIO in
1874 */
1875static bool ide_is_pio_out(IDEState *s)
1876{
1877 if (s->end_transfer_func == ide_sector_write ||
1878 s->end_transfer_func == ide_atapi_cmd) {
1879 return false;
1880 } else if (s->end_transfer_func == ide_sector_read ||
1881 s->end_transfer_func == ide_transfer_stop ||
1882 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1883 s->end_transfer_func == ide_dummy_transfer_stop) {
1884 return true;
1885 }
1886
1887 abort();
1888}
1889
356721ae 1890void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1891{
bcbdc4d3
GH		 1892 IDEBus *bus = opaque;
1893 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1894 uint8_t *p;
1895
40c4ed3f
KW		 1896 /* PIO data access allowed only when DRQ bit is set. The result of a write
1897 * during PIO out is indeterminate, just ignore it. */
1898 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1899 return;
40c4ed3f 1900 }
fcdd25ab 1901
5391d806 1902 p = s->data_ptr;
0c4ad8dc 1903 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1904 p += 2;
1905 s->data_ptr = p;
1906 if (p >= s->data_end)
1907 s->end_transfer_func(s);
1908}
1909
356721ae 1910uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1911{
bcbdc4d3
GH		 1912 IDEBus *bus = opaque;
1913 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1914 uint8_t *p;
1915 int ret;
fcdd25ab 1916
40c4ed3f
KW		 1917 /* PIO data access allowed only when DRQ bit is set. The result of a read
1918 * during PIO in is indeterminate, return 0 and don't move forward. */
1919 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1920 return 0;
40c4ed3f 1921 }
fcdd25ab 1922
5391d806 1923 p = s->data_ptr;
0c4ad8dc 1924 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1925 p += 2;
1926 s->data_ptr = p;
1927 if (p >= s->data_end)
1928 s->end_transfer_func(s);
1929 return ret;
1930}
1931
356721ae 1932void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1933{
bcbdc4d3
GH		 1934 IDEBus *bus = opaque;
1935 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1936 uint8_t *p;
1937
40c4ed3f
KW		 1938 /* PIO data access allowed only when DRQ bit is set. The result of a write
1939 * during PIO out is indeterminate, just ignore it. */
1940 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1941 return;
40c4ed3f 1942 }
fcdd25ab 1943
5391d806 1944 p = s->data_ptr;
0c4ad8dc 1945 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1946 p += 4;
1947 s->data_ptr = p;
1948 if (p >= s->data_end)
1949 s->end_transfer_func(s);
1950}
1951
356721ae 1952uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1953{
bcbdc4d3
GH		 1954 IDEBus *bus = opaque;
1955 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1956 uint8_t *p;
1957 int ret;
3b46e624 1958
40c4ed3f
KW		 1959 /* PIO data access allowed only when DRQ bit is set. The result of a read
1960 * during PIO in is indeterminate, return 0 and don't move forward. */
1961 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1962 return 0;
40c4ed3f 1963 }
fcdd25ab 1964
5391d806 1965 p = s->data_ptr;
0c4ad8dc 1966 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 1967 p += 4;
1968 s->data_ptr = p;
1969 if (p >= s->data_end)
1970 s->end_transfer_func(s);
1971 return ret;
1972}
1973
a7dfe172
FB		 1974static void ide_dummy_transfer_stop(IDEState *s)
1975{
1976 s->data_ptr = s->io_buffer;
1977 s->data_end = s->io_buffer;
1978 s->io_buffer[0] = 0xff;
1979 s->io_buffer[1] = 0xff;
1980 s->io_buffer[2] = 0xff;
1981 s->io_buffer[3] = 0xff;
1982}
1983
4a643563 1984static void ide_reset(IDEState *s)
5391d806 1985{
4a643563
BS		 1986#ifdef DEBUG_IDE
1987 printf("ide: reset\n");
1988#endif
bef0fd59
SH		 1989
1990 if (s->pio_aiocb) {
1991 bdrv_aio_cancel(s->pio_aiocb);
1992 s->pio_aiocb = NULL;
1993 }
1994
cd8722bb 1995 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 1996 s->mult_sectors = 0;
1997 else
1998 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 1999 /* ide regs */
2000 s->feature = 0;
2001 s->error = 0;
2002 s->nsector = 0;
2003 s->sector = 0;
2004 s->lcyl = 0;
2005 s->hcyl = 0;
2006
2007 /* lba48 */
2008 s->hob_feature = 0;
2009 s->hob_sector = 0;
2010 s->hob_nsector = 0;
2011 s->hob_lcyl = 0;
2012 s->hob_hcyl = 0;
2013
5391d806 2014 s->select = 0xa0;
41a2b959 2015 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 2016
2017 s->lba48 = 0;
2018
2019 /* ATAPI specific */
2020 s->sense_key = 0;
2021 s->asc = 0;
2022 s->cdrom_changed = 0;
2023 s->packet_transfer_size = 0;
2024 s->elementary_transfer_size = 0;
2025 s->io_buffer_index = 0;
2026 s->cd_sector_size = 0;
2027 s->atapi_dma = 0;
a7f3d65b
PH		 2028 s->tray_locked = 0;
2029 s->tray_open = 0;
4a643563
BS		 2030 /* ATA DMA state */
2031 s->io_buffer_size = 0;
2032 s->req_nb_sectors = 0;
2033
5391d806 2034 ide_set_signature(s);
a7dfe172
FB		 2035 /* init the transfer handler so that 0xffff is returned on data
2036 accesses */
2037 s->end_transfer_func = ide_dummy_transfer_stop;
2038 ide_dummy_transfer_stop(s);
201a51fc 2039 s->media_changed = 0;
5391d806
FB		 2040}
2041
4a643563
BS		 2042void ide_bus_reset(IDEBus *bus)
2043{
2044 bus->unit = 0;
2045 bus->cmd = 0;
2046 ide_reset(&bus->ifs[0]);
2047 ide_reset(&bus->ifs[1]);
2048 ide_clear_hob(bus);
40a6238a
AG		 2049
2050 /* pending async DMA */
2051 if (bus->dma->aiocb) {
2052#ifdef DEBUG_AIO
2053 printf("aio_cancel\n");
2054#endif
2055 bdrv_aio_cancel(bus->dma->aiocb);
2056 bus->dma->aiocb = NULL;
2057 }
2058
2059 /* reset dma provider too */
2060 bus->dma->ops->reset(bus->dma);
4a643563
BS		 2061}
2062
e4def80b
MA		 2063static bool ide_cd_is_tray_open(void *opaque)
2064{
2065 return ((IDEState *)opaque)->tray_open;
2066}
2067
f107639a
MA		 2068static bool ide_cd_is_medium_locked(void *opaque)
2069{
2070 return ((IDEState *)opaque)->tray_locked;
2071}
2072
0e49de52 2073static const BlockDevOps ide_cd_block_ops = {
145feb17 2074 .change_media_cb = ide_cd_change_cb,
2df0a3a3 2075 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 2076 .is_tray_open = ide_cd_is_tray_open,
f107639a 2077 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 2078};
2079
1f56e32a 2080int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
95ebda85 2081 const char *version, const char *serial, const char *model,
ba801960
MA		 2082 uint64_t wwn,
2083 uint32_t cylinders, uint32_t heads, uint32_t secs,
2084 int chs_trans)
88804180 2085{
88804180
GH		 2086 uint64_t nb_sectors;
2087
f8b6cc00 2088 s->bs = bs;
1f56e32a
MA		 2089 s->drive_kind = kind;
2090
f8b6cc00 2091 bdrv_get_geometry(bs, &nb_sectors);
870111c8
MA		 2092 s->cylinders = cylinders;
2093 s->heads = heads;
2094 s->sectors = secs;
ba801960 2095 s->chs_trans = chs_trans;
870111c8 2096 s->nb_sectors = nb_sectors;
95ebda85 2097 s->wwn = wwn;
870111c8
MA		 2098 /* The SMART values should be preserved across power cycles
2099 but they aren't. */
2100 s->smart_enabled = 1;
2101 s->smart_autosave = 1;
2102 s->smart_errors = 0;
2103 s->smart_selftest_count = 0;
1f56e32a 2104 if (kind == IDE_CD) {
0e49de52 2105 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
7b6f9300 2106 bdrv_set_buffer_alignment(bs, 2048);
7aa9c811 2107 } else {
98f28ad7
MA		 2108 if (!bdrv_is_inserted(s->bs)) {
2109 error_report("Device needs media, but drive is empty");
2110 return -1;
2111 }
7aa9c811
MA		 2112 if (bdrv_is_read_only(bs)) {
2113 error_report("Can't use a read-only drive");
2114 return -1;
2115 }
88804180 2116 }
f8b6cc00 2117 if (serial) {
aa2c91bd 2118 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 2119 } else {
88804180
GH		 2120 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2121 "QM%05d", s->drive_serial);
870111c8 2122 }
27e0c9a1
FB		 2123 if (model) {
2124 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2125 } else {
2126 switch (kind) {
2127 case IDE_CD:
2128 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2129 break;
2130 case IDE_CFATA:
2131 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2132 break;
2133 default:
2134 strcpy(s->drive_model_str, "QEMU HARDDISK");
2135 break;
2136 }
2137 }
2138
47c06340
GH		 2139 if (version) {
2140 pstrcpy(s->version, sizeof(s->version), version);
2141 } else {
93bfef4c 2142 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
47c06340 2143 }
40a6238a 2144
88804180 2145 ide_reset(s);
50fb1900 2146 bdrv_iostatus_enable(bs);
c4d74df7 2147 return 0;
88804180
GH		 2148}
2149
57234ee4 2150static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 2151{
2152 static int drive_serial = 1;
2153 IDEState *s = &bus->ifs[unit];
2154
2155 s->bus = bus;
2156 s->unit = unit;
2157 s->drive_serial = drive_serial++;
1b2adf28 2158 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2159 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2160 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2161 memset(s->io_buffer, 0, s->io_buffer_total_len);
2162
d459da0e 2163 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 2164 memset(s->smart_selftest_data, 0, 512);
2165
74475455 2166 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
d459da0e 2167 ide_sector_write_timer_cb, s);
57234ee4
MA		 2168}
2169
40a6238a
AG		 2170static void ide_nop_start(IDEDMA *dma, IDEState *s,
2171 BlockDriverCompletionFunc *cb)
2172{
2173}
2174
2175static int ide_nop(IDEDMA *dma)
2176{
2177 return 0;
2178}
2179
2180static int ide_nop_int(IDEDMA *dma, int x)
2181{
2182 return 0;
2183}
2184
1dfb4dd9 2185static void ide_nop_restart(void *opaque, int x, RunState y)
40a6238a
AG		 2186{
2187}
2188
2189static const IDEDMAOps ide_dma_nop_ops = {
2190 .start_dma = ide_nop_start,
2191 .start_transfer = ide_nop,
2192 .prepare_buf = ide_nop_int,
2193 .rw_buf = ide_nop_int,
2194 .set_unit = ide_nop_int,
2195 .add_status = ide_nop_int,
2196 .set_inactive = ide_nop,
2197 .restart_cb = ide_nop_restart,
2198 .reset = ide_nop,
2199};
2200
2201static IDEDMA ide_dma_nop = {
2202 .ops = &ide_dma_nop_ops,
2203 .aiocb = NULL,
2204};
2205
57234ee4
MA		 2206void ide_init2(IDEBus *bus, qemu_irq irq)
2207{
2208 int i;
2209
2210 for(i = 0; i < 2; i++) {
2211 ide_init1(bus, i);
2212 ide_reset(&bus->ifs[i]);
870111c8 2213 }
57234ee4 2214 bus->irq = irq;
40a6238a 2215 bus->dma = &ide_dma_nop;
d459da0e
MA		 2216}
2217
57234ee4
MA		 2218/* TODO convert users to qdev and remove */
2219void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
2220 DriveInfo *hd1, qemu_irq irq)
5391d806 2221{
ba801960 2222 int i, trans;
57234ee4 2223 DriveInfo *dinfo;
ba801960 2224 uint32_t cyls, heads, secs;
5391d806 2225
caed8802 2226 for(i = 0; i < 2; i++) {
57234ee4
MA		 2227 dinfo = i == 0 ? hd0 : hd1;
2228 ide_init1(bus, i);
2229 if (dinfo) {
ba801960
MA		 2230 cyls = dinfo->cyls;
2231 heads = dinfo->heads;
2232 secs = dinfo->secs;
2233 trans = dinfo->trans;
2234 if (!cyls && !heads && !secs) {
2235 hd_geometry_guess(dinfo->bdrv, &cyls, &heads, &secs, &trans);
2adc99b2
MA		 2236 } else if (trans == BIOS_ATA_TRANSLATION_AUTO) {
2237 trans = hd_bios_chs_auto_trans(cyls, heads, secs);
ba801960 2238 }
b7eb0c9f
MA		 2239 if (cyls < 1 || cyls > 65535) {
2240 error_report("cyls must be between 1 and 65535");
2241 exit(1);
2242 }
2243 if (heads < 1 || heads > 16) {
2244 error_report("heads must be between 1 and 16");
2245 exit(1);
2246 }
2247 if (secs < 1 || secs > 255) {
2248 error_report("secs must be between 1 and 255");
2249 exit(1);
2250 }
1f56e32a 2251 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
577d0a38
MA		 2252 dinfo->media_cd ? IDE_CD : IDE_HD,
2253 NULL, dinfo->serial, NULL, 0,
2254 cyls, heads, secs, trans) < 0) {
c4d74df7
MA		 2255 error_report("Can't set up IDE drive %s", dinfo->id);
2256 exit(1);
2257 }
fa879d62 2258 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
57234ee4
MA		 2259 } else {
2260 ide_reset(&bus->ifs[i]);
2261 }
5391d806 2262 }
9cdd03a7 2263 bus->irq = irq;
40a6238a 2264 bus->dma = &ide_dma_nop;
69b91039
FB		 2265}
2266
4a91d3b3
RH		 2267static const MemoryRegionPortio ide_portio_list[] = {
2268 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2269 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2270 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2271 PORTIO_END_OF_LIST(),
2272};
2273
2274static const MemoryRegionPortio ide_portio2_list[] = {
2275 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2276 PORTIO_END_OF_LIST(),
2277};
2278
2279void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2280{
4a91d3b3
RH		 2281 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2282 bridge has been setup properly to always register with ISA. */
2283 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2284
caed8802 2285 if (iobase2) {
4a91d3b3 2286 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2287 }
5391d806 2288}
69b91039 2289
37159f13 2290static bool is_identify_set(void *opaque, int version_id)
aa941b94 2291{
37159f13
JQ		 2292 IDEState *s = opaque;
2293
2294 return s->identify_set != 0;
2295}
2296
50641c5c
JQ		 2297static EndTransferFunc* transfer_end_table[] = {
2298 ide_sector_read,
2299 ide_sector_write,
2300 ide_transfer_stop,
2301 ide_atapi_cmd_reply_end,
2302 ide_atapi_cmd,
2303 ide_dummy_transfer_stop,
2304};
2305
2306static int transfer_end_table_idx(EndTransferFunc *fn)
2307{
2308 int i;
2309
2310 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2311 if (transfer_end_table[i] == fn)
2312 return i;
2313
2314 return -1;
2315}
2316
37159f13 2317static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2318{
37159f13
JQ		 2319 IDEState *s = opaque;
2320
7cdd481c
PB		 2321 if (s->identify_set) {
2322 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2323 }
37159f13 2324 return 0;
aa941b94
AZ		 2325}
2326
50641c5c
JQ		 2327static int ide_drive_pio_post_load(void *opaque, int version_id)
2328{
2329 IDEState *s = opaque;
2330
fb60105d 2331 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2332 return -EINVAL;
2333 }
2334 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2335 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2336 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2337
2338 return 0;
2339}
2340
2341static void ide_drive_pio_pre_save(void *opaque)
2342{
2343 IDEState *s = opaque;
2344 int idx;
2345
2346 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2347 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2348
2349 idx = transfer_end_table_idx(s->end_transfer_func);
2350 if (idx == -1) {
2351 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2352 __func__);
2353 s->end_transfer_fn_idx = 2;
2354 } else {
2355 s->end_transfer_fn_idx = idx;
2356 }
2357}
2358
2359static bool ide_drive_pio_state_needed(void *opaque)
2360{
2361 IDEState *s = opaque;
2362
fdc650d7
KW		 2363 return ((s->status & DRQ_STAT) != 0)
2364 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 2365}
2366
db118fe7
MA		 2367static bool ide_tray_state_needed(void *opaque)
2368{
2369 IDEState *s = opaque;
2370
2371 return s->tray_open || s->tray_locked;
2372}
2373
996faf1a
AS		 2374static bool ide_atapi_gesn_needed(void *opaque)
2375{
2376 IDEState *s = opaque;
2377
2378 return s->events.new_media || s->events.eject_request;
2379}
2380
def93791
KW		 2381static bool ide_error_needed(void *opaque)
2382{
2383 IDEBus *bus = opaque;
2384
2385 return (bus->error_status != 0);
2386}
2387
996faf1a 2388/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2389static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2390 .name ="ide_drive/atapi/gesn_state",
2391 .version_id = 1,
2392 .minimum_version_id = 1,
2393 .minimum_version_id_old = 1,
2394 .fields = (VMStateField []) {
2395 VMSTATE_BOOL(events.new_media, IDEState),
2396 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2397 VMSTATE_END_OF_LIST()
996faf1a
AS		 2398 }
2399};
2400
db118fe7
MA		 2401static const VMStateDescription vmstate_ide_tray_state = {
2402 .name = "ide_drive/tray_state",
2403 .version_id = 1,
2404 .minimum_version_id = 1,
2405 .minimum_version_id_old = 1,
db118fe7
MA		 2406 .fields = (VMStateField[]) {
2407 VMSTATE_BOOL(tray_open, IDEState),
2408 VMSTATE_BOOL(tray_locked, IDEState),
2409 VMSTATE_END_OF_LIST()
2410 }
2411};
2412
656fbeff 2413static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2414 .name = "ide_drive/pio_state",
2415 .version_id = 1,
2416 .minimum_version_id = 1,
2417 .minimum_version_id_old = 1,
2418 .pre_save = ide_drive_pio_pre_save,
2419 .post_load = ide_drive_pio_post_load,
2420 .fields = (VMStateField []) {
2421 VMSTATE_INT32(req_nb_sectors, IDEState),
2422 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2423 vmstate_info_uint8, uint8_t),
2424 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2425 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2426 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2427 VMSTATE_INT32(elementary_transfer_size, IDEState),
2428 VMSTATE_INT32(packet_transfer_size, IDEState),
2429 VMSTATE_END_OF_LIST()
2430 }
2431};
2432
37159f13
JQ		 2433const VMStateDescription vmstate_ide_drive = {
2434 .name = "ide_drive",
3abb6260 2435 .version_id = 3,
37159f13
JQ		 2436 .minimum_version_id = 0,
2437 .minimum_version_id_old = 0,
2438 .post_load = ide_drive_post_load,
2439 .fields = (VMStateField []) {
2440 VMSTATE_INT32(mult_sectors, IDEState),
2441 VMSTATE_INT32(identify_set, IDEState),
2442 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2443 VMSTATE_UINT8(feature, IDEState),
2444 VMSTATE_UINT8(error, IDEState),
2445 VMSTATE_UINT32(nsector, IDEState),
2446 VMSTATE_UINT8(sector, IDEState),
2447 VMSTATE_UINT8(lcyl, IDEState),
2448 VMSTATE_UINT8(hcyl, IDEState),
2449 VMSTATE_UINT8(hob_feature, IDEState),
2450 VMSTATE_UINT8(hob_sector, IDEState),
2451 VMSTATE_UINT8(hob_nsector, IDEState),
2452 VMSTATE_UINT8(hob_lcyl, IDEState),
2453 VMSTATE_UINT8(hob_hcyl, IDEState),
2454 VMSTATE_UINT8(select, IDEState),
2455 VMSTATE_UINT8(status, IDEState),
2456 VMSTATE_UINT8(lba48, IDEState),
2457 VMSTATE_UINT8(sense_key, IDEState),
2458 VMSTATE_UINT8(asc, IDEState),
2459 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2460 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2461 },
2462 .subsections = (VMStateSubsection []) {
2463 {
2464 .vmsd = &vmstate_ide_drive_pio_state,
2465 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2466 }, {
2467 .vmsd = &vmstate_ide_tray_state,
2468 .needed = ide_tray_state_needed,
996faf1a
AS		 2469 }, {
2470 .vmsd = &vmstate_ide_atapi_gesn_state,
2471 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2472 }, {
2473 /* empty */
2474 }
37159f13
JQ		 2475 }
2476};
2477
656fbeff 2478static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2479 .name ="ide_bus/error",
2480 .version_id = 1,
2481 .minimum_version_id = 1,
2482 .minimum_version_id_old = 1,
2483 .fields = (VMStateField []) {
2484 VMSTATE_INT32(error_status, IDEBus),
2485 VMSTATE_END_OF_LIST()
2486 }
2487};
2488
6521dc62
JQ		 2489const VMStateDescription vmstate_ide_bus = {
2490 .name = "ide_bus",
2491 .version_id = 1,
2492 .minimum_version_id = 1,
2493 .minimum_version_id_old = 1,
2494 .fields = (VMStateField []) {
2495 VMSTATE_UINT8(cmd, IDEBus),
2496 VMSTATE_UINT8(unit, IDEBus),
2497 VMSTATE_END_OF_LIST()
def93791
KW		 2498 },
2499 .subsections = (VMStateSubsection []) {
2500 {
2501 .vmsd = &vmstate_ide_error_status,
2502 .needed = ide_error_needed,
2503 }, {
2504 /* empty */
2505 }
6521dc62
JQ		 2506 }
2507};
75717903
IY		 2508
2509void ide_drive_get(DriveInfo **hd, int max_bus)
2510{
2511 int i;
2512
2513 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2514 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2515 exit(1);
2516 }
2517
2518 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2519 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2520 }
2521}
Qemu copy for testing