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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
17e5ad6c | 21 | #include <linux/dma-mapping.h> |
1da177e4 | 22 | #include <linux/mm.h> |
8bc3bcc9 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
5a0e3ad6 | 31 | #include <linux/gfp.h> |
1da177e4 LT |
32 | |
33 | #include <asm/io.h> | |
1da177e4 | 34 | #include <asm/dma.h> |
17e5ad6c | 35 | #include <asm/scatterlist.h> |
1da177e4 LT |
36 | |
37 | #include <linux/init.h> | |
38 | #include <linux/bootmem.h> | |
a8522509 | 39 | #include <linux/iommu-helper.h> |
1da177e4 | 40 | |
2b2b614d ZK |
41 | #include <trace/events/swiotlb.h> |
42 | ||
1da177e4 LT |
43 | #define OFFSET(val,align) ((unsigned long) \ |
44 | ( (val) & ( (align) - 1))) | |
45 | ||
0b9afede AW |
46 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
47 | ||
48 | /* | |
49 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
50 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
51 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
52 | */ | |
53 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
54 | ||
1da177e4 LT |
55 | int swiotlb_force; |
56 | ||
57 | /* | |
bfc5501f KRW |
58 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
59 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
60 | * API. |
61 | */ | |
ff7204a7 | 62 | static phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
63 | |
64 | /* | |
b595076a | 65 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
66 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
67 | */ | |
68 | static unsigned long io_tlb_nslabs; | |
69 | ||
70 | /* | |
71 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
72 | */ | |
73 | static unsigned long io_tlb_overflow = 32*1024; | |
74 | ||
ee3f6ba8 | 75 | static phys_addr_t io_tlb_overflow_buffer; |
1da177e4 LT |
76 | |
77 | /* | |
78 | * This is a free list describing the number of free entries available from | |
79 | * each index | |
80 | */ | |
81 | static unsigned int *io_tlb_list; | |
82 | static unsigned int io_tlb_index; | |
83 | ||
84 | /* | |
85 | * We need to save away the original address corresponding to a mapped entry | |
86 | * for the sync operations. | |
87 | */ | |
bc40ac66 | 88 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
89 | |
90 | /* | |
91 | * Protect the above data structures in the map and unmap calls | |
92 | */ | |
93 | static DEFINE_SPINLOCK(io_tlb_lock); | |
94 | ||
5740afdb FT |
95 | static int late_alloc; |
96 | ||
1da177e4 LT |
97 | static int __init |
98 | setup_io_tlb_npages(char *str) | |
99 | { | |
100 | if (isdigit(*str)) { | |
e8579e72 | 101 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
102 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
103 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
104 | } | |
105 | if (*str == ',') | |
106 | ++str; | |
b18485e7 | 107 | if (!strcmp(str, "force")) |
1da177e4 | 108 | swiotlb_force = 1; |
b18485e7 | 109 | |
c729de8f | 110 | return 0; |
1da177e4 | 111 | } |
c729de8f | 112 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 LT |
113 | /* make io_tlb_overflow tunable too? */ |
114 | ||
f21ffe9f | 115 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
116 | { |
117 | return io_tlb_nslabs; | |
118 | } | |
f21ffe9f | 119 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f YL |
120 | |
121 | /* default to 64MB */ | |
122 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
123 | unsigned long swiotlb_size_or_default(void) | |
124 | { | |
125 | unsigned long size; | |
126 | ||
127 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
128 | ||
129 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
130 | } | |
131 | ||
02ca646e | 132 | /* Note that this doesn't work with highmem page */ |
70a7d3cc JF |
133 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
134 | volatile void *address) | |
e08e1f7a | 135 | { |
862d196b | 136 | return phys_to_dma(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
137 | } |
138 | ||
ac2cbab2 YL |
139 | static bool no_iotlb_memory; |
140 | ||
ad32e8cb | 141 | void swiotlb_print_info(void) |
2e5b2b86 | 142 | { |
ad32e8cb | 143 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
ff7204a7 | 144 | unsigned char *vstart, *vend; |
2e5b2b86 | 145 | |
ac2cbab2 YL |
146 | if (no_iotlb_memory) { |
147 | pr_warn("software IO TLB: No low mem\n"); | |
148 | return; | |
149 | } | |
150 | ||
ff7204a7 | 151 | vstart = phys_to_virt(io_tlb_start); |
c40dba06 | 152 | vend = phys_to_virt(io_tlb_end); |
2e5b2b86 | 153 | |
3af684c7 | 154 | printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n", |
ff7204a7 | 155 | (unsigned long long)io_tlb_start, |
c40dba06 | 156 | (unsigned long long)io_tlb_end, |
ff7204a7 | 157 | bytes >> 20, vstart, vend - 1); |
2e5b2b86 IC |
158 | } |
159 | ||
ac2cbab2 | 160 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 161 | { |
ee3f6ba8 | 162 | void *v_overflow_buffer; |
563aaf06 | 163 | unsigned long i, bytes; |
1da177e4 | 164 | |
abbceff7 | 165 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 166 | |
abbceff7 | 167 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
168 | io_tlb_start = __pa(tlb); |
169 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 | 170 | |
ee3f6ba8 AD |
171 | /* |
172 | * Get the overflow emergency buffer | |
173 | */ | |
ac2cbab2 YL |
174 | v_overflow_buffer = alloc_bootmem_low_pages_nopanic( |
175 | PAGE_ALIGN(io_tlb_overflow)); | |
ee3f6ba8 | 176 | if (!v_overflow_buffer) |
ac2cbab2 | 177 | return -ENOMEM; |
ee3f6ba8 AD |
178 | |
179 | io_tlb_overflow_buffer = __pa(v_overflow_buffer); | |
180 | ||
1da177e4 LT |
181 | /* |
182 | * Allocate and initialize the free list array. This array is used | |
183 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
184 | * between io_tlb_start and io_tlb_end. | |
185 | */ | |
e79f86b2 | 186 | io_tlb_list = alloc_bootmem_pages(PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); |
25667d67 | 187 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
188 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
189 | io_tlb_index = 0; | |
e79f86b2 | 190 | io_tlb_orig_addr = alloc_bootmem_pages(PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); |
1da177e4 | 191 | |
ad32e8cb FT |
192 | if (verbose) |
193 | swiotlb_print_info(); | |
ac2cbab2 YL |
194 | |
195 | return 0; | |
1da177e4 LT |
196 | } |
197 | ||
abbceff7 FT |
198 | /* |
199 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
200 | * structures for the software IO TLB used to implement the DMA API. | |
201 | */ | |
ac2cbab2 YL |
202 | void __init |
203 | swiotlb_init(int verbose) | |
abbceff7 | 204 | { |
c729de8f | 205 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 206 | unsigned char *vstart; |
abbceff7 FT |
207 | unsigned long bytes; |
208 | ||
209 | if (!io_tlb_nslabs) { | |
210 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
211 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
212 | } | |
213 | ||
214 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
215 | ||
ac2cbab2 YL |
216 | /* Get IO TLB memory from the low pages */ |
217 | vstart = alloc_bootmem_low_pages_nopanic(PAGE_ALIGN(bytes)); | |
218 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) | |
219 | return; | |
abbceff7 | 220 | |
ac2cbab2 YL |
221 | if (io_tlb_start) |
222 | free_bootmem(io_tlb_start, | |
223 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
224 | pr_warn("Cannot allocate SWIOTLB buffer"); | |
225 | no_iotlb_memory = true; | |
1da177e4 LT |
226 | } |
227 | ||
0b9afede AW |
228 | /* |
229 | * Systems with larger DMA zones (those that don't support ISA) can | |
230 | * initialize the swiotlb later using the slab allocator if needed. | |
231 | * This should be just like above, but with some error catching. | |
232 | */ | |
233 | int | |
563aaf06 | 234 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 235 | { |
74838b75 | 236 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 237 | unsigned char *vstart = NULL; |
0b9afede | 238 | unsigned int order; |
74838b75 | 239 | int rc = 0; |
0b9afede AW |
240 | |
241 | if (!io_tlb_nslabs) { | |
242 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
243 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
244 | } | |
245 | ||
246 | /* | |
247 | * Get IO TLB memory from the low pages | |
248 | */ | |
563aaf06 | 249 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 250 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 251 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
252 | |
253 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
254 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
255 | order); | |
256 | if (vstart) | |
0b9afede AW |
257 | break; |
258 | order--; | |
259 | } | |
260 | ||
ff7204a7 | 261 | if (!vstart) { |
74838b75 KRW |
262 | io_tlb_nslabs = req_nslabs; |
263 | return -ENOMEM; | |
264 | } | |
563aaf06 | 265 | if (order != get_order(bytes)) { |
0b9afede AW |
266 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
267 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
268 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
269 | } | |
ff7204a7 | 270 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 271 | if (rc) |
ff7204a7 | 272 | free_pages((unsigned long)vstart, order); |
74838b75 KRW |
273 | return rc; |
274 | } | |
275 | ||
276 | int | |
277 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
278 | { | |
279 | unsigned long i, bytes; | |
ee3f6ba8 | 280 | unsigned char *v_overflow_buffer; |
74838b75 KRW |
281 | |
282 | bytes = nslabs << IO_TLB_SHIFT; | |
283 | ||
284 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
285 | io_tlb_start = virt_to_phys(tlb); |
286 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 287 | |
ff7204a7 | 288 | memset(tlb, 0, bytes); |
0b9afede | 289 | |
ee3f6ba8 AD |
290 | /* |
291 | * Get the overflow emergency buffer | |
292 | */ | |
293 | v_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
294 | get_order(io_tlb_overflow)); | |
295 | if (!v_overflow_buffer) | |
296 | goto cleanup2; | |
297 | ||
298 | io_tlb_overflow_buffer = virt_to_phys(v_overflow_buffer); | |
299 | ||
0b9afede AW |
300 | /* |
301 | * Allocate and initialize the free list array. This array is used | |
302 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
303 | * between io_tlb_start and io_tlb_end. | |
304 | */ | |
305 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
306 | get_order(io_tlb_nslabs * sizeof(int))); | |
307 | if (!io_tlb_list) | |
ee3f6ba8 | 308 | goto cleanup3; |
0b9afede AW |
309 | |
310 | for (i = 0; i < io_tlb_nslabs; i++) | |
311 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
312 | io_tlb_index = 0; | |
313 | ||
bc40ac66 BB |
314 | io_tlb_orig_addr = (phys_addr_t *) |
315 | __get_free_pages(GFP_KERNEL, | |
316 | get_order(io_tlb_nslabs * | |
317 | sizeof(phys_addr_t))); | |
0b9afede | 318 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 319 | goto cleanup4; |
0b9afede | 320 | |
bc40ac66 | 321 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(phys_addr_t)); |
0b9afede | 322 | |
ad32e8cb | 323 | swiotlb_print_info(); |
0b9afede | 324 | |
5740afdb FT |
325 | late_alloc = 1; |
326 | ||
0b9afede AW |
327 | return 0; |
328 | ||
329 | cleanup4: | |
25667d67 TL |
330 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
331 | sizeof(int))); | |
0b9afede | 332 | io_tlb_list = NULL; |
ee3f6ba8 AD |
333 | cleanup3: |
334 | free_pages((unsigned long)v_overflow_buffer, | |
335 | get_order(io_tlb_overflow)); | |
336 | io_tlb_overflow_buffer = 0; | |
0b9afede | 337 | cleanup2: |
c40dba06 | 338 | io_tlb_end = 0; |
ff7204a7 | 339 | io_tlb_start = 0; |
74838b75 | 340 | io_tlb_nslabs = 0; |
0b9afede AW |
341 | return -ENOMEM; |
342 | } | |
343 | ||
5740afdb FT |
344 | void __init swiotlb_free(void) |
345 | { | |
ee3f6ba8 | 346 | if (!io_tlb_orig_addr) |
5740afdb FT |
347 | return; |
348 | ||
349 | if (late_alloc) { | |
ee3f6ba8 | 350 | free_pages((unsigned long)phys_to_virt(io_tlb_overflow_buffer), |
5740afdb FT |
351 | get_order(io_tlb_overflow)); |
352 | free_pages((unsigned long)io_tlb_orig_addr, | |
353 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
354 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
355 | sizeof(int))); | |
ff7204a7 | 356 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
357 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
358 | } else { | |
ee3f6ba8 | 359 | free_bootmem_late(io_tlb_overflow_buffer, |
e79f86b2 | 360 | PAGE_ALIGN(io_tlb_overflow)); |
5740afdb | 361 | free_bootmem_late(__pa(io_tlb_orig_addr), |
e79f86b2 | 362 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); |
5740afdb | 363 | free_bootmem_late(__pa(io_tlb_list), |
e79f86b2 | 364 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); |
ff7204a7 | 365 | free_bootmem_late(io_tlb_start, |
e79f86b2 | 366 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); |
5740afdb | 367 | } |
f21ffe9f | 368 | io_tlb_nslabs = 0; |
5740afdb FT |
369 | } |
370 | ||
02ca646e | 371 | static int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 372 | { |
ff7204a7 | 373 | return paddr >= io_tlb_start && paddr < io_tlb_end; |
640aebfe FT |
374 | } |
375 | ||
fb05a379 BB |
376 | /* |
377 | * Bounce: copy the swiotlb buffer back to the original dma location | |
378 | */ | |
af51a9f1 AD |
379 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
380 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 381 | { |
af51a9f1 AD |
382 | unsigned long pfn = PFN_DOWN(orig_addr); |
383 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
384 | |
385 | if (PageHighMem(pfn_to_page(pfn))) { | |
386 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 387 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
388 | char *buffer; |
389 | unsigned int sz = 0; | |
390 | unsigned long flags; | |
391 | ||
392 | while (size) { | |
67131ad0 | 393 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
394 | |
395 | local_irq_save(flags); | |
c3eede8e | 396 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 397 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 398 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 399 | else |
af51a9f1 | 400 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 401 | kunmap_atomic(buffer); |
ef9b1893 | 402 | local_irq_restore(flags); |
fb05a379 BB |
403 | |
404 | size -= sz; | |
405 | pfn++; | |
af51a9f1 | 406 | vaddr += sz; |
fb05a379 | 407 | offset = 0; |
ef9b1893 | 408 | } |
af51a9f1 AD |
409 | } else if (dir == DMA_TO_DEVICE) { |
410 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 411 | } else { |
af51a9f1 | 412 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 413 | } |
1b548f66 JF |
414 | } |
415 | ||
e05ed4d1 AD |
416 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
417 | dma_addr_t tbl_dma_addr, | |
418 | phys_addr_t orig_addr, size_t size, | |
419 | enum dma_data_direction dir) | |
1da177e4 LT |
420 | { |
421 | unsigned long flags; | |
e05ed4d1 | 422 | phys_addr_t tlb_addr; |
1da177e4 LT |
423 | unsigned int nslots, stride, index, wrap; |
424 | int i; | |
681cc5cd FT |
425 | unsigned long mask; |
426 | unsigned long offset_slots; | |
427 | unsigned long max_slots; | |
428 | ||
ac2cbab2 YL |
429 | if (no_iotlb_memory) |
430 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
431 | ||
681cc5cd | 432 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 433 | |
eb605a57 FT |
434 | tbl_dma_addr &= mask; |
435 | ||
436 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
437 | |
438 | /* | |
439 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
440 | */ | |
b15a3891 JB |
441 | max_slots = mask + 1 |
442 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
443 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
444 | |
445 | /* | |
446 | * For mappings greater than a page, we limit the stride (and | |
447 | * hence alignment) to a page size. | |
448 | */ | |
449 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
450 | if (size > PAGE_SIZE) | |
451 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
452 | else | |
453 | stride = 1; | |
454 | ||
34814545 | 455 | BUG_ON(!nslots); |
1da177e4 LT |
456 | |
457 | /* | |
458 | * Find suitable number of IO TLB entries size that will fit this | |
459 | * request and allocate a buffer from that IO TLB pool. | |
460 | */ | |
461 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
462 | index = ALIGN(io_tlb_index, stride); |
463 | if (index >= io_tlb_nslabs) | |
464 | index = 0; | |
465 | wrap = index; | |
466 | ||
467 | do { | |
a8522509 FT |
468 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
469 | max_slots)) { | |
b15a3891 JB |
470 | index += stride; |
471 | if (index >= io_tlb_nslabs) | |
472 | index = 0; | |
a7133a15 AM |
473 | if (index == wrap) |
474 | goto not_found; | |
475 | } | |
476 | ||
477 | /* | |
478 | * If we find a slot that indicates we have 'nslots' number of | |
479 | * contiguous buffers, we allocate the buffers from that slot | |
480 | * and mark the entries as '0' indicating unavailable. | |
481 | */ | |
482 | if (io_tlb_list[index] >= nslots) { | |
483 | int count = 0; | |
484 | ||
485 | for (i = index; i < (int) (index + nslots); i++) | |
486 | io_tlb_list[i] = 0; | |
487 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
488 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 489 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 490 | |
a7133a15 AM |
491 | /* |
492 | * Update the indices to avoid searching in the next | |
493 | * round. | |
494 | */ | |
495 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
496 | ? (index + nslots) : 0); | |
497 | ||
498 | goto found; | |
499 | } | |
500 | index += stride; | |
501 | if (index >= io_tlb_nslabs) | |
502 | index = 0; | |
503 | } while (index != wrap); | |
504 | ||
505 | not_found: | |
506 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
e05ed4d1 | 507 | return SWIOTLB_MAP_ERROR; |
a7133a15 | 508 | found: |
1da177e4 LT |
509 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
510 | ||
511 | /* | |
512 | * Save away the mapping from the original address to the DMA address. | |
513 | * This is needed when we sync the memory. Then we sync the buffer if | |
514 | * needed. | |
515 | */ | |
bc40ac66 | 516 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 517 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
1da177e4 | 518 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
af51a9f1 | 519 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE); |
1da177e4 | 520 | |
e05ed4d1 | 521 | return tlb_addr; |
1da177e4 | 522 | } |
d7ef1533 | 523 | EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single); |
1da177e4 | 524 | |
eb605a57 FT |
525 | /* |
526 | * Allocates bounce buffer and returns its kernel virtual address. | |
527 | */ | |
528 | ||
e05ed4d1 AD |
529 | phys_addr_t map_single(struct device *hwdev, phys_addr_t phys, size_t size, |
530 | enum dma_data_direction dir) | |
eb605a57 | 531 | { |
ff7204a7 | 532 | dma_addr_t start_dma_addr = phys_to_dma(hwdev, io_tlb_start); |
eb605a57 FT |
533 | |
534 | return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, dir); | |
535 | } | |
536 | ||
1da177e4 LT |
537 | /* |
538 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
539 | */ | |
61ca08c3 AD |
540 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
541 | size_t size, enum dma_data_direction dir) | |
1da177e4 LT |
542 | { |
543 | unsigned long flags; | |
544 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
61ca08c3 AD |
545 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
546 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
547 | |
548 | /* | |
549 | * First, sync the memory before unmapping the entry | |
550 | */ | |
af51a9f1 AD |
551 | if (orig_addr && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
552 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE); | |
1da177e4 LT |
553 | |
554 | /* | |
555 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 556 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
557 | * While returning the entries to the free list, we merge the entries |
558 | * with slots below and above the pool being returned. | |
559 | */ | |
560 | spin_lock_irqsave(&io_tlb_lock, flags); | |
561 | { | |
562 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
563 | io_tlb_list[index + nslots] : 0); | |
564 | /* | |
565 | * Step 1: return the slots to the free list, merging the | |
566 | * slots with superceeding slots | |
567 | */ | |
568 | for (i = index + nslots - 1; i >= index; i--) | |
569 | io_tlb_list[i] = ++count; | |
570 | /* | |
571 | * Step 2: merge the returned slots with the preceding slots, | |
572 | * if available (non zero) | |
573 | */ | |
574 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
575 | io_tlb_list[i] = ++count; | |
576 | } | |
577 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
578 | } | |
d7ef1533 | 579 | EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single); |
1da177e4 | 580 | |
fbfda893 AD |
581 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
582 | size_t size, enum dma_data_direction dir, | |
583 | enum dma_sync_target target) | |
1da177e4 | 584 | { |
fbfda893 AD |
585 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
586 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 587 | |
fbfda893 | 588 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 589 | |
de69e0f0 JL |
590 | switch (target) { |
591 | case SYNC_FOR_CPU: | |
592 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 593 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 594 | size, DMA_FROM_DEVICE); |
34814545 ES |
595 | else |
596 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
597 | break; |
598 | case SYNC_FOR_DEVICE: | |
599 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 600 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 601 | size, DMA_TO_DEVICE); |
34814545 ES |
602 | else |
603 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
604 | break; |
605 | default: | |
1da177e4 | 606 | BUG(); |
de69e0f0 | 607 | } |
1da177e4 | 608 | } |
d7ef1533 | 609 | EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single); |
1da177e4 LT |
610 | |
611 | void * | |
612 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 613 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 614 | { |
563aaf06 | 615 | dma_addr_t dev_addr; |
1da177e4 LT |
616 | void *ret; |
617 | int order = get_order(size); | |
284901a9 | 618 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
619 | |
620 | if (hwdev && hwdev->coherent_dma_mask) | |
621 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 622 | |
25667d67 | 623 | ret = (void *)__get_free_pages(flags, order); |
e05ed4d1 AD |
624 | if (ret) { |
625 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); | |
626 | if (dev_addr + size - 1 > dma_mask) { | |
627 | /* | |
628 | * The allocated memory isn't reachable by the device. | |
629 | */ | |
630 | free_pages((unsigned long) ret, order); | |
631 | ret = NULL; | |
632 | } | |
1da177e4 LT |
633 | } |
634 | if (!ret) { | |
635 | /* | |
bfc5501f KRW |
636 | * We are either out of memory or the device can't DMA to |
637 | * GFP_DMA memory; fall back on map_single(), which | |
ceb5ac32 | 638 | * will grab memory from the lowest available address range. |
1da177e4 | 639 | */ |
e05ed4d1 AD |
640 | phys_addr_t paddr = map_single(hwdev, 0, size, DMA_FROM_DEVICE); |
641 | if (paddr == SWIOTLB_MAP_ERROR) | |
1da177e4 | 642 | return NULL; |
1da177e4 | 643 | |
e05ed4d1 AD |
644 | ret = phys_to_virt(paddr); |
645 | dev_addr = phys_to_dma(hwdev, paddr); | |
1da177e4 | 646 | |
61ca08c3 AD |
647 | /* Confirm address can be DMA'd by device */ |
648 | if (dev_addr + size - 1 > dma_mask) { | |
649 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", | |
650 | (unsigned long long)dma_mask, | |
651 | (unsigned long long)dev_addr); | |
a2b89b59 | 652 | |
61ca08c3 AD |
653 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ |
654 | swiotlb_tbl_unmap_single(hwdev, paddr, | |
655 | size, DMA_TO_DEVICE); | |
656 | return NULL; | |
657 | } | |
1da177e4 | 658 | } |
e05ed4d1 | 659 | |
1da177e4 | 660 | *dma_handle = dev_addr; |
e05ed4d1 AD |
661 | memset(ret, 0, size); |
662 | ||
1da177e4 LT |
663 | return ret; |
664 | } | |
874d6a95 | 665 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
666 | |
667 | void | |
668 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
02ca646e | 669 | dma_addr_t dev_addr) |
1da177e4 | 670 | { |
862d196b | 671 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
02ca646e | 672 | |
aa24886e | 673 | WARN_ON(irqs_disabled()); |
02ca646e FT |
674 | if (!is_swiotlb_buffer(paddr)) |
675 | free_pages((unsigned long)vaddr, get_order(size)); | |
1da177e4 | 676 | else |
bfc5501f | 677 | /* DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single */ |
61ca08c3 | 678 | swiotlb_tbl_unmap_single(hwdev, paddr, size, DMA_TO_DEVICE); |
1da177e4 | 679 | } |
874d6a95 | 680 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
681 | |
682 | static void | |
22d48269 KRW |
683 | swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, |
684 | int do_panic) | |
1da177e4 LT |
685 | { |
686 | /* | |
687 | * Ran out of IOMMU space for this operation. This is very bad. | |
688 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 689 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
690 | * When the mapping is small enough return a static buffer to limit |
691 | * the damage, or panic when the transfer is too big. | |
692 | */ | |
563aaf06 | 693 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
94b32486 | 694 | "device %s\n", size, dev ? dev_name(dev) : "?"); |
1da177e4 | 695 | |
c7084b35 CD |
696 | if (size <= io_tlb_overflow || !do_panic) |
697 | return; | |
698 | ||
699 | if (dir == DMA_BIDIRECTIONAL) | |
700 | panic("DMA: Random memory could be DMA accessed\n"); | |
701 | if (dir == DMA_FROM_DEVICE) | |
702 | panic("DMA: Random memory could be DMA written\n"); | |
703 | if (dir == DMA_TO_DEVICE) | |
704 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
705 | } |
706 | ||
707 | /* | |
708 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 709 | * physical address to use is returned. |
1da177e4 LT |
710 | * |
711 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 712 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 713 | */ |
f98eee8e FT |
714 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
715 | unsigned long offset, size_t size, | |
716 | enum dma_data_direction dir, | |
717 | struct dma_attrs *attrs) | |
1da177e4 | 718 | { |
e05ed4d1 | 719 | phys_addr_t map, phys = page_to_phys(page) + offset; |
862d196b | 720 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 | 721 | |
34814545 | 722 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 723 | /* |
ceb5ac32 | 724 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
725 | * we can safely return the device addr and not worry about bounce |
726 | * buffering it. | |
727 | */ | |
b9394647 | 728 | if (dma_capable(dev, dev_addr, size) && !swiotlb_force) |
1da177e4 LT |
729 | return dev_addr; |
730 | ||
2b2b614d ZK |
731 | trace_swiotlb_bounced(dev, dev_addr, size, swiotlb_force); |
732 | ||
e05ed4d1 | 733 | /* Oh well, have to allocate and map a bounce buffer. */ |
f98eee8e | 734 | map = map_single(dev, phys, size, dir); |
e05ed4d1 | 735 | if (map == SWIOTLB_MAP_ERROR) { |
f98eee8e | 736 | swiotlb_full(dev, size, dir, 1); |
ee3f6ba8 | 737 | return phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 LT |
738 | } |
739 | ||
e05ed4d1 | 740 | dev_addr = phys_to_dma(dev, map); |
1da177e4 | 741 | |
e05ed4d1 | 742 | /* Ensure that the address returned is DMA'ble */ |
fba99fa3 | 743 | if (!dma_capable(dev, dev_addr, size)) { |
61ca08c3 | 744 | swiotlb_tbl_unmap_single(dev, map, size, dir); |
ee3f6ba8 | 745 | return phys_to_dma(dev, io_tlb_overflow_buffer); |
fba99fa3 | 746 | } |
1da177e4 LT |
747 | |
748 | return dev_addr; | |
749 | } | |
f98eee8e | 750 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 751 | |
1da177e4 LT |
752 | /* |
753 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 754 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
755 | * other usages are undefined. |
756 | * | |
757 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
758 | * whatever the device wrote there. | |
759 | */ | |
7fcebbd2 | 760 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
22d48269 | 761 | size_t size, enum dma_data_direction dir) |
1da177e4 | 762 | { |
862d196b | 763 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 764 | |
34814545 | 765 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 766 | |
02ca646e | 767 | if (is_swiotlb_buffer(paddr)) { |
61ca08c3 | 768 | swiotlb_tbl_unmap_single(hwdev, paddr, size, dir); |
7fcebbd2 BB |
769 | return; |
770 | } | |
771 | ||
772 | if (dir != DMA_FROM_DEVICE) | |
773 | return; | |
774 | ||
02ca646e FT |
775 | /* |
776 | * phys_to_virt doesn't work with hihgmem page but we could | |
777 | * call dma_mark_clean() with hihgmem page here. However, we | |
778 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
779 | * make dma_mark_clean() take a physical address if necessary. | |
780 | */ | |
781 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
782 | } |
783 | ||
784 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
785 | size_t size, enum dma_data_direction dir, | |
786 | struct dma_attrs *attrs) | |
787 | { | |
788 | unmap_single(hwdev, dev_addr, size, dir); | |
1da177e4 | 789 | } |
f98eee8e | 790 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 791 | |
1da177e4 LT |
792 | /* |
793 | * Make physical memory consistent for a single streaming mode DMA translation | |
794 | * after a transfer. | |
795 | * | |
ceb5ac32 | 796 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
797 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
798 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
799 | * address back to the card, you must first perform a |
800 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
801 | */ | |
be6b0267 | 802 | static void |
8270f3f1 | 803 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
d7ef1533 KRW |
804 | size_t size, enum dma_data_direction dir, |
805 | enum dma_sync_target target) | |
1da177e4 | 806 | { |
862d196b | 807 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 808 | |
34814545 | 809 | BUG_ON(dir == DMA_NONE); |
380d6878 | 810 | |
02ca646e | 811 | if (is_swiotlb_buffer(paddr)) { |
fbfda893 | 812 | swiotlb_tbl_sync_single(hwdev, paddr, size, dir, target); |
380d6878 BB |
813 | return; |
814 | } | |
815 | ||
816 | if (dir != DMA_FROM_DEVICE) | |
817 | return; | |
818 | ||
02ca646e | 819 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
820 | } |
821 | ||
8270f3f1 JL |
822 | void |
823 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 824 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 825 | { |
de69e0f0 | 826 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 827 | } |
874d6a95 | 828 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 829 | |
1da177e4 LT |
830 | void |
831 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 832 | size_t size, enum dma_data_direction dir) |
1da177e4 | 833 | { |
de69e0f0 | 834 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 835 | } |
874d6a95 | 836 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 LT |
837 | |
838 | /* | |
839 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 840 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
841 | * interface. Here the scatter gather list elements are each tagged with the |
842 | * appropriate dma address and length. They are obtained via | |
843 | * sg_dma_{address,length}(SG). | |
844 | * | |
845 | * NOTE: An implementation may be able to use a smaller number of | |
846 | * DMA address/length pairs than there are SG table elements. | |
847 | * (for example via virtual mapping capabilities) | |
848 | * The routine returns the number of addr/length pairs actually | |
849 | * used, at most nents. | |
850 | * | |
ceb5ac32 | 851 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
852 | * same here. |
853 | */ | |
854 | int | |
309df0c5 | 855 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
160c1d8e | 856 | enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 857 | { |
dbfd49fe | 858 | struct scatterlist *sg; |
1da177e4 LT |
859 | int i; |
860 | ||
34814545 | 861 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 862 | |
dbfd49fe | 863 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 864 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 865 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 866 | |
cf56e3f2 | 867 | if (swiotlb_force || |
b9394647 | 868 | !dma_capable(hwdev, dev_addr, sg->length)) { |
e05ed4d1 AD |
869 | phys_addr_t map = map_single(hwdev, sg_phys(sg), |
870 | sg->length, dir); | |
871 | if (map == SWIOTLB_MAP_ERROR) { | |
1da177e4 LT |
872 | /* Don't panic here, we expect map_sg users |
873 | to do proper error handling. */ | |
874 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
875 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
876 | attrs); | |
4d86ec7a | 877 | sg_dma_len(sgl) = 0; |
1da177e4 LT |
878 | return 0; |
879 | } | |
e05ed4d1 | 880 | sg->dma_address = phys_to_dma(hwdev, map); |
1da177e4 LT |
881 | } else |
882 | sg->dma_address = dev_addr; | |
4d86ec7a | 883 | sg_dma_len(sg) = sg->length; |
1da177e4 LT |
884 | } |
885 | return nelems; | |
886 | } | |
309df0c5 AK |
887 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
888 | ||
889 | int | |
890 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
22d48269 | 891 | enum dma_data_direction dir) |
309df0c5 AK |
892 | { |
893 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
894 | } | |
874d6a95 | 895 | EXPORT_SYMBOL(swiotlb_map_sg); |
1da177e4 LT |
896 | |
897 | /* | |
898 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 899 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
900 | */ |
901 | void | |
309df0c5 | 902 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
160c1d8e | 903 | int nelems, enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 904 | { |
dbfd49fe | 905 | struct scatterlist *sg; |
1da177e4 LT |
906 | int i; |
907 | ||
34814545 | 908 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 909 | |
7fcebbd2 | 910 | for_each_sg(sgl, sg, nelems, i) |
4d86ec7a | 911 | unmap_single(hwdev, sg->dma_address, sg_dma_len(sg), dir); |
7fcebbd2 | 912 | |
1da177e4 | 913 | } |
309df0c5 AK |
914 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
915 | ||
916 | void | |
917 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
22d48269 | 918 | enum dma_data_direction dir) |
309df0c5 AK |
919 | { |
920 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
921 | } | |
874d6a95 | 922 | EXPORT_SYMBOL(swiotlb_unmap_sg); |
1da177e4 LT |
923 | |
924 | /* | |
925 | * Make physical memory consistent for a set of streaming mode DMA translations | |
926 | * after a transfer. | |
927 | * | |
928 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
929 | * and usage. | |
930 | */ | |
be6b0267 | 931 | static void |
dbfd49fe | 932 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
d7ef1533 KRW |
933 | int nelems, enum dma_data_direction dir, |
934 | enum dma_sync_target target) | |
1da177e4 | 935 | { |
dbfd49fe | 936 | struct scatterlist *sg; |
1da177e4 LT |
937 | int i; |
938 | ||
380d6878 BB |
939 | for_each_sg(sgl, sg, nelems, i) |
940 | swiotlb_sync_single(hwdev, sg->dma_address, | |
4d86ec7a | 941 | sg_dma_len(sg), dir, target); |
1da177e4 LT |
942 | } |
943 | ||
8270f3f1 JL |
944 | void |
945 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 946 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 947 | { |
de69e0f0 | 948 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 949 | } |
874d6a95 | 950 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 951 | |
1da177e4 LT |
952 | void |
953 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 954 | int nelems, enum dma_data_direction dir) |
1da177e4 | 955 | { |
de69e0f0 | 956 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 957 | } |
874d6a95 | 958 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
959 | |
960 | int | |
8d8bb39b | 961 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 962 | { |
ee3f6ba8 | 963 | return (dma_addr == phys_to_dma(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 964 | } |
874d6a95 | 965 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
966 | |
967 | /* | |
17e5ad6c | 968 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 969 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 970 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
971 | * this function. |
972 | */ | |
973 | int | |
563aaf06 | 974 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 975 | { |
c40dba06 | 976 | return phys_to_dma(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 977 | } |
1da177e4 | 978 | EXPORT_SYMBOL(swiotlb_dma_supported); |