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CommitLineData
1da177e4
LT
1/*
2 * Dynamic DMA mapping support.
3 *
563aaf06 4 * This implementation is a fallback for platforms that do not support
1da177e4
LT
5 * I/O TLBs (aka DMA address translation hardware).
6 * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com>
7 * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com>
8 * Copyright (C) 2000, 2003 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 *
11 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
12 * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid
13 * unnecessary i-cache flushing.
569c8bf5
JL
14 * 04/07/.. ak Better overflow handling. Assorted fixes.
15 * 05/09/10 linville Add support for syncing ranges, support syncing for
16 * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup.
fb05a379 17 * 08/12/11 beckyb Add highmem support
1da177e4
LT
18 */
19
20#include <linux/cache.h>
17e5ad6c 21#include <linux/dma-mapping.h>
1da177e4 22#include <linux/mm.h>
8bc3bcc9 23#include <linux/export.h>
1da177e4
LT
24#include <linux/spinlock.h>
25#include <linux/string.h>
0016fdee 26#include <linux/swiotlb.h>
fb05a379 27#include <linux/pfn.h>
1da177e4
LT
28#include <linux/types.h>
29#include <linux/ctype.h>
ef9b1893 30#include <linux/highmem.h>
5a0e3ad6 31#include <linux/gfp.h>
1da177e4
LT
32
33#include <asm/io.h>
1da177e4 34#include <asm/dma.h>
17e5ad6c 35#include <asm/scatterlist.h>
1da177e4
LT
36
37#include <linux/init.h>
38#include <linux/bootmem.h>
a8522509 39#include <linux/iommu-helper.h>
1da177e4
LT
40
41#define OFFSET(val,align) ((unsigned long) \
42 ( (val) & ( (align) - 1)))
43
0b9afede
AW
44#define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT))
45
46/*
47 * Minimum IO TLB size to bother booting with. Systems with mainly
48 * 64bit capable cards will only lightly use the swiotlb. If we can't
49 * allocate a contiguous 1MB, we're probably in trouble anyway.
50 */
51#define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT)
52
1da177e4
LT
53int swiotlb_force;
54
55/*
bfc5501f
KRW
56 * Used to do a quick range check in swiotlb_tbl_unmap_single and
57 * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this
1da177e4
LT
58 * API.
59 */
60static char *io_tlb_start, *io_tlb_end;
61
62/*
b595076a 63 * The number of IO TLB blocks (in groups of 64) between io_tlb_start and
1da177e4
LT
64 * io_tlb_end. This is command line adjustable via setup_io_tlb_npages.
65 */
66static unsigned long io_tlb_nslabs;
67
68/*
69 * When the IOMMU overflows we return a fallback buffer. This sets the size.
70 */
71static unsigned long io_tlb_overflow = 32*1024;
72
03620b2d 73static void *io_tlb_overflow_buffer;
1da177e4
LT
74
75/*
76 * This is a free list describing the number of free entries available from
77 * each index
78 */
79static unsigned int *io_tlb_list;
80static unsigned int io_tlb_index;
81
82/*
83 * We need to save away the original address corresponding to a mapped entry
84 * for the sync operations.
85 */
bc40ac66 86static phys_addr_t *io_tlb_orig_addr;
1da177e4
LT
87
88/*
89 * Protect the above data structures in the map and unmap calls
90 */
91static DEFINE_SPINLOCK(io_tlb_lock);
92
5740afdb
FT
93static int late_alloc;
94
1da177e4
LT
95static int __init
96setup_io_tlb_npages(char *str)
97{
98 if (isdigit(*str)) {
e8579e72 99 io_tlb_nslabs = simple_strtoul(str, &str, 0);
1da177e4
LT
100 /* avoid tail segment of size < IO_TLB_SEGSIZE */
101 io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
102 }
103 if (*str == ',')
104 ++str;
b18485e7 105 if (!strcmp(str, "force"))
1da177e4 106 swiotlb_force = 1;
b18485e7 107
1da177e4
LT
108 return 1;
109}
110__setup("swiotlb=", setup_io_tlb_npages);
111/* make io_tlb_overflow tunable too? */
112
f21ffe9f 113unsigned long swiotlb_nr_tbl(void)
5f98ecdb
FT
114{
115 return io_tlb_nslabs;
116}
f21ffe9f 117EXPORT_SYMBOL_GPL(swiotlb_nr_tbl);
02ca646e 118/* Note that this doesn't work with highmem page */
70a7d3cc
JF
119static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev,
120 volatile void *address)
e08e1f7a 121{
862d196b 122 return phys_to_dma(hwdev, virt_to_phys(address));
e08e1f7a
IC
123}
124
ad32e8cb 125void swiotlb_print_info(void)
2e5b2b86 126{
ad32e8cb 127 unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT;
2e5b2b86 128 phys_addr_t pstart, pend;
2e5b2b86
IC
129
130 pstart = virt_to_phys(io_tlb_start);
131 pend = virt_to_phys(io_tlb_end);
132
2e5b2b86
IC
133 printk(KERN_INFO "Placing %luMB software IO TLB between %p - %p\n",
134 bytes >> 20, io_tlb_start, io_tlb_end);
70a7d3cc
JF
135 printk(KERN_INFO "software IO TLB at phys %#llx - %#llx\n",
136 (unsigned long long)pstart,
137 (unsigned long long)pend);
2e5b2b86
IC
138}
139
abbceff7 140void __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose)
1da177e4 141{
563aaf06 142 unsigned long i, bytes;
1da177e4 143
abbceff7 144 bytes = nslabs << IO_TLB_SHIFT;
1da177e4 145
abbceff7
FT
146 io_tlb_nslabs = nslabs;
147 io_tlb_start = tlb;
563aaf06 148 io_tlb_end = io_tlb_start + bytes;
1da177e4
LT
149
150 /*
151 * Allocate and initialize the free list array. This array is used
152 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
153 * between io_tlb_start and io_tlb_end.
154 */
e79f86b2 155 io_tlb_list = alloc_bootmem_pages(PAGE_ALIGN(io_tlb_nslabs * sizeof(int)));
25667d67 156 for (i = 0; i < io_tlb_nslabs; i++)
1da177e4
LT
157 io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
158 io_tlb_index = 0;
e79f86b2 159 io_tlb_orig_addr = alloc_bootmem_pages(PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)));
1da177e4
LT
160
161 /*
162 * Get the overflow emergency buffer
163 */
e79f86b2 164 io_tlb_overflow_buffer = alloc_bootmem_low_pages(PAGE_ALIGN(io_tlb_overflow));
563aaf06
JB
165 if (!io_tlb_overflow_buffer)
166 panic("Cannot allocate SWIOTLB overflow buffer!\n");
ad32e8cb
FT
167 if (verbose)
168 swiotlb_print_info();
1da177e4
LT
169}
170
abbceff7
FT
171/*
172 * Statically reserve bounce buffer space and initialize bounce buffer data
173 * structures for the software IO TLB used to implement the DMA API.
174 */
175void __init
176swiotlb_init_with_default_size(size_t default_size, int verbose)
177{
178 unsigned long bytes;
179
180 if (!io_tlb_nslabs) {
181 io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
182 io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
183 }
184
185 bytes = io_tlb_nslabs << IO_TLB_SHIFT;
186
187 /*
188 * Get IO TLB memory from the low pages
189 */
e79f86b2 190 io_tlb_start = alloc_bootmem_low_pages(PAGE_ALIGN(bytes));
abbceff7
FT
191 if (!io_tlb_start)
192 panic("Cannot allocate SWIOTLB buffer");
193
194 swiotlb_init_with_tbl(io_tlb_start, io_tlb_nslabs, verbose);
195}
196
563aaf06 197void __init
ad32e8cb 198swiotlb_init(int verbose)
1da177e4 199{
ad32e8cb 200 swiotlb_init_with_default_size(64 * (1<<20), verbose); /* default to 64MB */
1da177e4
LT
201}
202
0b9afede
AW
203/*
204 * Systems with larger DMA zones (those that don't support ISA) can
205 * initialize the swiotlb later using the slab allocator if needed.
206 * This should be just like above, but with some error catching.
207 */
208int
563aaf06 209swiotlb_late_init_with_default_size(size_t default_size)
0b9afede 210{
563aaf06 211 unsigned long i, bytes, req_nslabs = io_tlb_nslabs;
0b9afede
AW
212 unsigned int order;
213
214 if (!io_tlb_nslabs) {
215 io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
216 io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
217 }
218
219 /*
220 * Get IO TLB memory from the low pages
221 */
563aaf06 222 order = get_order(io_tlb_nslabs << IO_TLB_SHIFT);
0b9afede 223 io_tlb_nslabs = SLABS_PER_PAGE << order;
563aaf06 224 bytes = io_tlb_nslabs << IO_TLB_SHIFT;
0b9afede
AW
225
226 while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) {
bb52196b
FT
227 io_tlb_start = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN,
228 order);
0b9afede
AW
229 if (io_tlb_start)
230 break;
231 order--;
232 }
233
234 if (!io_tlb_start)
235 goto cleanup1;
236
563aaf06 237 if (order != get_order(bytes)) {
0b9afede
AW
238 printk(KERN_WARNING "Warning: only able to allocate %ld MB "
239 "for software IO TLB\n", (PAGE_SIZE << order) >> 20);
240 io_tlb_nslabs = SLABS_PER_PAGE << order;
563aaf06 241 bytes = io_tlb_nslabs << IO_TLB_SHIFT;
0b9afede 242 }
563aaf06
JB
243 io_tlb_end = io_tlb_start + bytes;
244 memset(io_tlb_start, 0, bytes);
0b9afede
AW
245
246 /*
247 * Allocate and initialize the free list array. This array is used
248 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
249 * between io_tlb_start and io_tlb_end.
250 */
251 io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL,
252 get_order(io_tlb_nslabs * sizeof(int)));
253 if (!io_tlb_list)
254 goto cleanup2;
255
256 for (i = 0; i < io_tlb_nslabs; i++)
257 io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
258 io_tlb_index = 0;
259
bc40ac66
BB
260 io_tlb_orig_addr = (phys_addr_t *)
261 __get_free_pages(GFP_KERNEL,
262 get_order(io_tlb_nslabs *
263 sizeof(phys_addr_t)));
0b9afede
AW
264 if (!io_tlb_orig_addr)
265 goto cleanup3;
266
bc40ac66 267 memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(phys_addr_t));
0b9afede
AW
268
269 /*
270 * Get the overflow emergency buffer
271 */
272 io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA,
273 get_order(io_tlb_overflow));
274 if (!io_tlb_overflow_buffer)
275 goto cleanup4;
276
ad32e8cb 277 swiotlb_print_info();
0b9afede 278
5740afdb
FT
279 late_alloc = 1;
280
0b9afede
AW
281 return 0;
282
283cleanup4:
bc40ac66
BB
284 free_pages((unsigned long)io_tlb_orig_addr,
285 get_order(io_tlb_nslabs * sizeof(phys_addr_t)));
0b9afede
AW
286 io_tlb_orig_addr = NULL;
287cleanup3:
25667d67
TL
288 free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs *
289 sizeof(int)));
0b9afede 290 io_tlb_list = NULL;
0b9afede 291cleanup2:
563aaf06 292 io_tlb_end = NULL;
0b9afede
AW
293 free_pages((unsigned long)io_tlb_start, order);
294 io_tlb_start = NULL;
295cleanup1:
296 io_tlb_nslabs = req_nslabs;
297 return -ENOMEM;
298}
299
5740afdb
FT
300void __init swiotlb_free(void)
301{
302 if (!io_tlb_overflow_buffer)
303 return;
304
305 if (late_alloc) {
306 free_pages((unsigned long)io_tlb_overflow_buffer,
307 get_order(io_tlb_overflow));
308 free_pages((unsigned long)io_tlb_orig_addr,
309 get_order(io_tlb_nslabs * sizeof(phys_addr_t)));
310 free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs *
311 sizeof(int)));
312 free_pages((unsigned long)io_tlb_start,
313 get_order(io_tlb_nslabs << IO_TLB_SHIFT));
314 } else {
315 free_bootmem_late(__pa(io_tlb_overflow_buffer),
e79f86b2 316 PAGE_ALIGN(io_tlb_overflow));
5740afdb 317 free_bootmem_late(__pa(io_tlb_orig_addr),
e79f86b2 318 PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)));
5740afdb 319 free_bootmem_late(__pa(io_tlb_list),
e79f86b2 320 PAGE_ALIGN(io_tlb_nslabs * sizeof(int)));
5740afdb 321 free_bootmem_late(__pa(io_tlb_start),
e79f86b2 322 PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT));
5740afdb 323 }
f21ffe9f 324 io_tlb_nslabs = 0;
5740afdb
FT
325}
326
02ca646e 327static int is_swiotlb_buffer(phys_addr_t paddr)
640aebfe 328{
02ca646e
FT
329 return paddr >= virt_to_phys(io_tlb_start) &&
330 paddr < virt_to_phys(io_tlb_end);
640aebfe
FT
331}
332
fb05a379
BB
333/*
334 * Bounce: copy the swiotlb buffer back to the original dma location
335 */
d7ef1533
KRW
336void swiotlb_bounce(phys_addr_t phys, char *dma_addr, size_t size,
337 enum dma_data_direction dir)
fb05a379
BB
338{
339 unsigned long pfn = PFN_DOWN(phys);
340
341 if (PageHighMem(pfn_to_page(pfn))) {
342 /* The buffer does not have a mapping. Map it in and copy */
343 unsigned int offset = phys & ~PAGE_MASK;
344 char *buffer;
345 unsigned int sz = 0;
346 unsigned long flags;
347
348 while (size) {
67131ad0 349 sz = min_t(size_t, PAGE_SIZE - offset, size);
fb05a379
BB
350
351 local_irq_save(flags);
c3eede8e 352 buffer = kmap_atomic(pfn_to_page(pfn));
fb05a379
BB
353 if (dir == DMA_TO_DEVICE)
354 memcpy(dma_addr, buffer + offset, sz);
ef9b1893 355 else
fb05a379 356 memcpy(buffer + offset, dma_addr, sz);
c3eede8e 357 kunmap_atomic(buffer);
ef9b1893 358 local_irq_restore(flags);
fb05a379
BB
359
360 size -= sz;
361 pfn++;
362 dma_addr += sz;
363 offset = 0;
ef9b1893
JF
364 }
365 } else {
ef9b1893 366 if (dir == DMA_TO_DEVICE)
fb05a379 367 memcpy(dma_addr, phys_to_virt(phys), size);
ef9b1893 368 else
fb05a379 369 memcpy(phys_to_virt(phys), dma_addr, size);
ef9b1893 370 }
1b548f66 371}
d7ef1533 372EXPORT_SYMBOL_GPL(swiotlb_bounce);
1b548f66 373
eb605a57 374void *swiotlb_tbl_map_single(struct device *hwdev, dma_addr_t tbl_dma_addr,
22d48269
KRW
375 phys_addr_t phys, size_t size,
376 enum dma_data_direction dir)
1da177e4
LT
377{
378 unsigned long flags;
379 char *dma_addr;
380 unsigned int nslots, stride, index, wrap;
381 int i;
681cc5cd
FT
382 unsigned long mask;
383 unsigned long offset_slots;
384 unsigned long max_slots;
385
386 mask = dma_get_seg_boundary(hwdev);
681cc5cd 387
eb605a57
FT
388 tbl_dma_addr &= mask;
389
390 offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
a5ddde4a
IC
391
392 /*
393 * Carefully handle integer overflow which can occur when mask == ~0UL.
394 */
b15a3891
JB
395 max_slots = mask + 1
396 ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT
397 : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT);
1da177e4
LT
398
399 /*
400 * For mappings greater than a page, we limit the stride (and
401 * hence alignment) to a page size.
402 */
403 nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
404 if (size > PAGE_SIZE)
405 stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
406 else
407 stride = 1;
408
34814545 409 BUG_ON(!nslots);
1da177e4
LT
410
411 /*
412 * Find suitable number of IO TLB entries size that will fit this
413 * request and allocate a buffer from that IO TLB pool.
414 */
415 spin_lock_irqsave(&io_tlb_lock, flags);
a7133a15
AM
416 index = ALIGN(io_tlb_index, stride);
417 if (index >= io_tlb_nslabs)
418 index = 0;
419 wrap = index;
420
421 do {
a8522509
FT
422 while (iommu_is_span_boundary(index, nslots, offset_slots,
423 max_slots)) {
b15a3891
JB
424 index += stride;
425 if (index >= io_tlb_nslabs)
426 index = 0;
a7133a15
AM
427 if (index == wrap)
428 goto not_found;
429 }
430
431 /*
432 * If we find a slot that indicates we have 'nslots' number of
433 * contiguous buffers, we allocate the buffers from that slot
434 * and mark the entries as '0' indicating unavailable.
435 */
436 if (io_tlb_list[index] >= nslots) {
437 int count = 0;
438
439 for (i = index; i < (int) (index + nslots); i++)
440 io_tlb_list[i] = 0;
441 for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--)
442 io_tlb_list[i] = ++count;
443 dma_addr = io_tlb_start + (index << IO_TLB_SHIFT);
1da177e4 444
a7133a15
AM
445 /*
446 * Update the indices to avoid searching in the next
447 * round.
448 */
449 io_tlb_index = ((index + nslots) < io_tlb_nslabs
450 ? (index + nslots) : 0);
451
452 goto found;
453 }
454 index += stride;
455 if (index >= io_tlb_nslabs)
456 index = 0;
457 } while (index != wrap);
458
459not_found:
460 spin_unlock_irqrestore(&io_tlb_lock, flags);
461 return NULL;
462found:
1da177e4
LT
463 spin_unlock_irqrestore(&io_tlb_lock, flags);
464
465 /*
466 * Save away the mapping from the original address to the DMA address.
467 * This is needed when we sync the memory. Then we sync the buffer if
468 * needed.
469 */
bc40ac66
BB
470 for (i = 0; i < nslots; i++)
471 io_tlb_orig_addr[index+i] = phys + (i << IO_TLB_SHIFT);
1da177e4 472 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)
fb05a379 473 swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE);
1da177e4
LT
474
475 return dma_addr;
476}
d7ef1533 477EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single);
1da177e4 478
eb605a57
FT
479/*
480 * Allocates bounce buffer and returns its kernel virtual address.
481 */
482
483static void *
22d48269
KRW
484map_single(struct device *hwdev, phys_addr_t phys, size_t size,
485 enum dma_data_direction dir)
eb605a57
FT
486{
487 dma_addr_t start_dma_addr = swiotlb_virt_to_bus(hwdev, io_tlb_start);
488
489 return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, dir);
490}
491
1da177e4
LT
492/*
493 * dma_addr is the kernel virtual address of the bounce buffer to unmap.
494 */
d7ef1533 495void
bfc5501f 496swiotlb_tbl_unmap_single(struct device *hwdev, char *dma_addr, size_t size,
22d48269 497 enum dma_data_direction dir)
1da177e4
LT
498{
499 unsigned long flags;
500 int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
501 int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT;
bc40ac66 502 phys_addr_t phys = io_tlb_orig_addr[index];
1da177e4
LT
503
504 /*
505 * First, sync the memory before unmapping the entry
506 */
bc40ac66 507 if (phys && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL)))
fb05a379 508 swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE);
1da177e4
LT
509
510 /*
511 * Return the buffer to the free list by setting the corresponding
af901ca1 512 * entries to indicate the number of contiguous entries available.
1da177e4
LT
513 * While returning the entries to the free list, we merge the entries
514 * with slots below and above the pool being returned.
515 */
516 spin_lock_irqsave(&io_tlb_lock, flags);
517 {
518 count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ?
519 io_tlb_list[index + nslots] : 0);
520 /*
521 * Step 1: return the slots to the free list, merging the
522 * slots with superceeding slots
523 */
524 for (i = index + nslots - 1; i >= index; i--)
525 io_tlb_list[i] = ++count;
526 /*
527 * Step 2: merge the returned slots with the preceding slots,
528 * if available (non zero)
529 */
530 for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--)
531 io_tlb_list[i] = ++count;
532 }
533 spin_unlock_irqrestore(&io_tlb_lock, flags);
534}
d7ef1533 535EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single);
1da177e4 536
d7ef1533 537void
bfc5501f 538swiotlb_tbl_sync_single(struct device *hwdev, char *dma_addr, size_t size,
d7ef1533
KRW
539 enum dma_data_direction dir,
540 enum dma_sync_target target)
1da177e4 541{
bc40ac66
BB
542 int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT;
543 phys_addr_t phys = io_tlb_orig_addr[index];
544
545 phys += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1));
df336d1c 546
de69e0f0
JL
547 switch (target) {
548 case SYNC_FOR_CPU:
549 if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL))
fb05a379 550 swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE);
34814545
ES
551 else
552 BUG_ON(dir != DMA_TO_DEVICE);
de69e0f0
JL
553 break;
554 case SYNC_FOR_DEVICE:
555 if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL))
fb05a379 556 swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE);
34814545
ES
557 else
558 BUG_ON(dir != DMA_FROM_DEVICE);
de69e0f0
JL
559 break;
560 default:
1da177e4 561 BUG();
de69e0f0 562 }
1da177e4 563}
d7ef1533 564EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single);
1da177e4
LT
565
566void *
567swiotlb_alloc_coherent(struct device *hwdev, size_t size,
06a54497 568 dma_addr_t *dma_handle, gfp_t flags)
1da177e4 569{
563aaf06 570 dma_addr_t dev_addr;
1da177e4
LT
571 void *ret;
572 int order = get_order(size);
284901a9 573 u64 dma_mask = DMA_BIT_MASK(32);
1e74f300
FT
574
575 if (hwdev && hwdev->coherent_dma_mask)
576 dma_mask = hwdev->coherent_dma_mask;
1da177e4 577
25667d67 578 ret = (void *)__get_free_pages(flags, order);
ac2b3e67 579 if (ret && swiotlb_virt_to_bus(hwdev, ret) + size - 1 > dma_mask) {
1da177e4
LT
580 /*
581 * The allocated memory isn't reachable by the device.
1da177e4
LT
582 */
583 free_pages((unsigned long) ret, order);
584 ret = NULL;
585 }
586 if (!ret) {
587 /*
bfc5501f
KRW
588 * We are either out of memory or the device can't DMA to
589 * GFP_DMA memory; fall back on map_single(), which
ceb5ac32 590 * will grab memory from the lowest available address range.
1da177e4 591 */
bc40ac66 592 ret = map_single(hwdev, 0, size, DMA_FROM_DEVICE);
9dfda12b 593 if (!ret)
1da177e4 594 return NULL;
1da177e4
LT
595 }
596
597 memset(ret, 0, size);
70a7d3cc 598 dev_addr = swiotlb_virt_to_bus(hwdev, ret);
1da177e4
LT
599
600 /* Confirm address can be DMA'd by device */
ac2b3e67 601 if (dev_addr + size - 1 > dma_mask) {
563aaf06 602 printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n",
1e74f300 603 (unsigned long long)dma_mask,
563aaf06 604 (unsigned long long)dev_addr);
a2b89b59
FT
605
606 /* DMA_TO_DEVICE to avoid memcpy in unmap_single */
bfc5501f 607 swiotlb_tbl_unmap_single(hwdev, ret, size, DMA_TO_DEVICE);
a2b89b59 608 return NULL;
1da177e4
LT
609 }
610 *dma_handle = dev_addr;
611 return ret;
612}
874d6a95 613EXPORT_SYMBOL(swiotlb_alloc_coherent);
1da177e4
LT
614
615void
616swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr,
02ca646e 617 dma_addr_t dev_addr)
1da177e4 618{
862d196b 619 phys_addr_t paddr = dma_to_phys(hwdev, dev_addr);
02ca646e 620
aa24886e 621 WARN_ON(irqs_disabled());
02ca646e
FT
622 if (!is_swiotlb_buffer(paddr))
623 free_pages((unsigned long)vaddr, get_order(size));
1da177e4 624 else
bfc5501f
KRW
625 /* DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single */
626 swiotlb_tbl_unmap_single(hwdev, vaddr, size, DMA_TO_DEVICE);
1da177e4 627}
874d6a95 628EXPORT_SYMBOL(swiotlb_free_coherent);
1da177e4
LT
629
630static void
22d48269
KRW
631swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir,
632 int do_panic)
1da177e4
LT
633{
634 /*
635 * Ran out of IOMMU space for this operation. This is very bad.
636 * Unfortunately the drivers cannot handle this operation properly.
17e5ad6c 637 * unless they check for dma_mapping_error (most don't)
1da177e4
LT
638 * When the mapping is small enough return a static buffer to limit
639 * the damage, or panic when the transfer is too big.
640 */
563aaf06 641 printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at "
94b32486 642 "device %s\n", size, dev ? dev_name(dev) : "?");
1da177e4 643
c7084b35
CD
644 if (size <= io_tlb_overflow || !do_panic)
645 return;
646
647 if (dir == DMA_BIDIRECTIONAL)
648 panic("DMA: Random memory could be DMA accessed\n");
649 if (dir == DMA_FROM_DEVICE)
650 panic("DMA: Random memory could be DMA written\n");
651 if (dir == DMA_TO_DEVICE)
652 panic("DMA: Random memory could be DMA read\n");
1da177e4
LT
653}
654
655/*
656 * Map a single buffer of the indicated size for DMA in streaming mode. The
17e5ad6c 657 * physical address to use is returned.
1da177e4
LT
658 *
659 * Once the device is given the dma address, the device owns this memory until
ceb5ac32 660 * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed.
1da177e4 661 */
f98eee8e
FT
662dma_addr_t swiotlb_map_page(struct device *dev, struct page *page,
663 unsigned long offset, size_t size,
664 enum dma_data_direction dir,
665 struct dma_attrs *attrs)
1da177e4 666{
f98eee8e 667 phys_addr_t phys = page_to_phys(page) + offset;
862d196b 668 dma_addr_t dev_addr = phys_to_dma(dev, phys);
1da177e4
LT
669 void *map;
670
34814545 671 BUG_ON(dir == DMA_NONE);
1da177e4 672 /*
ceb5ac32 673 * If the address happens to be in the device's DMA window,
1da177e4
LT
674 * we can safely return the device addr and not worry about bounce
675 * buffering it.
676 */
b9394647 677 if (dma_capable(dev, dev_addr, size) && !swiotlb_force)
1da177e4
LT
678 return dev_addr;
679
680 /*
681 * Oh well, have to allocate and map a bounce buffer.
682 */
f98eee8e 683 map = map_single(dev, phys, size, dir);
1da177e4 684 if (!map) {
f98eee8e 685 swiotlb_full(dev, size, dir, 1);
1da177e4
LT
686 map = io_tlb_overflow_buffer;
687 }
688
f98eee8e 689 dev_addr = swiotlb_virt_to_bus(dev, map);
1da177e4
LT
690
691 /*
692 * Ensure that the address returned is DMA'ble
693 */
fba99fa3
FT
694 if (!dma_capable(dev, dev_addr, size)) {
695 swiotlb_tbl_unmap_single(dev, map, size, dir);
696 dev_addr = swiotlb_virt_to_bus(dev, io_tlb_overflow_buffer);
697 }
1da177e4
LT
698
699 return dev_addr;
700}
f98eee8e 701EXPORT_SYMBOL_GPL(swiotlb_map_page);
1da177e4 702
1da177e4
LT
703/*
704 * Unmap a single streaming mode DMA translation. The dma_addr and size must
ceb5ac32 705 * match what was provided for in a previous swiotlb_map_page call. All
1da177e4
LT
706 * other usages are undefined.
707 *
708 * After this call, reads by the cpu to the buffer are guaranteed to see
709 * whatever the device wrote there.
710 */
7fcebbd2 711static void unmap_single(struct device *hwdev, dma_addr_t dev_addr,
22d48269 712 size_t size, enum dma_data_direction dir)
1da177e4 713{
862d196b 714 phys_addr_t paddr = dma_to_phys(hwdev, dev_addr);
1da177e4 715
34814545 716 BUG_ON(dir == DMA_NONE);
7fcebbd2 717
02ca646e 718 if (is_swiotlb_buffer(paddr)) {
bfc5501f 719 swiotlb_tbl_unmap_single(hwdev, phys_to_virt(paddr), size, dir);
7fcebbd2
BB
720 return;
721 }
722
723 if (dir != DMA_FROM_DEVICE)
724 return;
725
02ca646e
FT
726 /*
727 * phys_to_virt doesn't work with hihgmem page but we could
728 * call dma_mark_clean() with hihgmem page here. However, we
729 * are fine since dma_mark_clean() is null on POWERPC. We can
730 * make dma_mark_clean() take a physical address if necessary.
731 */
732 dma_mark_clean(phys_to_virt(paddr), size);
7fcebbd2
BB
733}
734
735void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr,
736 size_t size, enum dma_data_direction dir,
737 struct dma_attrs *attrs)
738{
739 unmap_single(hwdev, dev_addr, size, dir);
1da177e4 740}
f98eee8e 741EXPORT_SYMBOL_GPL(swiotlb_unmap_page);
874d6a95 742
1da177e4
LT
743/*
744 * Make physical memory consistent for a single streaming mode DMA translation
745 * after a transfer.
746 *
ceb5ac32 747 * If you perform a swiotlb_map_page() but wish to interrogate the buffer
17e5ad6c
TL
748 * using the cpu, yet do not wish to teardown the dma mapping, you must
749 * call this function before doing so. At the next point you give the dma
1da177e4
LT
750 * address back to the card, you must first perform a
751 * swiotlb_dma_sync_for_device, and then the device again owns the buffer
752 */
be6b0267 753static void
8270f3f1 754swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr,
d7ef1533
KRW
755 size_t size, enum dma_data_direction dir,
756 enum dma_sync_target target)
1da177e4 757{
862d196b 758 phys_addr_t paddr = dma_to_phys(hwdev, dev_addr);
1da177e4 759
34814545 760 BUG_ON(dir == DMA_NONE);
380d6878 761
02ca646e 762 if (is_swiotlb_buffer(paddr)) {
bfc5501f
KRW
763 swiotlb_tbl_sync_single(hwdev, phys_to_virt(paddr), size, dir,
764 target);
380d6878
BB
765 return;
766 }
767
768 if (dir != DMA_FROM_DEVICE)
769 return;
770
02ca646e 771 dma_mark_clean(phys_to_virt(paddr), size);
1da177e4
LT
772}
773
8270f3f1
JL
774void
775swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
160c1d8e 776 size_t size, enum dma_data_direction dir)
8270f3f1 777{
de69e0f0 778 swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU);
8270f3f1 779}
874d6a95 780EXPORT_SYMBOL(swiotlb_sync_single_for_cpu);
8270f3f1 781
1da177e4
LT
782void
783swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr,
160c1d8e 784 size_t size, enum dma_data_direction dir)
1da177e4 785{
de69e0f0 786 swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE);
1da177e4 787}
874d6a95 788EXPORT_SYMBOL(swiotlb_sync_single_for_device);
1da177e4
LT
789
790/*
791 * Map a set of buffers described by scatterlist in streaming mode for DMA.
ceb5ac32 792 * This is the scatter-gather version of the above swiotlb_map_page
1da177e4
LT
793 * interface. Here the scatter gather list elements are each tagged with the
794 * appropriate dma address and length. They are obtained via
795 * sg_dma_{address,length}(SG).
796 *
797 * NOTE: An implementation may be able to use a smaller number of
798 * DMA address/length pairs than there are SG table elements.
799 * (for example via virtual mapping capabilities)
800 * The routine returns the number of addr/length pairs actually
801 * used, at most nents.
802 *
ceb5ac32 803 * Device ownership issues as mentioned above for swiotlb_map_page are the
1da177e4
LT
804 * same here.
805 */
806int
309df0c5 807swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems,
160c1d8e 808 enum dma_data_direction dir, struct dma_attrs *attrs)
1da177e4 809{
dbfd49fe 810 struct scatterlist *sg;
1da177e4
LT
811 int i;
812
34814545 813 BUG_ON(dir == DMA_NONE);
1da177e4 814
dbfd49fe 815 for_each_sg(sgl, sg, nelems, i) {
961d7d0e 816 phys_addr_t paddr = sg_phys(sg);
862d196b 817 dma_addr_t dev_addr = phys_to_dma(hwdev, paddr);
bc40ac66 818
cf56e3f2 819 if (swiotlb_force ||
b9394647 820 !dma_capable(hwdev, dev_addr, sg->length)) {
bc40ac66
BB
821 void *map = map_single(hwdev, sg_phys(sg),
822 sg->length, dir);
7e870233 823 if (!map) {
1da177e4
LT
824 /* Don't panic here, we expect map_sg users
825 to do proper error handling. */
826 swiotlb_full(hwdev, sg->length, dir, 0);
309df0c5
AK
827 swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir,
828 attrs);
dbfd49fe 829 sgl[0].dma_length = 0;
1da177e4
LT
830 return 0;
831 }
70a7d3cc 832 sg->dma_address = swiotlb_virt_to_bus(hwdev, map);
1da177e4
LT
833 } else
834 sg->dma_address = dev_addr;
835 sg->dma_length = sg->length;
836 }
837 return nelems;
838}
309df0c5
AK
839EXPORT_SYMBOL(swiotlb_map_sg_attrs);
840
841int
842swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems,
22d48269 843 enum dma_data_direction dir)
309df0c5
AK
844{
845 return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL);
846}
874d6a95 847EXPORT_SYMBOL(swiotlb_map_sg);
1da177e4
LT
848
849/*
850 * Unmap a set of streaming mode DMA translations. Again, cpu read rules
ceb5ac32 851 * concerning calls here are the same as for swiotlb_unmap_page() above.
1da177e4
LT
852 */
853void
309df0c5 854swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl,
160c1d8e 855 int nelems, enum dma_data_direction dir, struct dma_attrs *attrs)
1da177e4 856{
dbfd49fe 857 struct scatterlist *sg;
1da177e4
LT
858 int i;
859
34814545 860 BUG_ON(dir == DMA_NONE);
1da177e4 861
7fcebbd2
BB
862 for_each_sg(sgl, sg, nelems, i)
863 unmap_single(hwdev, sg->dma_address, sg->dma_length, dir);
864
1da177e4 865}
309df0c5
AK
866EXPORT_SYMBOL(swiotlb_unmap_sg_attrs);
867
868void
869swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems,
22d48269 870 enum dma_data_direction dir)
309df0c5
AK
871{
872 return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL);
873}
874d6a95 874EXPORT_SYMBOL(swiotlb_unmap_sg);
1da177e4
LT
875
876/*
877 * Make physical memory consistent for a set of streaming mode DMA translations
878 * after a transfer.
879 *
880 * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules
881 * and usage.
882 */
be6b0267 883static void
dbfd49fe 884swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl,
d7ef1533
KRW
885 int nelems, enum dma_data_direction dir,
886 enum dma_sync_target target)
1da177e4 887{
dbfd49fe 888 struct scatterlist *sg;
1da177e4
LT
889 int i;
890
380d6878
BB
891 for_each_sg(sgl, sg, nelems, i)
892 swiotlb_sync_single(hwdev, sg->dma_address,
de69e0f0 893 sg->dma_length, dir, target);
1da177e4
LT
894}
895
8270f3f1
JL
896void
897swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
160c1d8e 898 int nelems, enum dma_data_direction dir)
8270f3f1 899{
de69e0f0 900 swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU);
8270f3f1 901}
874d6a95 902EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu);
8270f3f1 903
1da177e4
LT
904void
905swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
160c1d8e 906 int nelems, enum dma_data_direction dir)
1da177e4 907{
de69e0f0 908 swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE);
1da177e4 909}
874d6a95 910EXPORT_SYMBOL(swiotlb_sync_sg_for_device);
1da177e4
LT
911
912int
8d8bb39b 913swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr)
1da177e4 914{
70a7d3cc 915 return (dma_addr == swiotlb_virt_to_bus(hwdev, io_tlb_overflow_buffer));
1da177e4 916}
874d6a95 917EXPORT_SYMBOL(swiotlb_dma_mapping_error);
1da177e4
LT
918
919/*
17e5ad6c 920 * Return whether the given device DMA address mask can be supported
1da177e4 921 * properly. For example, if your device can only drive the low 24-bits
17e5ad6c 922 * during bus mastering, then you would pass 0x00ffffff as the mask to
1da177e4
LT
923 * this function.
924 */
925int
563aaf06 926swiotlb_dma_supported(struct device *hwdev, u64 mask)
1da177e4 927{
70a7d3cc 928 return swiotlb_virt_to_bus(hwdev, io_tlb_end - 1) <= mask;
1da177e4 929}
1da177e4 930EXPORT_SYMBOL(swiotlb_dma_supported);