]> git.proxmox.com Git - mirror_ubuntu-disco-kernel.git/blame - sound/soc/ti/davinci-mcasp.c
projects / mirror_ubuntu-disco-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: davinci-mcasp: Fix clang warning without CONFIG_PM
[mirror_ubuntu-disco-kernel.git] / sound / soc / ti / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
ae726e93 24#include <linux/clk.h>
10884347 25#include <linux/pm_runtime.h>
3e3b8c34
HG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
9759e7ef 29#include <linux/platform_data/davinci_asp.h>
a75a053f 30#include <linux/math64.h>
ca3d9433 31#include <linux/bitmap.h>
b67f4487 32
6479285d 33#include <sound/asoundef.h>
b67f4487
C		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/initval.h>
38#include <sound/soc.h>
453c4990 39#include <sound/dmaengine_pcm.h>
b67f4487 40
f3f9cfa8 41#include "edma-pcm.h"
f2055e14 42#include "sdma-pcm.h"
b67f4487
C		 43#include "davinci-mcasp.h"
44
0bf0e8ae
PU		 45#define MCASP_MAX_AFIFO_DEPTH 64
46
c99b0d69 47#ifdef CONFIG_PM
1cc0c054
PU		 48static u32 context_regs[] = {
49 DAVINCI_MCASP_TXFMCTL_REG,
50 DAVINCI_MCASP_RXFMCTL_REG,
51 DAVINCI_MCASP_TXFMT_REG,
52 DAVINCI_MCASP_RXFMT_REG,
53 DAVINCI_MCASP_ACLKXCTL_REG,
54 DAVINCI_MCASP_ACLKRCTL_REG,
f114ce60
PU		 55 DAVINCI_MCASP_AHCLKXCTL_REG,
56 DAVINCI_MCASP_AHCLKRCTL_REG,
1cc0c054 57 DAVINCI_MCASP_PDIR_REG,
f114ce60
PU		 58 DAVINCI_MCASP_RXMASK_REG,
59 DAVINCI_MCASP_TXMASK_REG,
60 DAVINCI_MCASP_RXTDM_REG,
61 DAVINCI_MCASP_TXTDM_REG,
1cc0c054
PU		 62};
63
790bb94b 64struct davinci_mcasp_context {
1cc0c054 65 u32 config_regs[ARRAY_SIZE(context_regs)];
f114ce60
PU		 66 u32 afifo_regs[2]; /* for read/write fifo control registers */
67 u32 *xrsr_regs; /* for serializer configuration */
6afda7f5 68 bool pm_state;
790bb94b 69};
c99b0d69 70#endif
790bb94b 71
a75a053f
JS		 72struct davinci_mcasp_ruledata {
73 struct davinci_mcasp *mcasp;
74 int serializers;
75};
76
70091a3e 77struct davinci_mcasp {
453c4990 78 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 79 void __iomem *base;
487dce88 80 u32 fifo_base;
21400a72 81 struct device *dev;
a7a3324a 82 struct snd_pcm_substream *substreams[2];
4a11ff26 83 unsigned int dai_fmt;
21400a72
PU		 84
85 /* McASP specific data */
86 int tdm_slots;
dd55ff83
JS		 87 u32 tdm_mask[2];
88 int slot_width;
21400a72 89 u8 op_mode;
bc184549 90 u8 dismod;
21400a72
PU		 91 u8 num_serializer;
92 u8 *serial_dir;
93 u8 version;
8267525c 94 u8 bclk_div;
4dcb5a0b 95 int streams;
a7a3324a 96 u32 irq_request[2];
9759e7ef 97 int dma_request[2];
21400a72 98
ab8b14b6
JS		 99 int sysclk_freq;
100 bool bclk_master;
101
ca3d9433
PU		 102 unsigned long pdir; /* Pin direction bitfield */
103
21400a72
PU		 104 /* McASP FIFO related */
105 u8 txnumevt;
106 u8 rxnumevt;
107
cbc7956c
PU		 108 bool dat_port;
109
11277833
PU		 110 /* Used for comstraint setting on the second stream */
111 u32 channels;
112
61754717 113#ifdef CONFIG_PM
790bb94b 114 struct davinci_mcasp_context context;
21400a72 115#endif
a75a053f
JS		 116
117 struct davinci_mcasp_ruledata ruledata[2];
5935a056 118 struct snd_pcm_hw_constraint_list chconstr[2];
21400a72
PU		 119};
120
f68205a7
PU		 121static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
122 u32 val)
b67f4487 123{
f68205a7 124 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 125 __raw_writel(__raw_readl(reg) | val, reg);
126}
127
f68205a7
PU		 128static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
129 u32 val)
b67f4487 130{
f68205a7 131 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 132 __raw_writel((__raw_readl(reg) & ~(val)), reg);
133}
134
f68205a7
PU		 135static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
136 u32 val, u32 mask)
b67f4487 137{
f68205a7 138 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 139 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
140}
141
f68205a7
PU		 142static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
143 u32 val)
b67f4487 144{
f68205a7 145 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 146}
147
f68205a7 148static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 149{
f68205a7 150 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 151}
152
f68205a7 153static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 154{
155 int i = 0;
156
f68205a7 157 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 158
159 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
160 /* loop count is to avoid the lock-up */
161 for (i = 0; i < 1000; i++) {
f68205a7 162 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 163 break;
164 }
165
f68205a7 166 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 167 printk(KERN_ERR "GBLCTL write error\n");
168}
169
4dcb5a0b
PU		 170static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
171{
f68205a7
PU		 172 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
173 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 174
175 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
176}
177
ca3d9433
PU		 178static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
179{
180 u32 bit = PIN_BIT_AMUTE;
181
182 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
183 if (enable)
184 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
185 else
186 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
187 }
188}
189
190static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
191{
192 u32 bit;
193
194 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) {
195 if (enable)
196 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
197 else
198 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
199 }
200}
201
70091a3e 202static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 203{
bb372af0
PU		 204 if (mcasp->rxnumevt) { /* enable FIFO */
205 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
206
207 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
208 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
209 }
210
44982735 211 /* Start clocks */
f68205a7
PU		 212 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
213 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 214 /*
215 * When ASYNC == 0 the transmit and receive sections operate
216 * synchronously from the transmit clock and frame sync. We need to make
217 * sure that the TX signlas are enabled when starting reception.
218 */
219 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
4dcb5a0b
PU		 222 }
223
44982735 224 /* Activate serializer(s) */
1003c27a 225 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
f68205a7 226 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
44982735 227 /* Release RX state machine */
f68205a7 228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
44982735 229 /* Release Frame Sync generator */
f68205a7 230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b 231 if (mcasp_is_synchronous(mcasp))
f68205a7 232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 233
234 /* enable receive IRQs */
235 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
236 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
b67f4487
C		 237}
238
70091a3e 239static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 240{
6a99fb5f
C		 241 u32 cnt;
242
bb372af0
PU		 243 if (mcasp->txnumevt) { /* enable FIFO */
244 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
245
246 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
247 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
248 }
249
36bcecd0 250 /* Start clocks */
f68205a7
PU		 251 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
252 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
ca3d9433
PU		 253 mcasp_set_clk_pdir(mcasp, true);
254
36bcecd0 255 /* Activate serializer(s) */
1003c27a 256 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
f68205a7 257 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
b67f4487 258
36bcecd0 259 /* wait for XDATA to be cleared */
6a99fb5f 260 cnt = 0;
e2a0c9fa
PU		 261 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
262 (cnt < 100000))
6a99fb5f
C		 263 cnt++;
264
ca3d9433
PU		 265 mcasp_set_axr_pdir(mcasp, true);
266
36bcecd0
PU		 267 /* Release TX state machine */
268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
269 /* Release Frame Sync generator */
270 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 271
272 /* enable transmit IRQs */
273 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
274 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
b67f4487
C		 275}
276
70091a3e 277static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 278{
4dcb5a0b
PU		 279 mcasp->streams++;
280
bb372af0 281 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 282 mcasp_start_tx(mcasp);
bb372af0 283 else
70091a3e 284 mcasp_start_rx(mcasp);
b67f4487
C		 285}
286
70091a3e 287static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 288{
a7a3324a
MLC		 289 /* disable IRQ sources */
290 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
291 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
292
4dcb5a0b
PU		 293 /*
294 * In synchronous mode stop the TX clocks if no other stream is
295 * running
296 */
ca3d9433
PU		 297 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
298 mcasp_set_clk_pdir(mcasp, false);
f68205a7 299 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
ca3d9433 300 }
4dcb5a0b 301
f68205a7
PU		 302 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
303 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 304
305 if (mcasp->rxnumevt) { /* disable FIFO */
306 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
307
308 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
309 }
b67f4487
C		 310}
311
70091a3e 312static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 313{
4dcb5a0b
PU		 314 u32 val = 0;
315
a7a3324a
MLC		 316 /* disable IRQ sources */
317 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
318 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
319
4dcb5a0b
PU		 320 /*
321 * In synchronous mode keep TX clocks running if the capture stream is
322 * still running.
323 */
324 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
325 val = TXHCLKRST | TXCLKRST | TXFSRST;
ca3d9433
PU		 326 else
327 mcasp_set_clk_pdir(mcasp, false);
328
4dcb5a0b 329
f68205a7
PU		 330 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
331 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 332
333 if (mcasp->txnumevt) { /* disable FIFO */
334 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
335
336 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
337 }
ca3d9433
PU		 338
339 mcasp_set_axr_pdir(mcasp, false);
b67f4487
C		 340}
341
70091a3e 342static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 343{
4dcb5a0b
PU		 344 mcasp->streams--;
345
0380866a 346 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 347 mcasp_stop_tx(mcasp);
0380866a 348 else
70091a3e 349 mcasp_stop_rx(mcasp);
b67f4487
C		 350}
351
a7a3324a
MLC		 352static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
353{
354 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
355 struct snd_pcm_substream *substream;
356 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
357 u32 handled_mask = 0;
358 u32 stat;
359
360 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
361 if (stat & XUNDRN & irq_mask) {
362 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
363 handled_mask |= XUNDRN;
364
365 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
dae35d1f
TI		 366 if (substream)
367 snd_pcm_stop_xrun(substream);
a7a3324a
MLC		 368 }
369
370 if (!handled_mask)
371 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
372 stat);
373
374 if (stat & XRERR)
375 handled_mask |= XRERR;
376
377 /* Ack the handled event only */
378 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
379
380 return IRQ_RETVAL(handled_mask);
381}
382
383static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
384{
385 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
386 struct snd_pcm_substream *substream;
387 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
388 u32 handled_mask = 0;
389 u32 stat;
390
391 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
392 if (stat & ROVRN & irq_mask) {
393 dev_warn(mcasp->dev, "Receive buffer overflow\n");
394 handled_mask |= ROVRN;
395
396 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
dae35d1f
TI		 397 if (substream)
398 snd_pcm_stop_xrun(substream);
a7a3324a
MLC		 399 }
400
401 if (!handled_mask)
402 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
403 stat);
404
405 if (stat & XRERR)
406 handled_mask |= XRERR;
407
408 /* Ack the handled event only */
409 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
410
411 return IRQ_RETVAL(handled_mask);
412}
413
5a1b8a80
PU		 414static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
415{
416 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
417 irqreturn_t ret = IRQ_NONE;
418
419 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
420 ret = davinci_mcasp_tx_irq_handler(irq, data);
421
422 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
423 ret |= davinci_mcasp_rx_irq_handler(irq, data);
424
425 return ret;
426}
427
b67f4487
C		 428static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
429 unsigned int fmt)
430{
70091a3e 431 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 432 int ret = 0;
6dfa9a4e 433 u32 data_delay;
83f12503 434 bool fs_pol_rising;
ffd950f7 435 bool inv_fs = false;
b67f4487 436
4a11ff26
PU		 437 if (!fmt)
438 return 0;
439
1d17a04e 440 pm_runtime_get_sync(mcasp->dev);
5296cf2d 441 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188edc59
PU		 442 case SND_SOC_DAIFMT_DSP_A:
443 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
444 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
188edc59
PU		 445 /* 1st data bit occur one ACLK cycle after the frame sync */
446 data_delay = 1;
447 break;
5296cf2d
DM		 448 case SND_SOC_DAIFMT_DSP_B:
449 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 450 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 452 /* No delay after FS */
453 data_delay = 0;
5296cf2d 454 break;
ffd950f7 455 case SND_SOC_DAIFMT_I2S:
5296cf2d 456 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 457 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 459 /* 1st data bit occur one ACLK cycle after the frame sync */
460 data_delay = 1;
ffd950f7
PU		 461 /* FS need to be inverted */
462 inv_fs = true;
5296cf2d 463 break;
423761e0
PU		 464 case SND_SOC_DAIFMT_LEFT_J:
465 /* configure a full-word SYNC pulse (LRCLK) */
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
467 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
468 /* No delay after FS */
469 data_delay = 0;
470 break;
ffd950f7
PU		 471 default:
472 ret = -EINVAL;
473 goto out;
5296cf2d
DM		 474 }
475
6dfa9a4e
PU		 476 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
477 FSXDLY(3));
478 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
479 FSRDLY(3));
480
b67f4487
C		 481 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
482 case SND_SOC_DAIFMT_CBS_CFS:
483 /* codec is clock and frame slave */
f68205a7
PU		 484 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
485 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 486
f68205a7
PU		 487 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
488 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 489
ca3d9433
PU		 490 /* BCLK */
491 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
492 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
493 /* Frame Sync */
494 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
495 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
496
ab8b14b6 497 mcasp->bclk_master = 1;
b67f4487 498 break;
226e2f1b
PU		 499 case SND_SOC_DAIFMT_CBS_CFM:
500 /* codec is clock slave and frame master */
501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
502 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
503
504 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
506
ca3d9433
PU		 507 /* BCLK */
508 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
509 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
510 /* Frame Sync */
511 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
512 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
513
226e2f1b
PU		 514 mcasp->bclk_master = 1;
515 break;
517ee6cf
C		 516 case SND_SOC_DAIFMT_CBM_CFS:
517 /* codec is clock master and frame slave */
f68205a7
PU		 518 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
519 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 520
f68205a7
PU		 521 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
522 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 523
ca3d9433
PU		 524 /* BCLK */
525 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
526 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
527 /* Frame Sync */
528 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
529 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
530
ab8b14b6 531 mcasp->bclk_master = 0;
517ee6cf 532 break;
b67f4487
C		 533 case SND_SOC_DAIFMT_CBM_CFM:
534 /* codec is clock and frame master */
f68205a7
PU		 535 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
536 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 537
f68205a7
PU		 538 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
539 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 540
ca3d9433
PU		 541 /* BCLK */
542 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
543 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
544 /* Frame Sync */
545 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
546 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
547
ab8b14b6 548 mcasp->bclk_master = 0;
b67f4487 549 break;
b67f4487 550 default:
1d17a04e
PU		 551 ret = -EINVAL;
552 goto out;
b67f4487
C		 553 }
554
555 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
556 case SND_SOC_DAIFMT_IB_NF:
f68205a7 557 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 558 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 559 fs_pol_rising = true;
b67f4487 560 break;
b67f4487 561 case SND_SOC_DAIFMT_NB_IF:
f68205a7 562 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 563 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 564 fs_pol_rising = false;
b67f4487 565 break;
b67f4487 566 case SND_SOC_DAIFMT_IB_IF:
f68205a7 567 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 568 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 569 fs_pol_rising = false;
b67f4487 570 break;
b67f4487 571 case SND_SOC_DAIFMT_NB_NF:
f68205a7 572 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
f68205a7 573 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 574 fs_pol_rising = true;
b67f4487 575 break;
b67f4487 576 default:
1d17a04e 577 ret = -EINVAL;
83f12503
PU		 578 goto out;
579 }
580
ffd950f7
PU		 581 if (inv_fs)
582 fs_pol_rising = !fs_pol_rising;
583
83f12503
PU		 584 if (fs_pol_rising) {
585 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
586 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
587 } else {
588 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
589 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487 590 }
4a11ff26
PU		 591
592 mcasp->dai_fmt = fmt;
1d17a04e 593out:
6afda7f5 594 pm_runtime_put(mcasp->dev);
1d17a04e 595 return ret;
b67f4487
C		 596}
597
226e73e2 598static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
8813543e 599 int div, bool explicit)
4ed8c9b7 600{
6afda7f5 601 pm_runtime_get_sync(mcasp->dev);
4ed8c9b7 602 switch (div_id) {
20d4b107 603 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
f68205a7 604 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 605 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 606 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 607 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
608 break;
609
20d4b107 610 case MCASP_CLKDIV_BCLK: /* BCLK divider */
f68205a7 611 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 612 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 613 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7 614 ACLKRDIV(div - 1), ACLKRDIV_MASK);
8813543e
JS		 615 if (explicit)
616 mcasp->bclk_div = div;
4ed8c9b7
DM		 617 break;
618
20d4b107
PU		 619 case MCASP_CLKDIV_BCLK_FS_RATIO:
620 /*
14a998be
JS		 621 * BCLK/LRCLK ratio descries how many bit-clock cycles
622 * fit into one frame. The clock ratio is given for a
623 * full period of data (for I2S format both left and
624 * right channels), so it has to be divided by number
625 * of tdm-slots (for I2S - divided by 2).
626 * Instead of storing this ratio, we calculate a new
627 * tdm_slot width by dividing the the ratio by the
628 * number of configured tdm slots.
629 */
630 mcasp->slot_width = div / mcasp->tdm_slots;
631 if (div % mcasp->tdm_slots)
632 dev_warn(mcasp->dev,
633 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
634 __func__, div, mcasp->tdm_slots);
1b3bc060
DM		 635 break;
636
4ed8c9b7
DM		 637 default:
638 return -EINVAL;
639 }
640
6afda7f5 641 pm_runtime_put(mcasp->dev);
4ed8c9b7
DM		 642 return 0;
643}
644
8813543e
JS		 645static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
646 int div)
647{
226e73e2
PU		 648 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
649
650 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
8813543e
JS		 651}
652
5b66aa2d
DM		 653static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
654 unsigned int freq, int dir)
655{
70091a3e 656 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d 657
6afda7f5 658 pm_runtime_get_sync(mcasp->dev);
5b66aa2d 659 if (dir == SND_SOC_CLOCK_OUT) {
f68205a7
PU		 660 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
661 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
ca3d9433 662 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
5b66aa2d 663 } else {
f68205a7
PU		 664 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
665 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
ca3d9433 666 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
5b66aa2d
DM		 667 }
668
ab8b14b6
JS		 669 mcasp->sysclk_freq = freq;
670
6afda7f5 671 pm_runtime_put(mcasp->dev);
5b66aa2d
DM		 672 return 0;
673}
674
dd55ff83
JS		 675/* All serializers must have equal number of channels */
676static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
677 int serializers)
678{
679 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
680 unsigned int *list = (unsigned int *) cl->list;
681 int slots = mcasp->tdm_slots;
682 int i, count = 0;
683
684 if (mcasp->tdm_mask[stream])
685 slots = hweight32(mcasp->tdm_mask[stream]);
686
e4798d26 687 for (i = 1; i <= slots; i++)
dd55ff83
JS		 688 list[count++] = i;
689
690 for (i = 2; i <= serializers; i++)
691 list[count++] = i*slots;
692
693 cl->count = count;
694
695 return 0;
696}
697
698static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
699{
700 int rx_serializers = 0, tx_serializers = 0, ret, i;
701
702 for (i = 0; i < mcasp->num_serializer; i++)
703 if (mcasp->serial_dir[i] == TX_MODE)
704 tx_serializers++;
705 else if (mcasp->serial_dir[i] == RX_MODE)
706 rx_serializers++;
707
708 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
709 tx_serializers);
710 if (ret)
711 return ret;
712
713 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
714 rx_serializers);
715
716 return ret;
717}
718
719
720static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
721 unsigned int tx_mask,
722 unsigned int rx_mask,
723 int slots, int slot_width)
724{
725 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
726
727 dev_dbg(mcasp->dev,
728 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
729 __func__, tx_mask, rx_mask, slots, slot_width);
730
731 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
732 dev_err(mcasp->dev,
733 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
734 tx_mask, rx_mask, slots);
735 return -EINVAL;
736 }
737
738 if (slot_width &&
739 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
740 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
741 __func__, slot_width);
742 return -EINVAL;
743 }
744
745 mcasp->tdm_slots = slots;
1bdd5932
AD		 746 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
747 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
dd55ff83
JS		 748 mcasp->slot_width = slot_width;
749
750 return davinci_mcasp_set_ch_constraints(mcasp);
751}
752
70091a3e 753static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
14a998be 754 int sample_width)
b67f4487 755{
ba764b3d 756 u32 fmt;
14a998be
JS		 757 u32 tx_rotate = (sample_width / 4) & 0x7;
758 u32 mask = (1ULL << sample_width) - 1;
759 u32 slot_width = sample_width;
760
fe0a29e1
PU		 761 /*
762 * For captured data we should not rotate, inversion and masking is
763 * enoguh to get the data to the right position:
764 * Format data from bus after reverse (XRBUF)
765 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
766 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
767 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
768 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
769 */
770 u32 rx_rotate = 0;
b67f4487 771
1b3bc060 772 /*
14a998be
JS		 773 * Setting the tdm slot width either with set_clkdiv() or
774 * set_tdm_slot() allows us to for example send 32 bits per
775 * channel to the codec, while only 16 of them carry audio
776 * payload.
1b3bc060 777 */
14a998be 778 if (mcasp->slot_width) {
d742b925 779 /*
14a998be
JS		 780 * When we have more bclk then it is needed for the
781 * data, we need to use the rotation to move the
782 * received samples to have correct alignment.
d742b925 783 */
14a998be
JS		 784 slot_width = mcasp->slot_width;
785 rx_rotate = (slot_width - sample_width) / 4;
d742b925 786 }
1b3bc060 787
ba764b3d 788 /* mapping of the XSSZ bit-field as described in the datasheet */
14a998be 789 fmt = (slot_width >> 1) - 1;
b67f4487 790
70091a3e 791 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 792 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
793 RXSSZ(0x0F));
794 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
795 TXSSZ(0x0F));
796 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
797 TXROT(7));
798 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
799 RXROT(7));
800 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 801 }
802
f68205a7 803 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 804
b67f4487
C		 805 return 0;
806}
807
662ffae9 808static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
dd093a0f 809 int period_words, int channels)
b67f4487 810{
5f04c603 811 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
b67f4487 812 int i;
6a99fb5f
C		 813 u8 tx_ser = 0;
814 u8 rx_ser = 0;
70091a3e 815 u8 slots = mcasp->tdm_slots;
2952b27e 816 u8 max_active_serializers = (channels + slots - 1) / slots;
72383192 817 int active_serializers, numevt;
487dce88 818 u32 reg;
b67f4487 819 /* Default configuration */
40448e5e 820 if (mcasp->version < MCASP_VERSION_3)
f68205a7 821 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487
C		 822
823 /* All PINS as McASP */
f68205a7 824 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
b67f4487
C		 825
826 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 827 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
828 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487 829 } else {
f68205a7
PU		 830 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
831 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b67f4487
C		 832 }
833
70091a3e 834 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 835 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
836 mcasp->serial_dir[i]);
70091a3e 837 if (mcasp->serial_dir[i] == TX_MODE &&
2952b27e 838 tx_ser < max_active_serializers) {
19db62ea 839 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
bc184549 840 mcasp->dismod, DISMOD_MASK);
ca3d9433 841 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f 842 tx_ser++;
70091a3e 843 } else if (mcasp->serial_dir[i] == RX_MODE &&
2952b27e 844 rx_ser < max_active_serializers) {
ca3d9433 845 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f 846 rx_ser++;
096a8f83 847 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
f68205a7
PU		 848 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
849 SRMOD_INACTIVE, SRMOD_MASK);
ca3d9433
PU		 850 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
851 } else if (mcasp->serial_dir[i] == TX_MODE) {
852 /* Unused TX pins, clear PDIR */
bc184549
PU		 853 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
854 mcasp->dismod, DISMOD_MASK);
ca3d9433 855 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
6a99fb5f
C		 856 }
857 }
858
0bf0e8ae
PU		 859 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
860 active_serializers = tx_ser;
861 numevt = mcasp->txnumevt;
862 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
863 } else {
864 active_serializers = rx_ser;
865 numevt = mcasp->rxnumevt;
866 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
867 }
ecf327c7 868
0bf0e8ae 869 if (active_serializers < max_active_serializers) {
70091a3e 870 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0bf0e8ae
PU		 871 "enabled in mcasp (%d)\n", channels,
872 active_serializers * slots);
ecf327c7
DM		 873 return -EINVAL;
874 }
875
0bf0e8ae 876 /* AFIFO is not in use */
5f04c603
PU		 877 if (!numevt) {
878 /* Configure the burst size for platform drivers */
33445643
PU		 879 if (active_serializers > 1) {
880 /*
881 * If more than one serializers are in use we have one
882 * DMA request to provide data for all serializers.
883 * For example if three serializers are enabled the DMA
884 * need to transfer three words per DMA request.
885 */
33445643
PU		 886 dma_data->maxburst = active_serializers;
887 } else {
33445643
PU		 888 dma_data->maxburst = 0;
889 }
0bf0e8ae 890 return 0;
5f04c603 891 }
6a99fb5f 892
dd093a0f
PU		 893 if (period_words % active_serializers) {
894 dev_err(mcasp->dev, "Invalid combination of period words and "
895 "active serializers: %d, %d\n", period_words,
896 active_serializers);
897 return -EINVAL;
898 }
899
900 /*
901 * Calculate the optimal AFIFO depth for platform side:
902 * The number of words for numevt need to be in steps of active
903 * serializers.
904 */
72383192
PU		 905 numevt = (numevt / active_serializers) * active_serializers;
906
dd093a0f
PU		 907 while (period_words % numevt && numevt > 0)
908 numevt -= active_serializers;
909 if (numevt <= 0)
0bf0e8ae 910 numevt = active_serializers;
487dce88 911
0bf0e8ae
PU		 912 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
913 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
2952b27e 914
5f04c603 915 /* Configure the burst size for platform drivers */
33445643
PU		 916 if (numevt == 1)
917 numevt = 0;
5f04c603
PU		 918 dma_data->maxburst = numevt;
919
2952b27e 920 return 0;
b67f4487
C		 921}
922
18a4f557
MLC		 923static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
924 int channels)
b67f4487
C		 925{
926 int i, active_slots;
18a4f557
MLC		 927 int total_slots;
928 int active_serializers;
b67f4487 929 u32 mask = 0;
cbc7956c 930 u32 busel = 0;
b67f4487 931
18a4f557
MLC		 932 total_slots = mcasp->tdm_slots;
933
934 /*
935 * If more than one serializer is needed, then use them with
dd55ff83
JS		 936 * all the specified tdm_slots. Otherwise, one serializer can
937 * cope with the transaction using just as many slots as there
938 * are channels in the stream.
18a4f557 939 */
dd55ff83
JS		 940 if (mcasp->tdm_mask[stream]) {
941 active_slots = hweight32(mcasp->tdm_mask[stream]);
942 active_serializers = (channels + active_slots - 1) /
943 active_slots;
944 if (active_serializers == 1) {
945 active_slots = channels;
946 for (i = 0; i < total_slots; i++) {
947 if ((1 << i) & mcasp->tdm_mask[stream]) {
948 mask |= (1 << i);
949 if (--active_slots <= 0)
950 break;
951 }
952 }
953 }
954 } else {
955 active_serializers = (channels + total_slots - 1) / total_slots;
956 if (active_serializers == 1)
957 active_slots = channels;
958 else
959 active_slots = total_slots;
b67f4487 960
dd55ff83
JS		 961 for (i = 0; i < active_slots; i++)
962 mask |= (1 << i);
963 }
f68205a7 964 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 965
cbc7956c
PU		 966 if (!mcasp->dat_port)
967 busel = TXSEL;
968
dd55ff83
JS		 969 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
970 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
971 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
972 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
973 FSXMOD(total_slots), FSXMOD(0x1FF));
974 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
975 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
976 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
977 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
978 FSRMOD(total_slots), FSRMOD(0x1FF));
0ad7d3a0
PU		 979 /*
980 * If McASP is set to be TX/RX synchronous and the playback is
981 * not running already we need to configure the TX slots in
982 * order to have correct FSX on the bus
983 */
984 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
985 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
986 FSXMOD(total_slots), FSXMOD(0x1FF));
dd55ff83 987 }
2c56c4c2
PU		 988
989 return 0;
b67f4487
C		 990}
991
992/* S/PDIF */
6479285d
DM		 993static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
994 unsigned int rate)
b67f4487 995{
6479285d
DM		 996 u32 cs_value = 0;
997 u8 *cs_bytes = (u8*) &cs_value;
998
b67f4487
C		 999 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1000 and LSB first */
f68205a7 1001 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 1002
1003 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 1004 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 1005
1006 /* Set the TX tdm : for all the slots */
f68205a7 1007 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 1008
1009 /* Set the TX clock controls : div = 1 and internal */
f68205a7 1010 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 1011
f68205a7 1012 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 1013
1014 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 1015 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 1016
1017 /* Enable the DIT */
f68205a7 1018 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2 1019
6479285d
DM		 1020 /* Set S/PDIF channel status bits */
1021 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1022 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1023
1024 switch (rate) {
1025 case 22050:
1026 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1027 break;
1028 case 24000:
1029 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1030 break;
1031 case 32000:
1032 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1033 break;
1034 case 44100:
1035 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1036 break;
1037 case 48000:
1038 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1039 break;
1040 case 88200:
1041 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1042 break;
1043 case 96000:
1044 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1045 break;
1046 case 176400:
1047 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1048 break;
1049 case 192000:
1050 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1051 break;
1052 default:
1053 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1054 return -EINVAL;
1055 }
1056
1057 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1058 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1059
2c56c4c2 1060 return 0;
b67f4487
C		 1061}
1062
a75a053f 1063static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
3e9bee11 1064 unsigned int bclk_freq, bool set)
a75a053f 1065{
3e9bee11 1066 int error_ppm;
ddecd149
PU		 1067 unsigned int sysclk_freq = mcasp->sysclk_freq;
1068 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1069 int div = sysclk_freq / bclk_freq;
1070 int rem = sysclk_freq % bclk_freq;
1071 int aux_div = 1;
1072
1073 if (div > (ACLKXDIV_MASK + 1)) {
1074 if (reg & AHCLKXE) {
1075 aux_div = div / (ACLKXDIV_MASK + 1);
1076 if (div % (ACLKXDIV_MASK + 1))
1077 aux_div++;
1078
1079 sysclk_freq /= aux_div;
1080 div = sysclk_freq / bclk_freq;
1081 rem = sysclk_freq % bclk_freq;
1082 } else if (set) {
1083 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1084 sysclk_freq);
1085 }
1086 }
a75a053f
JS		 1087
1088 if (rem != 0) {
1089 if (div == 0 ||
ddecd149
PU		 1090 ((sysclk_freq / div) - bclk_freq) >
1091 (bclk_freq - (sysclk_freq / (div+1)))) {
a75a053f
JS		 1092 div++;
1093 rem = rem - bclk_freq;
1094 }
1095 }
3e9bee11
PU		 1096 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1097 (int)bclk_freq)) / div - 1000000;
a75a053f 1098
3e9bee11
PU		 1099 if (set) {
1100 if (error_ppm)
1101 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1102 error_ppm);
1103
1104 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
ddecd149
PU		 1105 if (reg & AHCLKXE)
1106 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1107 aux_div, 0);
3e9bee11 1108 }
a75a053f 1109
3e9bee11 1110 return error_ppm;
a75a053f
JS		 1111}
1112
5fcb457a
PU		 1113static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1114{
1115 if (!mcasp->txnumevt)
1116 return 0;
1117
1118 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1119}
1120
1121static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1122{
1123 if (!mcasp->rxnumevt)
1124 return 0;
1125
1126 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1127}
1128
1129static snd_pcm_sframes_t davinci_mcasp_delay(
1130 struct snd_pcm_substream *substream,
1131 struct snd_soc_dai *cpu_dai)
1132{
1133 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1134 u32 fifo_use;
1135
1136 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1137 fifo_use = davinci_mcasp_tx_delay(mcasp);
1138 else
1139 fifo_use = davinci_mcasp_rx_delay(mcasp);
1140
1141 /*
1142 * Divide the used locations with the channel count to get the
1143 * FIFO usage in samples (don't care about partial samples in the
1144 * buffer).
1145 */
1146 return fifo_use / substream->runtime->channels;
1147}
1148
b67f4487
C		 1149static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1150 struct snd_pcm_hw_params *params,
1151 struct snd_soc_dai *cpu_dai)
1152{
70091a3e 1153 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 1154 int word_length;
a7e46bd9 1155 int channels = params_channels(params);
dd093a0f 1156 int period_size = params_period_size(params);
2c56c4c2 1157 int ret;
ab8b14b6 1158
4a11ff26
PU		 1159 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1160 if (ret)
1161 return ret;
1162
8267525c
DM		 1163 /*
1164 * If mcasp is BCLK master, and a BCLK divider was not provided by
1165 * the machine driver, we need to calculate the ratio.
1166 */
1167 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1f114f77 1168 int slots = mcasp->tdm_slots;
a75a053f
JS		 1169 int rate = params_rate(params);
1170 int sbits = params_width(params);
a75a053f 1171
dd55ff83
JS		 1172 if (mcasp->slot_width)
1173 sbits = mcasp->slot_width;
1174
3e9bee11 1175 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
ab8b14b6
JS		 1176 }
1177
dd093a0f
PU		 1178 ret = mcasp_common_hw_param(mcasp, substream->stream,
1179 period_size * channels, channels);
0f7d9a63
PU		 1180 if (ret)
1181 return ret;
1182
70091a3e 1183 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
6479285d 1184 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
b67f4487 1185 else
18a4f557
MLC		 1186 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1187 channels);
2c56c4c2
PU		 1188
1189 if (ret)
1190 return ret;
b67f4487
C		 1191
1192 switch (params_format(params)) {
0a9d1385 1193 case SNDRV_PCM_FORMAT_U8:
b67f4487 1194 case SNDRV_PCM_FORMAT_S8:
ba764b3d 1195 word_length = 8;
b67f4487
C		 1196 break;
1197
0a9d1385 1198 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487 1199 case SNDRV_PCM_FORMAT_S16_LE:
ba764b3d 1200 word_length = 16;
b67f4487
C		 1201 break;
1202
21eb24d8
DM		 1203 case SNDRV_PCM_FORMAT_U24_3LE:
1204 case SNDRV_PCM_FORMAT_S24_3LE:
ba764b3d 1205 word_length = 24;
21eb24d8
DM		 1206 break;
1207
6b7fa011
DM		 1208 case SNDRV_PCM_FORMAT_U24_LE:
1209 case SNDRV_PCM_FORMAT_S24_LE:
182bef86
PU		 1210 word_length = 24;
1211 break;
1212
0a9d1385 1213 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487 1214 case SNDRV_PCM_FORMAT_S32_LE:
ba764b3d 1215 word_length = 32;
b67f4487
C		 1216 break;
1217
1218 default:
1219 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1220 return -EINVAL;
1221 }
6a99fb5f 1222
70091a3e 1223 davinci_config_channel_size(mcasp, word_length);
b67f4487 1224
11277833
PU		 1225 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1226 mcasp->channels = channels;
1227
b67f4487
C		 1228 return 0;
1229}
1230
1231static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1232 int cmd, struct snd_soc_dai *cpu_dai)
1233{
70091a3e 1234 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 1235 int ret = 0;
1236
1237 switch (cmd) {
b67f4487 1238 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 1239 case SNDRV_PCM_TRIGGER_START:
1240 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 1241 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 1242 break;
b67f4487 1243 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 1244 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 1245 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 1246 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 1247 break;
1248
1249 default:
1250 ret = -EINVAL;
1251 }
1252
1253 return ret;
1254}
1255
a75a053f
JS		 1256static const unsigned int davinci_mcasp_dai_rates[] = {
1257 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1258 88200, 96000, 176400, 192000,
1259};
1260
1261#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1262
1263static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1264 struct snd_pcm_hw_rule *rule)
1265{
1266 struct davinci_mcasp_ruledata *rd = rule->private;
1267 struct snd_interval *ri =
1268 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1269 int sbits = params_width(params);
1f114f77 1270 int slots = rd->mcasp->tdm_slots;
518f6bab
JS		 1271 struct snd_interval range;
1272 int i;
a75a053f 1273
dd55ff83
JS		 1274 if (rd->mcasp->slot_width)
1275 sbits = rd->mcasp->slot_width;
1276
518f6bab
JS		 1277 snd_interval_any(&range);
1278 range.empty = 1;
a75a053f
JS		 1279
1280 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
518f6bab 1281 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1f114f77 1282 uint bclk_freq = sbits*slots*
a75a053f
JS		 1283 davinci_mcasp_dai_rates[i];
1284 int ppm;
1285
3e9bee11
PU		 1286 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1287 false);
518f6bab
JS		 1288 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1289 if (range.empty) {
1290 range.min = davinci_mcasp_dai_rates[i];
1291 range.empty = 0;
1292 }
1293 range.max = davinci_mcasp_dai_rates[i];
1294 }
a75a053f
JS		 1295 }
1296 }
518f6bab 1297
a75a053f 1298 dev_dbg(rd->mcasp->dev,
518f6bab
JS		 1299 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1300 ri->min, ri->max, range.min, range.max, sbits, slots);
a75a053f 1301
518f6bab
JS		 1302 return snd_interval_refine(hw_param_interval(params, rule->var),
1303 &range);
a75a053f
JS		 1304}
1305
1306static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1307 struct snd_pcm_hw_rule *rule)
1308{
1309 struct davinci_mcasp_ruledata *rd = rule->private;
1310 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1311 struct snd_mask nfmt;
1312 int rate = params_rate(params);
1f114f77 1313 int slots = rd->mcasp->tdm_slots;
a75a053f
JS		 1314 int i, count = 0;
1315
1316 snd_mask_none(&nfmt);
1317
9be072a6 1318 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
a75a053f 1319 if (snd_mask_test(fmt, i)) {
dd55ff83 1320 uint sbits = snd_pcm_format_width(i);
a75a053f
JS		 1321 int ppm;
1322
dd55ff83
JS		 1323 if (rd->mcasp->slot_width)
1324 sbits = rd->mcasp->slot_width;
1325
3e9bee11
PU		 1326 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1327 sbits * slots * rate,
1328 false);
a75a053f
JS		 1329 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1330 snd_mask_set(&nfmt, i);
1331 count++;
1332 }
1333 }
1334 }
1335 dev_dbg(rd->mcasp->dev,
1f114f77
JS		 1336 "%d possible sample format for %d Hz and %d tdm slots\n",
1337 count, rate, slots);
a75a053f
JS		 1338
1339 return snd_mask_refine(fmt, &nfmt);
1340}
1341
d43c17da
PU		 1342static int davinci_mcasp_hw_rule_min_periodsize(
1343 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1344{
1345 struct snd_interval *period_size = hw_param_interval(params,
1346 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1347 struct snd_interval frames;
1348
1349 snd_interval_any(&frames);
1350 frames.min = 64;
1351 frames.integer = 1;
1352
1353 return snd_interval_refine(period_size, &frames);
1354}
1355
11277833
PU		 1356static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1357 struct snd_soc_dai *cpu_dai)
1358{
1359 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
4cd9db08
PU		 1360 struct davinci_mcasp_ruledata *ruledata =
1361 &mcasp->ruledata[substream->stream];
11277833
PU		 1362 u32 max_channels = 0;
1363 int i, dir;
dd55ff83
JS		 1364 int tdm_slots = mcasp->tdm_slots;
1365
19357366
PU		 1366 /* Do not allow more then one stream per direction */
1367 if (mcasp->substreams[substream->stream])
1368 return -EBUSY;
11277833 1369
a7a3324a
MLC		 1370 mcasp->substreams[substream->stream] = substream;
1371
19357366
PU		 1372 if (mcasp->tdm_mask[substream->stream])
1373 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1374
11277833
PU		 1375 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1376 return 0;
1377
1378 /*
1379 * Limit the maximum allowed channels for the first stream:
1380 * number of serializers for the direction * tdm slots per serializer
1381 */
1382 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1383 dir = TX_MODE;
1384 else
1385 dir = RX_MODE;
1386
1387 for (i = 0; i < mcasp->num_serializer; i++) {
1388 if (mcasp->serial_dir[i] == dir)
1389 max_channels++;
1390 }
4cd9db08 1391 ruledata->serializers = max_channels;
dd55ff83 1392 max_channels *= tdm_slots;
11277833
PU		 1393 /*
1394 * If the already active stream has less channels than the calculated
1395 * limnit based on the seirializers * tdm_slots, we need to use that as
1396 * a constraint for the second stream.
1397 * Otherwise (first stream or less allowed channels) we use the
1398 * calculated constraint.
1399 */
1400 if (mcasp->channels && mcasp->channels < max_channels)
1401 max_channels = mcasp->channels;
dd55ff83
JS		 1402 /*
1403 * But we can always allow channels upto the amount of
1404 * the available tdm_slots.
1405 */
1406 if (max_channels < tdm_slots)
1407 max_channels = tdm_slots;
11277833
PU		 1408
1409 snd_pcm_hw_constraint_minmax(substream->runtime,
1410 SNDRV_PCM_HW_PARAM_CHANNELS,
e4798d26 1411 0, max_channels);
a75a053f 1412
dd55ff83
JS		 1413 snd_pcm_hw_constraint_list(substream->runtime,
1414 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1415 &mcasp->chconstr[substream->stream]);
1416
1417 if (mcasp->slot_width)
1418 snd_pcm_hw_constraint_minmax(substream->runtime,
1419 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1420 8, mcasp->slot_width);
5935a056 1421
a75a053f
JS		 1422 /*
1423 * If we rely on implicit BCLK divider setting we should
1424 * set constraints based on what we can provide.
1425 */
1426 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1427 int ret;
1428
4cd9db08 1429 ruledata->mcasp = mcasp;
a75a053f
JS		 1430
1431 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1432 SNDRV_PCM_HW_PARAM_RATE,
1433 davinci_mcasp_hw_rule_rate,
4cd9db08 1434 ruledata,
1f114f77 1435 SNDRV_PCM_HW_PARAM_FORMAT, -1);
a75a053f
JS		 1436 if (ret)
1437 return ret;
1438 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1439 SNDRV_PCM_HW_PARAM_FORMAT,
1440 davinci_mcasp_hw_rule_format,
4cd9db08 1441 ruledata,
1f114f77 1442 SNDRV_PCM_HW_PARAM_RATE, -1);
a75a053f
JS		 1443 if (ret)
1444 return ret;
1445 }
1446
d43c17da
PU		 1447 snd_pcm_hw_rule_add(substream->runtime, 0,
1448 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1449 davinci_mcasp_hw_rule_min_periodsize, NULL,
1450 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1451
11277833
PU		 1452 return 0;
1453}
1454
1455static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1456 struct snd_soc_dai *cpu_dai)
1457{
1458 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1459
a7a3324a
MLC		 1460 mcasp->substreams[substream->stream] = NULL;
1461
11277833
PU		 1462 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1463 return;
1464
1465 if (!cpu_dai->active)
1466 mcasp->channels = 0;
1467}
1468
85e7652d 1469static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
11277833
PU		 1470 .startup = davinci_mcasp_startup,
1471 .shutdown = davinci_mcasp_shutdown,
b67f4487 1472 .trigger = davinci_mcasp_trigger,
5fcb457a 1473 .delay = davinci_mcasp_delay,
b67f4487
C		 1474 .hw_params = davinci_mcasp_hw_params,
1475 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 1476 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 1477 .set_sysclk = davinci_mcasp_set_sysclk,
dd55ff83 1478 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
b67f4487
C		 1479};
1480
d5902f69
PU		 1481static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1482{
1483 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1484
9759e7ef
PU		 1485 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1486 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
d5902f69
PU		 1487
1488 return 0;
1489}
1490
ed29cd5e
PU		 1491#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1492
0a9d1385
BG		 1493#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1494 SNDRV_PCM_FMTBIT_U8 | \
1495 SNDRV_PCM_FMTBIT_S16_LE | \
1496 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 1497 SNDRV_PCM_FMTBIT_S24_LE | \
1498 SNDRV_PCM_FMTBIT_U24_LE | \
1499 SNDRV_PCM_FMTBIT_S24_3LE | \
1500 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 1501 SNDRV_PCM_FMTBIT_S32_LE | \
1502 SNDRV_PCM_FMTBIT_U32_LE)
1503
f0fba2ad 1504static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 1505 {
f0fba2ad 1506 .name = "davinci-mcasp.0",
d5902f69 1507 .probe = davinci_mcasp_dai_probe,
b67f4487 1508 .playback = {
e4798d26 1509 .channels_min = 1,
2952b27e 1510 .channels_max = 32 * 16,
b67f4487 1511 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1512 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1513 },
1514 .capture = {
e4798d26 1515 .channels_min = 1,
2952b27e 1516 .channels_max = 32 * 16,
b67f4487 1517 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1518 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1519 },
1520 .ops = &davinci_mcasp_dai_ops,
1521
d75249f5 1522 .symmetric_samplebits = 1,
295c3405 1523 .symmetric_rates = 1,
b67f4487
C		 1524 },
1525 {
58e48d97 1526 .name = "davinci-mcasp.1",
d5902f69 1527 .probe = davinci_mcasp_dai_probe,
b67f4487
C		 1528 .playback = {
1529 .channels_min = 1,
1530 .channels_max = 384,
1531 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1532 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1533 },
1534 .ops = &davinci_mcasp_dai_ops,
1535 },
1536
1537};
b67f4487 1538
eeef0eda
KM		 1539static const struct snd_soc_component_driver davinci_mcasp_component = {
1540 .name = "davinci-mcasp",
1541};
1542
256ba181 1543/* Some HW specific values and defaults. The rest is filled in from DT. */
d1debafc 1544static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
256ba181
JS		 1545 .tx_dma_offset = 0x400,
1546 .rx_dma_offset = 0x400,
256ba181
JS		 1547 .version = MCASP_VERSION_1,
1548};
1549
d1debafc 1550static struct davinci_mcasp_pdata da830_mcasp_pdata = {
256ba181
JS		 1551 .tx_dma_offset = 0x2000,
1552 .rx_dma_offset = 0x2000,
256ba181
JS		 1553 .version = MCASP_VERSION_2,
1554};
1555
d1debafc 1556static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
256ba181
JS		 1557 .tx_dma_offset = 0,
1558 .rx_dma_offset = 0,
256ba181
JS		 1559 .version = MCASP_VERSION_3,
1560};
1561
d1debafc 1562static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
9ac0013c
PU		 1563 /* The CFG port offset will be calculated if it is needed */
1564 .tx_dma_offset = 0,
1565 .rx_dma_offset = 0,
453c4990
PU		 1566 .version = MCASP_VERSION_4,
1567};
1568
3e3b8c34
HG		 1569static const struct of_device_id mcasp_dt_ids[] = {
1570 {
1571 .compatible = "ti,dm646x-mcasp-audio",
256ba181 1572 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 1573 },
1574 {
1575 .compatible = "ti,da830-mcasp-audio",
256ba181 1576 .data = &da830_mcasp_pdata,
3e3b8c34 1577 },
e5ec69da 1578 {
3af9e031 1579 .compatible = "ti,am33xx-mcasp-audio",
b14899da 1580 .data = &am33xx_mcasp_pdata,
e5ec69da 1581 },
453c4990
PU		 1582 {
1583 .compatible = "ti,dra7-mcasp-audio",
1584 .data = &dra7_mcasp_pdata,
1585 },
3e3b8c34
HG		 1586 { /* sentinel */ }
1587};
1588MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1589
ae726e93
PU		 1590static int mcasp_reparent_fck(struct platform_device *pdev)
1591{
1592 struct device_node *node = pdev->dev.of_node;
1593 struct clk *gfclk, *parent_clk;
1594 const char *parent_name;
1595 int ret;
1596
1597 if (!node)
1598 return 0;
1599
1600 parent_name = of_get_property(node, "fck_parent", NULL);
1601 if (!parent_name)
1602 return 0;
1603
c670254f
PU		 1604 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1605
ae726e93
PU		 1606 gfclk = clk_get(&pdev->dev, "fck");
1607 if (IS_ERR(gfclk)) {
1608 dev_err(&pdev->dev, "failed to get fck\n");
1609 return PTR_ERR(gfclk);
1610 }
1611
1612 parent_clk = clk_get(NULL, parent_name);
1613 if (IS_ERR(parent_clk)) {
1614 dev_err(&pdev->dev, "failed to get parent clock\n");
1615 ret = PTR_ERR(parent_clk);
1616 goto err1;
1617 }
1618
1619 ret = clk_set_parent(gfclk, parent_clk);
1620 if (ret) {
1621 dev_err(&pdev->dev, "failed to reparent fck\n");
1622 goto err2;
1623 }
1624
1625err2:
1626 clk_put(parent_clk);
1627err1:
1628 clk_put(gfclk);
1629 return ret;
1630}
1631
d1debafc 1632static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
3e3b8c34
HG		 1633 struct platform_device *pdev)
1634{
1635 struct device_node *np = pdev->dev.of_node;
d1debafc 1636 struct davinci_mcasp_pdata *pdata = NULL;
3e3b8c34 1637 const struct of_device_id *match =
ea421eb1 1638 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 1639 struct of_phandle_args dma_spec;
3e3b8c34
HG		 1640
1641 const u32 *of_serial_dir32;
3e3b8c34
HG		 1642 u32 val;
1643 int i, ret = 0;
1644
1645 if (pdev->dev.platform_data) {
1646 pdata = pdev->dev.platform_data;
bc184549 1647 pdata->dismod = DISMOD_LOW;
3e3b8c34
HG		 1648 return pdata;
1649 } else if (match) {
272ee030
PU		 1650 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1651 GFP_KERNEL);
1652 if (!pdata) {
272ee030
PU		 1653 ret = -ENOMEM;
1654 return pdata;
1655 }
3e3b8c34
HG		 1656 } else {
1657 /* control shouldn't reach here. something is wrong */
1658 ret = -EINVAL;
1659 goto nodata;
1660 }
1661
3e3b8c34
HG		 1662 ret = of_property_read_u32(np, "op-mode", &val);
1663 if (ret >= 0)
1664 pdata->op_mode = val;
1665
1666 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 1667 if (ret >= 0) {
1668 if (val < 2 || val > 32) {
1669 dev_err(&pdev->dev,
1670 "tdm-slots must be in rage [2-32]\n");
1671 ret = -EINVAL;
1672 goto nodata;
1673 }
1674
3e3b8c34 1675 pdata->tdm_slots = val;
2952b27e 1676 }
3e3b8c34 1677
3e3b8c34
HG		 1678 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1679 val /= sizeof(u32);
3e3b8c34 1680 if (of_serial_dir32) {
1427e660
PU		 1681 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1682 (sizeof(*of_serial_dir) * val),
1683 GFP_KERNEL);
3e3b8c34
HG		 1684 if (!of_serial_dir) {
1685 ret = -ENOMEM;
1686 goto nodata;
1687 }
1688
1427e660 1689 for (i = 0; i < val; i++)
3e3b8c34
HG		 1690 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1691
1427e660 1692 pdata->num_serializer = val;
3e3b8c34
HG		 1693 pdata->serial_dir = of_serial_dir;
1694 }
1695
4023fe6f
JS		 1696 ret = of_property_match_string(np, "dma-names", "tx");
1697 if (ret < 0)
1698 goto nodata;
1699
1700 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1701 &dma_spec);
1702 if (ret < 0)
1703 goto nodata;
1704
1705 pdata->tx_dma_channel = dma_spec.args[0];
1706
caa1d794
PU		 1707 /* RX is not valid in DIT mode */
1708 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1709 ret = of_property_match_string(np, "dma-names", "rx");
1710 if (ret < 0)
1711 goto nodata;
4023fe6f 1712
caa1d794
PU		 1713 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1714 &dma_spec);
1715 if (ret < 0)
1716 goto nodata;
4023fe6f 1717
caa1d794
PU		 1718 pdata->rx_dma_channel = dma_spec.args[0];
1719 }
4023fe6f 1720
3e3b8c34
HG		 1721 ret = of_property_read_u32(np, "tx-num-evt", &val);
1722 if (ret >= 0)
1723 pdata->txnumevt = val;
1724
1725 ret = of_property_read_u32(np, "rx-num-evt", &val);
1726 if (ret >= 0)
1727 pdata->rxnumevt = val;
1728
1729 ret = of_property_read_u32(np, "sram-size-playback", &val);
1730 if (ret >= 0)
1731 pdata->sram_size_playback = val;
1732
1733 ret = of_property_read_u32(np, "sram-size-capture", &val);
1734 if (ret >= 0)
1735 pdata->sram_size_capture = val;
1736
bc184549
PU		 1737 ret = of_property_read_u32(np, "dismod", &val);
1738 if (ret >= 0) {
1739 if (val == 0 || val == 2 || val == 3) {
1740 pdata->dismod = DISMOD_VAL(val);
1741 } else {
1742 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1743 pdata->dismod = DISMOD_LOW;
1744 }
1745 } else {
1746 pdata->dismod = DISMOD_LOW;
1747 }
1748
3e3b8c34
HG		 1749 return pdata;
1750
1751nodata:
1752 if (ret < 0) {
1753 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1754 ret);
1755 pdata = NULL;
1756 }
1757 return pdata;
1758}
1759
9fbd58cf
JS		 1760enum {
1761 PCM_EDMA,
1762 PCM_SDMA,
1763};
1764static const char *sdma_prefix = "ti,omap";
1765
1766static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1767{
1768 struct dma_chan *chan;
1769 const char *tmp;
1770 int ret = PCM_EDMA;
1771
1772 if (!mcasp->dev->of_node)
1773 return PCM_EDMA;
1774
1775 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1776 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1777 if (IS_ERR(chan)) {
1778 if (PTR_ERR(chan) != -EPROBE_DEFER)
1779 dev_err(mcasp->dev,
1780 "Can't verify DMA configuration (%ld)\n",
1781 PTR_ERR(chan));
1782 return PTR_ERR(chan);
1783 }
befff4fb
TI		 1784 if (WARN_ON(!chan->device || !chan->device->dev))
1785 return -EINVAL;
9fbd58cf
JS		 1786
1787 if (chan->device->dev->of_node)
1788 ret = of_property_read_string(chan->device->dev->of_node,
1789 "compatible", &tmp);
1790 else
1791 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1792
1793 dma_release_channel(chan);
1794 if (ret)
1795 return ret;
1796
1797 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1798 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1799 return PCM_SDMA;
1800
1801 return PCM_EDMA;
1802}
1803
9ac0013c
PU		 1804static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1805{
1806 int i;
1807 u32 offset = 0;
1808
1809 if (pdata->version != MCASP_VERSION_4)
1810 return pdata->tx_dma_offset;
1811
1812 for (i = 0; i < pdata->num_serializer; i++) {
1813 if (pdata->serial_dir[i] == TX_MODE) {
1814 if (!offset) {
1815 offset = DAVINCI_MCASP_TXBUF_REG(i);
1816 } else {
1817 pr_err("%s: Only one serializer allowed!\n",
1818 __func__);
1819 break;
1820 }
1821 }
1822 }
1823
1824 return offset;
1825}
1826
1827static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1828{
1829 int i;
1830 u32 offset = 0;
1831
1832 if (pdata->version != MCASP_VERSION_4)
1833 return pdata->rx_dma_offset;
1834
1835 for (i = 0; i < pdata->num_serializer; i++) {
1836 if (pdata->serial_dir[i] == RX_MODE) {
1837 if (!offset) {
1838 offset = DAVINCI_MCASP_RXBUF_REG(i);
1839 } else {
1840 pr_err("%s: Only one serializer allowed!\n",
1841 __func__);
1842 break;
1843 }
1844 }
1845 }
1846
1847 return offset;
1848}
1849
b67f4487
C		 1850static int davinci_mcasp_probe(struct platform_device *pdev)
1851{
8de131f2 1852 struct snd_dmaengine_dai_dma_data *dma_data;
508a43fd 1853 struct resource *mem, *res, *dat;
d1debafc 1854 struct davinci_mcasp_pdata *pdata;
70091a3e 1855 struct davinci_mcasp *mcasp;
a7a3324a 1856 char *irq_name;
9759e7ef 1857 int *dma;
a7a3324a 1858 int irq;
96d31e2b 1859 int ret;
b67f4487 1860
3e3b8c34
HG		 1861 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1862 dev_err(&pdev->dev, "No platform data supplied\n");
1863 return -EINVAL;
1864 }
1865
70091a3e 1866 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 1867 GFP_KERNEL);
70091a3e 1868 if (!mcasp)
b67f4487
C		 1869 return -ENOMEM;
1870
3e3b8c34
HG		 1871 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1872 if (!pdata) {
1873 dev_err(&pdev->dev, "no platform data\n");
1874 return -EINVAL;
1875 }
1876
256ba181 1877 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 1878 if (!mem) {
70091a3e 1879 dev_warn(mcasp->dev,
256ba181
JS		 1880 "\"mpu\" mem resource not found, using index 0\n");
1881 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1882 if (!mem) {
1883 dev_err(&pdev->dev, "no mem resource?\n");
1884 return -ENODEV;
1885 }
b67f4487
C		 1886 }
1887
508a43fd
AL		 1888 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1889 if (IS_ERR(mcasp->base))
1890 return PTR_ERR(mcasp->base);
b67f4487 1891
10884347 1892 pm_runtime_enable(&pdev->dev);
b67f4487 1893
70091a3e 1894 mcasp->op_mode = pdata->op_mode;
1a5923da
PU		 1895 /* sanity check for tdm slots parameter */
1896 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1897 if (pdata->tdm_slots < 2) {
1898 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1899 pdata->tdm_slots);
1900 mcasp->tdm_slots = 2;
1901 } else if (pdata->tdm_slots > 32) {
1902 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1903 pdata->tdm_slots);
1904 mcasp->tdm_slots = 32;
1905 } else {
1906 mcasp->tdm_slots = pdata->tdm_slots;
1907 }
1908 }
1909
70091a3e 1910 mcasp->num_serializer = pdata->num_serializer;
61754717 1911#ifdef CONFIG_PM
a86854d0
KC		 1912 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1913 mcasp->num_serializer, sizeof(u32),
f114ce60 1914 GFP_KERNEL);
4243e045
CJ		 1915 if (!mcasp->context.xrsr_regs) {
1916 ret = -ENOMEM;
1917 goto err;
1918 }
f114ce60 1919#endif
70091a3e
PU		 1920 mcasp->serial_dir = pdata->serial_dir;
1921 mcasp->version = pdata->version;
1922 mcasp->txnumevt = pdata->txnumevt;
1923 mcasp->rxnumevt = pdata->rxnumevt;
bc184549 1924 mcasp->dismod = pdata->dismod;
487dce88 1925
70091a3e 1926 mcasp->dev = &pdev->dev;
b67f4487 1927
5a1b8a80
PU		 1928 irq = platform_get_irq_byname(pdev, "common");
1929 if (irq >= 0) {
ab1fffe3 1930 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
5a1b8a80 1931 dev_name(&pdev->dev));
0c8b794c
AY		 1932 if (!irq_name) {
1933 ret = -ENOMEM;
1934 goto err;
1935 }
5a1b8a80
PU		 1936 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1937 davinci_mcasp_common_irq_handler,
8f511ffb
PU		 1938 IRQF_ONESHOT | IRQF_SHARED,
1939 irq_name, mcasp);
5a1b8a80
PU		 1940 if (ret) {
1941 dev_err(&pdev->dev, "common IRQ request failed\n");
1942 goto err;
1943 }
1944
1945 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1946 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1947 }
1948
a7a3324a
MLC		 1949 irq = platform_get_irq_byname(pdev, "rx");
1950 if (irq >= 0) {
ab1fffe3 1951 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
a7a3324a 1952 dev_name(&pdev->dev));
0c8b794c
AY		 1953 if (!irq_name) {
1954 ret = -ENOMEM;
1955 goto err;
1956 }
a7a3324a
MLC		 1957 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1958 davinci_mcasp_rx_irq_handler,
1959 IRQF_ONESHOT, irq_name, mcasp);
1960 if (ret) {
1961 dev_err(&pdev->dev, "RX IRQ request failed\n");
1962 goto err;
1963 }
1964
1965 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1966 }
1967
1968 irq = platform_get_irq_byname(pdev, "tx");
1969 if (irq >= 0) {
ab1fffe3 1970 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
a7a3324a 1971 dev_name(&pdev->dev));
0c8b794c
AY		 1972 if (!irq_name) {
1973 ret = -ENOMEM;
1974 goto err;
1975 }
a7a3324a
MLC		 1976 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1977 davinci_mcasp_tx_irq_handler,
1978 IRQF_ONESHOT, irq_name, mcasp);
1979 if (ret) {
1980 dev_err(&pdev->dev, "TX IRQ request failed\n");
1981 goto err;
1982 }
1983
1984 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1985 }
1986
256ba181 1987 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 1988 if (dat)
1989 mcasp->dat_port = true;
256ba181 1990
8de131f2 1991 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
cbc7956c 1992 if (dat)
9759e7ef 1993 dma_data->addr = dat->start;
cbc7956c 1994 else
9ac0013c 1995 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
453c4990 1996
9759e7ef 1997 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
b67f4487 1998 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f 1999 if (res)
9759e7ef 2000 *dma = res->start;
4023fe6f 2001 else
9759e7ef 2002 *dma = pdata->tx_dma_channel;
92e2a6f6 2003
8de131f2
PU		 2004 /* dmaengine filter data for DT and non-DT boot */
2005 if (pdev->dev.of_node)
2006 dma_data->filter_data = "tx";
2007 else
9759e7ef 2008 dma_data->filter_data = dma;
8de131f2 2009
caa1d794
PU		 2010 /* RX is not valid in DIT mode */
2011 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
caa1d794 2012 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
caa1d794 2013 if (dat)
9759e7ef 2014 dma_data->addr = dat->start;
caa1d794 2015 else
9ac0013c
PU		 2016 dma_data->addr =
2017 mem->start + davinci_mcasp_rxdma_offset(pdata);
caa1d794 2018
9759e7ef 2019 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
caa1d794
PU		 2020 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2021 if (res)
9759e7ef 2022 *dma = res->start;
caa1d794 2023 else
9759e7ef 2024 *dma = pdata->rx_dma_channel;
caa1d794
PU		 2025
2026 /* dmaengine filter data for DT and non-DT boot */
2027 if (pdev->dev.of_node)
2028 dma_data->filter_data = "rx";
2029 else
9759e7ef 2030 dma_data->filter_data = dma;
caa1d794 2031 }
453c4990 2032
cbc7956c
PU		 2033 if (mcasp->version < MCASP_VERSION_3) {
2034 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
64ebdec3 2035 /* dma_params->dma_addr is pointing to the data port address */
cbc7956c
PU		 2036 mcasp->dat_port = true;
2037 } else {
2038 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2039 }
b67f4487 2040
dd55ff83
JS		 2041 /* Allocate memory for long enough list for all possible
2042 * scenarios. Maximum number tdm slots is 32 and there cannot
2043 * be more serializers than given in the configuration. The
2044 * serializer directions could be taken into account, but it
2045 * would make code much more complex and save only couple of
2046 * bytes.
2047 */
2048 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
a86854d0
KC		 2049 devm_kcalloc(mcasp->dev,
2050 32 + mcasp->num_serializer - 1,
2051 sizeof(unsigned int),
dd55ff83
JS		 2052 GFP_KERNEL);
2053
2054 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
a86854d0
KC		 2055 devm_kcalloc(mcasp->dev,
2056 32 + mcasp->num_serializer - 1,
2057 sizeof(unsigned int),
dd55ff83
JS		 2058 GFP_KERNEL);
2059
2060 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1b8b68b0
CJ		 2061 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2062 ret = -ENOMEM;
2063 goto err;
2064 }
dd55ff83
JS		 2065
2066 ret = davinci_mcasp_set_ch_constraints(mcasp);
5935a056
JS		 2067 if (ret)
2068 goto err;
2069
70091a3e 2070 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 2071
2072 mcasp_reparent_fck(pdev);
2073
b6bb3709
PU		 2074 ret = devm_snd_soc_register_component(&pdev->dev,
2075 &davinci_mcasp_component,
2076 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 2077
2078 if (ret != 0)
b6bb3709 2079 goto err;
f08095a4 2080
9fbd58cf
JS		 2081 ret = davinci_mcasp_get_dma_type(mcasp);
2082 switch (ret) {
2083 case PCM_EDMA:
f2055e14
PU		 2084#if IS_BUILTIN(CONFIG_SND_SOC_TI_EDMA_PCM) || \
2085 (IS_MODULE(CONFIG_SND_SOC_DAVINCI_MCASP) && \
2086 IS_MODULE(CONFIG_SND_SOC_TI_EDMA_PCM))
f3f9cfa8 2087 ret = edma_pcm_platform_register(&pdev->dev);
9fbd58cf
JS		 2088#else
2089 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2090 ret = -EINVAL;
2091 goto err;
f3f9cfa8 2092#endif
9fbd58cf
JS		 2093 break;
2094 case PCM_SDMA:
f2055e14
PU		 2095#if IS_BUILTIN(CONFIG_SND_SOC_TI_SDMA_PCM) || \
2096 (IS_MODULE(CONFIG_SND_SOC_DAVINCI_MCASP) && \
2097 IS_MODULE(CONFIG_SND_SOC_TI_SDMA_PCM))
077a403d 2098 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
9fbd58cf
JS		 2099#else
2100 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2101 ret = -EINVAL;
2102 goto err;
7f28f357 2103#endif
9fbd58cf 2104 break;
d5c6c59a 2105 default:
9fbd58cf
JS		 2106 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2107 case -EPROBE_DEFER:
2108 goto err;
d5c6c59a
PU		 2109 break;
2110 }
2111
2112 if (ret) {
2113 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
b6bb3709 2114 goto err;
f08095a4
HG		 2115 }
2116
b67f4487
C		 2117 return 0;
2118
b6bb3709 2119err:
10884347 2120 pm_runtime_disable(&pdev->dev);
b67f4487
C		 2121 return ret;
2122}
2123
2124static int davinci_mcasp_remove(struct platform_device *pdev)
2125{
10884347 2126 pm_runtime_disable(&pdev->dev);
b67f4487 2127
b67f4487
C		 2128 return 0;
2129}
2130
61754717
PU		 2131#ifdef CONFIG_PM
2132static int davinci_mcasp_runtime_suspend(struct device *dev)
2133{
2134 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2135 struct davinci_mcasp_context *context = &mcasp->context;
2136 u32 reg;
2137 int i;
2138
2139 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2140 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2141
2142 if (mcasp->txnumevt) {
2143 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2144 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2145 }
2146 if (mcasp->rxnumevt) {
2147 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2148 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2149 }
2150
2151 for (i = 0; i < mcasp->num_serializer; i++)
2152 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2153 DAVINCI_MCASP_XRSRCTL_REG(i));
2154
2155 return 0;
2156}
2157
2158static int davinci_mcasp_runtime_resume(struct device *dev)
2159{
2160 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2161 struct davinci_mcasp_context *context = &mcasp->context;
2162 u32 reg;
2163 int i;
2164
2165 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2166 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2167
2168 if (mcasp->txnumevt) {
2169 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2170 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2171 }
2172 if (mcasp->rxnumevt) {
2173 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2174 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2175 }
2176
2177 for (i = 0; i < mcasp->num_serializer; i++)
2178 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2179 context->xrsr_regs[i]);
2180
2181 return 0;
2182}
2183
2184#endif
2185
2186static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2187 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2188 davinci_mcasp_runtime_resume,
2189 NULL)
2190};
2191
b67f4487
C		 2192static struct platform_driver davinci_mcasp_driver = {
2193 .probe = davinci_mcasp_probe,
2194 .remove = davinci_mcasp_remove,
2195 .driver = {
2196 .name = "davinci-mcasp",
61754717 2197 .pm = &davinci_mcasp_pm_ops,
ea421eb1 2198 .of_match_table = mcasp_dt_ids,
b67f4487
C		 2199 },
2200};
2201
f9b8a514 2202module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 2203
2204MODULE_AUTHOR("Steve Chen");
2205MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2206MODULE_LICENSE("GPL");
Ubuntu Disco kernel mirror for Proxmox VE and PMG