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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d9ff33ad | 9 | * version 2.1 of the License, or (at your option) any later version. |
2c0262af FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 18 | */ |
07f5a258 MA |
19 | |
20 | #ifndef I386_CPU_H | |
21 | #define I386_CPU_H | |
2c0262af | 22 | |
14a48c1d | 23 | #include "sysemu/tcg.h" |
4da6f8d9 | 24 | #include "cpu-qom.h" |
a9dc68d9 | 25 | #include "kvm/hyperv-proto.h" |
c97d6d2c | 26 | #include "exec/cpu-defs.h" |
30d6ff66 | 27 | #include "qapi/qapi-types-common.h" |
69242e7e | 28 | #include "qemu/cpu-float.h" |
b746a779 | 29 | #include "qemu/timer.h" |
c97d6d2c | 30 | |
c723d4c1 DW |
31 | #define XEN_NR_VIRQS 24 |
32 | ||
72c1701f AB |
33 | /* The x86 has a strong memory model with some store-after-load re-ordering */ |
34 | #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) | |
35 | ||
e24fd076 DG |
36 | #define KVM_HAVE_MCE_INJECTION 1 |
37 | ||
d720b93d FB |
38 | /* support for self modifying code even if the modified instruction is |
39 | close to the modifying instruction */ | |
40 | #define TARGET_HAS_PRECISE_SMC | |
41 | ||
9042c0e2 | 42 | #ifdef TARGET_X86_64 |
a5e8788f | 43 | #define I386_ELF_MACHINE EM_X86_64 |
4ab23a91 | 44 | #define ELF_MACHINE_UNAME "x86_64" |
9042c0e2 | 45 | #else |
a5e8788f | 46 | #define I386_ELF_MACHINE EM_386 |
4ab23a91 | 47 | #define ELF_MACHINE_UNAME "i686" |
9042c0e2 TS |
48 | #endif |
49 | ||
6701d81d PB |
50 | enum { |
51 | R_EAX = 0, | |
52 | R_ECX = 1, | |
53 | R_EDX = 2, | |
54 | R_EBX = 3, | |
55 | R_ESP = 4, | |
56 | R_EBP = 5, | |
57 | R_ESI = 6, | |
58 | R_EDI = 7, | |
59 | R_R8 = 8, | |
60 | R_R9 = 9, | |
61 | R_R10 = 10, | |
62 | R_R11 = 11, | |
63 | R_R12 = 12, | |
64 | R_R13 = 13, | |
65 | R_R14 = 14, | |
66 | R_R15 = 15, | |
2c0262af | 67 | |
6701d81d PB |
68 | R_AL = 0, |
69 | R_CL = 1, | |
70 | R_DL = 2, | |
71 | R_BL = 3, | |
72 | R_AH = 4, | |
73 | R_CH = 5, | |
74 | R_DH = 6, | |
75 | R_BH = 7, | |
76 | }; | |
2c0262af | 77 | |
6701d81d PB |
78 | typedef enum X86Seg { |
79 | R_ES = 0, | |
80 | R_CS = 1, | |
81 | R_SS = 2, | |
82 | R_DS = 3, | |
83 | R_FS = 4, | |
84 | R_GS = 5, | |
85 | R_LDTR = 6, | |
86 | R_TR = 7, | |
87 | } X86Seg; | |
2c0262af FB |
88 | |
89 | /* segment descriptor fields */ | |
c97d6d2c SAGDR |
90 | #define DESC_G_SHIFT 23 |
91 | #define DESC_G_MASK (1 << DESC_G_SHIFT) | |
2c0262af FB |
92 | #define DESC_B_SHIFT 22 |
93 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
14ce26e7 FB |
94 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
95 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
c97d6d2c SAGDR |
96 | #define DESC_AVL_SHIFT 20 |
97 | #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) | |
98 | #define DESC_P_SHIFT 15 | |
99 | #define DESC_P_MASK (1 << DESC_P_SHIFT) | |
2c0262af | 100 | #define DESC_DPL_SHIFT 13 |
a3867ed2 | 101 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
c97d6d2c SAGDR |
102 | #define DESC_S_SHIFT 12 |
103 | #define DESC_S_MASK (1 << DESC_S_SHIFT) | |
2c0262af | 104 | #define DESC_TYPE_SHIFT 8 |
a3867ed2 | 105 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
2c0262af FB |
106 | #define DESC_A_MASK (1 << 8) |
107 | ||
e670b89e FB |
108 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
109 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
110 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
2c0262af | 111 | |
e670b89e FB |
112 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
113 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
114 | ||
115 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
2c0262af FB |
116 | |
117 | /* eflags masks */ | |
e4a09c96 PB |
118 | #define CC_C 0x0001 |
119 | #define CC_P 0x0004 | |
120 | #define CC_A 0x0010 | |
121 | #define CC_Z 0x0040 | |
2c0262af FB |
122 | #define CC_S 0x0080 |
123 | #define CC_O 0x0800 | |
124 | ||
125 | #define TF_SHIFT 8 | |
126 | #define IOPL_SHIFT 12 | |
127 | #define VM_SHIFT 17 | |
128 | ||
e4a09c96 PB |
129 | #define TF_MASK 0x00000100 |
130 | #define IF_MASK 0x00000200 | |
131 | #define DF_MASK 0x00000400 | |
132 | #define IOPL_MASK 0x00003000 | |
133 | #define NT_MASK 0x00004000 | |
134 | #define RF_MASK 0x00010000 | |
135 | #define VM_MASK 0x00020000 | |
136 | #define AC_MASK 0x00040000 | |
2c0262af FB |
137 | #define VIF_MASK 0x00080000 |
138 | #define VIP_MASK 0x00100000 | |
139 | #define ID_MASK 0x00200000 | |
140 | ||
aa1f17c1 | 141 | /* hidden flags - used internally by qemu to represent additional cpu |
7848c8d1 KC |
142 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We |
143 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit | |
144 | positions to ease oring with eflags. */ | |
2c0262af FB |
145 | /* current cpl */ |
146 | #define HF_CPL_SHIFT 0 | |
2c0262af FB |
147 | /* true if hardware interrupts must be disabled for next instruction */ |
148 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
149 | /* 16 or 32 segments */ | |
150 | #define HF_CS32_SHIFT 4 | |
151 | #define HF_SS32_SHIFT 5 | |
dc196a57 | 152 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
2c0262af | 153 | #define HF_ADDSEG_SHIFT 6 |
65262d57 FB |
154 | /* copy of CR0.PE (protected mode) */ |
155 | #define HF_PE_SHIFT 7 | |
156 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
7eee2a50 FB |
157 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
158 | #define HF_EM_SHIFT 10 | |
159 | #define HF_TS_SHIFT 11 | |
65262d57 | 160 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
14ce26e7 FB |
161 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
162 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
a2397807 | 163 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
65262d57 | 164 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
a9321a4d | 165 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
3b21e03e | 166 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
db620f46 | 167 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
f8dc4c64 | 168 | #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ |
a2397807 | 169 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
a9321a4d | 170 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
5223a942 | 171 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ |
f4f1110e RH |
172 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ |
173 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ | |
637f1ee3 | 174 | #define HF_UMIP_SHIFT 27 /* CR4.UMIP */ |
608db8db | 175 | #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */ |
2c0262af FB |
176 | |
177 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
2c0262af FB |
178 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
179 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
180 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
181 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
65262d57 | 182 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
58fe2f10 | 183 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
7eee2a50 FB |
184 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
185 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
186 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
0650f1ab | 187 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
14ce26e7 FB |
188 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
189 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
a2397807 | 190 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
0650f1ab | 191 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
a9321a4d | 192 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
3b21e03e | 193 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
872929aa | 194 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
f8dc4c64 | 195 | #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) |
a2397807 | 196 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
a9321a4d | 197 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
5223a942 | 198 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) |
f4f1110e RH |
199 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) |
200 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) | |
637f1ee3 | 201 | #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT) |
608db8db | 202 | #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT) |
2c0262af | 203 | |
db620f46 FB |
204 | /* hflags2 */ |
205 | ||
9982f74b PB |
206 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
207 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
208 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
209 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
210 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ | |
f4f1110e | 211 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ |
fe441054 | 212 | #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ |
bf13bfab | 213 | #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ |
b67e2796 | 214 | #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ |
9982f74b PB |
215 | |
216 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
217 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
218 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
219 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
220 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) | |
f4f1110e | 221 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) |
fe441054 | 222 | #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) |
bf13bfab | 223 | #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) |
b67e2796 | 224 | #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) |
db620f46 | 225 | |
0650f1ab AL |
226 | #define CR0_PE_SHIFT 0 |
227 | #define CR0_MP_SHIFT 1 | |
228 | ||
2cd49cbf PM |
229 | #define CR0_PE_MASK (1U << 0) |
230 | #define CR0_MP_MASK (1U << 1) | |
231 | #define CR0_EM_MASK (1U << 2) | |
232 | #define CR0_TS_MASK (1U << 3) | |
233 | #define CR0_ET_MASK (1U << 4) | |
234 | #define CR0_NE_MASK (1U << 5) | |
235 | #define CR0_WP_MASK (1U << 16) | |
236 | #define CR0_AM_MASK (1U << 18) | |
498df2a7 LL |
237 | #define CR0_NW_MASK (1U << 29) |
238 | #define CR0_CD_MASK (1U << 30) | |
2cd49cbf PM |
239 | #define CR0_PG_MASK (1U << 31) |
240 | ||
241 | #define CR4_VME_MASK (1U << 0) | |
242 | #define CR4_PVI_MASK (1U << 1) | |
243 | #define CR4_TSD_MASK (1U << 2) | |
244 | #define CR4_DE_MASK (1U << 3) | |
245 | #define CR4_PSE_MASK (1U << 4) | |
246 | #define CR4_PAE_MASK (1U << 5) | |
247 | #define CR4_MCE_MASK (1U << 6) | |
248 | #define CR4_PGE_MASK (1U << 7) | |
249 | #define CR4_PCE_MASK (1U << 8) | |
0650f1ab | 250 | #define CR4_OSFXSR_SHIFT 9 |
2cd49cbf PM |
251 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) |
252 | #define CR4_OSXMMEXCPT_MASK (1U << 10) | |
213ff024 | 253 | #define CR4_UMIP_MASK (1U << 11) |
6c7c3c21 | 254 | #define CR4_LA57_MASK (1U << 12) |
2cd49cbf PM |
255 | #define CR4_VMXE_MASK (1U << 13) |
256 | #define CR4_SMXE_MASK (1U << 14) | |
257 | #define CR4_FSGSBASE_MASK (1U << 16) | |
258 | #define CR4_PCIDE_MASK (1U << 17) | |
259 | #define CR4_OSXSAVE_MASK (1U << 18) | |
260 | #define CR4_SMEP_MASK (1U << 20) | |
261 | #define CR4_SMAP_MASK (1U << 21) | |
0f70ed47 | 262 | #define CR4_PKE_MASK (1U << 22) |
e7e7bdab | 263 | #define CR4_PKS_MASK (1U << 24) |
2c0262af | 264 | |
213ff024 LL |
265 | #define CR4_RESERVED_MASK \ |
266 | (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | |
267 | | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ | |
268 | | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ | |
637f1ee3 | 269 | | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ |
69e3895f | 270 | | CR4_LA57_MASK \ |
213ff024 LL |
271 | | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ |
272 | | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) | |
273 | ||
01df040b AL |
274 | #define DR6_BD (1 << 13) |
275 | #define DR6_BS (1 << 14) | |
276 | #define DR6_BT (1 << 15) | |
277 | #define DR6_FIXED_1 0xffff0ff0 | |
278 | ||
279 | #define DR7_GD (1 << 13) | |
280 | #define DR7_TYPE_SHIFT 16 | |
281 | #define DR7_LEN_SHIFT 18 | |
282 | #define DR7_FIXED_1 0x00000400 | |
93d00d0f | 283 | #define DR7_GLOBAL_BP_MASK 0xaa |
428065ce LG |
284 | #define DR7_LOCAL_BP_MASK 0x55 |
285 | #define DR7_MAX_BP 4 | |
286 | #define DR7_TYPE_BP_INST 0x0 | |
287 | #define DR7_TYPE_DATA_WR 0x1 | |
288 | #define DR7_TYPE_IO_RW 0x2 | |
289 | #define DR7_TYPE_DATA_RW 0x3 | |
01df040b | 290 | |
533883fd PB |
291 | #define DR_RESERVED_MASK 0xffffffff00000000ULL |
292 | ||
e4a09c96 PB |
293 | #define PG_PRESENT_BIT 0 |
294 | #define PG_RW_BIT 1 | |
295 | #define PG_USER_BIT 2 | |
296 | #define PG_PWT_BIT 3 | |
297 | #define PG_PCD_BIT 4 | |
298 | #define PG_ACCESSED_BIT 5 | |
299 | #define PG_DIRTY_BIT 6 | |
300 | #define PG_PSE_BIT 7 | |
301 | #define PG_GLOBAL_BIT 8 | |
eaad03e4 | 302 | #define PG_PSE_PAT_BIT 12 |
0f70ed47 | 303 | #define PG_PKRU_BIT 59 |
e4a09c96 | 304 | #define PG_NX_BIT 63 |
2c0262af FB |
305 | |
306 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
e4a09c96 PB |
307 | #define PG_RW_MASK (1 << PG_RW_BIT) |
308 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
309 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
310 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
2c0262af | 311 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
e4a09c96 PB |
312 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
313 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
314 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
eaad03e4 | 315 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) |
e8f6d00c | 316 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL |
3f2cbf0d | 317 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
0f70ed47 PB |
318 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) |
319 | #define PG_NX_MASK (1ULL << PG_NX_BIT) | |
2c0262af FB |
320 | |
321 | #define PG_ERROR_W_BIT 1 | |
322 | ||
323 | #define PG_ERROR_P_MASK 0x01 | |
324 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
325 | #define PG_ERROR_U_MASK 0x04 | |
326 | #define PG_ERROR_RSVD_MASK 0x08 | |
5cf38396 | 327 | #define PG_ERROR_I_D_MASK 0x10 |
0f70ed47 | 328 | #define PG_ERROR_PK_MASK 0x20 |
2c0262af | 329 | |
616a89ea PB |
330 | #define PG_MODE_PAE (1 << 0) |
331 | #define PG_MODE_LMA (1 << 1) | |
332 | #define PG_MODE_NXE (1 << 2) | |
333 | #define PG_MODE_PSE (1 << 3) | |
31dd35eb PB |
334 | #define PG_MODE_LA57 (1 << 4) |
335 | #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) | |
336 | ||
337 | /* Bits of CR4 that do not affect the NPT page format. */ | |
338 | #define PG_MODE_WP (1 << 16) | |
339 | #define PG_MODE_PKE (1 << 17) | |
340 | #define PG_MODE_PKS (1 << 18) | |
341 | #define PG_MODE_SMEP (1 << 19) | |
616a89ea | 342 | |
e4a09c96 PB |
343 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
344 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
87f8b626 | 345 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ |
79c4f6b0 | 346 | |
e4a09c96 PB |
347 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
348 | #define MCE_BANKS_DEF 10 | |
79c4f6b0 | 349 | |
2590f15b EH |
350 | #define MCG_CAP_BANKS_MASK 0xff |
351 | ||
e4a09c96 PB |
352 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
353 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
354 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
87f8b626 AR |
355 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ |
356 | ||
357 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ | |
79c4f6b0 | 358 | |
e4a09c96 PB |
359 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
360 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
361 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
362 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
363 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
364 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
365 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
366 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
367 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
c0532a76 MT |
368 | |
369 | /* MISC register defines */ | |
e4a09c96 PB |
370 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
371 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
372 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
373 | #define MCM_ADDR_MEM 3 /* memory address */ | |
374 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
79c4f6b0 | 375 | |
0650f1ab | 376 | #define MSR_IA32_TSC 0x10 |
2c0262af FB |
377 | #define MSR_IA32_APICBASE 0x1b |
378 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
379 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
33d7a288 | 380 | #define MSR_IA32_APICBASE_EXTD (1 << 10) |
458cf469 | 381 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) |
0779caeb | 382 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
f28558d3 | 383 | #define MSR_TSC_ADJUST 0x0000003b |
a33a2cfe | 384 | #define MSR_IA32_SPEC_CTRL 0x48 |
cfeea0c0 | 385 | #define MSR_VIRT_SSBD 0xc001011f |
8c80c99f | 386 | #define MSR_IA32_PRED_CMD 0x49 |
4e45aff3 | 387 | #define MSR_IA32_UCODE_REV 0x8b |
597360c0 | 388 | #define MSR_IA32_CORE_CAPABILITY 0xcf |
2a9758c5 | 389 | |
8c80c99f | 390 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a |
2a9758c5 PB |
391 | #define ARCH_CAP_TSX_CTRL_MSR (1<<7) |
392 | ||
ea39f9b6 | 393 | #define MSR_IA32_PERF_CAPABILITIES 0x345 |
f06d8a18 | 394 | #define PERF_CAP_LBR_FMT 0x3f |
ea39f9b6 | 395 | |
2a9758c5 | 396 | #define MSR_IA32_TSX_CTRL 0x122 |
aa82ba54 | 397 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
e7e7bdab | 398 | #define MSR_IA32_PKRS 0x6e1 |
12703d4e YW |
399 | #define MSR_ARCH_LBR_CTL 0x000014ce |
400 | #define MSR_ARCH_LBR_DEPTH 0x000014cf | |
401 | #define MSR_ARCH_LBR_FROM_0 0x00001500 | |
402 | #define MSR_ARCH_LBR_TO_0 0x00001600 | |
403 | #define MSR_ARCH_LBR_INFO_0 0x00001200 | |
2c0262af | 404 | |
217f1b4a | 405 | #define FEATURE_CONTROL_LOCKED (1<<0) |
5c76b651 | 406 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1) |
217f1b4a | 407 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
5c76b651 SC |
408 | #define FEATURE_CONTROL_SGX_LC (1ULL << 17) |
409 | #define FEATURE_CONTROL_SGX (1ULL << 18) | |
217f1b4a HZ |
410 | #define FEATURE_CONTROL_LMCE (1<<20) |
411 | ||
5c76b651 SC |
412 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c |
413 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d | |
414 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e | |
415 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f | |
416 | ||
0d894367 PB |
417 | #define MSR_P6_PERFCTR0 0xc1 |
418 | ||
fc12d72e | 419 | #define MSR_IA32_SMBASE 0x9e |
e13713db | 420 | #define MSR_SMI_COUNT 0x34 |
027ac0cb | 421 | #define MSR_CORE_THREAD_COUNT 0x35 |
e4a09c96 PB |
422 | #define MSR_MTRRcap 0xfe |
423 | #define MSR_MTRRcap_VCNT 8 | |
424 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
425 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
dd5e3b17 | 426 | |
2c0262af FB |
427 | #define MSR_IA32_SYSENTER_CS 0x174 |
428 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
429 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
430 | ||
8f091a59 FB |
431 | #define MSR_MCG_CAP 0x179 |
432 | #define MSR_MCG_STATUS 0x17a | |
433 | #define MSR_MCG_CTL 0x17b | |
87f8b626 | 434 | #define MSR_MCG_EXT_CTL 0x4d0 |
8f091a59 | 435 | |
0d894367 PB |
436 | #define MSR_P6_EVNTSEL0 0x186 |
437 | ||
e737b32a AZ |
438 | #define MSR_IA32_PERF_STATUS 0x198 |
439 | ||
e4a09c96 | 440 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
21e87c46 AK |
441 | /* Indicates good rep/movs microcode on some processors: */ |
442 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
4cfd7bab | 443 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) |
21e87c46 | 444 | |
e4a09c96 PB |
445 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
446 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
447 | ||
d1ae67f6 AW |
448 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) |
449 | ||
e4a09c96 PB |
450 | #define MSR_MTRRfix64K_00000 0x250 |
451 | #define MSR_MTRRfix16K_80000 0x258 | |
452 | #define MSR_MTRRfix16K_A0000 0x259 | |
453 | #define MSR_MTRRfix4K_C0000 0x268 | |
454 | #define MSR_MTRRfix4K_C8000 0x269 | |
455 | #define MSR_MTRRfix4K_D0000 0x26a | |
456 | #define MSR_MTRRfix4K_D8000 0x26b | |
457 | #define MSR_MTRRfix4K_E0000 0x26c | |
458 | #define MSR_MTRRfix4K_E8000 0x26d | |
459 | #define MSR_MTRRfix4K_F0000 0x26e | |
460 | #define MSR_MTRRfix4K_F8000 0x26f | |
165d9b82 | 461 | |
8f091a59 FB |
462 | #define MSR_PAT 0x277 |
463 | ||
e4a09c96 | 464 | #define MSR_MTRRdefType 0x2ff |
165d9b82 | 465 | |
0d894367 PB |
466 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 |
467 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | |
468 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | |
469 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | |
470 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | |
471 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | |
472 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | |
165d9b82 | 473 | |
e4a09c96 PB |
474 | #define MSR_MC0_CTL 0x400 |
475 | #define MSR_MC0_STATUS 0x401 | |
476 | #define MSR_MC0_ADDR 0x402 | |
477 | #define MSR_MC0_MISC 0x403 | |
79c4f6b0 | 478 | |
b77146e9 CP |
479 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 |
480 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 | |
481 | #define MSR_IA32_RTIT_CTL 0x570 | |
482 | #define MSR_IA32_RTIT_STATUS 0x571 | |
483 | #define MSR_IA32_RTIT_CR3_MATCH 0x572 | |
484 | #define MSR_IA32_RTIT_ADDR0_A 0x580 | |
485 | #define MSR_IA32_RTIT_ADDR0_B 0x581 | |
486 | #define MSR_IA32_RTIT_ADDR1_A 0x582 | |
487 | #define MSR_IA32_RTIT_ADDR1_B 0x583 | |
488 | #define MSR_IA32_RTIT_ADDR2_A 0x584 | |
489 | #define MSR_IA32_RTIT_ADDR2_B 0x585 | |
490 | #define MSR_IA32_RTIT_ADDR3_A 0x586 | |
491 | #define MSR_IA32_RTIT_ADDR3_B 0x587 | |
492 | #define MAX_RTIT_ADDRS 8 | |
493 | ||
14ce26e7 FB |
494 | #define MSR_EFER 0xc0000080 |
495 | ||
496 | #define MSR_EFER_SCE (1 << 0) | |
497 | #define MSR_EFER_LME (1 << 8) | |
498 | #define MSR_EFER_LMA (1 << 10) | |
499 | #define MSR_EFER_NXE (1 << 11) | |
872929aa | 500 | #define MSR_EFER_SVME (1 << 12) |
14ce26e7 FB |
501 | #define MSR_EFER_FFXSR (1 << 14) |
502 | ||
d499f196 LL |
503 | #define MSR_EFER_RESERVED\ |
504 | (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ | |
505 | | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ | |
506 | | MSR_EFER_FFXSR)) | |
507 | ||
14ce26e7 FB |
508 | #define MSR_STAR 0xc0000081 |
509 | #define MSR_LSTAR 0xc0000082 | |
510 | #define MSR_CSTAR 0xc0000083 | |
511 | #define MSR_FMASK 0xc0000084 | |
512 | #define MSR_FSBASE 0xc0000100 | |
513 | #define MSR_GSBASE 0xc0000101 | |
514 | #define MSR_KERNELGSBASE 0xc0000102 | |
1b050077 | 515 | #define MSR_TSC_AUX 0xc0000103 |
cabf9862 ML |
516 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
517 | ||
518 | #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL | |
14ce26e7 | 519 | |
0573fbfc TS |
520 | #define MSR_VM_HSAVE_PA 0xc0010117 |
521 | ||
cdec2b75 ZG |
522 | #define MSR_IA32_XFD 0x000001c4 |
523 | #define MSR_IA32_XFD_ERR 0x000001c5 | |
524 | ||
79e9ebeb | 525 | #define MSR_IA32_BNDCFGS 0x00000d90 |
18cd2c17 | 526 | #define MSR_IA32_XSS 0x00000da0 |
65087997 | 527 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 |
79e9ebeb | 528 | |
704798ad PB |
529 | #define MSR_IA32_VMX_BASIC 0x00000480 |
530 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | |
531 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | |
532 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | |
533 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | |
534 | #define MSR_IA32_VMX_MISC 0x00000485 | |
535 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | |
536 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | |
537 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | |
538 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | |
539 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | |
540 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | |
541 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | |
542 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d | |
543 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e | |
544 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f | |
545 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 | |
546 | #define MSR_IA32_VMX_VMFUNC 0x00000491 | |
547 | ||
cfc3b074 PB |
548 | #define XSTATE_FP_BIT 0 |
549 | #define XSTATE_SSE_BIT 1 | |
550 | #define XSTATE_YMM_BIT 2 | |
551 | #define XSTATE_BNDREGS_BIT 3 | |
552 | #define XSTATE_BNDCSR_BIT 4 | |
553 | #define XSTATE_OPMASK_BIT 5 | |
554 | #define XSTATE_ZMM_Hi256_BIT 6 | |
555 | #define XSTATE_Hi16_ZMM_BIT 7 | |
556 | #define XSTATE_PKRU_BIT 9 | |
10f0abcb | 557 | #define XSTATE_ARCH_LBR_BIT 15 |
1f16764f JL |
558 | #define XSTATE_XTILE_CFG_BIT 17 |
559 | #define XSTATE_XTILE_DATA_BIT 18 | |
cfc3b074 PB |
560 | |
561 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) | |
562 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) | |
563 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) | |
564 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) | |
565 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) | |
566 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) | |
567 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) | |
568 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) | |
569 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) | |
10f0abcb | 570 | #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) |
19db68ca YZ |
571 | #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) |
572 | #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) | |
573 | ||
574 | #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) | |
c74f41bb | 575 | |
131266b7 | 576 | #define ESA_FEATURE_ALIGN64_BIT 1 |
0f17f6b3 | 577 | #define ESA_FEATURE_XFD_BIT 2 |
131266b7 JL |
578 | |
579 | #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) | |
0f17f6b3 | 580 | #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) |
131266b7 JL |
581 | |
582 | ||
301e9067 YW |
583 | /* CPUID feature bits available in XCR0 */ |
584 | #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ | |
585 | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ | |
586 | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \ | |
587 | XSTATE_ZMM_Hi256_MASK | \ | |
588 | XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \ | |
589 | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK) | |
590 | ||
5ef57876 EH |
591 | /* CPUID feature words */ |
592 | typedef enum FeatureWord { | |
593 | FEAT_1_EDX, /* CPUID[1].EDX */ | |
594 | FEAT_1_ECX, /* CPUID[1].ECX */ | |
595 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ | |
f74eefe0 | 596 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ |
95ea69fb | 597 | FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ |
80db491d | 598 | FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ |
5ef57876 EH |
599 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
600 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ | |
303752a9 | 601 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ |
1b3420e1 | 602 | FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ |
b70eec31 | 603 | FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ |
5ef57876 EH |
604 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
605 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ | |
be777326 | 606 | FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ |
5ef57876 | 607 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
0bb0b2d2 | 608 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ |
28b8e4d0 | 609 | FEAT_6_EAX, /* CPUID[6].EAX */ |
301e9067 YW |
610 | FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ |
611 | FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ | |
d86f9636 | 612 | FEAT_ARCH_CAPABILITIES, |
597360c0 | 613 | FEAT_CORE_CAPABILITY, |
ea39f9b6 | 614 | FEAT_PERF_CAPABILITIES, |
20a78b02 PB |
615 | FEAT_VMX_PROCBASED_CTLS, |
616 | FEAT_VMX_SECONDARY_CTLS, | |
617 | FEAT_VMX_PINBASED_CTLS, | |
618 | FEAT_VMX_EXIT_CTLS, | |
619 | FEAT_VMX_ENTRY_CTLS, | |
620 | FEAT_VMX_MISC, | |
621 | FEAT_VMX_EPT_VPID_CAPS, | |
622 | FEAT_VMX_BASIC, | |
623 | FEAT_VMX_VMFUNC, | |
d1615ea5 | 624 | FEAT_14_0_ECX, |
4b841a79 | 625 | FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ |
120ca112 | 626 | FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ |
165981a5 | 627 | FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ |
301e9067 YW |
628 | FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ |
629 | FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ | |
eaaa197d | 630 | FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ |
9dd8b710 | 631 | FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ |
5ef57876 EH |
632 | FEATURE_WORDS, |
633 | } FeatureWord; | |
634 | ||
ede146c2 | 635 | typedef uint64_t FeatureWordArray[FEATURE_WORDS]; |
58f7db26 PB |
636 | uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, |
637 | bool migratable_only); | |
5ef57876 | 638 | |
14ce26e7 | 639 | /* cpuid_features bits */ |
2cd49cbf PM |
640 | #define CPUID_FP87 (1U << 0) |
641 | #define CPUID_VME (1U << 1) | |
642 | #define CPUID_DE (1U << 2) | |
643 | #define CPUID_PSE (1U << 3) | |
644 | #define CPUID_TSC (1U << 4) | |
645 | #define CPUID_MSR (1U << 5) | |
646 | #define CPUID_PAE (1U << 6) | |
647 | #define CPUID_MCE (1U << 7) | |
648 | #define CPUID_CX8 (1U << 8) | |
649 | #define CPUID_APIC (1U << 9) | |
650 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ | |
651 | #define CPUID_MTRR (1U << 12) | |
652 | #define CPUID_PGE (1U << 13) | |
653 | #define CPUID_MCA (1U << 14) | |
654 | #define CPUID_CMOV (1U << 15) | |
655 | #define CPUID_PAT (1U << 16) | |
656 | #define CPUID_PSE36 (1U << 17) | |
657 | #define CPUID_PN (1U << 18) | |
658 | #define CPUID_CLFLUSH (1U << 19) | |
659 | #define CPUID_DTS (1U << 21) | |
660 | #define CPUID_ACPI (1U << 22) | |
661 | #define CPUID_MMX (1U << 23) | |
662 | #define CPUID_FXSR (1U << 24) | |
663 | #define CPUID_SSE (1U << 25) | |
664 | #define CPUID_SSE2 (1U << 26) | |
665 | #define CPUID_SS (1U << 27) | |
666 | #define CPUID_HT (1U << 28) | |
667 | #define CPUID_TM (1U << 29) | |
668 | #define CPUID_IA64 (1U << 30) | |
669 | #define CPUID_PBE (1U << 31) | |
670 | ||
671 | #define CPUID_EXT_SSE3 (1U << 0) | |
672 | #define CPUID_EXT_PCLMULQDQ (1U << 1) | |
673 | #define CPUID_EXT_DTES64 (1U << 2) | |
674 | #define CPUID_EXT_MONITOR (1U << 3) | |
675 | #define CPUID_EXT_DSCPL (1U << 4) | |
676 | #define CPUID_EXT_VMX (1U << 5) | |
677 | #define CPUID_EXT_SMX (1U << 6) | |
678 | #define CPUID_EXT_EST (1U << 7) | |
679 | #define CPUID_EXT_TM2 (1U << 8) | |
680 | #define CPUID_EXT_SSSE3 (1U << 9) | |
681 | #define CPUID_EXT_CID (1U << 10) | |
682 | #define CPUID_EXT_FMA (1U << 12) | |
683 | #define CPUID_EXT_CX16 (1U << 13) | |
684 | #define CPUID_EXT_XTPR (1U << 14) | |
685 | #define CPUID_EXT_PDCM (1U << 15) | |
686 | #define CPUID_EXT_PCID (1U << 17) | |
687 | #define CPUID_EXT_DCA (1U << 18) | |
688 | #define CPUID_EXT_SSE41 (1U << 19) | |
689 | #define CPUID_EXT_SSE42 (1U << 20) | |
690 | #define CPUID_EXT_X2APIC (1U << 21) | |
691 | #define CPUID_EXT_MOVBE (1U << 22) | |
692 | #define CPUID_EXT_POPCNT (1U << 23) | |
693 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) | |
694 | #define CPUID_EXT_AES (1U << 25) | |
695 | #define CPUID_EXT_XSAVE (1U << 26) | |
696 | #define CPUID_EXT_OSXSAVE (1U << 27) | |
697 | #define CPUID_EXT_AVX (1U << 28) | |
698 | #define CPUID_EXT_F16C (1U << 29) | |
699 | #define CPUID_EXT_RDRAND (1U << 30) | |
700 | #define CPUID_EXT_HYPERVISOR (1U << 31) | |
701 | ||
702 | #define CPUID_EXT2_FPU (1U << 0) | |
703 | #define CPUID_EXT2_VME (1U << 1) | |
704 | #define CPUID_EXT2_DE (1U << 2) | |
705 | #define CPUID_EXT2_PSE (1U << 3) | |
706 | #define CPUID_EXT2_TSC (1U << 4) | |
707 | #define CPUID_EXT2_MSR (1U << 5) | |
708 | #define CPUID_EXT2_PAE (1U << 6) | |
709 | #define CPUID_EXT2_MCE (1U << 7) | |
710 | #define CPUID_EXT2_CX8 (1U << 8) | |
711 | #define CPUID_EXT2_APIC (1U << 9) | |
712 | #define CPUID_EXT2_SYSCALL (1U << 11) | |
713 | #define CPUID_EXT2_MTRR (1U << 12) | |
714 | #define CPUID_EXT2_PGE (1U << 13) | |
715 | #define CPUID_EXT2_MCA (1U << 14) | |
716 | #define CPUID_EXT2_CMOV (1U << 15) | |
717 | #define CPUID_EXT2_PAT (1U << 16) | |
718 | #define CPUID_EXT2_PSE36 (1U << 17) | |
719 | #define CPUID_EXT2_MP (1U << 19) | |
720 | #define CPUID_EXT2_NX (1U << 20) | |
721 | #define CPUID_EXT2_MMXEXT (1U << 22) | |
722 | #define CPUID_EXT2_MMX (1U << 23) | |
723 | #define CPUID_EXT2_FXSR (1U << 24) | |
724 | #define CPUID_EXT2_FFXSR (1U << 25) | |
725 | #define CPUID_EXT2_PDPE1GB (1U << 26) | |
726 | #define CPUID_EXT2_RDTSCP (1U << 27) | |
727 | #define CPUID_EXT2_LM (1U << 29) | |
728 | #define CPUID_EXT2_3DNOWEXT (1U << 30) | |
729 | #define CPUID_EXT2_3DNOW (1U << 31) | |
9df217a3 | 730 | |
bad5cfcd | 731 | /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */ |
8fad4b44 EH |
732 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ |
733 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
734 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
735 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
736 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
737 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
738 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
739 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
740 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
741 | ||
2cd49cbf PM |
742 | #define CPUID_EXT3_LAHF_LM (1U << 0) |
743 | #define CPUID_EXT3_CMP_LEG (1U << 1) | |
744 | #define CPUID_EXT3_SVM (1U << 2) | |
745 | #define CPUID_EXT3_EXTAPIC (1U << 3) | |
746 | #define CPUID_EXT3_CR8LEG (1U << 4) | |
747 | #define CPUID_EXT3_ABM (1U << 5) | |
748 | #define CPUID_EXT3_SSE4A (1U << 6) | |
749 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) | |
750 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) | |
751 | #define CPUID_EXT3_OSVW (1U << 9) | |
752 | #define CPUID_EXT3_IBS (1U << 10) | |
753 | #define CPUID_EXT3_XOP (1U << 11) | |
754 | #define CPUID_EXT3_SKINIT (1U << 12) | |
755 | #define CPUID_EXT3_WDT (1U << 13) | |
756 | #define CPUID_EXT3_LWP (1U << 15) | |
757 | #define CPUID_EXT3_FMA4 (1U << 16) | |
758 | #define CPUID_EXT3_TCE (1U << 17) | |
759 | #define CPUID_EXT3_NODEID (1U << 19) | |
760 | #define CPUID_EXT3_TBM (1U << 21) | |
761 | #define CPUID_EXT3_TOPOEXT (1U << 22) | |
762 | #define CPUID_EXT3_PERFCORE (1U << 23) | |
763 | #define CPUID_EXT3_PERFNB (1U << 24) | |
764 | ||
5447089c WH |
765 | #define CPUID_SVM_NPT (1U << 0) |
766 | #define CPUID_SVM_LBRV (1U << 1) | |
767 | #define CPUID_SVM_SVMLOCK (1U << 2) | |
768 | #define CPUID_SVM_NRIPSAVE (1U << 3) | |
769 | #define CPUID_SVM_TSCSCALE (1U << 4) | |
770 | #define CPUID_SVM_VMCBCLEAN (1U << 5) | |
771 | #define CPUID_SVM_FLUSHASID (1U << 6) | |
772 | #define CPUID_SVM_DECODEASSIST (1U << 7) | |
773 | #define CPUID_SVM_PAUSEFILTER (1U << 10) | |
774 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) | |
775 | #define CPUID_SVM_AVIC (1U << 13) | |
776 | #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) | |
777 | #define CPUID_SVM_VGIF (1U << 16) | |
62a798d4 | 778 | #define CPUID_SVM_VNMI (1U << 25) |
5447089c | 779 | #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) |
2cd49cbf | 780 | |
f2be0beb TX |
781 | /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ |
782 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) | |
5c76b651 SC |
783 | /* Support SGX */ |
784 | #define CPUID_7_0_EBX_SGX (1U << 2) | |
f2be0beb TX |
785 | /* 1st Group of Advanced Bit Manipulation Extensions */ |
786 | #define CPUID_7_0_EBX_BMI1 (1U << 3) | |
787 | /* Hardware Lock Elision */ | |
788 | #define CPUID_7_0_EBX_HLE (1U << 4) | |
789 | /* Intel Advanced Vector Extensions 2 */ | |
790 | #define CPUID_7_0_EBX_AVX2 (1U << 5) | |
791 | /* Supervisor-mode Execution Prevention */ | |
792 | #define CPUID_7_0_EBX_SMEP (1U << 7) | |
793 | /* 2nd Group of Advanced Bit Manipulation Extensions */ | |
794 | #define CPUID_7_0_EBX_BMI2 (1U << 8) | |
795 | /* Enhanced REP MOVSB/STOSB */ | |
796 | #define CPUID_7_0_EBX_ERMS (1U << 9) | |
797 | /* Invalidate Process-Context Identifier */ | |
798 | #define CPUID_7_0_EBX_INVPCID (1U << 10) | |
799 | /* Restricted Transactional Memory */ | |
800 | #define CPUID_7_0_EBX_RTM (1U << 11) | |
801 | /* Memory Protection Extension */ | |
802 | #define CPUID_7_0_EBX_MPX (1U << 14) | |
803 | /* AVX-512 Foundation */ | |
804 | #define CPUID_7_0_EBX_AVX512F (1U << 16) | |
805 | /* AVX-512 Doubleword & Quadword Instruction */ | |
806 | #define CPUID_7_0_EBX_AVX512DQ (1U << 17) | |
807 | /* Read Random SEED */ | |
808 | #define CPUID_7_0_EBX_RDSEED (1U << 18) | |
809 | /* ADCX and ADOX instructions */ | |
810 | #define CPUID_7_0_EBX_ADX (1U << 19) | |
811 | /* Supervisor Mode Access Prevention */ | |
812 | #define CPUID_7_0_EBX_SMAP (1U << 20) | |
813 | /* AVX-512 Integer Fused Multiply Add */ | |
814 | #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) | |
815 | /* Persistent Commit */ | |
816 | #define CPUID_7_0_EBX_PCOMMIT (1U << 22) | |
817 | /* Flush a Cache Line Optimized */ | |
818 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) | |
819 | /* Cache Line Write Back */ | |
820 | #define CPUID_7_0_EBX_CLWB (1U << 24) | |
821 | /* Intel Processor Trace */ | |
822 | #define CPUID_7_0_EBX_INTEL_PT (1U << 25) | |
823 | /* AVX-512 Prefetch */ | |
824 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) | |
825 | /* AVX-512 Exponential and Reciprocal */ | |
826 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) | |
827 | /* AVX-512 Conflict Detection */ | |
828 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) | |
829 | /* SHA1/SHA256 Instruction Extensions */ | |
830 | #define CPUID_7_0_EBX_SHA_NI (1U << 29) | |
831 | /* AVX-512 Byte and Word Instructions */ | |
832 | #define CPUID_7_0_EBX_AVX512BW (1U << 30) | |
833 | /* AVX-512 Vector Length Extensions */ | |
834 | #define CPUID_7_0_EBX_AVX512VL (1U << 31) | |
835 | ||
836 | /* AVX-512 Vector Byte Manipulation Instruction */ | |
e7694a5e | 837 | #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) |
f2be0beb TX |
838 | /* User-Mode Instruction Prevention */ |
839 | #define CPUID_7_0_ECX_UMIP (1U << 2) | |
840 | /* Protection Keys for User-mode Pages */ | |
841 | #define CPUID_7_0_ECX_PKU (1U << 3) | |
842 | /* OS Enable Protection Keys */ | |
843 | #define CPUID_7_0_ECX_OSPKE (1U << 4) | |
67192a29 TX |
844 | /* UMONITOR/UMWAIT/TPAUSE Instructions */ |
845 | #define CPUID_7_0_ECX_WAITPKG (1U << 5) | |
f2be0beb | 846 | /* Additional AVX-512 Vector Byte Manipulation Instruction */ |
e7694a5e | 847 | #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) |
f2be0beb TX |
848 | /* Galois Field New Instructions */ |
849 | #define CPUID_7_0_ECX_GFNI (1U << 8) | |
850 | /* Vector AES Instructions */ | |
851 | #define CPUID_7_0_ECX_VAES (1U << 9) | |
852 | /* Carry-Less Multiplication Quadword */ | |
853 | #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) | |
854 | /* Vector Neural Network Instructions */ | |
855 | #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) | |
856 | /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ | |
857 | #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) | |
858 | /* POPCNT for vectors of DW/QW */ | |
859 | #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) | |
860 | /* 5-level Page Tables */ | |
861 | #define CPUID_7_0_ECX_LA57 (1U << 16) | |
862 | /* Read Processor ID */ | |
863 | #define CPUID_7_0_ECX_RDPID (1U << 22) | |
06e878b4 CQ |
864 | /* Bus Lock Debug Exception */ |
865 | #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) | |
f2be0beb TX |
866 | /* Cache Line Demote Instruction */ |
867 | #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) | |
868 | /* Move Doubleword as Direct Store Instruction */ | |
869 | #define CPUID_7_0_ECX_MOVDIRI (1U << 27) | |
870 | /* Move 64 Bytes as Direct Store Instruction */ | |
871 | #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) | |
5c76b651 SC |
872 | /* Support SGX Launch Control */ |
873 | #define CPUID_7_0_ECX_SGX_LC (1U << 30) | |
e7e7bdab PB |
874 | /* Protection Keys for Supervisor-mode Pages */ |
875 | #define CPUID_7_0_ECX_PKS (1U << 31) | |
f2be0beb TX |
876 | |
877 | /* AVX512 Neural Network Instructions */ | |
878 | #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) | |
879 | /* AVX512 Multiply Accumulation Single Precision */ | |
880 | #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) | |
5cb287d2 CQ |
881 | /* Fast Short Rep Mov */ |
882 | #define CPUID_7_0_EDX_FSRM (1U << 4) | |
353f98c9 CZ |
883 | /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ |
884 | #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) | |
5dd13f2a CZ |
885 | /* SERIALIZE instruction */ |
886 | #define CPUID_7_0_EDX_SERIALIZE (1U << 14) | |
b3c7344e CZ |
887 | /* TSX Suspend Load Address Tracking instruction */ |
888 | #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) | |
10f0abcb YW |
889 | /* Architectural LBRs */ |
890 | #define CPUID_7_0_EDX_ARCH_LBR (1U << 19) | |
7eb061b0 WL |
891 | /* AMX_BF16 instruction */ |
892 | #define CPUID_7_0_EDX_AMX_BF16 (1U << 22) | |
40399ecb CZ |
893 | /* AVX512_FP16 instruction */ |
894 | #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) | |
1f16764f JL |
895 | /* AMX tile (two-dimensional register) */ |
896 | #define CPUID_7_0_EDX_AMX_TILE (1U << 24) | |
7eb061b0 WL |
897 | /* AMX_INT8 instruction */ |
898 | #define CPUID_7_0_EDX_AMX_INT8 (1U << 25) | |
f2be0beb TX |
899 | /* Speculation Control */ |
900 | #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) | |
5af514d0 CZ |
901 | /* Single Thread Indirect Branch Predictors */ |
902 | #define CPUID_7_0_EDX_STIBP (1U << 27) | |
0e7e3bf1 EGE |
903 | /* Flush L1D cache */ |
904 | #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28) | |
f2be0beb TX |
905 | /* Arch Capabilities */ |
906 | #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) | |
907 | /* Core Capability */ | |
908 | #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) | |
909 | /* Speculative Store Bypass Disable */ | |
910 | #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) | |
911 | ||
c1826ea6 YZ |
912 | /* AVX VNNI Instruction */ |
913 | #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) | |
f2be0beb TX |
914 | /* AVX512 BFloat16 Instruction */ |
915 | #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) | |
a9ce107f JC |
916 | /* CMPCCXADD Instructions */ |
917 | #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) | |
58794f64 PB |
918 | /* Fast Zero REP MOVS */ |
919 | #define CPUID_7_1_EAX_FZRM (1U << 10) | |
920 | /* Fast Short REP STOS */ | |
921 | #define CPUID_7_1_EAX_FSRS (1U << 11) | |
922 | /* Fast Short REP CMPS/SCAS */ | |
923 | #define CPUID_7_1_EAX_FSRC (1U << 12) | |
99ed8445 JC |
924 | /* Support Tile Computational Operations on FP16 Numbers */ |
925 | #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) | |
a957a884 JC |
926 | /* Support for VPMADD52[H,L]UQ */ |
927 | #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) | |
58794f64 | 928 | |
eaaa197d JC |
929 | /* Support for VPDPB[SU,UU,SS]D[,S] */ |
930 | #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) | |
ecd2e6ca JC |
931 | /* AVX NE CONVERT Instructions */ |
932 | #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) | |
3e76bafb TS |
933 | /* AMX COMPLEX Instructions */ |
934 | #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8) | |
d1a11115 JC |
935 | /* PREFETCHIT0/1 Instructions */ |
936 | #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) | |
eaaa197d | 937 | |
9dd8b710 TS |
938 | /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ |
939 | #define CPUID_7_2_EDX_MCDT_NO (1U << 5) | |
940 | ||
cdec2b75 ZG |
941 | /* XFD Extend Feature Disabled */ |
942 | #define CPUID_D_1_EAX_XFD (1U << 4) | |
f2be0beb | 943 | |
d1615ea5 LK |
944 | /* Packets which contain IP payload have LIP values */ |
945 | #define CPUID_14_0_ECX_LIP (1U << 31) | |
946 | ||
f2be0beb TX |
947 | /* CLZERO instruction */ |
948 | #define CPUID_8000_0008_EBX_CLZERO (1U << 0) | |
949 | /* Always save/restore FP error pointers */ | |
950 | #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) | |
951 | /* Write back and do not invalidate cache */ | |
952 | #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) | |
953 | /* Indirect Branch Prediction Barrier */ | |
954 | #define CPUID_8000_0008_EBX_IBPB (1U << 12) | |
623972ce BM |
955 | /* Indirect Branch Restricted Speculation */ |
956 | #define CPUID_8000_0008_EBX_IBRS (1U << 14) | |
143c30d4 MB |
957 | /* Single Thread Indirect Branch Predictors */ |
958 | #define CPUID_8000_0008_EBX_STIBP (1U << 15) | |
bb039a23 BM |
959 | /* STIBP mode has enhanced performance and may be left always on */ |
960 | #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17) | |
623972ce BM |
961 | /* Speculative Store Bypass Disable */ |
962 | #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) | |
bb039a23 BM |
963 | /* Predictive Store Forwarding Disable */ |
964 | #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) | |
1b3420e1 | 965 | |
b70eec31 BM |
966 | /* Processor ignores nested data breakpoints */ |
967 | #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0) | |
968 | /* LFENCE is always serializing */ | |
969 | #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) | |
970 | /* Null Selector Clears Base */ | |
971 | #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) | |
62a798d4 BM |
972 | /* Automatic IBRS */ |
973 | #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) | |
b70eec31 | 974 | |
0bb0b2d2 PB |
975 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) |
976 | #define CPUID_XSAVE_XSAVEC (1U << 1) | |
977 | #define CPUID_XSAVE_XGETBV1 (1U << 2) | |
978 | #define CPUID_XSAVE_XSAVES (1U << 3) | |
979 | ||
28b8e4d0 JK |
980 | #define CPUID_6_EAX_ARAT (1U << 2) |
981 | ||
303752a9 MT |
982 | /* CPUID[0x80000007].EDX flags: */ |
983 | #define CPUID_APM_INVTSC (1U << 8) | |
984 | ||
9df694ee IM |
985 | #define CPUID_VENDOR_SZ 12 |
986 | ||
c5096daf AZ |
987 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
988 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
989 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
99b88a17 | 990 | #define CPUID_VENDOR_INTEL "GenuineIntel" |
c5096daf AZ |
991 | |
992 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
b3baa152 | 993 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
c5096daf | 994 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
99b88a17 | 995 | #define CPUID_VENDOR_AMD "AuthenticAMD" |
c5096daf | 996 | |
99b88a17 | 997 | #define CPUID_VENDOR_VIA "CentaurHauls" |
b3baa152 | 998 | |
8d031cec PW |
999 | #define CPUID_VENDOR_HYGON "HygonGenuine" |
1000 | ||
18ab37ba LA |
1001 | #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ |
1002 | (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ | |
1003 | (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) | |
1004 | #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ | |
1005 | (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ | |
1006 | (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) | |
1007 | ||
2cd49cbf PM |
1008 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ |
1009 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ | |
e737b32a | 1010 | |
5232d00a RK |
1011 | /* CPUID[0xB].ECX level types */ |
1012 | #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) | |
1013 | #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) | |
1014 | #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) | |
a94e1428 | 1015 | #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) |
5232d00a | 1016 | |
d86f9636 | 1017 | /* MSR Feature Bits */ |
6c997b4a XL |
1018 | #define MSR_ARCH_CAP_RDCL_NO (1U << 0) |
1019 | #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) | |
1020 | #define MSR_ARCH_CAP_RSBA (1U << 2) | |
d86f9636 | 1021 | #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) |
6c997b4a XL |
1022 | #define MSR_ARCH_CAP_SSB_NO (1U << 4) |
1023 | #define MSR_ARCH_CAP_MDS_NO (1U << 5) | |
1024 | #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) | |
1025 | #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) | |
1026 | #define MSR_ARCH_CAP_TAA_NO (1U << 8) | |
6c43ec3b TS |
1027 | #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13) |
1028 | #define MSR_ARCH_CAP_FBSDP_NO (1U << 14) | |
1029 | #define MSR_ARCH_CAP_PSDP_NO (1U << 15) | |
22e1094c | 1030 | #define MSR_ARCH_CAP_FB_CLEAR (1U << 17) |
6c43ec3b | 1031 | #define MSR_ARCH_CAP_PBRSB_NO (1U << 24) |
d86f9636 | 1032 | |
597360c0 XL |
1033 | #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) |
1034 | ||
704798ad PB |
1035 | /* VMX MSR features */ |
1036 | #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull | |
1037 | #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) | |
1038 | #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) | |
1039 | #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) | |
1040 | #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) | |
1041 | #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) | |
0c49c918 | 1042 | #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) |
704798ad PB |
1043 | |
1044 | #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full | |
1045 | #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) | |
1046 | #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) | |
1047 | #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) | |
1048 | #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) | |
1049 | #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull | |
1050 | #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) | |
1051 | #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) | |
1052 | ||
1053 | #define MSR_VMX_EPT_EXECONLY (1ULL << 0) | |
1054 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) | |
1055 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) | |
1056 | #define MSR_VMX_EPT_UC (1ULL << 8) | |
1057 | #define MSR_VMX_EPT_WB (1ULL << 14) | |
1058 | #define MSR_VMX_EPT_2MB (1ULL << 16) | |
1059 | #define MSR_VMX_EPT_1GB (1ULL << 17) | |
1060 | #define MSR_VMX_EPT_INVEPT (1ULL << 20) | |
1061 | #define MSR_VMX_EPT_AD_BITS (1ULL << 21) | |
1062 | #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) | |
1063 | #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) | |
1064 | #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) | |
1065 | #define MSR_VMX_EPT_INVVPID (1ULL << 32) | |
1066 | #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) | |
1067 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) | |
1068 | #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) | |
1069 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) | |
1070 | ||
1071 | #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) | |
1072 | ||
1073 | ||
1074 | /* VMX controls */ | |
1075 | #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 | |
1076 | #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 | |
1077 | #define VMX_CPU_BASED_HLT_EXITING 0x00000080 | |
1078 | #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 | |
1079 | #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 | |
1080 | #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 | |
1081 | #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 | |
1082 | #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 | |
1083 | #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 | |
1084 | #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 | |
1085 | #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 | |
1086 | #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 | |
1087 | #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 | |
1088 | #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 | |
1089 | #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 | |
1090 | #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 | |
1091 | #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 | |
1092 | #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 | |
1093 | #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 | |
1094 | #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 | |
1095 | #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 | |
1096 | ||
1097 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 | |
1098 | #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 | |
1099 | #define VMX_SECONDARY_EXEC_DESC 0x00000004 | |
1100 | #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 | |
1101 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 | |
1102 | #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 | |
1103 | #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 | |
1104 | #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 | |
1105 | #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 | |
1106 | #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 | |
1107 | #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 | |
1108 | #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 | |
1109 | #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 | |
1110 | #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 | |
1111 | #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 | |
1112 | #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 | |
1113 | #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 | |
1114 | #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 | |
1115 | #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 | |
9ce8af4d | 1116 | #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 |
33cc8826 | 1117 | #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000 |
704798ad PB |
1118 | |
1119 | #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 | |
1120 | #define VMX_PIN_BASED_NMI_EXITING 0x00000008 | |
1121 | #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 | |
1122 | #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 | |
1123 | #define VMX_PIN_BASED_POSTED_INTR 0x00000080 | |
1124 | ||
1125 | #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 | |
1126 | #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 | |
1127 | #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 | |
1128 | #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 | |
1129 | #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 | |
1130 | #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 | |
1131 | #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 | |
1132 | #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 | |
1133 | #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 | |
1134 | #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 | |
1135 | #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 | |
1136 | #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 | |
52a44ad2 | 1137 | #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 |
704798ad PB |
1138 | |
1139 | #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 | |
1140 | #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 | |
1141 | #define VMX_VM_ENTRY_SMM 0x00000400 | |
1142 | #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 | |
1143 | #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 | |
1144 | #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 | |
1145 | #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 | |
1146 | #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 | |
1147 | #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 | |
1148 | #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 | |
52a44ad2 | 1149 | #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 |
704798ad | 1150 | |
2d384d7c VK |
1151 | /* Supported Hyper-V Enlightenments */ |
1152 | #define HYPERV_FEAT_RELAXED 0 | |
1153 | #define HYPERV_FEAT_VAPIC 1 | |
1154 | #define HYPERV_FEAT_TIME 2 | |
1155 | #define HYPERV_FEAT_CRASH 3 | |
1156 | #define HYPERV_FEAT_RESET 4 | |
1157 | #define HYPERV_FEAT_VPINDEX 5 | |
1158 | #define HYPERV_FEAT_RUNTIME 6 | |
1159 | #define HYPERV_FEAT_SYNIC 7 | |
1160 | #define HYPERV_FEAT_STIMER 8 | |
1161 | #define HYPERV_FEAT_FREQUENCIES 9 | |
1162 | #define HYPERV_FEAT_REENLIGHTENMENT 10 | |
1163 | #define HYPERV_FEAT_TLBFLUSH 11 | |
1164 | #define HYPERV_FEAT_EVMCS 12 | |
1165 | #define HYPERV_FEAT_IPI 13 | |
128531d9 | 1166 | #define HYPERV_FEAT_STIMER_DIRECT 14 |
e1f9a8e8 | 1167 | #define HYPERV_FEAT_AVIC 15 |
73d24074 | 1168 | #define HYPERV_FEAT_SYNDBG 16 |
869840d2 | 1169 | #define HYPERV_FEAT_MSR_BITMAP 17 |
9411e8b6 | 1170 | #define HYPERV_FEAT_XMM_INPUT 18 |
aa6bb5fa | 1171 | #define HYPERV_FEAT_TLBFLUSH_EXT 19 |
3aae0854 | 1172 | #define HYPERV_FEAT_TLBFLUSH_DIRECT 20 |
2d384d7c | 1173 | |
f701c082 VK |
1174 | #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY |
1175 | #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF | |
92067bf4 IM |
1176 | #endif |
1177 | ||
2c0262af | 1178 | #define EXCP00_DIVZ 0 |
01df040b | 1179 | #define EXCP01_DB 1 |
2c0262af FB |
1180 | #define EXCP02_NMI 2 |
1181 | #define EXCP03_INT3 3 | |
1182 | #define EXCP04_INTO 4 | |
1183 | #define EXCP05_BOUND 5 | |
1184 | #define EXCP06_ILLOP 6 | |
1185 | #define EXCP07_PREX 7 | |
1186 | #define EXCP08_DBLE 8 | |
1187 | #define EXCP09_XERR 9 | |
1188 | #define EXCP0A_TSS 10 | |
1189 | #define EXCP0B_NOSEG 11 | |
1190 | #define EXCP0C_STACK 12 | |
1191 | #define EXCP0D_GPF 13 | |
1192 | #define EXCP0E_PAGE 14 | |
1193 | #define EXCP10_COPR 16 | |
1194 | #define EXCP11_ALGN 17 | |
1195 | #define EXCP12_MCHK 18 | |
1196 | ||
62846089 RH |
1197 | #define EXCP_VMEXIT 0x100 /* only for system emulation */ |
1198 | #define EXCP_SYSCALL 0x101 /* only for user emulation */ | |
b26491b4 | 1199 | #define EXCP_VSYSCALL 0x102 /* only for user emulation */ |
d2fd1af7 | 1200 | |
00a152b4 | 1201 | /* i386-specific interrupt pending bits. */ |
5d62c43a | 1202 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
00a152b4 | 1203 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
85097db6 | 1204 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
00a152b4 RH |
1205 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
1206 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
4a92a558 PB |
1207 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 |
1208 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 | |
00a152b4 | 1209 | |
4a92a558 PB |
1210 | /* Use a clearer name for this. */ |
1211 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET | |
00a152b4 | 1212 | |
c3ce5a23 PB |
1213 | /* Instead of computing the condition codes after each x86 instruction, |
1214 | * QEMU just stores one operand (called CC_SRC), the result | |
1215 | * (called CC_DST) and the type of operation (called CC_OP). When the | |
1216 | * condition codes are needed, the condition codes can be calculated | |
1217 | * using this information. Condition codes are not generated if they | |
1218 | * are only needed for conditional branches. | |
1219 | */ | |
fee71888 | 1220 | typedef enum { |
2c0262af | 1221 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
1235fc06 | 1222 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
d36cd60e FB |
1223 | |
1224 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
1225 | CC_OP_MULW, | |
1226 | CC_OP_MULL, | |
14ce26e7 | 1227 | CC_OP_MULQ, |
2c0262af FB |
1228 | |
1229 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1230 | CC_OP_ADDW, | |
1231 | CC_OP_ADDL, | |
14ce26e7 | 1232 | CC_OP_ADDQ, |
2c0262af FB |
1233 | |
1234 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1235 | CC_OP_ADCW, | |
1236 | CC_OP_ADCL, | |
14ce26e7 | 1237 | CC_OP_ADCQ, |
2c0262af FB |
1238 | |
1239 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1240 | CC_OP_SUBW, | |
1241 | CC_OP_SUBL, | |
14ce26e7 | 1242 | CC_OP_SUBQ, |
2c0262af FB |
1243 | |
1244 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1245 | CC_OP_SBBW, | |
1246 | CC_OP_SBBL, | |
14ce26e7 | 1247 | CC_OP_SBBQ, |
2c0262af FB |
1248 | |
1249 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
1250 | CC_OP_LOGICW, | |
1251 | CC_OP_LOGICL, | |
14ce26e7 | 1252 | CC_OP_LOGICQ, |
2c0262af FB |
1253 | |
1254 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
1255 | CC_OP_INCW, | |
1256 | CC_OP_INCL, | |
14ce26e7 | 1257 | CC_OP_INCQ, |
2c0262af FB |
1258 | |
1259 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
1260 | CC_OP_DECW, | |
1261 | CC_OP_DECL, | |
14ce26e7 | 1262 | CC_OP_DECQ, |
2c0262af | 1263 | |
6b652794 | 1264 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
2c0262af FB |
1265 | CC_OP_SHLW, |
1266 | CC_OP_SHLL, | |
14ce26e7 | 1267 | CC_OP_SHLQ, |
2c0262af FB |
1268 | |
1269 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
1270 | CC_OP_SARW, | |
1271 | CC_OP_SARL, | |
14ce26e7 | 1272 | CC_OP_SARQ, |
2c0262af | 1273 | |
bc4b43dc RH |
1274 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ |
1275 | CC_OP_BMILGW, | |
1276 | CC_OP_BMILGL, | |
1277 | CC_OP_BMILGQ, | |
1278 | ||
cd7f97ca RH |
1279 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ |
1280 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ | |
1281 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ | |
1282 | ||
436ff2d2 | 1283 | CC_OP_CLR, /* Z set, all other flags clear. */ |
4885c3c4 | 1284 | CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ |
436ff2d2 | 1285 | |
2c0262af | 1286 | CC_OP_NB, |
fee71888 | 1287 | } CCOp; |
2c0262af | 1288 | |
2c0262af FB |
1289 | typedef struct SegmentCache { |
1290 | uint32_t selector; | |
14ce26e7 | 1291 | target_ulong base; |
2c0262af FB |
1292 | uint32_t limit; |
1293 | uint32_t flags; | |
1294 | } SegmentCache; | |
1295 | ||
75f107a8 RH |
1296 | typedef union MMXReg { |
1297 | uint8_t _b_MMXReg[64 / 8]; | |
1298 | uint16_t _w_MMXReg[64 / 16]; | |
1299 | uint32_t _l_MMXReg[64 / 32]; | |
1300 | uint64_t _q_MMXReg[64 / 64]; | |
1301 | float32 _s_MMXReg[64 / 32]; | |
1302 | float64 _d_MMXReg[64 / 64]; | |
1303 | } MMXReg; | |
1304 | ||
1305 | typedef union XMMReg { | |
1306 | uint64_t _q_XMMReg[128 / 64]; | |
1307 | } XMMReg; | |
1308 | ||
1309 | typedef union YMMReg { | |
1310 | uint64_t _q_YMMReg[256 / 64]; | |
1311 | XMMReg _x_YMMReg[256 / 128]; | |
1312 | } YMMReg; | |
1313 | ||
1314 | typedef union ZMMReg { | |
1315 | uint8_t _b_ZMMReg[512 / 8]; | |
1316 | uint16_t _w_ZMMReg[512 / 16]; | |
1317 | uint32_t _l_ZMMReg[512 / 32]; | |
1318 | uint64_t _q_ZMMReg[512 / 64]; | |
cf5ec664 | 1319 | float16 _h_ZMMReg[512 / 16]; |
75f107a8 RH |
1320 | float32 _s_ZMMReg[512 / 32]; |
1321 | float64 _d_ZMMReg[512 / 64]; | |
1322 | XMMReg _x_ZMMReg[512 / 128]; | |
1323 | YMMReg _y_ZMMReg[512 / 256]; | |
1324 | } ZMMReg; | |
826461bb | 1325 | |
79e9ebeb LJ |
1326 | typedef struct BNDReg { |
1327 | uint64_t lb; | |
1328 | uint64_t ub; | |
1329 | } BNDReg; | |
1330 | ||
1331 | typedef struct BNDCSReg { | |
1332 | uint64_t cfgu; | |
1333 | uint64_t sts; | |
1334 | } BNDCSReg; | |
1335 | ||
f4f1110e RH |
1336 | #define BNDCFG_ENABLE 1ULL |
1337 | #define BNDCFG_BNDPRESERVE 2ULL | |
1338 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK | |
1339 | ||
e03b5686 | 1340 | #if HOST_BIG_ENDIAN |
f23a9db6 EH |
1341 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] |
1342 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] | |
1343 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] | |
cf5ec664 | 1344 | #define ZMM_H(n) _h_ZMMReg[31 - (n)] |
f23a9db6 EH |
1345 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] |
1346 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] | |
1347 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] | |
75f107a8 RH |
1348 | #define ZMM_X(n) _x_ZMMReg[3 - (n)] |
1349 | #define ZMM_Y(n) _y_ZMMReg[1 - (n)] | |
1350 | ||
1351 | #define XMM_Q(n) _q_XMMReg[1 - (n)] | |
1352 | ||
1353 | #define YMM_Q(n) _q_YMMReg[3 - (n)] | |
1354 | #define YMM_X(n) _x_YMMReg[1 - (n)] | |
f23a9db6 EH |
1355 | |
1356 | #define MMX_B(n) _b_MMXReg[7 - (n)] | |
1357 | #define MMX_W(n) _w_MMXReg[3 - (n)] | |
1358 | #define MMX_L(n) _l_MMXReg[1 - (n)] | |
1359 | #define MMX_S(n) _s_MMXReg[1 - (n)] | |
826461bb | 1360 | #else |
f23a9db6 EH |
1361 | #define ZMM_B(n) _b_ZMMReg[n] |
1362 | #define ZMM_W(n) _w_ZMMReg[n] | |
1363 | #define ZMM_L(n) _l_ZMMReg[n] | |
cf5ec664 | 1364 | #define ZMM_H(n) _h_ZMMReg[n] |
f23a9db6 EH |
1365 | #define ZMM_S(n) _s_ZMMReg[n] |
1366 | #define ZMM_Q(n) _q_ZMMReg[n] | |
1367 | #define ZMM_D(n) _d_ZMMReg[n] | |
75f107a8 RH |
1368 | #define ZMM_X(n) _x_ZMMReg[n] |
1369 | #define ZMM_Y(n) _y_ZMMReg[n] | |
1370 | ||
1371 | #define XMM_Q(n) _q_XMMReg[n] | |
1372 | ||
1373 | #define YMM_Q(n) _q_YMMReg[n] | |
1374 | #define YMM_X(n) _x_YMMReg[n] | |
f23a9db6 EH |
1375 | |
1376 | #define MMX_B(n) _b_MMXReg[n] | |
1377 | #define MMX_W(n) _w_MMXReg[n] | |
1378 | #define MMX_L(n) _l_MMXReg[n] | |
1379 | #define MMX_S(n) _s_MMXReg[n] | |
826461bb | 1380 | #endif |
f23a9db6 | 1381 | #define MMX_Q(n) _q_MMXReg[n] |
826461bb | 1382 | |
acc68836 | 1383 | typedef union { |
c31da136 | 1384 | floatx80 d __attribute__((aligned(16))); |
acc68836 JQ |
1385 | MMXReg mmx; |
1386 | } FPReg; | |
1387 | ||
c1a54d57 JQ |
1388 | typedef struct { |
1389 | uint64_t base; | |
1390 | uint64_t mask; | |
1391 | } MTRRVar; | |
1392 | ||
5f30fa18 JK |
1393 | #define CPU_NB_REGS64 16 |
1394 | #define CPU_NB_REGS32 8 | |
1395 | ||
14ce26e7 | 1396 | #ifdef TARGET_X86_64 |
5f30fa18 | 1397 | #define CPU_NB_REGS CPU_NB_REGS64 |
14ce26e7 | 1398 | #else |
5f30fa18 | 1399 | #define CPU_NB_REGS CPU_NB_REGS32 |
14ce26e7 FB |
1400 | #endif |
1401 | ||
0d894367 PB |
1402 | #define MAX_FIXED_COUNTERS 3 |
1403 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) | |
1404 | ||
2066d095 | 1405 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 1406 | |
9aecd6f8 CP |
1407 | #define NB_OPMASK_REGS 8 |
1408 | ||
d9c84f19 IM |
1409 | /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish |
1410 | * that APIC ID hasn't been set yet | |
1411 | */ | |
1412 | #define UNASSIGNED_APIC_ID 0xFFFFFFFF | |
1413 | ||
b503717d EH |
1414 | typedef union X86LegacyXSaveArea { |
1415 | struct { | |
1416 | uint16_t fcw; | |
1417 | uint16_t fsw; | |
1418 | uint8_t ftw; | |
1419 | uint8_t reserved; | |
1420 | uint16_t fpop; | |
1421 | uint64_t fpip; | |
1422 | uint64_t fpdp; | |
1423 | uint32_t mxcsr; | |
1424 | uint32_t mxcsr_mask; | |
1425 | FPReg fpregs[8]; | |
1426 | uint8_t xmm_regs[16][16]; | |
1427 | }; | |
1428 | uint8_t data[512]; | |
1429 | } X86LegacyXSaveArea; | |
1430 | ||
1431 | typedef struct X86XSaveHeader { | |
1432 | uint64_t xstate_bv; | |
1433 | uint64_t xcomp_bv; | |
3f32bd21 RH |
1434 | uint64_t reserve0; |
1435 | uint8_t reserved[40]; | |
b503717d EH |
1436 | } X86XSaveHeader; |
1437 | ||
1438 | /* Ext. save area 2: AVX State */ | |
1439 | typedef struct XSaveAVX { | |
1440 | uint8_t ymmh[16][16]; | |
1441 | } XSaveAVX; | |
1442 | ||
1443 | /* Ext. save area 3: BNDREG */ | |
1444 | typedef struct XSaveBNDREG { | |
1445 | BNDReg bnd_regs[4]; | |
1446 | } XSaveBNDREG; | |
1447 | ||
1448 | /* Ext. save area 4: BNDCSR */ | |
1449 | typedef union XSaveBNDCSR { | |
1450 | BNDCSReg bndcsr; | |
1451 | uint8_t data[64]; | |
1452 | } XSaveBNDCSR; | |
1453 | ||
1454 | /* Ext. save area 5: Opmask */ | |
1455 | typedef struct XSaveOpmask { | |
1456 | uint64_t opmask_regs[NB_OPMASK_REGS]; | |
1457 | } XSaveOpmask; | |
1458 | ||
1459 | /* Ext. save area 6: ZMM_Hi256 */ | |
1460 | typedef struct XSaveZMM_Hi256 { | |
1461 | uint8_t zmm_hi256[16][32]; | |
1462 | } XSaveZMM_Hi256; | |
1463 | ||
1464 | /* Ext. save area 7: Hi16_ZMM */ | |
1465 | typedef struct XSaveHi16_ZMM { | |
1466 | uint8_t hi16_zmm[16][64]; | |
1467 | } XSaveHi16_ZMM; | |
1468 | ||
1469 | /* Ext. save area 9: PKRU state */ | |
1470 | typedef struct XSavePKRU { | |
1471 | uint32_t pkru; | |
1472 | uint32_t padding; | |
1473 | } XSavePKRU; | |
1474 | ||
1f16764f JL |
1475 | /* Ext. save area 17: AMX XTILECFG state */ |
1476 | typedef struct XSaveXTILECFG { | |
1477 | uint8_t xtilecfg[64]; | |
1478 | } XSaveXTILECFG; | |
1479 | ||
1480 | /* Ext. save area 18: AMX XTILEDATA state */ | |
1481 | typedef struct XSaveXTILEDATA { | |
1482 | uint8_t xtiledata[8][1024]; | |
1483 | } XSaveXTILEDATA; | |
1484 | ||
10f0abcb YW |
1485 | typedef struct { |
1486 | uint64_t from; | |
1487 | uint64_t to; | |
1488 | uint64_t info; | |
1489 | } LBREntry; | |
1490 | ||
1491 | #define ARCH_LBR_NR_ENTRIES 32 | |
1492 | ||
1493 | /* Ext. save area 19: Supervisor mode Arch LBR state */ | |
1494 | typedef struct XSavesArchLBR { | |
1495 | uint64_t lbr_ctl; | |
1496 | uint64_t lbr_depth; | |
1497 | uint64_t ler_from; | |
1498 | uint64_t ler_to; | |
1499 | uint64_t ler_info; | |
1500 | LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; | |
1501 | } XSavesArchLBR; | |
1502 | ||
b503717d | 1503 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); |
b503717d | 1504 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); |
b503717d | 1505 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); |
b503717d | 1506 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); |
b503717d | 1507 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); |
b503717d | 1508 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); |
b503717d | 1509 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); |
1f16764f JL |
1510 | QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40); |
1511 | QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000); | |
10f0abcb | 1512 | QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328); |
b503717d | 1513 | |
5aa10ab1 DE |
1514 | typedef struct ExtSaveArea { |
1515 | uint32_t feature, bits; | |
1516 | uint32_t offset, size; | |
131266b7 | 1517 | uint32_t ecx; |
5aa10ab1 DE |
1518 | } ExtSaveArea; |
1519 | ||
1f16764f | 1520 | #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) |
5aa10ab1 | 1521 | |
fea45008 | 1522 | extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; |
5aa10ab1 | 1523 | |
d362e757 JK |
1524 | typedef enum TPRAccess { |
1525 | TPR_ACCESS_READ, | |
1526 | TPR_ACCESS_WRITE, | |
1527 | } TPRAccess; | |
1528 | ||
7e3482f8 EH |
1529 | /* Cache information data structures: */ |
1530 | ||
1531 | enum CacheType { | |
5f00335a EH |
1532 | DATA_CACHE, |
1533 | INSTRUCTION_CACHE, | |
7e3482f8 EH |
1534 | UNIFIED_CACHE |
1535 | }; | |
1536 | ||
1537 | typedef struct CPUCacheInfo { | |
1538 | enum CacheType type; | |
1539 | uint8_t level; | |
1540 | /* Size in bytes */ | |
1541 | uint32_t size; | |
1542 | /* Line size, in bytes */ | |
1543 | uint16_t line_size; | |
1544 | /* | |
1545 | * Associativity. | |
1546 | * Note: representation of fully-associative caches is not implemented | |
1547 | */ | |
1548 | uint8_t associativity; | |
1549 | /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ | |
1550 | uint8_t partitions; | |
1551 | /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ | |
1552 | uint32_t sets; | |
1553 | /* | |
1554 | * Lines per tag. | |
1555 | * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. | |
1556 | * (Is this synonym to @partitions?) | |
1557 | */ | |
1558 | uint8_t lines_per_tag; | |
1559 | ||
1560 | /* Self-initializing cache */ | |
1561 | bool self_init; | |
1562 | /* | |
1563 | * WBINVD/INVD is not guaranteed to act upon lower level caches of | |
1564 | * non-originating threads sharing this cache. | |
1565 | * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] | |
1566 | */ | |
1567 | bool no_invd_sharing; | |
1568 | /* | |
1569 | * Cache is inclusive of lower cache levels. | |
1570 | * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. | |
1571 | */ | |
1572 | bool inclusive; | |
1573 | /* | |
1574 | * A complex function is used to index the cache, potentially using all | |
1575 | * address bits. CPUID[4].EDX[bit 2]. | |
1576 | */ | |
1577 | bool complex_indexing; | |
1578 | } CPUCacheInfo; | |
1579 | ||
1580 | ||
6aaeb054 | 1581 | typedef struct CPUCaches { |
a9f27ea9 EH |
1582 | CPUCacheInfo *l1d_cache; |
1583 | CPUCacheInfo *l1i_cache; | |
1584 | CPUCacheInfo *l2_cache; | |
1585 | CPUCacheInfo *l3_cache; | |
6aaeb054 | 1586 | } CPUCaches; |
7e3482f8 | 1587 | |
577f02b8 RB |
1588 | typedef struct HVFX86LazyFlags { |
1589 | target_ulong result; | |
1590 | target_ulong auxbits; | |
1591 | } HVFX86LazyFlags; | |
1592 | ||
1ea4a06a | 1593 | typedef struct CPUArchState { |
2c0262af | 1594 | /* standard registers */ |
14ce26e7 FB |
1595 | target_ulong regs[CPU_NB_REGS]; |
1596 | target_ulong eip; | |
1597 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
2c0262af FB |
1598 | flags and DF are set to zero because they are |
1599 | stored elsewhere */ | |
1600 | ||
1601 | /* emulator internal eflags handling */ | |
14ce26e7 | 1602 | target_ulong cc_dst; |
988c3eb0 RH |
1603 | target_ulong cc_src; |
1604 | target_ulong cc_src2; | |
2c0262af FB |
1605 | uint32_t cc_op; |
1606 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
db620f46 FB |
1607 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
1608 | are known at translation time. */ | |
1609 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
2c0262af | 1610 | |
9df217a3 FB |
1611 | /* segments */ |
1612 | SegmentCache segs[6]; /* selector values */ | |
1613 | SegmentCache ldt; | |
1614 | SegmentCache tr; | |
1615 | SegmentCache gdt; /* only base and limit are used */ | |
1616 | SegmentCache idt; /* only base and limit are used */ | |
1617 | ||
db620f46 | 1618 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
8f515d38 ML |
1619 | |
1620 | bool pdptrs_valid; | |
1621 | uint64_t pdptrs[4]; | |
5ee0ffaa | 1622 | int32_t a20_mask; |
9df217a3 | 1623 | |
05e7e819 PB |
1624 | BNDReg bnd_regs[4]; |
1625 | BNDCSReg bndcs_regs; | |
1626 | uint64_t msr_bndcfgs; | |
2188cc52 | 1627 | uint64_t efer; |
05e7e819 | 1628 | |
43175fa9 PB |
1629 | /* Beginning of state preserved by INIT (dummy marker). */ |
1630 | struct {} start_init_save; | |
1631 | ||
2c0262af FB |
1632 | /* FPU state */ |
1633 | unsigned int fpstt; /* top of stack index */ | |
67b8f419 | 1634 | uint16_t fpus; |
eb831623 | 1635 | uint16_t fpuc; |
2c0262af | 1636 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
acc68836 | 1637 | FPReg fpregs[8]; |
42cc8fa6 JK |
1638 | /* KVM-only so far */ |
1639 | uint16_t fpop; | |
84abdd7d ZK |
1640 | uint16_t fpcs; |
1641 | uint16_t fpds; | |
42cc8fa6 JK |
1642 | uint64_t fpip; |
1643 | uint64_t fpdp; | |
2c0262af FB |
1644 | |
1645 | /* emulator internal variables */ | |
7a0e1f41 | 1646 | float_status fp_status; |
c31da136 | 1647 | floatx80 ft0; |
3b46e624 | 1648 | |
a35f3ec7 | 1649 | float_status mmx_status; /* for 3DNow! float ops */ |
7a0e1f41 | 1650 | float_status sse_status; |
664e0f19 | 1651 | uint32_t mxcsr; |
75f107a8 RH |
1652 | ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16); |
1653 | ZMMReg xmm_t0 QEMU_ALIGNED(16); | |
664e0f19 | 1654 | MMXReg mmx_t0; |
14ce26e7 | 1655 | |
9aecd6f8 | 1656 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
e56dd3c7 JL |
1657 | #ifdef TARGET_X86_64 |
1658 | uint8_t xtilecfg[64]; | |
1659 | uint8_t xtiledata[8192]; | |
1660 | #endif | |
9aecd6f8 | 1661 | |
2c0262af FB |
1662 | /* sysenter registers */ |
1663 | uint32_t sysenter_cs; | |
2436b61a AZ |
1664 | target_ulong sysenter_esp; |
1665 | target_ulong sysenter_eip; | |
8d9bfc2b | 1666 | uint64_t star; |
0573fbfc | 1667 | |
5cc1d1e6 | 1668 | uint64_t vm_hsave; |
0573fbfc | 1669 | |
14ce26e7 | 1670 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
1671 | target_ulong lstar; |
1672 | target_ulong cstar; | |
1673 | target_ulong fmask; | |
1674 | target_ulong kernelgsbase; | |
1675 | #endif | |
58fe2f10 | 1676 | |
f28558d3 | 1677 | uint64_t tsc_adjust; |
aa82ba54 | 1678 | uint64_t tsc_deadline; |
7616f1c2 PB |
1679 | uint64_t tsc_aux; |
1680 | ||
1681 | uint64_t xcr0; | |
7ba1e619 | 1682 | |
18559232 | 1683 | uint64_t mcg_status; |
21e87c46 | 1684 | uint64_t msr_ia32_misc_enable; |
0779caeb | 1685 | uint64_t msr_ia32_feature_control; |
db888065 | 1686 | uint64_t msr_ia32_sgxlepubkeyhash[4]; |
18559232 | 1687 | |
0d894367 PB |
1688 | uint64_t msr_fixed_ctr_ctrl; |
1689 | uint64_t msr_global_ctrl; | |
1690 | uint64_t msr_global_status; | |
1691 | uint64_t msr_global_ovf_ctrl; | |
1692 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; | |
1693 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; | |
1694 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; | |
43175fa9 PB |
1695 | |
1696 | uint64_t pat; | |
1697 | uint32_t smbase; | |
e13713db | 1698 | uint64_t msr_smi_count; |
43175fa9 | 1699 | |
7616f1c2 | 1700 | uint32_t pkru; |
e7e7bdab | 1701 | uint32_t pkrs; |
2a9758c5 | 1702 | uint32_t tsx_ctrl; |
7616f1c2 | 1703 | |
a33a2cfe | 1704 | uint64_t spec_ctrl; |
cabf9862 | 1705 | uint64_t amd_tsc_scale_msr; |
cfeea0c0 | 1706 | uint64_t virt_ssbd; |
a33a2cfe | 1707 | |
43175fa9 PB |
1708 | /* End of state preserved by INIT (dummy marker). */ |
1709 | struct {} end_init_save; | |
1710 | ||
1711 | uint64_t system_time_msr; | |
1712 | uint64_t wall_clock_msr; | |
1713 | uint64_t steal_time_msr; | |
1714 | uint64_t async_pf_en_msr; | |
db5daafa | 1715 | uint64_t async_pf_int_msr; |
43175fa9 | 1716 | uint64_t pv_eoi_en_msr; |
d645e132 | 1717 | uint64_t poll_control_msr; |
43175fa9 | 1718 | |
da1cc323 | 1719 | /* Partition-wide HV MSRs, will be updated only on the first vcpu */ |
1c90ef26 VR |
1720 | uint64_t msr_hv_hypercall; |
1721 | uint64_t msr_hv_guest_os_id; | |
48a5f3bc | 1722 | uint64_t msr_hv_tsc; |
73d24074 JD |
1723 | uint64_t msr_hv_syndbg_control; |
1724 | uint64_t msr_hv_syndbg_status; | |
1725 | uint64_t msr_hv_syndbg_send_page; | |
1726 | uint64_t msr_hv_syndbg_recv_page; | |
1727 | uint64_t msr_hv_syndbg_pending_page; | |
1728 | uint64_t msr_hv_syndbg_options; | |
da1cc323 EY |
1729 | |
1730 | /* Per-VCPU HV MSRs */ | |
1731 | uint64_t msr_hv_vapic; | |
5e953812 | 1732 | uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; |
46eb8f98 | 1733 | uint64_t msr_hv_runtime; |
866eea9a | 1734 | uint64_t msr_hv_synic_control; |
866eea9a AS |
1735 | uint64_t msr_hv_synic_evt_page; |
1736 | uint64_t msr_hv_synic_msg_page; | |
5e953812 RK |
1737 | uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; |
1738 | uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; | |
1739 | uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; | |
ba6a4fd9 VK |
1740 | uint64_t msr_hv_reenlightenment_control; |
1741 | uint64_t msr_hv_tsc_emulation_control; | |
1742 | uint64_t msr_hv_tsc_emulation_status; | |
18559232 | 1743 | |
b77146e9 CP |
1744 | uint64_t msr_rtit_ctrl; |
1745 | uint64_t msr_rtit_status; | |
1746 | uint64_t msr_rtit_output_base; | |
1747 | uint64_t msr_rtit_output_mask; | |
1748 | uint64_t msr_rtit_cr3_match; | |
1749 | uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; | |
1750 | ||
cdec2b75 ZG |
1751 | /* Per-VCPU XFD MSRs */ |
1752 | uint64_t msr_xfd; | |
1753 | uint64_t msr_xfd_err; | |
1754 | ||
12703d4e YW |
1755 | /* Per-VCPU Arch LBR MSRs */ |
1756 | uint64_t msr_lbr_ctl; | |
1757 | uint64_t msr_lbr_depth; | |
1758 | LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; | |
1759 | ||
2c0262af | 1760 | /* exception/interrupt handling */ |
2c0262af FB |
1761 | int error_code; |
1762 | int exception_is_int; | |
826461bb | 1763 | target_ulong exception_next_eip; |
d0052339 | 1764 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ |
01df040b | 1765 | union { |
f0c3c505 | 1766 | struct CPUBreakpoint *cpu_breakpoint[4]; |
ff4700b0 | 1767 | struct CPUWatchpoint *cpu_watchpoint[4]; |
01df040b | 1768 | }; /* break/watchpoints for dr[0..3] */ |
678dde13 | 1769 | int old_exception; /* exception in flight */ |
2c0262af | 1770 | |
43175fa9 PB |
1771 | uint64_t vm_vmcb; |
1772 | uint64_t tsc_offset; | |
1773 | uint64_t intercept; | |
1774 | uint16_t intercept_cr_read; | |
1775 | uint16_t intercept_cr_write; | |
1776 | uint16_t intercept_dr_read; | |
1777 | uint16_t intercept_dr_write; | |
1778 | uint32_t intercept_exceptions; | |
fe441054 JK |
1779 | uint64_t nested_cr3; |
1780 | uint32_t nested_pg_mode; | |
43175fa9 | 1781 | uint8_t v_tpr; |
e3126a5c | 1782 | uint32_t int_ctl; |
43175fa9 | 1783 | |
d8f771d9 JK |
1784 | /* KVM states, automatically cleared on reset */ |
1785 | uint8_t nmi_injected; | |
1786 | uint8_t nmi_pending; | |
1787 | ||
fe441054 JK |
1788 | uintptr_t retaddr; |
1789 | ||
1f5c00cf AB |
1790 | /* Fields up to this point are cleared by a CPU reset */ |
1791 | struct {} end_reset_fields; | |
1792 | ||
e8b5fae5 | 1793 | /* Fields after this point are preserved across CPU reset. */ |
ebda377f | 1794 | |
14ce26e7 | 1795 | /* processor features (e.g. for CPUID insn) */ |
80db491d JL |
1796 | /* Minimum cpuid leaf 7 value */ |
1797 | uint32_t cpuid_level_func7; | |
1798 | /* Actual cpuid leaf 7 value */ | |
1799 | uint32_t cpuid_min_level_func7; | |
c39c0edf EH |
1800 | /* Minimum level/xlevel/xlevel2, based on CPU model + features */ |
1801 | uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; | |
1802 | /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ | |
1803 | uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; | |
1804 | /* Actual level/xlevel/xlevel2 value: */ | |
1805 | uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; | |
14ce26e7 FB |
1806 | uint32_t cpuid_vendor1; |
1807 | uint32_t cpuid_vendor2; | |
1808 | uint32_t cpuid_vendor3; | |
1809 | uint32_t cpuid_version; | |
0514ef2f | 1810 | FeatureWordArray features; |
d4a606b3 EH |
1811 | /* Features that were explicitly enabled/disabled */ |
1812 | FeatureWordArray user_features; | |
8d9bfc2b | 1813 | uint32_t cpuid_model[12]; |
a9f27ea9 EH |
1814 | /* Cache information for CPUID. When legacy-cache=on, the cache data |
1815 | * on each CPUID leaf will be different, because we keep compatibility | |
1816 | * with old QEMU versions. | |
1817 | */ | |
1818 | CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; | |
3b46e624 | 1819 | |
165d9b82 AL |
1820 | /* MTRRs */ |
1821 | uint64_t mtrr_fixed[11]; | |
1822 | uint64_t mtrr_deftype; | |
d8b5c67b | 1823 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; |
165d9b82 | 1824 | |
7ba1e619 | 1825 | /* For KVM */ |
f8d926e9 | 1826 | uint32_t mp_state; |
fd13f23b | 1827 | int32_t exception_nr; |
0e607a80 | 1828 | int32_t interrupt_injected; |
a0fb002c | 1829 | uint8_t soft_interrupt; |
fd13f23b LA |
1830 | uint8_t exception_pending; |
1831 | uint8_t exception_injected; | |
a0fb002c | 1832 | uint8_t has_error_code; |
fd13f23b LA |
1833 | uint8_t exception_has_payload; |
1834 | uint64_t exception_payload; | |
12f89a39 | 1835 | uint8_t triple_fault_pending; |
c97d6d2c | 1836 | uint32_t ins_len; |
a0fb002c | 1837 | uint32_t sipi_vector; |
b8cc45d6 | 1838 | bool tsc_valid; |
06ef227e | 1839 | int64_t tsc_khz; |
36f96c4b | 1840 | int64_t user_tsc_khz; /* for sanity check only */ |
73b994f6 | 1841 | uint64_t apic_bus_freq; |
5286c366 | 1842 | uint64_t tsc; |
5b8063c4 LA |
1843 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) |
1844 | void *xsave_buf; | |
c0198c5f | 1845 | uint32_t xsave_buf_len; |
5b8063c4 | 1846 | #endif |
ebbfef2f LA |
1847 | #if defined(CONFIG_KVM) |
1848 | struct kvm_nested_state *nested_state; | |
27d4075d DW |
1849 | MemoryRegion *xen_vcpu_info_mr; |
1850 | void *xen_vcpu_info_hva; | |
c345104c JM |
1851 | uint64_t xen_vcpu_info_gpa; |
1852 | uint64_t xen_vcpu_info_default_gpa; | |
f0689302 | 1853 | uint64_t xen_vcpu_time_info_gpa; |
5092db87 | 1854 | uint64_t xen_vcpu_runstate_gpa; |
105b47fd | 1855 | uint8_t xen_vcpu_callback_vector; |
ddf0fd9a | 1856 | bool xen_callback_asserted; |
c723d4c1 DW |
1857 | uint16_t xen_virq[XEN_NR_VIRQS]; |
1858 | uint64_t xen_singleshot_timer_ns; | |
b746a779 JM |
1859 | QEMUTimer *xen_singleshot_timer; |
1860 | uint64_t xen_periodic_timer_period; | |
1861 | QEMUTimer *xen_periodic_timer; | |
1862 | QemuMutex xen_timers_lock; | |
ebbfef2f | 1863 | #endif |
c97d6d2c | 1864 | #if defined(CONFIG_HVF) |
577f02b8 | 1865 | HVFX86LazyFlags hvf_lflags; |
fe76b09c | 1866 | void *hvf_mmio_buf; |
c97d6d2c | 1867 | #endif |
fabacc0f | 1868 | |
ac6c4120 | 1869 | uint64_t mcg_cap; |
ac6c4120 | 1870 | uint64_t mcg_ctl; |
87f8b626 | 1871 | uint64_t mcg_ext_ctl; |
ac6c4120 | 1872 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
7616f1c2 | 1873 | uint64_t xstate_bv; |
5a2d0e57 AJ |
1874 | |
1875 | /* vmstate */ | |
1876 | uint16_t fpus_vmstate; | |
1877 | uint16_t fptag_vmstate; | |
1878 | uint16_t fpregs_format_vmstate; | |
f1665b21 | 1879 | |
18cd2c17 | 1880 | uint64_t xss; |
65087997 | 1881 | uint32_t umwait; |
d362e757 JK |
1882 | |
1883 | TPRAccess tpr_access_type; | |
c26ae610 LX |
1884 | |
1885 | unsigned nr_dies; | |
2c0262af FB |
1886 | } CPUX86State; |
1887 | ||
d71b62a1 EH |
1888 | struct kvm_msrs; |
1889 | ||
4da6f8d9 PB |
1890 | /** |
1891 | * X86CPU: | |
1892 | * @env: #CPUX86State | |
1893 | * @migratable: If set, only migratable flags will be accepted when "enforce" | |
1894 | * mode is used, and only migratable flags will be included in the "host" | |
1895 | * CPU model. | |
1896 | * | |
1897 | * An x86 CPU. | |
1898 | */ | |
b36e239e | 1899 | struct ArchCPU { |
4da6f8d9 | 1900 | CPUState parent_obj; |
4da6f8d9 PB |
1901 | |
1902 | CPUX86State env; | |
2a693142 | 1903 | VMChangeStateEntry *vmsentry; |
4da6f8d9 | 1904 | |
4e45aff3 PB |
1905 | uint64_t ucode_rev; |
1906 | ||
4f2beda4 | 1907 | uint32_t hyperv_spinlock_attempts; |
08856771 | 1908 | char *hyperv_vendor; |
9b4cf107 | 1909 | bool hyperv_synic_kvm_only; |
2d384d7c | 1910 | uint64_t hyperv_features; |
e48ddcc6 | 1911 | bool hyperv_passthrough; |
30d6ff66 | 1912 | OnOffAuto hyperv_no_nonarch_cs; |
08856771 | 1913 | uint32_t hyperv_vendor_id[3]; |
735db465 | 1914 | uint32_t hyperv_interface_id[4]; |
23eb5d03 | 1915 | uint32_t hyperv_limits[3]; |
70367f09 | 1916 | bool hyperv_enforce_cpuid; |
af7228b8 VK |
1917 | uint32_t hyperv_ver_id_build; |
1918 | uint16_t hyperv_ver_id_major; | |
1919 | uint16_t hyperv_ver_id_minor; | |
1920 | uint32_t hyperv_ver_id_sp; | |
1921 | uint8_t hyperv_ver_id_sb; | |
1922 | uint32_t hyperv_ver_id_sn; | |
2d384d7c | 1923 | |
4da6f8d9 PB |
1924 | bool check_cpuid; |
1925 | bool enforce_cpuid; | |
dac1deae EH |
1926 | /* |
1927 | * Force features to be enabled even if the host doesn't support them. | |
1928 | * This is dangerous and should be done only for testing CPUID | |
1929 | * compatibility. | |
1930 | */ | |
1931 | bool force_features; | |
4da6f8d9 | 1932 | bool expose_kvm; |
1ce36bfe | 1933 | bool expose_tcg; |
4da6f8d9 | 1934 | bool migratable; |
990e0be2 | 1935 | bool migrate_smi_count; |
44bd8e53 | 1936 | bool max_features; /* Enable all supported features automatically */ |
d9c84f19 | 1937 | uint32_t apic_id; |
4da6f8d9 | 1938 | |
9954a158 PDJ |
1939 | /* Enables publishing of TSC increment and Local APIC bus frequencies to |
1940 | * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ | |
1941 | bool vmware_cpuid_freq; | |
1942 | ||
4da6f8d9 PB |
1943 | /* if true the CPUID code directly forward host cache leaves to the guest */ |
1944 | bool cache_info_passthrough; | |
1945 | ||
2266d443 MT |
1946 | /* if true the CPUID code directly forwards |
1947 | * host monitor/mwait leaves to the guest */ | |
1948 | struct { | |
1949 | uint32_t eax; | |
1950 | uint32_t ebx; | |
1951 | uint32_t ecx; | |
1952 | uint32_t edx; | |
1953 | } mwait; | |
1954 | ||
4da6f8d9 | 1955 | /* Features that were filtered out because of missing host capabilities */ |
f69ecddb | 1956 | FeatureWordArray filtered_features; |
4da6f8d9 PB |
1957 | |
1958 | /* Enable PMU CPUID bits. This can't be enabled by default yet because | |
1959 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID | |
1960 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel | |
1961 | * capabilities) directly to the guest. | |
1962 | */ | |
1963 | bool enable_pmu; | |
1964 | ||
f06d8a18 YW |
1965 | /* |
1966 | * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR. | |
1967 | * This can't be initialized with a default because it doesn't have | |
1968 | * stable ABI support yet. It is only allowed to pass all LBR_FMT bits | |
1969 | * returned by kvm_arch_get_supported_msr_feature()(which depends on both | |
1970 | * host CPU and kernel capabilities) to the guest. | |
1971 | */ | |
1972 | uint64_t lbr_fmt; | |
1973 | ||
87f8b626 AR |
1974 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is |
1975 | * disabled by default to avoid breaking migration between QEMU with | |
1976 | * different LMCE configurations. | |
1977 | */ | |
1978 | bool enable_lmce; | |
1979 | ||
14c985cf LM |
1980 | /* Compatibility bits for old machine types. |
1981 | * If true present virtual l3 cache for VM, the vcpus in the same virtual | |
1982 | * socket share an virtual l3 cache. | |
1983 | */ | |
1984 | bool enable_l3_cache; | |
1985 | ||
ab8f992e BM |
1986 | /* Compatibility bits for old machine types. |
1987 | * If true present the old cache topology information | |
1988 | */ | |
1989 | bool legacy_cache; | |
1990 | ||
5232d00a RK |
1991 | /* Compatibility bits for old machine types: */ |
1992 | bool enable_cpuid_0xb; | |
1993 | ||
c39c0edf EH |
1994 | /* Enable auto level-increase for all CPUID leaves */ |
1995 | bool full_cpuid_auto_level; | |
1996 | ||
a7a0da84 MR |
1997 | /* Only advertise CPUID leaves defined by the vendor */ |
1998 | bool vendor_cpuid_only; | |
1999 | ||
f24c3a79 LK |
2000 | /* Enable auto level-increase for Intel Processor Trace leave */ |
2001 | bool intel_pt_auto_level; | |
2002 | ||
fcc35e7c DDAG |
2003 | /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ |
2004 | bool fill_mtrr_mask; | |
2005 | ||
11f6fee5 DDAG |
2006 | /* if true override the phys_bits value with a value read from the host */ |
2007 | bool host_phys_bits; | |
2008 | ||
258fe08b EH |
2009 | /* if set, limit maximum value for phys_bits when host_phys_bits is true */ |
2010 | uint8_t host_phys_bits_limit; | |
2011 | ||
fc3a1fd7 DDAG |
2012 | /* Stop SMI delivery for migration compatibility with old machines */ |
2013 | bool kvm_no_smi_migration; | |
2014 | ||
988f7b8b VK |
2015 | /* Forcefully disable KVM PV features not exposed in guest CPUIDs */ |
2016 | bool kvm_pv_enforce_cpuid; | |
2017 | ||
af45907a DDAG |
2018 | /* Number of physical address bits supported */ |
2019 | uint32_t phys_bits; | |
2020 | ||
4da6f8d9 PB |
2021 | /* in order to simplify APIC support, we leave this pointer to the |
2022 | user */ | |
2023 | struct DeviceState *apic_state; | |
2024 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; | |
2025 | Notifier machine_done; | |
d71b62a1 EH |
2026 | |
2027 | struct kvm_msrs *kvm_msr_buf; | |
d89c2b8b | 2028 | |
15f8b142 | 2029 | int32_t node_id; /* NUMA node this CPU belongs to */ |
d89c2b8b | 2030 | int32_t socket_id; |
176d2cda | 2031 | int32_t die_id; |
d89c2b8b IM |
2032 | int32_t core_id; |
2033 | int32_t thread_id; | |
6c69dfb6 GA |
2034 | |
2035 | int32_t hv_max_vps; | |
f66b8a83 JM |
2036 | |
2037 | bool xen_vapic; | |
4da6f8d9 PB |
2038 | }; |
2039 | ||
4da6f8d9 PB |
2040 | |
2041 | #ifndef CONFIG_USER_ONLY | |
ac701a4f | 2042 | extern const VMStateDescription vmstate_x86_cpu; |
4da6f8d9 PB |
2043 | #endif |
2044 | ||
92d5f1a4 | 2045 | int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); |
4da6f8d9 PB |
2046 | |
2047 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1af0006a | 2048 | int cpuid, DumpState *s); |
4da6f8d9 | 2049 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, |
1af0006a | 2050 | int cpuid, DumpState *s); |
4da6f8d9 | 2051 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
1af0006a | 2052 | DumpState *s); |
4da6f8d9 | 2053 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
1af0006a | 2054 | DumpState *s); |
4da6f8d9 | 2055 | |
8a5b974b | 2056 | bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
4da6f8d9 PB |
2057 | Error **errp); |
2058 | ||
90c84c56 | 2059 | void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); |
4da6f8d9 | 2060 | |
a010bdbe | 2061 | int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
4da6f8d9 PB |
2062 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
2063 | ||
0442428a | 2064 | void x86_cpu_list(void); |
317ac620 | 2065 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
b5ec5ce0 | 2066 | |
76d0042b | 2067 | #ifndef CONFIG_USER_ONLY |
6d2d454a PMD |
2068 | hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
2069 | MemTxAttrs *attrs); | |
d720b93d | 2070 | int cpu_get_pic_interrupt(CPUX86State *s); |
7ce08865 | 2071 | |
bad5cfcd | 2072 | /* MS-DOS compatibility mode FPU exception support */ |
6f529b75 | 2073 | void x86_register_ferr_irq(qemu_irq irq); |
83a3d9c7 | 2074 | void fpu_check_raise_ferr_irq(CPUX86State *s); |
bf13bfab | 2075 | void cpu_set_ignne(void); |
83a3d9c7 | 2076 | void cpu_clear_ignne(void); |
7ce08865 | 2077 | #endif |
83a3d9c7 | 2078 | |
5e76d84e PB |
2079 | /* mpx_helper.c */ |
2080 | void cpu_sync_bndcs_hflags(CPUX86State *env); | |
2c0262af FB |
2081 | |
2082 | /* this function must always be used to load data in the segment | |
2083 | cache: it synchronizes the hflags with the segment cache values */ | |
5fafdf24 | 2084 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
c117e5b1 | 2085 | X86Seg seg_reg, unsigned int selector, |
8988ae89 | 2086 | target_ulong base, |
5fafdf24 | 2087 | unsigned int limit, |
2c0262af FB |
2088 | unsigned int flags) |
2089 | { | |
2090 | SegmentCache *sc; | |
2091 | unsigned int new_hflags; | |
3b46e624 | 2092 | |
2c0262af FB |
2093 | sc = &env->segs[seg_reg]; |
2094 | sc->selector = selector; | |
2095 | sc->base = base; | |
2096 | sc->limit = limit; | |
2097 | sc->flags = flags; | |
2098 | ||
2099 | /* update the hidden flags */ | |
14ce26e7 FB |
2100 | { |
2101 | if (seg_reg == R_CS) { | |
2102 | #ifdef TARGET_X86_64 | |
2103 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
2104 | /* long mode */ | |
2105 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
2106 | env->hflags &= ~(HF_ADDSEG_MASK); | |
5fafdf24 | 2107 | } else |
14ce26e7 FB |
2108 | #endif |
2109 | { | |
2110 | /* legacy / compatibility case */ | |
2111 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
2112 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
2113 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
2114 | new_hflags; | |
2115 | } | |
7125c937 PB |
2116 | } |
2117 | if (seg_reg == R_SS) { | |
2118 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; | |
7848c8d1 KC |
2119 | #if HF_CPL_MASK != 3 |
2120 | #error HF_CPL_MASK is hardcoded | |
2121 | #endif | |
2122 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; | |
5e76d84e PB |
2123 | /* Possibly switch between BNDCFGS and BNDCFGU */ |
2124 | cpu_sync_bndcs_hflags(env); | |
14ce26e7 FB |
2125 | } |
2126 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
2127 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
2128 | if (env->hflags & HF_CS64_MASK) { | |
2129 | /* zero base assumed for DS, ES and SS in long mode */ | |
5fafdf24 | 2130 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
735a8fd3 FB |
2131 | (env->eflags & VM_MASK) || |
2132 | !(env->hflags & HF_CS32_MASK)) { | |
14ce26e7 FB |
2133 | /* XXX: try to avoid this test. The problem comes from the |
2134 | fact that is real mode or vm86 mode we only modify the | |
2135 | 'base' and 'selector' fields of the segment cache to go | |
2136 | faster. A solution may be to force addseg to one in | |
2137 | translate-i386.c. */ | |
2138 | new_hflags |= HF_ADDSEG_MASK; | |
2139 | } else { | |
5fafdf24 | 2140 | new_hflags |= ((env->segs[R_DS].base | |
735a8fd3 | 2141 | env->segs[R_ES].base | |
5fafdf24 | 2142 | env->segs[R_SS].base) != 0) << |
14ce26e7 FB |
2143 | HF_ADDSEG_SHIFT; |
2144 | } | |
5fafdf24 | 2145 | env->hflags = (env->hflags & |
14ce26e7 | 2146 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
2c0262af | 2147 | } |
2c0262af FB |
2148 | } |
2149 | ||
e9f9d6b1 | 2150 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
e6a33e45 | 2151 | uint8_t sipi_vector) |
0e26b7b8 | 2152 | { |
259186a7 | 2153 | CPUState *cs = CPU(cpu); |
e9f9d6b1 AF |
2154 | CPUX86State *env = &cpu->env; |
2155 | ||
0e26b7b8 BS |
2156 | env->eip = 0; |
2157 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
2158 | sipi_vector << 12, | |
2159 | env->segs[R_CS].limit, | |
2160 | env->segs[R_CS].flags); | |
259186a7 | 2161 | cs->halted = 0; |
0e26b7b8 BS |
2162 | } |
2163 | ||
84273177 JK |
2164 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
2165 | target_ulong *base, unsigned int *limit, | |
2166 | unsigned int *flags); | |
2167 | ||
d9957a8b | 2168 | /* op_helper.c */ |
1f1af9fd | 2169 | /* used for debug or cpu save/restore */ |
1f1af9fd | 2170 | |
d9957a8b | 2171 | /* cpu-exec.c */ |
2c0262af FB |
2172 | /* the following helpers are only usable in user mode simulation as |
2173 | they can trigger unexpected exceptions */ | |
c117e5b1 | 2174 | void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); |
6f12a2a6 FB |
2175 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
2176 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
1c1df019 PK |
2177 | void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); |
2178 | void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); | |
5d245678 PB |
2179 | void cpu_x86_xsave(CPUX86State *s, target_ulong ptr); |
2180 | void cpu_x86_xrstor(CPUX86State *s, target_ulong ptr); | |
2c0262af | 2181 | |
f4f1110e | 2182 | /* cpu.c */ |
f5cc5a5c CF |
2183 | void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, |
2184 | uint32_t vendor2, uint32_t vendor3); | |
2185 | typedef struct PropValue { | |
2186 | const char *prop, *value; | |
2187 | } PropValue; | |
2188 | void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); | |
2189 | ||
ec19444a MS |
2190 | void x86_cpu_after_reset(X86CPU *cpu); |
2191 | ||
97afb47e LL |
2192 | uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); |
2193 | ||
f5cc5a5c | 2194 | /* cpu.c other functions (cpuid) */ |
c6dc6f63 AP |
2195 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
2196 | uint32_t *eax, uint32_t *ebx, | |
2197 | uint32_t *ecx, uint32_t *edx); | |
0e26b7b8 | 2198 | void cpu_clear_apic_feature(CPUX86State *env); |
bb44e0d1 JK |
2199 | void host_cpuid(uint32_t function, uint32_t count, |
2200 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
c6dc6f63 | 2201 | |
d9957a8b | 2202 | /* helper.c */ |
cc36a7a2 | 2203 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); |
608db8db | 2204 | void cpu_sync_avx_hflag(CPUX86State *env); |
2c0262af | 2205 | |
b216aa6c | 2206 | #ifndef CONFIG_USER_ONLY |
f8c45c65 PB |
2207 | static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) |
2208 | { | |
2209 | return !!attrs.secure; | |
2210 | } | |
2211 | ||
2212 | static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) | |
2213 | { | |
2214 | return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); | |
2215 | } | |
2216 | ||
63087289 CF |
2217 | /* |
2218 | * load efer and update the corresponding hflags. XXX: do consistency | |
2219 | * checks with cpuid bits? | |
2220 | */ | |
2221 | void cpu_load_efer(CPUX86State *env, uint64_t val); | |
b216aa6c PB |
2222 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); |
2223 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); | |
2224 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); | |
2225 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); | |
2226 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); | |
2227 | void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); | |
2228 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
2229 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
2230 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); | |
2231 | #endif | |
2232 | ||
d9957a8b BS |
2233 | /* will be suppressed */ |
2234 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
2235 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
2236 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
93d00d0f | 2237 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); |
d9957a8b | 2238 | |
d9957a8b | 2239 | /* hw/pc.c */ |
d9957a8b | 2240 | uint64_t cpu_get_tsc(CPUX86State *env); |
6fd805e1 | 2241 | |
311ca98d IM |
2242 | #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU |
2243 | #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) | |
0dacec87 | 2244 | #define CPU_RESOLVING_TYPE TYPE_X86_CPU |
311ca98d IM |
2245 | |
2246 | #ifdef TARGET_X86_64 | |
2247 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") | |
2248 | #else | |
2249 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") | |
2250 | #endif | |
2251 | ||
e916cbf8 | 2252 | #define cpu_list x86_cpu_list |
9467d44c | 2253 | |
6ebbf390 | 2254 | /* MMU modes definitions */ |
8a201bd4 | 2255 | #define MMU_KSMAP_IDX 0 |
a9321a4d | 2256 | #define MMU_USER_IDX 1 |
43773ed3 | 2257 | #define MMU_KNOSMAP_IDX 2 |
98281984 RH |
2258 | #define MMU_NESTED_IDX 3 |
2259 | #define MMU_PHYS_IDX 4 | |
2260 | ||
97ed5ccd | 2261 | static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) |
6ebbf390 | 2262 | { |
a9321a4d | 2263 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
f57584dc | 2264 | (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) |
8a201bd4 PB |
2265 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; |
2266 | } | |
2267 | ||
2268 | static inline int cpu_mmu_index_kernel(CPUX86State *env) | |
2269 | { | |
2270 | return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : | |
2271 | ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) | |
2272 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; | |
6ebbf390 JM |
2273 | } |
2274 | ||
988c3eb0 RH |
2275 | #define CC_DST (env->cc_dst) |
2276 | #define CC_SRC (env->cc_src) | |
2277 | #define CC_SRC2 (env->cc_src2) | |
2278 | #define CC_OP (env->cc_op) | |
f081c76c | 2279 | |
022c62cb | 2280 | #include "exec/cpu-all.h" |
0573fbfc TS |
2281 | #include "svm.h" |
2282 | ||
0e26b7b8 | 2283 | #if !defined(CONFIG_USER_ONLY) |
0d09e41a | 2284 | #include "hw/i386/apic.h" |
0e26b7b8 BS |
2285 | #endif |
2286 | ||
bb5de525 AJ |
2287 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, |
2288 | uint64_t *cs_base, uint32_t *flags) | |
6b917547 AL |
2289 | { |
2290 | *cs_base = env->segs[R_CS].base; | |
2291 | *pc = *cs_base + env->eip; | |
a2397807 | 2292 | *flags = env->hflags | |
a9321a4d | 2293 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
6b917547 AL |
2294 | } |
2295 | ||
232fc23b | 2296 | void do_cpu_init(X86CPU *cpu); |
2fa11da0 | 2297 | |
747461c7 JK |
2298 | #define MCE_INJECT_BROADCAST 1 |
2299 | #define MCE_INJECT_UNCOND_AO 2 | |
2300 | ||
8c5cf3b6 | 2301 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
316378e4 | 2302 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
747461c7 | 2303 | uint64_t misc, int flags); |
2fa11da0 | 2304 | |
5918fffb BS |
2305 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); |
2306 | ||
2307 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
2308 | { | |
79c664f6 YZ |
2309 | uint32_t eflags = env->eflags; |
2310 | if (tcg_enabled()) { | |
2311 | eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); | |
2312 | } | |
2313 | return eflags; | |
5918fffb BS |
2314 | } |
2315 | ||
f794aa4a PB |
2316 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) |
2317 | { | |
2318 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); | |
2319 | } | |
2320 | ||
c8bc83a4 PB |
2321 | static inline int32_t x86_get_a20_mask(CPUX86State *env) |
2322 | { | |
2323 | if (env->hflags & HF_SMM_MASK) { | |
2324 | return -1; | |
2325 | } else { | |
2326 | return env->a20_mask; | |
2327 | } | |
2328 | } | |
2329 | ||
18ab37ba LA |
2330 | static inline bool cpu_has_vmx(CPUX86State *env) |
2331 | { | |
2332 | return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; | |
2333 | } | |
2334 | ||
b16c0e20 PB |
2335 | static inline bool cpu_has_svm(CPUX86State *env) |
2336 | { | |
2337 | return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; | |
2338 | } | |
2339 | ||
79a197ab LA |
2340 | /* |
2341 | * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. | |
2342 | * Since it was set, CR4.VMXE must remain set as long as vCPU is in | |
2343 | * VMX operation. This is because CR4.VMXE is one of the bits set | |
2344 | * in MSR_IA32_VMX_CR4_FIXED1. | |
2345 | * | |
2346 | * There is one exception to above statement when vCPU enters SMM mode. | |
2347 | * When a vCPU enters SMM mode, it temporarily exit VMX operation and | |
2348 | * may also reset CR4.VMXE during execution in SMM mode. | |
2349 | * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation | |
2350 | * and CR4.VMXE is restored to it's original value of being set. | |
2351 | * | |
2352 | * Therefore, when vCPU is not in SMM mode, we can infer whether | |
2353 | * VMX is being used by examining CR4.VMXE. Otherwise, we cannot | |
2354 | * know for certain. | |
2355 | */ | |
2356 | static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) | |
2357 | { | |
2358 | return cpu_has_vmx(env) && | |
2359 | ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); | |
2360 | } | |
2361 | ||
616a89ea PB |
2362 | /* excp_helper.c */ |
2363 | int get_pg_mode(CPUX86State *env); | |
2364 | ||
4e47e39a | 2365 | /* fpu_helper.c */ |
1d8ad165 YZ |
2366 | void update_fp_status(CPUX86State *env); |
2367 | void update_mxcsr_status(CPUX86State *env); | |
418b0f93 | 2368 | void update_mxcsr_from_sse_status(CPUX86State *env); |
1d8ad165 YZ |
2369 | |
2370 | static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) | |
2371 | { | |
2372 | env->mxcsr = mxcsr; | |
2373 | if (tcg_enabled()) { | |
2374 | update_mxcsr_status(env); | |
2375 | } | |
2376 | } | |
2377 | ||
2378 | static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) | |
2379 | { | |
2380 | env->fpuc = fpuc; | |
2381 | if (tcg_enabled()) { | |
2382 | update_fp_status(env); | |
2383 | } | |
2384 | } | |
4e47e39a | 2385 | |
6bada5e8 | 2386 | /* svm_helper.c */ |
27bd3216 RH |
2387 | #ifdef CONFIG_USER_ONLY |
2388 | static inline void | |
2389 | cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
2390 | uint64_t param, uintptr_t retaddr) | |
2391 | { /* no-op */ } | |
813c6459 LL |
2392 | static inline bool |
2393 | cpu_svm_has_intercept(CPUX86State *env, uint32_t type) | |
2394 | { return false; } | |
27bd3216 | 2395 | #else |
6bada5e8 | 2396 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, |
65c9d60a | 2397 | uint64_t param, uintptr_t retaddr); |
813c6459 | 2398 | bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); |
27bd3216 RH |
2399 | #endif |
2400 | ||
d613f8cc | 2401 | /* apic.c */ |
317ac620 | 2402 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
d613f8cc PB |
2403 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
2404 | TPRAccess access); | |
2405 | ||
dcafd1ef EH |
2406 | /* Special values for X86CPUVersion: */ |
2407 | ||
2408 | /* Resolve to latest CPU version */ | |
2409 | #define CPU_VERSION_LATEST -1 | |
2410 | ||
0788a56b EH |
2411 | /* |
2412 | * Resolve to version defined by current machine type. | |
2413 | * See x86_cpu_set_default_version() | |
2414 | */ | |
2415 | #define CPU_VERSION_AUTO -2 | |
2416 | ||
dcafd1ef EH |
2417 | /* Don't resolve to any versioned CPU models, like old QEMU versions */ |
2418 | #define CPU_VERSION_LEGACY 0 | |
2419 | ||
2420 | typedef int X86CPUVersion; | |
2421 | ||
0788a56b EH |
2422 | /* |
2423 | * Set default CPU model version for CPU models having | |
2424 | * version == CPU_VERSION_AUTO. | |
2425 | */ | |
2426 | void x86_cpu_set_default_version(X86CPUVersion version); | |
2427 | ||
b5c6a3c1 PMD |
2428 | #ifndef CONFIG_USER_ONLY |
2429 | ||
3b8484c5 PMD |
2430 | void do_cpu_sipi(X86CPU *cpu); |
2431 | ||
dab86234 | 2432 | #define APIC_DEFAULT_ADDRESS 0xfee00000 |
baaeda08 | 2433 | #define APIC_SPACE_SIZE 0x100000 |
dab86234 | 2434 | |
0c36af8c | 2435 | /* cpu-dump.c */ |
d3fd9e4b | 2436 | void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); |
1f871d49 | 2437 | |
b5c6a3c1 PMD |
2438 | #endif |
2439 | ||
d613f8cc PB |
2440 | /* cpu.c */ |
2441 | bool cpu_is_bsp(X86CPU *cpu); | |
2442 | ||
c0198c5f DE |
2443 | void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); |
2444 | void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); | |
5d245678 | 2445 | uint32_t xsave_area_size(uint64_t mask, bool compacted); |
35b1b927 TW |
2446 | void x86_update_hflags(CPUX86State* env); |
2447 | ||
2d384d7c VK |
2448 | static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) |
2449 | { | |
2450 | return !!(cpu->hyperv_features & BIT(feat)); | |
2451 | } | |
2452 | ||
213ff024 LL |
2453 | static inline uint64_t cr4_reserved_bits(CPUX86State *env) |
2454 | { | |
2455 | uint64_t reserved_bits = CR4_RESERVED_MASK; | |
2456 | if (!env->features[FEAT_XSAVE]) { | |
2457 | reserved_bits |= CR4_OSXSAVE_MASK; | |
2458 | } | |
2459 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { | |
2460 | reserved_bits |= CR4_SMEP_MASK; | |
2461 | } | |
2462 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { | |
2463 | reserved_bits |= CR4_SMAP_MASK; | |
2464 | } | |
2465 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { | |
2466 | reserved_bits |= CR4_FSGSBASE_MASK; | |
2467 | } | |
2468 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { | |
2469 | reserved_bits |= CR4_PKE_MASK; | |
2470 | } | |
2471 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { | |
2472 | reserved_bits |= CR4_LA57_MASK; | |
2473 | } | |
2474 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { | |
2475 | reserved_bits |= CR4_UMIP_MASK; | |
2476 | } | |
2477 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { | |
2478 | reserved_bits |= CR4_PKS_MASK; | |
2479 | } | |
2480 | return reserved_bits; | |
2481 | } | |
2482 | ||
7760bb06 LL |
2483 | static inline bool ctl_has_irq(CPUX86State *env) |
2484 | { | |
2485 | uint32_t int_prio; | |
2486 | uint32_t tpr; | |
2487 | ||
2488 | int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; | |
2489 | tpr = env->int_ctl & V_TPR_MASK; | |
2490 | ||
2491 | if (env->int_ctl & V_IGN_TPR_MASK) { | |
2492 | return (env->int_ctl & V_IRQ_MASK); | |
2493 | } | |
2494 | ||
2495 | return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); | |
2496 | } | |
2497 | ||
b26491b4 RH |
2498 | #if defined(TARGET_X86_64) && \ |
2499 | defined(CONFIG_USER_ONLY) && \ | |
2500 | defined(CONFIG_LINUX) | |
2501 | # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) | |
2502 | #endif | |
2503 | ||
07f5a258 | 2504 | #endif /* I386_CPU_H */ |