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Commit | Line | Data |
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2c0262af FB |
1 | /* |
2 | * i386 virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 18 | */ |
07f5a258 MA |
19 | |
20 | #ifndef I386_CPU_H | |
21 | #define I386_CPU_H | |
2c0262af | 22 | |
9a78eead | 23 | #include "qemu-common.h" |
4da6f8d9 | 24 | #include "cpu-qom.h" |
f2a53c9e | 25 | #include "standard-headers/asm-x86/hyperv.h" |
14ce26e7 FB |
26 | |
27 | #ifdef TARGET_X86_64 | |
28 | #define TARGET_LONG_BITS 64 | |
29 | #else | |
3cf1e035 | 30 | #define TARGET_LONG_BITS 32 |
14ce26e7 | 31 | #endif |
3cf1e035 | 32 | |
72c1701f AB |
33 | /* The x86 has a strong memory model with some store-after-load re-ordering */ |
34 | #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) | |
35 | ||
5b9efc39 PD |
36 | /* Maximum instruction code size */ |
37 | #define TARGET_MAX_INSN_SIZE 16 | |
38 | ||
d720b93d FB |
39 | /* support for self modifying code even if the modified instruction is |
40 | close to the modifying instruction */ | |
41 | #define TARGET_HAS_PRECISE_SMC | |
42 | ||
9042c0e2 | 43 | #ifdef TARGET_X86_64 |
a5e8788f | 44 | #define I386_ELF_MACHINE EM_X86_64 |
4ab23a91 | 45 | #define ELF_MACHINE_UNAME "x86_64" |
9042c0e2 | 46 | #else |
a5e8788f | 47 | #define I386_ELF_MACHINE EM_386 |
4ab23a91 | 48 | #define ELF_MACHINE_UNAME "i686" |
9042c0e2 TS |
49 | #endif |
50 | ||
9349b4f9 | 51 | #define CPUArchState struct CPUX86State |
c2764719 | 52 | |
022c62cb | 53 | #include "exec/cpu-defs.h" |
2c0262af | 54 | |
79c664f6 | 55 | #ifdef CONFIG_TCG |
6b4c305c | 56 | #include "fpu/softfloat.h" |
79c664f6 | 57 | #endif |
7a0e1f41 | 58 | |
2c0262af FB |
59 | #define R_EAX 0 |
60 | #define R_ECX 1 | |
61 | #define R_EDX 2 | |
62 | #define R_EBX 3 | |
63 | #define R_ESP 4 | |
64 | #define R_EBP 5 | |
65 | #define R_ESI 6 | |
66 | #define R_EDI 7 | |
67 | ||
68 | #define R_AL 0 | |
69 | #define R_CL 1 | |
70 | #define R_DL 2 | |
71 | #define R_BL 3 | |
72 | #define R_AH 4 | |
73 | #define R_CH 5 | |
74 | #define R_DH 6 | |
75 | #define R_BH 7 | |
76 | ||
77 | #define R_ES 0 | |
78 | #define R_CS 1 | |
79 | #define R_SS 2 | |
80 | #define R_DS 3 | |
81 | #define R_FS 4 | |
82 | #define R_GS 5 | |
83 | ||
84 | /* segment descriptor fields */ | |
85 | #define DESC_G_MASK (1 << 23) | |
86 | #define DESC_B_SHIFT 22 | |
87 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
14ce26e7 FB |
88 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
89 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
2c0262af FB |
90 | #define DESC_AVL_MASK (1 << 20) |
91 | #define DESC_P_MASK (1 << 15) | |
92 | #define DESC_DPL_SHIFT 13 | |
a3867ed2 | 93 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
2c0262af FB |
94 | #define DESC_S_MASK (1 << 12) |
95 | #define DESC_TYPE_SHIFT 8 | |
a3867ed2 | 96 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
2c0262af FB |
97 | #define DESC_A_MASK (1 << 8) |
98 | ||
e670b89e FB |
99 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
100 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
101 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
2c0262af | 102 | |
e670b89e FB |
103 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
104 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
105 | ||
106 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
2c0262af FB |
107 | |
108 | /* eflags masks */ | |
e4a09c96 PB |
109 | #define CC_C 0x0001 |
110 | #define CC_P 0x0004 | |
111 | #define CC_A 0x0010 | |
112 | #define CC_Z 0x0040 | |
2c0262af FB |
113 | #define CC_S 0x0080 |
114 | #define CC_O 0x0800 | |
115 | ||
116 | #define TF_SHIFT 8 | |
117 | #define IOPL_SHIFT 12 | |
118 | #define VM_SHIFT 17 | |
119 | ||
e4a09c96 PB |
120 | #define TF_MASK 0x00000100 |
121 | #define IF_MASK 0x00000200 | |
122 | #define DF_MASK 0x00000400 | |
123 | #define IOPL_MASK 0x00003000 | |
124 | #define NT_MASK 0x00004000 | |
125 | #define RF_MASK 0x00010000 | |
126 | #define VM_MASK 0x00020000 | |
127 | #define AC_MASK 0x00040000 | |
2c0262af FB |
128 | #define VIF_MASK 0x00080000 |
129 | #define VIP_MASK 0x00100000 | |
130 | #define ID_MASK 0x00200000 | |
131 | ||
aa1f17c1 | 132 | /* hidden flags - used internally by qemu to represent additional cpu |
7848c8d1 KC |
133 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We |
134 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit | |
135 | positions to ease oring with eflags. */ | |
2c0262af FB |
136 | /* current cpl */ |
137 | #define HF_CPL_SHIFT 0 | |
2c0262af FB |
138 | /* true if hardware interrupts must be disabled for next instruction */ |
139 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
140 | /* 16 or 32 segments */ | |
141 | #define HF_CS32_SHIFT 4 | |
142 | #define HF_SS32_SHIFT 5 | |
dc196a57 | 143 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
2c0262af | 144 | #define HF_ADDSEG_SHIFT 6 |
65262d57 FB |
145 | /* copy of CR0.PE (protected mode) */ |
146 | #define HF_PE_SHIFT 7 | |
147 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
7eee2a50 FB |
148 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
149 | #define HF_EM_SHIFT 10 | |
150 | #define HF_TS_SHIFT 11 | |
65262d57 | 151 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
14ce26e7 FB |
152 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
153 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
a2397807 | 154 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
65262d57 | 155 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
a9321a4d | 156 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
3b21e03e | 157 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
db620f46 FB |
158 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
159 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ | |
a2397807 | 160 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
a9321a4d | 161 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
5223a942 | 162 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ |
f4f1110e RH |
163 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ |
164 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ | |
2c0262af FB |
165 | |
166 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
2c0262af FB |
167 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
168 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
169 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
170 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
65262d57 | 171 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
58fe2f10 | 172 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
7eee2a50 FB |
173 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
174 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
175 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
0650f1ab | 176 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
14ce26e7 FB |
177 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
178 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
a2397807 | 179 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
0650f1ab | 180 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
a9321a4d | 181 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
3b21e03e | 182 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
872929aa FB |
183 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
184 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) | |
a2397807 | 185 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
a9321a4d | 186 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
5223a942 | 187 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) |
f4f1110e RH |
188 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) |
189 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) | |
2c0262af | 190 | |
db620f46 FB |
191 | /* hflags2 */ |
192 | ||
9982f74b PB |
193 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
194 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
195 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
196 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
197 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ | |
f4f1110e | 198 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ |
9982f74b PB |
199 | |
200 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
201 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
202 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
203 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
204 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) | |
f4f1110e | 205 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) |
db620f46 | 206 | |
0650f1ab AL |
207 | #define CR0_PE_SHIFT 0 |
208 | #define CR0_MP_SHIFT 1 | |
209 | ||
2cd49cbf PM |
210 | #define CR0_PE_MASK (1U << 0) |
211 | #define CR0_MP_MASK (1U << 1) | |
212 | #define CR0_EM_MASK (1U << 2) | |
213 | #define CR0_TS_MASK (1U << 3) | |
214 | #define CR0_ET_MASK (1U << 4) | |
215 | #define CR0_NE_MASK (1U << 5) | |
216 | #define CR0_WP_MASK (1U << 16) | |
217 | #define CR0_AM_MASK (1U << 18) | |
218 | #define CR0_PG_MASK (1U << 31) | |
219 | ||
220 | #define CR4_VME_MASK (1U << 0) | |
221 | #define CR4_PVI_MASK (1U << 1) | |
222 | #define CR4_TSD_MASK (1U << 2) | |
223 | #define CR4_DE_MASK (1U << 3) | |
224 | #define CR4_PSE_MASK (1U << 4) | |
225 | #define CR4_PAE_MASK (1U << 5) | |
226 | #define CR4_MCE_MASK (1U << 6) | |
227 | #define CR4_PGE_MASK (1U << 7) | |
228 | #define CR4_PCE_MASK (1U << 8) | |
0650f1ab | 229 | #define CR4_OSFXSR_SHIFT 9 |
2cd49cbf PM |
230 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) |
231 | #define CR4_OSXMMEXCPT_MASK (1U << 10) | |
6c7c3c21 | 232 | #define CR4_LA57_MASK (1U << 12) |
2cd49cbf PM |
233 | #define CR4_VMXE_MASK (1U << 13) |
234 | #define CR4_SMXE_MASK (1U << 14) | |
235 | #define CR4_FSGSBASE_MASK (1U << 16) | |
236 | #define CR4_PCIDE_MASK (1U << 17) | |
237 | #define CR4_OSXSAVE_MASK (1U << 18) | |
238 | #define CR4_SMEP_MASK (1U << 20) | |
239 | #define CR4_SMAP_MASK (1U << 21) | |
0f70ed47 | 240 | #define CR4_PKE_MASK (1U << 22) |
2c0262af | 241 | |
01df040b AL |
242 | #define DR6_BD (1 << 13) |
243 | #define DR6_BS (1 << 14) | |
244 | #define DR6_BT (1 << 15) | |
245 | #define DR6_FIXED_1 0xffff0ff0 | |
246 | ||
247 | #define DR7_GD (1 << 13) | |
248 | #define DR7_TYPE_SHIFT 16 | |
249 | #define DR7_LEN_SHIFT 18 | |
250 | #define DR7_FIXED_1 0x00000400 | |
93d00d0f | 251 | #define DR7_GLOBAL_BP_MASK 0xaa |
428065ce LG |
252 | #define DR7_LOCAL_BP_MASK 0x55 |
253 | #define DR7_MAX_BP 4 | |
254 | #define DR7_TYPE_BP_INST 0x0 | |
255 | #define DR7_TYPE_DATA_WR 0x1 | |
256 | #define DR7_TYPE_IO_RW 0x2 | |
257 | #define DR7_TYPE_DATA_RW 0x3 | |
01df040b | 258 | |
e4a09c96 PB |
259 | #define PG_PRESENT_BIT 0 |
260 | #define PG_RW_BIT 1 | |
261 | #define PG_USER_BIT 2 | |
262 | #define PG_PWT_BIT 3 | |
263 | #define PG_PCD_BIT 4 | |
264 | #define PG_ACCESSED_BIT 5 | |
265 | #define PG_DIRTY_BIT 6 | |
266 | #define PG_PSE_BIT 7 | |
267 | #define PG_GLOBAL_BIT 8 | |
eaad03e4 | 268 | #define PG_PSE_PAT_BIT 12 |
0f70ed47 | 269 | #define PG_PKRU_BIT 59 |
e4a09c96 | 270 | #define PG_NX_BIT 63 |
2c0262af FB |
271 | |
272 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
e4a09c96 PB |
273 | #define PG_RW_MASK (1 << PG_RW_BIT) |
274 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
275 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
276 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
2c0262af | 277 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
e4a09c96 PB |
278 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
279 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
280 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
eaad03e4 | 281 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) |
e8f6d00c PB |
282 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL |
283 | #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) | |
3f2cbf0d | 284 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
0f70ed47 PB |
285 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) |
286 | #define PG_NX_MASK (1ULL << PG_NX_BIT) | |
2c0262af FB |
287 | |
288 | #define PG_ERROR_W_BIT 1 | |
289 | ||
290 | #define PG_ERROR_P_MASK 0x01 | |
291 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
292 | #define PG_ERROR_U_MASK 0x04 | |
293 | #define PG_ERROR_RSVD_MASK 0x08 | |
5cf38396 | 294 | #define PG_ERROR_I_D_MASK 0x10 |
0f70ed47 | 295 | #define PG_ERROR_PK_MASK 0x20 |
2c0262af | 296 | |
e4a09c96 PB |
297 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
298 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
87f8b626 | 299 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ |
79c4f6b0 | 300 | |
e4a09c96 PB |
301 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
302 | #define MCE_BANKS_DEF 10 | |
79c4f6b0 | 303 | |
2590f15b EH |
304 | #define MCG_CAP_BANKS_MASK 0xff |
305 | ||
e4a09c96 PB |
306 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
307 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
308 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
87f8b626 AR |
309 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ |
310 | ||
311 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ | |
79c4f6b0 | 312 | |
e4a09c96 PB |
313 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
314 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
315 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
316 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
317 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
318 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
319 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
320 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
321 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
c0532a76 MT |
322 | |
323 | /* MISC register defines */ | |
e4a09c96 PB |
324 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
325 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
326 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
327 | #define MCM_ADDR_MEM 3 /* memory address */ | |
328 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
79c4f6b0 | 329 | |
0650f1ab | 330 | #define MSR_IA32_TSC 0x10 |
2c0262af FB |
331 | #define MSR_IA32_APICBASE 0x1b |
332 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
333 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
33d7a288 | 334 | #define MSR_IA32_APICBASE_EXTD (1 << 10) |
458cf469 | 335 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) |
0779caeb | 336 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
f28558d3 | 337 | #define MSR_TSC_ADJUST 0x0000003b |
aa82ba54 | 338 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
2c0262af | 339 | |
217f1b4a HZ |
340 | #define FEATURE_CONTROL_LOCKED (1<<0) |
341 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) | |
342 | #define FEATURE_CONTROL_LMCE (1<<20) | |
343 | ||
0d894367 PB |
344 | #define MSR_P6_PERFCTR0 0xc1 |
345 | ||
fc12d72e | 346 | #define MSR_IA32_SMBASE 0x9e |
e4a09c96 PB |
347 | #define MSR_MTRRcap 0xfe |
348 | #define MSR_MTRRcap_VCNT 8 | |
349 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
350 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
dd5e3b17 | 351 | |
2c0262af FB |
352 | #define MSR_IA32_SYSENTER_CS 0x174 |
353 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
354 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
355 | ||
8f091a59 FB |
356 | #define MSR_MCG_CAP 0x179 |
357 | #define MSR_MCG_STATUS 0x17a | |
358 | #define MSR_MCG_CTL 0x17b | |
87f8b626 | 359 | #define MSR_MCG_EXT_CTL 0x4d0 |
8f091a59 | 360 | |
0d894367 PB |
361 | #define MSR_P6_EVNTSEL0 0x186 |
362 | ||
e737b32a AZ |
363 | #define MSR_IA32_PERF_STATUS 0x198 |
364 | ||
e4a09c96 | 365 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
21e87c46 AK |
366 | /* Indicates good rep/movs microcode on some processors: */ |
367 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
368 | ||
e4a09c96 PB |
369 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
370 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
371 | ||
d1ae67f6 AW |
372 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) |
373 | ||
e4a09c96 PB |
374 | #define MSR_MTRRfix64K_00000 0x250 |
375 | #define MSR_MTRRfix16K_80000 0x258 | |
376 | #define MSR_MTRRfix16K_A0000 0x259 | |
377 | #define MSR_MTRRfix4K_C0000 0x268 | |
378 | #define MSR_MTRRfix4K_C8000 0x269 | |
379 | #define MSR_MTRRfix4K_D0000 0x26a | |
380 | #define MSR_MTRRfix4K_D8000 0x26b | |
381 | #define MSR_MTRRfix4K_E0000 0x26c | |
382 | #define MSR_MTRRfix4K_E8000 0x26d | |
383 | #define MSR_MTRRfix4K_F0000 0x26e | |
384 | #define MSR_MTRRfix4K_F8000 0x26f | |
165d9b82 | 385 | |
8f091a59 FB |
386 | #define MSR_PAT 0x277 |
387 | ||
e4a09c96 | 388 | #define MSR_MTRRdefType 0x2ff |
165d9b82 | 389 | |
0d894367 PB |
390 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 |
391 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | |
392 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | |
393 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | |
394 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | |
395 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | |
396 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | |
165d9b82 | 397 | |
e4a09c96 PB |
398 | #define MSR_MC0_CTL 0x400 |
399 | #define MSR_MC0_STATUS 0x401 | |
400 | #define MSR_MC0_ADDR 0x402 | |
401 | #define MSR_MC0_MISC 0x403 | |
79c4f6b0 | 402 | |
14ce26e7 FB |
403 | #define MSR_EFER 0xc0000080 |
404 | ||
405 | #define MSR_EFER_SCE (1 << 0) | |
406 | #define MSR_EFER_LME (1 << 8) | |
407 | #define MSR_EFER_LMA (1 << 10) | |
408 | #define MSR_EFER_NXE (1 << 11) | |
872929aa | 409 | #define MSR_EFER_SVME (1 << 12) |
14ce26e7 FB |
410 | #define MSR_EFER_FFXSR (1 << 14) |
411 | ||
412 | #define MSR_STAR 0xc0000081 | |
413 | #define MSR_LSTAR 0xc0000082 | |
414 | #define MSR_CSTAR 0xc0000083 | |
415 | #define MSR_FMASK 0xc0000084 | |
416 | #define MSR_FSBASE 0xc0000100 | |
417 | #define MSR_GSBASE 0xc0000101 | |
418 | #define MSR_KERNELGSBASE 0xc0000102 | |
1b050077 | 419 | #define MSR_TSC_AUX 0xc0000103 |
14ce26e7 | 420 | |
0573fbfc TS |
421 | #define MSR_VM_HSAVE_PA 0xc0010117 |
422 | ||
79e9ebeb | 423 | #define MSR_IA32_BNDCFGS 0x00000d90 |
18cd2c17 | 424 | #define MSR_IA32_XSS 0x00000da0 |
79e9ebeb | 425 | |
cfc3b074 PB |
426 | #define XSTATE_FP_BIT 0 |
427 | #define XSTATE_SSE_BIT 1 | |
428 | #define XSTATE_YMM_BIT 2 | |
429 | #define XSTATE_BNDREGS_BIT 3 | |
430 | #define XSTATE_BNDCSR_BIT 4 | |
431 | #define XSTATE_OPMASK_BIT 5 | |
432 | #define XSTATE_ZMM_Hi256_BIT 6 | |
433 | #define XSTATE_Hi16_ZMM_BIT 7 | |
434 | #define XSTATE_PKRU_BIT 9 | |
435 | ||
436 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) | |
437 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) | |
438 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) | |
439 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) | |
440 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) | |
441 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) | |
442 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) | |
443 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) | |
444 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) | |
c74f41bb | 445 | |
5ef57876 EH |
446 | /* CPUID feature words */ |
447 | typedef enum FeatureWord { | |
448 | FEAT_1_EDX, /* CPUID[1].EDX */ | |
449 | FEAT_1_ECX, /* CPUID[1].ECX */ | |
450 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ | |
f74eefe0 | 451 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ |
95ea69fb | 452 | FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ |
5ef57876 EH |
453 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
454 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ | |
303752a9 | 455 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ |
5ef57876 EH |
456 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
457 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ | |
c35bd19a EY |
458 | FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ |
459 | FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ | |
460 | FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ | |
5ef57876 | 461 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
0bb0b2d2 | 462 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ |
28b8e4d0 | 463 | FEAT_6_EAX, /* CPUID[6].EAX */ |
96193c22 EH |
464 | FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ |
465 | FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ | |
5ef57876 EH |
466 | FEATURE_WORDS, |
467 | } FeatureWord; | |
468 | ||
469 | typedef uint32_t FeatureWordArray[FEATURE_WORDS]; | |
470 | ||
14ce26e7 | 471 | /* cpuid_features bits */ |
2cd49cbf PM |
472 | #define CPUID_FP87 (1U << 0) |
473 | #define CPUID_VME (1U << 1) | |
474 | #define CPUID_DE (1U << 2) | |
475 | #define CPUID_PSE (1U << 3) | |
476 | #define CPUID_TSC (1U << 4) | |
477 | #define CPUID_MSR (1U << 5) | |
478 | #define CPUID_PAE (1U << 6) | |
479 | #define CPUID_MCE (1U << 7) | |
480 | #define CPUID_CX8 (1U << 8) | |
481 | #define CPUID_APIC (1U << 9) | |
482 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ | |
483 | #define CPUID_MTRR (1U << 12) | |
484 | #define CPUID_PGE (1U << 13) | |
485 | #define CPUID_MCA (1U << 14) | |
486 | #define CPUID_CMOV (1U << 15) | |
487 | #define CPUID_PAT (1U << 16) | |
488 | #define CPUID_PSE36 (1U << 17) | |
489 | #define CPUID_PN (1U << 18) | |
490 | #define CPUID_CLFLUSH (1U << 19) | |
491 | #define CPUID_DTS (1U << 21) | |
492 | #define CPUID_ACPI (1U << 22) | |
493 | #define CPUID_MMX (1U << 23) | |
494 | #define CPUID_FXSR (1U << 24) | |
495 | #define CPUID_SSE (1U << 25) | |
496 | #define CPUID_SSE2 (1U << 26) | |
497 | #define CPUID_SS (1U << 27) | |
498 | #define CPUID_HT (1U << 28) | |
499 | #define CPUID_TM (1U << 29) | |
500 | #define CPUID_IA64 (1U << 30) | |
501 | #define CPUID_PBE (1U << 31) | |
502 | ||
503 | #define CPUID_EXT_SSE3 (1U << 0) | |
504 | #define CPUID_EXT_PCLMULQDQ (1U << 1) | |
505 | #define CPUID_EXT_DTES64 (1U << 2) | |
506 | #define CPUID_EXT_MONITOR (1U << 3) | |
507 | #define CPUID_EXT_DSCPL (1U << 4) | |
508 | #define CPUID_EXT_VMX (1U << 5) | |
509 | #define CPUID_EXT_SMX (1U << 6) | |
510 | #define CPUID_EXT_EST (1U << 7) | |
511 | #define CPUID_EXT_TM2 (1U << 8) | |
512 | #define CPUID_EXT_SSSE3 (1U << 9) | |
513 | #define CPUID_EXT_CID (1U << 10) | |
514 | #define CPUID_EXT_FMA (1U << 12) | |
515 | #define CPUID_EXT_CX16 (1U << 13) | |
516 | #define CPUID_EXT_XTPR (1U << 14) | |
517 | #define CPUID_EXT_PDCM (1U << 15) | |
518 | #define CPUID_EXT_PCID (1U << 17) | |
519 | #define CPUID_EXT_DCA (1U << 18) | |
520 | #define CPUID_EXT_SSE41 (1U << 19) | |
521 | #define CPUID_EXT_SSE42 (1U << 20) | |
522 | #define CPUID_EXT_X2APIC (1U << 21) | |
523 | #define CPUID_EXT_MOVBE (1U << 22) | |
524 | #define CPUID_EXT_POPCNT (1U << 23) | |
525 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) | |
526 | #define CPUID_EXT_AES (1U << 25) | |
527 | #define CPUID_EXT_XSAVE (1U << 26) | |
528 | #define CPUID_EXT_OSXSAVE (1U << 27) | |
529 | #define CPUID_EXT_AVX (1U << 28) | |
530 | #define CPUID_EXT_F16C (1U << 29) | |
531 | #define CPUID_EXT_RDRAND (1U << 30) | |
532 | #define CPUID_EXT_HYPERVISOR (1U << 31) | |
533 | ||
534 | #define CPUID_EXT2_FPU (1U << 0) | |
535 | #define CPUID_EXT2_VME (1U << 1) | |
536 | #define CPUID_EXT2_DE (1U << 2) | |
537 | #define CPUID_EXT2_PSE (1U << 3) | |
538 | #define CPUID_EXT2_TSC (1U << 4) | |
539 | #define CPUID_EXT2_MSR (1U << 5) | |
540 | #define CPUID_EXT2_PAE (1U << 6) | |
541 | #define CPUID_EXT2_MCE (1U << 7) | |
542 | #define CPUID_EXT2_CX8 (1U << 8) | |
543 | #define CPUID_EXT2_APIC (1U << 9) | |
544 | #define CPUID_EXT2_SYSCALL (1U << 11) | |
545 | #define CPUID_EXT2_MTRR (1U << 12) | |
546 | #define CPUID_EXT2_PGE (1U << 13) | |
547 | #define CPUID_EXT2_MCA (1U << 14) | |
548 | #define CPUID_EXT2_CMOV (1U << 15) | |
549 | #define CPUID_EXT2_PAT (1U << 16) | |
550 | #define CPUID_EXT2_PSE36 (1U << 17) | |
551 | #define CPUID_EXT2_MP (1U << 19) | |
552 | #define CPUID_EXT2_NX (1U << 20) | |
553 | #define CPUID_EXT2_MMXEXT (1U << 22) | |
554 | #define CPUID_EXT2_MMX (1U << 23) | |
555 | #define CPUID_EXT2_FXSR (1U << 24) | |
556 | #define CPUID_EXT2_FFXSR (1U << 25) | |
557 | #define CPUID_EXT2_PDPE1GB (1U << 26) | |
558 | #define CPUID_EXT2_RDTSCP (1U << 27) | |
559 | #define CPUID_EXT2_LM (1U << 29) | |
560 | #define CPUID_EXT2_3DNOWEXT (1U << 30) | |
561 | #define CPUID_EXT2_3DNOW (1U << 31) | |
9df217a3 | 562 | |
8fad4b44 EH |
563 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ |
564 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ | |
565 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
566 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
567 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
568 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
569 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
570 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
571 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
572 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
573 | ||
2cd49cbf PM |
574 | #define CPUID_EXT3_LAHF_LM (1U << 0) |
575 | #define CPUID_EXT3_CMP_LEG (1U << 1) | |
576 | #define CPUID_EXT3_SVM (1U << 2) | |
577 | #define CPUID_EXT3_EXTAPIC (1U << 3) | |
578 | #define CPUID_EXT3_CR8LEG (1U << 4) | |
579 | #define CPUID_EXT3_ABM (1U << 5) | |
580 | #define CPUID_EXT3_SSE4A (1U << 6) | |
581 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) | |
582 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) | |
583 | #define CPUID_EXT3_OSVW (1U << 9) | |
584 | #define CPUID_EXT3_IBS (1U << 10) | |
585 | #define CPUID_EXT3_XOP (1U << 11) | |
586 | #define CPUID_EXT3_SKINIT (1U << 12) | |
587 | #define CPUID_EXT3_WDT (1U << 13) | |
588 | #define CPUID_EXT3_LWP (1U << 15) | |
589 | #define CPUID_EXT3_FMA4 (1U << 16) | |
590 | #define CPUID_EXT3_TCE (1U << 17) | |
591 | #define CPUID_EXT3_NODEID (1U << 19) | |
592 | #define CPUID_EXT3_TBM (1U << 21) | |
593 | #define CPUID_EXT3_TOPOEXT (1U << 22) | |
594 | #define CPUID_EXT3_PERFCORE (1U << 23) | |
595 | #define CPUID_EXT3_PERFNB (1U << 24) | |
596 | ||
597 | #define CPUID_SVM_NPT (1U << 0) | |
598 | #define CPUID_SVM_LBRV (1U << 1) | |
599 | #define CPUID_SVM_SVMLOCK (1U << 2) | |
600 | #define CPUID_SVM_NRIPSAVE (1U << 3) | |
601 | #define CPUID_SVM_TSCSCALE (1U << 4) | |
602 | #define CPUID_SVM_VMCBCLEAN (1U << 5) | |
603 | #define CPUID_SVM_FLUSHASID (1U << 6) | |
604 | #define CPUID_SVM_DECODEASSIST (1U << 7) | |
605 | #define CPUID_SVM_PAUSEFILTER (1U << 10) | |
606 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) | |
607 | ||
608 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) | |
609 | #define CPUID_7_0_EBX_BMI1 (1U << 3) | |
610 | #define CPUID_7_0_EBX_HLE (1U << 4) | |
611 | #define CPUID_7_0_EBX_AVX2 (1U << 5) | |
612 | #define CPUID_7_0_EBX_SMEP (1U << 7) | |
613 | #define CPUID_7_0_EBX_BMI2 (1U << 8) | |
614 | #define CPUID_7_0_EBX_ERMS (1U << 9) | |
615 | #define CPUID_7_0_EBX_INVPCID (1U << 10) | |
616 | #define CPUID_7_0_EBX_RTM (1U << 11) | |
617 | #define CPUID_7_0_EBX_MPX (1U << 14) | |
9aecd6f8 | 618 | #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ |
cc728d14 | 619 | #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ |
2cd49cbf PM |
620 | #define CPUID_7_0_EBX_RDSEED (1U << 18) |
621 | #define CPUID_7_0_EBX_ADX (1U << 19) | |
622 | #define CPUID_7_0_EBX_SMAP (1U << 20) | |
cc728d14 | 623 | #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ |
f7fda280 XG |
624 | #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ |
625 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ | |
626 | #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ | |
9aecd6f8 CP |
627 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ |
628 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ | |
629 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ | |
638cbd45 | 630 | #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ |
cc728d14 LK |
631 | #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ |
632 | #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ | |
a9321a4d | 633 | |
cc728d14 | 634 | #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ |
c2f193b5 | 635 | #define CPUID_7_0_ECX_UMIP (1U << 2) |
f74eefe0 HH |
636 | #define CPUID_7_0_ECX_PKU (1U << 3) |
637 | #define CPUID_7_0_ECX_OSPKE (1U << 4) | |
f7754377 | 638 | #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ |
6c7c3c21 | 639 | #define CPUID_7_0_ECX_LA57 (1U << 16) |
c2f193b5 | 640 | #define CPUID_7_0_ECX_RDPID (1U << 22) |
f74eefe0 | 641 | |
95ea69fb LK |
642 | #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ |
643 | #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ | |
644 | ||
0bb0b2d2 PB |
645 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) |
646 | #define CPUID_XSAVE_XSAVEC (1U << 1) | |
647 | #define CPUID_XSAVE_XGETBV1 (1U << 2) | |
648 | #define CPUID_XSAVE_XSAVES (1U << 3) | |
649 | ||
28b8e4d0 JK |
650 | #define CPUID_6_EAX_ARAT (1U << 2) |
651 | ||
303752a9 MT |
652 | /* CPUID[0x80000007].EDX flags: */ |
653 | #define CPUID_APM_INVTSC (1U << 8) | |
654 | ||
9df694ee IM |
655 | #define CPUID_VENDOR_SZ 12 |
656 | ||
c5096daf AZ |
657 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
658 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
659 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
99b88a17 | 660 | #define CPUID_VENDOR_INTEL "GenuineIntel" |
c5096daf AZ |
661 | |
662 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
b3baa152 | 663 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
c5096daf | 664 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
99b88a17 | 665 | #define CPUID_VENDOR_AMD "AuthenticAMD" |
c5096daf | 666 | |
99b88a17 | 667 | #define CPUID_VENDOR_VIA "CentaurHauls" |
b3baa152 | 668 | |
2cd49cbf PM |
669 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ |
670 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ | |
e737b32a | 671 | |
5232d00a RK |
672 | /* CPUID[0xB].ECX level types */ |
673 | #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) | |
674 | #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) | |
675 | #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) | |
676 | ||
92067bf4 IM |
677 | #ifndef HYPERV_SPINLOCK_NEVER_RETRY |
678 | #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF | |
679 | #endif | |
680 | ||
2c0262af | 681 | #define EXCP00_DIVZ 0 |
01df040b | 682 | #define EXCP01_DB 1 |
2c0262af FB |
683 | #define EXCP02_NMI 2 |
684 | #define EXCP03_INT3 3 | |
685 | #define EXCP04_INTO 4 | |
686 | #define EXCP05_BOUND 5 | |
687 | #define EXCP06_ILLOP 6 | |
688 | #define EXCP07_PREX 7 | |
689 | #define EXCP08_DBLE 8 | |
690 | #define EXCP09_XERR 9 | |
691 | #define EXCP0A_TSS 10 | |
692 | #define EXCP0B_NOSEG 11 | |
693 | #define EXCP0C_STACK 12 | |
694 | #define EXCP0D_GPF 13 | |
695 | #define EXCP0E_PAGE 14 | |
696 | #define EXCP10_COPR 16 | |
697 | #define EXCP11_ALGN 17 | |
698 | #define EXCP12_MCHK 18 | |
699 | ||
d2fd1af7 FB |
700 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
701 | for syscall instruction */ | |
10cde894 | 702 | #define EXCP_VMEXIT 0x100 |
d2fd1af7 | 703 | |
00a152b4 | 704 | /* i386-specific interrupt pending bits. */ |
5d62c43a | 705 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
00a152b4 | 706 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
85097db6 | 707 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
00a152b4 RH |
708 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
709 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
4a92a558 PB |
710 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 |
711 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 | |
00a152b4 | 712 | |
4a92a558 PB |
713 | /* Use a clearer name for this. */ |
714 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET | |
00a152b4 | 715 | |
c3ce5a23 PB |
716 | /* Instead of computing the condition codes after each x86 instruction, |
717 | * QEMU just stores one operand (called CC_SRC), the result | |
718 | * (called CC_DST) and the type of operation (called CC_OP). When the | |
719 | * condition codes are needed, the condition codes can be calculated | |
720 | * using this information. Condition codes are not generated if they | |
721 | * are only needed for conditional branches. | |
722 | */ | |
fee71888 | 723 | typedef enum { |
2c0262af | 724 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
1235fc06 | 725 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
d36cd60e FB |
726 | |
727 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
728 | CC_OP_MULW, | |
729 | CC_OP_MULL, | |
14ce26e7 | 730 | CC_OP_MULQ, |
2c0262af FB |
731 | |
732 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
733 | CC_OP_ADDW, | |
734 | CC_OP_ADDL, | |
14ce26e7 | 735 | CC_OP_ADDQ, |
2c0262af FB |
736 | |
737 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
738 | CC_OP_ADCW, | |
739 | CC_OP_ADCL, | |
14ce26e7 | 740 | CC_OP_ADCQ, |
2c0262af FB |
741 | |
742 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
743 | CC_OP_SUBW, | |
744 | CC_OP_SUBL, | |
14ce26e7 | 745 | CC_OP_SUBQ, |
2c0262af FB |
746 | |
747 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
748 | CC_OP_SBBW, | |
749 | CC_OP_SBBL, | |
14ce26e7 | 750 | CC_OP_SBBQ, |
2c0262af FB |
751 | |
752 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
753 | CC_OP_LOGICW, | |
754 | CC_OP_LOGICL, | |
14ce26e7 | 755 | CC_OP_LOGICQ, |
2c0262af FB |
756 | |
757 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
758 | CC_OP_INCW, | |
759 | CC_OP_INCL, | |
14ce26e7 | 760 | CC_OP_INCQ, |
2c0262af FB |
761 | |
762 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
763 | CC_OP_DECW, | |
764 | CC_OP_DECL, | |
14ce26e7 | 765 | CC_OP_DECQ, |
2c0262af | 766 | |
6b652794 | 767 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
2c0262af FB |
768 | CC_OP_SHLW, |
769 | CC_OP_SHLL, | |
14ce26e7 | 770 | CC_OP_SHLQ, |
2c0262af FB |
771 | |
772 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
773 | CC_OP_SARW, | |
774 | CC_OP_SARL, | |
14ce26e7 | 775 | CC_OP_SARQ, |
2c0262af | 776 | |
bc4b43dc RH |
777 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ |
778 | CC_OP_BMILGW, | |
779 | CC_OP_BMILGL, | |
780 | CC_OP_BMILGQ, | |
781 | ||
cd7f97ca RH |
782 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ |
783 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ | |
784 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ | |
785 | ||
436ff2d2 | 786 | CC_OP_CLR, /* Z set, all other flags clear. */ |
4885c3c4 | 787 | CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ |
436ff2d2 | 788 | |
2c0262af | 789 | CC_OP_NB, |
fee71888 | 790 | } CCOp; |
2c0262af | 791 | |
2c0262af FB |
792 | typedef struct SegmentCache { |
793 | uint32_t selector; | |
14ce26e7 | 794 | target_ulong base; |
2c0262af FB |
795 | uint32_t limit; |
796 | uint32_t flags; | |
797 | } SegmentCache; | |
798 | ||
f23a9db6 EH |
799 | #define MMREG_UNION(n, bits) \ |
800 | union n { \ | |
801 | uint8_t _b_##n[(bits)/8]; \ | |
802 | uint16_t _w_##n[(bits)/16]; \ | |
803 | uint32_t _l_##n[(bits)/32]; \ | |
804 | uint64_t _q_##n[(bits)/64]; \ | |
805 | float32 _s_##n[(bits)/32]; \ | |
806 | float64 _d_##n[(bits)/64]; \ | |
31d414d6 EH |
807 | } |
808 | ||
f23a9db6 EH |
809 | typedef MMREG_UNION(ZMMReg, 512) ZMMReg; |
810 | typedef MMREG_UNION(MMXReg, 64) MMXReg; | |
826461bb | 811 | |
79e9ebeb LJ |
812 | typedef struct BNDReg { |
813 | uint64_t lb; | |
814 | uint64_t ub; | |
815 | } BNDReg; | |
816 | ||
817 | typedef struct BNDCSReg { | |
818 | uint64_t cfgu; | |
819 | uint64_t sts; | |
820 | } BNDCSReg; | |
821 | ||
f4f1110e RH |
822 | #define BNDCFG_ENABLE 1ULL |
823 | #define BNDCFG_BNDPRESERVE 2ULL | |
824 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK | |
825 | ||
e2542fe2 | 826 | #ifdef HOST_WORDS_BIGENDIAN |
f23a9db6 EH |
827 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] |
828 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] | |
829 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] | |
830 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] | |
831 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] | |
832 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] | |
833 | ||
834 | #define MMX_B(n) _b_MMXReg[7 - (n)] | |
835 | #define MMX_W(n) _w_MMXReg[3 - (n)] | |
836 | #define MMX_L(n) _l_MMXReg[1 - (n)] | |
837 | #define MMX_S(n) _s_MMXReg[1 - (n)] | |
826461bb | 838 | #else |
f23a9db6 EH |
839 | #define ZMM_B(n) _b_ZMMReg[n] |
840 | #define ZMM_W(n) _w_ZMMReg[n] | |
841 | #define ZMM_L(n) _l_ZMMReg[n] | |
842 | #define ZMM_S(n) _s_ZMMReg[n] | |
843 | #define ZMM_Q(n) _q_ZMMReg[n] | |
844 | #define ZMM_D(n) _d_ZMMReg[n] | |
845 | ||
846 | #define MMX_B(n) _b_MMXReg[n] | |
847 | #define MMX_W(n) _w_MMXReg[n] | |
848 | #define MMX_L(n) _l_MMXReg[n] | |
849 | #define MMX_S(n) _s_MMXReg[n] | |
826461bb | 850 | #endif |
f23a9db6 | 851 | #define MMX_Q(n) _q_MMXReg[n] |
826461bb | 852 | |
acc68836 | 853 | typedef union { |
c31da136 | 854 | floatx80 d __attribute__((aligned(16))); |
acc68836 JQ |
855 | MMXReg mmx; |
856 | } FPReg; | |
857 | ||
c1a54d57 JQ |
858 | typedef struct { |
859 | uint64_t base; | |
860 | uint64_t mask; | |
861 | } MTRRVar; | |
862 | ||
5f30fa18 JK |
863 | #define CPU_NB_REGS64 16 |
864 | #define CPU_NB_REGS32 8 | |
865 | ||
14ce26e7 | 866 | #ifdef TARGET_X86_64 |
5f30fa18 | 867 | #define CPU_NB_REGS CPU_NB_REGS64 |
14ce26e7 | 868 | #else |
5f30fa18 | 869 | #define CPU_NB_REGS CPU_NB_REGS32 |
14ce26e7 FB |
870 | #endif |
871 | ||
0d894367 PB |
872 | #define MAX_FIXED_COUNTERS 3 |
873 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) | |
874 | ||
a9321a4d | 875 | #define NB_MMU_MODES 3 |
2066d095 | 876 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 877 | |
9aecd6f8 CP |
878 | #define NB_OPMASK_REGS 8 |
879 | ||
d9c84f19 IM |
880 | /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish |
881 | * that APIC ID hasn't been set yet | |
882 | */ | |
883 | #define UNASSIGNED_APIC_ID 0xFFFFFFFF | |
884 | ||
b503717d EH |
885 | typedef union X86LegacyXSaveArea { |
886 | struct { | |
887 | uint16_t fcw; | |
888 | uint16_t fsw; | |
889 | uint8_t ftw; | |
890 | uint8_t reserved; | |
891 | uint16_t fpop; | |
892 | uint64_t fpip; | |
893 | uint64_t fpdp; | |
894 | uint32_t mxcsr; | |
895 | uint32_t mxcsr_mask; | |
896 | FPReg fpregs[8]; | |
897 | uint8_t xmm_regs[16][16]; | |
898 | }; | |
899 | uint8_t data[512]; | |
900 | } X86LegacyXSaveArea; | |
901 | ||
902 | typedef struct X86XSaveHeader { | |
903 | uint64_t xstate_bv; | |
904 | uint64_t xcomp_bv; | |
3f32bd21 RH |
905 | uint64_t reserve0; |
906 | uint8_t reserved[40]; | |
b503717d EH |
907 | } X86XSaveHeader; |
908 | ||
909 | /* Ext. save area 2: AVX State */ | |
910 | typedef struct XSaveAVX { | |
911 | uint8_t ymmh[16][16]; | |
912 | } XSaveAVX; | |
913 | ||
914 | /* Ext. save area 3: BNDREG */ | |
915 | typedef struct XSaveBNDREG { | |
916 | BNDReg bnd_regs[4]; | |
917 | } XSaveBNDREG; | |
918 | ||
919 | /* Ext. save area 4: BNDCSR */ | |
920 | typedef union XSaveBNDCSR { | |
921 | BNDCSReg bndcsr; | |
922 | uint8_t data[64]; | |
923 | } XSaveBNDCSR; | |
924 | ||
925 | /* Ext. save area 5: Opmask */ | |
926 | typedef struct XSaveOpmask { | |
927 | uint64_t opmask_regs[NB_OPMASK_REGS]; | |
928 | } XSaveOpmask; | |
929 | ||
930 | /* Ext. save area 6: ZMM_Hi256 */ | |
931 | typedef struct XSaveZMM_Hi256 { | |
932 | uint8_t zmm_hi256[16][32]; | |
933 | } XSaveZMM_Hi256; | |
934 | ||
935 | /* Ext. save area 7: Hi16_ZMM */ | |
936 | typedef struct XSaveHi16_ZMM { | |
937 | uint8_t hi16_zmm[16][64]; | |
938 | } XSaveHi16_ZMM; | |
939 | ||
940 | /* Ext. save area 9: PKRU state */ | |
941 | typedef struct XSavePKRU { | |
942 | uint32_t pkru; | |
943 | uint32_t padding; | |
944 | } XSavePKRU; | |
945 | ||
946 | typedef struct X86XSaveArea { | |
947 | X86LegacyXSaveArea legacy; | |
948 | X86XSaveHeader header; | |
949 | ||
950 | /* Extended save areas: */ | |
951 | ||
952 | /* AVX State: */ | |
953 | XSaveAVX avx_state; | |
954 | uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; | |
955 | /* MPX State: */ | |
956 | XSaveBNDREG bndreg_state; | |
957 | XSaveBNDCSR bndcsr_state; | |
958 | /* AVX-512 State: */ | |
959 | XSaveOpmask opmask_state; | |
960 | XSaveZMM_Hi256 zmm_hi256_state; | |
961 | XSaveHi16_ZMM hi16_zmm_state; | |
962 | /* PKRU State: */ | |
963 | XSavePKRU pkru_state; | |
964 | } X86XSaveArea; | |
965 | ||
966 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); | |
967 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); | |
968 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); | |
969 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); | |
970 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); | |
971 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); | |
972 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); | |
973 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); | |
974 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); | |
975 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); | |
976 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); | |
977 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); | |
978 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); | |
979 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); | |
980 | ||
d362e757 JK |
981 | typedef enum TPRAccess { |
982 | TPR_ACCESS_READ, | |
983 | TPR_ACCESS_WRITE, | |
984 | } TPRAccess; | |
985 | ||
2c0262af FB |
986 | typedef struct CPUX86State { |
987 | /* standard registers */ | |
14ce26e7 FB |
988 | target_ulong regs[CPU_NB_REGS]; |
989 | target_ulong eip; | |
990 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
2c0262af FB |
991 | flags and DF are set to zero because they are |
992 | stored elsewhere */ | |
993 | ||
994 | /* emulator internal eflags handling */ | |
14ce26e7 | 995 | target_ulong cc_dst; |
988c3eb0 RH |
996 | target_ulong cc_src; |
997 | target_ulong cc_src2; | |
2c0262af FB |
998 | uint32_t cc_op; |
999 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
db620f46 FB |
1000 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
1001 | are known at translation time. */ | |
1002 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
2c0262af | 1003 | |
9df217a3 FB |
1004 | /* segments */ |
1005 | SegmentCache segs[6]; /* selector values */ | |
1006 | SegmentCache ldt; | |
1007 | SegmentCache tr; | |
1008 | SegmentCache gdt; /* only base and limit are used */ | |
1009 | SegmentCache idt; /* only base and limit are used */ | |
1010 | ||
db620f46 | 1011 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
5ee0ffaa | 1012 | int32_t a20_mask; |
9df217a3 | 1013 | |
05e7e819 PB |
1014 | BNDReg bnd_regs[4]; |
1015 | BNDCSReg bndcs_regs; | |
1016 | uint64_t msr_bndcfgs; | |
2188cc52 | 1017 | uint64_t efer; |
05e7e819 | 1018 | |
43175fa9 PB |
1019 | /* Beginning of state preserved by INIT (dummy marker). */ |
1020 | struct {} start_init_save; | |
1021 | ||
2c0262af FB |
1022 | /* FPU state */ |
1023 | unsigned int fpstt; /* top of stack index */ | |
67b8f419 | 1024 | uint16_t fpus; |
eb831623 | 1025 | uint16_t fpuc; |
2c0262af | 1026 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
acc68836 | 1027 | FPReg fpregs[8]; |
42cc8fa6 JK |
1028 | /* KVM-only so far */ |
1029 | uint16_t fpop; | |
1030 | uint64_t fpip; | |
1031 | uint64_t fpdp; | |
2c0262af FB |
1032 | |
1033 | /* emulator internal variables */ | |
7a0e1f41 | 1034 | float_status fp_status; |
c31da136 | 1035 | floatx80 ft0; |
3b46e624 | 1036 | |
a35f3ec7 | 1037 | float_status mmx_status; /* for 3DNow! float ops */ |
7a0e1f41 | 1038 | float_status sse_status; |
664e0f19 | 1039 | uint32_t mxcsr; |
fa451874 EH |
1040 | ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; |
1041 | ZMMReg xmm_t0; | |
664e0f19 | 1042 | MMXReg mmx_t0; |
14ce26e7 | 1043 | |
9aecd6f8 | 1044 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
9aecd6f8 | 1045 | |
2c0262af FB |
1046 | /* sysenter registers */ |
1047 | uint32_t sysenter_cs; | |
2436b61a AZ |
1048 | target_ulong sysenter_esp; |
1049 | target_ulong sysenter_eip; | |
8d9bfc2b | 1050 | uint64_t star; |
0573fbfc | 1051 | |
5cc1d1e6 | 1052 | uint64_t vm_hsave; |
0573fbfc | 1053 | |
14ce26e7 | 1054 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
1055 | target_ulong lstar; |
1056 | target_ulong cstar; | |
1057 | target_ulong fmask; | |
1058 | target_ulong kernelgsbase; | |
1059 | #endif | |
58fe2f10 | 1060 | |
7ba1e619 | 1061 | uint64_t tsc; |
f28558d3 | 1062 | uint64_t tsc_adjust; |
aa82ba54 | 1063 | uint64_t tsc_deadline; |
7616f1c2 PB |
1064 | uint64_t tsc_aux; |
1065 | ||
1066 | uint64_t xcr0; | |
7ba1e619 | 1067 | |
18559232 | 1068 | uint64_t mcg_status; |
21e87c46 | 1069 | uint64_t msr_ia32_misc_enable; |
0779caeb | 1070 | uint64_t msr_ia32_feature_control; |
18559232 | 1071 | |
0d894367 PB |
1072 | uint64_t msr_fixed_ctr_ctrl; |
1073 | uint64_t msr_global_ctrl; | |
1074 | uint64_t msr_global_status; | |
1075 | uint64_t msr_global_ovf_ctrl; | |
1076 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; | |
1077 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; | |
1078 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; | |
43175fa9 PB |
1079 | |
1080 | uint64_t pat; | |
1081 | uint32_t smbase; | |
1082 | ||
7616f1c2 PB |
1083 | uint32_t pkru; |
1084 | ||
43175fa9 PB |
1085 | /* End of state preserved by INIT (dummy marker). */ |
1086 | struct {} end_init_save; | |
1087 | ||
1088 | uint64_t system_time_msr; | |
1089 | uint64_t wall_clock_msr; | |
1090 | uint64_t steal_time_msr; | |
1091 | uint64_t async_pf_en_msr; | |
1092 | uint64_t pv_eoi_en_msr; | |
1093 | ||
1c90ef26 VR |
1094 | uint64_t msr_hv_hypercall; |
1095 | uint64_t msr_hv_guest_os_id; | |
5ef68987 | 1096 | uint64_t msr_hv_vapic; |
48a5f3bc | 1097 | uint64_t msr_hv_tsc; |
f2a53c9e | 1098 | uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS]; |
46eb8f98 | 1099 | uint64_t msr_hv_runtime; |
866eea9a AS |
1100 | uint64_t msr_hv_synic_control; |
1101 | uint64_t msr_hv_synic_version; | |
1102 | uint64_t msr_hv_synic_evt_page; | |
1103 | uint64_t msr_hv_synic_msg_page; | |
1104 | uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; | |
ff99aa64 AS |
1105 | uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT]; |
1106 | uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT]; | |
18559232 | 1107 | |
2c0262af | 1108 | /* exception/interrupt handling */ |
2c0262af FB |
1109 | int error_code; |
1110 | int exception_is_int; | |
826461bb | 1111 | target_ulong exception_next_eip; |
d0052339 | 1112 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ |
01df040b | 1113 | union { |
f0c3c505 | 1114 | struct CPUBreakpoint *cpu_breakpoint[4]; |
ff4700b0 | 1115 | struct CPUWatchpoint *cpu_watchpoint[4]; |
01df040b | 1116 | }; /* break/watchpoints for dr[0..3] */ |
678dde13 | 1117 | int old_exception; /* exception in flight */ |
2c0262af | 1118 | |
43175fa9 PB |
1119 | uint64_t vm_vmcb; |
1120 | uint64_t tsc_offset; | |
1121 | uint64_t intercept; | |
1122 | uint16_t intercept_cr_read; | |
1123 | uint16_t intercept_cr_write; | |
1124 | uint16_t intercept_dr_read; | |
1125 | uint16_t intercept_dr_write; | |
1126 | uint32_t intercept_exceptions; | |
1127 | uint8_t v_tpr; | |
1128 | ||
d8f771d9 JK |
1129 | /* KVM states, automatically cleared on reset */ |
1130 | uint8_t nmi_injected; | |
1131 | uint8_t nmi_pending; | |
1132 | ||
1f5c00cf AB |
1133 | /* Fields up to this point are cleared by a CPU reset */ |
1134 | struct {} end_reset_fields; | |
1135 | ||
a316d335 | 1136 | CPU_COMMON |
2c0262af | 1137 | |
1f5c00cf | 1138 | /* Fields after CPU_COMMON are preserved across CPU reset. */ |
ebda377f | 1139 | |
14ce26e7 | 1140 | /* processor features (e.g. for CPUID insn) */ |
c39c0edf EH |
1141 | /* Minimum level/xlevel/xlevel2, based on CPU model + features */ |
1142 | uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; | |
1143 | /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ | |
1144 | uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; | |
1145 | /* Actual level/xlevel/xlevel2 value: */ | |
1146 | uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; | |
14ce26e7 FB |
1147 | uint32_t cpuid_vendor1; |
1148 | uint32_t cpuid_vendor2; | |
1149 | uint32_t cpuid_vendor3; | |
1150 | uint32_t cpuid_version; | |
0514ef2f | 1151 | FeatureWordArray features; |
d4a606b3 EH |
1152 | /* Features that were explicitly enabled/disabled */ |
1153 | FeatureWordArray user_features; | |
8d9bfc2b | 1154 | uint32_t cpuid_model[12]; |
3b46e624 | 1155 | |
165d9b82 AL |
1156 | /* MTRRs */ |
1157 | uint64_t mtrr_fixed[11]; | |
1158 | uint64_t mtrr_deftype; | |
d8b5c67b | 1159 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; |
165d9b82 | 1160 | |
7ba1e619 | 1161 | /* For KVM */ |
f8d926e9 | 1162 | uint32_t mp_state; |
31827373 | 1163 | int32_t exception_injected; |
0e607a80 | 1164 | int32_t interrupt_injected; |
a0fb002c | 1165 | uint8_t soft_interrupt; |
a0fb002c JK |
1166 | uint8_t has_error_code; |
1167 | uint32_t sipi_vector; | |
b8cc45d6 | 1168 | bool tsc_valid; |
06ef227e | 1169 | int64_t tsc_khz; |
36f96c4b | 1170 | int64_t user_tsc_khz; /* for sanity check only */ |
fabacc0f JK |
1171 | void *kvm_xsave_buf; |
1172 | ||
ac6c4120 | 1173 | uint64_t mcg_cap; |
ac6c4120 | 1174 | uint64_t mcg_ctl; |
87f8b626 | 1175 | uint64_t mcg_ext_ctl; |
ac6c4120 | 1176 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
7616f1c2 | 1177 | uint64_t xstate_bv; |
5a2d0e57 AJ |
1178 | |
1179 | /* vmstate */ | |
1180 | uint16_t fpus_vmstate; | |
1181 | uint16_t fptag_vmstate; | |
1182 | uint16_t fpregs_format_vmstate; | |
f1665b21 | 1183 | |
18cd2c17 | 1184 | uint64_t xss; |
d362e757 JK |
1185 | |
1186 | TPRAccess tpr_access_type; | |
2c0262af FB |
1187 | } CPUX86State; |
1188 | ||
d71b62a1 EH |
1189 | struct kvm_msrs; |
1190 | ||
4da6f8d9 PB |
1191 | /** |
1192 | * X86CPU: | |
1193 | * @env: #CPUX86State | |
1194 | * @migratable: If set, only migratable flags will be accepted when "enforce" | |
1195 | * mode is used, and only migratable flags will be included in the "host" | |
1196 | * CPU model. | |
1197 | * | |
1198 | * An x86 CPU. | |
1199 | */ | |
1200 | struct X86CPU { | |
1201 | /*< private >*/ | |
1202 | CPUState parent_obj; | |
1203 | /*< public >*/ | |
1204 | ||
1205 | CPUX86State env; | |
1206 | ||
1207 | bool hyperv_vapic; | |
1208 | bool hyperv_relaxed_timing; | |
1209 | int hyperv_spinlock_attempts; | |
1210 | char *hyperv_vendor_id; | |
1211 | bool hyperv_time; | |
1212 | bool hyperv_crash; | |
1213 | bool hyperv_reset; | |
1214 | bool hyperv_vpindex; | |
1215 | bool hyperv_runtime; | |
1216 | bool hyperv_synic; | |
1217 | bool hyperv_stimer; | |
1218 | bool check_cpuid; | |
1219 | bool enforce_cpuid; | |
1220 | bool expose_kvm; | |
1221 | bool migratable; | |
44bd8e53 | 1222 | bool max_features; /* Enable all supported features automatically */ |
d9c84f19 | 1223 | uint32_t apic_id; |
4da6f8d9 | 1224 | |
9954a158 PDJ |
1225 | /* Enables publishing of TSC increment and Local APIC bus frequencies to |
1226 | * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ | |
1227 | bool vmware_cpuid_freq; | |
1228 | ||
4da6f8d9 PB |
1229 | /* if true the CPUID code directly forward host cache leaves to the guest */ |
1230 | bool cache_info_passthrough; | |
1231 | ||
1232 | /* Features that were filtered out because of missing host capabilities */ | |
1233 | uint32_t filtered_features[FEATURE_WORDS]; | |
1234 | ||
1235 | /* Enable PMU CPUID bits. This can't be enabled by default yet because | |
1236 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID | |
1237 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel | |
1238 | * capabilities) directly to the guest. | |
1239 | */ | |
1240 | bool enable_pmu; | |
1241 | ||
87f8b626 AR |
1242 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is |
1243 | * disabled by default to avoid breaking migration between QEMU with | |
1244 | * different LMCE configurations. | |
1245 | */ | |
1246 | bool enable_lmce; | |
1247 | ||
14c985cf LM |
1248 | /* Compatibility bits for old machine types. |
1249 | * If true present virtual l3 cache for VM, the vcpus in the same virtual | |
1250 | * socket share an virtual l3 cache. | |
1251 | */ | |
1252 | bool enable_l3_cache; | |
1253 | ||
5232d00a RK |
1254 | /* Compatibility bits for old machine types: */ |
1255 | bool enable_cpuid_0xb; | |
1256 | ||
c39c0edf EH |
1257 | /* Enable auto level-increase for all CPUID leaves */ |
1258 | bool full_cpuid_auto_level; | |
1259 | ||
fcc35e7c DDAG |
1260 | /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ |
1261 | bool fill_mtrr_mask; | |
1262 | ||
11f6fee5 DDAG |
1263 | /* if true override the phys_bits value with a value read from the host */ |
1264 | bool host_phys_bits; | |
1265 | ||
fc3a1fd7 DDAG |
1266 | /* Stop SMI delivery for migration compatibility with old machines */ |
1267 | bool kvm_no_smi_migration; | |
1268 | ||
af45907a DDAG |
1269 | /* Number of physical address bits supported */ |
1270 | uint32_t phys_bits; | |
1271 | ||
4da6f8d9 PB |
1272 | /* in order to simplify APIC support, we leave this pointer to the |
1273 | user */ | |
1274 | struct DeviceState *apic_state; | |
1275 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; | |
1276 | Notifier machine_done; | |
d71b62a1 EH |
1277 | |
1278 | struct kvm_msrs *kvm_msr_buf; | |
d89c2b8b | 1279 | |
15f8b142 | 1280 | int32_t node_id; /* NUMA node this CPU belongs to */ |
d89c2b8b IM |
1281 | int32_t socket_id; |
1282 | int32_t core_id; | |
1283 | int32_t thread_id; | |
4da6f8d9 PB |
1284 | }; |
1285 | ||
1286 | static inline X86CPU *x86_env_get_cpu(CPUX86State *env) | |
1287 | { | |
1288 | return container_of(env, X86CPU, env); | |
1289 | } | |
1290 | ||
1291 | #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) | |
1292 | ||
1293 | #define ENV_OFFSET offsetof(X86CPU, env) | |
1294 | ||
1295 | #ifndef CONFIG_USER_ONLY | |
1296 | extern struct VMStateDescription vmstate_x86_cpu; | |
1297 | #endif | |
1298 | ||
1299 | /** | |
1300 | * x86_cpu_do_interrupt: | |
1301 | * @cpu: vCPU the interrupt is to be handled by. | |
1302 | */ | |
1303 | void x86_cpu_do_interrupt(CPUState *cpu); | |
1304 | bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
1305 | ||
1306 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1307 | int cpuid, void *opaque); | |
1308 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1309 | int cpuid, void *opaque); | |
1310 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
1311 | void *opaque); | |
1312 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
1313 | void *opaque); | |
1314 | ||
1315 | void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
1316 | Error **errp); | |
1317 | ||
1318 | void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | |
1319 | int flags); | |
1320 | ||
1321 | hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
1322 | ||
1323 | int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
1324 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
1325 | ||
1326 | void x86_cpu_exec_enter(CPUState *cpu); | |
1327 | void x86_cpu_exec_exit(CPUState *cpu); | |
5fd2087a | 1328 | |
0856579c | 1329 | X86CPU *cpu_x86_init(const char *cpu_model); |
e916cbf8 | 1330 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
317ac620 | 1331 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
b5ec5ce0 | 1332 | |
d720b93d | 1333 | int cpu_get_pic_interrupt(CPUX86State *s); |
2ee73ac3 FB |
1334 | /* MSDOS compatibility mode FPU exception support */ |
1335 | void cpu_set_ferr(CPUX86State *s); | |
2c0262af FB |
1336 | |
1337 | /* this function must always be used to load data in the segment | |
1338 | cache: it synchronizes the hflags with the segment cache values */ | |
5fafdf24 | 1339 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
2c0262af | 1340 | int seg_reg, unsigned int selector, |
8988ae89 | 1341 | target_ulong base, |
5fafdf24 | 1342 | unsigned int limit, |
2c0262af FB |
1343 | unsigned int flags) |
1344 | { | |
1345 | SegmentCache *sc; | |
1346 | unsigned int new_hflags; | |
3b46e624 | 1347 | |
2c0262af FB |
1348 | sc = &env->segs[seg_reg]; |
1349 | sc->selector = selector; | |
1350 | sc->base = base; | |
1351 | sc->limit = limit; | |
1352 | sc->flags = flags; | |
1353 | ||
1354 | /* update the hidden flags */ | |
14ce26e7 FB |
1355 | { |
1356 | if (seg_reg == R_CS) { | |
1357 | #ifdef TARGET_X86_64 | |
1358 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
1359 | /* long mode */ | |
1360 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1361 | env->hflags &= ~(HF_ADDSEG_MASK); | |
5fafdf24 | 1362 | } else |
14ce26e7 FB |
1363 | #endif |
1364 | { | |
1365 | /* legacy / compatibility case */ | |
1366 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
1367 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
1368 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
1369 | new_hflags; | |
1370 | } | |
7125c937 PB |
1371 | } |
1372 | if (seg_reg == R_SS) { | |
1373 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; | |
7848c8d1 KC |
1374 | #if HF_CPL_MASK != 3 |
1375 | #error HF_CPL_MASK is hardcoded | |
1376 | #endif | |
1377 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; | |
14ce26e7 FB |
1378 | } |
1379 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
1380 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
1381 | if (env->hflags & HF_CS64_MASK) { | |
1382 | /* zero base assumed for DS, ES and SS in long mode */ | |
5fafdf24 | 1383 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
735a8fd3 FB |
1384 | (env->eflags & VM_MASK) || |
1385 | !(env->hflags & HF_CS32_MASK)) { | |
14ce26e7 FB |
1386 | /* XXX: try to avoid this test. The problem comes from the |
1387 | fact that is real mode or vm86 mode we only modify the | |
1388 | 'base' and 'selector' fields of the segment cache to go | |
1389 | faster. A solution may be to force addseg to one in | |
1390 | translate-i386.c. */ | |
1391 | new_hflags |= HF_ADDSEG_MASK; | |
1392 | } else { | |
5fafdf24 | 1393 | new_hflags |= ((env->segs[R_DS].base | |
735a8fd3 | 1394 | env->segs[R_ES].base | |
5fafdf24 | 1395 | env->segs[R_SS].base) != 0) << |
14ce26e7 FB |
1396 | HF_ADDSEG_SHIFT; |
1397 | } | |
5fafdf24 | 1398 | env->hflags = (env->hflags & |
14ce26e7 | 1399 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
2c0262af | 1400 | } |
2c0262af FB |
1401 | } |
1402 | ||
e9f9d6b1 | 1403 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
e6a33e45 | 1404 | uint8_t sipi_vector) |
0e26b7b8 | 1405 | { |
259186a7 | 1406 | CPUState *cs = CPU(cpu); |
e9f9d6b1 AF |
1407 | CPUX86State *env = &cpu->env; |
1408 | ||
0e26b7b8 BS |
1409 | env->eip = 0; |
1410 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
1411 | sipi_vector << 12, | |
1412 | env->segs[R_CS].limit, | |
1413 | env->segs[R_CS].flags); | |
259186a7 | 1414 | cs->halted = 0; |
0e26b7b8 BS |
1415 | } |
1416 | ||
84273177 JK |
1417 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
1418 | target_ulong *base, unsigned int *limit, | |
1419 | unsigned int *flags); | |
1420 | ||
d9957a8b | 1421 | /* op_helper.c */ |
1f1af9fd | 1422 | /* used for debug or cpu save/restore */ |
1f1af9fd | 1423 | |
d9957a8b | 1424 | /* cpu-exec.c */ |
2c0262af FB |
1425 | /* the following helpers are only usable in user mode simulation as |
1426 | they can trigger unexpected exceptions */ | |
1427 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); | |
6f12a2a6 FB |
1428 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
1429 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
1c1df019 PK |
1430 | void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); |
1431 | void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); | |
2c0262af FB |
1432 | |
1433 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
1434 | signal handlers to inform the virtual CPU of exceptions. non zero | |
1435 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 1436 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
2c0262af | 1437 | void *puc); |
d9957a8b | 1438 | |
f4f1110e | 1439 | /* cpu.c */ |
c6dc6f63 AP |
1440 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
1441 | uint32_t *eax, uint32_t *ebx, | |
1442 | uint32_t *ecx, uint32_t *edx); | |
0e26b7b8 | 1443 | void cpu_clear_apic_feature(CPUX86State *env); |
bb44e0d1 JK |
1444 | void host_cpuid(uint32_t function, uint32_t count, |
1445 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
20271d48 | 1446 | void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); |
c6dc6f63 | 1447 | |
d9957a8b | 1448 | /* helper.c */ |
7510454e | 1449 | int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, |
97b348e7 | 1450 | int is_write, int mmu_idx); |
cc36a7a2 | 1451 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); |
2c0262af | 1452 | |
b216aa6c | 1453 | #ifndef CONFIG_USER_ONLY |
f8c45c65 PB |
1454 | static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) |
1455 | { | |
1456 | return !!attrs.secure; | |
1457 | } | |
1458 | ||
1459 | static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) | |
1460 | { | |
1461 | return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); | |
1462 | } | |
1463 | ||
b216aa6c PB |
1464 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); |
1465 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); | |
1466 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); | |
1467 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); | |
1468 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); | |
1469 | void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); | |
1470 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
1471 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
1472 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); | |
1473 | #endif | |
1474 | ||
86025ee4 | 1475 | void breakpoint_handler(CPUState *cs); |
d9957a8b BS |
1476 | |
1477 | /* will be suppressed */ | |
1478 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
1479 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
1480 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
93d00d0f | 1481 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); |
d9957a8b | 1482 | |
d9957a8b | 1483 | /* hw/pc.c */ |
d9957a8b | 1484 | uint64_t cpu_get_tsc(CPUX86State *env); |
6fd805e1 | 1485 | |
2c0262af | 1486 | #define TARGET_PAGE_BITS 12 |
9467d44c | 1487 | |
52705890 RH |
1488 | #ifdef TARGET_X86_64 |
1489 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 | |
1490 | /* ??? This is really 48 bits, sign-extended, but the only thing | |
1491 | accessible to userland with bit 48 set is the VSYSCALL, and that | |
1492 | is handled via other mechanisms. */ | |
1493 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 | |
1494 | #else | |
1495 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
1496 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1497 | #endif | |
1498 | ||
e8f6d00c PB |
1499 | /* XXX: This value should match the one returned by CPUID |
1500 | * and in exec.c */ | |
1501 | # if defined(TARGET_X86_64) | |
709787ee | 1502 | # define TCG_PHYS_ADDR_BITS 40 |
e8f6d00c | 1503 | # else |
709787ee | 1504 | # define TCG_PHYS_ADDR_BITS 36 |
e8f6d00c PB |
1505 | # endif |
1506 | ||
709787ee DDAG |
1507 | #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) |
1508 | ||
2994fd96 | 1509 | #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model)) |
b47ed996 | 1510 | |
9467d44c | 1511 | #define cpu_signal_handler cpu_x86_signal_handler |
e916cbf8 | 1512 | #define cpu_list x86_cpu_list |
9467d44c | 1513 | |
6ebbf390 | 1514 | /* MMU modes definitions */ |
8a201bd4 | 1515 | #define MMU_MODE0_SUFFIX _ksmap |
6ebbf390 | 1516 | #define MMU_MODE1_SUFFIX _user |
43773ed3 | 1517 | #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ |
8a201bd4 | 1518 | #define MMU_KSMAP_IDX 0 |
a9321a4d | 1519 | #define MMU_USER_IDX 1 |
43773ed3 | 1520 | #define MMU_KNOSMAP_IDX 2 |
97ed5ccd | 1521 | static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) |
6ebbf390 | 1522 | { |
a9321a4d | 1523 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
f57584dc | 1524 | (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) |
8a201bd4 PB |
1525 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; |
1526 | } | |
1527 | ||
1528 | static inline int cpu_mmu_index_kernel(CPUX86State *env) | |
1529 | { | |
1530 | return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : | |
1531 | ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) | |
1532 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; | |
6ebbf390 JM |
1533 | } |
1534 | ||
988c3eb0 RH |
1535 | #define CC_DST (env->cc_dst) |
1536 | #define CC_SRC (env->cc_src) | |
1537 | #define CC_SRC2 (env->cc_src2) | |
1538 | #define CC_OP (env->cc_op) | |
f081c76c | 1539 | |
5918fffb BS |
1540 | /* n must be a constant to be efficient */ |
1541 | static inline target_long lshift(target_long x, int n) | |
1542 | { | |
1543 | if (n >= 0) { | |
1544 | return x << n; | |
1545 | } else { | |
1546 | return x >> (-n); | |
1547 | } | |
1548 | } | |
1549 | ||
f081c76c BS |
1550 | /* float macros */ |
1551 | #define FT0 (env->ft0) | |
1552 | #define ST0 (env->fpregs[env->fpstt].d) | |
1553 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
1554 | #define ST1 ST(1) | |
1555 | ||
d9957a8b | 1556 | /* translate.c */ |
63618b4e | 1557 | void tcg_x86_init(void); |
26a5f13b | 1558 | |
022c62cb | 1559 | #include "exec/cpu-all.h" |
0573fbfc TS |
1560 | #include "svm.h" |
1561 | ||
0e26b7b8 | 1562 | #if !defined(CONFIG_USER_ONLY) |
0d09e41a | 1563 | #include "hw/i386/apic.h" |
0e26b7b8 BS |
1564 | #endif |
1565 | ||
317ac620 | 1566 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
89fee74a | 1567 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
1568 | { |
1569 | *cs_base = env->segs[R_CS].base; | |
1570 | *pc = *cs_base + env->eip; | |
a2397807 | 1571 | *flags = env->hflags | |
a9321a4d | 1572 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
6b917547 AL |
1573 | } |
1574 | ||
232fc23b AF |
1575 | void do_cpu_init(X86CPU *cpu); |
1576 | void do_cpu_sipi(X86CPU *cpu); | |
2fa11da0 | 1577 | |
747461c7 JK |
1578 | #define MCE_INJECT_BROADCAST 1 |
1579 | #define MCE_INJECT_UNCOND_AO 2 | |
1580 | ||
8c5cf3b6 | 1581 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
316378e4 | 1582 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
747461c7 | 1583 | uint64_t misc, int flags); |
2fa11da0 | 1584 | |
599b9a5a | 1585 | /* excp_helper.c */ |
77b2bc2c | 1586 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
91980095 PD |
1587 | void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, |
1588 | uintptr_t retaddr); | |
77b2bc2c BS |
1589 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, |
1590 | int error_code); | |
91980095 PD |
1591 | void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, |
1592 | int error_code, uintptr_t retaddr); | |
599b9a5a BS |
1593 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
1594 | int error_code, int next_eip_addend); | |
1595 | ||
5918fffb BS |
1596 | /* cc_helper.c */ |
1597 | extern const uint8_t parity_table[256]; | |
1598 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); | |
1599 | ||
1600 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
1601 | { | |
79c664f6 YZ |
1602 | uint32_t eflags = env->eflags; |
1603 | if (tcg_enabled()) { | |
1604 | eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); | |
1605 | } | |
1606 | return eflags; | |
5918fffb BS |
1607 | } |
1608 | ||
28fb26f1 PB |
1609 | /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS |
1610 | * after generating a call to a helper that uses this. | |
1611 | */ | |
5918fffb BS |
1612 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, |
1613 | int update_mask) | |
1614 | { | |
1615 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
28fb26f1 | 1616 | CC_OP = CC_OP_EFLAGS; |
80cf2c81 | 1617 | env->df = 1 - (2 * ((eflags >> 10) & 1)); |
5918fffb BS |
1618 | env->eflags = (env->eflags & ~update_mask) | |
1619 | (eflags & update_mask) | 0x2; | |
1620 | } | |
1621 | ||
1622 | /* load efer and update the corresponding hflags. XXX: do consistency | |
1623 | checks with cpuid bits? */ | |
1624 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) | |
1625 | { | |
1626 | env->efer = val; | |
1627 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
1628 | if (env->efer & MSR_EFER_LMA) { | |
1629 | env->hflags |= HF_LMA_MASK; | |
1630 | } | |
1631 | if (env->efer & MSR_EFER_SVME) { | |
1632 | env->hflags |= HF_SVME_MASK; | |
1633 | } | |
1634 | } | |
1635 | ||
f794aa4a PB |
1636 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) |
1637 | { | |
1638 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); | |
1639 | } | |
1640 | ||
c8bc83a4 PB |
1641 | static inline int32_t x86_get_a20_mask(CPUX86State *env) |
1642 | { | |
1643 | if (env->hflags & HF_SMM_MASK) { | |
1644 | return -1; | |
1645 | } else { | |
1646 | return env->a20_mask; | |
1647 | } | |
1648 | } | |
1649 | ||
4e47e39a | 1650 | /* fpu_helper.c */ |
1d8ad165 YZ |
1651 | void update_fp_status(CPUX86State *env); |
1652 | void update_mxcsr_status(CPUX86State *env); | |
1653 | ||
1654 | static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) | |
1655 | { | |
1656 | env->mxcsr = mxcsr; | |
1657 | if (tcg_enabled()) { | |
1658 | update_mxcsr_status(env); | |
1659 | } | |
1660 | } | |
1661 | ||
1662 | static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) | |
1663 | { | |
1664 | env->fpuc = fpuc; | |
1665 | if (tcg_enabled()) { | |
1666 | update_fp_status(env); | |
1667 | } | |
1668 | } | |
4e47e39a | 1669 | |
677ef623 FK |
1670 | /* mem_helper.c */ |
1671 | void helper_lock_init(void); | |
1672 | ||
6bada5e8 BS |
1673 | /* svm_helper.c */ |
1674 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
65c9d60a PB |
1675 | uint64_t param, uintptr_t retaddr); |
1676 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1, | |
1677 | uintptr_t retaddr); | |
10cde894 | 1678 | void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); |
6bada5e8 | 1679 | |
97a8ea5a | 1680 | /* seg_helper.c */ |
599b9a5a | 1681 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); |
e694d4e2 | 1682 | |
f809c605 | 1683 | /* smm_helper.c */ |
518e9d7d | 1684 | void do_smm_enter(X86CPU *cpu); |
e694d4e2 | 1685 | |
d613f8cc | 1686 | /* apic.c */ |
317ac620 | 1687 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
d613f8cc PB |
1688 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
1689 | TPRAccess access); | |
1690 | ||
d362e757 | 1691 | |
5114e842 EH |
1692 | /* Change the value of a KVM-specific default |
1693 | * | |
1694 | * If value is NULL, no default will be set and the original | |
1695 | * value from the CPU model table will be kept. | |
1696 | * | |
cb8d4c8f | 1697 | * It is valid to call this function only for properties that |
5114e842 EH |
1698 | * are already present in the kvm_default_props table. |
1699 | */ | |
1700 | void x86_cpu_change_kvm_default(const char *prop, const char *value); | |
8fb4f821 | 1701 | |
f4f1110e RH |
1702 | /* mpx_helper.c */ |
1703 | void cpu_sync_bndcs_hflags(CPUX86State *env); | |
0668af54 | 1704 | |
8b4beddc EH |
1705 | /* Return name of 32-bit register, from a R_* constant */ |
1706 | const char *get_register_name_32(unsigned int reg); | |
1707 | ||
8932cfdf | 1708 | void enable_compat_apic_id_mode(void); |
cb41bad3 | 1709 | |
dab86234 | 1710 | #define APIC_DEFAULT_ADDRESS 0xfee00000 |
baaeda08 | 1711 | #define APIC_SPACE_SIZE 0x100000 |
dab86234 | 1712 | |
1f871d49 PB |
1713 | void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, |
1714 | fprintf_function cpu_fprintf, int flags); | |
1715 | ||
d613f8cc PB |
1716 | /* cpu.c */ |
1717 | bool cpu_is_bsp(X86CPU *cpu); | |
1718 | ||
86a57621 SAGDR |
1719 | void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); |
1720 | void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); | |
07f5a258 | 1721 | #endif /* I386_CPU_H */ |