]>
Commit | Line | Data |
---|---|---|
e13713db | 1 | |
2c0262af FB |
2 | /* |
3 | * i386 virtual CPU header | |
5fafdf24 | 4 | * |
2c0262af FB |
5 | * Copyright (c) 2003 Fabrice Bellard |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 19 | */ |
07f5a258 MA |
20 | |
21 | #ifndef I386_CPU_H | |
22 | #define I386_CPU_H | |
2c0262af | 23 | |
9a78eead | 24 | #include "qemu-common.h" |
4da6f8d9 | 25 | #include "cpu-qom.h" |
5e953812 | 26 | #include "hyperv-proto.h" |
14ce26e7 FB |
27 | |
28 | #ifdef TARGET_X86_64 | |
29 | #define TARGET_LONG_BITS 64 | |
30 | #else | |
3cf1e035 | 31 | #define TARGET_LONG_BITS 32 |
14ce26e7 | 32 | #endif |
3cf1e035 | 33 | |
c97d6d2c SAGDR |
34 | #include "exec/cpu-defs.h" |
35 | ||
72c1701f AB |
36 | /* The x86 has a strong memory model with some store-after-load re-ordering */ |
37 | #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) | |
38 | ||
5b9efc39 PD |
39 | /* Maximum instruction code size */ |
40 | #define TARGET_MAX_INSN_SIZE 16 | |
41 | ||
d720b93d FB |
42 | /* support for self modifying code even if the modified instruction is |
43 | close to the modifying instruction */ | |
44 | #define TARGET_HAS_PRECISE_SMC | |
45 | ||
9042c0e2 | 46 | #ifdef TARGET_X86_64 |
a5e8788f | 47 | #define I386_ELF_MACHINE EM_X86_64 |
4ab23a91 | 48 | #define ELF_MACHINE_UNAME "x86_64" |
9042c0e2 | 49 | #else |
a5e8788f | 50 | #define I386_ELF_MACHINE EM_386 |
4ab23a91 | 51 | #define ELF_MACHINE_UNAME "i686" |
9042c0e2 TS |
52 | #endif |
53 | ||
9349b4f9 | 54 | #define CPUArchState struct CPUX86State |
c2764719 | 55 | |
6701d81d PB |
56 | enum { |
57 | R_EAX = 0, | |
58 | R_ECX = 1, | |
59 | R_EDX = 2, | |
60 | R_EBX = 3, | |
61 | R_ESP = 4, | |
62 | R_EBP = 5, | |
63 | R_ESI = 6, | |
64 | R_EDI = 7, | |
65 | R_R8 = 8, | |
66 | R_R9 = 9, | |
67 | R_R10 = 10, | |
68 | R_R11 = 11, | |
69 | R_R12 = 12, | |
70 | R_R13 = 13, | |
71 | R_R14 = 14, | |
72 | R_R15 = 15, | |
2c0262af | 73 | |
6701d81d PB |
74 | R_AL = 0, |
75 | R_CL = 1, | |
76 | R_DL = 2, | |
77 | R_BL = 3, | |
78 | R_AH = 4, | |
79 | R_CH = 5, | |
80 | R_DH = 6, | |
81 | R_BH = 7, | |
82 | }; | |
2c0262af | 83 | |
6701d81d PB |
84 | typedef enum X86Seg { |
85 | R_ES = 0, | |
86 | R_CS = 1, | |
87 | R_SS = 2, | |
88 | R_DS = 3, | |
89 | R_FS = 4, | |
90 | R_GS = 5, | |
91 | R_LDTR = 6, | |
92 | R_TR = 7, | |
93 | } X86Seg; | |
2c0262af FB |
94 | |
95 | /* segment descriptor fields */ | |
c97d6d2c SAGDR |
96 | #define DESC_G_SHIFT 23 |
97 | #define DESC_G_MASK (1 << DESC_G_SHIFT) | |
2c0262af FB |
98 | #define DESC_B_SHIFT 22 |
99 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
14ce26e7 FB |
100 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
101 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
c97d6d2c SAGDR |
102 | #define DESC_AVL_SHIFT 20 |
103 | #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) | |
104 | #define DESC_P_SHIFT 15 | |
105 | #define DESC_P_MASK (1 << DESC_P_SHIFT) | |
2c0262af | 106 | #define DESC_DPL_SHIFT 13 |
a3867ed2 | 107 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
c97d6d2c SAGDR |
108 | #define DESC_S_SHIFT 12 |
109 | #define DESC_S_MASK (1 << DESC_S_SHIFT) | |
2c0262af | 110 | #define DESC_TYPE_SHIFT 8 |
a3867ed2 | 111 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
2c0262af FB |
112 | #define DESC_A_MASK (1 << 8) |
113 | ||
e670b89e FB |
114 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
115 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
116 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
2c0262af | 117 | |
e670b89e FB |
118 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
119 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
120 | ||
121 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
2c0262af FB |
122 | |
123 | /* eflags masks */ | |
e4a09c96 PB |
124 | #define CC_C 0x0001 |
125 | #define CC_P 0x0004 | |
126 | #define CC_A 0x0010 | |
127 | #define CC_Z 0x0040 | |
2c0262af FB |
128 | #define CC_S 0x0080 |
129 | #define CC_O 0x0800 | |
130 | ||
131 | #define TF_SHIFT 8 | |
132 | #define IOPL_SHIFT 12 | |
133 | #define VM_SHIFT 17 | |
134 | ||
e4a09c96 PB |
135 | #define TF_MASK 0x00000100 |
136 | #define IF_MASK 0x00000200 | |
137 | #define DF_MASK 0x00000400 | |
138 | #define IOPL_MASK 0x00003000 | |
139 | #define NT_MASK 0x00004000 | |
140 | #define RF_MASK 0x00010000 | |
141 | #define VM_MASK 0x00020000 | |
142 | #define AC_MASK 0x00040000 | |
2c0262af FB |
143 | #define VIF_MASK 0x00080000 |
144 | #define VIP_MASK 0x00100000 | |
145 | #define ID_MASK 0x00200000 | |
146 | ||
aa1f17c1 | 147 | /* hidden flags - used internally by qemu to represent additional cpu |
7848c8d1 KC |
148 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We |
149 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit | |
150 | positions to ease oring with eflags. */ | |
2c0262af FB |
151 | /* current cpl */ |
152 | #define HF_CPL_SHIFT 0 | |
2c0262af FB |
153 | /* true if hardware interrupts must be disabled for next instruction */ |
154 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
155 | /* 16 or 32 segments */ | |
156 | #define HF_CS32_SHIFT 4 | |
157 | #define HF_SS32_SHIFT 5 | |
dc196a57 | 158 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
2c0262af | 159 | #define HF_ADDSEG_SHIFT 6 |
65262d57 FB |
160 | /* copy of CR0.PE (protected mode) */ |
161 | #define HF_PE_SHIFT 7 | |
162 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
7eee2a50 FB |
163 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
164 | #define HF_EM_SHIFT 10 | |
165 | #define HF_TS_SHIFT 11 | |
65262d57 | 166 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
14ce26e7 FB |
167 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
168 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
a2397807 | 169 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
65262d57 | 170 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
a9321a4d | 171 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
3b21e03e | 172 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
db620f46 | 173 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
f8dc4c64 | 174 | #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ |
a2397807 | 175 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
a9321a4d | 176 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
5223a942 | 177 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ |
f4f1110e RH |
178 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ |
179 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ | |
2c0262af FB |
180 | |
181 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
2c0262af FB |
182 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
183 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
184 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
185 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
65262d57 | 186 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
58fe2f10 | 187 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
7eee2a50 FB |
188 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
189 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
190 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
0650f1ab | 191 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
14ce26e7 FB |
192 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
193 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
a2397807 | 194 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
0650f1ab | 195 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
a9321a4d | 196 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
3b21e03e | 197 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
872929aa | 198 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
f8dc4c64 | 199 | #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) |
a2397807 | 200 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
a9321a4d | 201 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
5223a942 | 202 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) |
f4f1110e RH |
203 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) |
204 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) | |
2c0262af | 205 | |
db620f46 FB |
206 | /* hflags2 */ |
207 | ||
9982f74b PB |
208 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
209 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
210 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
211 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
212 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ | |
f4f1110e | 213 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ |
fe441054 | 214 | #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ |
9982f74b PB |
215 | |
216 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
217 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
218 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
219 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
220 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) | |
f4f1110e | 221 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) |
fe441054 | 222 | #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) |
db620f46 | 223 | |
0650f1ab AL |
224 | #define CR0_PE_SHIFT 0 |
225 | #define CR0_MP_SHIFT 1 | |
226 | ||
2cd49cbf PM |
227 | #define CR0_PE_MASK (1U << 0) |
228 | #define CR0_MP_MASK (1U << 1) | |
229 | #define CR0_EM_MASK (1U << 2) | |
230 | #define CR0_TS_MASK (1U << 3) | |
231 | #define CR0_ET_MASK (1U << 4) | |
232 | #define CR0_NE_MASK (1U << 5) | |
233 | #define CR0_WP_MASK (1U << 16) | |
234 | #define CR0_AM_MASK (1U << 18) | |
235 | #define CR0_PG_MASK (1U << 31) | |
236 | ||
237 | #define CR4_VME_MASK (1U << 0) | |
238 | #define CR4_PVI_MASK (1U << 1) | |
239 | #define CR4_TSD_MASK (1U << 2) | |
240 | #define CR4_DE_MASK (1U << 3) | |
241 | #define CR4_PSE_MASK (1U << 4) | |
242 | #define CR4_PAE_MASK (1U << 5) | |
243 | #define CR4_MCE_MASK (1U << 6) | |
244 | #define CR4_PGE_MASK (1U << 7) | |
245 | #define CR4_PCE_MASK (1U << 8) | |
0650f1ab | 246 | #define CR4_OSFXSR_SHIFT 9 |
2cd49cbf PM |
247 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) |
248 | #define CR4_OSXMMEXCPT_MASK (1U << 10) | |
6c7c3c21 | 249 | #define CR4_LA57_MASK (1U << 12) |
2cd49cbf PM |
250 | #define CR4_VMXE_MASK (1U << 13) |
251 | #define CR4_SMXE_MASK (1U << 14) | |
252 | #define CR4_FSGSBASE_MASK (1U << 16) | |
253 | #define CR4_PCIDE_MASK (1U << 17) | |
254 | #define CR4_OSXSAVE_MASK (1U << 18) | |
255 | #define CR4_SMEP_MASK (1U << 20) | |
256 | #define CR4_SMAP_MASK (1U << 21) | |
0f70ed47 | 257 | #define CR4_PKE_MASK (1U << 22) |
2c0262af | 258 | |
01df040b AL |
259 | #define DR6_BD (1 << 13) |
260 | #define DR6_BS (1 << 14) | |
261 | #define DR6_BT (1 << 15) | |
262 | #define DR6_FIXED_1 0xffff0ff0 | |
263 | ||
264 | #define DR7_GD (1 << 13) | |
265 | #define DR7_TYPE_SHIFT 16 | |
266 | #define DR7_LEN_SHIFT 18 | |
267 | #define DR7_FIXED_1 0x00000400 | |
93d00d0f | 268 | #define DR7_GLOBAL_BP_MASK 0xaa |
428065ce LG |
269 | #define DR7_LOCAL_BP_MASK 0x55 |
270 | #define DR7_MAX_BP 4 | |
271 | #define DR7_TYPE_BP_INST 0x0 | |
272 | #define DR7_TYPE_DATA_WR 0x1 | |
273 | #define DR7_TYPE_IO_RW 0x2 | |
274 | #define DR7_TYPE_DATA_RW 0x3 | |
01df040b | 275 | |
e4a09c96 PB |
276 | #define PG_PRESENT_BIT 0 |
277 | #define PG_RW_BIT 1 | |
278 | #define PG_USER_BIT 2 | |
279 | #define PG_PWT_BIT 3 | |
280 | #define PG_PCD_BIT 4 | |
281 | #define PG_ACCESSED_BIT 5 | |
282 | #define PG_DIRTY_BIT 6 | |
283 | #define PG_PSE_BIT 7 | |
284 | #define PG_GLOBAL_BIT 8 | |
eaad03e4 | 285 | #define PG_PSE_PAT_BIT 12 |
0f70ed47 | 286 | #define PG_PKRU_BIT 59 |
e4a09c96 | 287 | #define PG_NX_BIT 63 |
2c0262af FB |
288 | |
289 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
e4a09c96 PB |
290 | #define PG_RW_MASK (1 << PG_RW_BIT) |
291 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
292 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
293 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
2c0262af | 294 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
e4a09c96 PB |
295 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
296 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
297 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
eaad03e4 | 298 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) |
e8f6d00c PB |
299 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL |
300 | #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) | |
3f2cbf0d | 301 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
0f70ed47 PB |
302 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) |
303 | #define PG_NX_MASK (1ULL << PG_NX_BIT) | |
2c0262af FB |
304 | |
305 | #define PG_ERROR_W_BIT 1 | |
306 | ||
307 | #define PG_ERROR_P_MASK 0x01 | |
308 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
309 | #define PG_ERROR_U_MASK 0x04 | |
310 | #define PG_ERROR_RSVD_MASK 0x08 | |
5cf38396 | 311 | #define PG_ERROR_I_D_MASK 0x10 |
0f70ed47 | 312 | #define PG_ERROR_PK_MASK 0x20 |
2c0262af | 313 | |
e4a09c96 PB |
314 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
315 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
87f8b626 | 316 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ |
79c4f6b0 | 317 | |
e4a09c96 PB |
318 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
319 | #define MCE_BANKS_DEF 10 | |
79c4f6b0 | 320 | |
2590f15b EH |
321 | #define MCG_CAP_BANKS_MASK 0xff |
322 | ||
e4a09c96 PB |
323 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
324 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
325 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
87f8b626 AR |
326 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ |
327 | ||
328 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ | |
79c4f6b0 | 329 | |
e4a09c96 PB |
330 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
331 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
332 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
333 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
334 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
335 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
336 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
337 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
338 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
c0532a76 MT |
339 | |
340 | /* MISC register defines */ | |
e4a09c96 PB |
341 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
342 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
343 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
344 | #define MCM_ADDR_MEM 3 /* memory address */ | |
345 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
79c4f6b0 | 346 | |
0650f1ab | 347 | #define MSR_IA32_TSC 0x10 |
2c0262af FB |
348 | #define MSR_IA32_APICBASE 0x1b |
349 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
350 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
33d7a288 | 351 | #define MSR_IA32_APICBASE_EXTD (1 << 10) |
458cf469 | 352 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) |
0779caeb | 353 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
f28558d3 | 354 | #define MSR_TSC_ADJUST 0x0000003b |
a33a2cfe | 355 | #define MSR_IA32_SPEC_CTRL 0x48 |
cfeea0c0 | 356 | #define MSR_VIRT_SSBD 0xc001011f |
8c80c99f RH |
357 | #define MSR_IA32_PRED_CMD 0x49 |
358 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a | |
aa82ba54 | 359 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
2c0262af | 360 | |
217f1b4a HZ |
361 | #define FEATURE_CONTROL_LOCKED (1<<0) |
362 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) | |
363 | #define FEATURE_CONTROL_LMCE (1<<20) | |
364 | ||
0d894367 PB |
365 | #define MSR_P6_PERFCTR0 0xc1 |
366 | ||
fc12d72e | 367 | #define MSR_IA32_SMBASE 0x9e |
e13713db | 368 | #define MSR_SMI_COUNT 0x34 |
e4a09c96 PB |
369 | #define MSR_MTRRcap 0xfe |
370 | #define MSR_MTRRcap_VCNT 8 | |
371 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
372 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
dd5e3b17 | 373 | |
2c0262af FB |
374 | #define MSR_IA32_SYSENTER_CS 0x174 |
375 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
376 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
377 | ||
8f091a59 FB |
378 | #define MSR_MCG_CAP 0x179 |
379 | #define MSR_MCG_STATUS 0x17a | |
380 | #define MSR_MCG_CTL 0x17b | |
87f8b626 | 381 | #define MSR_MCG_EXT_CTL 0x4d0 |
8f091a59 | 382 | |
0d894367 PB |
383 | #define MSR_P6_EVNTSEL0 0x186 |
384 | ||
e737b32a AZ |
385 | #define MSR_IA32_PERF_STATUS 0x198 |
386 | ||
e4a09c96 | 387 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
21e87c46 AK |
388 | /* Indicates good rep/movs microcode on some processors: */ |
389 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
390 | ||
e4a09c96 PB |
391 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
392 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
393 | ||
d1ae67f6 AW |
394 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) |
395 | ||
e4a09c96 PB |
396 | #define MSR_MTRRfix64K_00000 0x250 |
397 | #define MSR_MTRRfix16K_80000 0x258 | |
398 | #define MSR_MTRRfix16K_A0000 0x259 | |
399 | #define MSR_MTRRfix4K_C0000 0x268 | |
400 | #define MSR_MTRRfix4K_C8000 0x269 | |
401 | #define MSR_MTRRfix4K_D0000 0x26a | |
402 | #define MSR_MTRRfix4K_D8000 0x26b | |
403 | #define MSR_MTRRfix4K_E0000 0x26c | |
404 | #define MSR_MTRRfix4K_E8000 0x26d | |
405 | #define MSR_MTRRfix4K_F0000 0x26e | |
406 | #define MSR_MTRRfix4K_F8000 0x26f | |
165d9b82 | 407 | |
8f091a59 FB |
408 | #define MSR_PAT 0x277 |
409 | ||
e4a09c96 | 410 | #define MSR_MTRRdefType 0x2ff |
165d9b82 | 411 | |
0d894367 PB |
412 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 |
413 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | |
414 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | |
415 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | |
416 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | |
417 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | |
418 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | |
165d9b82 | 419 | |
e4a09c96 PB |
420 | #define MSR_MC0_CTL 0x400 |
421 | #define MSR_MC0_STATUS 0x401 | |
422 | #define MSR_MC0_ADDR 0x402 | |
423 | #define MSR_MC0_MISC 0x403 | |
79c4f6b0 | 424 | |
b77146e9 CP |
425 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 |
426 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 | |
427 | #define MSR_IA32_RTIT_CTL 0x570 | |
428 | #define MSR_IA32_RTIT_STATUS 0x571 | |
429 | #define MSR_IA32_RTIT_CR3_MATCH 0x572 | |
430 | #define MSR_IA32_RTIT_ADDR0_A 0x580 | |
431 | #define MSR_IA32_RTIT_ADDR0_B 0x581 | |
432 | #define MSR_IA32_RTIT_ADDR1_A 0x582 | |
433 | #define MSR_IA32_RTIT_ADDR1_B 0x583 | |
434 | #define MSR_IA32_RTIT_ADDR2_A 0x584 | |
435 | #define MSR_IA32_RTIT_ADDR2_B 0x585 | |
436 | #define MSR_IA32_RTIT_ADDR3_A 0x586 | |
437 | #define MSR_IA32_RTIT_ADDR3_B 0x587 | |
438 | #define MAX_RTIT_ADDRS 8 | |
439 | ||
14ce26e7 FB |
440 | #define MSR_EFER 0xc0000080 |
441 | ||
442 | #define MSR_EFER_SCE (1 << 0) | |
443 | #define MSR_EFER_LME (1 << 8) | |
444 | #define MSR_EFER_LMA (1 << 10) | |
445 | #define MSR_EFER_NXE (1 << 11) | |
872929aa | 446 | #define MSR_EFER_SVME (1 << 12) |
14ce26e7 FB |
447 | #define MSR_EFER_FFXSR (1 << 14) |
448 | ||
449 | #define MSR_STAR 0xc0000081 | |
450 | #define MSR_LSTAR 0xc0000082 | |
451 | #define MSR_CSTAR 0xc0000083 | |
452 | #define MSR_FMASK 0xc0000084 | |
453 | #define MSR_FSBASE 0xc0000100 | |
454 | #define MSR_GSBASE 0xc0000101 | |
455 | #define MSR_KERNELGSBASE 0xc0000102 | |
1b050077 | 456 | #define MSR_TSC_AUX 0xc0000103 |
14ce26e7 | 457 | |
0573fbfc TS |
458 | #define MSR_VM_HSAVE_PA 0xc0010117 |
459 | ||
79e9ebeb | 460 | #define MSR_IA32_BNDCFGS 0x00000d90 |
18cd2c17 | 461 | #define MSR_IA32_XSS 0x00000da0 |
79e9ebeb | 462 | |
cfc3b074 PB |
463 | #define XSTATE_FP_BIT 0 |
464 | #define XSTATE_SSE_BIT 1 | |
465 | #define XSTATE_YMM_BIT 2 | |
466 | #define XSTATE_BNDREGS_BIT 3 | |
467 | #define XSTATE_BNDCSR_BIT 4 | |
468 | #define XSTATE_OPMASK_BIT 5 | |
469 | #define XSTATE_ZMM_Hi256_BIT 6 | |
470 | #define XSTATE_Hi16_ZMM_BIT 7 | |
471 | #define XSTATE_PKRU_BIT 9 | |
472 | ||
473 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) | |
474 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) | |
475 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) | |
476 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) | |
477 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) | |
478 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) | |
479 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) | |
480 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) | |
481 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) | |
c74f41bb | 482 | |
5ef57876 EH |
483 | /* CPUID feature words */ |
484 | typedef enum FeatureWord { | |
485 | FEAT_1_EDX, /* CPUID[1].EDX */ | |
486 | FEAT_1_ECX, /* CPUID[1].ECX */ | |
487 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ | |
f74eefe0 | 488 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ |
95ea69fb | 489 | FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ |
5ef57876 EH |
490 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
491 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ | |
303752a9 | 492 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ |
1b3420e1 | 493 | FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ |
5ef57876 EH |
494 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
495 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ | |
be777326 | 496 | FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ |
c35bd19a EY |
497 | FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ |
498 | FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ | |
499 | FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ | |
a2b107db VK |
500 | FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ |
501 | FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ | |
5ef57876 | 502 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
0bb0b2d2 | 503 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ |
28b8e4d0 | 504 | FEAT_6_EAX, /* CPUID[6].EAX */ |
96193c22 EH |
505 | FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ |
506 | FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ | |
d86f9636 | 507 | FEAT_ARCH_CAPABILITIES, |
5ef57876 EH |
508 | FEATURE_WORDS, |
509 | } FeatureWord; | |
510 | ||
511 | typedef uint32_t FeatureWordArray[FEATURE_WORDS]; | |
512 | ||
14ce26e7 | 513 | /* cpuid_features bits */ |
2cd49cbf PM |
514 | #define CPUID_FP87 (1U << 0) |
515 | #define CPUID_VME (1U << 1) | |
516 | #define CPUID_DE (1U << 2) | |
517 | #define CPUID_PSE (1U << 3) | |
518 | #define CPUID_TSC (1U << 4) | |
519 | #define CPUID_MSR (1U << 5) | |
520 | #define CPUID_PAE (1U << 6) | |
521 | #define CPUID_MCE (1U << 7) | |
522 | #define CPUID_CX8 (1U << 8) | |
523 | #define CPUID_APIC (1U << 9) | |
524 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ | |
525 | #define CPUID_MTRR (1U << 12) | |
526 | #define CPUID_PGE (1U << 13) | |
527 | #define CPUID_MCA (1U << 14) | |
528 | #define CPUID_CMOV (1U << 15) | |
529 | #define CPUID_PAT (1U << 16) | |
530 | #define CPUID_PSE36 (1U << 17) | |
531 | #define CPUID_PN (1U << 18) | |
532 | #define CPUID_CLFLUSH (1U << 19) | |
533 | #define CPUID_DTS (1U << 21) | |
534 | #define CPUID_ACPI (1U << 22) | |
535 | #define CPUID_MMX (1U << 23) | |
536 | #define CPUID_FXSR (1U << 24) | |
537 | #define CPUID_SSE (1U << 25) | |
538 | #define CPUID_SSE2 (1U << 26) | |
539 | #define CPUID_SS (1U << 27) | |
540 | #define CPUID_HT (1U << 28) | |
541 | #define CPUID_TM (1U << 29) | |
542 | #define CPUID_IA64 (1U << 30) | |
543 | #define CPUID_PBE (1U << 31) | |
544 | ||
545 | #define CPUID_EXT_SSE3 (1U << 0) | |
546 | #define CPUID_EXT_PCLMULQDQ (1U << 1) | |
547 | #define CPUID_EXT_DTES64 (1U << 2) | |
548 | #define CPUID_EXT_MONITOR (1U << 3) | |
549 | #define CPUID_EXT_DSCPL (1U << 4) | |
550 | #define CPUID_EXT_VMX (1U << 5) | |
551 | #define CPUID_EXT_SMX (1U << 6) | |
552 | #define CPUID_EXT_EST (1U << 7) | |
553 | #define CPUID_EXT_TM2 (1U << 8) | |
554 | #define CPUID_EXT_SSSE3 (1U << 9) | |
555 | #define CPUID_EXT_CID (1U << 10) | |
556 | #define CPUID_EXT_FMA (1U << 12) | |
557 | #define CPUID_EXT_CX16 (1U << 13) | |
558 | #define CPUID_EXT_XTPR (1U << 14) | |
559 | #define CPUID_EXT_PDCM (1U << 15) | |
560 | #define CPUID_EXT_PCID (1U << 17) | |
561 | #define CPUID_EXT_DCA (1U << 18) | |
562 | #define CPUID_EXT_SSE41 (1U << 19) | |
563 | #define CPUID_EXT_SSE42 (1U << 20) | |
564 | #define CPUID_EXT_X2APIC (1U << 21) | |
565 | #define CPUID_EXT_MOVBE (1U << 22) | |
566 | #define CPUID_EXT_POPCNT (1U << 23) | |
567 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) | |
568 | #define CPUID_EXT_AES (1U << 25) | |
569 | #define CPUID_EXT_XSAVE (1U << 26) | |
570 | #define CPUID_EXT_OSXSAVE (1U << 27) | |
571 | #define CPUID_EXT_AVX (1U << 28) | |
572 | #define CPUID_EXT_F16C (1U << 29) | |
573 | #define CPUID_EXT_RDRAND (1U << 30) | |
574 | #define CPUID_EXT_HYPERVISOR (1U << 31) | |
575 | ||
576 | #define CPUID_EXT2_FPU (1U << 0) | |
577 | #define CPUID_EXT2_VME (1U << 1) | |
578 | #define CPUID_EXT2_DE (1U << 2) | |
579 | #define CPUID_EXT2_PSE (1U << 3) | |
580 | #define CPUID_EXT2_TSC (1U << 4) | |
581 | #define CPUID_EXT2_MSR (1U << 5) | |
582 | #define CPUID_EXT2_PAE (1U << 6) | |
583 | #define CPUID_EXT2_MCE (1U << 7) | |
584 | #define CPUID_EXT2_CX8 (1U << 8) | |
585 | #define CPUID_EXT2_APIC (1U << 9) | |
586 | #define CPUID_EXT2_SYSCALL (1U << 11) | |
587 | #define CPUID_EXT2_MTRR (1U << 12) | |
588 | #define CPUID_EXT2_PGE (1U << 13) | |
589 | #define CPUID_EXT2_MCA (1U << 14) | |
590 | #define CPUID_EXT2_CMOV (1U << 15) | |
591 | #define CPUID_EXT2_PAT (1U << 16) | |
592 | #define CPUID_EXT2_PSE36 (1U << 17) | |
593 | #define CPUID_EXT2_MP (1U << 19) | |
594 | #define CPUID_EXT2_NX (1U << 20) | |
595 | #define CPUID_EXT2_MMXEXT (1U << 22) | |
596 | #define CPUID_EXT2_MMX (1U << 23) | |
597 | #define CPUID_EXT2_FXSR (1U << 24) | |
598 | #define CPUID_EXT2_FFXSR (1U << 25) | |
599 | #define CPUID_EXT2_PDPE1GB (1U << 26) | |
600 | #define CPUID_EXT2_RDTSCP (1U << 27) | |
601 | #define CPUID_EXT2_LM (1U << 29) | |
602 | #define CPUID_EXT2_3DNOWEXT (1U << 30) | |
603 | #define CPUID_EXT2_3DNOW (1U << 31) | |
9df217a3 | 604 | |
8fad4b44 EH |
605 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ |
606 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ | |
607 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
608 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
609 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
610 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
611 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
612 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
613 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
614 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
615 | ||
2cd49cbf PM |
616 | #define CPUID_EXT3_LAHF_LM (1U << 0) |
617 | #define CPUID_EXT3_CMP_LEG (1U << 1) | |
618 | #define CPUID_EXT3_SVM (1U << 2) | |
619 | #define CPUID_EXT3_EXTAPIC (1U << 3) | |
620 | #define CPUID_EXT3_CR8LEG (1U << 4) | |
621 | #define CPUID_EXT3_ABM (1U << 5) | |
622 | #define CPUID_EXT3_SSE4A (1U << 6) | |
623 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) | |
624 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) | |
625 | #define CPUID_EXT3_OSVW (1U << 9) | |
626 | #define CPUID_EXT3_IBS (1U << 10) | |
627 | #define CPUID_EXT3_XOP (1U << 11) | |
628 | #define CPUID_EXT3_SKINIT (1U << 12) | |
629 | #define CPUID_EXT3_WDT (1U << 13) | |
630 | #define CPUID_EXT3_LWP (1U << 15) | |
631 | #define CPUID_EXT3_FMA4 (1U << 16) | |
632 | #define CPUID_EXT3_TCE (1U << 17) | |
633 | #define CPUID_EXT3_NODEID (1U << 19) | |
634 | #define CPUID_EXT3_TBM (1U << 21) | |
635 | #define CPUID_EXT3_TOPOEXT (1U << 22) | |
636 | #define CPUID_EXT3_PERFCORE (1U << 23) | |
637 | #define CPUID_EXT3_PERFNB (1U << 24) | |
638 | ||
639 | #define CPUID_SVM_NPT (1U << 0) | |
640 | #define CPUID_SVM_LBRV (1U << 1) | |
641 | #define CPUID_SVM_SVMLOCK (1U << 2) | |
642 | #define CPUID_SVM_NRIPSAVE (1U << 3) | |
643 | #define CPUID_SVM_TSCSCALE (1U << 4) | |
644 | #define CPUID_SVM_VMCBCLEAN (1U << 5) | |
645 | #define CPUID_SVM_FLUSHASID (1U << 6) | |
646 | #define CPUID_SVM_DECODEASSIST (1U << 7) | |
647 | #define CPUID_SVM_PAUSEFILTER (1U << 10) | |
648 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) | |
649 | ||
650 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) | |
651 | #define CPUID_7_0_EBX_BMI1 (1U << 3) | |
652 | #define CPUID_7_0_EBX_HLE (1U << 4) | |
653 | #define CPUID_7_0_EBX_AVX2 (1U << 5) | |
654 | #define CPUID_7_0_EBX_SMEP (1U << 7) | |
655 | #define CPUID_7_0_EBX_BMI2 (1U << 8) | |
656 | #define CPUID_7_0_EBX_ERMS (1U << 9) | |
657 | #define CPUID_7_0_EBX_INVPCID (1U << 10) | |
658 | #define CPUID_7_0_EBX_RTM (1U << 11) | |
659 | #define CPUID_7_0_EBX_MPX (1U << 14) | |
9aecd6f8 | 660 | #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ |
cc728d14 | 661 | #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */ |
2cd49cbf PM |
662 | #define CPUID_7_0_EBX_RDSEED (1U << 18) |
663 | #define CPUID_7_0_EBX_ADX (1U << 19) | |
664 | #define CPUID_7_0_EBX_SMAP (1U << 20) | |
cc728d14 | 665 | #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */ |
f7fda280 XG |
666 | #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ |
667 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ | |
668 | #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ | |
e37a5c7f | 669 | #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ |
9aecd6f8 CP |
670 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ |
671 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ | |
672 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ | |
638cbd45 | 673 | #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */ |
cc728d14 LK |
674 | #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */ |
675 | #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */ | |
a9321a4d | 676 | |
c97d6d2c | 677 | #define CPUID_7_0_ECX_AVX512BMI (1U << 1) |
cc728d14 | 678 | #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */ |
c2f193b5 | 679 | #define CPUID_7_0_ECX_UMIP (1U << 2) |
f74eefe0 HH |
680 | #define CPUID_7_0_ECX_PKU (1U << 3) |
681 | #define CPUID_7_0_ECX_OSPKE (1U << 4) | |
aff9e6e4 YZ |
682 | #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ |
683 | #define CPUID_7_0_ECX_GFNI (1U << 8) | |
684 | #define CPUID_7_0_ECX_VAES (1U << 9) | |
685 | #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) | |
686 | #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) | |
687 | #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) | |
f7754377 | 688 | #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ |
6c7c3c21 | 689 | #define CPUID_7_0_ECX_LA57 (1U << 16) |
c2f193b5 | 690 | #define CPUID_7_0_ECX_RDPID (1U << 22) |
0da0fb06 | 691 | #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ |
24261de4 | 692 | #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ |
1c65775f | 693 | #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ |
f74eefe0 | 694 | |
95ea69fb LK |
695 | #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ |
696 | #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ | |
5131dc43 | 697 | #define CPUID_7_0_EDX_PCONFIG (1U << 18) /* Platform Configuration */ |
a2381f09 | 698 | #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ |
3fc7c731 | 699 | #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ |
d19d1f96 | 700 | #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ |
95ea69fb | 701 | |
59a80a19 RH |
702 | #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and |
703 | do not invalidate cache */ | |
1b3420e1 EH |
704 | #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ |
705 | ||
0bb0b2d2 PB |
706 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) |
707 | #define CPUID_XSAVE_XSAVEC (1U << 1) | |
708 | #define CPUID_XSAVE_XGETBV1 (1U << 2) | |
709 | #define CPUID_XSAVE_XSAVES (1U << 3) | |
710 | ||
28b8e4d0 JK |
711 | #define CPUID_6_EAX_ARAT (1U << 2) |
712 | ||
303752a9 MT |
713 | /* CPUID[0x80000007].EDX flags: */ |
714 | #define CPUID_APM_INVTSC (1U << 8) | |
715 | ||
9df694ee IM |
716 | #define CPUID_VENDOR_SZ 12 |
717 | ||
c5096daf AZ |
718 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
719 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
720 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
99b88a17 | 721 | #define CPUID_VENDOR_INTEL "GenuineIntel" |
c5096daf AZ |
722 | |
723 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
b3baa152 | 724 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
c5096daf | 725 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
99b88a17 | 726 | #define CPUID_VENDOR_AMD "AuthenticAMD" |
c5096daf | 727 | |
99b88a17 | 728 | #define CPUID_VENDOR_VIA "CentaurHauls" |
b3baa152 | 729 | |
2cd49cbf PM |
730 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ |
731 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ | |
e737b32a | 732 | |
5232d00a RK |
733 | /* CPUID[0xB].ECX level types */ |
734 | #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) | |
735 | #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) | |
736 | #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) | |
737 | ||
d86f9636 RH |
738 | /* MSR Feature Bits */ |
739 | #define MSR_ARCH_CAP_RDCL_NO (1U << 0) | |
740 | #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) | |
741 | #define MSR_ARCH_CAP_RSBA (1U << 2) | |
742 | #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) | |
743 | #define MSR_ARCH_CAP_SSB_NO (1U << 4) | |
744 | ||
92067bf4 IM |
745 | #ifndef HYPERV_SPINLOCK_NEVER_RETRY |
746 | #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF | |
747 | #endif | |
748 | ||
2c0262af | 749 | #define EXCP00_DIVZ 0 |
01df040b | 750 | #define EXCP01_DB 1 |
2c0262af FB |
751 | #define EXCP02_NMI 2 |
752 | #define EXCP03_INT3 3 | |
753 | #define EXCP04_INTO 4 | |
754 | #define EXCP05_BOUND 5 | |
755 | #define EXCP06_ILLOP 6 | |
756 | #define EXCP07_PREX 7 | |
757 | #define EXCP08_DBLE 8 | |
758 | #define EXCP09_XERR 9 | |
759 | #define EXCP0A_TSS 10 | |
760 | #define EXCP0B_NOSEG 11 | |
761 | #define EXCP0C_STACK 12 | |
762 | #define EXCP0D_GPF 13 | |
763 | #define EXCP0E_PAGE 14 | |
764 | #define EXCP10_COPR 16 | |
765 | #define EXCP11_ALGN 17 | |
766 | #define EXCP12_MCHK 18 | |
767 | ||
d2fd1af7 FB |
768 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
769 | for syscall instruction */ | |
10cde894 | 770 | #define EXCP_VMEXIT 0x100 |
d2fd1af7 | 771 | |
00a152b4 | 772 | /* i386-specific interrupt pending bits. */ |
5d62c43a | 773 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
00a152b4 | 774 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
85097db6 | 775 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
00a152b4 RH |
776 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
777 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
4a92a558 PB |
778 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 |
779 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 | |
00a152b4 | 780 | |
4a92a558 PB |
781 | /* Use a clearer name for this. */ |
782 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET | |
00a152b4 | 783 | |
c3ce5a23 PB |
784 | /* Instead of computing the condition codes after each x86 instruction, |
785 | * QEMU just stores one operand (called CC_SRC), the result | |
786 | * (called CC_DST) and the type of operation (called CC_OP). When the | |
787 | * condition codes are needed, the condition codes can be calculated | |
788 | * using this information. Condition codes are not generated if they | |
789 | * are only needed for conditional branches. | |
790 | */ | |
fee71888 | 791 | typedef enum { |
2c0262af | 792 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
1235fc06 | 793 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
d36cd60e FB |
794 | |
795 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
796 | CC_OP_MULW, | |
797 | CC_OP_MULL, | |
14ce26e7 | 798 | CC_OP_MULQ, |
2c0262af FB |
799 | |
800 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
801 | CC_OP_ADDW, | |
802 | CC_OP_ADDL, | |
14ce26e7 | 803 | CC_OP_ADDQ, |
2c0262af FB |
804 | |
805 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
806 | CC_OP_ADCW, | |
807 | CC_OP_ADCL, | |
14ce26e7 | 808 | CC_OP_ADCQ, |
2c0262af FB |
809 | |
810 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
811 | CC_OP_SUBW, | |
812 | CC_OP_SUBL, | |
14ce26e7 | 813 | CC_OP_SUBQ, |
2c0262af FB |
814 | |
815 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
816 | CC_OP_SBBW, | |
817 | CC_OP_SBBL, | |
14ce26e7 | 818 | CC_OP_SBBQ, |
2c0262af FB |
819 | |
820 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
821 | CC_OP_LOGICW, | |
822 | CC_OP_LOGICL, | |
14ce26e7 | 823 | CC_OP_LOGICQ, |
2c0262af FB |
824 | |
825 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
826 | CC_OP_INCW, | |
827 | CC_OP_INCL, | |
14ce26e7 | 828 | CC_OP_INCQ, |
2c0262af FB |
829 | |
830 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
831 | CC_OP_DECW, | |
832 | CC_OP_DECL, | |
14ce26e7 | 833 | CC_OP_DECQ, |
2c0262af | 834 | |
6b652794 | 835 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
2c0262af FB |
836 | CC_OP_SHLW, |
837 | CC_OP_SHLL, | |
14ce26e7 | 838 | CC_OP_SHLQ, |
2c0262af FB |
839 | |
840 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
841 | CC_OP_SARW, | |
842 | CC_OP_SARL, | |
14ce26e7 | 843 | CC_OP_SARQ, |
2c0262af | 844 | |
bc4b43dc RH |
845 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ |
846 | CC_OP_BMILGW, | |
847 | CC_OP_BMILGL, | |
848 | CC_OP_BMILGQ, | |
849 | ||
cd7f97ca RH |
850 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ |
851 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ | |
852 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ | |
853 | ||
436ff2d2 | 854 | CC_OP_CLR, /* Z set, all other flags clear. */ |
4885c3c4 | 855 | CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ |
436ff2d2 | 856 | |
2c0262af | 857 | CC_OP_NB, |
fee71888 | 858 | } CCOp; |
2c0262af | 859 | |
2c0262af FB |
860 | typedef struct SegmentCache { |
861 | uint32_t selector; | |
14ce26e7 | 862 | target_ulong base; |
2c0262af FB |
863 | uint32_t limit; |
864 | uint32_t flags; | |
865 | } SegmentCache; | |
866 | ||
f23a9db6 EH |
867 | #define MMREG_UNION(n, bits) \ |
868 | union n { \ | |
869 | uint8_t _b_##n[(bits)/8]; \ | |
870 | uint16_t _w_##n[(bits)/16]; \ | |
871 | uint32_t _l_##n[(bits)/32]; \ | |
872 | uint64_t _q_##n[(bits)/64]; \ | |
873 | float32 _s_##n[(bits)/32]; \ | |
874 | float64 _d_##n[(bits)/64]; \ | |
31d414d6 EH |
875 | } |
876 | ||
c97d6d2c SAGDR |
877 | typedef union { |
878 | uint8_t _b[16]; | |
879 | uint16_t _w[8]; | |
880 | uint32_t _l[4]; | |
881 | uint64_t _q[2]; | |
882 | } XMMReg; | |
883 | ||
884 | typedef union { | |
885 | uint8_t _b[32]; | |
886 | uint16_t _w[16]; | |
887 | uint32_t _l[8]; | |
888 | uint64_t _q[4]; | |
889 | } YMMReg; | |
890 | ||
f23a9db6 EH |
891 | typedef MMREG_UNION(ZMMReg, 512) ZMMReg; |
892 | typedef MMREG_UNION(MMXReg, 64) MMXReg; | |
826461bb | 893 | |
79e9ebeb LJ |
894 | typedef struct BNDReg { |
895 | uint64_t lb; | |
896 | uint64_t ub; | |
897 | } BNDReg; | |
898 | ||
899 | typedef struct BNDCSReg { | |
900 | uint64_t cfgu; | |
901 | uint64_t sts; | |
902 | } BNDCSReg; | |
903 | ||
f4f1110e RH |
904 | #define BNDCFG_ENABLE 1ULL |
905 | #define BNDCFG_BNDPRESERVE 2ULL | |
906 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK | |
907 | ||
e2542fe2 | 908 | #ifdef HOST_WORDS_BIGENDIAN |
f23a9db6 EH |
909 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] |
910 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] | |
911 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] | |
912 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] | |
913 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] | |
914 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] | |
915 | ||
916 | #define MMX_B(n) _b_MMXReg[7 - (n)] | |
917 | #define MMX_W(n) _w_MMXReg[3 - (n)] | |
918 | #define MMX_L(n) _l_MMXReg[1 - (n)] | |
919 | #define MMX_S(n) _s_MMXReg[1 - (n)] | |
826461bb | 920 | #else |
f23a9db6 EH |
921 | #define ZMM_B(n) _b_ZMMReg[n] |
922 | #define ZMM_W(n) _w_ZMMReg[n] | |
923 | #define ZMM_L(n) _l_ZMMReg[n] | |
924 | #define ZMM_S(n) _s_ZMMReg[n] | |
925 | #define ZMM_Q(n) _q_ZMMReg[n] | |
926 | #define ZMM_D(n) _d_ZMMReg[n] | |
927 | ||
928 | #define MMX_B(n) _b_MMXReg[n] | |
929 | #define MMX_W(n) _w_MMXReg[n] | |
930 | #define MMX_L(n) _l_MMXReg[n] | |
931 | #define MMX_S(n) _s_MMXReg[n] | |
826461bb | 932 | #endif |
f23a9db6 | 933 | #define MMX_Q(n) _q_MMXReg[n] |
826461bb | 934 | |
acc68836 | 935 | typedef union { |
c31da136 | 936 | floatx80 d __attribute__((aligned(16))); |
acc68836 JQ |
937 | MMXReg mmx; |
938 | } FPReg; | |
939 | ||
c1a54d57 JQ |
940 | typedef struct { |
941 | uint64_t base; | |
942 | uint64_t mask; | |
943 | } MTRRVar; | |
944 | ||
5f30fa18 JK |
945 | #define CPU_NB_REGS64 16 |
946 | #define CPU_NB_REGS32 8 | |
947 | ||
14ce26e7 | 948 | #ifdef TARGET_X86_64 |
5f30fa18 | 949 | #define CPU_NB_REGS CPU_NB_REGS64 |
14ce26e7 | 950 | #else |
5f30fa18 | 951 | #define CPU_NB_REGS CPU_NB_REGS32 |
14ce26e7 FB |
952 | #endif |
953 | ||
0d894367 PB |
954 | #define MAX_FIXED_COUNTERS 3 |
955 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) | |
956 | ||
a9321a4d | 957 | #define NB_MMU_MODES 3 |
2066d095 | 958 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 959 | |
9aecd6f8 CP |
960 | #define NB_OPMASK_REGS 8 |
961 | ||
d9c84f19 IM |
962 | /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish |
963 | * that APIC ID hasn't been set yet | |
964 | */ | |
965 | #define UNASSIGNED_APIC_ID 0xFFFFFFFF | |
966 | ||
b503717d EH |
967 | typedef union X86LegacyXSaveArea { |
968 | struct { | |
969 | uint16_t fcw; | |
970 | uint16_t fsw; | |
971 | uint8_t ftw; | |
972 | uint8_t reserved; | |
973 | uint16_t fpop; | |
974 | uint64_t fpip; | |
975 | uint64_t fpdp; | |
976 | uint32_t mxcsr; | |
977 | uint32_t mxcsr_mask; | |
978 | FPReg fpregs[8]; | |
979 | uint8_t xmm_regs[16][16]; | |
980 | }; | |
981 | uint8_t data[512]; | |
982 | } X86LegacyXSaveArea; | |
983 | ||
984 | typedef struct X86XSaveHeader { | |
985 | uint64_t xstate_bv; | |
986 | uint64_t xcomp_bv; | |
3f32bd21 RH |
987 | uint64_t reserve0; |
988 | uint8_t reserved[40]; | |
b503717d EH |
989 | } X86XSaveHeader; |
990 | ||
991 | /* Ext. save area 2: AVX State */ | |
992 | typedef struct XSaveAVX { | |
993 | uint8_t ymmh[16][16]; | |
994 | } XSaveAVX; | |
995 | ||
996 | /* Ext. save area 3: BNDREG */ | |
997 | typedef struct XSaveBNDREG { | |
998 | BNDReg bnd_regs[4]; | |
999 | } XSaveBNDREG; | |
1000 | ||
1001 | /* Ext. save area 4: BNDCSR */ | |
1002 | typedef union XSaveBNDCSR { | |
1003 | BNDCSReg bndcsr; | |
1004 | uint8_t data[64]; | |
1005 | } XSaveBNDCSR; | |
1006 | ||
1007 | /* Ext. save area 5: Opmask */ | |
1008 | typedef struct XSaveOpmask { | |
1009 | uint64_t opmask_regs[NB_OPMASK_REGS]; | |
1010 | } XSaveOpmask; | |
1011 | ||
1012 | /* Ext. save area 6: ZMM_Hi256 */ | |
1013 | typedef struct XSaveZMM_Hi256 { | |
1014 | uint8_t zmm_hi256[16][32]; | |
1015 | } XSaveZMM_Hi256; | |
1016 | ||
1017 | /* Ext. save area 7: Hi16_ZMM */ | |
1018 | typedef struct XSaveHi16_ZMM { | |
1019 | uint8_t hi16_zmm[16][64]; | |
1020 | } XSaveHi16_ZMM; | |
1021 | ||
1022 | /* Ext. save area 9: PKRU state */ | |
1023 | typedef struct XSavePKRU { | |
1024 | uint32_t pkru; | |
1025 | uint32_t padding; | |
1026 | } XSavePKRU; | |
1027 | ||
1028 | typedef struct X86XSaveArea { | |
1029 | X86LegacyXSaveArea legacy; | |
1030 | X86XSaveHeader header; | |
1031 | ||
1032 | /* Extended save areas: */ | |
1033 | ||
1034 | /* AVX State: */ | |
1035 | XSaveAVX avx_state; | |
1036 | uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; | |
1037 | /* MPX State: */ | |
1038 | XSaveBNDREG bndreg_state; | |
1039 | XSaveBNDCSR bndcsr_state; | |
1040 | /* AVX-512 State: */ | |
1041 | XSaveOpmask opmask_state; | |
1042 | XSaveZMM_Hi256 zmm_hi256_state; | |
1043 | XSaveHi16_ZMM hi16_zmm_state; | |
1044 | /* PKRU State: */ | |
1045 | XSavePKRU pkru_state; | |
1046 | } X86XSaveArea; | |
1047 | ||
1048 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); | |
1049 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); | |
1050 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); | |
1051 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); | |
1052 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); | |
1053 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); | |
1054 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); | |
1055 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); | |
1056 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); | |
1057 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); | |
1058 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); | |
1059 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); | |
1060 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); | |
1061 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); | |
1062 | ||
d362e757 JK |
1063 | typedef enum TPRAccess { |
1064 | TPR_ACCESS_READ, | |
1065 | TPR_ACCESS_WRITE, | |
1066 | } TPRAccess; | |
1067 | ||
7e3482f8 EH |
1068 | /* Cache information data structures: */ |
1069 | ||
1070 | enum CacheType { | |
5f00335a EH |
1071 | DATA_CACHE, |
1072 | INSTRUCTION_CACHE, | |
7e3482f8 EH |
1073 | UNIFIED_CACHE |
1074 | }; | |
1075 | ||
1076 | typedef struct CPUCacheInfo { | |
1077 | enum CacheType type; | |
1078 | uint8_t level; | |
1079 | /* Size in bytes */ | |
1080 | uint32_t size; | |
1081 | /* Line size, in bytes */ | |
1082 | uint16_t line_size; | |
1083 | /* | |
1084 | * Associativity. | |
1085 | * Note: representation of fully-associative caches is not implemented | |
1086 | */ | |
1087 | uint8_t associativity; | |
1088 | /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ | |
1089 | uint8_t partitions; | |
1090 | /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ | |
1091 | uint32_t sets; | |
1092 | /* | |
1093 | * Lines per tag. | |
1094 | * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. | |
1095 | * (Is this synonym to @partitions?) | |
1096 | */ | |
1097 | uint8_t lines_per_tag; | |
1098 | ||
1099 | /* Self-initializing cache */ | |
1100 | bool self_init; | |
1101 | /* | |
1102 | * WBINVD/INVD is not guaranteed to act upon lower level caches of | |
1103 | * non-originating threads sharing this cache. | |
1104 | * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] | |
1105 | */ | |
1106 | bool no_invd_sharing; | |
1107 | /* | |
1108 | * Cache is inclusive of lower cache levels. | |
1109 | * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. | |
1110 | */ | |
1111 | bool inclusive; | |
1112 | /* | |
1113 | * A complex function is used to index the cache, potentially using all | |
1114 | * address bits. CPUID[4].EDX[bit 2]. | |
1115 | */ | |
1116 | bool complex_indexing; | |
1117 | } CPUCacheInfo; | |
1118 | ||
1119 | ||
6aaeb054 | 1120 | typedef struct CPUCaches { |
a9f27ea9 EH |
1121 | CPUCacheInfo *l1d_cache; |
1122 | CPUCacheInfo *l1i_cache; | |
1123 | CPUCacheInfo *l2_cache; | |
1124 | CPUCacheInfo *l3_cache; | |
6aaeb054 | 1125 | } CPUCaches; |
7e3482f8 | 1126 | |
2c0262af FB |
1127 | typedef struct CPUX86State { |
1128 | /* standard registers */ | |
14ce26e7 FB |
1129 | target_ulong regs[CPU_NB_REGS]; |
1130 | target_ulong eip; | |
1131 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
2c0262af FB |
1132 | flags and DF are set to zero because they are |
1133 | stored elsewhere */ | |
1134 | ||
1135 | /* emulator internal eflags handling */ | |
14ce26e7 | 1136 | target_ulong cc_dst; |
988c3eb0 RH |
1137 | target_ulong cc_src; |
1138 | target_ulong cc_src2; | |
2c0262af FB |
1139 | uint32_t cc_op; |
1140 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
db620f46 FB |
1141 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
1142 | are known at translation time. */ | |
1143 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
2c0262af | 1144 | |
9df217a3 FB |
1145 | /* segments */ |
1146 | SegmentCache segs[6]; /* selector values */ | |
1147 | SegmentCache ldt; | |
1148 | SegmentCache tr; | |
1149 | SegmentCache gdt; /* only base and limit are used */ | |
1150 | SegmentCache idt; /* only base and limit are used */ | |
1151 | ||
db620f46 | 1152 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
5ee0ffaa | 1153 | int32_t a20_mask; |
9df217a3 | 1154 | |
05e7e819 PB |
1155 | BNDReg bnd_regs[4]; |
1156 | BNDCSReg bndcs_regs; | |
1157 | uint64_t msr_bndcfgs; | |
2188cc52 | 1158 | uint64_t efer; |
05e7e819 | 1159 | |
43175fa9 PB |
1160 | /* Beginning of state preserved by INIT (dummy marker). */ |
1161 | struct {} start_init_save; | |
1162 | ||
2c0262af FB |
1163 | /* FPU state */ |
1164 | unsigned int fpstt; /* top of stack index */ | |
67b8f419 | 1165 | uint16_t fpus; |
eb831623 | 1166 | uint16_t fpuc; |
2c0262af | 1167 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
acc68836 | 1168 | FPReg fpregs[8]; |
42cc8fa6 JK |
1169 | /* KVM-only so far */ |
1170 | uint16_t fpop; | |
1171 | uint64_t fpip; | |
1172 | uint64_t fpdp; | |
2c0262af FB |
1173 | |
1174 | /* emulator internal variables */ | |
7a0e1f41 | 1175 | float_status fp_status; |
c31da136 | 1176 | floatx80 ft0; |
3b46e624 | 1177 | |
a35f3ec7 | 1178 | float_status mmx_status; /* for 3DNow! float ops */ |
7a0e1f41 | 1179 | float_status sse_status; |
664e0f19 | 1180 | uint32_t mxcsr; |
fa451874 EH |
1181 | ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; |
1182 | ZMMReg xmm_t0; | |
664e0f19 | 1183 | MMXReg mmx_t0; |
14ce26e7 | 1184 | |
c97d6d2c SAGDR |
1185 | XMMReg ymmh_regs[CPU_NB_REGS]; |
1186 | ||
9aecd6f8 | 1187 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
c97d6d2c SAGDR |
1188 | YMMReg zmmh_regs[CPU_NB_REGS]; |
1189 | ZMMReg hi16_zmm_regs[CPU_NB_REGS]; | |
9aecd6f8 | 1190 | |
2c0262af FB |
1191 | /* sysenter registers */ |
1192 | uint32_t sysenter_cs; | |
2436b61a AZ |
1193 | target_ulong sysenter_esp; |
1194 | target_ulong sysenter_eip; | |
8d9bfc2b | 1195 | uint64_t star; |
0573fbfc | 1196 | |
5cc1d1e6 | 1197 | uint64_t vm_hsave; |
0573fbfc | 1198 | |
14ce26e7 | 1199 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
1200 | target_ulong lstar; |
1201 | target_ulong cstar; | |
1202 | target_ulong fmask; | |
1203 | target_ulong kernelgsbase; | |
1204 | #endif | |
58fe2f10 | 1205 | |
7ba1e619 | 1206 | uint64_t tsc; |
f28558d3 | 1207 | uint64_t tsc_adjust; |
aa82ba54 | 1208 | uint64_t tsc_deadline; |
7616f1c2 PB |
1209 | uint64_t tsc_aux; |
1210 | ||
1211 | uint64_t xcr0; | |
7ba1e619 | 1212 | |
18559232 | 1213 | uint64_t mcg_status; |
21e87c46 | 1214 | uint64_t msr_ia32_misc_enable; |
0779caeb | 1215 | uint64_t msr_ia32_feature_control; |
18559232 | 1216 | |
0d894367 PB |
1217 | uint64_t msr_fixed_ctr_ctrl; |
1218 | uint64_t msr_global_ctrl; | |
1219 | uint64_t msr_global_status; | |
1220 | uint64_t msr_global_ovf_ctrl; | |
1221 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; | |
1222 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; | |
1223 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; | |
43175fa9 PB |
1224 | |
1225 | uint64_t pat; | |
1226 | uint32_t smbase; | |
e13713db | 1227 | uint64_t msr_smi_count; |
43175fa9 | 1228 | |
7616f1c2 PB |
1229 | uint32_t pkru; |
1230 | ||
a33a2cfe | 1231 | uint64_t spec_ctrl; |
cfeea0c0 | 1232 | uint64_t virt_ssbd; |
a33a2cfe | 1233 | |
43175fa9 PB |
1234 | /* End of state preserved by INIT (dummy marker). */ |
1235 | struct {} end_init_save; | |
1236 | ||
1237 | uint64_t system_time_msr; | |
1238 | uint64_t wall_clock_msr; | |
1239 | uint64_t steal_time_msr; | |
1240 | uint64_t async_pf_en_msr; | |
1241 | uint64_t pv_eoi_en_msr; | |
1242 | ||
da1cc323 | 1243 | /* Partition-wide HV MSRs, will be updated only on the first vcpu */ |
1c90ef26 VR |
1244 | uint64_t msr_hv_hypercall; |
1245 | uint64_t msr_hv_guest_os_id; | |
48a5f3bc | 1246 | uint64_t msr_hv_tsc; |
da1cc323 EY |
1247 | |
1248 | /* Per-VCPU HV MSRs */ | |
1249 | uint64_t msr_hv_vapic; | |
5e953812 | 1250 | uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; |
46eb8f98 | 1251 | uint64_t msr_hv_runtime; |
866eea9a | 1252 | uint64_t msr_hv_synic_control; |
866eea9a AS |
1253 | uint64_t msr_hv_synic_evt_page; |
1254 | uint64_t msr_hv_synic_msg_page; | |
5e953812 RK |
1255 | uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; |
1256 | uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; | |
1257 | uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; | |
ba6a4fd9 VK |
1258 | uint64_t msr_hv_reenlightenment_control; |
1259 | uint64_t msr_hv_tsc_emulation_control; | |
1260 | uint64_t msr_hv_tsc_emulation_status; | |
18559232 | 1261 | |
b77146e9 CP |
1262 | uint64_t msr_rtit_ctrl; |
1263 | uint64_t msr_rtit_status; | |
1264 | uint64_t msr_rtit_output_base; | |
1265 | uint64_t msr_rtit_output_mask; | |
1266 | uint64_t msr_rtit_cr3_match; | |
1267 | uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; | |
1268 | ||
2c0262af | 1269 | /* exception/interrupt handling */ |
2c0262af FB |
1270 | int error_code; |
1271 | int exception_is_int; | |
826461bb | 1272 | target_ulong exception_next_eip; |
d0052339 | 1273 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ |
01df040b | 1274 | union { |
f0c3c505 | 1275 | struct CPUBreakpoint *cpu_breakpoint[4]; |
ff4700b0 | 1276 | struct CPUWatchpoint *cpu_watchpoint[4]; |
01df040b | 1277 | }; /* break/watchpoints for dr[0..3] */ |
678dde13 | 1278 | int old_exception; /* exception in flight */ |
2c0262af | 1279 | |
43175fa9 PB |
1280 | uint64_t vm_vmcb; |
1281 | uint64_t tsc_offset; | |
1282 | uint64_t intercept; | |
1283 | uint16_t intercept_cr_read; | |
1284 | uint16_t intercept_cr_write; | |
1285 | uint16_t intercept_dr_read; | |
1286 | uint16_t intercept_dr_write; | |
1287 | uint32_t intercept_exceptions; | |
fe441054 JK |
1288 | uint64_t nested_cr3; |
1289 | uint32_t nested_pg_mode; | |
43175fa9 PB |
1290 | uint8_t v_tpr; |
1291 | ||
d8f771d9 JK |
1292 | /* KVM states, automatically cleared on reset */ |
1293 | uint8_t nmi_injected; | |
1294 | uint8_t nmi_pending; | |
1295 | ||
fe441054 JK |
1296 | uintptr_t retaddr; |
1297 | ||
1f5c00cf AB |
1298 | /* Fields up to this point are cleared by a CPU reset */ |
1299 | struct {} end_reset_fields; | |
1300 | ||
a316d335 | 1301 | CPU_COMMON |
2c0262af | 1302 | |
1f5c00cf | 1303 | /* Fields after CPU_COMMON are preserved across CPU reset. */ |
ebda377f | 1304 | |
14ce26e7 | 1305 | /* processor features (e.g. for CPUID insn) */ |
c39c0edf EH |
1306 | /* Minimum level/xlevel/xlevel2, based on CPU model + features */ |
1307 | uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; | |
1308 | /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ | |
1309 | uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; | |
1310 | /* Actual level/xlevel/xlevel2 value: */ | |
1311 | uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; | |
14ce26e7 FB |
1312 | uint32_t cpuid_vendor1; |
1313 | uint32_t cpuid_vendor2; | |
1314 | uint32_t cpuid_vendor3; | |
1315 | uint32_t cpuid_version; | |
0514ef2f | 1316 | FeatureWordArray features; |
d4a606b3 EH |
1317 | /* Features that were explicitly enabled/disabled */ |
1318 | FeatureWordArray user_features; | |
8d9bfc2b | 1319 | uint32_t cpuid_model[12]; |
a9f27ea9 EH |
1320 | /* Cache information for CPUID. When legacy-cache=on, the cache data |
1321 | * on each CPUID leaf will be different, because we keep compatibility | |
1322 | * with old QEMU versions. | |
1323 | */ | |
1324 | CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; | |
3b46e624 | 1325 | |
165d9b82 AL |
1326 | /* MTRRs */ |
1327 | uint64_t mtrr_fixed[11]; | |
1328 | uint64_t mtrr_deftype; | |
d8b5c67b | 1329 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; |
165d9b82 | 1330 | |
7ba1e619 | 1331 | /* For KVM */ |
f8d926e9 | 1332 | uint32_t mp_state; |
31827373 | 1333 | int32_t exception_injected; |
0e607a80 | 1334 | int32_t interrupt_injected; |
a0fb002c | 1335 | uint8_t soft_interrupt; |
a0fb002c | 1336 | uint8_t has_error_code; |
c97d6d2c | 1337 | uint32_t ins_len; |
a0fb002c | 1338 | uint32_t sipi_vector; |
b8cc45d6 | 1339 | bool tsc_valid; |
06ef227e | 1340 | int64_t tsc_khz; |
36f96c4b | 1341 | int64_t user_tsc_khz; /* for sanity check only */ |
5b8063c4 LA |
1342 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) |
1343 | void *xsave_buf; | |
1344 | #endif | |
c97d6d2c SAGDR |
1345 | #if defined(CONFIG_HVF) |
1346 | HVFX86EmulatorState *hvf_emul; | |
1347 | #endif | |
fabacc0f | 1348 | |
ac6c4120 | 1349 | uint64_t mcg_cap; |
ac6c4120 | 1350 | uint64_t mcg_ctl; |
87f8b626 | 1351 | uint64_t mcg_ext_ctl; |
ac6c4120 | 1352 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
7616f1c2 | 1353 | uint64_t xstate_bv; |
5a2d0e57 AJ |
1354 | |
1355 | /* vmstate */ | |
1356 | uint16_t fpus_vmstate; | |
1357 | uint16_t fptag_vmstate; | |
1358 | uint16_t fpregs_format_vmstate; | |
f1665b21 | 1359 | |
18cd2c17 | 1360 | uint64_t xss; |
d362e757 JK |
1361 | |
1362 | TPRAccess tpr_access_type; | |
2c0262af FB |
1363 | } CPUX86State; |
1364 | ||
d71b62a1 EH |
1365 | struct kvm_msrs; |
1366 | ||
4da6f8d9 PB |
1367 | /** |
1368 | * X86CPU: | |
1369 | * @env: #CPUX86State | |
1370 | * @migratable: If set, only migratable flags will be accepted when "enforce" | |
1371 | * mode is used, and only migratable flags will be included in the "host" | |
1372 | * CPU model. | |
1373 | * | |
1374 | * An x86 CPU. | |
1375 | */ | |
1376 | struct X86CPU { | |
1377 | /*< private >*/ | |
1378 | CPUState parent_obj; | |
1379 | /*< public >*/ | |
1380 | ||
1381 | CPUX86State env; | |
1382 | ||
1383 | bool hyperv_vapic; | |
1384 | bool hyperv_relaxed_timing; | |
1385 | int hyperv_spinlock_attempts; | |
1386 | char *hyperv_vendor_id; | |
1387 | bool hyperv_time; | |
1388 | bool hyperv_crash; | |
1389 | bool hyperv_reset; | |
1390 | bool hyperv_vpindex; | |
1391 | bool hyperv_runtime; | |
1392 | bool hyperv_synic; | |
9b4cf107 | 1393 | bool hyperv_synic_kvm_only; |
4da6f8d9 | 1394 | bool hyperv_stimer; |
9445597b | 1395 | bool hyperv_frequencies; |
ba6a4fd9 | 1396 | bool hyperv_reenlightenment; |
47512009 | 1397 | bool hyperv_tlbflush; |
e204ac61 | 1398 | bool hyperv_evmcs; |
6b7a9830 | 1399 | bool hyperv_ipi; |
4da6f8d9 PB |
1400 | bool check_cpuid; |
1401 | bool enforce_cpuid; | |
1402 | bool expose_kvm; | |
1ce36bfe | 1403 | bool expose_tcg; |
4da6f8d9 | 1404 | bool migratable; |
990e0be2 | 1405 | bool migrate_smi_count; |
44bd8e53 | 1406 | bool max_features; /* Enable all supported features automatically */ |
d9c84f19 | 1407 | uint32_t apic_id; |
4da6f8d9 | 1408 | |
9954a158 PDJ |
1409 | /* Enables publishing of TSC increment and Local APIC bus frequencies to |
1410 | * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ | |
1411 | bool vmware_cpuid_freq; | |
1412 | ||
4da6f8d9 PB |
1413 | /* if true the CPUID code directly forward host cache leaves to the guest */ |
1414 | bool cache_info_passthrough; | |
1415 | ||
2266d443 MT |
1416 | /* if true the CPUID code directly forwards |
1417 | * host monitor/mwait leaves to the guest */ | |
1418 | struct { | |
1419 | uint32_t eax; | |
1420 | uint32_t ebx; | |
1421 | uint32_t ecx; | |
1422 | uint32_t edx; | |
1423 | } mwait; | |
1424 | ||
4da6f8d9 PB |
1425 | /* Features that were filtered out because of missing host capabilities */ |
1426 | uint32_t filtered_features[FEATURE_WORDS]; | |
1427 | ||
1428 | /* Enable PMU CPUID bits. This can't be enabled by default yet because | |
1429 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID | |
1430 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel | |
1431 | * capabilities) directly to the guest. | |
1432 | */ | |
1433 | bool enable_pmu; | |
1434 | ||
87f8b626 AR |
1435 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is |
1436 | * disabled by default to avoid breaking migration between QEMU with | |
1437 | * different LMCE configurations. | |
1438 | */ | |
1439 | bool enable_lmce; | |
1440 | ||
14c985cf LM |
1441 | /* Compatibility bits for old machine types. |
1442 | * If true present virtual l3 cache for VM, the vcpus in the same virtual | |
1443 | * socket share an virtual l3 cache. | |
1444 | */ | |
1445 | bool enable_l3_cache; | |
1446 | ||
ab8f992e BM |
1447 | /* Compatibility bits for old machine types. |
1448 | * If true present the old cache topology information | |
1449 | */ | |
1450 | bool legacy_cache; | |
1451 | ||
5232d00a RK |
1452 | /* Compatibility bits for old machine types: */ |
1453 | bool enable_cpuid_0xb; | |
1454 | ||
c39c0edf EH |
1455 | /* Enable auto level-increase for all CPUID leaves */ |
1456 | bool full_cpuid_auto_level; | |
1457 | ||
fcc35e7c DDAG |
1458 | /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ |
1459 | bool fill_mtrr_mask; | |
1460 | ||
11f6fee5 DDAG |
1461 | /* if true override the phys_bits value with a value read from the host */ |
1462 | bool host_phys_bits; | |
1463 | ||
fc3a1fd7 DDAG |
1464 | /* Stop SMI delivery for migration compatibility with old machines */ |
1465 | bool kvm_no_smi_migration; | |
1466 | ||
af45907a DDAG |
1467 | /* Number of physical address bits supported */ |
1468 | uint32_t phys_bits; | |
1469 | ||
4da6f8d9 PB |
1470 | /* in order to simplify APIC support, we leave this pointer to the |
1471 | user */ | |
1472 | struct DeviceState *apic_state; | |
1473 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; | |
1474 | Notifier machine_done; | |
d71b62a1 EH |
1475 | |
1476 | struct kvm_msrs *kvm_msr_buf; | |
d89c2b8b | 1477 | |
15f8b142 | 1478 | int32_t node_id; /* NUMA node this CPU belongs to */ |
d89c2b8b IM |
1479 | int32_t socket_id; |
1480 | int32_t core_id; | |
1481 | int32_t thread_id; | |
6c69dfb6 GA |
1482 | |
1483 | int32_t hv_max_vps; | |
4da6f8d9 PB |
1484 | }; |
1485 | ||
1486 | static inline X86CPU *x86_env_get_cpu(CPUX86State *env) | |
1487 | { | |
1488 | return container_of(env, X86CPU, env); | |
1489 | } | |
1490 | ||
1491 | #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) | |
1492 | ||
1493 | #define ENV_OFFSET offsetof(X86CPU, env) | |
1494 | ||
1495 | #ifndef CONFIG_USER_ONLY | |
1496 | extern struct VMStateDescription vmstate_x86_cpu; | |
1497 | #endif | |
1498 | ||
1499 | /** | |
1500 | * x86_cpu_do_interrupt: | |
1501 | * @cpu: vCPU the interrupt is to be handled by. | |
1502 | */ | |
1503 | void x86_cpu_do_interrupt(CPUState *cpu); | |
1504 | bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
92d5f1a4 | 1505 | int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); |
4da6f8d9 PB |
1506 | |
1507 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1508 | int cpuid, void *opaque); | |
1509 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1510 | int cpuid, void *opaque); | |
1511 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
1512 | void *opaque); | |
1513 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
1514 | void *opaque); | |
1515 | ||
1516 | void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
1517 | Error **errp); | |
1518 | ||
1519 | void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | |
1520 | int flags); | |
1521 | ||
1522 | hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
1523 | ||
1524 | int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
1525 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
1526 | ||
1527 | void x86_cpu_exec_enter(CPUState *cpu); | |
1528 | void x86_cpu_exec_exit(CPUState *cpu); | |
5fd2087a | 1529 | |
e916cbf8 | 1530 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
317ac620 | 1531 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
b5ec5ce0 | 1532 | |
d720b93d | 1533 | int cpu_get_pic_interrupt(CPUX86State *s); |
2ee73ac3 FB |
1534 | /* MSDOS compatibility mode FPU exception support */ |
1535 | void cpu_set_ferr(CPUX86State *s); | |
5e76d84e PB |
1536 | /* mpx_helper.c */ |
1537 | void cpu_sync_bndcs_hflags(CPUX86State *env); | |
2c0262af FB |
1538 | |
1539 | /* this function must always be used to load data in the segment | |
1540 | cache: it synchronizes the hflags with the segment cache values */ | |
5fafdf24 | 1541 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
2c0262af | 1542 | int seg_reg, unsigned int selector, |
8988ae89 | 1543 | target_ulong base, |
5fafdf24 | 1544 | unsigned int limit, |
2c0262af FB |
1545 | unsigned int flags) |
1546 | { | |
1547 | SegmentCache *sc; | |
1548 | unsigned int new_hflags; | |
3b46e624 | 1549 | |
2c0262af FB |
1550 | sc = &env->segs[seg_reg]; |
1551 | sc->selector = selector; | |
1552 | sc->base = base; | |
1553 | sc->limit = limit; | |
1554 | sc->flags = flags; | |
1555 | ||
1556 | /* update the hidden flags */ | |
14ce26e7 FB |
1557 | { |
1558 | if (seg_reg == R_CS) { | |
1559 | #ifdef TARGET_X86_64 | |
1560 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
1561 | /* long mode */ | |
1562 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1563 | env->hflags &= ~(HF_ADDSEG_MASK); | |
5fafdf24 | 1564 | } else |
14ce26e7 FB |
1565 | #endif |
1566 | { | |
1567 | /* legacy / compatibility case */ | |
1568 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
1569 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
1570 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
1571 | new_hflags; | |
1572 | } | |
7125c937 PB |
1573 | } |
1574 | if (seg_reg == R_SS) { | |
1575 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; | |
7848c8d1 KC |
1576 | #if HF_CPL_MASK != 3 |
1577 | #error HF_CPL_MASK is hardcoded | |
1578 | #endif | |
1579 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; | |
5e76d84e PB |
1580 | /* Possibly switch between BNDCFGS and BNDCFGU */ |
1581 | cpu_sync_bndcs_hflags(env); | |
14ce26e7 FB |
1582 | } |
1583 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
1584 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
1585 | if (env->hflags & HF_CS64_MASK) { | |
1586 | /* zero base assumed for DS, ES and SS in long mode */ | |
5fafdf24 | 1587 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
735a8fd3 FB |
1588 | (env->eflags & VM_MASK) || |
1589 | !(env->hflags & HF_CS32_MASK)) { | |
14ce26e7 FB |
1590 | /* XXX: try to avoid this test. The problem comes from the |
1591 | fact that is real mode or vm86 mode we only modify the | |
1592 | 'base' and 'selector' fields of the segment cache to go | |
1593 | faster. A solution may be to force addseg to one in | |
1594 | translate-i386.c. */ | |
1595 | new_hflags |= HF_ADDSEG_MASK; | |
1596 | } else { | |
5fafdf24 | 1597 | new_hflags |= ((env->segs[R_DS].base | |
735a8fd3 | 1598 | env->segs[R_ES].base | |
5fafdf24 | 1599 | env->segs[R_SS].base) != 0) << |
14ce26e7 FB |
1600 | HF_ADDSEG_SHIFT; |
1601 | } | |
5fafdf24 | 1602 | env->hflags = (env->hflags & |
14ce26e7 | 1603 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
2c0262af | 1604 | } |
2c0262af FB |
1605 | } |
1606 | ||
e9f9d6b1 | 1607 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
e6a33e45 | 1608 | uint8_t sipi_vector) |
0e26b7b8 | 1609 | { |
259186a7 | 1610 | CPUState *cs = CPU(cpu); |
e9f9d6b1 AF |
1611 | CPUX86State *env = &cpu->env; |
1612 | ||
0e26b7b8 BS |
1613 | env->eip = 0; |
1614 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
1615 | sipi_vector << 12, | |
1616 | env->segs[R_CS].limit, | |
1617 | env->segs[R_CS].flags); | |
259186a7 | 1618 | cs->halted = 0; |
0e26b7b8 BS |
1619 | } |
1620 | ||
84273177 JK |
1621 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
1622 | target_ulong *base, unsigned int *limit, | |
1623 | unsigned int *flags); | |
1624 | ||
d9957a8b | 1625 | /* op_helper.c */ |
1f1af9fd | 1626 | /* used for debug or cpu save/restore */ |
1f1af9fd | 1627 | |
d9957a8b | 1628 | /* cpu-exec.c */ |
2c0262af FB |
1629 | /* the following helpers are only usable in user mode simulation as |
1630 | they can trigger unexpected exceptions */ | |
1631 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); | |
6f12a2a6 FB |
1632 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
1633 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
1c1df019 PK |
1634 | void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); |
1635 | void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); | |
2c0262af FB |
1636 | |
1637 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
1638 | signal handlers to inform the virtual CPU of exceptions. non zero | |
1639 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 1640 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
2c0262af | 1641 | void *puc); |
d9957a8b | 1642 | |
f4f1110e | 1643 | /* cpu.c */ |
c6dc6f63 AP |
1644 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
1645 | uint32_t *eax, uint32_t *ebx, | |
1646 | uint32_t *ecx, uint32_t *edx); | |
0e26b7b8 | 1647 | void cpu_clear_apic_feature(CPUX86State *env); |
bb44e0d1 JK |
1648 | void host_cpuid(uint32_t function, uint32_t count, |
1649 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
20271d48 | 1650 | void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); |
c6dc6f63 | 1651 | |
d9957a8b | 1652 | /* helper.c */ |
98670d47 | 1653 | int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size, |
97b348e7 | 1654 | int is_write, int mmu_idx); |
cc36a7a2 | 1655 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); |
2c0262af | 1656 | |
b216aa6c | 1657 | #ifndef CONFIG_USER_ONLY |
f8c45c65 PB |
1658 | static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) |
1659 | { | |
1660 | return !!attrs.secure; | |
1661 | } | |
1662 | ||
1663 | static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) | |
1664 | { | |
1665 | return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); | |
1666 | } | |
1667 | ||
b216aa6c PB |
1668 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); |
1669 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); | |
1670 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); | |
1671 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); | |
1672 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); | |
1673 | void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); | |
1674 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
1675 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
1676 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); | |
1677 | #endif | |
1678 | ||
86025ee4 | 1679 | void breakpoint_handler(CPUState *cs); |
d9957a8b BS |
1680 | |
1681 | /* will be suppressed */ | |
1682 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
1683 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
1684 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
93d00d0f | 1685 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); |
d9957a8b | 1686 | |
d9957a8b | 1687 | /* hw/pc.c */ |
d9957a8b | 1688 | uint64_t cpu_get_tsc(CPUX86State *env); |
6fd805e1 | 1689 | |
2c0262af | 1690 | #define TARGET_PAGE_BITS 12 |
9467d44c | 1691 | |
52705890 RH |
1692 | #ifdef TARGET_X86_64 |
1693 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 | |
1694 | /* ??? This is really 48 bits, sign-extended, but the only thing | |
1695 | accessible to userland with bit 48 set is the VSYSCALL, and that | |
1696 | is handled via other mechanisms. */ | |
1697 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 | |
1698 | #else | |
1699 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
1700 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1701 | #endif | |
1702 | ||
e8f6d00c PB |
1703 | /* XXX: This value should match the one returned by CPUID |
1704 | * and in exec.c */ | |
1705 | # if defined(TARGET_X86_64) | |
709787ee | 1706 | # define TCG_PHYS_ADDR_BITS 40 |
e8f6d00c | 1707 | # else |
709787ee | 1708 | # define TCG_PHYS_ADDR_BITS 36 |
e8f6d00c PB |
1709 | # endif |
1710 | ||
709787ee DDAG |
1711 | #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) |
1712 | ||
311ca98d IM |
1713 | #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU |
1714 | #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) | |
0dacec87 | 1715 | #define CPU_RESOLVING_TYPE TYPE_X86_CPU |
311ca98d IM |
1716 | |
1717 | #ifdef TARGET_X86_64 | |
1718 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") | |
1719 | #else | |
1720 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") | |
1721 | #endif | |
1722 | ||
9467d44c | 1723 | #define cpu_signal_handler cpu_x86_signal_handler |
e916cbf8 | 1724 | #define cpu_list x86_cpu_list |
9467d44c | 1725 | |
6ebbf390 | 1726 | /* MMU modes definitions */ |
8a201bd4 | 1727 | #define MMU_MODE0_SUFFIX _ksmap |
6ebbf390 | 1728 | #define MMU_MODE1_SUFFIX _user |
43773ed3 | 1729 | #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ |
8a201bd4 | 1730 | #define MMU_KSMAP_IDX 0 |
a9321a4d | 1731 | #define MMU_USER_IDX 1 |
43773ed3 | 1732 | #define MMU_KNOSMAP_IDX 2 |
97ed5ccd | 1733 | static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) |
6ebbf390 | 1734 | { |
a9321a4d | 1735 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
f57584dc | 1736 | (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) |
8a201bd4 PB |
1737 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; |
1738 | } | |
1739 | ||
1740 | static inline int cpu_mmu_index_kernel(CPUX86State *env) | |
1741 | { | |
1742 | return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : | |
1743 | ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) | |
1744 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; | |
6ebbf390 JM |
1745 | } |
1746 | ||
988c3eb0 RH |
1747 | #define CC_DST (env->cc_dst) |
1748 | #define CC_SRC (env->cc_src) | |
1749 | #define CC_SRC2 (env->cc_src2) | |
1750 | #define CC_OP (env->cc_op) | |
f081c76c | 1751 | |
5918fffb BS |
1752 | /* n must be a constant to be efficient */ |
1753 | static inline target_long lshift(target_long x, int n) | |
1754 | { | |
1755 | if (n >= 0) { | |
1756 | return x << n; | |
1757 | } else { | |
1758 | return x >> (-n); | |
1759 | } | |
1760 | } | |
1761 | ||
f081c76c BS |
1762 | /* float macros */ |
1763 | #define FT0 (env->ft0) | |
1764 | #define ST0 (env->fpregs[env->fpstt].d) | |
1765 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
1766 | #define ST1 ST(1) | |
1767 | ||
d9957a8b | 1768 | /* translate.c */ |
63618b4e | 1769 | void tcg_x86_init(void); |
26a5f13b | 1770 | |
022c62cb | 1771 | #include "exec/cpu-all.h" |
0573fbfc TS |
1772 | #include "svm.h" |
1773 | ||
0e26b7b8 | 1774 | #if !defined(CONFIG_USER_ONLY) |
0d09e41a | 1775 | #include "hw/i386/apic.h" |
0e26b7b8 BS |
1776 | #endif |
1777 | ||
317ac620 | 1778 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
89fee74a | 1779 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
1780 | { |
1781 | *cs_base = env->segs[R_CS].base; | |
1782 | *pc = *cs_base + env->eip; | |
a2397807 | 1783 | *flags = env->hflags | |
a9321a4d | 1784 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
6b917547 AL |
1785 | } |
1786 | ||
232fc23b AF |
1787 | void do_cpu_init(X86CPU *cpu); |
1788 | void do_cpu_sipi(X86CPU *cpu); | |
2fa11da0 | 1789 | |
747461c7 JK |
1790 | #define MCE_INJECT_BROADCAST 1 |
1791 | #define MCE_INJECT_UNCOND_AO 2 | |
1792 | ||
8c5cf3b6 | 1793 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
316378e4 | 1794 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
747461c7 | 1795 | uint64_t misc, int flags); |
2fa11da0 | 1796 | |
599b9a5a | 1797 | /* excp_helper.c */ |
77b2bc2c | 1798 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
91980095 PD |
1799 | void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, |
1800 | uintptr_t retaddr); | |
77b2bc2c BS |
1801 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, |
1802 | int error_code); | |
91980095 PD |
1803 | void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, |
1804 | int error_code, uintptr_t retaddr); | |
599b9a5a BS |
1805 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
1806 | int error_code, int next_eip_addend); | |
1807 | ||
5918fffb BS |
1808 | /* cc_helper.c */ |
1809 | extern const uint8_t parity_table[256]; | |
1810 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); | |
1811 | ||
1812 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
1813 | { | |
79c664f6 YZ |
1814 | uint32_t eflags = env->eflags; |
1815 | if (tcg_enabled()) { | |
1816 | eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); | |
1817 | } | |
1818 | return eflags; | |
5918fffb BS |
1819 | } |
1820 | ||
28fb26f1 PB |
1821 | /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS |
1822 | * after generating a call to a helper that uses this. | |
1823 | */ | |
5918fffb BS |
1824 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, |
1825 | int update_mask) | |
1826 | { | |
1827 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
28fb26f1 | 1828 | CC_OP = CC_OP_EFLAGS; |
80cf2c81 | 1829 | env->df = 1 - (2 * ((eflags >> 10) & 1)); |
5918fffb BS |
1830 | env->eflags = (env->eflags & ~update_mask) | |
1831 | (eflags & update_mask) | 0x2; | |
1832 | } | |
1833 | ||
1834 | /* load efer and update the corresponding hflags. XXX: do consistency | |
1835 | checks with cpuid bits? */ | |
1836 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) | |
1837 | { | |
1838 | env->efer = val; | |
1839 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
1840 | if (env->efer & MSR_EFER_LMA) { | |
1841 | env->hflags |= HF_LMA_MASK; | |
1842 | } | |
1843 | if (env->efer & MSR_EFER_SVME) { | |
1844 | env->hflags |= HF_SVME_MASK; | |
1845 | } | |
1846 | } | |
1847 | ||
f794aa4a PB |
1848 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) |
1849 | { | |
1850 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); | |
1851 | } | |
1852 | ||
c8bc83a4 PB |
1853 | static inline int32_t x86_get_a20_mask(CPUX86State *env) |
1854 | { | |
1855 | if (env->hflags & HF_SMM_MASK) { | |
1856 | return -1; | |
1857 | } else { | |
1858 | return env->a20_mask; | |
1859 | } | |
1860 | } | |
1861 | ||
4e47e39a | 1862 | /* fpu_helper.c */ |
1d8ad165 YZ |
1863 | void update_fp_status(CPUX86State *env); |
1864 | void update_mxcsr_status(CPUX86State *env); | |
1865 | ||
1866 | static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) | |
1867 | { | |
1868 | env->mxcsr = mxcsr; | |
1869 | if (tcg_enabled()) { | |
1870 | update_mxcsr_status(env); | |
1871 | } | |
1872 | } | |
1873 | ||
1874 | static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) | |
1875 | { | |
1876 | env->fpuc = fpuc; | |
1877 | if (tcg_enabled()) { | |
1878 | update_fp_status(env); | |
1879 | } | |
1880 | } | |
4e47e39a | 1881 | |
677ef623 FK |
1882 | /* mem_helper.c */ |
1883 | void helper_lock_init(void); | |
1884 | ||
6bada5e8 BS |
1885 | /* svm_helper.c */ |
1886 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
65c9d60a | 1887 | uint64_t param, uintptr_t retaddr); |
50b3de6e JK |
1888 | void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, |
1889 | uint64_t exit_info_1, uintptr_t retaddr); | |
10cde894 | 1890 | void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); |
6bada5e8 | 1891 | |
97a8ea5a | 1892 | /* seg_helper.c */ |
599b9a5a | 1893 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); |
e694d4e2 | 1894 | |
f809c605 | 1895 | /* smm_helper.c */ |
518e9d7d | 1896 | void do_smm_enter(X86CPU *cpu); |
e694d4e2 | 1897 | |
d613f8cc | 1898 | /* apic.c */ |
317ac620 | 1899 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
d613f8cc PB |
1900 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
1901 | TPRAccess access); | |
1902 | ||
d362e757 | 1903 | |
5114e842 EH |
1904 | /* Change the value of a KVM-specific default |
1905 | * | |
1906 | * If value is NULL, no default will be set and the original | |
1907 | * value from the CPU model table will be kept. | |
1908 | * | |
cb8d4c8f | 1909 | * It is valid to call this function only for properties that |
5114e842 EH |
1910 | * are already present in the kvm_default_props table. |
1911 | */ | |
1912 | void x86_cpu_change_kvm_default(const char *prop, const char *value); | |
8fb4f821 | 1913 | |
8b4beddc EH |
1914 | /* Return name of 32-bit register, from a R_* constant */ |
1915 | const char *get_register_name_32(unsigned int reg); | |
1916 | ||
8932cfdf | 1917 | void enable_compat_apic_id_mode(void); |
cb41bad3 | 1918 | |
dab86234 | 1919 | #define APIC_DEFAULT_ADDRESS 0xfee00000 |
baaeda08 | 1920 | #define APIC_SPACE_SIZE 0x100000 |
dab86234 | 1921 | |
1f871d49 PB |
1922 | void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, |
1923 | fprintf_function cpu_fprintf, int flags); | |
1924 | ||
d613f8cc PB |
1925 | /* cpu.c */ |
1926 | bool cpu_is_bsp(X86CPU *cpu); | |
1927 | ||
86a57621 SAGDR |
1928 | void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); |
1929 | void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); | |
35b1b927 TW |
1930 | void x86_update_hflags(CPUX86State* env); |
1931 | ||
07f5a258 | 1932 | #endif /* I386_CPU_H */ |