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Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
7b59220e 8#include "helper.h"
ca10f867 9#include "qemu-common.h"
7bbcb0af 10#include "host-utils.h"
4f78c9ad 11#if !defined(CONFIG_USER_ONLY)
983fe826 12#include "hw/loader.h"
4f78c9ad 13#endif
9ee6e8bb 14
10055562
PB		 15static uint32_t cortexa9_cp15_c0_c1[8] =
16{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17
18static uint32_t cortexa9_cp15_c0_c2[8] =
19{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20
9ee6e8bb
PB		 21static uint32_t cortexa8_cp15_c0_c1[8] =
22{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23
24static uint32_t cortexa8_cp15_c0_c2[8] =
25{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26
27static uint32_t mpcore_cp15_c0_c1[8] =
28{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29
30static uint32_t mpcore_cp15_c0_c2[8] =
31{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32
33static uint32_t arm1136_cp15_c0_c1[8] =
34{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35
36static uint32_t arm1136_cp15_c0_c2[8] =
37{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 38
aaed909a
FB		 39static uint32_t cpu_arm_find_by_name(const char *name);
40
f3d6b95e
PB		 41static inline void set_feature(CPUARMState *env, int feature)
42{
43 env->features |= 1u << feature;
44}
45
46static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
47{
48 env->cp15.c0_cpuid = id;
49 switch (id) {
50 case ARM_CPUID_ARM926:
be5e7a76
DES		 51 set_feature(env, ARM_FEATURE_V4T);
52 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 53 set_feature(env, ARM_FEATURE_VFP);
54 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 55 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 56 env->cp15.c1_sys = 0x00090078;
f3d6b95e 57 break;
ce819861 58 case ARM_CPUID_ARM946:
be5e7a76
DES		 59 set_feature(env, ARM_FEATURE_V4T);
60 set_feature(env, ARM_FEATURE_V5);
ce819861
PB		 61 set_feature(env, ARM_FEATURE_MPU);
62 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 63 env->cp15.c1_sys = 0x00000078;
ce819861 64 break;
f3d6b95e 65 case ARM_CPUID_ARM1026:
be5e7a76
DES		 66 set_feature(env, ARM_FEATURE_V4T);
67 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 68 set_feature(env, ARM_FEATURE_VFP);
69 set_feature(env, ARM_FEATURE_AUXCR);
70 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 71 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 72 env->cp15.c1_sys = 0x00090078;
c1713132 73 break;
827df9f3 74 case ARM_CPUID_ARM1136_R2:
9ee6e8bb 75 case ARM_CPUID_ARM1136:
be5e7a76
DES		 76 set_feature(env, ARM_FEATURE_V4T);
77 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 78 set_feature(env, ARM_FEATURE_V6);
79 set_feature(env, ARM_FEATURE_VFP);
80 set_feature(env, ARM_FEATURE_AUXCR);
81 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
82 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
83 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
84 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 85 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 86 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 87 env->cp15.c1_sys = 0x00050078;
9ee6e8bb
PB		 88 break;
89 case ARM_CPUID_ARM11MPCORE:
be5e7a76
DES		 90 set_feature(env, ARM_FEATURE_V4T);
91 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 92 set_feature(env, ARM_FEATURE_V6);
93 set_feature(env, ARM_FEATURE_V6K);
94 set_feature(env, ARM_FEATURE_VFP);
95 set_feature(env, ARM_FEATURE_AUXCR);
96 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
97 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
98 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
99 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 100 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 101 env->cp15.c0_cachetype = 0x1dd20d2;
102 break;
103 case ARM_CPUID_CORTEXA8:
be5e7a76
DES		 104 set_feature(env, ARM_FEATURE_V4T);
105 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 106 set_feature(env, ARM_FEATURE_V6);
107 set_feature(env, ARM_FEATURE_V6K);
108 set_feature(env, ARM_FEATURE_V7);
109 set_feature(env, ARM_FEATURE_AUXCR);
110 set_feature(env, ARM_FEATURE_THUMB2);
111 set_feature(env, ARM_FEATURE_VFP);
112 set_feature(env, ARM_FEATURE_VFP3);
113 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 114 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 115 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
116 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
117 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
118 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 119 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 120 env->cp15.c0_cachetype = 0x82048004;
121 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
122 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
123 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
124 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 125 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 126 break;
10055562 127 case ARM_CPUID_CORTEXA9:
be5e7a76
DES		 128 set_feature(env, ARM_FEATURE_V4T);
129 set_feature(env, ARM_FEATURE_V5);
10055562
PB		 130 set_feature(env, ARM_FEATURE_V6);
131 set_feature(env, ARM_FEATURE_V6K);
132 set_feature(env, ARM_FEATURE_V7);
133 set_feature(env, ARM_FEATURE_AUXCR);
134 set_feature(env, ARM_FEATURE_THUMB2);
135 set_feature(env, ARM_FEATURE_VFP);
136 set_feature(env, ARM_FEATURE_VFP3);
137 set_feature(env, ARM_FEATURE_VFP_FP16);
138 set_feature(env, ARM_FEATURE_NEON);
139 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 140 /* Note that A9 supports the MP extensions even for
141 * A9UP and single-core A9MP (which are both different
142 * and valid configurations; we don't model A9UP).
143 */
144 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 145 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
146 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
147 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
148 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
149 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
150 env->cp15.c0_cachetype = 0x80038003;
151 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
152 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
153 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 154 env->cp15.c1_sys = 0x00c50078;
10055562 155 break;
9ee6e8bb 156 case ARM_CPUID_CORTEXM3:
be5e7a76
DES		 157 set_feature(env, ARM_FEATURE_V4T);
158 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 159 set_feature(env, ARM_FEATURE_V6);
160 set_feature(env, ARM_FEATURE_THUMB2);
161 set_feature(env, ARM_FEATURE_V7);
162 set_feature(env, ARM_FEATURE_M);
163 set_feature(env, ARM_FEATURE_DIV);
164 break;
165 case ARM_CPUID_ANY: /* For userspace emulation. */
be5e7a76
DES		 166 set_feature(env, ARM_FEATURE_V4T);
167 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 168 set_feature(env, ARM_FEATURE_V6);
169 set_feature(env, ARM_FEATURE_V6K);
170 set_feature(env, ARM_FEATURE_V7);
171 set_feature(env, ARM_FEATURE_THUMB2);
172 set_feature(env, ARM_FEATURE_VFP);
173 set_feature(env, ARM_FEATURE_VFP3);
60011498 174 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 175 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 176 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb 177 set_feature(env, ARM_FEATURE_DIV);
e1bbf446 178 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 179 break;
c3d2689d
AZ		 180 case ARM_CPUID_TI915T:
181 case ARM_CPUID_TI925T:
be5e7a76 182 set_feature(env, ARM_FEATURE_V4T);
c3d2689d
AZ		 183 set_feature(env, ARM_FEATURE_OMAPCP);
184 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
185 env->cp15.c0_cachetype = 0x5109149;
186 env->cp15.c1_sys = 0x00000070;
187 env->cp15.c15_i_max = 0x000;
188 env->cp15.c15_i_min = 0xff0;
189 break;
c1713132
AZ		 190 case ARM_CPUID_PXA250:
191 case ARM_CPUID_PXA255:
192 case ARM_CPUID_PXA260:
193 case ARM_CPUID_PXA261:
194 case ARM_CPUID_PXA262:
be5e7a76
DES		 195 set_feature(env, ARM_FEATURE_V4T);
196 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 197 set_feature(env, ARM_FEATURE_XSCALE);
198 /* JTAG_ID is ((id << 28) | 0x09265013) */
199 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 200 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 201 break;
202 case ARM_CPUID_PXA270_A0:
203 case ARM_CPUID_PXA270_A1:
204 case ARM_CPUID_PXA270_B0:
205 case ARM_CPUID_PXA270_B1:
206 case ARM_CPUID_PXA270_C0:
207 case ARM_CPUID_PXA270_C5:
be5e7a76
DES		 208 set_feature(env, ARM_FEATURE_V4T);
209 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 210 set_feature(env, ARM_FEATURE_XSCALE);
211 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 212 set_feature(env, ARM_FEATURE_IWMMXT);
213 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 214 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 215 env->cp15.c1_sys = 0x00000078;
f3d6b95e 216 break;
5bc95aa2
DES		 217 case ARM_CPUID_SA1100:
218 case ARM_CPUID_SA1110:
219 set_feature(env, ARM_FEATURE_STRONGARM);
220 env->cp15.c1_sys = 0x00000070;
221 break;
f3d6b95e
PB		 222 default:
223 cpu_abort(env, "Bad CPU ID: %x\n", id);
224 break;
225 }
226}
227
40f137e1
PB		 228void cpu_reset(CPUARMState *env)
229{
f3d6b95e 230 uint32_t id;
eca1bdf4
AL		 231
232 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
233 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
234 log_cpu_state(env, 0);
235 }
236
f3d6b95e
PB		 237 id = env->cp15.c0_cpuid;
238 memset(env, 0, offsetof(CPUARMState, breakpoints));
239 if (id)
240 cpu_reset_model_id(env, id);
40f137e1
PB		 241#if defined (CONFIG_USER_ONLY)
242 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 243 /* For user mode we must enable access to coprocessors */
40f137e1 244 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 245 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
246 env->cp15.c15_cpar = 3;
247 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
248 env->cp15.c15_cpar = 1;
249 }
40f137e1
PB		 250#else
251 /* SVC mode with interrupts disabled. */
252 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 253 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 254 clear at reset. Initial SP and PC are loaded from ROM. */
255 if (IS_M(env)) {
256 uint32_t pc;
257 uint8_t *rom;
9ee6e8bb 258 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 259 rom = rom_ptr(0);
260 if (rom) {
261 /* We should really use ldl_phys here, in case the guest
262 modified flash and reset itself. However images
263 loaded via -kenrel have not been copied yet, so load the
264 values directly from there. */
265 env->regs[13] = ldl_p(rom);
266 pc = ldl_p(rom + 4);
267 env->thumb = pc & 1;
268 env->regs[15] = pc & ~1;
269 }
270 }
40f137e1 271 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 272 env->cp15.c2_base_mask = 0xffffc000u;
40f137e1 273#endif
3a492f3a
PM		 274 set_flush_to_zero(1, &env->vfp.standard_fp_status);
275 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
276 set_default_nan_mode(1, &env->vfp.standard_fp_status);
9df38c47
PM		 277 set_float_detect_tininess(float_tininess_before_rounding,
278 &env->vfp.fp_status);
279 set_float_detect_tininess(float_tininess_before_rounding,
280 &env->vfp.standard_fp_status);
f3d6b95e 281 tlb_flush(env, 1);
40f137e1
PB		 282}
283
56aebc89
PB		 284static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
285{
286 int nregs;
287
288 /* VFP data registers are always little-endian. */
289 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
290 if (reg < nregs) {
291 stfq_le_p(buf, env->vfp.regs[reg]);
292 return 8;
293 }
294 if (arm_feature(env, ARM_FEATURE_NEON)) {
295 /* Aliases for Q regs. */
296 nregs += 16;
297 if (reg < nregs) {
298 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
299 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
300 return 16;
301 }
302 }
303 switch (reg - nregs) {
304 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
305 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
306 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
307 }
308 return 0;
309}
310
311static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
312{
313 int nregs;
314
315 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
316 if (reg < nregs) {
317 env->vfp.regs[reg] = ldfq_le_p(buf);
318 return 8;
319 }
320 if (arm_feature(env, ARM_FEATURE_NEON)) {
321 nregs += 16;
322 if (reg < nregs) {
323 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
324 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
325 return 16;
326 }
327 }
328 switch (reg - nregs) {
329 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
330 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 331 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 332 }
333 return 0;
334}
335
aaed909a 336CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 337{
338 CPUARMState *env;
aaed909a 339 uint32_t id;
b26eefb6 340 static int inited = 0;
40f137e1 341
aaed909a
FB		 342 id = cpu_arm_find_by_name(cpu_model);
343 if (id == 0)
344 return NULL;
40f137e1 345 env = qemu_mallocz(sizeof(CPUARMState));
40f137e1 346 cpu_exec_init(env);
b26eefb6
PB		 347 if (!inited) {
348 inited = 1;
349 arm_translate_init();
350 }
351
01ba9816 352 env->cpu_model_str = cpu_model;
aaed909a 353 env->cp15.c0_cpuid = id;
40f137e1 354 cpu_reset(env);
56aebc89
PB		 355 if (arm_feature(env, ARM_FEATURE_NEON)) {
356 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
357 51, "arm-neon.xml", 0);
358 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
359 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
360 35, "arm-vfp3.xml", 0);
361 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
362 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
363 19, "arm-vfp.xml", 0);
364 }
0bf46a40 365 qemu_init_vcpu(env);
40f137e1
PB		 366 return env;
367}
368
3371d272
PB		 369struct arm_cpu_t {
370 uint32_t id;
371 const char *name;
372};
373
374static const struct arm_cpu_t arm_cpu_names[] = {
375 { ARM_CPUID_ARM926, "arm926"},
ce819861 376 { ARM_CPUID_ARM946, "arm946"},
3371d272 377 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 378 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 379 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 380 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
381 { ARM_CPUID_CORTEXM3, "cortex-m3"},
382 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 383 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 384 { ARM_CPUID_TI925T, "ti925t" },
c1713132 385 { ARM_CPUID_PXA250, "pxa250" },
5bc95aa2
DES		 386 { ARM_CPUID_SA1100, "sa1100" },
387 { ARM_CPUID_SA1110, "sa1110" },
c1713132
AZ		 388 { ARM_CPUID_PXA255, "pxa255" },
389 { ARM_CPUID_PXA260, "pxa260" },
390 { ARM_CPUID_PXA261, "pxa261" },
391 { ARM_CPUID_PXA262, "pxa262" },
392 { ARM_CPUID_PXA270, "pxa270" },
393 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
394 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
395 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
396 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
397 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
398 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 399 { ARM_CPUID_ANY, "any"},
3371d272
PB		 400 { 0, NULL}
401};
402
9a78eead 403void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 404{
405 int i;
406
c732abe2 407 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 408 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 409 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 410 }
411}
412
aaed909a
FB		 413/* return 0 if not found */
414static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 415{
3371d272
PB		 416 int i;
417 uint32_t id;
418
419 id = 0;
3371d272
PB		 420 for (i = 0; arm_cpu_names[i].name; i++) {
421 if (strcmp(name, arm_cpu_names[i].name) == 0) {
422 id = arm_cpu_names[i].id;
423 break;
424 }
425 }
aaed909a 426 return id;
40f137e1
PB		 427}
428
429void cpu_arm_close(CPUARMState *env)
430{
431 free(env);
432}
433
2f4a40e5
AZ		 434uint32_t cpsr_read(CPUARMState *env)
435{
436 int ZF;
6fbe23d5
PB		 437 ZF = (env->ZF == 0);
438 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 439 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
440 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
441 | ((env->condexec_bits & 0xfc) << 8)
442 | (env->GE << 16);
443}
444
445void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
446{
2f4a40e5 447 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 448 env->ZF = (~val) & CPSR_Z;
449 env->NF = val;
2f4a40e5
AZ		 450 env->CF = (val >> 29) & 1;
451 env->VF = (val << 3) & 0x80000000;
452 }
453 if (mask & CPSR_Q)
454 env->QF = ((val & CPSR_Q) != 0);
455 if (mask & CPSR_T)
456 env->thumb = ((val & CPSR_T) != 0);
457 if (mask & CPSR_IT_0_1) {
458 env->condexec_bits &= ~3;
459 env->condexec_bits |= (val >> 25) & 3;
460 }
461 if (mask & CPSR_IT_2_7) {
462 env->condexec_bits &= 3;
463 env->condexec_bits |= (val >> 8) & 0xfc;
464 }
465 if (mask & CPSR_GE) {
466 env->GE = (val >> 16) & 0xf;
467 }
468
469 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
470 switch_mode(env, val & CPSR_M);
471 }
472 mask &= ~CACHED_CPSR_BITS;
473 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
474}
475
b26eefb6
PB		 476/* Sign/zero extend */
477uint32_t HELPER(sxtb16)(uint32_t x)
478{
479 uint32_t res;
480 res = (uint16_t)(int8_t)x;
481 res |= (uint32_t)(int8_t)(x >> 16) << 16;
482 return res;
483}
484
485uint32_t HELPER(uxtb16)(uint32_t x)
486{
487 uint32_t res;
488 res = (uint16_t)(uint8_t)x;
489 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
490 return res;
491}
492
f51bbbfe
PB		 493uint32_t HELPER(clz)(uint32_t x)
494{
7bbcb0af 495 return clz32(x);
f51bbbfe
PB		 496}
497
3670669c
PB		 498int32_t HELPER(sdiv)(int32_t num, int32_t den)
499{
500 if (den == 0)
501 return 0;
686eeb93
AJ		 502 if (num == INT_MIN && den == -1)
503 return INT_MIN;
3670669c
PB		 504 return num / den;
505}
506
507uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
508{
509 if (den == 0)
510 return 0;
511 return num / den;
512}
513
514uint32_t HELPER(rbit)(uint32_t x)
515{
516 x = ((x & 0xff000000) >> 24)
517 | ((x & 0x00ff0000) >> 8)
518 | ((x & 0x0000ff00) << 8)
519 | ((x & 0x000000ff) << 24);
520 x = ((x & 0xf0f0f0f0) >> 4)
521 | ((x & 0x0f0f0f0f) << 4);
522 x = ((x & 0x88888888) >> 3)
523 | ((x & 0x44444444) >> 1)
524 | ((x & 0x22222222) << 1)
525 | ((x & 0x11111111) << 3);
526 return x;
527}
528
ad69471c
PB		 529uint32_t HELPER(abs)(uint32_t x)
530{
531 return ((int32_t)x < 0) ? -x : x;
532}
533
5fafdf24 534#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 535
536void do_interrupt (CPUState *env)
537{
538 env->exception_index = -1;
539}
540
541int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 542 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 543{
544 if (rw == 2) {
545 env->exception_index = EXCP_PREFETCH_ABORT;
546 env->cp15.c6_insn = address;
547 } else {
548 env->exception_index = EXCP_DATA_ABORT;
549 env->cp15.c6_data = address;
550 }
551 return 1;
552}
553
b5ff1b31 554/* These should probably raise undefined insn exceptions. */
8984bd2e 555void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 556{
557 int op1 = (insn >> 8) & 0xf;
558 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
559 return;
560}
561
8984bd2e 562uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 563{
564 int op1 = (insn >> 8) & 0xf;
565 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
566 return 0;
567}
568
8984bd2e 569void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 570{
571 cpu_abort(env, "cp15 insn %08x\n", insn);
572}
573
8984bd2e 574uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 575{
576 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 577}
578
9ee6e8bb 579/* These should probably raise undefined insn exceptions. */
8984bd2e 580void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 581{
582 cpu_abort(env, "v7m_mrs %d\n", reg);
583}
584
8984bd2e 585uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 586{
587 cpu_abort(env, "v7m_mrs %d\n", reg);
588 return 0;
589}
590
b5ff1b31
FB		 591void switch_mode(CPUState *env, int mode)
592{
593 if (mode != ARM_CPU_MODE_USR)
594 cpu_abort(env, "Tried to switch out of user mode\n");
595}
596
b0109805 597void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 598{
599 cpu_abort(env, "banked r13 write\n");
600}
601
b0109805 602uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 603{
604 cpu_abort(env, "banked r13 read\n");
605 return 0;
606}
607
b5ff1b31
FB		 608#else
609
8e71621f
PB		 610extern int semihosting_enabled;
611
b5ff1b31
FB		 612/* Map CPU modes onto saved register banks. */
613static inline int bank_number (int mode)
614{
615 switch (mode) {
616 case ARM_CPU_MODE_USR:
617 case ARM_CPU_MODE_SYS:
618 return 0;
619 case ARM_CPU_MODE_SVC:
620 return 1;
621 case ARM_CPU_MODE_ABT:
622 return 2;
623 case ARM_CPU_MODE_UND:
624 return 3;
625 case ARM_CPU_MODE_IRQ:
626 return 4;
627 case ARM_CPU_MODE_FIQ:
628 return 5;
629 }
630 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
631 return -1;
632}
633
634void switch_mode(CPUState *env, int mode)
635{
636 int old_mode;
637 int i;
638
639 old_mode = env->uncached_cpsr & CPSR_M;
640 if (mode == old_mode)
641 return;
642
643 if (old_mode == ARM_CPU_MODE_FIQ) {
644 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 645 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 646 } else if (mode == ARM_CPU_MODE_FIQ) {
647 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 648 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 649 }
650
651 i = bank_number(old_mode);
652 env->banked_r13[i] = env->regs[13];
653 env->banked_r14[i] = env->regs[14];
654 env->banked_spsr[i] = env->spsr;
655
656 i = bank_number(mode);
657 env->regs[13] = env->banked_r13[i];
658 env->regs[14] = env->banked_r14[i];
659 env->spsr = env->banked_spsr[i];
660}
661
9ee6e8bb
PB		 662static void v7m_push(CPUARMState *env, uint32_t val)
663{
664 env->regs[13] -= 4;
665 stl_phys(env->regs[13], val);
666}
667
668static uint32_t v7m_pop(CPUARMState *env)
669{
670 uint32_t val;
671 val = ldl_phys(env->regs[13]);
672 env->regs[13] += 4;
673 return val;
674}
675
676/* Switch to V7M main or process stack pointer. */
677static void switch_v7m_sp(CPUARMState *env, int process)
678{
679 uint32_t tmp;
680 if (env->v7m.current_sp != process) {
681 tmp = env->v7m.other_sp;
682 env->v7m.other_sp = env->regs[13];
683 env->regs[13] = tmp;
684 env->v7m.current_sp = process;
685 }
686}
687
688static void do_v7m_exception_exit(CPUARMState *env)
689{
690 uint32_t type;
691 uint32_t xpsr;
692
693 type = env->regs[15];
694 if (env->v7m.exception != 0)
983fe826 695 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 696
697 /* Switch to the target stack. */
698 switch_v7m_sp(env, (type & 4) != 0);
699 /* Pop registers. */
700 env->regs[0] = v7m_pop(env);
701 env->regs[1] = v7m_pop(env);
702 env->regs[2] = v7m_pop(env);
703 env->regs[3] = v7m_pop(env);
704 env->regs[12] = v7m_pop(env);
705 env->regs[14] = v7m_pop(env);
706 env->regs[15] = v7m_pop(env);
707 xpsr = v7m_pop(env);
708 xpsr_write(env, xpsr, 0xfffffdff);
709 /* Undo stack alignment. */
710 if (xpsr & 0x200)
711 env->regs[13] |= 4;
712 /* ??? The exception return type specifies Thread/Handler mode. However
713 this is also implied by the xPSR value. Not sure what to do
714 if there is a mismatch. */
715 /* ??? Likewise for mismatches between the CONTROL register and the stack
716 pointer. */
717}
718
2b3ea315 719static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 720{
721 uint32_t xpsr = xpsr_read(env);
722 uint32_t lr;
723 uint32_t addr;
724
725 lr = 0xfffffff1;
726 if (env->v7m.current_sp)
727 lr |= 4;
728 if (env->v7m.exception == 0)
729 lr |= 8;
730
731 /* For exceptions we just mark as pending on the NVIC, and let that
732 handle it. */
733 /* TODO: Need to escalate if the current priority is higher than the
734 one we're raising. */
735 switch (env->exception_index) {
736 case EXCP_UDEF:
983fe826 737 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 738 return;
739 case EXCP_SWI:
740 env->regs[15] += 2;
983fe826 741 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 742 return;
743 case EXCP_PREFETCH_ABORT:
744 case EXCP_DATA_ABORT:
983fe826 745 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 746 return;
747 case EXCP_BKPT:
2ad207d4
PB		 748 if (semihosting_enabled) {
749 int nr;
750 nr = lduw_code(env->regs[15]) & 0xff;
751 if (nr == 0xab) {
752 env->regs[15] += 2;
753 env->regs[0] = do_arm_semihosting(env);
754 return;
755 }
756 }
983fe826 757 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 758 return;
759 case EXCP_IRQ:
983fe826 760 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 761 break;
762 case EXCP_EXCEPTION_EXIT:
763 do_v7m_exception_exit(env);
764 return;
765 default:
766 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
767 return; /* Never happens. Keep compiler happy. */
768 }
769
770 /* Align stack pointer. */
771 /* ??? Should only do this if Configuration Control Register
772 STACKALIGN bit is set. */
773 if (env->regs[13] & 4) {
ab19b0ec 774 env->regs[13] -= 4;
9ee6e8bb
PB		 775 xpsr |= 0x200;
776 }
6c95676b 777 /* Switch to the handler mode. */
9ee6e8bb
PB		 778 v7m_push(env, xpsr);
779 v7m_push(env, env->regs[15]);
780 v7m_push(env, env->regs[14]);
781 v7m_push(env, env->regs[12]);
782 v7m_push(env, env->regs[3]);
783 v7m_push(env, env->regs[2]);
784 v7m_push(env, env->regs[1]);
785 v7m_push(env, env->regs[0]);
786 switch_v7m_sp(env, 0);
787 env->uncached_cpsr &= ~CPSR_IT;
788 env->regs[14] = lr;
789 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
790 env->regs[15] = addr & 0xfffffffe;
791 env->thumb = addr & 1;
792}
793
b5ff1b31
FB		 794/* Handle a CPU exception. */
795void do_interrupt(CPUARMState *env)
796{
797 uint32_t addr;
798 uint32_t mask;
799 int new_mode;
800 uint32_t offset;
801
9ee6e8bb
PB		 802 if (IS_M(env)) {
803 do_interrupt_v7m(env);
804 return;
805 }
b5ff1b31
FB		 806 /* TODO: Vectored interrupt controller. */
807 switch (env->exception_index) {
808 case EXCP_UDEF:
809 new_mode = ARM_CPU_MODE_UND;
810 addr = 0x04;
811 mask = CPSR_I;
812 if (env->thumb)
813 offset = 2;
814 else
815 offset = 4;
816 break;
817 case EXCP_SWI:
8e71621f
PB		 818 if (semihosting_enabled) {
819 /* Check for semihosting interrupt. */
820 if (env->thumb) {
821 mask = lduw_code(env->regs[15] - 2) & 0xff;
822 } else {
823 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
824 }
825 /* Only intercept calls from privileged modes, to provide some
826 semblance of security. */
827 if (((mask == 0x123456 && !env->thumb)
828 || (mask == 0xab && env->thumb))
829 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
830 env->regs[0] = do_arm_semihosting(env);
831 return;
832 }
833 }
b5ff1b31
FB		 834 new_mode = ARM_CPU_MODE_SVC;
835 addr = 0x08;
836 mask = CPSR_I;
601d70b9 837 /* The PC already points to the next instruction. */
b5ff1b31
FB		 838 offset = 0;
839 break;
06c949e6 840 case EXCP_BKPT:
9ee6e8bb 841 /* See if this is a semihosting syscall. */
2ad207d4 842 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 843 mask = lduw_code(env->regs[15]) & 0xff;
844 if (mask == 0xab
845 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
846 env->regs[15] += 2;
847 env->regs[0] = do_arm_semihosting(env);
848 return;
849 }
850 }
81c05daf 851 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 852 /* Fall through to prefetch abort. */
853 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 854 new_mode = ARM_CPU_MODE_ABT;
855 addr = 0x0c;
856 mask = CPSR_A | CPSR_I;
857 offset = 4;
858 break;
859 case EXCP_DATA_ABORT:
860 new_mode = ARM_CPU_MODE_ABT;
861 addr = 0x10;
862 mask = CPSR_A | CPSR_I;
863 offset = 8;
864 break;
865 case EXCP_IRQ:
866 new_mode = ARM_CPU_MODE_IRQ;
867 addr = 0x18;
868 /* Disable IRQ and imprecise data aborts. */
869 mask = CPSR_A | CPSR_I;
870 offset = 4;
871 break;
872 case EXCP_FIQ:
873 new_mode = ARM_CPU_MODE_FIQ;
874 addr = 0x1c;
875 /* Disable FIQ, IRQ and imprecise data aborts. */
876 mask = CPSR_A | CPSR_I | CPSR_F;
877 offset = 4;
878 break;
879 default:
880 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
881 return; /* Never happens. Keep compiler happy. */
882 }
883 /* High vectors. */
884 if (env->cp15.c1_sys & (1 << 13)) {
885 addr += 0xffff0000;
886 }
887 switch_mode (env, new_mode);
888 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 889 /* Clear IT bits. */
890 env->condexec_bits = 0;
30a8cac1 891 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 892 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 893 env->uncached_cpsr |= mask;
be5e7a76
DES		 894 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
895 * and we should just guard the thumb mode on V4 */
896 if (arm_feature(env, ARM_FEATURE_V4T)) {
897 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
898 }
b5ff1b31
FB		 899 env->regs[14] = env->regs[15] + offset;
900 env->regs[15] = addr;
901 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
902}
903
904/* Check section/page access permissions.
905 Returns the page protection flags, or zero if the access is not
906 permitted. */
907static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
908 int is_user)
909{
9ee6e8bb
PB		 910 int prot_ro;
911
b5ff1b31
FB		 912 if (domain == 3)
913 return PAGE_READ | PAGE_WRITE;
914
9ee6e8bb
PB		 915 if (access_type == 1)
916 prot_ro = 0;
917 else
918 prot_ro = PAGE_READ;
919
b5ff1b31
FB		 920 switch (ap) {
921 case 0:
78600320 922 if (access_type == 1)
b5ff1b31
FB		 923 return 0;
924 switch ((env->cp15.c1_sys >> 8) & 3) {
925 case 1:
926 return is_user ? 0 : PAGE_READ;
927 case 2:
928 return PAGE_READ;
929 default:
930 return 0;
931 }
932 case 1:
933 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
934 case 2:
935 if (is_user)
9ee6e8bb 936 return prot_ro;
b5ff1b31
FB		 937 else
938 return PAGE_READ | PAGE_WRITE;
939 case 3:
940 return PAGE_READ | PAGE_WRITE;
d4934d18 941 case 4: /* Reserved. */
9ee6e8bb
PB		 942 return 0;
943 case 5:
944 return is_user ? 0 : prot_ro;
945 case 6:
946 return prot_ro;
d4934d18
PB		 947 case 7:
948 if (!arm_feature (env, ARM_FEATURE_V7))
949 return 0;
950 return prot_ro;
b5ff1b31
FB		 951 default:
952 abort();
953 }
954}
955
b2fa1797
PB		 956static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
957{
958 uint32_t table;
959
960 if (address & env->cp15.c2_mask)
961 table = env->cp15.c2_base1 & 0xffffc000;
962 else
963 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
964
965 table |= (address >> 18) & 0x3ffc;
966 return table;
967}
968
9ee6e8bb 969static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 970 int is_user, uint32_t *phys_ptr, int *prot,
971 target_ulong *page_size)
b5ff1b31
FB		 972{
973 int code;
974 uint32_t table;
975 uint32_t desc;
976 int type;
977 int ap;
978 int domain;
979 uint32_t phys_addr;
980
9ee6e8bb
PB		 981 /* Pagetable walk. */
982 /* Lookup l1 descriptor. */
b2fa1797 983 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 984 desc = ldl_phys(table);
985 type = (desc & 3);
986 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
987 if (type == 0) {
601d70b9 988 /* Section translation fault. */
9ee6e8bb
PB		 989 code = 5;
990 goto do_fault;
991 }
992 if (domain == 0 || domain == 2) {
993 if (type == 2)
994 code = 9; /* Section domain fault. */
995 else
996 code = 11; /* Page domain fault. */
997 goto do_fault;
998 }
999 if (type == 2) {
1000 /* 1Mb section. */
1001 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1002 ap = (desc >> 10) & 3;
1003 code = 13;
d4c430a8 1004 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1005 } else {
1006 /* Lookup l2 entry. */
1007 if (type == 1) {
1008 /* Coarse pagetable. */
1009 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1010 } else {
1011 /* Fine pagetable. */
1012 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1013 }
1014 desc = ldl_phys(table);
1015 switch (desc & 3) {
1016 case 0: /* Page translation fault. */
1017 code = 7;
1018 goto do_fault;
1019 case 1: /* 64k page. */
1020 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1021 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1022 *page_size = 0x10000;
ce819861 1023 break;
9ee6e8bb
PB		 1024 case 2: /* 4k page. */
1025 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1026 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1027 *page_size = 0x1000;
ce819861 1028 break;
9ee6e8bb
PB		 1029 case 3: /* 1k page. */
1030 if (type == 1) {
1031 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1032 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1033 } else {
1034 /* Page translation fault. */
1035 code = 7;
1036 goto do_fault;
1037 }
1038 } else {
1039 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1040 }
1041 ap = (desc >> 4) & 3;
d4c430a8 1042 *page_size = 0x400;
ce819861
PB		 1043 break;
1044 default:
9ee6e8bb
PB		 1045 /* Never happens, but compiler isn't smart enough to tell. */
1046 abort();
ce819861 1047 }
9ee6e8bb
PB		 1048 code = 15;
1049 }
1050 *prot = check_ap(env, ap, domain, access_type, is_user);
1051 if (!*prot) {
1052 /* Access permission fault. */
1053 goto do_fault;
1054 }
3ad493fc 1055 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1056 *phys_ptr = phys_addr;
1057 return 0;
1058do_fault:
1059 return code | (domain << 4);
1060}
1061
1062static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1063 int is_user, uint32_t *phys_ptr, int *prot,
1064 target_ulong *page_size)
9ee6e8bb
PB		 1065{
1066 int code;
1067 uint32_t table;
1068 uint32_t desc;
1069 uint32_t xn;
1070 int type;
1071 int ap;
1072 int domain;
1073 uint32_t phys_addr;
1074
1075 /* Pagetable walk. */
1076 /* Lookup l1 descriptor. */
b2fa1797 1077 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1078 desc = ldl_phys(table);
1079 type = (desc & 3);
1080 if (type == 0) {
601d70b9 1081 /* Section translation fault. */
9ee6e8bb
PB		 1082 code = 5;
1083 domain = 0;
1084 goto do_fault;
1085 } else if (type == 2 && (desc & (1 << 18))) {
1086 /* Supersection. */
1087 domain = 0;
b5ff1b31 1088 } else {
9ee6e8bb
PB		 1089 /* Section or page. */
1090 domain = (desc >> 4) & 0x1e;
1091 }
1092 domain = (env->cp15.c3 >> domain) & 3;
1093 if (domain == 0 || domain == 2) {
1094 if (type == 2)
1095 code = 9; /* Section domain fault. */
1096 else
1097 code = 11; /* Page domain fault. */
1098 goto do_fault;
1099 }
1100 if (type == 2) {
1101 if (desc & (1 << 18)) {
1102 /* Supersection. */
1103 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1104 *page_size = 0x1000000;
b5ff1b31 1105 } else {
9ee6e8bb
PB		 1106 /* Section. */
1107 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1108 *page_size = 0x100000;
b5ff1b31 1109 }
9ee6e8bb
PB		 1110 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1111 xn = desc & (1 << 4);
1112 code = 13;
1113 } else {
1114 /* Lookup l2 entry. */
1115 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1116 desc = ldl_phys(table);
1117 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1118 switch (desc & 3) {
1119 case 0: /* Page translation fault. */
1120 code = 7;
b5ff1b31 1121 goto do_fault;
9ee6e8bb
PB		 1122 case 1: /* 64k page. */
1123 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1124 xn = desc & (1 << 15);
d4c430a8 1125 *page_size = 0x10000;
9ee6e8bb
PB		 1126 break;
1127 case 2: case 3: /* 4k page. */
1128 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1129 xn = desc & 1;
d4c430a8 1130 *page_size = 0x1000;
9ee6e8bb
PB		 1131 break;
1132 default:
1133 /* Never happens, but compiler isn't smart enough to tell. */
1134 abort();
b5ff1b31 1135 }
9ee6e8bb
PB		 1136 code = 15;
1137 }
c0034328
JR		 1138 if (domain == 3) {
1139 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1140 } else {
1141 if (xn && access_type == 2)
1142 goto do_fault;
9ee6e8bb 1143
c0034328
JR		 1144 /* The simplified model uses AP[0] as an access control bit. */
1145 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1146 /* Access flag fault. */
1147 code = (code == 15) ? 6 : 3;
1148 goto do_fault;
1149 }
1150 *prot = check_ap(env, ap, domain, access_type, is_user);
1151 if (!*prot) {
1152 /* Access permission fault. */
1153 goto do_fault;
1154 }
1155 if (!xn) {
1156 *prot |= PAGE_EXEC;
1157 }
3ad493fc 1158 }
9ee6e8bb 1159 *phys_ptr = phys_addr;
b5ff1b31
FB		 1160 return 0;
1161do_fault:
1162 return code | (domain << 4);
1163}
1164
9ee6e8bb
PB		 1165static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1166 int is_user, uint32_t *phys_ptr, int *prot)
1167{
1168 int n;
1169 uint32_t mask;
1170 uint32_t base;
1171
1172 *phys_ptr = address;
1173 for (n = 7; n >= 0; n--) {
1174 base = env->cp15.c6_region[n];
1175 if ((base & 1) == 0)
1176 continue;
1177 mask = 1 << ((base >> 1) & 0x1f);
1178 /* Keep this shift separate from the above to avoid an
1179 (undefined) << 32. */
1180 mask = (mask << 1) - 1;
1181 if (((base ^ address) & ~mask) == 0)
1182 break;
1183 }
1184 if (n < 0)
1185 return 2;
1186
1187 if (access_type == 2) {
1188 mask = env->cp15.c5_insn;
1189 } else {
1190 mask = env->cp15.c5_data;
1191 }
1192 mask = (mask >> (n * 4)) & 0xf;
1193 switch (mask) {
1194 case 0:
1195 return 1;
1196 case 1:
1197 if (is_user)
1198 return 1;
1199 *prot = PAGE_READ | PAGE_WRITE;
1200 break;
1201 case 2:
1202 *prot = PAGE_READ;
1203 if (!is_user)
1204 *prot |= PAGE_WRITE;
1205 break;
1206 case 3:
1207 *prot = PAGE_READ | PAGE_WRITE;
1208 break;
1209 case 5:
1210 if (is_user)
1211 return 1;
1212 *prot = PAGE_READ;
1213 break;
1214 case 6:
1215 *prot = PAGE_READ;
1216 break;
1217 default:
1218 /* Bad permission. */
1219 return 1;
1220 }
3ad493fc 1221 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1222 return 0;
1223}
1224
1225static inline int get_phys_addr(CPUState *env, uint32_t address,
1226 int access_type, int is_user,
d4c430a8
PB		 1227 uint32_t *phys_ptr, int *prot,
1228 target_ulong *page_size)
9ee6e8bb
PB		 1229{
1230 /* Fast Context Switch Extension. */
1231 if (address < 0x02000000)
1232 address += env->cp15.c13_fcse;
1233
1234 if ((env->cp15.c1_sys & 1) == 0) {
1235 /* MMU/MPU disabled. */
1236 *phys_ptr = address;
3ad493fc 1237 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1238 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1239 return 0;
1240 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1241 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1242 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1243 prot);
1244 } else if (env->cp15.c1_sys & (1 << 23)) {
1245 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1246 prot, page_size);
9ee6e8bb
PB		 1247 } else {
1248 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1249 prot, page_size);
9ee6e8bb
PB		 1250 }
1251}
1252
b5ff1b31 1253int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1254 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1255{
1256 uint32_t phys_addr;
d4c430a8 1257 target_ulong page_size;
b5ff1b31 1258 int prot;
6ebbf390 1259 int ret, is_user;
b5ff1b31 1260
6ebbf390 1261 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1262 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1263 &page_size);
b5ff1b31
FB		 1264 if (ret == 0) {
1265 /* Map a single [sub]page. */
1266 phys_addr &= ~(uint32_t)0x3ff;
1267 address &= ~(uint32_t)0x3ff;
3ad493fc 1268 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1269 return 0;
b5ff1b31
FB		 1270 }
1271
1272 if (access_type == 2) {
1273 env->cp15.c5_insn = ret;
1274 env->cp15.c6_insn = address;
1275 env->exception_index = EXCP_PREFETCH_ABORT;
1276 } else {
1277 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1278 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1279 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1280 env->cp15.c6_data = address;
1281 env->exception_index = EXCP_DATA_ABORT;
1282 }
1283 return 1;
1284}
1285
c227f099 1286target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1287{
1288 uint32_t phys_addr;
d4c430a8 1289 target_ulong page_size;
b5ff1b31
FB		 1290 int prot;
1291 int ret;
1292
d4c430a8 1293 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1294
1295 if (ret != 0)
1296 return -1;
1297
1298 return phys_addr;
1299}
1300
8984bd2e 1301void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1302{
1303 int cp_num = (insn >> 8) & 0xf;
1304 int cp_info = (insn >> 5) & 7;
1305 int src = (insn >> 16) & 0xf;
1306 int operand = insn & 0xf;
1307
1308 if (env->cp[cp_num].cp_write)
1309 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1310 cp_info, src, operand, val);
1311}
1312
8984bd2e 1313uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1314{
1315 int cp_num = (insn >> 8) & 0xf;
1316 int cp_info = (insn >> 5) & 7;
1317 int dest = (insn >> 16) & 0xf;
1318 int operand = insn & 0xf;
1319
1320 if (env->cp[cp_num].cp_read)
1321 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1322 cp_info, dest, operand);
1323 return 0;
1324}
1325
ce819861
PB		 1326/* Return basic MPU access permission bits. */
1327static uint32_t simple_mpu_ap_bits(uint32_t val)
1328{
1329 uint32_t ret;
1330 uint32_t mask;
1331 int i;
1332 ret = 0;
1333 mask = 3;
1334 for (i = 0; i < 16; i += 2) {
1335 ret |= (val >> i) & mask;
1336 mask <<= 2;
1337 }
1338 return ret;
1339}
1340
1341/* Pad basic MPU access permission bits to extended format. */
1342static uint32_t extended_mpu_ap_bits(uint32_t val)
1343{
1344 uint32_t ret;
1345 uint32_t mask;
1346 int i;
1347 ret = 0;
1348 mask = 3;
1349 for (i = 0; i < 16; i += 2) {
1350 ret |= (val & mask) << i;
1351 mask <<= 2;
1352 }
1353 return ret;
1354}
1355
8984bd2e 1356void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1357{
9ee6e8bb
PB		 1358 int op1;
1359 int op2;
1360 int crm;
b5ff1b31 1361
9ee6e8bb 1362 op1 = (insn >> 21) & 7;
b5ff1b31 1363 op2 = (insn >> 5) & 7;
ce819861 1364 crm = insn & 0xf;
b5ff1b31 1365 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1366 case 0:
9ee6e8bb 1367 /* ID codes. */
610c3c8a
AZ		 1368 if (arm_feature(env, ARM_FEATURE_XSCALE))
1369 break;
c3d2689d
AZ		 1370 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1371 break;
a49ea279
PB		 1372 if (arm_feature(env, ARM_FEATURE_V7)
1373 && op1 == 2 && crm == 0 && op2 == 0) {
1374 env->cp15.c0_cssel = val & 0xf;
1375 break;
1376 }
b5ff1b31
FB		 1377 goto bad_reg;
1378 case 1: /* System configuration. */
c3d2689d
AZ		 1379 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1380 op2 = 0;
b5ff1b31
FB		 1381 switch (op2) {
1382 case 0:
ce819861 1383 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1384 env->cp15.c1_sys = val;
b5ff1b31
FB		 1385 /* ??? Lots of these bits are not implemented. */
1386 /* This may enable/disable the MMU, so do a TLB flush. */
1387 tlb_flush(env, 1);
1388 break;
61cc8701 1389 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1390 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1391 env->cp15.c1_xscaleauxcr = val;
c1713132 1392 break;
610c3c8a 1393 }
9ee6e8bb
PB		 1394 /* Not implemented. */
1395 break;
b5ff1b31 1396 case 2:
610c3c8a
AZ		 1397 if (arm_feature(env, ARM_FEATURE_XSCALE))
1398 goto bad_reg;
4be27dbb
PB		 1399 if (env->cp15.c1_coproc != val) {
1400 env->cp15.c1_coproc = val;
1401 /* ??? Is this safe when called from within a TB? */
1402 tb_flush(env);
1403 }
c1713132 1404 break;
b5ff1b31
FB		 1405 default:
1406 goto bad_reg;
1407 }
1408 break;
ce819861
PB		 1409 case 2: /* MMU Page table control / MPU cache control. */
1410 if (arm_feature(env, ARM_FEATURE_MPU)) {
1411 switch (op2) {
1412 case 0:
1413 env->cp15.c2_data = val;
1414 break;
1415 case 1:
1416 env->cp15.c2_insn = val;
1417 break;
1418 default:
1419 goto bad_reg;
1420 }
1421 } else {
9ee6e8bb
PB		 1422 switch (op2) {
1423 case 0:
1424 env->cp15.c2_base0 = val;
1425 break;
1426 case 1:
1427 env->cp15.c2_base1 = val;
1428 break;
1429 case 2:
b2fa1797
PB		 1430 val &= 7;
1431 env->cp15.c2_control = val;
9ee6e8bb 1432 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1433 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1434 break;
1435 default:
1436 goto bad_reg;
1437 }
ce819861 1438 }
b5ff1b31 1439 break;
ce819861 1440 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1441 env->cp15.c3 = val;
405ee3ad 1442 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1443 break;
1444 case 4: /* Reserved. */
1445 goto bad_reg;
ce819861 1446 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1447 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1448 op2 = 0;
b5ff1b31
FB		 1449 switch (op2) {
1450 case 0:
ce819861
PB		 1451 if (arm_feature(env, ARM_FEATURE_MPU))
1452 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1453 env->cp15.c5_data = val;
1454 break;
1455 case 1:
ce819861
PB		 1456 if (arm_feature(env, ARM_FEATURE_MPU))
1457 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1458 env->cp15.c5_insn = val;
1459 break;
ce819861
PB		 1460 case 2:
1461 if (!arm_feature(env, ARM_FEATURE_MPU))
1462 goto bad_reg;
1463 env->cp15.c5_data = val;
b5ff1b31 1464 break;
ce819861
PB		 1465 case 3:
1466 if (!arm_feature(env, ARM_FEATURE_MPU))
1467 goto bad_reg;
1468 env->cp15.c5_insn = val;
b5ff1b31
FB		 1469 break;
1470 default:
1471 goto bad_reg;
1472 }
1473 break;
ce819861
PB		 1474 case 6: /* MMU Fault address / MPU base/size. */
1475 if (arm_feature(env, ARM_FEATURE_MPU)) {
1476 if (crm >= 8)
1477 goto bad_reg;
1478 env->cp15.c6_region[crm] = val;
1479 } else {
c3d2689d
AZ		 1480 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1481 op2 = 0;
ce819861
PB		 1482 switch (op2) {
1483 case 0:
1484 env->cp15.c6_data = val;
1485 break;
9ee6e8bb
PB		 1486 case 1: /* ??? This is WFAR on armv6 */
1487 case 2:
ce819861
PB		 1488 env->cp15.c6_insn = val;
1489 break;
1490 default:
1491 goto bad_reg;
1492 }
1493 }
1494 break;
b5ff1b31 1495 case 7: /* Cache control. */
c3d2689d
AZ		 1496 env->cp15.c15_i_max = 0x000;
1497 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1498 if (op1 != 0) {
1499 goto bad_reg;
1500 }
1501 /* No cache, so nothing to do except VA->PA translations. */
1502 if (arm_feature(env, ARM_FEATURE_V6K)) {
1503 switch (crm) {
1504 case 4:
1505 if (arm_feature(env, ARM_FEATURE_V7)) {
1506 env->cp15.c7_par = val & 0xfffff6ff;
1507 } else {
1508 env->cp15.c7_par = val & 0xfffff1ff;
1509 }
1510 break;
1511 case 8: {
1512 uint32_t phys_addr;
1513 target_ulong page_size;
1514 int prot;
1515 int ret, is_user = op2 & 2;
1516 int access_type = op2 & 1;
1517
1518 if (op2 & 4) {
1519 /* Other states are only available with TrustZone */
1520 goto bad_reg;
1521 }
1522 ret = get_phys_addr(env, val, access_type, is_user,
1523 &phys_addr, &prot, &page_size);
1524 if (ret == 0) {
1525 /* We do not set any attribute bits in the PAR */
1526 if (page_size == (1 << 24)
1527 && arm_feature(env, ARM_FEATURE_V7)) {
1528 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1529 } else {
1530 env->cp15.c7_par = phys_addr & 0xfffff000;
1531 }
1532 } else {
1533 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1534 ((ret & (12 << 1)) >> 6) |
1535 ((ret & 0xf) << 1) | 1;
1536 }
1537 break;
1538 }
1539 }
1540 }
b5ff1b31
FB		 1541 break;
1542 case 8: /* MMU TLB control. */
1543 switch (op2) {
1544 case 0: /* Invalidate all. */
1545 tlb_flush(env, 0);
1546 break;
1547 case 1: /* Invalidate single TLB entry. */
d4c430a8 1548 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1549 break;
9ee6e8bb
PB		 1550 case 2: /* Invalidate on ASID. */
1551 tlb_flush(env, val == 0);
1552 break;
1553 case 3: /* Invalidate single entry on MVA. */
1554 /* ??? This is like case 1, but ignores ASID. */
1555 tlb_flush(env, 1);
1556 break;
b5ff1b31
FB		 1557 default:
1558 goto bad_reg;
1559 }
1560 break;
ce819861 1561 case 9:
c3d2689d
AZ		 1562 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1563 break;
5bc95aa2
DES		 1564 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1565 break; /* Ignore ReadBuffer access */
ce819861
PB		 1566 switch (crm) {
1567 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1568 switch (op1) {
1569 case 0: /* L1 cache. */
1570 switch (op2) {
1571 case 0:
1572 env->cp15.c9_data = val;
1573 break;
1574 case 1:
1575 env->cp15.c9_insn = val;
1576 break;
1577 default:
1578 goto bad_reg;
1579 }
1580 break;
1581 case 1: /* L2 cache. */
1582 /* Ignore writes to L2 lockdown/auxiliary registers. */
1583 break;
1584 default:
1585 goto bad_reg;
1586 }
1587 break;
ce819861
PB		 1588 case 1: /* TCM memory region registers. */
1589 /* Not implemented. */
1590 goto bad_reg;
b5ff1b31
FB		 1591 default:
1592 goto bad_reg;
1593 }
1594 break;
1595 case 10: /* MMU TLB lockdown. */
1596 /* ??? TLB lockdown not implemented. */
1597 break;
b5ff1b31
FB		 1598 case 12: /* Reserved. */
1599 goto bad_reg;
1600 case 13: /* Process ID. */
1601 switch (op2) {
1602 case 0:
d07edbfa
PB		 1603 /* Unlike real hardware the qemu TLB uses virtual addresses,
1604 not modified virtual addresses, so this causes a TLB flush.
1605 */
1606 if (env->cp15.c13_fcse != val)
1607 tlb_flush(env, 1);
1608 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1609 break;
1610 case 1:
d07edbfa 1611 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1612 if (env->cp15.c13_context != val
1613 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1614 tlb_flush(env, 0);
1615 env->cp15.c13_context = val;
b5ff1b31
FB		 1616 break;
1617 default:
1618 goto bad_reg;
1619 }
1620 break;
1621 case 14: /* Reserved. */
1622 goto bad_reg;
1623 case 15: /* Implementation specific. */
c1713132 1624 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1625 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1626 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1627 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1628 tb_flush(env);
1629 env->cp15.c15_cpar = val & 0x3fff;
1630 }
c1713132
AZ		 1631 break;
1632 }
1633 goto bad_reg;
1634 }
c3d2689d
AZ		 1635 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1636 switch (crm) {
1637 case 0:
1638 break;
1639 case 1: /* Set TI925T configuration. */
1640 env->cp15.c15_ticonfig = val & 0xe7;
1641 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1642 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1643 break;
1644 case 2: /* Set I_max. */
1645 env->cp15.c15_i_max = val;
1646 break;
1647 case 3: /* Set I_min. */
1648 env->cp15.c15_i_min = val;
1649 break;
1650 case 4: /* Set thread-ID. */
1651 env->cp15.c15_threadid = val & 0xffff;
1652 break;
1653 case 8: /* Wait-for-interrupt (deprecated). */
1654 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1655 break;
1656 default:
1657 goto bad_reg;
1658 }
1659 }
b5ff1b31
FB		 1660 break;
1661 }
1662 return;
1663bad_reg:
1664 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1665 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1666 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1667}
1668
8984bd2e 1669uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1670{
9ee6e8bb
PB		 1671 int op1;
1672 int op2;
1673 int crm;
b5ff1b31 1674
9ee6e8bb 1675 op1 = (insn >> 21) & 7;
b5ff1b31 1676 op2 = (insn >> 5) & 7;
c3d2689d 1677 crm = insn & 0xf;
b5ff1b31
FB		 1678 switch ((insn >> 16) & 0xf) {
1679 case 0: /* ID codes. */
9ee6e8bb
PB		 1680 switch (op1) {
1681 case 0:
1682 switch (crm) {
1683 case 0:
1684 switch (op2) {
1685 case 0: /* Device ID. */
1686 return env->cp15.c0_cpuid;
1687 case 1: /* Cache Type. */
1688 return env->cp15.c0_cachetype;
1689 case 2: /* TCM status. */
1690 return 0;
1691 case 3: /* TLB type register. */
1692 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1693 case 5: /* MPIDR */
1694 /* The MPIDR was standardised in v7; prior to
1695 * this it was implemented only in the 11MPCore.
1696 * For all other pre-v7 cores it does not exist.
1697 */
1698 if (arm_feature(env, ARM_FEATURE_V7) ||
1699 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1700 int mpidr = env->cpu_index;
1701 /* We don't support setting cluster ID ([8..11])
1702 * so these bits always RAZ.
1703 */
1704 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1705 mpidr |= (1 << 31);
1706 /* Cores which are uniprocessor (non-coherent)
1707 * but still implement the MP extensions set
1708 * bit 30. (For instance, A9UP.) However we do
1709 * not currently model any of those cores.
1710 */
1711 }
1712 return mpidr;
10055562 1713 }
607b4b08 1714 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1715 default:
1716 goto bad_reg;
1717 }
1718 case 1:
1719 if (!arm_feature(env, ARM_FEATURE_V6))
1720 goto bad_reg;
1721 return env->cp15.c0_c1[op2];
1722 case 2:
1723 if (!arm_feature(env, ARM_FEATURE_V6))
1724 goto bad_reg;
1725 return env->cp15.c0_c2[op2];
1726 case 3: case 4: case 5: case 6: case 7:
1727 return 0;
1728 default:
1729 goto bad_reg;
1730 }
1731 case 1:
1732 /* These registers aren't documented on arm11 cores. However
1733 Linux looks at them anyway. */
1734 if (!arm_feature(env, ARM_FEATURE_V6))
1735 goto bad_reg;
1736 if (crm != 0)
1737 goto bad_reg;
a49ea279
PB		 1738 if (!arm_feature(env, ARM_FEATURE_V7))
1739 return 0;
1740
1741 switch (op2) {
1742 case 0:
1743 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1744 case 1:
1745 return env->cp15.c0_clid;
1746 case 7:
1747 return 0;
1748 }
1749 goto bad_reg;
1750 case 2:
1751 if (op2 != 0 || crm != 0)
610c3c8a 1752 goto bad_reg;
a49ea279 1753 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1754 default:
1755 goto bad_reg;
b5ff1b31
FB		 1756 }
1757 case 1: /* System configuration. */
c3d2689d
AZ		 1758 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1759 op2 = 0;
b5ff1b31
FB		 1760 switch (op2) {
1761 case 0: /* Control register. */
1762 return env->cp15.c1_sys;
1763 case 1: /* Auxiliary control register. */
c1713132 1764 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1765 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1766 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1767 goto bad_reg;
1768 switch (ARM_CPUID(env)) {
1769 case ARM_CPUID_ARM1026:
1770 return 1;
1771 case ARM_CPUID_ARM1136:
827df9f3 1772 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1773 return 7;
1774 case ARM_CPUID_ARM11MPCORE:
1775 return 1;
1776 case ARM_CPUID_CORTEXA8:
533d177a 1777 return 2;
10055562
PB		 1778 case ARM_CPUID_CORTEXA9:
1779 return 0;
9ee6e8bb
PB		 1780 default:
1781 goto bad_reg;
1782 }
b5ff1b31 1783 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1784 if (arm_feature(env, ARM_FEATURE_XSCALE))
1785 goto bad_reg;
b5ff1b31
FB		 1786 return env->cp15.c1_coproc;
1787 default:
1788 goto bad_reg;
1789 }
ce819861
PB		 1790 case 2: /* MMU Page table control / MPU cache control. */
1791 if (arm_feature(env, ARM_FEATURE_MPU)) {
1792 switch (op2) {
1793 case 0:
1794 return env->cp15.c2_data;
1795 break;
1796 case 1:
1797 return env->cp15.c2_insn;
1798 break;
1799 default:
1800 goto bad_reg;
1801 }
1802 } else {
9ee6e8bb
PB		 1803 switch (op2) {
1804 case 0:
1805 return env->cp15.c2_base0;
1806 case 1:
1807 return env->cp15.c2_base1;
1808 case 2:
b2fa1797 1809 return env->cp15.c2_control;
9ee6e8bb
PB		 1810 default:
1811 goto bad_reg;
1812 }
1813 }
ce819861 1814 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1815 return env->cp15.c3;
1816 case 4: /* Reserved. */
1817 goto bad_reg;
ce819861 1818 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1819 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1820 op2 = 0;
b5ff1b31
FB		 1821 switch (op2) {
1822 case 0:
ce819861
PB		 1823 if (arm_feature(env, ARM_FEATURE_MPU))
1824 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1825 return env->cp15.c5_data;
1826 case 1:
ce819861
PB		 1827 if (arm_feature(env, ARM_FEATURE_MPU))
1828 return simple_mpu_ap_bits(env->cp15.c5_data);
1829 return env->cp15.c5_insn;
1830 case 2:
1831 if (!arm_feature(env, ARM_FEATURE_MPU))
1832 goto bad_reg;
1833 return env->cp15.c5_data;
1834 case 3:
1835 if (!arm_feature(env, ARM_FEATURE_MPU))
1836 goto bad_reg;
b5ff1b31
FB		 1837 return env->cp15.c5_insn;
1838 default:
1839 goto bad_reg;
1840 }
9ee6e8bb 1841 case 6: /* MMU Fault address. */
ce819861 1842 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1843 if (crm >= 8)
ce819861 1844 goto bad_reg;
9ee6e8bb 1845 return env->cp15.c6_region[crm];
ce819861 1846 } else {
c3d2689d
AZ		 1847 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1848 op2 = 0;
9ee6e8bb
PB		 1849 switch (op2) {
1850 case 0:
1851 return env->cp15.c6_data;
1852 case 1:
1853 if (arm_feature(env, ARM_FEATURE_V6)) {
1854 /* Watchpoint Fault Adrress. */
1855 return 0; /* Not implemented. */
1856 } else {
1857 /* Instruction Fault Adrress. */
1858 /* Arm9 doesn't have an IFAR, but implementing it anyway
1859 shouldn't do any harm. */
1860 return env->cp15.c6_insn;
1861 }
1862 case 2:
1863 if (arm_feature(env, ARM_FEATURE_V6)) {
1864 /* Instruction Fault Adrress. */
1865 return env->cp15.c6_insn;
1866 } else {
1867 goto bad_reg;
1868 }
1869 default:
1870 goto bad_reg;
1871 }
b5ff1b31
FB		 1872 }
1873 case 7: /* Cache control. */
f8bf8606
AL		 1874 if (crm == 4 && op1 == 0 && op2 == 0) {
1875 return env->cp15.c7_par;
1876 }
6fbe23d5
PB		 1877 /* FIXME: Should only clear Z flag if destination is r15. */
1878 env->ZF = 0;
b5ff1b31
FB		 1879 return 0;
1880 case 8: /* MMU TLB control. */
1881 goto bad_reg;
1882 case 9: /* Cache lockdown. */
9ee6e8bb
PB		 1883 switch (op1) {
1884 case 0: /* L1 cache. */
1885 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1886 return 0;
1887 switch (op2) {
1888 case 0:
1889 return env->cp15.c9_data;
1890 case 1:
1891 return env->cp15.c9_insn;
1892 default:
1893 goto bad_reg;
1894 }
1895 case 1: /* L2 cache */
1896 if (crm != 0)
1897 goto bad_reg;
1898 /* L2 Lockdown and Auxiliary control. */
c3d2689d 1899 return 0;
b5ff1b31
FB		 1900 default:
1901 goto bad_reg;
1902 }
1903 case 10: /* MMU TLB lockdown. */
1904 /* ??? TLB lockdown not implemented. */
1905 return 0;
1906 case 11: /* TCM DMA control. */
1907 case 12: /* Reserved. */
1908 goto bad_reg;
1909 case 13: /* Process ID. */
1910 switch (op2) {
1911 case 0:
1912 return env->cp15.c13_fcse;
1913 case 1:
1914 return env->cp15.c13_context;
1915 default:
1916 goto bad_reg;
1917 }
1918 case 14: /* Reserved. */
1919 goto bad_reg;
1920 case 15: /* Implementation specific. */
c1713132 1921 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 1922 if (op2 == 0 && crm == 1)
c1713132
AZ		 1923 return env->cp15.c15_cpar;
1924
1925 goto bad_reg;
1926 }
c3d2689d
AZ		 1927 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1928 switch (crm) {
1929 case 0:
1930 return 0;
1931 case 1: /* Read TI925T configuration. */
1932 return env->cp15.c15_ticonfig;
1933 case 2: /* Read I_max. */
1934 return env->cp15.c15_i_max;
1935 case 3: /* Read I_min. */
1936 return env->cp15.c15_i_min;
1937 case 4: /* Read thread-ID. */
1938 return env->cp15.c15_threadid;
1939 case 8: /* TI925T_status */
1940 return 0;
1941 }
827df9f3
AZ		 1942 /* TODO: Peripheral port remap register:
1943 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1944 * controller base address at $rn & ~0xfff and map size of
1945 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 1946 goto bad_reg;
1947 }
b5ff1b31
FB		 1948 return 0;
1949 }
1950bad_reg:
1951 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1952 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1953 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1954 return 0;
1955}
1956
b0109805 1957void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 1958{
39ea3d4e
PM		 1959 if ((env->uncached_cpsr & CPSR_M) == mode) {
1960 env->regs[13] = val;
1961 } else {
1962 env->banked_r13[bank_number(mode)] = val;
1963 }
9ee6e8bb
PB		 1964}
1965
b0109805 1966uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 1967{
39ea3d4e
PM		 1968 if ((env->uncached_cpsr & CPSR_M) == mode) {
1969 return env->regs[13];
1970 } else {
1971 return env->banked_r13[bank_number(mode)];
1972 }
9ee6e8bb
PB		 1973}
1974
8984bd2e 1975uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 1976{
1977 switch (reg) {
1978 case 0: /* APSR */
1979 return xpsr_read(env) & 0xf8000000;
1980 case 1: /* IAPSR */
1981 return xpsr_read(env) & 0xf80001ff;
1982 case 2: /* EAPSR */
1983 return xpsr_read(env) & 0xff00fc00;
1984 case 3: /* xPSR */
1985 return xpsr_read(env) & 0xff00fdff;
1986 case 5: /* IPSR */
1987 return xpsr_read(env) & 0x000001ff;
1988 case 6: /* EPSR */
1989 return xpsr_read(env) & 0x0700fc00;
1990 case 7: /* IEPSR */
1991 return xpsr_read(env) & 0x0700edff;
1992 case 8: /* MSP */
1993 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1994 case 9: /* PSP */
1995 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1996 case 16: /* PRIMASK */
1997 return (env->uncached_cpsr & CPSR_I) != 0;
1998 case 17: /* FAULTMASK */
1999 return (env->uncached_cpsr & CPSR_F) != 0;
2000 case 18: /* BASEPRI */
2001 case 19: /* BASEPRI_MAX */
2002 return env->v7m.basepri;
2003 case 20: /* CONTROL */
2004 return env->v7m.control;
2005 default:
2006 /* ??? For debugging only. */
2007 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2008 return 0;
2009 }
2010}
2011
8984bd2e 2012void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2013{
2014 switch (reg) {
2015 case 0: /* APSR */
2016 xpsr_write(env, val, 0xf8000000);
2017 break;
2018 case 1: /* IAPSR */
2019 xpsr_write(env, val, 0xf8000000);
2020 break;
2021 case 2: /* EAPSR */
2022 xpsr_write(env, val, 0xfe00fc00);
2023 break;
2024 case 3: /* xPSR */
2025 xpsr_write(env, val, 0xfe00fc00);
2026 break;
2027 case 5: /* IPSR */
2028 /* IPSR bits are readonly. */
2029 break;
2030 case 6: /* EPSR */
2031 xpsr_write(env, val, 0x0600fc00);
2032 break;
2033 case 7: /* IEPSR */
2034 xpsr_write(env, val, 0x0600fc00);
2035 break;
2036 case 8: /* MSP */
2037 if (env->v7m.current_sp)
2038 env->v7m.other_sp = val;
2039 else
2040 env->regs[13] = val;
2041 break;
2042 case 9: /* PSP */
2043 if (env->v7m.current_sp)
2044 env->regs[13] = val;
2045 else
2046 env->v7m.other_sp = val;
2047 break;
2048 case 16: /* PRIMASK */
2049 if (val & 1)
2050 env->uncached_cpsr |= CPSR_I;
2051 else
2052 env->uncached_cpsr &= ~CPSR_I;
2053 break;
2054 case 17: /* FAULTMASK */
2055 if (val & 1)
2056 env->uncached_cpsr |= CPSR_F;
2057 else
2058 env->uncached_cpsr &= ~CPSR_F;
2059 break;
2060 case 18: /* BASEPRI */
2061 env->v7m.basepri = val & 0xff;
2062 break;
2063 case 19: /* BASEPRI_MAX */
2064 val &= 0xff;
2065 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2066 env->v7m.basepri = val;
2067 break;
2068 case 20: /* CONTROL */
2069 env->v7m.control = val & 3;
2070 switch_v7m_sp(env, (val & 2) != 0);
2071 break;
2072 default:
2073 /* ??? For debugging only. */
2074 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2075 return;
2076 }
2077}
2078
c1713132
AZ		 2079void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2080 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2081 void *opaque)
2082{
2083 if (cpnum < 0 || cpnum > 14) {
2084 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2085 return;
2086 }
2087
2088 env->cp[cpnum].cp_read = cp_read;
2089 env->cp[cpnum].cp_write = cp_write;
2090 env->cp[cpnum].opaque = opaque;
2091}
2092
b5ff1b31 2093#endif
6ddbc6e4
PB		 2094
2095/* Note that signed overflow is undefined in C. The following routines are
2096 careful to use unsigned types where modulo arithmetic is required.
2097 Failure to do so _will_ break on newer gcc. */
2098
2099/* Signed saturating arithmetic. */
2100
1654b2d6 2101/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2102static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2103{
2104 uint16_t res;
2105
2106 res = a + b;
2107 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2108 if (a & 0x8000)
2109 res = 0x8000;
2110 else
2111 res = 0x7fff;
2112 }
2113 return res;
2114}
2115
1654b2d6 2116/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2117static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2118{
2119 uint8_t res;
2120
2121 res = a + b;
2122 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2123 if (a & 0x80)
2124 res = 0x80;
2125 else
2126 res = 0x7f;
2127 }
2128 return res;
2129}
2130
1654b2d6 2131/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2132static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2133{
2134 uint16_t res;
2135
2136 res = a - b;
2137 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2138 if (a & 0x8000)
2139 res = 0x8000;
2140 else
2141 res = 0x7fff;
2142 }
2143 return res;
2144}
2145
1654b2d6 2146/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2147static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2148{
2149 uint8_t res;
2150
2151 res = a - b;
2152 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2153 if (a & 0x80)
2154 res = 0x80;
2155 else
2156 res = 0x7f;
2157 }
2158 return res;
2159}
2160
2161#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2162#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2163#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2164#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2165#define PFX q
2166
2167#include "op_addsub.h"
2168
2169/* Unsigned saturating arithmetic. */
460a09c1 2170static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2171{
2172 uint16_t res;
2173 res = a + b;
2174 if (res < a)
2175 res = 0xffff;
2176 return res;
2177}
2178
460a09c1 2179static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2180{
4c4fd3f8 2181 if (a > b)
6ddbc6e4
PB		 2182 return a - b;
2183 else
2184 return 0;
2185}
2186
2187static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2188{
2189 uint8_t res;
2190 res = a + b;
2191 if (res < a)
2192 res = 0xff;
2193 return res;
2194}
2195
2196static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2197{
4c4fd3f8 2198 if (a > b)
6ddbc6e4
PB		 2199 return a - b;
2200 else
2201 return 0;
2202}
2203
2204#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2205#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2206#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2207#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2208#define PFX uq
2209
2210#include "op_addsub.h"
2211
2212/* Signed modulo arithmetic. */
2213#define SARITH16(a, b, n, op) do { \
2214 int32_t sum; \
db6e2e65 2215 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2216 RESULT(sum, n, 16); \
2217 if (sum >= 0) \
2218 ge |= 3 << (n * 2); \
2219 } while(0)
2220
2221#define SARITH8(a, b, n, op) do { \
2222 int32_t sum; \
db6e2e65 2223 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2224 RESULT(sum, n, 8); \
2225 if (sum >= 0) \
2226 ge |= 1 << n; \
2227 } while(0)
2228
2229
2230#define ADD16(a, b, n) SARITH16(a, b, n, +)
2231#define SUB16(a, b, n) SARITH16(a, b, n, -)
2232#define ADD8(a, b, n) SARITH8(a, b, n, +)
2233#define SUB8(a, b, n) SARITH8(a, b, n, -)
2234#define PFX s
2235#define ARITH_GE
2236
2237#include "op_addsub.h"
2238
2239/* Unsigned modulo arithmetic. */
2240#define ADD16(a, b, n) do { \
2241 uint32_t sum; \
2242 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2243 RESULT(sum, n, 16); \
a87aa10b 2244 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2245 ge |= 3 << (n * 2); \
2246 } while(0)
2247
2248#define ADD8(a, b, n) do { \
2249 uint32_t sum; \
2250 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2251 RESULT(sum, n, 8); \
a87aa10b
AZ		 2252 if ((sum >> 8) == 1) \
2253 ge |= 1 << n; \
6ddbc6e4
PB		 2254 } while(0)
2255
2256#define SUB16(a, b, n) do { \
2257 uint32_t sum; \
2258 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2259 RESULT(sum, n, 16); \
2260 if ((sum >> 16) == 0) \
2261 ge |= 3 << (n * 2); \
2262 } while(0)
2263
2264#define SUB8(a, b, n) do { \
2265 uint32_t sum; \
2266 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2267 RESULT(sum, n, 8); \
2268 if ((sum >> 8) == 0) \
a87aa10b 2269 ge |= 1 << n; \
6ddbc6e4
PB		 2270 } while(0)
2271
2272#define PFX u
2273#define ARITH_GE
2274
2275#include "op_addsub.h"
2276
2277/* Halved signed arithmetic. */
2278#define ADD16(a, b, n) \
2279 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2280#define SUB16(a, b, n) \
2281 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2282#define ADD8(a, b, n) \
2283 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2284#define SUB8(a, b, n) \
2285 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2286#define PFX sh
2287
2288#include "op_addsub.h"
2289
2290/* Halved unsigned arithmetic. */
2291#define ADD16(a, b, n) \
2292 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2293#define SUB16(a, b, n) \
2294 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2295#define ADD8(a, b, n) \
2296 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2297#define SUB8(a, b, n) \
2298 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2299#define PFX uh
2300
2301#include "op_addsub.h"
2302
2303static inline uint8_t do_usad(uint8_t a, uint8_t b)
2304{
2305 if (a > b)
2306 return a - b;
2307 else
2308 return b - a;
2309}
2310
2311/* Unsigned sum of absolute byte differences. */
2312uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2313{
2314 uint32_t sum;
2315 sum = do_usad(a, b);
2316 sum += do_usad(a >> 8, b >> 8);
2317 sum += do_usad(a >> 16, b >>16);
2318 sum += do_usad(a >> 24, b >> 24);
2319 return sum;
2320}
2321
2322/* For ARMv6 SEL instruction. */
2323uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2324{
2325 uint32_t mask;
2326
2327 mask = 0;
2328 if (flags & 1)
2329 mask |= 0xff;
2330 if (flags & 2)
2331 mask |= 0xff00;
2332 if (flags & 4)
2333 mask |= 0xff0000;
2334 if (flags & 8)
2335 mask |= 0xff000000;
2336 return (a & mask) | (b & ~mask);
2337}
2338
5e3f878a
PB		 2339uint32_t HELPER(logicq_cc)(uint64_t val)
2340{
2341 return (val >> 32) | (val != 0);
2342}
4373f3ce
PB		 2343
2344/* VFP support. We follow the convention used for VFP instrunctions:
2345 Single precition routines have a "s" suffix, double precision a
2346 "d" suffix. */
2347
2348/* Convert host exception flags to vfp form. */
2349static inline int vfp_exceptbits_from_host(int host_bits)
2350{
2351 int target_bits = 0;
2352
2353 if (host_bits & float_flag_invalid)
2354 target_bits |= 1;
2355 if (host_bits & float_flag_divbyzero)
2356 target_bits |= 2;
2357 if (host_bits & float_flag_overflow)
2358 target_bits |= 4;
36802b6b 2359 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2360 target_bits |= 8;
2361 if (host_bits & float_flag_inexact)
2362 target_bits |= 0x10;
cecd8504
PM		 2363 if (host_bits & float_flag_input_denormal)
2364 target_bits |= 0x80;
4373f3ce
PB		 2365 return target_bits;
2366}
2367
2368uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2369{
2370 int i;
2371 uint32_t fpscr;
2372
2373 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2374 | (env->vfp.vec_len << 16)
2375 | (env->vfp.vec_stride << 20);
2376 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2377 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2378 fpscr |= vfp_exceptbits_from_host(i);
2379 return fpscr;
2380}
2381
01653295
PM		 2382uint32_t vfp_get_fpscr(CPUState *env)
2383{
2384 return HELPER(vfp_get_fpscr)(env);
2385}
2386
4373f3ce
PB		 2387/* Convert vfp exception flags to target form. */
2388static inline int vfp_exceptbits_to_host(int target_bits)
2389{
2390 int host_bits = 0;
2391
2392 if (target_bits & 1)
2393 host_bits |= float_flag_invalid;
2394 if (target_bits & 2)
2395 host_bits |= float_flag_divbyzero;
2396 if (target_bits & 4)
2397 host_bits |= float_flag_overflow;
2398 if (target_bits & 8)
2399 host_bits |= float_flag_underflow;
2400 if (target_bits & 0x10)
2401 host_bits |= float_flag_inexact;
cecd8504
PM		 2402 if (target_bits & 0x80)
2403 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2404 return host_bits;
2405}
2406
2407void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2408{
2409 int i;
2410 uint32_t changed;
2411
2412 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2413 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2414 env->vfp.vec_len = (val >> 16) & 7;
2415 env->vfp.vec_stride = (val >> 20) & 3;
2416
2417 changed ^= val;
2418 if (changed & (3 << 22)) {
2419 i = (val >> 22) & 3;
2420 switch (i) {
2421 case 0:
2422 i = float_round_nearest_even;
2423 break;
2424 case 1:
2425 i = float_round_up;
2426 break;
2427 case 2:
2428 i = float_round_down;
2429 break;
2430 case 3:
2431 i = float_round_to_zero;
2432 break;
2433 }
2434 set_float_rounding_mode(i, &env->vfp.fp_status);
2435 }
cecd8504 2436 if (changed & (1 << 24)) {
fe76d976 2437 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2438 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2439 }
5c7908ed
PB		 2440 if (changed & (1 << 25))
2441 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2442
b12c390b 2443 i = vfp_exceptbits_to_host(val);
4373f3ce 2444 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2445 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2446}
2447
01653295
PM		 2448void vfp_set_fpscr(CPUState *env, uint32_t val)
2449{
2450 HELPER(vfp_set_fpscr)(env, val);
2451}
2452
4373f3ce
PB		 2453#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2454
2455#define VFP_BINOP(name) \
2456float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2457{ \
2458 return float32_ ## name (a, b, &env->vfp.fp_status); \
2459} \
2460float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2461{ \
2462 return float64_ ## name (a, b, &env->vfp.fp_status); \
2463}
2464VFP_BINOP(add)
2465VFP_BINOP(sub)
2466VFP_BINOP(mul)
2467VFP_BINOP(div)
2468#undef VFP_BINOP
2469
2470float32 VFP_HELPER(neg, s)(float32 a)
2471{
2472 return float32_chs(a);
2473}
2474
2475float64 VFP_HELPER(neg, d)(float64 a)
2476{
66230e0d 2477 return float64_chs(a);
4373f3ce
PB		 2478}
2479
2480float32 VFP_HELPER(abs, s)(float32 a)
2481{
2482 return float32_abs(a);
2483}
2484
2485float64 VFP_HELPER(abs, d)(float64 a)
2486{
66230e0d 2487 return float64_abs(a);
4373f3ce
PB		 2488}
2489
2490float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2491{
2492 return float32_sqrt(a, &env->vfp.fp_status);
2493}
2494
2495float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2496{
2497 return float64_sqrt(a, &env->vfp.fp_status);
2498}
2499
2500/* XXX: check quiet/signaling case */
2501#define DO_VFP_cmp(p, type) \
2502void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2503{ \
2504 uint32_t flags; \
2505 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2506 case 0: flags = 0x6; break; \
2507 case -1: flags = 0x8; break; \
2508 case 1: flags = 0x2; break; \
2509 default: case 2: flags = 0x3; break; \
2510 } \
2511 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2512 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2513} \
2514void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2515{ \
2516 uint32_t flags; \
2517 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2518 case 0: flags = 0x6; break; \
2519 case -1: flags = 0x8; break; \
2520 case 1: flags = 0x2; break; \
2521 default: case 2: flags = 0x3; break; \
2522 } \
2523 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2524 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2525}
2526DO_VFP_cmp(s, float32)
2527DO_VFP_cmp(d, float64)
2528#undef DO_VFP_cmp
2529
5500b06c 2530/* Integer to float and float to integer conversions */
4373f3ce 2531
5500b06c
PM		 2532#define CONV_ITOF(name, fsz, sign) \
2533 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2534{ \
2535 float_status *fpst = fpstp; \
2536 return sign##int32_to_##float##fsz(x, fpst); \
4373f3ce
PB		 2537}
2538
5500b06c
PM		 2539#define CONV_FTOI(name, fsz, sign, round) \
2540uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2541{ \
2542 float_status *fpst = fpstp; \
2543 if (float##fsz##_is_any_nan(x)) { \
2544 float_raise(float_flag_invalid, fpst); \
2545 return 0; \
2546 } \
2547 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2548}
2549
5500b06c
PM		 2550#define FLOAT_CONVS(name, p, fsz, sign) \
2551CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2552CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2553CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2554
5500b06c
PM		 2555FLOAT_CONVS(si, s, 32, )
2556FLOAT_CONVS(si, d, 64, )
2557FLOAT_CONVS(ui, s, 32, u)
2558FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2559
5500b06c
PM		 2560#undef CONV_ITOF
2561#undef CONV_FTOI
2562#undef FLOAT_CONVS
4373f3ce
PB		 2563
2564/* floating point conversion */
2565float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2566{
2d627737
PM		 2567 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2568 /* ARM requires that S<->D conversion of any kind of NaN generates
2569 * a quiet NaN by forcing the most significant frac bit to 1.
2570 */
2571 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2572}
2573
2574float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2575{
2d627737
PM		 2576 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2577 /* ARM requires that S<->D conversion of any kind of NaN generates
2578 * a quiet NaN by forcing the most significant frac bit to 1.
2579 */
2580 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2581}
2582
2583/* VFP3 fixed point conversion. */
622465e1 2584#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2585float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2586 void *fpstp) \
4373f3ce 2587{ \
5500b06c 2588 float_status *fpst = fpstp; \
622465e1 2589 float##fsz tmp; \
5500b06c
PM		 2590 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2591 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2592} \
5500b06c
PM		 2593uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2594 void *fpstp) \
4373f3ce 2595{ \
5500b06c 2596 float_status *fpst = fpstp; \
622465e1
PM		 2597 float##fsz tmp; \
2598 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2599 float_raise(float_flag_invalid, fpst); \
622465e1 2600 return 0; \
09d9487f 2601 } \
5500b06c
PM		 2602 tmp = float##fsz##_scalbn(x, shift, fpst); \
2603 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2604}
2605
2606VFP_CONV_FIX(sh, d, 64, int16, )
2607VFP_CONV_FIX(sl, d, 64, int32, )
2608VFP_CONV_FIX(uh, d, 64, uint16, u)
2609VFP_CONV_FIX(ul, d, 64, uint32, u)
2610VFP_CONV_FIX(sh, s, 32, int16, )
2611VFP_CONV_FIX(sl, s, 32, int32, )
2612VFP_CONV_FIX(uh, s, 32, uint16, u)
2613VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2614#undef VFP_CONV_FIX
2615
60011498 2616/* Half precision conversions. */
2d981da7 2617static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2618{
60011498 2619 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2620 float32 r = float16_to_float32(make_float16(a), ieee, s);
2621 if (ieee) {
2622 return float32_maybe_silence_nan(r);
2623 }
2624 return r;
60011498
PB		 2625}
2626
2d981da7 2627static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2628{
60011498 2629 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2630 float16 r = float32_to_float16(a, ieee, s);
2631 if (ieee) {
2632 r = float16_maybe_silence_nan(r);
2633 }
2634 return float16_val(r);
60011498
PB		 2635}
2636
2d981da7
PM		 2637float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2638{
2639 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2640}
2641
2642uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2643{
2644 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2645}
2646
2647float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2648{
2649 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2650}
2651
2652uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2653{
2654 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2655}
2656
dda3ec49 2657#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2658#define float32_three make_float32(0x40400000)
2659#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2660
4373f3ce
PB		 2661float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2662{
dda3ec49
PM		 2663 float_status *s = &env->vfp.standard_fp_status;
2664 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2665 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2666 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2667 float_raise(float_flag_input_denormal, s);
2668 }
dda3ec49
PM		 2669 return float32_two;
2670 }
2671 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2672}
2673
2674float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2675{
71826966 2676 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2677 float32 product;
2678 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2679 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2680 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2681 float_raise(float_flag_input_denormal, s);
2682 }
6aae3df1 2683 return float32_one_point_five;
9ea62f57 2684 }
6aae3df1
PM		 2685 product = float32_mul(a, b, s);
2686 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2687}
2688
8f8e3aa4
PB		 2689/* NEON helpers. */
2690
56bf4fe2
CL		 2691/* Constants 256 and 512 are used in some helpers; we avoid relying on
2692 * int->float conversions at run-time. */
2693#define float64_256 make_float64(0x4070000000000000LL)
2694#define float64_512 make_float64(0x4080000000000000LL)
2695
fe0e4872
CL		 2696/* The algorithm that must be used to calculate the estimate
2697 * is specified by the ARM ARM.
2698 */
2699static float64 recip_estimate(float64 a, CPUState *env)
2700{
1146a817
PM		 2701 /* These calculations mustn't set any fp exception flags,
2702 * so we use a local copy of the fp_status.
2703 */
2704 float_status dummy_status = env->vfp.standard_fp_status;
2705 float_status *s = &dummy_status;
fe0e4872
CL		 2706 /* q = (int)(a * 512.0) */
2707 float64 q = float64_mul(float64_512, a, s);
2708 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2709
2710 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2711 q = int64_to_float64(q_int, s);
2712 q = float64_add(q, float64_half, s);
2713 q = float64_div(q, float64_512, s);
2714 q = float64_div(float64_one, q, s);
2715
2716 /* s = (int)(256.0 * r + 0.5) */
2717 q = float64_mul(q, float64_256, s);
2718 q = float64_add(q, float64_half, s);
2719 q_int = float64_to_int64_round_to_zero(q, s);
2720
2721 /* return (double)s / 256.0 */
2722 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2723}
2724
4373f3ce
PB		 2725float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2726{
fe0e4872
CL		 2727 float_status *s = &env->vfp.standard_fp_status;
2728 float64 f64;
2729 uint32_t val32 = float32_val(a);
2730
2731 int result_exp;
2732 int a_exp = (val32 & 0x7f800000) >> 23;
2733 int sign = val32 & 0x80000000;
2734
2735 if (float32_is_any_nan(a)) {
2736 if (float32_is_signaling_nan(a)) {
2737 float_raise(float_flag_invalid, s);
2738 }
2739 return float32_default_nan;
2740 } else if (float32_is_infinity(a)) {
2741 return float32_set_sign(float32_zero, float32_is_neg(a));
2742 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2743 if (!float32_is_zero(a)) {
2744 float_raise(float_flag_input_denormal, s);
2745 }
fe0e4872
CL		 2746 float_raise(float_flag_divbyzero, s);
2747 return float32_set_sign(float32_infinity, float32_is_neg(a));
2748 } else if (a_exp >= 253) {
2749 float_raise(float_flag_underflow, s);
2750 return float32_set_sign(float32_zero, float32_is_neg(a));
2751 }
2752
2753 f64 = make_float64((0x3feULL << 52)
2754 | ((int64_t)(val32 & 0x7fffff) << 29));
2755
2756 result_exp = 253 - a_exp;
2757
2758 f64 = recip_estimate(f64, env);
2759
2760 val32 = sign
2761 | ((result_exp & 0xff) << 23)
2762 | ((float64_val(f64) >> 29) & 0x7fffff);
2763 return make_float32(val32);
4373f3ce
PB		 2764}
2765
e07be5d2
CL		 2766/* The algorithm that must be used to calculate the estimate
2767 * is specified by the ARM ARM.
2768 */
2769static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2770{
1146a817
PM		 2771 /* These calculations mustn't set any fp exception flags,
2772 * so we use a local copy of the fp_status.
2773 */
2774 float_status dummy_status = env->vfp.standard_fp_status;
2775 float_status *s = &dummy_status;
e07be5d2
CL		 2776 float64 q;
2777 int64_t q_int;
2778
2779 if (float64_lt(a, float64_half, s)) {
2780 /* range 0.25 <= a < 0.5 */
2781
2782 /* a in units of 1/512 rounded down */
2783 /* q0 = (int)(a * 512.0); */
2784 q = float64_mul(float64_512, a, s);
2785 q_int = float64_to_int64_round_to_zero(q, s);
2786
2787 /* reciprocal root r */
2788 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2789 q = int64_to_float64(q_int, s);
2790 q = float64_add(q, float64_half, s);
2791 q = float64_div(q, float64_512, s);
2792 q = float64_sqrt(q, s);
2793 q = float64_div(float64_one, q, s);
2794 } else {
2795 /* range 0.5 <= a < 1.0 */
2796
2797 /* a in units of 1/256 rounded down */
2798 /* q1 = (int)(a * 256.0); */
2799 q = float64_mul(float64_256, a, s);
2800 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2801
2802 /* reciprocal root r */
2803 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2804 q = int64_to_float64(q_int, s);
2805 q = float64_add(q, float64_half, s);
2806 q = float64_div(q, float64_256, s);
2807 q = float64_sqrt(q, s);
2808 q = float64_div(float64_one, q, s);
2809 }
2810 /* r in units of 1/256 rounded to nearest */
2811 /* s = (int)(256.0 * r + 0.5); */
2812
2813 q = float64_mul(q, float64_256,s );
2814 q = float64_add(q, float64_half, s);
2815 q_int = float64_to_int64_round_to_zero(q, s);
2816
2817 /* return (double)s / 256.0;*/
2818 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2819}
2820
4373f3ce
PB		 2821float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2822{
e07be5d2
CL		 2823 float_status *s = &env->vfp.standard_fp_status;
2824 int result_exp;
2825 float64 f64;
2826 uint32_t val;
2827 uint64_t val64;
2828
2829 val = float32_val(a);
2830
2831 if (float32_is_any_nan(a)) {
2832 if (float32_is_signaling_nan(a)) {
2833 float_raise(float_flag_invalid, s);
2834 }
2835 return float32_default_nan;
2836 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2837 if (!float32_is_zero(a)) {
2838 float_raise(float_flag_input_denormal, s);
2839 }
e07be5d2
CL		 2840 float_raise(float_flag_divbyzero, s);
2841 return float32_set_sign(float32_infinity, float32_is_neg(a));
2842 } else if (float32_is_neg(a)) {
2843 float_raise(float_flag_invalid, s);
2844 return float32_default_nan;
2845 } else if (float32_is_infinity(a)) {
2846 return float32_zero;
2847 }
2848
2849 /* Normalize to a double-precision value between 0.25 and 1.0,
2850 * preserving the parity of the exponent. */
2851 if ((val & 0x800000) == 0) {
2852 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2853 | (0x3feULL << 52)
2854 | ((uint64_t)(val & 0x7fffff) << 29));
2855 } else {
2856 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2857 | (0x3fdULL << 52)
2858 | ((uint64_t)(val & 0x7fffff) << 29));
2859 }
2860
2861 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
2862
2863 f64 = recip_sqrt_estimate(f64, env);
2864
2865 val64 = float64_val(f64);
2866
2867 val = ((val64 >> 63) & 0x80000000)
2868 | ((result_exp & 0xff) << 23)
2869 | ((val64 >> 29) & 0x7fffff);
2870 return make_float32(val);
4373f3ce
PB		 2871}
2872
2873uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2874{
fe0e4872
CL		 2875 float64 f64;
2876
2877 if ((a & 0x80000000) == 0) {
2878 return 0xffffffff;
2879 }
2880
2881 f64 = make_float64((0x3feULL << 52)
2882 | ((int64_t)(a & 0x7fffffff) << 21));
2883
2884 f64 = recip_estimate (f64, env);
2885
2886 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 2887}
2888
2889uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2890{
e07be5d2
CL		 2891 float64 f64;
2892
2893 if ((a & 0xc0000000) == 0) {
2894 return 0xffffffff;
2895 }
2896
2897 if (a & 0x80000000) {
2898 f64 = make_float64((0x3feULL << 52)
2899 | ((uint64_t)(a & 0x7fffffff) << 21));
2900 } else { /* bits 31-30 == '01' */
2901 f64 = make_float64((0x3fdULL << 52)
2902 | ((uint64_t)(a & 0x3fffffff) << 22));
2903 }
2904
2905 f64 = recip_sqrt_estimate(f64, env);
2906
2907 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 2908}
fe1479c3
PB		 2909
2910void HELPER(set_teecr)(CPUState *env, uint32_t val)
2911{
2912 val &= 1;
2913 if (env->teecr != val) {
2914 env->teecr = val;
2915 tb_flush(env);
2916 }
2917}
Qemu copy for testing