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target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
b26eefb6 8#include "helpers.h"
ca10f867 9#include "qemu-common.h"
7bbcb0af 10#include "host-utils.h"
4f78c9ad 11#if !defined(CONFIG_USER_ONLY)
983fe826 12#include "hw/loader.h"
4f78c9ad 13#endif
9ee6e8bb 14
10055562
PB		 15static uint32_t cortexa9_cp15_c0_c1[8] =
16{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
17
18static uint32_t cortexa9_cp15_c0_c2[8] =
19{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
20
9ee6e8bb
PB		 21static uint32_t cortexa8_cp15_c0_c1[8] =
22{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
23
24static uint32_t cortexa8_cp15_c0_c2[8] =
25{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
26
27static uint32_t mpcore_cp15_c0_c1[8] =
28{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
29
30static uint32_t mpcore_cp15_c0_c2[8] =
31{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
32
33static uint32_t arm1136_cp15_c0_c1[8] =
34{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
35
36static uint32_t arm1136_cp15_c0_c2[8] =
37{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 38
aaed909a
FB		 39static uint32_t cpu_arm_find_by_name(const char *name);
40
f3d6b95e
PB		 41static inline void set_feature(CPUARMState *env, int feature)
42{
43 env->features |= 1u << feature;
44}
45
46static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
47{
48 env->cp15.c0_cpuid = id;
49 switch (id) {
50 case ARM_CPUID_ARM926:
be5e7a76
DES		 51 set_feature(env, ARM_FEATURE_V4T);
52 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 53 set_feature(env, ARM_FEATURE_VFP);
54 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 55 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 56 env->cp15.c1_sys = 0x00090078;
f3d6b95e 57 break;
ce819861 58 case ARM_CPUID_ARM946:
be5e7a76
DES		 59 set_feature(env, ARM_FEATURE_V4T);
60 set_feature(env, ARM_FEATURE_V5);
ce819861
PB		 61 set_feature(env, ARM_FEATURE_MPU);
62 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 63 env->cp15.c1_sys = 0x00000078;
ce819861 64 break;
f3d6b95e 65 case ARM_CPUID_ARM1026:
be5e7a76
DES		 66 set_feature(env, ARM_FEATURE_V4T);
67 set_feature(env, ARM_FEATURE_V5);
f3d6b95e
PB		 68 set_feature(env, ARM_FEATURE_VFP);
69 set_feature(env, ARM_FEATURE_AUXCR);
70 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 71 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 72 env->cp15.c1_sys = 0x00090078;
c1713132 73 break;
827df9f3 74 case ARM_CPUID_ARM1136_R2:
9ee6e8bb 75 case ARM_CPUID_ARM1136:
be5e7a76
DES		 76 set_feature(env, ARM_FEATURE_V4T);
77 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 78 set_feature(env, ARM_FEATURE_V6);
79 set_feature(env, ARM_FEATURE_VFP);
80 set_feature(env, ARM_FEATURE_AUXCR);
81 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
82 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
83 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
84 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 85 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb 86 env->cp15.c0_cachetype = 0x1dd20d2;
16440c5f 87 env->cp15.c1_sys = 0x00050078;
9ee6e8bb
PB		 88 break;
89 case ARM_CPUID_ARM11MPCORE:
be5e7a76
DES		 90 set_feature(env, ARM_FEATURE_V4T);
91 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 92 set_feature(env, ARM_FEATURE_V6);
93 set_feature(env, ARM_FEATURE_V6K);
94 set_feature(env, ARM_FEATURE_VFP);
95 set_feature(env, ARM_FEATURE_AUXCR);
96 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
97 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
98 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
99 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 100 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 101 env->cp15.c0_cachetype = 0x1dd20d2;
102 break;
103 case ARM_CPUID_CORTEXA8:
be5e7a76
DES		 104 set_feature(env, ARM_FEATURE_V4T);
105 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 106 set_feature(env, ARM_FEATURE_V6);
107 set_feature(env, ARM_FEATURE_V6K);
108 set_feature(env, ARM_FEATURE_V7);
109 set_feature(env, ARM_FEATURE_AUXCR);
110 set_feature(env, ARM_FEATURE_THUMB2);
111 set_feature(env, ARM_FEATURE_VFP);
112 set_feature(env, ARM_FEATURE_VFP3);
113 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 114 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 115 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
116 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
117 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
118 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 119 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 120 env->cp15.c0_cachetype = 0x82048004;
121 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
122 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
123 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
124 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9c486ad6 125 env->cp15.c1_sys = 0x00c50078;
9ee6e8bb 126 break;
10055562 127 case ARM_CPUID_CORTEXA9:
be5e7a76
DES		 128 set_feature(env, ARM_FEATURE_V4T);
129 set_feature(env, ARM_FEATURE_V5);
10055562
PB		 130 set_feature(env, ARM_FEATURE_V6);
131 set_feature(env, ARM_FEATURE_V6K);
132 set_feature(env, ARM_FEATURE_V7);
133 set_feature(env, ARM_FEATURE_AUXCR);
134 set_feature(env, ARM_FEATURE_THUMB2);
135 set_feature(env, ARM_FEATURE_VFP);
136 set_feature(env, ARM_FEATURE_VFP3);
137 set_feature(env, ARM_FEATURE_VFP_FP16);
138 set_feature(env, ARM_FEATURE_NEON);
139 set_feature(env, ARM_FEATURE_THUMB2EE);
e1bbf446
PM		 140 /* Note that A9 supports the MP extensions even for
141 * A9UP and single-core A9MP (which are both different
142 * and valid configurations; we don't model A9UP).
143 */
144 set_feature(env, ARM_FEATURE_V7MP);
10055562
PB		 145 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
146 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
147 env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
148 memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
149 memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
150 env->cp15.c0_cachetype = 0x80038003;
151 env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
152 env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
153 env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
16440c5f 154 env->cp15.c1_sys = 0x00c50078;
10055562 155 break;
9ee6e8bb 156 case ARM_CPUID_CORTEXM3:
be5e7a76
DES		 157 set_feature(env, ARM_FEATURE_V4T);
158 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 159 set_feature(env, ARM_FEATURE_V6);
160 set_feature(env, ARM_FEATURE_THUMB2);
161 set_feature(env, ARM_FEATURE_V7);
162 set_feature(env, ARM_FEATURE_M);
163 set_feature(env, ARM_FEATURE_DIV);
164 break;
165 case ARM_CPUID_ANY: /* For userspace emulation. */
be5e7a76
DES		 166 set_feature(env, ARM_FEATURE_V4T);
167 set_feature(env, ARM_FEATURE_V5);
9ee6e8bb
PB		 168 set_feature(env, ARM_FEATURE_V6);
169 set_feature(env, ARM_FEATURE_V6K);
170 set_feature(env, ARM_FEATURE_V7);
171 set_feature(env, ARM_FEATURE_THUMB2);
172 set_feature(env, ARM_FEATURE_VFP);
173 set_feature(env, ARM_FEATURE_VFP3);
60011498 174 set_feature(env, ARM_FEATURE_VFP_FP16);
9ee6e8bb 175 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 176 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb 177 set_feature(env, ARM_FEATURE_DIV);
e1bbf446 178 set_feature(env, ARM_FEATURE_V7MP);
9ee6e8bb 179 break;
c3d2689d
AZ		 180 case ARM_CPUID_TI915T:
181 case ARM_CPUID_TI925T:
be5e7a76 182 set_feature(env, ARM_FEATURE_V4T);
c3d2689d
AZ		 183 set_feature(env, ARM_FEATURE_OMAPCP);
184 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
185 env->cp15.c0_cachetype = 0x5109149;
186 env->cp15.c1_sys = 0x00000070;
187 env->cp15.c15_i_max = 0x000;
188 env->cp15.c15_i_min = 0xff0;
189 break;
c1713132
AZ		 190 case ARM_CPUID_PXA250:
191 case ARM_CPUID_PXA255:
192 case ARM_CPUID_PXA260:
193 case ARM_CPUID_PXA261:
194 case ARM_CPUID_PXA262:
be5e7a76
DES		 195 set_feature(env, ARM_FEATURE_V4T);
196 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 197 set_feature(env, ARM_FEATURE_XSCALE);
198 /* JTAG_ID is ((id << 28) | 0x09265013) */
199 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 200 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 201 break;
202 case ARM_CPUID_PXA270_A0:
203 case ARM_CPUID_PXA270_A1:
204 case ARM_CPUID_PXA270_B0:
205 case ARM_CPUID_PXA270_B1:
206 case ARM_CPUID_PXA270_C0:
207 case ARM_CPUID_PXA270_C5:
be5e7a76
DES		 208 set_feature(env, ARM_FEATURE_V4T);
209 set_feature(env, ARM_FEATURE_V5);
c1713132
AZ		 210 set_feature(env, ARM_FEATURE_XSCALE);
211 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 212 set_feature(env, ARM_FEATURE_IWMMXT);
213 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 214 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 215 env->cp15.c1_sys = 0x00000078;
f3d6b95e
PB		 216 break;
217 default:
218 cpu_abort(env, "Bad CPU ID: %x\n", id);
219 break;
220 }
221}
222
40f137e1
PB		 223void cpu_reset(CPUARMState *env)
224{
f3d6b95e 225 uint32_t id;
eca1bdf4
AL		 226
227 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
228 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
229 log_cpu_state(env, 0);
230 }
231
f3d6b95e
PB		 232 id = env->cp15.c0_cpuid;
233 memset(env, 0, offsetof(CPUARMState, breakpoints));
234 if (id)
235 cpu_reset_model_id(env, id);
40f137e1
PB		 236#if defined (CONFIG_USER_ONLY)
237 env->uncached_cpsr = ARM_CPU_MODE_USR;
3a807dec 238 /* For user mode we must enable access to coprocessors */
40f137e1 239 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
3a807dec
PM		 240 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
241 env->cp15.c15_cpar = 3;
242 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
243 env->cp15.c15_cpar = 1;
244 }
40f137e1
PB		 245#else
246 /* SVC mode with interrupts disabled. */
247 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb 248 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
983fe826
PB		 249 clear at reset. Initial SP and PC are loaded from ROM. */
250 if (IS_M(env)) {
251 uint32_t pc;
252 uint8_t *rom;
9ee6e8bb 253 env->uncached_cpsr &= ~CPSR_I;
983fe826
PB		 254 rom = rom_ptr(0);
255 if (rom) {
256 /* We should really use ldl_phys here, in case the guest
257 modified flash and reset itself. However images
258 loaded via -kenrel have not been copied yet, so load the
259 values directly from there. */
260 env->regs[13] = ldl_p(rom);
261 pc = ldl_p(rom + 4);
262 env->thumb = pc & 1;
263 env->regs[15] = pc & ~1;
264 }
265 }
40f137e1 266 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 267 env->cp15.c2_base_mask = 0xffffc000u;
40f137e1 268#endif
3a492f3a
PM		 269 set_flush_to_zero(1, &env->vfp.standard_fp_status);
270 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
271 set_default_nan_mode(1, &env->vfp.standard_fp_status);
f3d6b95e 272 tlb_flush(env, 1);
40f137e1
PB		 273}
274
56aebc89
PB		 275static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
276{
277 int nregs;
278
279 /* VFP data registers are always little-endian. */
280 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
281 if (reg < nregs) {
282 stfq_le_p(buf, env->vfp.regs[reg]);
283 return 8;
284 }
285 if (arm_feature(env, ARM_FEATURE_NEON)) {
286 /* Aliases for Q regs. */
287 nregs += 16;
288 if (reg < nregs) {
289 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
290 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
291 return 16;
292 }
293 }
294 switch (reg - nregs) {
295 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
296 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
297 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
298 }
299 return 0;
300}
301
302static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
303{
304 int nregs;
305
306 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
307 if (reg < nregs) {
308 env->vfp.regs[reg] = ldfq_le_p(buf);
309 return 8;
310 }
311 if (arm_feature(env, ARM_FEATURE_NEON)) {
312 nregs += 16;
313 if (reg < nregs) {
314 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
315 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
316 return 16;
317 }
318 }
319 switch (reg - nregs) {
320 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
321 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 322 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 323 }
324 return 0;
325}
326
aaed909a 327CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 328{
329 CPUARMState *env;
aaed909a 330 uint32_t id;
b26eefb6 331 static int inited = 0;
40f137e1 332
aaed909a
FB		 333 id = cpu_arm_find_by_name(cpu_model);
334 if (id == 0)
335 return NULL;
40f137e1 336 env = qemu_mallocz(sizeof(CPUARMState));
40f137e1 337 cpu_exec_init(env);
b26eefb6
PB		 338 if (!inited) {
339 inited = 1;
340 arm_translate_init();
341 }
342
01ba9816 343 env->cpu_model_str = cpu_model;
aaed909a 344 env->cp15.c0_cpuid = id;
40f137e1 345 cpu_reset(env);
56aebc89
PB		 346 if (arm_feature(env, ARM_FEATURE_NEON)) {
347 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
348 51, "arm-neon.xml", 0);
349 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
350 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
351 35, "arm-vfp3.xml", 0);
352 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
353 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
354 19, "arm-vfp.xml", 0);
355 }
0bf46a40 356 qemu_init_vcpu(env);
40f137e1
PB		 357 return env;
358}
359
3371d272
PB		 360struct arm_cpu_t {
361 uint32_t id;
362 const char *name;
363};
364
365static const struct arm_cpu_t arm_cpu_names[] = {
366 { ARM_CPUID_ARM926, "arm926"},
ce819861 367 { ARM_CPUID_ARM946, "arm946"},
3371d272 368 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 369 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 370 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 371 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
372 { ARM_CPUID_CORTEXM3, "cortex-m3"},
373 { ARM_CPUID_CORTEXA8, "cortex-a8"},
10055562 374 { ARM_CPUID_CORTEXA9, "cortex-a9"},
c3d2689d 375 { ARM_CPUID_TI925T, "ti925t" },
c1713132
AZ		 376 { ARM_CPUID_PXA250, "pxa250" },
377 { ARM_CPUID_PXA255, "pxa255" },
378 { ARM_CPUID_PXA260, "pxa260" },
379 { ARM_CPUID_PXA261, "pxa261" },
380 { ARM_CPUID_PXA262, "pxa262" },
381 { ARM_CPUID_PXA270, "pxa270" },
382 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
383 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
384 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
385 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
386 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
387 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 388 { ARM_CPUID_ANY, "any"},
3371d272
PB		 389 { 0, NULL}
390};
391
9a78eead 392void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5adb4839
PB		 393{
394 int i;
395
c732abe2 396 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 397 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 398 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 399 }
400}
401
aaed909a
FB		 402/* return 0 if not found */
403static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 404{
3371d272
PB		 405 int i;
406 uint32_t id;
407
408 id = 0;
3371d272
PB		 409 for (i = 0; arm_cpu_names[i].name; i++) {
410 if (strcmp(name, arm_cpu_names[i].name) == 0) {
411 id = arm_cpu_names[i].id;
412 break;
413 }
414 }
aaed909a 415 return id;
40f137e1
PB		 416}
417
418void cpu_arm_close(CPUARMState *env)
419{
420 free(env);
421}
422
2f4a40e5
AZ		 423uint32_t cpsr_read(CPUARMState *env)
424{
425 int ZF;
6fbe23d5
PB		 426 ZF = (env->ZF == 0);
427 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 428 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
429 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
430 | ((env->condexec_bits & 0xfc) << 8)
431 | (env->GE << 16);
432}
433
434void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
435{
2f4a40e5 436 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 437 env->ZF = (~val) & CPSR_Z;
438 env->NF = val;
2f4a40e5
AZ		 439 env->CF = (val >> 29) & 1;
440 env->VF = (val << 3) & 0x80000000;
441 }
442 if (mask & CPSR_Q)
443 env->QF = ((val & CPSR_Q) != 0);
444 if (mask & CPSR_T)
445 env->thumb = ((val & CPSR_T) != 0);
446 if (mask & CPSR_IT_0_1) {
447 env->condexec_bits &= ~3;
448 env->condexec_bits |= (val >> 25) & 3;
449 }
450 if (mask & CPSR_IT_2_7) {
451 env->condexec_bits &= 3;
452 env->condexec_bits |= (val >> 8) & 0xfc;
453 }
454 if (mask & CPSR_GE) {
455 env->GE = (val >> 16) & 0xf;
456 }
457
458 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
459 switch_mode(env, val & CPSR_M);
460 }
461 mask &= ~CACHED_CPSR_BITS;
462 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
463}
464
b26eefb6
PB		 465/* Sign/zero extend */
466uint32_t HELPER(sxtb16)(uint32_t x)
467{
468 uint32_t res;
469 res = (uint16_t)(int8_t)x;
470 res |= (uint32_t)(int8_t)(x >> 16) << 16;
471 return res;
472}
473
474uint32_t HELPER(uxtb16)(uint32_t x)
475{
476 uint32_t res;
477 res = (uint16_t)(uint8_t)x;
478 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
479 return res;
480}
481
f51bbbfe
PB		 482uint32_t HELPER(clz)(uint32_t x)
483{
7bbcb0af 484 return clz32(x);
f51bbbfe
PB		 485}
486
3670669c
PB		 487int32_t HELPER(sdiv)(int32_t num, int32_t den)
488{
489 if (den == 0)
490 return 0;
686eeb93
AJ		 491 if (num == INT_MIN && den == -1)
492 return INT_MIN;
3670669c
PB		 493 return num / den;
494}
495
496uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
497{
498 if (den == 0)
499 return 0;
500 return num / den;
501}
502
503uint32_t HELPER(rbit)(uint32_t x)
504{
505 x = ((x & 0xff000000) >> 24)
506 | ((x & 0x00ff0000) >> 8)
507 | ((x & 0x0000ff00) << 8)
508 | ((x & 0x000000ff) << 24);
509 x = ((x & 0xf0f0f0f0) >> 4)
510 | ((x & 0x0f0f0f0f) << 4);
511 x = ((x & 0x88888888) >> 3)
512 | ((x & 0x44444444) >> 1)
513 | ((x & 0x22222222) << 1)
514 | ((x & 0x11111111) << 3);
515 return x;
516}
517
ad69471c
PB		 518uint32_t HELPER(abs)(uint32_t x)
519{
520 return ((int32_t)x < 0) ? -x : x;
521}
522
5fafdf24 523#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 524
525void do_interrupt (CPUState *env)
526{
527 env->exception_index = -1;
528}
529
530int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 531 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 532{
533 if (rw == 2) {
534 env->exception_index = EXCP_PREFETCH_ABORT;
535 env->cp15.c6_insn = address;
536 } else {
537 env->exception_index = EXCP_DATA_ABORT;
538 env->cp15.c6_data = address;
539 }
540 return 1;
541}
542
b5ff1b31 543/* These should probably raise undefined insn exceptions. */
8984bd2e 544void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 545{
546 int op1 = (insn >> 8) & 0xf;
547 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
548 return;
549}
550
8984bd2e 551uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 552{
553 int op1 = (insn >> 8) & 0xf;
554 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
555 return 0;
556}
557
8984bd2e 558void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 559{
560 cpu_abort(env, "cp15 insn %08x\n", insn);
561}
562
8984bd2e 563uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 564{
565 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 566}
567
9ee6e8bb 568/* These should probably raise undefined insn exceptions. */
8984bd2e 569void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 570{
571 cpu_abort(env, "v7m_mrs %d\n", reg);
572}
573
8984bd2e 574uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 575{
576 cpu_abort(env, "v7m_mrs %d\n", reg);
577 return 0;
578}
579
b5ff1b31
FB		 580void switch_mode(CPUState *env, int mode)
581{
582 if (mode != ARM_CPU_MODE_USR)
583 cpu_abort(env, "Tried to switch out of user mode\n");
584}
585
b0109805 586void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 587{
588 cpu_abort(env, "banked r13 write\n");
589}
590
b0109805 591uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 592{
593 cpu_abort(env, "banked r13 read\n");
594 return 0;
595}
596
b5ff1b31
FB		 597#else
598
8e71621f
PB		 599extern int semihosting_enabled;
600
b5ff1b31
FB		 601/* Map CPU modes onto saved register banks. */
602static inline int bank_number (int mode)
603{
604 switch (mode) {
605 case ARM_CPU_MODE_USR:
606 case ARM_CPU_MODE_SYS:
607 return 0;
608 case ARM_CPU_MODE_SVC:
609 return 1;
610 case ARM_CPU_MODE_ABT:
611 return 2;
612 case ARM_CPU_MODE_UND:
613 return 3;
614 case ARM_CPU_MODE_IRQ:
615 return 4;
616 case ARM_CPU_MODE_FIQ:
617 return 5;
618 }
619 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
620 return -1;
621}
622
623void switch_mode(CPUState *env, int mode)
624{
625 int old_mode;
626 int i;
627
628 old_mode = env->uncached_cpsr & CPSR_M;
629 if (mode == old_mode)
630 return;
631
632 if (old_mode == ARM_CPU_MODE_FIQ) {
633 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 634 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 635 } else if (mode == ARM_CPU_MODE_FIQ) {
636 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 637 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 638 }
639
640 i = bank_number(old_mode);
641 env->banked_r13[i] = env->regs[13];
642 env->banked_r14[i] = env->regs[14];
643 env->banked_spsr[i] = env->spsr;
644
645 i = bank_number(mode);
646 env->regs[13] = env->banked_r13[i];
647 env->regs[14] = env->banked_r14[i];
648 env->spsr = env->banked_spsr[i];
649}
650
9ee6e8bb
PB		 651static void v7m_push(CPUARMState *env, uint32_t val)
652{
653 env->regs[13] -= 4;
654 stl_phys(env->regs[13], val);
655}
656
657static uint32_t v7m_pop(CPUARMState *env)
658{
659 uint32_t val;
660 val = ldl_phys(env->regs[13]);
661 env->regs[13] += 4;
662 return val;
663}
664
665/* Switch to V7M main or process stack pointer. */
666static void switch_v7m_sp(CPUARMState *env, int process)
667{
668 uint32_t tmp;
669 if (env->v7m.current_sp != process) {
670 tmp = env->v7m.other_sp;
671 env->v7m.other_sp = env->regs[13];
672 env->regs[13] = tmp;
673 env->v7m.current_sp = process;
674 }
675}
676
677static void do_v7m_exception_exit(CPUARMState *env)
678{
679 uint32_t type;
680 uint32_t xpsr;
681
682 type = env->regs[15];
683 if (env->v7m.exception != 0)
983fe826 684 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 685
686 /* Switch to the target stack. */
687 switch_v7m_sp(env, (type & 4) != 0);
688 /* Pop registers. */
689 env->regs[0] = v7m_pop(env);
690 env->regs[1] = v7m_pop(env);
691 env->regs[2] = v7m_pop(env);
692 env->regs[3] = v7m_pop(env);
693 env->regs[12] = v7m_pop(env);
694 env->regs[14] = v7m_pop(env);
695 env->regs[15] = v7m_pop(env);
696 xpsr = v7m_pop(env);
697 xpsr_write(env, xpsr, 0xfffffdff);
698 /* Undo stack alignment. */
699 if (xpsr & 0x200)
700 env->regs[13] |= 4;
701 /* ??? The exception return type specifies Thread/Handler mode. However
702 this is also implied by the xPSR value. Not sure what to do
703 if there is a mismatch. */
704 /* ??? Likewise for mismatches between the CONTROL register and the stack
705 pointer. */
706}
707
2b3ea315 708static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 709{
710 uint32_t xpsr = xpsr_read(env);
711 uint32_t lr;
712 uint32_t addr;
713
714 lr = 0xfffffff1;
715 if (env->v7m.current_sp)
716 lr |= 4;
717 if (env->v7m.exception == 0)
718 lr |= 8;
719
720 /* For exceptions we just mark as pending on the NVIC, and let that
721 handle it. */
722 /* TODO: Need to escalate if the current priority is higher than the
723 one we're raising. */
724 switch (env->exception_index) {
725 case EXCP_UDEF:
983fe826 726 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 727 return;
728 case EXCP_SWI:
729 env->regs[15] += 2;
983fe826 730 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 731 return;
732 case EXCP_PREFETCH_ABORT:
733 case EXCP_DATA_ABORT:
983fe826 734 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 735 return;
736 case EXCP_BKPT:
2ad207d4
PB		 737 if (semihosting_enabled) {
738 int nr;
739 nr = lduw_code(env->regs[15]) & 0xff;
740 if (nr == 0xab) {
741 env->regs[15] += 2;
742 env->regs[0] = do_arm_semihosting(env);
743 return;
744 }
745 }
983fe826 746 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 747 return;
748 case EXCP_IRQ:
983fe826 749 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 750 break;
751 case EXCP_EXCEPTION_EXIT:
752 do_v7m_exception_exit(env);
753 return;
754 default:
755 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
756 return; /* Never happens. Keep compiler happy. */
757 }
758
759 /* Align stack pointer. */
760 /* ??? Should only do this if Configuration Control Register
761 STACKALIGN bit is set. */
762 if (env->regs[13] & 4) {
ab19b0ec 763 env->regs[13] -= 4;
9ee6e8bb
PB		 764 xpsr |= 0x200;
765 }
6c95676b 766 /* Switch to the handler mode. */
9ee6e8bb
PB		 767 v7m_push(env, xpsr);
768 v7m_push(env, env->regs[15]);
769 v7m_push(env, env->regs[14]);
770 v7m_push(env, env->regs[12]);
771 v7m_push(env, env->regs[3]);
772 v7m_push(env, env->regs[2]);
773 v7m_push(env, env->regs[1]);
774 v7m_push(env, env->regs[0]);
775 switch_v7m_sp(env, 0);
776 env->uncached_cpsr &= ~CPSR_IT;
777 env->regs[14] = lr;
778 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
779 env->regs[15] = addr & 0xfffffffe;
780 env->thumb = addr & 1;
781}
782
b5ff1b31
FB		 783/* Handle a CPU exception. */
784void do_interrupt(CPUARMState *env)
785{
786 uint32_t addr;
787 uint32_t mask;
788 int new_mode;
789 uint32_t offset;
790
9ee6e8bb
PB		 791 if (IS_M(env)) {
792 do_interrupt_v7m(env);
793 return;
794 }
b5ff1b31
FB		 795 /* TODO: Vectored interrupt controller. */
796 switch (env->exception_index) {
797 case EXCP_UDEF:
798 new_mode = ARM_CPU_MODE_UND;
799 addr = 0x04;
800 mask = CPSR_I;
801 if (env->thumb)
802 offset = 2;
803 else
804 offset = 4;
805 break;
806 case EXCP_SWI:
8e71621f
PB		 807 if (semihosting_enabled) {
808 /* Check for semihosting interrupt. */
809 if (env->thumb) {
810 mask = lduw_code(env->regs[15] - 2) & 0xff;
811 } else {
812 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
813 }
814 /* Only intercept calls from privileged modes, to provide some
815 semblance of security. */
816 if (((mask == 0x123456 && !env->thumb)
817 || (mask == 0xab && env->thumb))
818 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
819 env->regs[0] = do_arm_semihosting(env);
820 return;
821 }
822 }
b5ff1b31
FB		 823 new_mode = ARM_CPU_MODE_SVC;
824 addr = 0x08;
825 mask = CPSR_I;
601d70b9 826 /* The PC already points to the next instruction. */
b5ff1b31
FB		 827 offset = 0;
828 break;
06c949e6 829 case EXCP_BKPT:
9ee6e8bb 830 /* See if this is a semihosting syscall. */
2ad207d4 831 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 832 mask = lduw_code(env->regs[15]) & 0xff;
833 if (mask == 0xab
834 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
835 env->regs[15] += 2;
836 env->regs[0] = do_arm_semihosting(env);
837 return;
838 }
839 }
840 /* Fall through to prefetch abort. */
841 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 842 new_mode = ARM_CPU_MODE_ABT;
843 addr = 0x0c;
844 mask = CPSR_A | CPSR_I;
845 offset = 4;
846 break;
847 case EXCP_DATA_ABORT:
848 new_mode = ARM_CPU_MODE_ABT;
849 addr = 0x10;
850 mask = CPSR_A | CPSR_I;
851 offset = 8;
852 break;
853 case EXCP_IRQ:
854 new_mode = ARM_CPU_MODE_IRQ;
855 addr = 0x18;
856 /* Disable IRQ and imprecise data aborts. */
857 mask = CPSR_A | CPSR_I;
858 offset = 4;
859 break;
860 case EXCP_FIQ:
861 new_mode = ARM_CPU_MODE_FIQ;
862 addr = 0x1c;
863 /* Disable FIQ, IRQ and imprecise data aborts. */
864 mask = CPSR_A | CPSR_I | CPSR_F;
865 offset = 4;
866 break;
867 default:
868 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
869 return; /* Never happens. Keep compiler happy. */
870 }
871 /* High vectors. */
872 if (env->cp15.c1_sys & (1 << 13)) {
873 addr += 0xffff0000;
874 }
875 switch_mode (env, new_mode);
876 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 877 /* Clear IT bits. */
878 env->condexec_bits = 0;
30a8cac1 879 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 880 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 881 env->uncached_cpsr |= mask;
be5e7a76
DES		 882 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
883 * and we should just guard the thumb mode on V4 */
884 if (arm_feature(env, ARM_FEATURE_V4T)) {
885 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
886 }
b5ff1b31
FB		 887 env->regs[14] = env->regs[15] + offset;
888 env->regs[15] = addr;
889 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
890}
891
892/* Check section/page access permissions.
893 Returns the page protection flags, or zero if the access is not
894 permitted. */
895static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
896 int is_user)
897{
9ee6e8bb
PB		 898 int prot_ro;
899
b5ff1b31
FB		 900 if (domain == 3)
901 return PAGE_READ | PAGE_WRITE;
902
9ee6e8bb
PB		 903 if (access_type == 1)
904 prot_ro = 0;
905 else
906 prot_ro = PAGE_READ;
907
b5ff1b31
FB		 908 switch (ap) {
909 case 0:
78600320 910 if (access_type == 1)
b5ff1b31
FB		 911 return 0;
912 switch ((env->cp15.c1_sys >> 8) & 3) {
913 case 1:
914 return is_user ? 0 : PAGE_READ;
915 case 2:
916 return PAGE_READ;
917 default:
918 return 0;
919 }
920 case 1:
921 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
922 case 2:
923 if (is_user)
9ee6e8bb 924 return prot_ro;
b5ff1b31
FB		 925 else
926 return PAGE_READ | PAGE_WRITE;
927 case 3:
928 return PAGE_READ | PAGE_WRITE;
d4934d18 929 case 4: /* Reserved. */
9ee6e8bb
PB		 930 return 0;
931 case 5:
932 return is_user ? 0 : prot_ro;
933 case 6:
934 return prot_ro;
d4934d18
PB		 935 case 7:
936 if (!arm_feature (env, ARM_FEATURE_V7))
937 return 0;
938 return prot_ro;
b5ff1b31
FB		 939 default:
940 abort();
941 }
942}
943
b2fa1797
PB		 944static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
945{
946 uint32_t table;
947
948 if (address & env->cp15.c2_mask)
949 table = env->cp15.c2_base1 & 0xffffc000;
950 else
951 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
952
953 table |= (address >> 18) & 0x3ffc;
954 return table;
955}
956
9ee6e8bb 957static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 958 int is_user, uint32_t *phys_ptr, int *prot,
959 target_ulong *page_size)
b5ff1b31
FB		 960{
961 int code;
962 uint32_t table;
963 uint32_t desc;
964 int type;
965 int ap;
966 int domain;
967 uint32_t phys_addr;
968
9ee6e8bb
PB		 969 /* Pagetable walk. */
970 /* Lookup l1 descriptor. */
b2fa1797 971 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 972 desc = ldl_phys(table);
973 type = (desc & 3);
974 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
975 if (type == 0) {
601d70b9 976 /* Section translation fault. */
9ee6e8bb
PB		 977 code = 5;
978 goto do_fault;
979 }
980 if (domain == 0 || domain == 2) {
981 if (type == 2)
982 code = 9; /* Section domain fault. */
983 else
984 code = 11; /* Page domain fault. */
985 goto do_fault;
986 }
987 if (type == 2) {
988 /* 1Mb section. */
989 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
990 ap = (desc >> 10) & 3;
991 code = 13;
d4c430a8 992 *page_size = 1024 * 1024;
9ee6e8bb
PB		 993 } else {
994 /* Lookup l2 entry. */
995 if (type == 1) {
996 /* Coarse pagetable. */
997 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
998 } else {
999 /* Fine pagetable. */
1000 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1001 }
1002 desc = ldl_phys(table);
1003 switch (desc & 3) {
1004 case 0: /* Page translation fault. */
1005 code = 7;
1006 goto do_fault;
1007 case 1: /* 64k page. */
1008 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1009 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1010 *page_size = 0x10000;
ce819861 1011 break;
9ee6e8bb
PB		 1012 case 2: /* 4k page. */
1013 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1014 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1015 *page_size = 0x1000;
ce819861 1016 break;
9ee6e8bb
PB		 1017 case 3: /* 1k page. */
1018 if (type == 1) {
1019 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1020 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1021 } else {
1022 /* Page translation fault. */
1023 code = 7;
1024 goto do_fault;
1025 }
1026 } else {
1027 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1028 }
1029 ap = (desc >> 4) & 3;
d4c430a8 1030 *page_size = 0x400;
ce819861
PB		 1031 break;
1032 default:
9ee6e8bb
PB		 1033 /* Never happens, but compiler isn't smart enough to tell. */
1034 abort();
ce819861 1035 }
9ee6e8bb
PB		 1036 code = 15;
1037 }
1038 *prot = check_ap(env, ap, domain, access_type, is_user);
1039 if (!*prot) {
1040 /* Access permission fault. */
1041 goto do_fault;
1042 }
3ad493fc 1043 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1044 *phys_ptr = phys_addr;
1045 return 0;
1046do_fault:
1047 return code | (domain << 4);
1048}
1049
1050static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
d4c430a8
PB		 1051 int is_user, uint32_t *phys_ptr, int *prot,
1052 target_ulong *page_size)
9ee6e8bb
PB		 1053{
1054 int code;
1055 uint32_t table;
1056 uint32_t desc;
1057 uint32_t xn;
1058 int type;
1059 int ap;
1060 int domain;
1061 uint32_t phys_addr;
1062
1063 /* Pagetable walk. */
1064 /* Lookup l1 descriptor. */
b2fa1797 1065 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1066 desc = ldl_phys(table);
1067 type = (desc & 3);
1068 if (type == 0) {
601d70b9 1069 /* Section translation fault. */
9ee6e8bb
PB		 1070 code = 5;
1071 domain = 0;
1072 goto do_fault;
1073 } else if (type == 2 && (desc & (1 << 18))) {
1074 /* Supersection. */
1075 domain = 0;
b5ff1b31 1076 } else {
9ee6e8bb
PB		 1077 /* Section or page. */
1078 domain = (desc >> 4) & 0x1e;
1079 }
1080 domain = (env->cp15.c3 >> domain) & 3;
1081 if (domain == 0 || domain == 2) {
1082 if (type == 2)
1083 code = 9; /* Section domain fault. */
1084 else
1085 code = 11; /* Page domain fault. */
1086 goto do_fault;
1087 }
1088 if (type == 2) {
1089 if (desc & (1 << 18)) {
1090 /* Supersection. */
1091 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1092 *page_size = 0x1000000;
b5ff1b31 1093 } else {
9ee6e8bb
PB		 1094 /* Section. */
1095 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1096 *page_size = 0x100000;
b5ff1b31 1097 }
9ee6e8bb
PB		 1098 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1099 xn = desc & (1 << 4);
1100 code = 13;
1101 } else {
1102 /* Lookup l2 entry. */
1103 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1104 desc = ldl_phys(table);
1105 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1106 switch (desc & 3) {
1107 case 0: /* Page translation fault. */
1108 code = 7;
b5ff1b31 1109 goto do_fault;
9ee6e8bb
PB		 1110 case 1: /* 64k page. */
1111 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1112 xn = desc & (1 << 15);
d4c430a8 1113 *page_size = 0x10000;
9ee6e8bb
PB		 1114 break;
1115 case 2: case 3: /* 4k page. */
1116 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1117 xn = desc & 1;
d4c430a8 1118 *page_size = 0x1000;
9ee6e8bb
PB		 1119 break;
1120 default:
1121 /* Never happens, but compiler isn't smart enough to tell. */
1122 abort();
b5ff1b31 1123 }
9ee6e8bb
PB		 1124 code = 15;
1125 }
c0034328
JR		 1126 if (domain == 3) {
1127 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1128 } else {
1129 if (xn && access_type == 2)
1130 goto do_fault;
9ee6e8bb 1131
c0034328
JR		 1132 /* The simplified model uses AP[0] as an access control bit. */
1133 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1134 /* Access flag fault. */
1135 code = (code == 15) ? 6 : 3;
1136 goto do_fault;
1137 }
1138 *prot = check_ap(env, ap, domain, access_type, is_user);
1139 if (!*prot) {
1140 /* Access permission fault. */
1141 goto do_fault;
1142 }
1143 if (!xn) {
1144 *prot |= PAGE_EXEC;
1145 }
3ad493fc 1146 }
9ee6e8bb 1147 *phys_ptr = phys_addr;
b5ff1b31
FB		 1148 return 0;
1149do_fault:
1150 return code | (domain << 4);
1151}
1152
9ee6e8bb
PB		 1153static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1154 int is_user, uint32_t *phys_ptr, int *prot)
1155{
1156 int n;
1157 uint32_t mask;
1158 uint32_t base;
1159
1160 *phys_ptr = address;
1161 for (n = 7; n >= 0; n--) {
1162 base = env->cp15.c6_region[n];
1163 if ((base & 1) == 0)
1164 continue;
1165 mask = 1 << ((base >> 1) & 0x1f);
1166 /* Keep this shift separate from the above to avoid an
1167 (undefined) << 32. */
1168 mask = (mask << 1) - 1;
1169 if (((base ^ address) & ~mask) == 0)
1170 break;
1171 }
1172 if (n < 0)
1173 return 2;
1174
1175 if (access_type == 2) {
1176 mask = env->cp15.c5_insn;
1177 } else {
1178 mask = env->cp15.c5_data;
1179 }
1180 mask = (mask >> (n * 4)) & 0xf;
1181 switch (mask) {
1182 case 0:
1183 return 1;
1184 case 1:
1185 if (is_user)
1186 return 1;
1187 *prot = PAGE_READ | PAGE_WRITE;
1188 break;
1189 case 2:
1190 *prot = PAGE_READ;
1191 if (!is_user)
1192 *prot |= PAGE_WRITE;
1193 break;
1194 case 3:
1195 *prot = PAGE_READ | PAGE_WRITE;
1196 break;
1197 case 5:
1198 if (is_user)
1199 return 1;
1200 *prot = PAGE_READ;
1201 break;
1202 case 6:
1203 *prot = PAGE_READ;
1204 break;
1205 default:
1206 /* Bad permission. */
1207 return 1;
1208 }
3ad493fc 1209 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1210 return 0;
1211}
1212
1213static inline int get_phys_addr(CPUState *env, uint32_t address,
1214 int access_type, int is_user,
d4c430a8
PB		 1215 uint32_t *phys_ptr, int *prot,
1216 target_ulong *page_size)
9ee6e8bb
PB		 1217{
1218 /* Fast Context Switch Extension. */
1219 if (address < 0x02000000)
1220 address += env->cp15.c13_fcse;
1221
1222 if ((env->cp15.c1_sys & 1) == 0) {
1223 /* MMU/MPU disabled. */
1224 *phys_ptr = address;
3ad493fc 1225 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1226 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1227 return 0;
1228 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1229 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1230 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1231 prot);
1232 } else if (env->cp15.c1_sys & (1 << 23)) {
1233 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1234 prot, page_size);
9ee6e8bb
PB		 1235 } else {
1236 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1237 prot, page_size);
9ee6e8bb
PB		 1238 }
1239}
1240
b5ff1b31 1241int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1242 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1243{
1244 uint32_t phys_addr;
d4c430a8 1245 target_ulong page_size;
b5ff1b31 1246 int prot;
6ebbf390 1247 int ret, is_user;
b5ff1b31 1248
6ebbf390 1249 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1250 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1251 &page_size);
b5ff1b31
FB		 1252 if (ret == 0) {
1253 /* Map a single [sub]page. */
1254 phys_addr &= ~(uint32_t)0x3ff;
1255 address &= ~(uint32_t)0x3ff;
3ad493fc 1256 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1257 return 0;
b5ff1b31
FB		 1258 }
1259
1260 if (access_type == 2) {
1261 env->cp15.c5_insn = ret;
1262 env->cp15.c6_insn = address;
1263 env->exception_index = EXCP_PREFETCH_ABORT;
1264 } else {
1265 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1266 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1267 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1268 env->cp15.c6_data = address;
1269 env->exception_index = EXCP_DATA_ABORT;
1270 }
1271 return 1;
1272}
1273
c227f099 1274target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1275{
1276 uint32_t phys_addr;
d4c430a8 1277 target_ulong page_size;
b5ff1b31
FB		 1278 int prot;
1279 int ret;
1280
d4c430a8 1281 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1282
1283 if (ret != 0)
1284 return -1;
1285
1286 return phys_addr;
1287}
1288
8984bd2e 1289void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1290{
1291 int cp_num = (insn >> 8) & 0xf;
1292 int cp_info = (insn >> 5) & 7;
1293 int src = (insn >> 16) & 0xf;
1294 int operand = insn & 0xf;
1295
1296 if (env->cp[cp_num].cp_write)
1297 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1298 cp_info, src, operand, val);
1299}
1300
8984bd2e 1301uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1302{
1303 int cp_num = (insn >> 8) & 0xf;
1304 int cp_info = (insn >> 5) & 7;
1305 int dest = (insn >> 16) & 0xf;
1306 int operand = insn & 0xf;
1307
1308 if (env->cp[cp_num].cp_read)
1309 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1310 cp_info, dest, operand);
1311 return 0;
1312}
1313
ce819861
PB		 1314/* Return basic MPU access permission bits. */
1315static uint32_t simple_mpu_ap_bits(uint32_t val)
1316{
1317 uint32_t ret;
1318 uint32_t mask;
1319 int i;
1320 ret = 0;
1321 mask = 3;
1322 for (i = 0; i < 16; i += 2) {
1323 ret |= (val >> i) & mask;
1324 mask <<= 2;
1325 }
1326 return ret;
1327}
1328
1329/* Pad basic MPU access permission bits to extended format. */
1330static uint32_t extended_mpu_ap_bits(uint32_t val)
1331{
1332 uint32_t ret;
1333 uint32_t mask;
1334 int i;
1335 ret = 0;
1336 mask = 3;
1337 for (i = 0; i < 16; i += 2) {
1338 ret |= (val & mask) << i;
1339 mask <<= 2;
1340 }
1341 return ret;
1342}
1343
8984bd2e 1344void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1345{
9ee6e8bb
PB		 1346 int op1;
1347 int op2;
1348 int crm;
b5ff1b31 1349
9ee6e8bb 1350 op1 = (insn >> 21) & 7;
b5ff1b31 1351 op2 = (insn >> 5) & 7;
ce819861 1352 crm = insn & 0xf;
b5ff1b31 1353 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1354 case 0:
9ee6e8bb 1355 /* ID codes. */
610c3c8a
AZ		 1356 if (arm_feature(env, ARM_FEATURE_XSCALE))
1357 break;
c3d2689d
AZ		 1358 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1359 break;
a49ea279
PB		 1360 if (arm_feature(env, ARM_FEATURE_V7)
1361 && op1 == 2 && crm == 0 && op2 == 0) {
1362 env->cp15.c0_cssel = val & 0xf;
1363 break;
1364 }
b5ff1b31
FB		 1365 goto bad_reg;
1366 case 1: /* System configuration. */
c3d2689d
AZ		 1367 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1368 op2 = 0;
b5ff1b31
FB		 1369 switch (op2) {
1370 case 0:
ce819861 1371 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1372 env->cp15.c1_sys = val;
b5ff1b31
FB		 1373 /* ??? Lots of these bits are not implemented. */
1374 /* This may enable/disable the MMU, so do a TLB flush. */
1375 tlb_flush(env, 1);
1376 break;
9ee6e8bb 1377 case 1: /* Auxiliary cotrol register. */
610c3c8a
AZ		 1378 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1379 env->cp15.c1_xscaleauxcr = val;
c1713132 1380 break;
610c3c8a 1381 }
9ee6e8bb
PB		 1382 /* Not implemented. */
1383 break;
b5ff1b31 1384 case 2:
610c3c8a
AZ		 1385 if (arm_feature(env, ARM_FEATURE_XSCALE))
1386 goto bad_reg;
4be27dbb
PB		 1387 if (env->cp15.c1_coproc != val) {
1388 env->cp15.c1_coproc = val;
1389 /* ??? Is this safe when called from within a TB? */
1390 tb_flush(env);
1391 }
c1713132 1392 break;
b5ff1b31
FB		 1393 default:
1394 goto bad_reg;
1395 }
1396 break;
ce819861
PB		 1397 case 2: /* MMU Page table control / MPU cache control. */
1398 if (arm_feature(env, ARM_FEATURE_MPU)) {
1399 switch (op2) {
1400 case 0:
1401 env->cp15.c2_data = val;
1402 break;
1403 case 1:
1404 env->cp15.c2_insn = val;
1405 break;
1406 default:
1407 goto bad_reg;
1408 }
1409 } else {
9ee6e8bb
PB		 1410 switch (op2) {
1411 case 0:
1412 env->cp15.c2_base0 = val;
1413 break;
1414 case 1:
1415 env->cp15.c2_base1 = val;
1416 break;
1417 case 2:
b2fa1797
PB		 1418 val &= 7;
1419 env->cp15.c2_control = val;
9ee6e8bb 1420 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1421 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1422 break;
1423 default:
1424 goto bad_reg;
1425 }
ce819861 1426 }
b5ff1b31 1427 break;
ce819861 1428 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1429 env->cp15.c3 = val;
405ee3ad 1430 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1431 break;
1432 case 4: /* Reserved. */
1433 goto bad_reg;
ce819861 1434 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1435 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1436 op2 = 0;
b5ff1b31
FB		 1437 switch (op2) {
1438 case 0:
ce819861
PB		 1439 if (arm_feature(env, ARM_FEATURE_MPU))
1440 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1441 env->cp15.c5_data = val;
1442 break;
1443 case 1:
ce819861
PB		 1444 if (arm_feature(env, ARM_FEATURE_MPU))
1445 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1446 env->cp15.c5_insn = val;
1447 break;
ce819861
PB		 1448 case 2:
1449 if (!arm_feature(env, ARM_FEATURE_MPU))
1450 goto bad_reg;
1451 env->cp15.c5_data = val;
b5ff1b31 1452 break;
ce819861
PB		 1453 case 3:
1454 if (!arm_feature(env, ARM_FEATURE_MPU))
1455 goto bad_reg;
1456 env->cp15.c5_insn = val;
b5ff1b31
FB		 1457 break;
1458 default:
1459 goto bad_reg;
1460 }
1461 break;
ce819861
PB		 1462 case 6: /* MMU Fault address / MPU base/size. */
1463 if (arm_feature(env, ARM_FEATURE_MPU)) {
1464 if (crm >= 8)
1465 goto bad_reg;
1466 env->cp15.c6_region[crm] = val;
1467 } else {
c3d2689d
AZ		 1468 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1469 op2 = 0;
ce819861
PB		 1470 switch (op2) {
1471 case 0:
1472 env->cp15.c6_data = val;
1473 break;
9ee6e8bb
PB		 1474 case 1: /* ??? This is WFAR on armv6 */
1475 case 2:
ce819861
PB		 1476 env->cp15.c6_insn = val;
1477 break;
1478 default:
1479 goto bad_reg;
1480 }
1481 }
1482 break;
b5ff1b31 1483 case 7: /* Cache control. */
c3d2689d
AZ		 1484 env->cp15.c15_i_max = 0x000;
1485 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1486 if (op1 != 0) {
1487 goto bad_reg;
1488 }
1489 /* No cache, so nothing to do except VA->PA translations. */
1490 if (arm_feature(env, ARM_FEATURE_V6K)) {
1491 switch (crm) {
1492 case 4:
1493 if (arm_feature(env, ARM_FEATURE_V7)) {
1494 env->cp15.c7_par = val & 0xfffff6ff;
1495 } else {
1496 env->cp15.c7_par = val & 0xfffff1ff;
1497 }
1498 break;
1499 case 8: {
1500 uint32_t phys_addr;
1501 target_ulong page_size;
1502 int prot;
1503 int ret, is_user = op2 & 2;
1504 int access_type = op2 & 1;
1505
1506 if (op2 & 4) {
1507 /* Other states are only available with TrustZone */
1508 goto bad_reg;
1509 }
1510 ret = get_phys_addr(env, val, access_type, is_user,
1511 &phys_addr, &prot, &page_size);
1512 if (ret == 0) {
1513 /* We do not set any attribute bits in the PAR */
1514 if (page_size == (1 << 24)
1515 && arm_feature(env, ARM_FEATURE_V7)) {
1516 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1517 } else {
1518 env->cp15.c7_par = phys_addr & 0xfffff000;
1519 }
1520 } else {
1521 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1522 ((ret & (12 << 1)) >> 6) |
1523 ((ret & 0xf) << 1) | 1;
1524 }
1525 break;
1526 }
1527 }
1528 }
b5ff1b31
FB		 1529 break;
1530 case 8: /* MMU TLB control. */
1531 switch (op2) {
1532 case 0: /* Invalidate all. */
1533 tlb_flush(env, 0);
1534 break;
1535 case 1: /* Invalidate single TLB entry. */
d4c430a8 1536 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1537 break;
9ee6e8bb
PB		 1538 case 2: /* Invalidate on ASID. */
1539 tlb_flush(env, val == 0);
1540 break;
1541 case 3: /* Invalidate single entry on MVA. */
1542 /* ??? This is like case 1, but ignores ASID. */
1543 tlb_flush(env, 1);
1544 break;
b5ff1b31
FB		 1545 default:
1546 goto bad_reg;
1547 }
1548 break;
ce819861 1549 case 9:
c3d2689d
AZ		 1550 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1551 break;
ce819861
PB		 1552 switch (crm) {
1553 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1554 switch (op1) {
1555 case 0: /* L1 cache. */
1556 switch (op2) {
1557 case 0:
1558 env->cp15.c9_data = val;
1559 break;
1560 case 1:
1561 env->cp15.c9_insn = val;
1562 break;
1563 default:
1564 goto bad_reg;
1565 }
1566 break;
1567 case 1: /* L2 cache. */
1568 /* Ignore writes to L2 lockdown/auxiliary registers. */
1569 break;
1570 default:
1571 goto bad_reg;
1572 }
1573 break;
ce819861
PB		 1574 case 1: /* TCM memory region registers. */
1575 /* Not implemented. */
1576 goto bad_reg;
b5ff1b31
FB		 1577 default:
1578 goto bad_reg;
1579 }
1580 break;
1581 case 10: /* MMU TLB lockdown. */
1582 /* ??? TLB lockdown not implemented. */
1583 break;
b5ff1b31
FB		 1584 case 12: /* Reserved. */
1585 goto bad_reg;
1586 case 13: /* Process ID. */
1587 switch (op2) {
1588 case 0:
d07edbfa
PB		 1589 /* Unlike real hardware the qemu TLB uses virtual addresses,
1590 not modified virtual addresses, so this causes a TLB flush.
1591 */
1592 if (env->cp15.c13_fcse != val)
1593 tlb_flush(env, 1);
1594 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1595 break;
1596 case 1:
d07edbfa 1597 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1598 if (env->cp15.c13_context != val
1599 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1600 tlb_flush(env, 0);
1601 env->cp15.c13_context = val;
b5ff1b31
FB		 1602 break;
1603 default:
1604 goto bad_reg;
1605 }
1606 break;
1607 case 14: /* Reserved. */
1608 goto bad_reg;
1609 case 15: /* Implementation specific. */
c1713132 1610 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1611 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1612 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1613 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1614 tb_flush(env);
1615 env->cp15.c15_cpar = val & 0x3fff;
1616 }
c1713132
AZ		 1617 break;
1618 }
1619 goto bad_reg;
1620 }
c3d2689d
AZ		 1621 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1622 switch (crm) {
1623 case 0:
1624 break;
1625 case 1: /* Set TI925T configuration. */
1626 env->cp15.c15_ticonfig = val & 0xe7;
1627 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1628 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1629 break;
1630 case 2: /* Set I_max. */
1631 env->cp15.c15_i_max = val;
1632 break;
1633 case 3: /* Set I_min. */
1634 env->cp15.c15_i_min = val;
1635 break;
1636 case 4: /* Set thread-ID. */
1637 env->cp15.c15_threadid = val & 0xffff;
1638 break;
1639 case 8: /* Wait-for-interrupt (deprecated). */
1640 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1641 break;
1642 default:
1643 goto bad_reg;
1644 }
1645 }
b5ff1b31
FB		 1646 break;
1647 }
1648 return;
1649bad_reg:
1650 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1651 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1652 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1653}
1654
8984bd2e 1655uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1656{
9ee6e8bb
PB		 1657 int op1;
1658 int op2;
1659 int crm;
b5ff1b31 1660
9ee6e8bb 1661 op1 = (insn >> 21) & 7;
b5ff1b31 1662 op2 = (insn >> 5) & 7;
c3d2689d 1663 crm = insn & 0xf;
b5ff1b31
FB		 1664 switch ((insn >> 16) & 0xf) {
1665 case 0: /* ID codes. */
9ee6e8bb
PB		 1666 switch (op1) {
1667 case 0:
1668 switch (crm) {
1669 case 0:
1670 switch (op2) {
1671 case 0: /* Device ID. */
1672 return env->cp15.c0_cpuid;
1673 case 1: /* Cache Type. */
1674 return env->cp15.c0_cachetype;
1675 case 2: /* TCM status. */
1676 return 0;
1677 case 3: /* TLB type register. */
1678 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1679 case 5: /* MPIDR */
1680 /* The MPIDR was standardised in v7; prior to
1681 * this it was implemented only in the 11MPCore.
1682 * For all other pre-v7 cores it does not exist.
1683 */
1684 if (arm_feature(env, ARM_FEATURE_V7) ||
1685 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1686 int mpidr = env->cpu_index;
1687 /* We don't support setting cluster ID ([8..11])
1688 * so these bits always RAZ.
1689 */
1690 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1691 mpidr |= (1 << 31);
1692 /* Cores which are uniprocessor (non-coherent)
1693 * but still implement the MP extensions set
1694 * bit 30. (For instance, A9UP.) However we do
1695 * not currently model any of those cores.
1696 */
1697 }
1698 return mpidr;
10055562 1699 }
607b4b08 1700 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1701 default:
1702 goto bad_reg;
1703 }
1704 case 1:
1705 if (!arm_feature(env, ARM_FEATURE_V6))
1706 goto bad_reg;
1707 return env->cp15.c0_c1[op2];
1708 case 2:
1709 if (!arm_feature(env, ARM_FEATURE_V6))
1710 goto bad_reg;
1711 return env->cp15.c0_c2[op2];
1712 case 3: case 4: case 5: case 6: case 7:
1713 return 0;
1714 default:
1715 goto bad_reg;
1716 }
1717 case 1:
1718 /* These registers aren't documented on arm11 cores. However
1719 Linux looks at them anyway. */
1720 if (!arm_feature(env, ARM_FEATURE_V6))
1721 goto bad_reg;
1722 if (crm != 0)
1723 goto bad_reg;
a49ea279
PB		 1724 if (!arm_feature(env, ARM_FEATURE_V7))
1725 return 0;
1726
1727 switch (op2) {
1728 case 0:
1729 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1730 case 1:
1731 return env->cp15.c0_clid;
1732 case 7:
1733 return 0;
1734 }
1735 goto bad_reg;
1736 case 2:
1737 if (op2 != 0 || crm != 0)
610c3c8a 1738 goto bad_reg;
a49ea279 1739 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1740 default:
1741 goto bad_reg;
b5ff1b31
FB		 1742 }
1743 case 1: /* System configuration. */
c3d2689d
AZ		 1744 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1745 op2 = 0;
b5ff1b31
FB		 1746 switch (op2) {
1747 case 0: /* Control register. */
1748 return env->cp15.c1_sys;
1749 case 1: /* Auxiliary control register. */
c1713132 1750 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1751 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1752 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1753 goto bad_reg;
1754 switch (ARM_CPUID(env)) {
1755 case ARM_CPUID_ARM1026:
1756 return 1;
1757 case ARM_CPUID_ARM1136:
827df9f3 1758 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1759 return 7;
1760 case ARM_CPUID_ARM11MPCORE:
1761 return 1;
1762 case ARM_CPUID_CORTEXA8:
533d177a 1763 return 2;
10055562
PB		 1764 case ARM_CPUID_CORTEXA9:
1765 return 0;
9ee6e8bb
PB		 1766 default:
1767 goto bad_reg;
1768 }
b5ff1b31 1769 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1770 if (arm_feature(env, ARM_FEATURE_XSCALE))
1771 goto bad_reg;
b5ff1b31
FB		 1772 return env->cp15.c1_coproc;
1773 default:
1774 goto bad_reg;
1775 }
ce819861
PB		 1776 case 2: /* MMU Page table control / MPU cache control. */
1777 if (arm_feature(env, ARM_FEATURE_MPU)) {
1778 switch (op2) {
1779 case 0:
1780 return env->cp15.c2_data;
1781 break;
1782 case 1:
1783 return env->cp15.c2_insn;
1784 break;
1785 default:
1786 goto bad_reg;
1787 }
1788 } else {
9ee6e8bb
PB		 1789 switch (op2) {
1790 case 0:
1791 return env->cp15.c2_base0;
1792 case 1:
1793 return env->cp15.c2_base1;
1794 case 2:
b2fa1797 1795 return env->cp15.c2_control;
9ee6e8bb
PB		 1796 default:
1797 goto bad_reg;
1798 }
1799 }
ce819861 1800 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1801 return env->cp15.c3;
1802 case 4: /* Reserved. */
1803 goto bad_reg;
ce819861 1804 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1805 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1806 op2 = 0;
b5ff1b31
FB		 1807 switch (op2) {
1808 case 0:
ce819861
PB		 1809 if (arm_feature(env, ARM_FEATURE_MPU))
1810 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1811 return env->cp15.c5_data;
1812 case 1:
ce819861
PB		 1813 if (arm_feature(env, ARM_FEATURE_MPU))
1814 return simple_mpu_ap_bits(env->cp15.c5_data);
1815 return env->cp15.c5_insn;
1816 case 2:
1817 if (!arm_feature(env, ARM_FEATURE_MPU))
1818 goto bad_reg;
1819 return env->cp15.c5_data;
1820 case 3:
1821 if (!arm_feature(env, ARM_FEATURE_MPU))
1822 goto bad_reg;
b5ff1b31
FB		 1823 return env->cp15.c5_insn;
1824 default:
1825 goto bad_reg;
1826 }
9ee6e8bb 1827 case 6: /* MMU Fault address. */
ce819861 1828 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1829 if (crm >= 8)
ce819861 1830 goto bad_reg;
9ee6e8bb 1831 return env->cp15.c6_region[crm];
ce819861 1832 } else {
c3d2689d
AZ		 1833 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1834 op2 = 0;
9ee6e8bb
PB		 1835 switch (op2) {
1836 case 0:
1837 return env->cp15.c6_data;
1838 case 1:
1839 if (arm_feature(env, ARM_FEATURE_V6)) {
1840 /* Watchpoint Fault Adrress. */
1841 return 0; /* Not implemented. */
1842 } else {
1843 /* Instruction Fault Adrress. */
1844 /* Arm9 doesn't have an IFAR, but implementing it anyway
1845 shouldn't do any harm. */
1846 return env->cp15.c6_insn;
1847 }
1848 case 2:
1849 if (arm_feature(env, ARM_FEATURE_V6)) {
1850 /* Instruction Fault Adrress. */
1851 return env->cp15.c6_insn;
1852 } else {
1853 goto bad_reg;
1854 }
1855 default:
1856 goto bad_reg;
1857 }
b5ff1b31
FB		 1858 }
1859 case 7: /* Cache control. */
f8bf8606
AL		 1860 if (crm == 4 && op1 == 0 && op2 == 0) {
1861 return env->cp15.c7_par;
1862 }
6fbe23d5
PB		 1863 /* FIXME: Should only clear Z flag if destination is r15. */
1864 env->ZF = 0;
b5ff1b31
FB		 1865 return 0;
1866 case 8: /* MMU TLB control. */
1867 goto bad_reg;
1868 case 9: /* Cache lockdown. */
9ee6e8bb
PB		 1869 switch (op1) {
1870 case 0: /* L1 cache. */
1871 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1872 return 0;
1873 switch (op2) {
1874 case 0:
1875 return env->cp15.c9_data;
1876 case 1:
1877 return env->cp15.c9_insn;
1878 default:
1879 goto bad_reg;
1880 }
1881 case 1: /* L2 cache */
1882 if (crm != 0)
1883 goto bad_reg;
1884 /* L2 Lockdown and Auxiliary control. */
c3d2689d 1885 return 0;
b5ff1b31
FB		 1886 default:
1887 goto bad_reg;
1888 }
1889 case 10: /* MMU TLB lockdown. */
1890 /* ??? TLB lockdown not implemented. */
1891 return 0;
1892 case 11: /* TCM DMA control. */
1893 case 12: /* Reserved. */
1894 goto bad_reg;
1895 case 13: /* Process ID. */
1896 switch (op2) {
1897 case 0:
1898 return env->cp15.c13_fcse;
1899 case 1:
1900 return env->cp15.c13_context;
1901 default:
1902 goto bad_reg;
1903 }
1904 case 14: /* Reserved. */
1905 goto bad_reg;
1906 case 15: /* Implementation specific. */
c1713132 1907 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 1908 if (op2 == 0 && crm == 1)
c1713132
AZ		 1909 return env->cp15.c15_cpar;
1910
1911 goto bad_reg;
1912 }
c3d2689d
AZ		 1913 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1914 switch (crm) {
1915 case 0:
1916 return 0;
1917 case 1: /* Read TI925T configuration. */
1918 return env->cp15.c15_ticonfig;
1919 case 2: /* Read I_max. */
1920 return env->cp15.c15_i_max;
1921 case 3: /* Read I_min. */
1922 return env->cp15.c15_i_min;
1923 case 4: /* Read thread-ID. */
1924 return env->cp15.c15_threadid;
1925 case 8: /* TI925T_status */
1926 return 0;
1927 }
827df9f3
AZ		 1928 /* TODO: Peripheral port remap register:
1929 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1930 * controller base address at $rn & ~0xfff and map size of
1931 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 1932 goto bad_reg;
1933 }
b5ff1b31
FB		 1934 return 0;
1935 }
1936bad_reg:
1937 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1938 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1939 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1940 return 0;
1941}
1942
b0109805 1943void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb 1944{
39ea3d4e
PM		 1945 if ((env->uncached_cpsr & CPSR_M) == mode) {
1946 env->regs[13] = val;
1947 } else {
1948 env->banked_r13[bank_number(mode)] = val;
1949 }
9ee6e8bb
PB		 1950}
1951
b0109805 1952uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb 1953{
39ea3d4e
PM		 1954 if ((env->uncached_cpsr & CPSR_M) == mode) {
1955 return env->regs[13];
1956 } else {
1957 return env->banked_r13[bank_number(mode)];
1958 }
9ee6e8bb
PB		 1959}
1960
8984bd2e 1961uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 1962{
1963 switch (reg) {
1964 case 0: /* APSR */
1965 return xpsr_read(env) & 0xf8000000;
1966 case 1: /* IAPSR */
1967 return xpsr_read(env) & 0xf80001ff;
1968 case 2: /* EAPSR */
1969 return xpsr_read(env) & 0xff00fc00;
1970 case 3: /* xPSR */
1971 return xpsr_read(env) & 0xff00fdff;
1972 case 5: /* IPSR */
1973 return xpsr_read(env) & 0x000001ff;
1974 case 6: /* EPSR */
1975 return xpsr_read(env) & 0x0700fc00;
1976 case 7: /* IEPSR */
1977 return xpsr_read(env) & 0x0700edff;
1978 case 8: /* MSP */
1979 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1980 case 9: /* PSP */
1981 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1982 case 16: /* PRIMASK */
1983 return (env->uncached_cpsr & CPSR_I) != 0;
1984 case 17: /* FAULTMASK */
1985 return (env->uncached_cpsr & CPSR_F) != 0;
1986 case 18: /* BASEPRI */
1987 case 19: /* BASEPRI_MAX */
1988 return env->v7m.basepri;
1989 case 20: /* CONTROL */
1990 return env->v7m.control;
1991 default:
1992 /* ??? For debugging only. */
1993 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1994 return 0;
1995 }
1996}
1997
8984bd2e 1998void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1999{
2000 switch (reg) {
2001 case 0: /* APSR */
2002 xpsr_write(env, val, 0xf8000000);
2003 break;
2004 case 1: /* IAPSR */
2005 xpsr_write(env, val, 0xf8000000);
2006 break;
2007 case 2: /* EAPSR */
2008 xpsr_write(env, val, 0xfe00fc00);
2009 break;
2010 case 3: /* xPSR */
2011 xpsr_write(env, val, 0xfe00fc00);
2012 break;
2013 case 5: /* IPSR */
2014 /* IPSR bits are readonly. */
2015 break;
2016 case 6: /* EPSR */
2017 xpsr_write(env, val, 0x0600fc00);
2018 break;
2019 case 7: /* IEPSR */
2020 xpsr_write(env, val, 0x0600fc00);
2021 break;
2022 case 8: /* MSP */
2023 if (env->v7m.current_sp)
2024 env->v7m.other_sp = val;
2025 else
2026 env->regs[13] = val;
2027 break;
2028 case 9: /* PSP */
2029 if (env->v7m.current_sp)
2030 env->regs[13] = val;
2031 else
2032 env->v7m.other_sp = val;
2033 break;
2034 case 16: /* PRIMASK */
2035 if (val & 1)
2036 env->uncached_cpsr |= CPSR_I;
2037 else
2038 env->uncached_cpsr &= ~CPSR_I;
2039 break;
2040 case 17: /* FAULTMASK */
2041 if (val & 1)
2042 env->uncached_cpsr |= CPSR_F;
2043 else
2044 env->uncached_cpsr &= ~CPSR_F;
2045 break;
2046 case 18: /* BASEPRI */
2047 env->v7m.basepri = val & 0xff;
2048 break;
2049 case 19: /* BASEPRI_MAX */
2050 val &= 0xff;
2051 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2052 env->v7m.basepri = val;
2053 break;
2054 case 20: /* CONTROL */
2055 env->v7m.control = val & 3;
2056 switch_v7m_sp(env, (val & 2) != 0);
2057 break;
2058 default:
2059 /* ??? For debugging only. */
2060 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2061 return;
2062 }
2063}
2064
c1713132
AZ		 2065void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
2066 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
2067 void *opaque)
2068{
2069 if (cpnum < 0 || cpnum > 14) {
2070 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
2071 return;
2072 }
2073
2074 env->cp[cpnum].cp_read = cp_read;
2075 env->cp[cpnum].cp_write = cp_write;
2076 env->cp[cpnum].opaque = opaque;
2077}
2078
b5ff1b31 2079#endif
6ddbc6e4
PB		 2080
2081/* Note that signed overflow is undefined in C. The following routines are
2082 careful to use unsigned types where modulo arithmetic is required.
2083 Failure to do so _will_ break on newer gcc. */
2084
2085/* Signed saturating arithmetic. */
2086
1654b2d6 2087/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2088static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2089{
2090 uint16_t res;
2091
2092 res = a + b;
2093 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2094 if (a & 0x8000)
2095 res = 0x8000;
2096 else
2097 res = 0x7fff;
2098 }
2099 return res;
2100}
2101
1654b2d6 2102/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2103static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2104{
2105 uint8_t res;
2106
2107 res = a + b;
2108 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2109 if (a & 0x80)
2110 res = 0x80;
2111 else
2112 res = 0x7f;
2113 }
2114 return res;
2115}
2116
1654b2d6 2117/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2118static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2119{
2120 uint16_t res;
2121
2122 res = a - b;
2123 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2124 if (a & 0x8000)
2125 res = 0x8000;
2126 else
2127 res = 0x7fff;
2128 }
2129 return res;
2130}
2131
1654b2d6 2132/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2133static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2134{
2135 uint8_t res;
2136
2137 res = a - b;
2138 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2139 if (a & 0x80)
2140 res = 0x80;
2141 else
2142 res = 0x7f;
2143 }
2144 return res;
2145}
2146
2147#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2148#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2149#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2150#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2151#define PFX q
2152
2153#include "op_addsub.h"
2154
2155/* Unsigned saturating arithmetic. */
460a09c1 2156static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2157{
2158 uint16_t res;
2159 res = a + b;
2160 if (res < a)
2161 res = 0xffff;
2162 return res;
2163}
2164
460a09c1 2165static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2166{
4c4fd3f8 2167 if (a > b)
6ddbc6e4
PB		 2168 return a - b;
2169 else
2170 return 0;
2171}
2172
2173static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2174{
2175 uint8_t res;
2176 res = a + b;
2177 if (res < a)
2178 res = 0xff;
2179 return res;
2180}
2181
2182static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2183{
4c4fd3f8 2184 if (a > b)
6ddbc6e4
PB		 2185 return a - b;
2186 else
2187 return 0;
2188}
2189
2190#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2191#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2192#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2193#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2194#define PFX uq
2195
2196#include "op_addsub.h"
2197
2198/* Signed modulo arithmetic. */
2199#define SARITH16(a, b, n, op) do { \
2200 int32_t sum; \
db6e2e65 2201 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2202 RESULT(sum, n, 16); \
2203 if (sum >= 0) \
2204 ge |= 3 << (n * 2); \
2205 } while(0)
2206
2207#define SARITH8(a, b, n, op) do { \
2208 int32_t sum; \
db6e2e65 2209 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2210 RESULT(sum, n, 8); \
2211 if (sum >= 0) \
2212 ge |= 1 << n; \
2213 } while(0)
2214
2215
2216#define ADD16(a, b, n) SARITH16(a, b, n, +)
2217#define SUB16(a, b, n) SARITH16(a, b, n, -)
2218#define ADD8(a, b, n) SARITH8(a, b, n, +)
2219#define SUB8(a, b, n) SARITH8(a, b, n, -)
2220#define PFX s
2221#define ARITH_GE
2222
2223#include "op_addsub.h"
2224
2225/* Unsigned modulo arithmetic. */
2226#define ADD16(a, b, n) do { \
2227 uint32_t sum; \
2228 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2229 RESULT(sum, n, 16); \
a87aa10b 2230 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2231 ge |= 3 << (n * 2); \
2232 } while(0)
2233
2234#define ADD8(a, b, n) do { \
2235 uint32_t sum; \
2236 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2237 RESULT(sum, n, 8); \
a87aa10b
AZ		 2238 if ((sum >> 8) == 1) \
2239 ge |= 1 << n; \
6ddbc6e4
PB		 2240 } while(0)
2241
2242#define SUB16(a, b, n) do { \
2243 uint32_t sum; \
2244 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2245 RESULT(sum, n, 16); \
2246 if ((sum >> 16) == 0) \
2247 ge |= 3 << (n * 2); \
2248 } while(0)
2249
2250#define SUB8(a, b, n) do { \
2251 uint32_t sum; \
2252 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2253 RESULT(sum, n, 8); \
2254 if ((sum >> 8) == 0) \
a87aa10b 2255 ge |= 1 << n; \
6ddbc6e4
PB		 2256 } while(0)
2257
2258#define PFX u
2259#define ARITH_GE
2260
2261#include "op_addsub.h"
2262
2263/* Halved signed arithmetic. */
2264#define ADD16(a, b, n) \
2265 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2266#define SUB16(a, b, n) \
2267 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2268#define ADD8(a, b, n) \
2269 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2270#define SUB8(a, b, n) \
2271 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2272#define PFX sh
2273
2274#include "op_addsub.h"
2275
2276/* Halved unsigned arithmetic. */
2277#define ADD16(a, b, n) \
2278 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2279#define SUB16(a, b, n) \
2280 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2281#define ADD8(a, b, n) \
2282 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2283#define SUB8(a, b, n) \
2284 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2285#define PFX uh
2286
2287#include "op_addsub.h"
2288
2289static inline uint8_t do_usad(uint8_t a, uint8_t b)
2290{
2291 if (a > b)
2292 return a - b;
2293 else
2294 return b - a;
2295}
2296
2297/* Unsigned sum of absolute byte differences. */
2298uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2299{
2300 uint32_t sum;
2301 sum = do_usad(a, b);
2302 sum += do_usad(a >> 8, b >> 8);
2303 sum += do_usad(a >> 16, b >>16);
2304 sum += do_usad(a >> 24, b >> 24);
2305 return sum;
2306}
2307
2308/* For ARMv6 SEL instruction. */
2309uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2310{
2311 uint32_t mask;
2312
2313 mask = 0;
2314 if (flags & 1)
2315 mask |= 0xff;
2316 if (flags & 2)
2317 mask |= 0xff00;
2318 if (flags & 4)
2319 mask |= 0xff0000;
2320 if (flags & 8)
2321 mask |= 0xff000000;
2322 return (a & mask) | (b & ~mask);
2323}
2324
5e3f878a
PB		 2325uint32_t HELPER(logicq_cc)(uint64_t val)
2326{
2327 return (val >> 32) | (val != 0);
2328}
4373f3ce
PB		 2329
2330/* VFP support. We follow the convention used for VFP instrunctions:
2331 Single precition routines have a "s" suffix, double precision a
2332 "d" suffix. */
2333
2334/* Convert host exception flags to vfp form. */
2335static inline int vfp_exceptbits_from_host(int host_bits)
2336{
2337 int target_bits = 0;
2338
2339 if (host_bits & float_flag_invalid)
2340 target_bits |= 1;
2341 if (host_bits & float_flag_divbyzero)
2342 target_bits |= 2;
2343 if (host_bits & float_flag_overflow)
2344 target_bits |= 4;
2345 if (host_bits & float_flag_underflow)
2346 target_bits |= 8;
2347 if (host_bits & float_flag_inexact)
2348 target_bits |= 0x10;
cecd8504
PM		 2349 if (host_bits & float_flag_input_denormal)
2350 target_bits |= 0x80;
4373f3ce
PB		 2351 return target_bits;
2352}
2353
2354uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2355{
2356 int i;
2357 uint32_t fpscr;
2358
2359 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2360 | (env->vfp.vec_len << 16)
2361 | (env->vfp.vec_stride << 20);
2362 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2363 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2364 fpscr |= vfp_exceptbits_from_host(i);
2365 return fpscr;
2366}
2367
01653295
PM		 2368uint32_t vfp_get_fpscr(CPUState *env)
2369{
2370 return HELPER(vfp_get_fpscr)(env);
2371}
2372
4373f3ce
PB		 2373/* Convert vfp exception flags to target form. */
2374static inline int vfp_exceptbits_to_host(int target_bits)
2375{
2376 int host_bits = 0;
2377
2378 if (target_bits & 1)
2379 host_bits |= float_flag_invalid;
2380 if (target_bits & 2)
2381 host_bits |= float_flag_divbyzero;
2382 if (target_bits & 4)
2383 host_bits |= float_flag_overflow;
2384 if (target_bits & 8)
2385 host_bits |= float_flag_underflow;
2386 if (target_bits & 0x10)
2387 host_bits |= float_flag_inexact;
cecd8504
PM		 2388 if (target_bits & 0x80)
2389 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2390 return host_bits;
2391}
2392
2393void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2394{
2395 int i;
2396 uint32_t changed;
2397
2398 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2399 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2400 env->vfp.vec_len = (val >> 16) & 7;
2401 env->vfp.vec_stride = (val >> 20) & 3;
2402
2403 changed ^= val;
2404 if (changed & (3 << 22)) {
2405 i = (val >> 22) & 3;
2406 switch (i) {
2407 case 0:
2408 i = float_round_nearest_even;
2409 break;
2410 case 1:
2411 i = float_round_up;
2412 break;
2413 case 2:
2414 i = float_round_down;
2415 break;
2416 case 3:
2417 i = float_round_to_zero;
2418 break;
2419 }
2420 set_float_rounding_mode(i, &env->vfp.fp_status);
2421 }
cecd8504 2422 if (changed & (1 << 24)) {
fe76d976 2423 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2424 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2425 }
5c7908ed
PB		 2426 if (changed & (1 << 25))
2427 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2428
b12c390b 2429 i = vfp_exceptbits_to_host(val);
4373f3ce 2430 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2431 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2432}
2433
01653295
PM		 2434void vfp_set_fpscr(CPUState *env, uint32_t val)
2435{
2436 HELPER(vfp_set_fpscr)(env, val);
2437}
2438
4373f3ce
PB		 2439#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2440
2441#define VFP_BINOP(name) \
2442float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2443{ \
2444 return float32_ ## name (a, b, &env->vfp.fp_status); \
2445} \
2446float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2447{ \
2448 return float64_ ## name (a, b, &env->vfp.fp_status); \
2449}
2450VFP_BINOP(add)
2451VFP_BINOP(sub)
2452VFP_BINOP(mul)
2453VFP_BINOP(div)
2454#undef VFP_BINOP
2455
2456float32 VFP_HELPER(neg, s)(float32 a)
2457{
2458 return float32_chs(a);
2459}
2460
2461float64 VFP_HELPER(neg, d)(float64 a)
2462{
66230e0d 2463 return float64_chs(a);
4373f3ce
PB		 2464}
2465
2466float32 VFP_HELPER(abs, s)(float32 a)
2467{
2468 return float32_abs(a);
2469}
2470
2471float64 VFP_HELPER(abs, d)(float64 a)
2472{
66230e0d 2473 return float64_abs(a);
4373f3ce
PB		 2474}
2475
2476float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2477{
2478 return float32_sqrt(a, &env->vfp.fp_status);
2479}
2480
2481float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2482{
2483 return float64_sqrt(a, &env->vfp.fp_status);
2484}
2485
2486/* XXX: check quiet/signaling case */
2487#define DO_VFP_cmp(p, type) \
2488void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2489{ \
2490 uint32_t flags; \
2491 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2492 case 0: flags = 0x6; break; \
2493 case -1: flags = 0x8; break; \
2494 case 1: flags = 0x2; break; \
2495 default: case 2: flags = 0x3; break; \
2496 } \
2497 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2498 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2499} \
2500void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2501{ \
2502 uint32_t flags; \
2503 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2504 case 0: flags = 0x6; break; \
2505 case -1: flags = 0x8; break; \
2506 case 1: flags = 0x2; break; \
2507 default: case 2: flags = 0x3; break; \
2508 } \
2509 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2510 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2511}
2512DO_VFP_cmp(s, float32)
2513DO_VFP_cmp(d, float64)
2514#undef DO_VFP_cmp
2515
4373f3ce 2516/* Integer to float conversion. */
622465e1 2517float32 VFP_HELPER(uito, s)(uint32_t x, CPUState *env)
4373f3ce 2518{
622465e1 2519 return uint32_to_float32(x, &env->vfp.fp_status);
4373f3ce
PB		 2520}
2521
622465e1 2522float64 VFP_HELPER(uito, d)(uint32_t x, CPUState *env)
4373f3ce 2523{
622465e1 2524 return uint32_to_float64(x, &env->vfp.fp_status);
4373f3ce
PB		 2525}
2526
622465e1 2527float32 VFP_HELPER(sito, s)(uint32_t x, CPUState *env)
4373f3ce 2528{
622465e1 2529 return int32_to_float32(x, &env->vfp.fp_status);
4373f3ce
PB		 2530}
2531
622465e1 2532float64 VFP_HELPER(sito, d)(uint32_t x, CPUState *env)
4373f3ce 2533{
622465e1 2534 return int32_to_float64(x, &env->vfp.fp_status);
4373f3ce
PB		 2535}
2536
2537/* Float to integer conversion. */
622465e1 2538uint32_t VFP_HELPER(toui, s)(float32 x, CPUState *env)
4373f3ce 2539{
09d9487f 2540 if (float32_is_any_nan(x)) {
622465e1 2541 return 0;
09d9487f 2542 }
622465e1 2543 return float32_to_uint32(x, &env->vfp.fp_status);
4373f3ce
PB		 2544}
2545
622465e1 2546uint32_t VFP_HELPER(toui, d)(float64 x, CPUState *env)
4373f3ce 2547{
09d9487f 2548 if (float64_is_any_nan(x)) {
622465e1 2549 return 0;
09d9487f 2550 }
622465e1 2551 return float64_to_uint32(x, &env->vfp.fp_status);
4373f3ce
PB		 2552}
2553
622465e1 2554uint32_t VFP_HELPER(tosi, s)(float32 x, CPUState *env)
4373f3ce 2555{
09d9487f 2556 if (float32_is_any_nan(x)) {
622465e1 2557 return 0;
09d9487f 2558 }
622465e1 2559 return float32_to_int32(x, &env->vfp.fp_status);
4373f3ce
PB		 2560}
2561
622465e1 2562uint32_t VFP_HELPER(tosi, d)(float64 x, CPUState *env)
4373f3ce 2563{
09d9487f 2564 if (float64_is_any_nan(x)) {
622465e1 2565 return 0;
09d9487f 2566 }
622465e1 2567 return float64_to_int32(x, &env->vfp.fp_status);
4373f3ce
PB		 2568}
2569
622465e1 2570uint32_t VFP_HELPER(touiz, s)(float32 x, CPUState *env)
4373f3ce 2571{
09d9487f 2572 if (float32_is_any_nan(x)) {
622465e1 2573 return 0;
09d9487f 2574 }
622465e1 2575 return float32_to_uint32_round_to_zero(x, &env->vfp.fp_status);
4373f3ce
PB		 2576}
2577
622465e1 2578uint32_t VFP_HELPER(touiz, d)(float64 x, CPUState *env)
4373f3ce 2579{
09d9487f 2580 if (float64_is_any_nan(x)) {
622465e1 2581 return 0;
09d9487f 2582 }
622465e1 2583 return float64_to_uint32_round_to_zero(x, &env->vfp.fp_status);
4373f3ce
PB		 2584}
2585
622465e1 2586uint32_t VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
4373f3ce 2587{
09d9487f 2588 if (float32_is_any_nan(x)) {
622465e1 2589 return 0;
09d9487f 2590 }
622465e1 2591 return float32_to_int32_round_to_zero(x, &env->vfp.fp_status);
4373f3ce
PB		 2592}
2593
622465e1 2594uint32_t VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
4373f3ce 2595{
09d9487f 2596 if (float64_is_any_nan(x)) {
622465e1 2597 return 0;
09d9487f 2598 }
622465e1 2599 return float64_to_int32_round_to_zero(x, &env->vfp.fp_status);
4373f3ce
PB		 2600}
2601
2602/* floating point conversion */
2603float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2604{
2d627737
PM		 2605 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2606 /* ARM requires that S<->D conversion of any kind of NaN generates
2607 * a quiet NaN by forcing the most significant frac bit to 1.
2608 */
2609 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2610}
2611
2612float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2613{
2d627737
PM		 2614 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2615 /* ARM requires that S<->D conversion of any kind of NaN generates
2616 * a quiet NaN by forcing the most significant frac bit to 1.
2617 */
2618 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2619}
2620
2621/* VFP3 fixed point conversion. */
622465e1
PM		 2622#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2623float##fsz VFP_HELPER(name##to, p)(uint##fsz##_t x, uint32_t shift, \
2624 CPUState *env) \
4373f3ce 2625{ \
622465e1
PM		 2626 float##fsz tmp; \
2627 tmp = sign##int32_to_##float##fsz ((itype##_t)x, &env->vfp.fp_status); \
2628 return float##fsz##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
4373f3ce 2629} \
622465e1
PM		 2630uint##fsz##_t VFP_HELPER(to##name, p)(float##fsz x, uint32_t shift, \
2631 CPUState *env) \
4373f3ce 2632{ \
622465e1
PM		 2633 float##fsz tmp; \
2634 if (float##fsz##_is_any_nan(x)) { \
2635 return 0; \
09d9487f 2636 } \
622465e1
PM		 2637 tmp = float##fsz##_scalbn(x, shift, &env->vfp.fp_status); \
2638 return float##fsz##_to_##itype##_round_to_zero(tmp, &env->vfp.fp_status); \
2639}
2640
2641VFP_CONV_FIX(sh, d, 64, int16, )
2642VFP_CONV_FIX(sl, d, 64, int32, )
2643VFP_CONV_FIX(uh, d, 64, uint16, u)
2644VFP_CONV_FIX(ul, d, 64, uint32, u)
2645VFP_CONV_FIX(sh, s, 32, int16, )
2646VFP_CONV_FIX(sl, s, 32, int32, )
2647VFP_CONV_FIX(uh, s, 32, uint16, u)
2648VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2649#undef VFP_CONV_FIX
2650
60011498 2651/* Half precision conversions. */
2d981da7 2652static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
60011498 2653{
60011498 2654 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2655 float32 r = float16_to_float32(make_float16(a), ieee, s);
2656 if (ieee) {
2657 return float32_maybe_silence_nan(r);
2658 }
2659 return r;
60011498
PB		 2660}
2661
2d981da7 2662static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
60011498 2663{
60011498 2664 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2665 float16 r = float32_to_float16(a, ieee, s);
2666 if (ieee) {
2667 r = float16_maybe_silence_nan(r);
2668 }
2669 return float16_val(r);
60011498
PB		 2670}
2671
2d981da7
PM		 2672float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2673{
2674 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2675}
2676
2677uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
2678{
2679 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2680}
2681
2682float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
2683{
2684 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2685}
2686
2687uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
2688{
2689 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2690}
2691
dda3ec49 2692#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2693#define float32_three make_float32(0x40400000)
2694#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2695
4373f3ce
PB		 2696float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2697{
dda3ec49
PM		 2698 float_status *s = &env->vfp.standard_fp_status;
2699 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2700 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
2701 return float32_two;
2702 }
2703 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2704}
2705
2706float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2707{
71826966 2708 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2709 float32 product;
2710 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2711 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6aae3df1 2712 return float32_one_point_five;
9ea62f57 2713 }
6aae3df1
PM		 2714 product = float32_mul(a, b, s);
2715 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2716}
2717
8f8e3aa4
PB		 2718/* NEON helpers. */
2719
56bf4fe2
CL		 2720/* Constants 256 and 512 are used in some helpers; we avoid relying on
2721 * int->float conversions at run-time. */
2722#define float64_256 make_float64(0x4070000000000000LL)
2723#define float64_512 make_float64(0x4080000000000000LL)
2724
fe0e4872
CL		 2725/* The algorithm that must be used to calculate the estimate
2726 * is specified by the ARM ARM.
2727 */
2728static float64 recip_estimate(float64 a, CPUState *env)
2729{
2730 float_status *s = &env->vfp.standard_fp_status;
2731 /* q = (int)(a * 512.0) */
2732 float64 q = float64_mul(float64_512, a, s);
2733 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2734
2735 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2736 q = int64_to_float64(q_int, s);
2737 q = float64_add(q, float64_half, s);
2738 q = float64_div(q, float64_512, s);
2739 q = float64_div(float64_one, q, s);
2740
2741 /* s = (int)(256.0 * r + 0.5) */
2742 q = float64_mul(q, float64_256, s);
2743 q = float64_add(q, float64_half, s);
2744 q_int = float64_to_int64_round_to_zero(q, s);
2745
2746 /* return (double)s / 256.0 */
2747 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2748}
2749
4373f3ce
PB		 2750float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2751{
fe0e4872
CL		 2752 float_status *s = &env->vfp.standard_fp_status;
2753 float64 f64;
2754 uint32_t val32 = float32_val(a);
2755
2756 int result_exp;
2757 int a_exp = (val32 & 0x7f800000) >> 23;
2758 int sign = val32 & 0x80000000;
2759
2760 if (float32_is_any_nan(a)) {
2761 if (float32_is_signaling_nan(a)) {
2762 float_raise(float_flag_invalid, s);
2763 }
2764 return float32_default_nan;
2765 } else if (float32_is_infinity(a)) {
2766 return float32_set_sign(float32_zero, float32_is_neg(a));
2767 } else if (float32_is_zero_or_denormal(a)) {
2768 float_raise(float_flag_divbyzero, s);
2769 return float32_set_sign(float32_infinity, float32_is_neg(a));
2770 } else if (a_exp >= 253) {
2771 float_raise(float_flag_underflow, s);
2772 return float32_set_sign(float32_zero, float32_is_neg(a));
2773 }
2774
2775 f64 = make_float64((0x3feULL << 52)
2776 | ((int64_t)(val32 & 0x7fffff) << 29));
2777
2778 result_exp = 253 - a_exp;
2779
2780 f64 = recip_estimate(f64, env);
2781
2782 val32 = sign
2783 | ((result_exp & 0xff) << 23)
2784 | ((float64_val(f64) >> 29) & 0x7fffff);
2785 return make_float32(val32);
4373f3ce
PB		 2786}
2787
e07be5d2
CL		 2788/* The algorithm that must be used to calculate the estimate
2789 * is specified by the ARM ARM.
2790 */
2791static float64 recip_sqrt_estimate(float64 a, CPUState *env)
2792{
2793 float_status *s = &env->vfp.standard_fp_status;
2794 float64 q;
2795 int64_t q_int;
2796
2797 if (float64_lt(a, float64_half, s)) {
2798 /* range 0.25 <= a < 0.5 */
2799
2800 /* a in units of 1/512 rounded down */
2801 /* q0 = (int)(a * 512.0); */
2802 q = float64_mul(float64_512, a, s);
2803 q_int = float64_to_int64_round_to_zero(q, s);
2804
2805 /* reciprocal root r */
2806 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2807 q = int64_to_float64(q_int, s);
2808 q = float64_add(q, float64_half, s);
2809 q = float64_div(q, float64_512, s);
2810 q = float64_sqrt(q, s);
2811 q = float64_div(float64_one, q, s);
2812 } else {
2813 /* range 0.5 <= a < 1.0 */
2814
2815 /* a in units of 1/256 rounded down */
2816 /* q1 = (int)(a * 256.0); */
2817 q = float64_mul(float64_256, a, s);
2818 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2819
2820 /* reciprocal root r */
2821 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2822 q = int64_to_float64(q_int, s);
2823 q = float64_add(q, float64_half, s);
2824 q = float64_div(q, float64_256, s);
2825 q = float64_sqrt(q, s);
2826 q = float64_div(float64_one, q, s);
2827 }
2828 /* r in units of 1/256 rounded to nearest */
2829 /* s = (int)(256.0 * r + 0.5); */
2830
2831 q = float64_mul(q, float64_256,s );
2832 q = float64_add(q, float64_half, s);
2833 q_int = float64_to_int64_round_to_zero(q, s);
2834
2835 /* return (double)s / 256.0;*/
2836 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2837}
2838
4373f3ce
PB		 2839float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2840{
e07be5d2
CL		 2841 float_status *s = &env->vfp.standard_fp_status;
2842 int result_exp;
2843 float64 f64;
2844 uint32_t val;
2845 uint64_t val64;
2846
2847 val = float32_val(a);
2848
2849 if (float32_is_any_nan(a)) {
2850 if (float32_is_signaling_nan(a)) {
2851 float_raise(float_flag_invalid, s);
2852 }
2853 return float32_default_nan;
2854 } else if (float32_is_zero_or_denormal(a)) {
2855 float_raise(float_flag_divbyzero, s);
2856 return float32_set_sign(float32_infinity, float32_is_neg(a));
2857 } else if (float32_is_neg(a)) {
2858 float_raise(float_flag_invalid, s);
2859 return float32_default_nan;
2860 } else if (float32_is_infinity(a)) {
2861 return float32_zero;
2862 }
2863
2864 /* Normalize to a double-precision value between 0.25 and 1.0,
2865 * preserving the parity of the exponent. */
2866 if ((val & 0x800000) == 0) {
2867 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2868 | (0x3feULL << 52)
2869 | ((uint64_t)(val & 0x7fffff) << 29));
2870 } else {
2871 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
2872 | (0x3fdULL << 52)
2873 | ((uint64_t)(val & 0x7fffff) << 29));
2874 }
2875
2876 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
2877
2878 f64 = recip_sqrt_estimate(f64, env);
2879
2880 val64 = float64_val(f64);
2881
2882 val = ((val64 >> 63) & 0x80000000)
2883 | ((result_exp & 0xff) << 23)
2884 | ((val64 >> 29) & 0x7fffff);
2885 return make_float32(val);
4373f3ce
PB		 2886}
2887
2888uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2889{
fe0e4872
CL		 2890 float64 f64;
2891
2892 if ((a & 0x80000000) == 0) {
2893 return 0xffffffff;
2894 }
2895
2896 f64 = make_float64((0x3feULL << 52)
2897 | ((int64_t)(a & 0x7fffffff) << 21));
2898
2899 f64 = recip_estimate (f64, env);
2900
2901 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 2902}
2903
2904uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2905{
e07be5d2
CL		 2906 float64 f64;
2907
2908 if ((a & 0xc0000000) == 0) {
2909 return 0xffffffff;
2910 }
2911
2912 if (a & 0x80000000) {
2913 f64 = make_float64((0x3feULL << 52)
2914 | ((uint64_t)(a & 0x7fffffff) << 21));
2915 } else { /* bits 31-30 == '01' */
2916 f64 = make_float64((0x3fdULL << 52)
2917 | ((uint64_t)(a & 0x3fffffff) << 22));
2918 }
2919
2920 f64 = recip_sqrt_estimate(f64, env);
2921
2922 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 2923}
fe1479c3
PB		 2924
2925void HELPER(set_teecr)(CPUState *env, uint32_t val)
2926{
2927 val &= 1;
2928 if (env->teecr != val) {
2929 env->teecr = val;
2930 tb_flush(env);
2931 }
2932}
Qemu copy for testing