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81fdc5f8 TS |
1 | /* |
2 | * CRIS helper routines | |
3 | * | |
4 | * Copyright (c) 2007 AXIS Communications | |
5 | * Written by Edgar E. Iglesias | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
81fdc5f8 TS |
19 | */ |
20 | ||
3e457172 BS |
21 | #include "cpu.h" |
22 | #include "dyngen-exec.h" | |
786c02f1 | 23 | #include "mmu.h" |
30abcfc7 | 24 | #include "helper.h" |
c38ac98d | 25 | #include "host-utils.h" |
81fdc5f8 | 26 | |
d12d51d5 AL |
27 | //#define CRIS_OP_HELPER_DEBUG |
28 | ||
29 | ||
30 | #ifdef CRIS_OP_HELPER_DEBUG | |
31 | #define D(x) x | |
93fcfe39 | 32 | #define D_LOG(...) qemu_log(__VA__ARGS__) |
d12d51d5 | 33 | #else |
e2eef170 | 34 | #define D(x) |
d12d51d5 AL |
35 | #define D_LOG(...) do { } while (0) |
36 | #endif | |
e2eef170 PB |
37 | |
38 | #if !defined(CONFIG_USER_ONLY) | |
3e457172 | 39 | #include "softmmu_exec.h" |
e2eef170 | 40 | |
81fdc5f8 | 41 | #define MMUSUFFIX _mmu |
81fdc5f8 TS |
42 | |
43 | #define SHIFT 0 | |
44 | #include "softmmu_template.h" | |
45 | ||
46 | #define SHIFT 1 | |
47 | #include "softmmu_template.h" | |
48 | ||
49 | #define SHIFT 2 | |
50 | #include "softmmu_template.h" | |
51 | ||
52 | #define SHIFT 3 | |
53 | #include "softmmu_template.h" | |
54 | ||
55 | /* Try to fill the TLB and return an exception if error. If retaddr is | |
56 | NULL, it means that the function was called in C code (i.e. not | |
57 | from generated code or from helper.c) */ | |
58 | /* XXX: fix it to restore all registers */ | |
a1170bfd | 59 | void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 60 | uintptr_t retaddr) |
81fdc5f8 TS |
61 | { |
62 | TranslationBlock *tb; | |
a1170bfd | 63 | CPUCRISState *saved_env; |
81fdc5f8 TS |
64 | int ret; |
65 | ||
81fdc5f8 | 66 | saved_env = env; |
bccd9ec5 | 67 | env = env1; |
b41f7df0 | 68 | |
20503968 BS |
69 | D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__, |
70 | env->pc, env->debug1, (void *)retaddr); | |
97b348e7 | 71 | ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx); |
551bd27f | 72 | if (unlikely(ret)) { |
81fdc5f8 TS |
73 | if (retaddr) { |
74 | /* now we have a real cpu fault */ | |
20503968 | 75 | tb = tb_find_pc(retaddr); |
81fdc5f8 TS |
76 | if (tb) { |
77 | /* the PC is inside the translated code. It means that we have | |
78 | a virtual CPU fault */ | |
20503968 | 79 | cpu_restore_state(tb, env, retaddr); |
30abcfc7 EI |
80 | |
81 | /* Evaluate flags after retranslation. */ | |
febc9920 | 82 | helper_top_evaluate_flags(env); |
81fdc5f8 TS |
83 | } |
84 | } | |
1162c041 | 85 | cpu_loop_exit(env); |
81fdc5f8 TS |
86 | } |
87 | env = saved_env; | |
88 | } | |
89 | ||
e2eef170 PB |
90 | #endif |
91 | ||
febc9920 | 92 | void helper_raise_exception(CPUCRISState *env, uint32_t index) |
786c02f1 | 93 | { |
dceaf394 | 94 | env->exception_index = index; |
1162c041 | 95 | cpu_loop_exit(env); |
786c02f1 EI |
96 | } |
97 | ||
febc9920 | 98 | void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) |
cf1d97f0 EI |
99 | { |
100 | #if !defined(CONFIG_USER_ONLY) | |
28de16da EI |
101 | pid &= 0xff; |
102 | if (pid != (env->pregs[PR_PID] & 0xff)) | |
103 | cris_mmu_flush_pid(env, env->pregs[PR_PID]); | |
cf1d97f0 EI |
104 | #endif |
105 | } | |
106 | ||
febc9920 | 107 | void helper_spc_write(CPUCRISState *env, uint32_t new_spc) |
a1aebcb8 EI |
108 | { |
109 | #if !defined(CONFIG_USER_ONLY) | |
110 | tlb_flush_page(env, env->pregs[PR_SPC]); | |
111 | tlb_flush_page(env, new_spc); | |
112 | #endif | |
113 | } | |
114 | ||
30abcfc7 | 115 | void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2) |
b41f7df0 | 116 | { |
93fcfe39 | 117 | qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1); |
b41f7df0 EI |
118 | } |
119 | ||
cf1d97f0 EI |
120 | /* Used by the tlb decoder. */ |
121 | #define EXTRACT_FIELD(src, start, end) \ | |
122 | (((src) >> start) & ((1 << (end - start + 1)) - 1)) | |
123 | ||
febc9920 | 124 | void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) |
dceaf394 EI |
125 | { |
126 | uint32_t srs; | |
127 | srs = env->pregs[PR_SRS]; | |
128 | srs &= 3; | |
129 | env->sregs[srs][sreg] = env->regs[reg]; | |
130 | ||
131 | #if !defined(CONFIG_USER_ONLY) | |
132 | if (srs == 1 || srs == 2) { | |
133 | if (sreg == 6) { | |
134 | /* Writes to tlb-hi write to mm_cause as a side | |
135 | effect. */ | |
6913ba56 EI |
136 | env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg]; |
137 | env->sregs[SFR_R_MM_CAUSE] = env->regs[reg]; | |
dceaf394 EI |
138 | } |
139 | else if (sreg == 5) { | |
140 | uint32_t set; | |
141 | uint32_t idx; | |
142 | uint32_t lo, hi; | |
143 | uint32_t vaddr; | |
cf1d97f0 | 144 | int tlb_v; |
dceaf394 EI |
145 | |
146 | idx = set = env->sregs[SFR_RW_MM_TLB_SEL]; | |
147 | set >>= 4; | |
148 | set &= 3; | |
149 | ||
150 | idx &= 15; | |
151 | /* We've just made a write to tlb_lo. */ | |
152 | lo = env->sregs[SFR_RW_MM_TLB_LO]; | |
153 | /* Writes are done via r_mm_cause. */ | |
154 | hi = env->sregs[SFR_R_MM_CAUSE]; | |
cf1d97f0 EI |
155 | |
156 | vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi, | |
157 | 13, 31); | |
158 | vaddr <<= TARGET_PAGE_BITS; | |
159 | tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo, | |
160 | 3, 3); | |
dceaf394 EI |
161 | env->tlbsets[srs - 1][set][idx].lo = lo; |
162 | env->tlbsets[srs - 1][set][idx].hi = hi; | |
cf1d97f0 | 163 | |
d12d51d5 AL |
164 | D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", |
165 | vaddr, tlb_v, env->pc); | |
3e18c6bf EI |
166 | if (tlb_v) { |
167 | tlb_flush_page(env, vaddr); | |
168 | } | |
dceaf394 EI |
169 | } |
170 | } | |
171 | #endif | |
172 | } | |
173 | ||
febc9920 | 174 | void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg) |
dceaf394 EI |
175 | { |
176 | uint32_t srs; | |
177 | env->pregs[PR_SRS] &= 3; | |
178 | srs = env->pregs[PR_SRS]; | |
179 | ||
180 | #if !defined(CONFIG_USER_ONLY) | |
181 | if (srs == 1 || srs == 2) | |
182 | { | |
183 | uint32_t set; | |
184 | uint32_t idx; | |
185 | uint32_t lo, hi; | |
186 | ||
187 | idx = set = env->sregs[SFR_RW_MM_TLB_SEL]; | |
188 | set >>= 4; | |
189 | set &= 3; | |
190 | idx &= 15; | |
191 | ||
192 | /* Update the mirror regs. */ | |
193 | hi = env->tlbsets[srs - 1][set][idx].hi; | |
194 | lo = env->tlbsets[srs - 1][set][idx].lo; | |
195 | env->sregs[SFR_RW_MM_TLB_HI] = hi; | |
196 | env->sregs[SFR_RW_MM_TLB_LO] = lo; | |
197 | } | |
198 | #endif | |
199 | env->regs[reg] = env->sregs[srs][sreg]; | |
dceaf394 EI |
200 | } |
201 | ||
a1170bfd | 202 | static void cris_ccs_rshift(CPUCRISState *env) |
dceaf394 EI |
203 | { |
204 | uint32_t ccs; | |
205 | ||
206 | /* Apply the ccs shift. */ | |
207 | ccs = env->pregs[PR_CCS]; | |
208 | ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10); | |
209 | if (ccs & U_FLAG) | |
210 | { | |
211 | /* Enter user mode. */ | |
212 | env->ksp = env->regs[R_SP]; | |
213 | env->regs[R_SP] = env->pregs[PR_USP]; | |
214 | } | |
215 | ||
216 | env->pregs[PR_CCS] = ccs; | |
217 | } | |
218 | ||
febc9920 | 219 | void helper_rfe(CPUCRISState *env) |
b41f7df0 | 220 | { |
bf443337 EI |
221 | int rflag = env->pregs[PR_CCS] & R_FLAG; |
222 | ||
d12d51d5 | 223 | D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", |
b41f7df0 EI |
224 | env->pregs[PR_ERP], env->pregs[PR_PID], |
225 | env->pregs[PR_CCS], | |
d12d51d5 | 226 | env->btarget); |
dceaf394 EI |
227 | |
228 | cris_ccs_rshift(env); | |
229 | ||
230 | /* RFE sets the P_FLAG only if the R_FLAG is not set. */ | |
bf443337 | 231 | if (!rflag) |
dceaf394 | 232 | env->pregs[PR_CCS] |= P_FLAG; |
b41f7df0 EI |
233 | } |
234 | ||
febc9920 | 235 | void helper_rfn(CPUCRISState *env) |
5bf8f1ab EI |
236 | { |
237 | int rflag = env->pregs[PR_CCS] & R_FLAG; | |
238 | ||
d12d51d5 | 239 | D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", |
5bf8f1ab EI |
240 | env->pregs[PR_ERP], env->pregs[PR_PID], |
241 | env->pregs[PR_CCS], | |
d12d51d5 | 242 | env->btarget); |
5bf8f1ab EI |
243 | |
244 | cris_ccs_rshift(env); | |
245 | ||
246 | /* Set the P_FLAG only if the R_FLAG is not set. */ | |
247 | if (!rflag) | |
248 | env->pregs[PR_CCS] |= P_FLAG; | |
249 | ||
8219314b LP |
250 | /* Always set the M flag. */ |
251 | env->pregs[PR_CCS] |= M_FLAG_V32; | |
5bf8f1ab EI |
252 | } |
253 | ||
c38ac98d EI |
254 | uint32_t helper_lz(uint32_t t0) |
255 | { | |
256 | return clz32(t0); | |
257 | } | |
258 | ||
febc9920 | 259 | uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs) |
abd5c94e EI |
260 | { |
261 | /* FIXME: clean this up. */ | |
262 | ||
263 | /* des ref: | |
264 | The N flag is set according to the selected bit in the dest reg. | |
265 | The Z flag is set if the selected bit and all bits to the right are | |
266 | zero. | |
267 | The X flag is cleared. | |
268 | Other flags are left untouched. | |
269 | The destination reg is not affected.*/ | |
270 | unsigned int fz, sbit, bset, mask, masked_t0; | |
271 | ||
272 | sbit = t1 & 31; | |
273 | bset = !!(t0 & (1 << sbit)); | |
274 | mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1; | |
275 | masked_t0 = t0 & mask; | |
276 | fz = !(masked_t0 | bset); | |
277 | ||
278 | /* Clear the X, N and Z flags. */ | |
279 | ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG); | |
95475216 EI |
280 | if (env->pregs[PR_VR] < 32) |
281 | ccs &= ~(V_FLAG | C_FLAG); | |
abd5c94e EI |
282 | /* Set the N and Z flags accordingly. */ |
283 | ccs |= (bset << 3) | (fz << 2); | |
284 | return ccs; | |
285 | } | |
286 | ||
febc9920 AJ |
287 | static inline uint32_t evaluate_flags_writeback(CPUCRISState *env, |
288 | uint32_t flags, uint32_t ccs) | |
b41f7df0 | 289 | { |
a8cf66bb | 290 | unsigned int x, z, mask; |
b41f7df0 EI |
291 | |
292 | /* Extended arithmetics, leave the z flag alone. */ | |
30abcfc7 | 293 | x = env->cc_x; |
a8cf66bb EI |
294 | mask = env->cc_mask | X_FLAG; |
295 | if (x) { | |
296 | z = flags & Z_FLAG; | |
297 | mask = mask & ~z; | |
298 | } | |
299 | flags &= mask; | |
b41f7df0 EI |
300 | |
301 | /* all insn clear the x-flag except setf or clrf. */ | |
6231868b EI |
302 | ccs &= ~mask; |
303 | ccs |= flags; | |
304 | return ccs; | |
b41f7df0 EI |
305 | } |
306 | ||
febc9920 AJ |
307 | uint32_t helper_evaluate_flags_muls(CPUCRISState *env, |
308 | uint32_t ccs, uint32_t res, uint32_t mof) | |
b41f7df0 | 309 | { |
b41f7df0 | 310 | uint32_t flags = 0; |
dceaf394 | 311 | int64_t tmp; |
b41f7df0 EI |
312 | int dneg; |
313 | ||
b41f7df0 EI |
314 | dneg = ((int32_t)res) < 0; |
315 | ||
dceaf394 EI |
316 | tmp = mof; |
317 | tmp <<= 32; | |
318 | tmp |= res; | |
b41f7df0 EI |
319 | if (tmp == 0) |
320 | flags |= Z_FLAG; | |
321 | else if (tmp < 0) | |
322 | flags |= N_FLAG; | |
323 | if ((dneg && mof != -1) | |
324 | || (!dneg && mof != 0)) | |
325 | flags |= V_FLAG; | |
febc9920 | 326 | return evaluate_flags_writeback(env, flags, ccs); |
b41f7df0 EI |
327 | } |
328 | ||
febc9920 AJ |
329 | uint32_t helper_evaluate_flags_mulu(CPUCRISState *env, |
330 | uint32_t ccs, uint32_t res, uint32_t mof) | |
b41f7df0 | 331 | { |
b41f7df0 | 332 | uint32_t flags = 0; |
dceaf394 | 333 | uint64_t tmp; |
b41f7df0 | 334 | |
dceaf394 EI |
335 | tmp = mof; |
336 | tmp <<= 32; | |
337 | tmp |= res; | |
b41f7df0 EI |
338 | if (tmp == 0) |
339 | flags |= Z_FLAG; | |
340 | else if (tmp >> 63) | |
341 | flags |= N_FLAG; | |
342 | if (mof) | |
343 | flags |= V_FLAG; | |
344 | ||
febc9920 | 345 | return evaluate_flags_writeback(env, flags, ccs); |
b41f7df0 EI |
346 | } |
347 | ||
febc9920 | 348 | uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs, |
6231868b | 349 | uint32_t src, uint32_t dst, uint32_t res) |
b41f7df0 | 350 | { |
b41f7df0 EI |
351 | uint32_t flags = 0; |
352 | ||
6231868b EI |
353 | src = src & 0x80000000; |
354 | dst = dst & 0x80000000; | |
b41f7df0 EI |
355 | |
356 | if ((res & 0x80000000L) != 0L) | |
357 | { | |
358 | flags |= N_FLAG; | |
a8cf66bb | 359 | if (!src && !dst) |
b41f7df0 | 360 | flags |= V_FLAG; |
a8cf66bb | 361 | else if (src & dst) |
b41f7df0 | 362 | flags |= R_FLAG; |
b41f7df0 EI |
363 | } |
364 | else | |
365 | { | |
366 | if (res == 0L) | |
367 | flags |= Z_FLAG; | |
a8cf66bb | 368 | if (src & dst) |
b41f7df0 | 369 | flags |= V_FLAG; |
a8cf66bb | 370 | if (dst | src) |
b41f7df0 EI |
371 | flags |= R_FLAG; |
372 | } | |
373 | ||
febc9920 | 374 | return evaluate_flags_writeback(env, flags, ccs); |
b41f7df0 EI |
375 | } |
376 | ||
febc9920 | 377 | uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs, |
6231868b | 378 | uint32_t src, uint32_t dst, uint32_t res) |
b41f7df0 | 379 | { |
b41f7df0 EI |
380 | uint32_t flags = 0; |
381 | ||
6231868b EI |
382 | src = src & 0x80000000; |
383 | dst = dst & 0x80000000; | |
30abcfc7 | 384 | |
a8cf66bb | 385 | if ((res & 0x80000000L) != 0L) |
30abcfc7 | 386 | { |
a8cf66bb EI |
387 | flags |= N_FLAG; |
388 | if (!src && !dst) | |
389 | flags |= V_FLAG; | |
390 | else if (src & dst) | |
391 | flags |= C_FLAG; | |
392 | } | |
393 | else | |
394 | { | |
395 | if (res == 0L) | |
396 | flags |= Z_FLAG; | |
397 | if (src & dst) | |
398 | flags |= V_FLAG; | |
399 | if (dst | src) | |
400 | flags |= C_FLAG; | |
30abcfc7 EI |
401 | } |
402 | ||
febc9920 | 403 | return evaluate_flags_writeback(env, flags, ccs); |
a8cf66bb EI |
404 | } |
405 | ||
febc9920 | 406 | uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs, |
6231868b | 407 | uint32_t src, uint32_t dst, uint32_t res) |
a8cf66bb | 408 | { |
a8cf66bb EI |
409 | uint32_t flags = 0; |
410 | ||
6231868b EI |
411 | src = (~src) & 0x80000000; |
412 | dst = dst & 0x80000000; | |
b41f7df0 EI |
413 | |
414 | if ((res & 0x80000000L) != 0L) | |
415 | { | |
416 | flags |= N_FLAG; | |
a8cf66bb | 417 | if (!src && !dst) |
b41f7df0 | 418 | flags |= V_FLAG; |
a8cf66bb | 419 | else if (src & dst) |
b41f7df0 | 420 | flags |= C_FLAG; |
b41f7df0 EI |
421 | } |
422 | else | |
423 | { | |
424 | if (res == 0L) | |
425 | flags |= Z_FLAG; | |
a8cf66bb | 426 | if (src & dst) |
b41f7df0 | 427 | flags |= V_FLAG; |
a8cf66bb | 428 | if (dst | src) |
b41f7df0 EI |
429 | flags |= C_FLAG; |
430 | } | |
431 | ||
a8cf66bb | 432 | flags ^= C_FLAG; |
febc9920 | 433 | return evaluate_flags_writeback(env, flags, ccs); |
b41f7df0 EI |
434 | } |
435 | ||
febc9920 AJ |
436 | uint32_t helper_evaluate_flags_move_4(CPUCRISState *env, |
437 | uint32_t ccs, uint32_t res) | |
b41f7df0 | 438 | { |
b41f7df0 EI |
439 | uint32_t flags = 0; |
440 | ||
b41f7df0 EI |
441 | if ((int32_t)res < 0) |
442 | flags |= N_FLAG; | |
443 | else if (res == 0L) | |
444 | flags |= Z_FLAG; | |
445 | ||
febc9920 | 446 | return evaluate_flags_writeback(env, flags, ccs); |
b41f7df0 | 447 | } |
febc9920 AJ |
448 | uint32_t helper_evaluate_flags_move_2(CPUCRISState *env, |
449 | uint32_t ccs, uint32_t res) | |
b41f7df0 | 450 | { |
b41f7df0 | 451 | uint32_t flags = 0; |
b41f7df0 EI |
452 | |
453 | if ((int16_t)res < 0L) | |
454 | flags |= N_FLAG; | |
455 | else if (res == 0) | |
456 | flags |= Z_FLAG; | |
457 | ||
febc9920 | 458 | return evaluate_flags_writeback(env, flags, ccs); |
b41f7df0 EI |
459 | } |
460 | ||
461 | /* TODO: This is expensive. We could split things up and only evaluate part of | |
462 | CCR on a need to know basis. For now, we simply re-evaluate everything. */ | |
febc9920 | 463 | void helper_evaluate_flags(CPUCRISState *env) |
b41f7df0 | 464 | { |
6231868b | 465 | uint32_t src, dst, res; |
b41f7df0 EI |
466 | uint32_t flags = 0; |
467 | ||
468 | src = env->cc_src; | |
469 | dst = env->cc_dest; | |
470 | res = env->cc_result; | |
471 | ||
30abcfc7 EI |
472 | if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) |
473 | src = ~src; | |
b41f7df0 EI |
474 | |
475 | /* Now, evaluate the flags. This stuff is based on | |
476 | Per Zander's CRISv10 simulator. */ | |
477 | switch (env->cc_size) | |
478 | { | |
479 | case 1: | |
480 | if ((res & 0x80L) != 0L) | |
481 | { | |
482 | flags |= N_FLAG; | |
483 | if (((src & 0x80L) == 0L) | |
484 | && ((dst & 0x80L) == 0L)) | |
485 | { | |
486 | flags |= V_FLAG; | |
487 | } | |
488 | else if (((src & 0x80L) != 0L) | |
489 | && ((dst & 0x80L) != 0L)) | |
490 | { | |
491 | flags |= C_FLAG; | |
492 | } | |
493 | } | |
494 | else | |
495 | { | |
496 | if ((res & 0xFFL) == 0L) | |
497 | { | |
498 | flags |= Z_FLAG; | |
499 | } | |
500 | if (((src & 0x80L) != 0L) | |
501 | && ((dst & 0x80L) != 0L)) | |
502 | { | |
503 | flags |= V_FLAG; | |
504 | } | |
505 | if ((dst & 0x80L) != 0L | |
506 | || (src & 0x80L) != 0L) | |
507 | { | |
508 | flags |= C_FLAG; | |
509 | } | |
510 | } | |
511 | break; | |
512 | case 2: | |
513 | if ((res & 0x8000L) != 0L) | |
514 | { | |
515 | flags |= N_FLAG; | |
516 | if (((src & 0x8000L) == 0L) | |
517 | && ((dst & 0x8000L) == 0L)) | |
518 | { | |
519 | flags |= V_FLAG; | |
520 | } | |
521 | else if (((src & 0x8000L) != 0L) | |
522 | && ((dst & 0x8000L) != 0L)) | |
523 | { | |
524 | flags |= C_FLAG; | |
525 | } | |
526 | } | |
527 | else | |
528 | { | |
529 | if ((res & 0xFFFFL) == 0L) | |
530 | { | |
531 | flags |= Z_FLAG; | |
532 | } | |
533 | if (((src & 0x8000L) != 0L) | |
534 | && ((dst & 0x8000L) != 0L)) | |
535 | { | |
536 | flags |= V_FLAG; | |
537 | } | |
538 | if ((dst & 0x8000L) != 0L | |
539 | || (src & 0x8000L) != 0L) | |
540 | { | |
541 | flags |= C_FLAG; | |
542 | } | |
543 | } | |
544 | break; | |
545 | case 4: | |
546 | if ((res & 0x80000000L) != 0L) | |
547 | { | |
548 | flags |= N_FLAG; | |
549 | if (((src & 0x80000000L) == 0L) | |
550 | && ((dst & 0x80000000L) == 0L)) | |
551 | { | |
552 | flags |= V_FLAG; | |
553 | } | |
554 | else if (((src & 0x80000000L) != 0L) && | |
555 | ((dst & 0x80000000L) != 0L)) | |
556 | { | |
557 | flags |= C_FLAG; | |
558 | } | |
559 | } | |
560 | else | |
561 | { | |
562 | if (res == 0L) | |
563 | flags |= Z_FLAG; | |
564 | if (((src & 0x80000000L) != 0L) | |
565 | && ((dst & 0x80000000L) != 0L)) | |
566 | flags |= V_FLAG; | |
567 | if ((dst & 0x80000000L) != 0L | |
568 | || (src & 0x80000000L) != 0L) | |
569 | flags |= C_FLAG; | |
570 | } | |
571 | break; | |
572 | default: | |
573 | break; | |
574 | } | |
575 | ||
6231868b | 576 | if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) |
b41f7df0 | 577 | flags ^= C_FLAG; |
6231868b | 578 | |
febc9920 AJ |
579 | env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags, |
580 | env->pregs[PR_CCS]); | |
b41f7df0 | 581 | } |
30abcfc7 | 582 | |
febc9920 | 583 | void helper_top_evaluate_flags(CPUCRISState *env) |
30abcfc7 EI |
584 | { |
585 | switch (env->cc_op) | |
586 | { | |
587 | case CC_OP_MCP: | |
febc9920 | 588 | env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env, |
6231868b EI |
589 | env->pregs[PR_CCS], env->cc_src, |
590 | env->cc_dest, env->cc_result); | |
30abcfc7 EI |
591 | break; |
592 | case CC_OP_MULS: | |
febc9920 | 593 | env->pregs[PR_CCS] = helper_evaluate_flags_muls(env, |
6231868b EI |
594 | env->pregs[PR_CCS], env->cc_result, |
595 | env->pregs[PR_MOF]); | |
30abcfc7 EI |
596 | break; |
597 | case CC_OP_MULU: | |
febc9920 | 598 | env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env, |
6231868b EI |
599 | env->pregs[PR_CCS], env->cc_result, |
600 | env->pregs[PR_MOF]); | |
30abcfc7 EI |
601 | break; |
602 | case CC_OP_MOVE: | |
603 | case CC_OP_AND: | |
604 | case CC_OP_OR: | |
605 | case CC_OP_XOR: | |
606 | case CC_OP_ASR: | |
607 | case CC_OP_LSR: | |
608 | case CC_OP_LSL: | |
6231868b EI |
609 | switch (env->cc_size) |
610 | { | |
611 | case 4: | |
612 | env->pregs[PR_CCS] = | |
febc9920 | 613 | helper_evaluate_flags_move_4(env, |
6231868b EI |
614 | env->pregs[PR_CCS], |
615 | env->cc_result); | |
616 | break; | |
617 | case 2: | |
618 | env->pregs[PR_CCS] = | |
febc9920 | 619 | helper_evaluate_flags_move_2(env, |
6231868b EI |
620 | env->pregs[PR_CCS], |
621 | env->cc_result); | |
622 | break; | |
623 | default: | |
febc9920 | 624 | helper_evaluate_flags(env); |
6231868b EI |
625 | break; |
626 | } | |
627 | break; | |
30abcfc7 EI |
628 | case CC_OP_FLAGS: |
629 | /* live. */ | |
630 | break; | |
a8cf66bb EI |
631 | case CC_OP_SUB: |
632 | case CC_OP_CMP: | |
633 | if (env->cc_size == 4) | |
6231868b | 634 | env->pregs[PR_CCS] = |
febc9920 | 635 | helper_evaluate_flags_sub_4(env, |
6231868b EI |
636 | env->pregs[PR_CCS], |
637 | env->cc_src, env->cc_dest, | |
638 | env->cc_result); | |
a8cf66bb | 639 | else |
febc9920 | 640 | helper_evaluate_flags(env); |
a8cf66bb | 641 | break; |
30abcfc7 EI |
642 | default: |
643 | { | |
644 | switch (env->cc_size) | |
645 | { | |
6231868b EI |
646 | case 4: |
647 | env->pregs[PR_CCS] = | |
febc9920 | 648 | helper_evaluate_flags_alu_4(env, |
6231868b EI |
649 | env->pregs[PR_CCS], |
650 | env->cc_src, env->cc_dest, | |
651 | env->cc_result); | |
652 | break; | |
653 | default: | |
febc9920 | 654 | helper_evaluate_flags(env); |
6231868b | 655 | break; |
30abcfc7 EI |
656 | } |
657 | } | |
658 | break; | |
659 | } | |
660 | } |