[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__, 
	     env->pc, env->debug1, retaddr);
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc);

		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags();
            }
        }
        cpu_loop_exit(env);
    }
    env = saved_env;
}

#endif

void helper_raise_exception(uint32_t index)
{
	env->exception_index = index;
        cpu_loop_exit(env);
}

void helper_tlb_flush_pid(uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
	tlb_flush_page(env, env->pregs[PR_SPC]);
	tlb_flush_page(env, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
{
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			if (tlb_v) {
				tlb_flush_page(env, vaddr);
			}
		}
	}
#endif
}

void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

    /* Always set the M flag.  */
    env->pregs[PR_CCS] |= M_FLAG;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	if (env->pregs[PR_VR] < 32)
		ccs &= ~(V_FLAG | C_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void  helper_evaluate_flags(void)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(void)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
			env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
			env->pregs[PR_CCS] = helper_evaluate_flags_muls(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
			env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_4(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_2(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
					helper_evaluate_flags_sub_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
				helper_evaluate_flags();
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_alu_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
81fdc5f8	21	#include "exec.h"
786c02f1	22	#include "mmu.h"
30abcfc7	23	#include "helper.h"
c38ac98d	24	#include "host-utils.h"
81fdc5f8	25
d12d51d5 AL	26	//#define CRIS_OP_HELPER_DEBUG
	27
	28
	29	#ifdef CRIS_OP_HELPER_DEBUG
	30	#define D(x) x
93fcfe39	31	#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5	32	#else
e2eef170	33	#define D(x)
d12d51d5 AL	34	#define D_LOG(...) do { } while (0)
d12d51d5 AL	35	#endif
e2eef170 PB	36
	37	#if !defined(CONFIG_USER_ONLY)
	38
81fdc5f8	39	#define MMUSUFFIX _mmu
81fdc5f8 TS	40
	41	#define SHIFT 0
	42	#include "softmmu_template.h"
	43
	44	#define SHIFT 1
	45	#include "softmmu_template.h"
	46
	47	#define SHIFT 2
	48	#include "softmmu_template.h"
	49
	50	#define SHIFT 3
	51	#include "softmmu_template.h"
	52
	53	/* Try to fill the TLB and return an exception if error. If retaddr is
	54	NULL, it means that the function was called in C code (i.e. not
	55	from generated code or from helper.c) */
	56	/* XXX: fix it to restore all registers */
6ebbf390	57	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
81fdc5f8 TS	58	{
	59	TranslationBlock *tb;
	60	CPUState *saved_env;
44f8625d	61	unsigned long pc;
81fdc5f8 TS	62	int ret;
	63
	64	/* XXX: hack to restore env in all cases, even if not called from
	65	generated code */
	66	saved_env = env;
	67	env = cpu_single_env;
b41f7df0	68
d12d51d5 AL	69	D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
d12d51d5 AL	70	env->pc, env->debug1, retaddr);
6ebbf390	71	ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
551bd27f	72	if (unlikely(ret)) {
81fdc5f8 TS	73	if (retaddr) {
81fdc5f8 TS	74	/* now we have a real cpu fault */
44f8625d	75	pc = (unsigned long)retaddr;
81fdc5f8 TS	76	tb = tb_find_pc(pc);
	77	if (tb) {
	78	/* the PC is inside the translated code. It means that we have
	79	a virtual CPU fault */
618ba8e6	80	cpu_restore_state(tb, env, pc);
30abcfc7 EI	81
	82	/* Evaluate flags after retranslation. */
	83	helper_top_evaluate_flags();
81fdc5f8 TS	84	}
81fdc5f8 TS	85	}
1162c041	86	cpu_loop_exit(env);
81fdc5f8 TS	87	}
	88	env = saved_env;
	89	}
	90
e2eef170 PB	91	#endif
e2eef170 PB	92
dceaf394	93	void helper_raise_exception(uint32_t index)
786c02f1	94	{
dceaf394	95	env->exception_index = index;
1162c041	96	cpu_loop_exit(env);
786c02f1 EI	97	}
786c02f1 EI	98
cf1d97f0 EI	99	void helper_tlb_flush_pid(uint32_t pid)
	100	{
	101	#if !defined(CONFIG_USER_ONLY)
28de16da EI	102	pid &= 0xff;
	103	if (pid != (env->pregs[PR_PID] & 0xff))
	104	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	105	#endif
	106	}
	107
a1aebcb8 EI	108	void helper_spc_write(uint32_t new_spc)
	109	{
	110	#if !defined(CONFIG_USER_ONLY)
	111	tlb_flush_page(env, env->pregs[PR_SPC]);
	112	tlb_flush_page(env, new_spc);
	113	#endif
	114	}
	115
30abcfc7	116	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	117	{
93fcfe39	118	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	119	}
b41f7df0 EI	120
cf1d97f0 EI	121	/* Used by the tlb decoder. */
	122	#define EXTRACT_FIELD(src, start, end) \
	123	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	124
dceaf394 EI	125	void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
	126	{
	127	uint32_t srs;
	128	srs = env->pregs[PR_SRS];
	129	srs &= 3;
	130	env->sregs[srs][sreg] = env->regs[reg];
	131
	132	#if !defined(CONFIG_USER_ONLY)
	133	if (srs == 1 \|\| srs == 2) {
	134	if (sreg == 6) {
	135	/* Writes to tlb-hi write to mm_cause as a side
	136	effect. */
6913ba56 EI	137	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	138	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	139	}
	140	else if (sreg == 5) {
	141	uint32_t set;
	142	uint32_t idx;
	143	uint32_t lo, hi;
	144	uint32_t vaddr;
cf1d97f0	145	int tlb_v;
dceaf394 EI	146
	147	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	148	set >>= 4;
	149	set &= 3;
	150
	151	idx &= 15;
	152	/* We've just made a write to tlb_lo. */
	153	lo = env->sregs[SFR_RW_MM_TLB_LO];
	154	/* Writes are done via r_mm_cause. */
	155	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	156
	157	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	158	13, 31);
	159	vaddr <<= TARGET_PAGE_BITS;
	160	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	161	3, 3);
dceaf394 EI	162	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	163	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	164
d12d51d5 AL	165	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	166	vaddr, tlb_v, env->pc);
3e18c6bf EI	167	if (tlb_v) {
	168	tlb_flush_page(env, vaddr);
	169	}
dceaf394 EI	170	}
	171	}
	172	#endif
	173	}
	174
	175	void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
	176	{
	177	uint32_t srs;
	178	env->pregs[PR_SRS] &= 3;
	179	srs = env->pregs[PR_SRS];
	180
	181	#if !defined(CONFIG_USER_ONLY)
	182	if (srs == 1 \|\| srs == 2)
	183	{
	184	uint32_t set;
	185	uint32_t idx;
	186	uint32_t lo, hi;
	187
	188	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	189	set >>= 4;
	190	set &= 3;
	191	idx &= 15;
	192
	193	/* Update the mirror regs. */
	194	hi = env->tlbsets[srs - 1][set][idx].hi;
	195	lo = env->tlbsets[srs - 1][set][idx].lo;
	196	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	197	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	198	}
	199	#endif
	200	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	201	}
	202
	203	static void cris_ccs_rshift(CPUState *env)
	204	{
	205	uint32_t ccs;
	206
	207	/* Apply the ccs shift. */
	208	ccs = env->pregs[PR_CCS];
	209	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	210	if (ccs & U_FLAG)
	211	{
	212	/* Enter user mode. */
	213	env->ksp = env->regs[R_SP];
	214	env->regs[R_SP] = env->pregs[PR_USP];
	215	}
	216
	217	env->pregs[PR_CCS] = ccs;
	218	}
	219
b41f7df0 EI	220	void helper_rfe(void)
b41f7df0 EI	221	{
bf443337 EI	222	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	223
d12d51d5	224	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	225	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	226	env->pregs[PR_CCS],
d12d51d5	227	env->btarget);
dceaf394 EI	228
	229	cris_ccs_rshift(env);
	230
	231	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	232	if (!rflag)
dceaf394	233	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	234	}
b41f7df0 EI	235
5bf8f1ab EI	236	void helper_rfn(void)
	237	{
	238	int rflag = env->pregs[PR_CCS] & R_FLAG;
	239
d12d51d5	240	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	241	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	242	env->pregs[PR_CCS],
d12d51d5	243	env->btarget);
5bf8f1ab EI	244
	245	cris_ccs_rshift(env);
	246
	247	/* Set the P_FLAG only if the R_FLAG is not set. */
	248	if (!rflag)
	249	env->pregs[PR_CCS] \|= P_FLAG;
	250
	251	/* Always set the M flag. */
	252	env->pregs[PR_CCS] \|= M_FLAG;
	253	}
	254
c38ac98d EI	255	uint32_t helper_lz(uint32_t t0)
	256	{
	257	return clz32(t0);
	258	}
	259
abd5c94e EI	260	uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
	261	{
	262	/* FIXME: clean this up. */
	263
	264	/* des ref:
	265	The N flag is set according to the selected bit in the dest reg.
	266	The Z flag is set if the selected bit and all bits to the right are
	267	zero.
	268	The X flag is cleared.
	269	Other flags are left untouched.
	270	The destination reg is not affected.*/
	271	unsigned int fz, sbit, bset, mask, masked_t0;
	272
	273	sbit = t1 & 31;
	274	bset = !!(t0 & (1 << sbit));
	275	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	276	masked_t0 = t0 & mask;
	277	fz = !(masked_t0 \| bset);
	278
	279	/* Clear the X, N and Z flags. */
	280	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
95475216 EI	281	if (env->pregs[PR_VR] < 32)
95475216 EI	282	ccs &= ~(V_FLAG \| C_FLAG);
abd5c94e EI	283	/* Set the N and Z flags accordingly. */
	284	ccs \|= (bset << 3) \| (fz << 2);
	285	return ccs;
	286	}
	287
6231868b	288	static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
b41f7df0	289	{
a8cf66bb	290	unsigned int x, z, mask;
b41f7df0 EI	291
b41f7df0 EI	292	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	293	x = env->cc_x;
a8cf66bb EI	294	mask = env->cc_mask \| X_FLAG;
	295	if (x) {
	296	z = flags & Z_FLAG;
	297	mask = mask & ~z;
	298	}
	299	flags &= mask;
b41f7df0 EI	300
b41f7df0 EI	301	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	302	ccs &= ~mask;
	303	ccs \|= flags;
	304	return ccs;
b41f7df0 EI	305	}
b41f7df0 EI	306
6231868b	307	uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	308	{
b41f7df0	309	uint32_t flags = 0;
dceaf394	310	int64_t tmp;
b41f7df0 EI	311	int dneg;
b41f7df0 EI	312
b41f7df0 EI	313	dneg = ((int32_t)res) < 0;
b41f7df0 EI	314
dceaf394 EI	315	tmp = mof;
	316	tmp <<= 32;
	317	tmp \|= res;
b41f7df0 EI	318	if (tmp == 0)
	319	flags \|= Z_FLAG;
	320	else if (tmp < 0)
	321	flags \|= N_FLAG;
	322	if ((dneg && mof != -1)
	323	\|\| (!dneg && mof != 0))
	324	flags \|= V_FLAG;
6231868b	325	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	326	}
b41f7df0 EI	327
6231868b	328	uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	329	{
b41f7df0	330	uint32_t flags = 0;
dceaf394	331	uint64_t tmp;
b41f7df0	332
dceaf394 EI	333	tmp = mof;
	334	tmp <<= 32;
	335	tmp \|= res;
b41f7df0 EI	336	if (tmp == 0)
	337	flags \|= Z_FLAG;
	338	else if (tmp >> 63)
	339	flags \|= N_FLAG;
	340	if (mof)
	341	flags \|= V_FLAG;
	342
6231868b	343	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	344	}
b41f7df0 EI	345
6231868b EI	346	uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
6231868b EI	347	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	348	{
b41f7df0 EI	349	uint32_t flags = 0;
b41f7df0 EI	350
6231868b EI	351	src = src & 0x80000000;
6231868b EI	352	dst = dst & 0x80000000;
b41f7df0 EI	353
	354	if ((res & 0x80000000L) != 0L)
	355	{
	356	flags \|= N_FLAG;
a8cf66bb	357	if (!src && !dst)
b41f7df0	358	flags \|= V_FLAG;
a8cf66bb	359	else if (src & dst)
b41f7df0	360	flags \|= R_FLAG;
b41f7df0 EI	361	}
	362	else
	363	{
	364	if (res == 0L)
	365	flags \|= Z_FLAG;
a8cf66bb	366	if (src & dst)
b41f7df0	367	flags \|= V_FLAG;
a8cf66bb	368	if (dst \| src)
b41f7df0 EI	369	flags \|= R_FLAG;
	370	}
	371
6231868b	372	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	373	}
b41f7df0 EI	374
6231868b EI	375	uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
6231868b EI	376	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	377	{
b41f7df0 EI	378	uint32_t flags = 0;
b41f7df0 EI	379
6231868b EI	380	src = src & 0x80000000;
6231868b EI	381	dst = dst & 0x80000000;
30abcfc7	382
a8cf66bb	383	if ((res & 0x80000000L) != 0L)
30abcfc7	384	{
a8cf66bb EI	385	flags \|= N_FLAG;
	386	if (!src && !dst)
	387	flags \|= V_FLAG;
	388	else if (src & dst)
	389	flags \|= C_FLAG;
	390	}
	391	else
	392	{
	393	if (res == 0L)
	394	flags \|= Z_FLAG;
	395	if (src & dst)
	396	flags \|= V_FLAG;
	397	if (dst \| src)
	398	flags \|= C_FLAG;
30abcfc7 EI	399	}
30abcfc7 EI	400
6231868b	401	return evaluate_flags_writeback(flags, ccs);
a8cf66bb EI	402	}
a8cf66bb EI	403
6231868b EI	404	uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
6231868b EI	405	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	406	{
a8cf66bb EI	407	uint32_t flags = 0;
a8cf66bb EI	408
6231868b EI	409	src = (~src) & 0x80000000;
6231868b EI	410	dst = dst & 0x80000000;
b41f7df0 EI	411
	412	if ((res & 0x80000000L) != 0L)
	413	{
	414	flags \|= N_FLAG;
a8cf66bb	415	if (!src && !dst)
b41f7df0	416	flags \|= V_FLAG;
a8cf66bb	417	else if (src & dst)
b41f7df0	418	flags \|= C_FLAG;
b41f7df0 EI	419	}
	420	else
	421	{
	422	if (res == 0L)
	423	flags \|= Z_FLAG;
a8cf66bb	424	if (src & dst)
b41f7df0	425	flags \|= V_FLAG;
a8cf66bb	426	if (dst \| src)
b41f7df0 EI	427	flags \|= C_FLAG;
	428	}
	429
a8cf66bb	430	flags ^= C_FLAG;
6231868b	431	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	432	}
b41f7df0 EI	433
6231868b	434	uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
b41f7df0	435	{
b41f7df0 EI	436	uint32_t flags = 0;
b41f7df0 EI	437
b41f7df0 EI	438	if ((int32_t)res < 0)
	439	flags \|= N_FLAG;
	440	else if (res == 0L)
	441	flags \|= Z_FLAG;
	442
6231868b	443	return evaluate_flags_writeback(flags, ccs);
b41f7df0	444	}
6231868b	445	uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
b41f7df0	446	{
b41f7df0	447	uint32_t flags = 0;
b41f7df0 EI	448
	449	if ((int16_t)res < 0L)
	450	flags \|= N_FLAG;
	451	else if (res == 0)
	452	flags \|= Z_FLAG;
	453
6231868b	454	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	455	}
	456
	457	/* TODO: This is expensive. We could split things up and only evaluate part of
	458	CCR on a need to know basis. For now, we simply re-evaluate everything. */
6231868b	459	void helper_evaluate_flags(void)
b41f7df0	460	{
6231868b	461	uint32_t src, dst, res;
b41f7df0 EI	462	uint32_t flags = 0;
	463
	464	src = env->cc_src;
	465	dst = env->cc_dest;
	466	res = env->cc_result;
	467
30abcfc7 EI	468	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	469	src = ~src;
b41f7df0 EI	470
	471	/* Now, evaluate the flags. This stuff is based on
	472	Per Zander's CRISv10 simulator. */
	473	switch (env->cc_size)
	474	{
	475	case 1:
	476	if ((res & 0x80L) != 0L)
	477	{
	478	flags \|= N_FLAG;
	479	if (((src & 0x80L) == 0L)
	480	&& ((dst & 0x80L) == 0L))
	481	{
	482	flags \|= V_FLAG;
	483	}
	484	else if (((src & 0x80L) != 0L)
	485	&& ((dst & 0x80L) != 0L))
	486	{
	487	flags \|= C_FLAG;
	488	}
	489	}
	490	else
	491	{
	492	if ((res & 0xFFL) == 0L)
	493	{
	494	flags \|= Z_FLAG;
	495	}
	496	if (((src & 0x80L) != 0L)
	497	&& ((dst & 0x80L) != 0L))
	498	{
	499	flags \|= V_FLAG;
	500	}
	501	if ((dst & 0x80L) != 0L
	502	\|\| (src & 0x80L) != 0L)
	503	{
	504	flags \|= C_FLAG;
	505	}
	506	}
	507	break;
	508	case 2:
	509	if ((res & 0x8000L) != 0L)
	510	{
	511	flags \|= N_FLAG;
	512	if (((src & 0x8000L) == 0L)
	513	&& ((dst & 0x8000L) == 0L))
	514	{
	515	flags \|= V_FLAG;
	516	}
	517	else if (((src & 0x8000L) != 0L)
	518	&& ((dst & 0x8000L) != 0L))
	519	{
	520	flags \|= C_FLAG;
	521	}
	522	}
	523	else
	524	{
	525	if ((res & 0xFFFFL) == 0L)
	526	{
	527	flags \|= Z_FLAG;
	528	}
	529	if (((src & 0x8000L) != 0L)
	530	&& ((dst & 0x8000L) != 0L))
	531	{
	532	flags \|= V_FLAG;
	533	}
534	if ((dst & 0x8000L) != 0L
535	\|\| (src & 0x8000L) != 0L)
536	{
537	flags \|= C_FLAG;
538	}
539	}
540	break;
541	case 4:
542	if ((res & 0x80000000L) != 0L)
543	{
544	flags \|= N_FLAG;
545	if (((src & 0x80000000L) == 0L)
546	&& ((dst & 0x80000000L) == 0L))
547	{
548	flags \|= V_FLAG;
549	}
550	else if (((src & 0x80000000L) != 0L) &&
551	((dst & 0x80000000L) != 0L))
552	{
553	flags \|= C_FLAG;
554	}
555	}
556	else
557	{
558	if (res == 0L)
559	flags \|= Z_FLAG;
560	if (((src & 0x80000000L) != 0L)
561	&& ((dst & 0x80000000L) != 0L))
562	flags \|= V_FLAG;
563	if ((dst & 0x80000000L) != 0L
564	\|\| (src & 0x80000000L) != 0L)
565	flags \|= C_FLAG;
566	}
567	break;
568	default:
569	break;
570	}
571
6231868b	572	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	573	flags ^= C_FLAG;
6231868b EI	574
6231868b EI	575	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
b41f7df0	576	}
30abcfc7 EI	577
	578	void helper_top_evaluate_flags(void)
	579	{
	580	switch (env->cc_op)
	581	{
	582	case CC_OP_MCP:
6231868b EI	583	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
	584	env->pregs[PR_CCS], env->cc_src,
	585	env->cc_dest, env->cc_result);
30abcfc7 EI	586	break;
30abcfc7 EI	587	case CC_OP_MULS:
6231868b EI	588	env->pregs[PR_CCS] = helper_evaluate_flags_muls(
	589	env->pregs[PR_CCS], env->cc_result,
	590	env->pregs[PR_MOF]);
30abcfc7 EI	591	break;
30abcfc7 EI	592	case CC_OP_MULU:
6231868b EI	593	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
	594	env->pregs[PR_CCS], env->cc_result,
	595	env->pregs[PR_MOF]);
30abcfc7 EI	596	break;
	597	case CC_OP_MOVE:
	598	case CC_OP_AND:
	599	case CC_OP_OR:
	600	case CC_OP_XOR:
	601	case CC_OP_ASR:
	602	case CC_OP_LSR:
	603	case CC_OP_LSL:
6231868b EI	604	switch (env->cc_size)
	605	{
	606	case 4:
	607	env->pregs[PR_CCS] =
	608	helper_evaluate_flags_move_4(
	609	env->pregs[PR_CCS],
	610	env->cc_result);
	611	break;
	612	case 2:
	613	env->pregs[PR_CCS] =
	614	helper_evaluate_flags_move_2(
	615	env->pregs[PR_CCS],
	616	env->cc_result);
	617	break;
	618	default:
	619	helper_evaluate_flags();
	620	break;
	621	}
	622	break;
30abcfc7 EI	623	case CC_OP_FLAGS:
	624	/* live. */
	625	break;
a8cf66bb EI	626	case CC_OP_SUB:
	627	case CC_OP_CMP:
	628	if (env->cc_size == 4)
6231868b EI	629	env->pregs[PR_CCS] =
	630	helper_evaluate_flags_sub_4(
	631	env->pregs[PR_CCS],
	632	env->cc_src, env->cc_dest,
	633	env->cc_result);
a8cf66bb EI	634	else
	635	helper_evaluate_flags();
	636	break;
30abcfc7 EI	637	default:
	638	{
	639	switch (env->cc_size)
	640	{
6231868b EI	641	case 4:
	642	env->pregs[PR_CCS] =
	643	helper_evaluate_flags_alu_4(
	644	env->pregs[PR_CCS],
	645	env->cc_src, env->cc_dest,
	646	env->cc_result);
	647	break;
	648	default:
	649	helper_evaluate_flags();
	650	break;
30abcfc7 EI	651	}
	652	}
	653	break;
	654	}
	655	}