[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "dyngen-exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__, 
	     env->pc, env->debug1, retaddr);
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc);

		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags();
            }
        }
        cpu_loop_exit(env);
    }
    env = saved_env;
}

#endif

void helper_raise_exception(uint32_t index)
{
	env->exception_index = index;
        cpu_loop_exit(env);
}

void helper_tlb_flush_pid(uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
	tlb_flush_page(env, env->pregs[PR_SPC]);
	tlb_flush_page(env, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
{
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			if (tlb_v) {
				tlb_flush_page(env, vaddr);
			}
		}
	}
#endif
}

void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

    /* Always set the M flag.  */
    env->pregs[PR_CCS] |= M_FLAG;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	if (env->pregs[PR_VR] < 32)
		ccs &= ~(V_FLAG | C_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void  helper_evaluate_flags(void)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(void)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
			env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
			env->pregs[PR_CCS] = helper_evaluate_flags_muls(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
			env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_4(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_2(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
					helper_evaluate_flags_sub_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
				helper_evaluate_flags();
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_alu_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
3e457172 BS	21	#include "cpu.h"
3e457172 BS	22	#include "dyngen-exec.h"
786c02f1	23	#include "mmu.h"
30abcfc7	24	#include "helper.h"
c38ac98d	25	#include "host-utils.h"
81fdc5f8	26
d12d51d5 AL	27	//#define CRIS_OP_HELPER_DEBUG
	28
	29
	30	#ifdef CRIS_OP_HELPER_DEBUG
	31	#define D(x) x
93fcfe39	32	#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5	33	#else
e2eef170	34	#define D(x)
d12d51d5 AL	35	#define D_LOG(...) do { } while (0)
d12d51d5 AL	36	#endif
e2eef170 PB	37
e2eef170 PB	38	#if !defined(CONFIG_USER_ONLY)
3e457172	39	#include "softmmu_exec.h"
e2eef170	40
81fdc5f8	41	#define MMUSUFFIX _mmu
81fdc5f8 TS	42
	43	#define SHIFT 0
	44	#include "softmmu_template.h"
	45
	46	#define SHIFT 1
	47	#include "softmmu_template.h"
	48
	49	#define SHIFT 2
	50	#include "softmmu_template.h"
	51
	52	#define SHIFT 3
	53	#include "softmmu_template.h"
	54
	55	/* Try to fill the TLB and return an exception if error. If retaddr is
	56	NULL, it means that the function was called in C code (i.e. not
	57	from generated code or from helper.c) */
	58	/* XXX: fix it to restore all registers */
6ebbf390	59	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
81fdc5f8 TS	60	{
	61	TranslationBlock *tb;
	62	CPUState *saved_env;
44f8625d	63	unsigned long pc;
81fdc5f8 TS	64	int ret;
	65
	66	/* XXX: hack to restore env in all cases, even if not called from
	67	generated code */
	68	saved_env = env;
	69	env = cpu_single_env;
b41f7df0	70
d12d51d5 AL	71	D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
d12d51d5 AL	72	env->pc, env->debug1, retaddr);
6ebbf390	73	ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
551bd27f	74	if (unlikely(ret)) {
81fdc5f8 TS	75	if (retaddr) {
81fdc5f8 TS	76	/* now we have a real cpu fault */
44f8625d	77	pc = (unsigned long)retaddr;
81fdc5f8 TS	78	tb = tb_find_pc(pc);
	79	if (tb) {
	80	/* the PC is inside the translated code. It means that we have
	81	a virtual CPU fault */
618ba8e6	82	cpu_restore_state(tb, env, pc);
30abcfc7 EI	83
	84	/* Evaluate flags after retranslation. */
	85	helper_top_evaluate_flags();
81fdc5f8 TS	86	}
81fdc5f8 TS	87	}
1162c041	88	cpu_loop_exit(env);
81fdc5f8 TS	89	}
	90	env = saved_env;
	91	}
	92
e2eef170 PB	93	#endif
e2eef170 PB	94
dceaf394	95	void helper_raise_exception(uint32_t index)
786c02f1	96	{
dceaf394	97	env->exception_index = index;
1162c041	98	cpu_loop_exit(env);
786c02f1 EI	99	}
786c02f1 EI	100
cf1d97f0 EI	101	void helper_tlb_flush_pid(uint32_t pid)
	102	{
	103	#if !defined(CONFIG_USER_ONLY)
28de16da EI	104	pid &= 0xff;
	105	if (pid != (env->pregs[PR_PID] & 0xff))
	106	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	107	#endif
	108	}
	109
a1aebcb8 EI	110	void helper_spc_write(uint32_t new_spc)
	111	{
	112	#if !defined(CONFIG_USER_ONLY)
	113	tlb_flush_page(env, env->pregs[PR_SPC]);
	114	tlb_flush_page(env, new_spc);
	115	#endif
	116	}
	117
30abcfc7	118	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	119	{
93fcfe39	120	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	121	}
b41f7df0 EI	122
cf1d97f0 EI	123	/* Used by the tlb decoder. */
	124	#define EXTRACT_FIELD(src, start, end) \
	125	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	126
dceaf394 EI	127	void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
	128	{
	129	uint32_t srs;
	130	srs = env->pregs[PR_SRS];
	131	srs &= 3;
	132	env->sregs[srs][sreg] = env->regs[reg];
	133
	134	#if !defined(CONFIG_USER_ONLY)
	135	if (srs == 1 \|\| srs == 2) {
	136	if (sreg == 6) {
	137	/* Writes to tlb-hi write to mm_cause as a side
	138	effect. */
6913ba56 EI	139	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	140	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	141	}
	142	else if (sreg == 5) {
	143	uint32_t set;
	144	uint32_t idx;
	145	uint32_t lo, hi;
	146	uint32_t vaddr;
cf1d97f0	147	int tlb_v;
dceaf394 EI	148
	149	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	150	set >>= 4;
	151	set &= 3;
	152
	153	idx &= 15;
	154	/* We've just made a write to tlb_lo. */
	155	lo = env->sregs[SFR_RW_MM_TLB_LO];
	156	/* Writes are done via r_mm_cause. */
	157	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	158
	159	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	160	13, 31);
	161	vaddr <<= TARGET_PAGE_BITS;
	162	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	163	3, 3);
dceaf394 EI	164	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	165	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	166
d12d51d5 AL	167	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	168	vaddr, tlb_v, env->pc);
3e18c6bf EI	169	if (tlb_v) {
	170	tlb_flush_page(env, vaddr);
	171	}
dceaf394 EI	172	}
	173	}
	174	#endif
	175	}
	176
	177	void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
	178	{
	179	uint32_t srs;
	180	env->pregs[PR_SRS] &= 3;
	181	srs = env->pregs[PR_SRS];
	182
	183	#if !defined(CONFIG_USER_ONLY)
	184	if (srs == 1 \|\| srs == 2)
	185	{
	186	uint32_t set;
	187	uint32_t idx;
	188	uint32_t lo, hi;
	189
	190	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	191	set >>= 4;
	192	set &= 3;
	193	idx &= 15;
	194
	195	/* Update the mirror regs. */
	196	hi = env->tlbsets[srs - 1][set][idx].hi;
	197	lo = env->tlbsets[srs - 1][set][idx].lo;
	198	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	199	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	200	}
	201	#endif
	202	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	203	}
	204
	205	static void cris_ccs_rshift(CPUState *env)
	206	{
	207	uint32_t ccs;
	208
	209	/* Apply the ccs shift. */
	210	ccs = env->pregs[PR_CCS];
	211	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	212	if (ccs & U_FLAG)
	213	{
	214	/* Enter user mode. */
	215	env->ksp = env->regs[R_SP];
	216	env->regs[R_SP] = env->pregs[PR_USP];
	217	}
	218
	219	env->pregs[PR_CCS] = ccs;
	220	}
	221
b41f7df0 EI	222	void helper_rfe(void)
b41f7df0 EI	223	{
bf443337 EI	224	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	225
d12d51d5	226	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	227	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	228	env->pregs[PR_CCS],
d12d51d5	229	env->btarget);
dceaf394 EI	230
	231	cris_ccs_rshift(env);
	232
	233	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	234	if (!rflag)
dceaf394	235	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	236	}
b41f7df0 EI	237
5bf8f1ab EI	238	void helper_rfn(void)
	239	{
	240	int rflag = env->pregs[PR_CCS] & R_FLAG;
	241
d12d51d5	242	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	243	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	244	env->pregs[PR_CCS],
d12d51d5	245	env->btarget);
5bf8f1ab EI	246
	247	cris_ccs_rshift(env);
	248
	249	/* Set the P_FLAG only if the R_FLAG is not set. */
	250	if (!rflag)
	251	env->pregs[PR_CCS] \|= P_FLAG;
	252
	253	/* Always set the M flag. */
	254	env->pregs[PR_CCS] \|= M_FLAG;
	255	}
	256
c38ac98d EI	257	uint32_t helper_lz(uint32_t t0)
	258	{
	259	return clz32(t0);
	260	}
	261
abd5c94e EI	262	uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
	263	{
	264	/* FIXME: clean this up. */
	265
	266	/* des ref:
	267	The N flag is set according to the selected bit in the dest reg.
	268	The Z flag is set if the selected bit and all bits to the right are
	269	zero.
	270	The X flag is cleared.
	271	Other flags are left untouched.
	272	The destination reg is not affected.*/
	273	unsigned int fz, sbit, bset, mask, masked_t0;
	274
	275	sbit = t1 & 31;
	276	bset = !!(t0 & (1 << sbit));
	277	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	278	masked_t0 = t0 & mask;
	279	fz = !(masked_t0 \| bset);
	280
	281	/* Clear the X, N and Z flags. */
	282	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
95475216 EI	283	if (env->pregs[PR_VR] < 32)
95475216 EI	284	ccs &= ~(V_FLAG \| C_FLAG);
abd5c94e EI	285	/* Set the N and Z flags accordingly. */
	286	ccs \|= (bset << 3) \| (fz << 2);
	287	return ccs;
	288	}
	289
6231868b	290	static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
b41f7df0	291	{
a8cf66bb	292	unsigned int x, z, mask;
b41f7df0 EI	293
b41f7df0 EI	294	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	295	x = env->cc_x;
a8cf66bb EI	296	mask = env->cc_mask \| X_FLAG;
	297	if (x) {
	298	z = flags & Z_FLAG;
	299	mask = mask & ~z;
	300	}
	301	flags &= mask;
b41f7df0 EI	302
b41f7df0 EI	303	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	304	ccs &= ~mask;
	305	ccs \|= flags;
	306	return ccs;
b41f7df0 EI	307	}
b41f7df0 EI	308
6231868b	309	uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	310	{
b41f7df0	311	uint32_t flags = 0;
dceaf394	312	int64_t tmp;
b41f7df0 EI	313	int dneg;
b41f7df0 EI	314
b41f7df0 EI	315	dneg = ((int32_t)res) < 0;
b41f7df0 EI	316
dceaf394 EI	317	tmp = mof;
	318	tmp <<= 32;
	319	tmp \|= res;
b41f7df0 EI	320	if (tmp == 0)
	321	flags \|= Z_FLAG;
	322	else if (tmp < 0)
	323	flags \|= N_FLAG;
	324	if ((dneg && mof != -1)
	325	\|\| (!dneg && mof != 0))
	326	flags \|= V_FLAG;
6231868b	327	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	328	}
b41f7df0 EI	329
6231868b	330	uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	331	{
b41f7df0	332	uint32_t flags = 0;
dceaf394	333	uint64_t tmp;
b41f7df0	334
dceaf394 EI	335	tmp = mof;
	336	tmp <<= 32;
	337	tmp \|= res;
b41f7df0 EI	338	if (tmp == 0)
	339	flags \|= Z_FLAG;
	340	else if (tmp >> 63)
	341	flags \|= N_FLAG;
	342	if (mof)
	343	flags \|= V_FLAG;
	344
6231868b	345	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	346	}
b41f7df0 EI	347
6231868b EI	348	uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
6231868b EI	349	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	350	{
b41f7df0 EI	351	uint32_t flags = 0;
b41f7df0 EI	352
6231868b EI	353	src = src & 0x80000000;
6231868b EI	354	dst = dst & 0x80000000;
b41f7df0 EI	355
	356	if ((res & 0x80000000L) != 0L)
	357	{
	358	flags \|= N_FLAG;
a8cf66bb	359	if (!src && !dst)
b41f7df0	360	flags \|= V_FLAG;
a8cf66bb	361	else if (src & dst)
b41f7df0	362	flags \|= R_FLAG;
b41f7df0 EI	363	}
	364	else
	365	{
	366	if (res == 0L)
	367	flags \|= Z_FLAG;
a8cf66bb	368	if (src & dst)
b41f7df0	369	flags \|= V_FLAG;
a8cf66bb	370	if (dst \| src)
b41f7df0 EI	371	flags \|= R_FLAG;
	372	}
	373
6231868b	374	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	375	}
b41f7df0 EI	376
6231868b EI	377	uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
6231868b EI	378	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	379	{
b41f7df0 EI	380	uint32_t flags = 0;
b41f7df0 EI	381
6231868b EI	382	src = src & 0x80000000;
6231868b EI	383	dst = dst & 0x80000000;
30abcfc7	384
a8cf66bb	385	if ((res & 0x80000000L) != 0L)
30abcfc7	386	{
a8cf66bb EI	387	flags \|= N_FLAG;
	388	if (!src && !dst)
	389	flags \|= V_FLAG;
	390	else if (src & dst)
	391	flags \|= C_FLAG;
	392	}
	393	else
	394	{
	395	if (res == 0L)
	396	flags \|= Z_FLAG;
	397	if (src & dst)
	398	flags \|= V_FLAG;
	399	if (dst \| src)
	400	flags \|= C_FLAG;
30abcfc7 EI	401	}
30abcfc7 EI	402
6231868b	403	return evaluate_flags_writeback(flags, ccs);
a8cf66bb EI	404	}
a8cf66bb EI	405
6231868b EI	406	uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
6231868b EI	407	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	408	{
a8cf66bb EI	409	uint32_t flags = 0;
a8cf66bb EI	410
6231868b EI	411	src = (~src) & 0x80000000;
6231868b EI	412	dst = dst & 0x80000000;
b41f7df0 EI	413
	414	if ((res & 0x80000000L) != 0L)
	415	{
	416	flags \|= N_FLAG;
a8cf66bb	417	if (!src && !dst)
b41f7df0	418	flags \|= V_FLAG;
a8cf66bb	419	else if (src & dst)
b41f7df0	420	flags \|= C_FLAG;
b41f7df0 EI	421	}
	422	else
	423	{
	424	if (res == 0L)
	425	flags \|= Z_FLAG;
a8cf66bb	426	if (src & dst)
b41f7df0	427	flags \|= V_FLAG;
a8cf66bb	428	if (dst \| src)
b41f7df0 EI	429	flags \|= C_FLAG;
	430	}
	431
a8cf66bb	432	flags ^= C_FLAG;
6231868b	433	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	434	}
b41f7df0 EI	435
6231868b	436	uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
b41f7df0	437	{
b41f7df0 EI	438	uint32_t flags = 0;
b41f7df0 EI	439
b41f7df0 EI	440	if ((int32_t)res < 0)
	441	flags \|= N_FLAG;
	442	else if (res == 0L)
	443	flags \|= Z_FLAG;
	444
6231868b	445	return evaluate_flags_writeback(flags, ccs);
b41f7df0	446	}
6231868b	447	uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
b41f7df0	448	{
b41f7df0	449	uint32_t flags = 0;
b41f7df0 EI	450
	451	if ((int16_t)res < 0L)
	452	flags \|= N_FLAG;
	453	else if (res == 0)
	454	flags \|= Z_FLAG;
	455
6231868b	456	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	457	}
	458
	459	/* TODO: This is expensive. We could split things up and only evaluate part of
	460	CCR on a need to know basis. For now, we simply re-evaluate everything. */
6231868b	461	void helper_evaluate_flags(void)
b41f7df0	462	{
6231868b	463	uint32_t src, dst, res;
b41f7df0 EI	464	uint32_t flags = 0;
	465
	466	src = env->cc_src;
	467	dst = env->cc_dest;
	468	res = env->cc_result;
	469
30abcfc7 EI	470	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	471	src = ~src;
b41f7df0 EI	472
	473	/* Now, evaluate the flags. This stuff is based on
	474	Per Zander's CRISv10 simulator. */
	475	switch (env->cc_size)
	476	{
	477	case 1:
	478	if ((res & 0x80L) != 0L)
	479	{
	480	flags \|= N_FLAG;
	481	if (((src & 0x80L) == 0L)
	482	&& ((dst & 0x80L) == 0L))
	483	{
	484	flags \|= V_FLAG;
	485	}
	486	else if (((src & 0x80L) != 0L)
	487	&& ((dst & 0x80L) != 0L))
	488	{
	489	flags \|= C_FLAG;
	490	}
	491	}
	492	else
	493	{
	494	if ((res & 0xFFL) == 0L)
	495	{
	496	flags \|= Z_FLAG;
	497	}
	498	if (((src & 0x80L) != 0L)
	499	&& ((dst & 0x80L) != 0L))
	500	{
	501	flags \|= V_FLAG;
	502	}
	503	if ((dst & 0x80L) != 0L
	504	\|\| (src & 0x80L) != 0L)
	505	{
	506	flags \|= C_FLAG;
	507	}
	508	}
	509	break;
	510	case 2:
	511	if ((res & 0x8000L) != 0L)
	512	{
	513	flags \|= N_FLAG;
	514	if (((src & 0x8000L) == 0L)
	515	&& ((dst & 0x8000L) == 0L))
	516	{
	517	flags \|= V_FLAG;
	518	}
	519	else if (((src & 0x8000L) != 0L)
	520	&& ((dst & 0x8000L) != 0L))
	521	{
	522	flags \|= C_FLAG;
	523	}
	524	}
	525	else
	526	{
	527	if ((res & 0xFFFFL) == 0L)
	528	{
	529	flags \|= Z_FLAG;
	530	}
	531	if (((src & 0x8000L) != 0L)
	532	&& ((dst & 0x8000L) != 0L))
	533	{
	534	flags \|= V_FLAG;
	535	}
536	if ((dst & 0x8000L) != 0L
537	\|\| (src & 0x8000L) != 0L)
538	{
539	flags \|= C_FLAG;
540	}
541	}
542	break;
543	case 4:
544	if ((res & 0x80000000L) != 0L)
545	{
546	flags \|= N_FLAG;
547	if (((src & 0x80000000L) == 0L)
548	&& ((dst & 0x80000000L) == 0L))
549	{
550	flags \|= V_FLAG;
551	}
552	else if (((src & 0x80000000L) != 0L) &&
553	((dst & 0x80000000L) != 0L))
554	{
555	flags \|= C_FLAG;
556	}
557	}
558	else
559	{
560	if (res == 0L)
561	flags \|= Z_FLAG;
562	if (((src & 0x80000000L) != 0L)
563	&& ((dst & 0x80000000L) != 0L))
564	flags \|= V_FLAG;
565	if ((dst & 0x80000000L) != 0L
566	\|\| (src & 0x80000000L) != 0L)
567	flags \|= C_FLAG;
568	}
569	break;
570	default:
571	break;
572	}
573
6231868b	574	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	575	flags ^= C_FLAG;
6231868b EI	576
6231868b EI	577	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
b41f7df0	578	}
30abcfc7 EI	579
	580	void helper_top_evaluate_flags(void)
	581	{
	582	switch (env->cc_op)
	583	{
	584	case CC_OP_MCP:
6231868b EI	585	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
	586	env->pregs[PR_CCS], env->cc_src,
	587	env->cc_dest, env->cc_result);
30abcfc7 EI	588	break;
30abcfc7 EI	589	case CC_OP_MULS:
6231868b EI	590	env->pregs[PR_CCS] = helper_evaluate_flags_muls(
	591	env->pregs[PR_CCS], env->cc_result,
	592	env->pregs[PR_MOF]);
30abcfc7 EI	593	break;
30abcfc7 EI	594	case CC_OP_MULU:
6231868b EI	595	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
	596	env->pregs[PR_CCS], env->cc_result,
	597	env->pregs[PR_MOF]);
30abcfc7 EI	598	break;
	599	case CC_OP_MOVE:
	600	case CC_OP_AND:
	601	case CC_OP_OR:
	602	case CC_OP_XOR:
	603	case CC_OP_ASR:
	604	case CC_OP_LSR:
	605	case CC_OP_LSL:
6231868b EI	606	switch (env->cc_size)
	607	{
	608	case 4:
	609	env->pregs[PR_CCS] =
	610	helper_evaluate_flags_move_4(
	611	env->pregs[PR_CCS],
	612	env->cc_result);
	613	break;
	614	case 2:
	615	env->pregs[PR_CCS] =
	616	helper_evaluate_flags_move_2(
	617	env->pregs[PR_CCS],
	618	env->cc_result);
	619	break;
	620	default:
	621	helper_evaluate_flags();
	622	break;
	623	}
	624	break;
30abcfc7 EI	625	case CC_OP_FLAGS:
	626	/* live. */
	627	break;
a8cf66bb EI	628	case CC_OP_SUB:
	629	case CC_OP_CMP:
	630	if (env->cc_size == 4)
6231868b EI	631	env->pregs[PR_CCS] =
	632	helper_evaluate_flags_sub_4(
	633	env->pregs[PR_CCS],
	634	env->cc_src, env->cc_dest,
	635	env->cc_result);
a8cf66bb EI	636	else
	637	helper_evaluate_flags();
	638	break;
30abcfc7 EI	639	default:
	640	{
	641	switch (env->cc_size)
	642	{
6231868b EI	643	case 4:
	644	env->pregs[PR_CCS] =
	645	helper_evaluate_flags_alu_4(
	646	env->pregs[PR_CCS],
	647	env->cc_src, env->cc_dest,
	648	env->cc_result);
	649	break;
	650	default:
	651	helper_evaluate_flags();
	652	break;
30abcfc7 EI	653	}
	654	}
	655	break;
	656	}
	657	}