[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "dyngen-exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
              void *retaddr)
{
    TranslationBlock *tb;
    CPUCRISState *saved_env;
    unsigned long pc;
    int ret;

    saved_env = env;
    env = env1;

    D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__, 
	     env->pc, env->debug1, retaddr);
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc);

		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags();
            }
        }
        cpu_loop_exit(env);
    }
    env = saved_env;
}

#endif

void helper_raise_exception(uint32_t index)
{
	env->exception_index = index;
        cpu_loop_exit(env);
}

void helper_tlb_flush_pid(uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
	tlb_flush_page(env, env->pregs[PR_SPC]);
	tlb_flush_page(env, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
{
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			if (tlb_v) {
				tlb_flush_page(env, vaddr);
			}
		}
	}
#endif
}

void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUCRISState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

    /* Always set the M flag.  */
    env->pregs[PR_CCS] |= M_FLAG;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	if (env->pregs[PR_VR] < 32)
		ccs &= ~(V_FLAG | C_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void  helper_evaluate_flags(void)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(void)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
			env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
			env->pregs[PR_CCS] = helper_evaluate_flags_muls(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
			env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_4(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_2(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
					helper_evaluate_flags_sub_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
				helper_evaluate_flags();
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_alu_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
3e457172 BS	21	#include "cpu.h"
3e457172 BS	22	#include "dyngen-exec.h"
786c02f1	23	#include "mmu.h"
30abcfc7	24	#include "helper.h"
c38ac98d	25	#include "host-utils.h"
81fdc5f8	26
d12d51d5 AL	27	//#define CRIS_OP_HELPER_DEBUG
	28
	29
	30	#ifdef CRIS_OP_HELPER_DEBUG
	31	#define D(x) x
93fcfe39	32	#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5	33	#else
e2eef170	34	#define D(x)
d12d51d5 AL	35	#define D_LOG(...) do { } while (0)
d12d51d5 AL	36	#endif
e2eef170 PB	37
e2eef170 PB	38	#if !defined(CONFIG_USER_ONLY)
3e457172	39	#include "softmmu_exec.h"
e2eef170	40
81fdc5f8	41	#define MMUSUFFIX _mmu
81fdc5f8 TS	42
	43	#define SHIFT 0
	44	#include "softmmu_template.h"
	45
	46	#define SHIFT 1
	47	#include "softmmu_template.h"
	48
	49	#define SHIFT 2
	50	#include "softmmu_template.h"
	51
	52	#define SHIFT 3
	53	#include "softmmu_template.h"
	54
	55	/* Try to fill the TLB and return an exception if error. If retaddr is
	56	NULL, it means that the function was called in C code (i.e. not
	57	from generated code or from helper.c) */
	58	/* XXX: fix it to restore all registers */
a1170bfd	59	void tlb_fill(CPUCRISState *env1, target_ulong addr, int is_write, int mmu_idx,
bccd9ec5	60	void *retaddr)
81fdc5f8 TS	61	{
81fdc5f8 TS	62	TranslationBlock *tb;
a1170bfd	63	CPUCRISState *saved_env;
44f8625d	64	unsigned long pc;
81fdc5f8 TS	65	int ret;
81fdc5f8 TS	66
81fdc5f8	67	saved_env = env;
bccd9ec5	68	env = env1;
b41f7df0	69
d12d51d5 AL	70	D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
d12d51d5 AL	71	env->pc, env->debug1, retaddr);
97b348e7	72	ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
551bd27f	73	if (unlikely(ret)) {
81fdc5f8 TS	74	if (retaddr) {
81fdc5f8 TS	75	/* now we have a real cpu fault */
44f8625d	76	pc = (unsigned long)retaddr;
81fdc5f8 TS	77	tb = tb_find_pc(pc);
	78	if (tb) {
	79	/* the PC is inside the translated code. It means that we have
	80	a virtual CPU fault */
618ba8e6	81	cpu_restore_state(tb, env, pc);
30abcfc7 EI	82
	83	/* Evaluate flags after retranslation. */
	84	helper_top_evaluate_flags();
81fdc5f8 TS	85	}
81fdc5f8 TS	86	}
1162c041	87	cpu_loop_exit(env);
81fdc5f8 TS	88	}
	89	env = saved_env;
	90	}
	91
e2eef170 PB	92	#endif
e2eef170 PB	93
dceaf394	94	void helper_raise_exception(uint32_t index)
786c02f1	95	{
dceaf394	96	env->exception_index = index;
1162c041	97	cpu_loop_exit(env);
786c02f1 EI	98	}
786c02f1 EI	99
cf1d97f0 EI	100	void helper_tlb_flush_pid(uint32_t pid)
	101	{
	102	#if !defined(CONFIG_USER_ONLY)
28de16da EI	103	pid &= 0xff;
	104	if (pid != (env->pregs[PR_PID] & 0xff))
	105	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	106	#endif
	107	}
	108
a1aebcb8 EI	109	void helper_spc_write(uint32_t new_spc)
	110	{
	111	#if !defined(CONFIG_USER_ONLY)
	112	tlb_flush_page(env, env->pregs[PR_SPC]);
	113	tlb_flush_page(env, new_spc);
	114	#endif
	115	}
	116
30abcfc7	117	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	118	{
93fcfe39	119	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	120	}
b41f7df0 EI	121
cf1d97f0 EI	122	/* Used by the tlb decoder. */
	123	#define EXTRACT_FIELD(src, start, end) \
	124	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	125
dceaf394 EI	126	void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
	127	{
	128	uint32_t srs;
	129	srs = env->pregs[PR_SRS];
	130	srs &= 3;
	131	env->sregs[srs][sreg] = env->regs[reg];
	132
	133	#if !defined(CONFIG_USER_ONLY)
	134	if (srs == 1 \|\| srs == 2) {
	135	if (sreg == 6) {
	136	/* Writes to tlb-hi write to mm_cause as a side
	137	effect. */
6913ba56 EI	138	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	139	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	140	}
	141	else if (sreg == 5) {
	142	uint32_t set;
	143	uint32_t idx;
	144	uint32_t lo, hi;
	145	uint32_t vaddr;
cf1d97f0	146	int tlb_v;
dceaf394 EI	147
	148	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	149	set >>= 4;
	150	set &= 3;
	151
	152	idx &= 15;
	153	/* We've just made a write to tlb_lo. */
	154	lo = env->sregs[SFR_RW_MM_TLB_LO];
	155	/* Writes are done via r_mm_cause. */
	156	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	157
	158	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	159	13, 31);
	160	vaddr <<= TARGET_PAGE_BITS;
	161	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	162	3, 3);
dceaf394 EI	163	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	164	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	165
d12d51d5 AL	166	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	167	vaddr, tlb_v, env->pc);
3e18c6bf EI	168	if (tlb_v) {
	169	tlb_flush_page(env, vaddr);
	170	}
dceaf394 EI	171	}
	172	}
	173	#endif
	174	}
	175
	176	void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
	177	{
	178	uint32_t srs;
	179	env->pregs[PR_SRS] &= 3;
	180	srs = env->pregs[PR_SRS];
	181
	182	#if !defined(CONFIG_USER_ONLY)
	183	if (srs == 1 \|\| srs == 2)
	184	{
	185	uint32_t set;
	186	uint32_t idx;
	187	uint32_t lo, hi;
	188
	189	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	190	set >>= 4;
	191	set &= 3;
	192	idx &= 15;
	193
	194	/* Update the mirror regs. */
	195	hi = env->tlbsets[srs - 1][set][idx].hi;
	196	lo = env->tlbsets[srs - 1][set][idx].lo;
	197	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	198	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	199	}
	200	#endif
	201	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	202	}
dceaf394 EI	203
a1170bfd	204	static void cris_ccs_rshift(CPUCRISState *env)
dceaf394 EI	205	{
	206	uint32_t ccs;
	207
	208	/* Apply the ccs shift. */
	209	ccs = env->pregs[PR_CCS];
	210	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	211	if (ccs & U_FLAG)
	212	{
	213	/* Enter user mode. */
	214	env->ksp = env->regs[R_SP];
	215	env->regs[R_SP] = env->pregs[PR_USP];
	216	}
	217
	218	env->pregs[PR_CCS] = ccs;
	219	}
	220
b41f7df0 EI	221	void helper_rfe(void)
b41f7df0 EI	222	{
bf443337 EI	223	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	224
d12d51d5	225	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	226	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	227	env->pregs[PR_CCS],
d12d51d5	228	env->btarget);
dceaf394 EI	229
	230	cris_ccs_rshift(env);
	231
	232	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	233	if (!rflag)
dceaf394	234	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	235	}
b41f7df0 EI	236
5bf8f1ab EI	237	void helper_rfn(void)
	238	{
	239	int rflag = env->pregs[PR_CCS] & R_FLAG;
	240
d12d51d5	241	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	242	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	243	env->pregs[PR_CCS],
d12d51d5	244	env->btarget);
5bf8f1ab EI	245
	246	cris_ccs_rshift(env);
	247
	248	/* Set the P_FLAG only if the R_FLAG is not set. */
	249	if (!rflag)
	250	env->pregs[PR_CCS] \|= P_FLAG;
	251
	252	/* Always set the M flag. */
	253	env->pregs[PR_CCS] \|= M_FLAG;
	254	}
	255
c38ac98d EI	256	uint32_t helper_lz(uint32_t t0)
	257	{
	258	return clz32(t0);
	259	}
	260
abd5c94e EI	261	uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
	262	{
	263	/* FIXME: clean this up. */
	264
	265	/* des ref:
	266	The N flag is set according to the selected bit in the dest reg.
	267	The Z flag is set if the selected bit and all bits to the right are
	268	zero.
	269	The X flag is cleared.
	270	Other flags are left untouched.
	271	The destination reg is not affected.*/
	272	unsigned int fz, sbit, bset, mask, masked_t0;
	273
	274	sbit = t1 & 31;
	275	bset = !!(t0 & (1 << sbit));
	276	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	277	masked_t0 = t0 & mask;
	278	fz = !(masked_t0 \| bset);
	279
	280	/* Clear the X, N and Z flags. */
	281	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
95475216 EI	282	if (env->pregs[PR_VR] < 32)
95475216 EI	283	ccs &= ~(V_FLAG \| C_FLAG);
abd5c94e EI	284	/* Set the N and Z flags accordingly. */
	285	ccs \|= (bset << 3) \| (fz << 2);
	286	return ccs;
	287	}
	288
6231868b	289	static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
b41f7df0	290	{
a8cf66bb	291	unsigned int x, z, mask;
b41f7df0 EI	292
b41f7df0 EI	293	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	294	x = env->cc_x;
a8cf66bb EI	295	mask = env->cc_mask \| X_FLAG;
	296	if (x) {
	297	z = flags & Z_FLAG;
	298	mask = mask & ~z;
	299	}
	300	flags &= mask;
b41f7df0 EI	301
b41f7df0 EI	302	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	303	ccs &= ~mask;
	304	ccs \|= flags;
	305	return ccs;
b41f7df0 EI	306	}
b41f7df0 EI	307
6231868b	308	uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	309	{
b41f7df0	310	uint32_t flags = 0;
dceaf394	311	int64_t tmp;
b41f7df0 EI	312	int dneg;
b41f7df0 EI	313
b41f7df0 EI	314	dneg = ((int32_t)res) < 0;
b41f7df0 EI	315
dceaf394 EI	316	tmp = mof;
	317	tmp <<= 32;
	318	tmp \|= res;
b41f7df0 EI	319	if (tmp == 0)
	320	flags \|= Z_FLAG;
	321	else if (tmp < 0)
	322	flags \|= N_FLAG;
	323	if ((dneg && mof != -1)
	324	\|\| (!dneg && mof != 0))
	325	flags \|= V_FLAG;
6231868b	326	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	327	}
b41f7df0 EI	328
6231868b	329	uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	330	{
b41f7df0	331	uint32_t flags = 0;
dceaf394	332	uint64_t tmp;
b41f7df0	333
dceaf394 EI	334	tmp = mof;
	335	tmp <<= 32;
	336	tmp \|= res;
b41f7df0 EI	337	if (tmp == 0)
	338	flags \|= Z_FLAG;
	339	else if (tmp >> 63)
	340	flags \|= N_FLAG;
	341	if (mof)
	342	flags \|= V_FLAG;
	343
6231868b	344	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	345	}
b41f7df0 EI	346
6231868b EI	347	uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
6231868b EI	348	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	349	{
b41f7df0 EI	350	uint32_t flags = 0;
b41f7df0 EI	351
6231868b EI	352	src = src & 0x80000000;
6231868b EI	353	dst = dst & 0x80000000;
b41f7df0 EI	354
	355	if ((res & 0x80000000L) != 0L)
	356	{
	357	flags \|= N_FLAG;
a8cf66bb	358	if (!src && !dst)
b41f7df0	359	flags \|= V_FLAG;
a8cf66bb	360	else if (src & dst)
b41f7df0	361	flags \|= R_FLAG;
b41f7df0 EI	362	}
	363	else
	364	{
	365	if (res == 0L)
	366	flags \|= Z_FLAG;
a8cf66bb	367	if (src & dst)
b41f7df0	368	flags \|= V_FLAG;
a8cf66bb	369	if (dst \| src)
b41f7df0 EI	370	flags \|= R_FLAG;
	371	}
	372
6231868b	373	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	374	}
b41f7df0 EI	375
6231868b EI	376	uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
6231868b EI	377	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	378	{
b41f7df0 EI	379	uint32_t flags = 0;
b41f7df0 EI	380
6231868b EI	381	src = src & 0x80000000;
6231868b EI	382	dst = dst & 0x80000000;
30abcfc7	383
a8cf66bb	384	if ((res & 0x80000000L) != 0L)
30abcfc7	385	{
a8cf66bb EI	386	flags \|= N_FLAG;
	387	if (!src && !dst)
	388	flags \|= V_FLAG;
	389	else if (src & dst)
	390	flags \|= C_FLAG;
	391	}
	392	else
	393	{
	394	if (res == 0L)
	395	flags \|= Z_FLAG;
	396	if (src & dst)
	397	flags \|= V_FLAG;
	398	if (dst \| src)
	399	flags \|= C_FLAG;
30abcfc7 EI	400	}
30abcfc7 EI	401
6231868b	402	return evaluate_flags_writeback(flags, ccs);
a8cf66bb EI	403	}
a8cf66bb EI	404
6231868b EI	405	uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
6231868b EI	406	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	407	{
a8cf66bb EI	408	uint32_t flags = 0;
a8cf66bb EI	409
6231868b EI	410	src = (~src) & 0x80000000;
6231868b EI	411	dst = dst & 0x80000000;
b41f7df0 EI	412
	413	if ((res & 0x80000000L) != 0L)
	414	{
	415	flags \|= N_FLAG;
a8cf66bb	416	if (!src && !dst)
b41f7df0	417	flags \|= V_FLAG;
a8cf66bb	418	else if (src & dst)
b41f7df0	419	flags \|= C_FLAG;
b41f7df0 EI	420	}
	421	else
	422	{
	423	if (res == 0L)
	424	flags \|= Z_FLAG;
a8cf66bb	425	if (src & dst)
b41f7df0	426	flags \|= V_FLAG;
a8cf66bb	427	if (dst \| src)
b41f7df0 EI	428	flags \|= C_FLAG;
	429	}
	430
a8cf66bb	431	flags ^= C_FLAG;
6231868b	432	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	433	}
b41f7df0 EI	434
6231868b	435	uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
b41f7df0	436	{
b41f7df0 EI	437	uint32_t flags = 0;
b41f7df0 EI	438
b41f7df0 EI	439	if ((int32_t)res < 0)
	440	flags \|= N_FLAG;
	441	else if (res == 0L)
	442	flags \|= Z_FLAG;
	443
6231868b	444	return evaluate_flags_writeback(flags, ccs);
b41f7df0	445	}
6231868b	446	uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
b41f7df0	447	{
b41f7df0	448	uint32_t flags = 0;
b41f7df0 EI	449
	450	if ((int16_t)res < 0L)
	451	flags \|= N_FLAG;
	452	else if (res == 0)
	453	flags \|= Z_FLAG;
	454
6231868b	455	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	456	}
	457
	458	/* TODO: This is expensive. We could split things up and only evaluate part of
	459	CCR on a need to know basis. For now, we simply re-evaluate everything. */
6231868b	460	void helper_evaluate_flags(void)
b41f7df0	461	{
6231868b	462	uint32_t src, dst, res;
b41f7df0 EI	463	uint32_t flags = 0;
	464
	465	src = env->cc_src;
	466	dst = env->cc_dest;
	467	res = env->cc_result;
	468
30abcfc7 EI	469	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	470	src = ~src;
b41f7df0 EI	471
	472	/* Now, evaluate the flags. This stuff is based on
	473	Per Zander's CRISv10 simulator. */
	474	switch (env->cc_size)
	475	{
	476	case 1:
	477	if ((res & 0x80L) != 0L)
	478	{
	479	flags \|= N_FLAG;
	480	if (((src & 0x80L) == 0L)
	481	&& ((dst & 0x80L) == 0L))
	482	{
	483	flags \|= V_FLAG;
	484	}
	485	else if (((src & 0x80L) != 0L)
	486	&& ((dst & 0x80L) != 0L))
	487	{
	488	flags \|= C_FLAG;
	489	}
	490	}
	491	else
	492	{
	493	if ((res & 0xFFL) == 0L)
	494	{
	495	flags \|= Z_FLAG;
	496	}
	497	if (((src & 0x80L) != 0L)
	498	&& ((dst & 0x80L) != 0L))
	499	{
	500	flags \|= V_FLAG;
	501	}
	502	if ((dst & 0x80L) != 0L
	503	\|\| (src & 0x80L) != 0L)
	504	{
	505	flags \|= C_FLAG;
	506	}
	507	}
	508	break;
	509	case 2:
	510	if ((res & 0x8000L) != 0L)
	511	{
	512	flags \|= N_FLAG;
	513	if (((src & 0x8000L) == 0L)
	514	&& ((dst & 0x8000L) == 0L))
	515	{
	516	flags \|= V_FLAG;
	517	}
	518	else if (((src & 0x8000L) != 0L)
	519	&& ((dst & 0x8000L) != 0L))
	520	{
	521	flags \|= C_FLAG;
	522	}
	523	}
	524	else
	525	{
	526	if ((res & 0xFFFFL) == 0L)
	527	{
	528	flags \|= Z_FLAG;
	529	}
	530	if (((src & 0x8000L) != 0L)
	531	&& ((dst & 0x8000L) != 0L))
	532	{
	533	flags \|= V_FLAG;
	534	}
535	if ((dst & 0x8000L) != 0L
536	\|\| (src & 0x8000L) != 0L)
537	{
538	flags \|= C_FLAG;
539	}
540	}
541	break;
542	case 4:
543	if ((res & 0x80000000L) != 0L)
544	{
545	flags \|= N_FLAG;
546	if (((src & 0x80000000L) == 0L)
547	&& ((dst & 0x80000000L) == 0L))
548	{
549	flags \|= V_FLAG;
550	}
551	else if (((src & 0x80000000L) != 0L) &&
552	((dst & 0x80000000L) != 0L))
553	{
554	flags \|= C_FLAG;
555	}
556	}
557	else
558	{
559	if (res == 0L)
560	flags \|= Z_FLAG;
561	if (((src & 0x80000000L) != 0L)
562	&& ((dst & 0x80000000L) != 0L))
563	flags \|= V_FLAG;
564	if ((dst & 0x80000000L) != 0L
565	\|\| (src & 0x80000000L) != 0L)
566	flags \|= C_FLAG;
567	}
568	break;
569	default:
570	break;
571	}
572
6231868b	573	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	574	flags ^= C_FLAG;
6231868b EI	575
6231868b EI	576	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
b41f7df0	577	}
30abcfc7 EI	578
	579	void helper_top_evaluate_flags(void)
	580	{
	581	switch (env->cc_op)
	582	{
	583	case CC_OP_MCP:
6231868b EI	584	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
	585	env->pregs[PR_CCS], env->cc_src,
	586	env->cc_dest, env->cc_result);
30abcfc7 EI	587	break;
30abcfc7 EI	588	case CC_OP_MULS:
6231868b EI	589	env->pregs[PR_CCS] = helper_evaluate_flags_muls(
	590	env->pregs[PR_CCS], env->cc_result,
	591	env->pregs[PR_MOF]);
30abcfc7 EI	592	break;
30abcfc7 EI	593	case CC_OP_MULU:
6231868b EI	594	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
	595	env->pregs[PR_CCS], env->cc_result,
	596	env->pregs[PR_MOF]);
30abcfc7 EI	597	break;
	598	case CC_OP_MOVE:
	599	case CC_OP_AND:
	600	case CC_OP_OR:
	601	case CC_OP_XOR:
	602	case CC_OP_ASR:
	603	case CC_OP_LSR:
	604	case CC_OP_LSL:
6231868b EI	605	switch (env->cc_size)
	606	{
	607	case 4:
	608	env->pregs[PR_CCS] =
	609	helper_evaluate_flags_move_4(
	610	env->pregs[PR_CCS],
	611	env->cc_result);
	612	break;
	613	case 2:
	614	env->pregs[PR_CCS] =
	615	helper_evaluate_flags_move_2(
	616	env->pregs[PR_CCS],
	617	env->cc_result);
	618	break;
	619	default:
	620	helper_evaluate_flags();
	621	break;
	622	}
	623	break;
30abcfc7 EI	624	case CC_OP_FLAGS:
	625	/* live. */
	626	break;
a8cf66bb EI	627	case CC_OP_SUB:
	628	case CC_OP_CMP:
	629	if (env->cc_size == 4)
6231868b EI	630	env->pregs[PR_CCS] =
	631	helper_evaluate_flags_sub_4(
	632	env->pregs[PR_CCS],
	633	env->cc_src, env->cc_dest,
	634	env->cc_result);
a8cf66bb EI	635	else
	636	helper_evaluate_flags();
	637	break;
30abcfc7 EI	638	default:
	639	{
	640	switch (env->cc_size)
	641	{
6231868b EI	642	case 4:
	643	env->pregs[PR_CCS] =
	644	helper_evaluate_flags_alu_4(
	645	env->pregs[PR_CCS],
	646	env->cc_src, env->cc_dest,
	647	env->cc_result);
	648	break;
	649	default:
	650	helper_evaluate_flags();
	651	break;
30abcfc7 EI	652	}
	653	}
	654	break;
	655	}
	656	}