[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "exec.h"
#include "mmu.h"
#include "helper.h"
#include "host-utils.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA__ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)

#define MMUSUFFIX _mmu

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;

    D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__, 
	     env->pc, env->debug1, retaddr);
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc, NULL);

		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags();
            }
        }
        cpu_loop_exit();
    }
    env = saved_env;
}

#endif

void helper_raise_exception(uint32_t index)
{
	env->exception_index = index;
	cpu_loop_exit();
}

void helper_tlb_flush_pid(uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
	tlb_flush_page(env, env->pregs[PR_SPC]);
	tlb_flush_page(env, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
{
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			tlb_flush_page(env, vaddr);
		}
	}
#endif
}

void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(void)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

    /* Always set the M flag.  */
    env->pregs[PR_CCS] |= M_FLAG;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
	return evaluate_flags_writeback(flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

	return evaluate_flags_writeback(flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void  helper_evaluate_flags(void)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(void)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
			env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
			env->pregs[PR_CCS] = helper_evaluate_flags_muls(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
			env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_4(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_move_2(
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
					helper_evaluate_flags_sub_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
				helper_evaluate_flags();
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
					helper_evaluate_flags_alu_4(
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
				helper_evaluate_flags();
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
81fdc5f8	21	#include "exec.h"
786c02f1	22	#include "mmu.h"
30abcfc7	23	#include "helper.h"
c38ac98d	24	#include "host-utils.h"
81fdc5f8	25
d12d51d5 AL	26	//#define CRIS_OP_HELPER_DEBUG
	27
	28
	29	#ifdef CRIS_OP_HELPER_DEBUG
	30	#define D(x) x
93fcfe39	31	#define D_LOG(...) qemu_log(__VA__ARGS__)
d12d51d5	32	#else
e2eef170	33	#define D(x)
d12d51d5 AL	34	#define D_LOG(...) do { } while (0)
d12d51d5 AL	35	#endif
e2eef170 PB	36
	37	#if !defined(CONFIG_USER_ONLY)
	38
81fdc5f8	39	#define MMUSUFFIX _mmu
81fdc5f8 TS	40
	41	#define SHIFT 0
	42	#include "softmmu_template.h"
	43
	44	#define SHIFT 1
	45	#include "softmmu_template.h"
	46
	47	#define SHIFT 2
	48	#include "softmmu_template.h"
	49
	50	#define SHIFT 3
	51	#include "softmmu_template.h"
	52
	53	/* Try to fill the TLB and return an exception if error. If retaddr is
	54	NULL, it means that the function was called in C code (i.e. not
	55	from generated code or from helper.c) */
	56	/* XXX: fix it to restore all registers */
6ebbf390	57	void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
81fdc5f8 TS	58	{
	59	TranslationBlock *tb;
	60	CPUState *saved_env;
44f8625d	61	unsigned long pc;
81fdc5f8 TS	62	int ret;
	63
	64	/* XXX: hack to restore env in all cases, even if not called from
	65	generated code */
	66	saved_env = env;
	67	env = cpu_single_env;
b41f7df0	68
d12d51d5 AL	69	D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
d12d51d5 AL	70	env->pc, env->debug1, retaddr);
6ebbf390	71	ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
551bd27f	72	if (unlikely(ret)) {
81fdc5f8 TS	73	if (retaddr) {
81fdc5f8 TS	74	/* now we have a real cpu fault */
44f8625d	75	pc = (unsigned long)retaddr;
81fdc5f8 TS	76	tb = tb_find_pc(pc);
	77	if (tb) {
	78	/* the PC is inside the translated code. It means that we have
	79	a virtual CPU fault */
	80	cpu_restore_state(tb, env, pc, NULL);
30abcfc7 EI	81
	82	/* Evaluate flags after retranslation. */
	83	helper_top_evaluate_flags();
81fdc5f8 TS	84	}
	85	}
	86	cpu_loop_exit();
	87	}
	88	env = saved_env;
	89	}
	90
e2eef170 PB	91	#endif
e2eef170 PB	92
dceaf394	93	void helper_raise_exception(uint32_t index)
786c02f1	94	{
dceaf394 EI	95	env->exception_index = index;
dceaf394 EI	96	cpu_loop_exit();
786c02f1 EI	97	}
786c02f1 EI	98
cf1d97f0 EI	99	void helper_tlb_flush_pid(uint32_t pid)
	100	{
	101	#if !defined(CONFIG_USER_ONLY)
28de16da EI	102	pid &= 0xff;
	103	if (pid != (env->pregs[PR_PID] & 0xff))
	104	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	105	#endif
	106	}
	107
a1aebcb8 EI	108	void helper_spc_write(uint32_t new_spc)
	109	{
	110	#if !defined(CONFIG_USER_ONLY)
	111	tlb_flush_page(env, env->pregs[PR_SPC]);
	112	tlb_flush_page(env, new_spc);
	113	#endif
	114	}
	115
30abcfc7	116	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	117	{
93fcfe39	118	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	119	}
b41f7df0 EI	120
cf1d97f0 EI	121	/* Used by the tlb decoder. */
	122	#define EXTRACT_FIELD(src, start, end) \
	123	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	124
dceaf394 EI	125	void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
	126	{
	127	uint32_t srs;
	128	srs = env->pregs[PR_SRS];
	129	srs &= 3;
	130	env->sregs[srs][sreg] = env->regs[reg];
	131
	132	#if !defined(CONFIG_USER_ONLY)
	133	if (srs == 1 \|\| srs == 2) {
	134	if (sreg == 6) {
	135	/* Writes to tlb-hi write to mm_cause as a side
	136	effect. */
6913ba56 EI	137	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	138	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	139	}
	140	else if (sreg == 5) {
	141	uint32_t set;
	142	uint32_t idx;
	143	uint32_t lo, hi;
	144	uint32_t vaddr;
cf1d97f0	145	int tlb_v;
dceaf394 EI	146
	147	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	148	set >>= 4;
	149	set &= 3;
	150
	151	idx &= 15;
	152	/* We've just made a write to tlb_lo. */
	153	lo = env->sregs[SFR_RW_MM_TLB_LO];
	154	/* Writes are done via r_mm_cause. */
	155	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	156
	157	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	158	13, 31);
	159	vaddr <<= TARGET_PAGE_BITS;
	160	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	161	3, 3);
dceaf394 EI	162	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	163	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	164
d12d51d5 AL	165	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	166	vaddr, tlb_v, env->pc);
cf1d97f0	167	tlb_flush_page(env, vaddr);
dceaf394 EI	168	}
	169	}
	170	#endif
	171	}
	172
	173	void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
	174	{
	175	uint32_t srs;
	176	env->pregs[PR_SRS] &= 3;
	177	srs = env->pregs[PR_SRS];
	178
	179	#if !defined(CONFIG_USER_ONLY)
	180	if (srs == 1 \|\| srs == 2)
	181	{
	182	uint32_t set;
	183	uint32_t idx;
	184	uint32_t lo, hi;
	185
	186	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	187	set >>= 4;
	188	set &= 3;
	189	idx &= 15;
	190
	191	/* Update the mirror regs. */
	192	hi = env->tlbsets[srs - 1][set][idx].hi;
	193	lo = env->tlbsets[srs - 1][set][idx].lo;
	194	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	195	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	196	}
	197	#endif
	198	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	199	}
	200
	201	static void cris_ccs_rshift(CPUState *env)
	202	{
	203	uint32_t ccs;
	204
	205	/* Apply the ccs shift. */
	206	ccs = env->pregs[PR_CCS];
	207	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	208	if (ccs & U_FLAG)
	209	{
	210	/* Enter user mode. */
	211	env->ksp = env->regs[R_SP];
	212	env->regs[R_SP] = env->pregs[PR_USP];
	213	}
	214
	215	env->pregs[PR_CCS] = ccs;
	216	}
	217
b41f7df0 EI	218	void helper_rfe(void)
b41f7df0 EI	219	{
bf443337 EI	220	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	221
d12d51d5	222	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	223	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	224	env->pregs[PR_CCS],
d12d51d5	225	env->btarget);
dceaf394 EI	226
	227	cris_ccs_rshift(env);
	228
	229	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	230	if (!rflag)
dceaf394	231	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	232	}
b41f7df0 EI	233
5bf8f1ab EI	234	void helper_rfn(void)
	235	{
	236	int rflag = env->pregs[PR_CCS] & R_FLAG;
	237
d12d51d5	238	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	239	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	240	env->pregs[PR_CCS],
d12d51d5	241	env->btarget);
5bf8f1ab EI	242
	243	cris_ccs_rshift(env);
	244
	245	/* Set the P_FLAG only if the R_FLAG is not set. */
	246	if (!rflag)
	247	env->pregs[PR_CCS] \|= P_FLAG;
	248
	249	/* Always set the M flag. */
	250	env->pregs[PR_CCS] \|= M_FLAG;
	251	}
	252
c38ac98d EI	253	uint32_t helper_lz(uint32_t t0)
	254	{
	255	return clz32(t0);
	256	}
	257
abd5c94e EI	258	uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
	259	{
	260	/* FIXME: clean this up. */
	261
	262	/* des ref:
	263	The N flag is set according to the selected bit in the dest reg.
	264	The Z flag is set if the selected bit and all bits to the right are
	265	zero.
	266	The X flag is cleared.
	267	Other flags are left untouched.
	268	The destination reg is not affected.*/
	269	unsigned int fz, sbit, bset, mask, masked_t0;
	270
	271	sbit = t1 & 31;
	272	bset = !!(t0 & (1 << sbit));
	273	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	274	masked_t0 = t0 & mask;
	275	fz = !(masked_t0 \| bset);
	276
	277	/* Clear the X, N and Z flags. */
	278	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
	279	/* Set the N and Z flags accordingly. */
	280	ccs \|= (bset << 3) \| (fz << 2);
	281	return ccs;
	282	}
	283
6231868b	284	static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
b41f7df0	285	{
a8cf66bb	286	unsigned int x, z, mask;
b41f7df0 EI	287
b41f7df0 EI	288	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	289	x = env->cc_x;
a8cf66bb EI	290	mask = env->cc_mask \| X_FLAG;
	291	if (x) {
	292	z = flags & Z_FLAG;
	293	mask = mask & ~z;
	294	}
	295	flags &= mask;
b41f7df0 EI	296
b41f7df0 EI	297	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	298	ccs &= ~mask;
	299	ccs \|= flags;
	300	return ccs;
b41f7df0 EI	301	}
b41f7df0 EI	302
6231868b	303	uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	304	{
b41f7df0	305	uint32_t flags = 0;
dceaf394	306	int64_t tmp;
b41f7df0 EI	307	int dneg;
b41f7df0 EI	308
b41f7df0 EI	309	dneg = ((int32_t)res) < 0;
b41f7df0 EI	310
dceaf394 EI	311	tmp = mof;
	312	tmp <<= 32;
	313	tmp \|= res;
b41f7df0 EI	314	if (tmp == 0)
	315	flags \|= Z_FLAG;
	316	else if (tmp < 0)
	317	flags \|= N_FLAG;
	318	if ((dneg && mof != -1)
	319	\|\| (!dneg && mof != 0))
	320	flags \|= V_FLAG;
6231868b	321	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	322	}
b41f7df0 EI	323
6231868b	324	uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	325	{
b41f7df0	326	uint32_t flags = 0;
dceaf394	327	uint64_t tmp;
b41f7df0	328
dceaf394 EI	329	tmp = mof;
	330	tmp <<= 32;
	331	tmp \|= res;
b41f7df0 EI	332	if (tmp == 0)
	333	flags \|= Z_FLAG;
	334	else if (tmp >> 63)
	335	flags \|= N_FLAG;
	336	if (mof)
	337	flags \|= V_FLAG;
	338
6231868b	339	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	340	}
b41f7df0 EI	341
6231868b EI	342	uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
6231868b EI	343	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	344	{
b41f7df0 EI	345	uint32_t flags = 0;
b41f7df0 EI	346
6231868b EI	347	src = src & 0x80000000;
6231868b EI	348	dst = dst & 0x80000000;
b41f7df0 EI	349
	350	if ((res & 0x80000000L) != 0L)
	351	{
	352	flags \|= N_FLAG;
a8cf66bb	353	if (!src && !dst)
b41f7df0	354	flags \|= V_FLAG;
a8cf66bb	355	else if (src & dst)
b41f7df0	356	flags \|= R_FLAG;
b41f7df0 EI	357	}
	358	else
	359	{
	360	if (res == 0L)
	361	flags \|= Z_FLAG;
a8cf66bb	362	if (src & dst)
b41f7df0	363	flags \|= V_FLAG;
a8cf66bb	364	if (dst \| src)
b41f7df0 EI	365	flags \|= R_FLAG;
	366	}
	367
6231868b	368	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	369	}
b41f7df0 EI	370
6231868b EI	371	uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
6231868b EI	372	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	373	{
b41f7df0 EI	374	uint32_t flags = 0;
b41f7df0 EI	375
6231868b EI	376	src = src & 0x80000000;
6231868b EI	377	dst = dst & 0x80000000;
30abcfc7	378
a8cf66bb	379	if ((res & 0x80000000L) != 0L)
30abcfc7	380	{
a8cf66bb EI	381	flags \|= N_FLAG;
	382	if (!src && !dst)
	383	flags \|= V_FLAG;
	384	else if (src & dst)
	385	flags \|= C_FLAG;
	386	}
	387	else
	388	{
	389	if (res == 0L)
	390	flags \|= Z_FLAG;
	391	if (src & dst)
	392	flags \|= V_FLAG;
	393	if (dst \| src)
	394	flags \|= C_FLAG;
30abcfc7 EI	395	}
30abcfc7 EI	396
6231868b	397	return evaluate_flags_writeback(flags, ccs);
a8cf66bb EI	398	}
a8cf66bb EI	399
6231868b EI	400	uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
6231868b EI	401	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	402	{
a8cf66bb EI	403	uint32_t flags = 0;
a8cf66bb EI	404
6231868b EI	405	src = (~src) & 0x80000000;
6231868b EI	406	dst = dst & 0x80000000;
b41f7df0 EI	407
	408	if ((res & 0x80000000L) != 0L)
	409	{
	410	flags \|= N_FLAG;
a8cf66bb	411	if (!src && !dst)
b41f7df0	412	flags \|= V_FLAG;
a8cf66bb	413	else if (src & dst)
b41f7df0	414	flags \|= C_FLAG;
b41f7df0 EI	415	}
	416	else
	417	{
	418	if (res == 0L)
	419	flags \|= Z_FLAG;
a8cf66bb	420	if (src & dst)
b41f7df0	421	flags \|= V_FLAG;
a8cf66bb	422	if (dst \| src)
b41f7df0 EI	423	flags \|= C_FLAG;
	424	}
	425
a8cf66bb	426	flags ^= C_FLAG;
6231868b	427	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	428	}
b41f7df0 EI	429
6231868b	430	uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
b41f7df0	431	{
b41f7df0 EI	432	uint32_t flags = 0;
b41f7df0 EI	433
b41f7df0 EI	434	if ((int32_t)res < 0)
	435	flags \|= N_FLAG;
	436	else if (res == 0L)
	437	flags \|= Z_FLAG;
	438
6231868b	439	return evaluate_flags_writeback(flags, ccs);
b41f7df0	440	}
6231868b	441	uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
b41f7df0	442	{
b41f7df0	443	uint32_t flags = 0;
b41f7df0 EI	444
	445	if ((int16_t)res < 0L)
	446	flags \|= N_FLAG;
	447	else if (res == 0)
	448	flags \|= Z_FLAG;
	449
6231868b	450	return evaluate_flags_writeback(flags, ccs);
b41f7df0 EI	451	}
	452
	453	/* TODO: This is expensive. We could split things up and only evaluate part of
	454	CCR on a need to know basis. For now, we simply re-evaluate everything. */
6231868b	455	void helper_evaluate_flags(void)
b41f7df0	456	{
6231868b	457	uint32_t src, dst, res;
b41f7df0 EI	458	uint32_t flags = 0;
	459
	460	src = env->cc_src;
	461	dst = env->cc_dest;
	462	res = env->cc_result;
	463
30abcfc7 EI	464	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	465	src = ~src;
b41f7df0 EI	466
	467	/* Now, evaluate the flags. This stuff is based on
	468	Per Zander's CRISv10 simulator. */
	469	switch (env->cc_size)
	470	{
	471	case 1:
	472	if ((res & 0x80L) != 0L)
	473	{
	474	flags \|= N_FLAG;
	475	if (((src & 0x80L) == 0L)
	476	&& ((dst & 0x80L) == 0L))
	477	{
	478	flags \|= V_FLAG;
	479	}
	480	else if (((src & 0x80L) != 0L)
	481	&& ((dst & 0x80L) != 0L))
	482	{
	483	flags \|= C_FLAG;
	484	}
	485	}
	486	else
	487	{
	488	if ((res & 0xFFL) == 0L)
	489	{
	490	flags \|= Z_FLAG;
	491	}
	492	if (((src & 0x80L) != 0L)
	493	&& ((dst & 0x80L) != 0L))
	494	{
	495	flags \|= V_FLAG;
	496	}
	497	if ((dst & 0x80L) != 0L
	498	\|\| (src & 0x80L) != 0L)
	499	{
	500	flags \|= C_FLAG;
	501	}
	502	}
	503	break;
	504	case 2:
	505	if ((res & 0x8000L) != 0L)
	506	{
	507	flags \|= N_FLAG;
	508	if (((src & 0x8000L) == 0L)
	509	&& ((dst & 0x8000L) == 0L))
	510	{
	511	flags \|= V_FLAG;
	512	}
	513	else if (((src & 0x8000L) != 0L)
	514	&& ((dst & 0x8000L) != 0L))
	515	{
	516	flags \|= C_FLAG;
	517	}
	518	}
	519	else
	520	{
	521	if ((res & 0xFFFFL) == 0L)
	522	{
	523	flags \|= Z_FLAG;
	524	}
	525	if (((src & 0x8000L) != 0L)
	526	&& ((dst & 0x8000L) != 0L))
	527	{
	528	flags \|= V_FLAG;
	529	}
530	if ((dst & 0x8000L) != 0L
531	\|\| (src & 0x8000L) != 0L)
532	{
533	flags \|= C_FLAG;
534	}
535	}
536	break;
537	case 4:
538	if ((res & 0x80000000L) != 0L)
539	{
540	flags \|= N_FLAG;
541	if (((src & 0x80000000L) == 0L)
542	&& ((dst & 0x80000000L) == 0L))
543	{
544	flags \|= V_FLAG;
545	}
546	else if (((src & 0x80000000L) != 0L) &&
547	((dst & 0x80000000L) != 0L))
548	{
549	flags \|= C_FLAG;
550	}
551	}
552	else
553	{
554	if (res == 0L)
555	flags \|= Z_FLAG;
556	if (((src & 0x80000000L) != 0L)
557	&& ((dst & 0x80000000L) != 0L))
558	flags \|= V_FLAG;
559	if ((dst & 0x80000000L) != 0L
560	\|\| (src & 0x80000000L) != 0L)
561	flags \|= C_FLAG;
562	}
563	break;
564	default:
565	break;
566	}
567
6231868b	568	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	569	flags ^= C_FLAG;
6231868b EI	570
6231868b EI	571	env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
b41f7df0	572	}
30abcfc7 EI	573
	574	void helper_top_evaluate_flags(void)
	575	{
	576	switch (env->cc_op)
	577	{
	578	case CC_OP_MCP:
6231868b EI	579	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
	580	env->pregs[PR_CCS], env->cc_src,
	581	env->cc_dest, env->cc_result);
30abcfc7 EI	582	break;
30abcfc7 EI	583	case CC_OP_MULS:
6231868b EI	584	env->pregs[PR_CCS] = helper_evaluate_flags_muls(
	585	env->pregs[PR_CCS], env->cc_result,
	586	env->pregs[PR_MOF]);
30abcfc7 EI	587	break;
30abcfc7 EI	588	case CC_OP_MULU:
6231868b EI	589	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
	590	env->pregs[PR_CCS], env->cc_result,
	591	env->pregs[PR_MOF]);
30abcfc7 EI	592	break;
	593	case CC_OP_MOVE:
	594	case CC_OP_AND:
	595	case CC_OP_OR:
	596	case CC_OP_XOR:
	597	case CC_OP_ASR:
	598	case CC_OP_LSR:
	599	case CC_OP_LSL:
6231868b EI	600	switch (env->cc_size)
	601	{
	602	case 4:
	603	env->pregs[PR_CCS] =
	604	helper_evaluate_flags_move_4(
	605	env->pregs[PR_CCS],
	606	env->cc_result);
	607	break;
	608	case 2:
	609	env->pregs[PR_CCS] =
	610	helper_evaluate_flags_move_2(
	611	env->pregs[PR_CCS],
	612	env->cc_result);
	613	break;
	614	default:
	615	helper_evaluate_flags();
	616	break;
	617	}
	618	break;
30abcfc7 EI	619	case CC_OP_FLAGS:
	620	/* live. */
	621	break;
a8cf66bb EI	622	case CC_OP_SUB:
	623	case CC_OP_CMP:
	624	if (env->cc_size == 4)
6231868b EI	625	env->pregs[PR_CCS] =
	626	helper_evaluate_flags_sub_4(
	627	env->pregs[PR_CCS],
	628	env->cc_src, env->cc_dest,
	629	env->cc_result);
a8cf66bb EI	630	else
	631	helper_evaluate_flags();
	632	break;
30abcfc7 EI	633	default:
	634	{
	635	switch (env->cc_size)
	636	{
6231868b EI	637	case 4:
	638	env->pregs[PR_CCS] =
	639	helper_evaluate_flags_alu_4(
	640	env->pregs[PR_CCS],
	641	env->cc_src, env->cc_dest,
	642	env->cc_result);
	643	break;
	644	default:
	645	helper_evaluate_flags();
	646	break;
30abcfc7 EI	647	}
	648	}
	649	break;
	650	}
	651	}