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8170028d
TS		 1/*
2 * CRIS emulation for qemu: main translation routines.
3 *
05ba7d5f 4 * Copyright (c) 2008 AXIS Communications AB
8170028d
TS		 5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
b41f7df0
EI		 22/*
23 * FIXME:
cf1d97f0 24 * The condition code translation is in need of attention.
b41f7df0
EI		 25 */
26
8170028d
TS		 27#include <stdarg.h>
28#include <stdlib.h>
29#include <stdio.h>
30#include <string.h>
31#include <inttypes.h>
32#include <assert.h>
33
34#include "cpu.h"
35#include "exec-all.h"
36#include "disas.h"
57fec1fe 37#include "tcg-op.h"
05ba7d5f 38#include "helper.h"
8170028d 39#include "crisv32-decode.h"
ca10f867 40#include "qemu-common.h"
8170028d 41
8170028d
TS		 42#define DISAS_CRIS 0
43#if DISAS_CRIS
44#define DIS(x) x
45#else
46#define DIS(x)
47#endif
48
b41f7df0 49#define D(x)
8170028d
TS		 50#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51#define BUG_ON(x) ({if (x) BUG();})
52
4f400ab5
EI		 53#define DISAS_SWI 5
54
8170028d
TS		 55/* Used by the decoder. */
56#define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
58
59#define CC_MASK_NZ 0xc
60#define CC_MASK_NZV 0xe
61#define CC_MASK_NZVC 0xf
62#define CC_MASK_RNZV 0x10e
63
a825e703
EI		 64TCGv cpu_env;
65TCGv cpu_T[2];
66TCGv cpu_R[16];
67TCGv cpu_PR[16];
30abcfc7 68TCGv cc_x;
a825e703
EI		 69TCGv cc_src;
70TCGv cc_dest;
71TCGv cc_result;
72TCGv cc_op;
73TCGv cc_size;
74TCGv cc_mask;
05ba7d5f 75
2a44f7f1 76TCGv env_btaken;
b41f7df0
EI		 77TCGv env_btarget;
78TCGv env_pc;
79
8170028d
TS		 80/* This is the state at translation time. */
81typedef struct DisasContext {
82 CPUState *env;
b41f7df0 83 target_ulong pc, ppc;
8170028d
TS		 84
85 /* Decoder. */
86 uint32_t ir;
87 uint32_t opcode;
88 unsigned int op1;
89 unsigned int op2;
90 unsigned int zsize, zzsize;
91 unsigned int mode;
92 unsigned int postinc;
93
8170028d
TS		 94 int update_cc;
95 int cc_op;
96 int cc_size;
97 uint32_t cc_mask;
30abcfc7
EI		 98
99 int cc_size_uptodate; /* -1 invalid or last written value. */
100
101 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
102 int flags_uptodate; /* Wether or not $ccs is uptodate. */
103 int flagx_known; /* Wether or not flags_x has the x flag known at
104 translation time. */
8170028d 105 int flags_x;
8170028d 106
30abcfc7 107 int clear_x; /* Clear x after this insn? */
2a44f7f1
EI		 108 int cpustate_changed;
109 unsigned int tb_flags; /* tb dependent flags. */
8170028d 110 int is_jmp;
8170028d 111
2a44f7f1
EI		 112#define JMP_NOJMP 0
113#define JMP_DIRECT 1
114#define JMP_INDIRECT 2
115 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
116 uint32_t jmp_pc;
117
8170028d 118 int delayed_branch;
8170028d
TS		 119
120 struct TranslationBlock *tb;
121 int singlestep_enabled;
122} DisasContext;
123
8170028d
TS		 124static void gen_BUG(DisasContext *dc, char *file, int line)
125{
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
cf1d97f0 128 cpu_abort(dc->env, "%s:%d\n", file, line);
8170028d
TS		 129}
130
a825e703
EI		 131const char *regnames[] =
132{
133 "$r0", "$r1", "$r2", "$r3",
134 "$r4", "$r5", "$r6", "$r7",
135 "$r8", "$r9", "$r10", "$r11",
136 "$r12", "$r13", "$sp", "$acr",
137};
138const char *pregnames[] =
139{
140 "$bz", "$vr", "$pid", "$srs",
141 "$wz", "$exs", "$eda", "$mof",
142 "$dz", "$ebp", "$erp", "$srp",
143 "$nrp", "$ccs", "$usp", "$spc",
144};
145
05ba7d5f
EI		 146/* We need this table to handle preg-moves with implicit width. */
147int preg_sizes[] = {
148 1, /* bz. */
149 1, /* vr. */
150 4, /* pid. */
151 1, /* srs. */
152 2, /* wz. */
153 4, 4, 4,
154 4, 4, 4, 4,
155 4, 4, 4, 4,
156};
157
158#define t_gen_mov_TN_env(tn, member) \
3157a0a9 159 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
05ba7d5f 160#define t_gen_mov_env_TN(member, tn) \
3157a0a9 161 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
05ba7d5f 162
b41f7df0
EI		 163static inline void t_gen_mov_TN_reg(TCGv tn, int r)
164{
165 if (r < 0 || r > 15)
166 fprintf(stderr, "wrong register read $r%d\n", r);
167 tcg_gen_mov_tl(tn, cpu_R[r]);
168}
169static inline void t_gen_mov_reg_TN(int r, TCGv tn)
170{
171 if (r < 0 || r > 15)
172 fprintf(stderr, "wrong register write $r%d\n", r);
173 tcg_gen_mov_tl(cpu_R[r], tn);
174}
05ba7d5f
EI		 175
176static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
177{
b41f7df0
EI		 178 if (offset > sizeof (CPUState))
179 fprintf(stderr, "wrong load from env from off=%d\n", offset);
05ba7d5f
EI		 180 tcg_gen_ld_tl(tn, cpu_env, offset);
181}
182static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
183{
b41f7df0
EI		 184 if (offset > sizeof (CPUState))
185 fprintf(stderr, "wrong store to env at off=%d\n", offset);
05ba7d5f
EI		 186 tcg_gen_st_tl(tn, cpu_env, offset);
187}
188
189static inline void t_gen_mov_TN_preg(TCGv tn, int r)
190{
b41f7df0
EI		 191 if (r < 0 || r > 15)
192 fprintf(stderr, "wrong register read $p%d\n", r);
05ba7d5f 193 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
3157a0a9 194 tcg_gen_mov_tl(tn, tcg_const_tl(0));
05ba7d5f 195 else if (r == PR_VR)
3157a0a9 196 tcg_gen_mov_tl(tn, tcg_const_tl(32));
b41f7df0
EI		 197 else if (r == PR_EXS) {
198 printf("read from EXS!\n");
199 tcg_gen_mov_tl(tn, cpu_PR[r]);
200 }
201 else if (r == PR_EDA) {
202 printf("read from EDA!\n");
203 tcg_gen_mov_tl(tn, cpu_PR[r]);
204 }
05ba7d5f 205 else
a825e703 206 tcg_gen_mov_tl(tn, cpu_PR[r]);
05ba7d5f 207}
cf1d97f0 208static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
05ba7d5f 209{
b41f7df0
EI		 210 if (r < 0 || r > 15)
211 fprintf(stderr, "wrong register write $p%d\n", r);
05ba7d5f
EI		 212 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
213 return;
b41f7df0
EI		 214 else if (r == PR_SRS)
215 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
216 else {
a825e703 217 tcg_gen_mov_tl(cpu_PR[r], tn);
2a44f7f1 218 if (r == PR_PID)
cf1d97f0 219 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
2a44f7f1
EI		 220 else if (r == PR_CCS)
221 dc->cpustate_changed = 1;
b41f7df0 222 }
05ba7d5f
EI		 223}
224
dceaf394 225static inline void t_gen_raise_exception(uint32_t index)
05ba7d5f 226{
dceaf394 227 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
05ba7d5f
EI		 228}
229
230static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
231{
232 int l1;
233
234 l1 = gen_new_label();
235 /* Speculative shift. */
236 tcg_gen_shl_tl(d, a, b);
cb63669a 237 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
05ba7d5f
EI		 238 /* Clear dst if shift operands were to large. */
239 tcg_gen_movi_tl(d, 0);
240 gen_set_label(l1);
241}
242
243static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
244{
245 int l1;
246
247 l1 = gen_new_label();
248 /* Speculative shift. */
249 tcg_gen_shr_tl(d, a, b);
cb63669a 250 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
05ba7d5f
EI		 251 /* Clear dst if shift operands were to large. */
252 tcg_gen_movi_tl(d, 0);
253 gen_set_label(l1);
254}
255
256static void t_gen_asr(TCGv d, TCGv a, TCGv b)
257{
258 int l1;
259
260 l1 = gen_new_label();
261 /* Speculative shift. */
262 tcg_gen_sar_tl(d, a, b);
cb63669a 263 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
05ba7d5f 264 /* Clear dst if shift operands were to large. */
b41f7df0 265 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
05ba7d5f
EI		 266 gen_set_label(l1);
267}
268
3157a0a9
EI		 269/* 64-bit signed mul, lower result in d and upper in d2. */
270static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
271{
272 TCGv t0, t1;
273
274 t0 = tcg_temp_new(TCG_TYPE_I64);
275 t1 = tcg_temp_new(TCG_TYPE_I64);
276
277 tcg_gen_ext32s_i64(t0, a);
278 tcg_gen_ext32s_i64(t1, b);
279 tcg_gen_mul_i64(t0, t0, t1);
280
281 tcg_gen_trunc_i64_i32(d, t0);
282 tcg_gen_shri_i64(t0, t0, 32);
283 tcg_gen_trunc_i64_i32(d2, t0);
b41f7df0 284
30abcfc7
EI		 285 tcg_temp_free(t0);
286 tcg_temp_free(t1);
3157a0a9
EI		 287}
288
289/* 64-bit unsigned muls, lower result in d and upper in d2. */
290static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
291{
292 TCGv t0, t1;
293
294 t0 = tcg_temp_new(TCG_TYPE_I64);
295 t1 = tcg_temp_new(TCG_TYPE_I64);
296
297 tcg_gen_extu_i32_i64(t0, a);
298 tcg_gen_extu_i32_i64(t1, b);
299 tcg_gen_mul_i64(t0, t0, t1);
300
301 tcg_gen_trunc_i64_i32(d, t0);
302 tcg_gen_shri_i64(t0, t0, 32);
303 tcg_gen_trunc_i64_i32(d2, t0);
b41f7df0 304
30abcfc7
EI		 305 tcg_temp_free(t0);
306 tcg_temp_free(t1);
3157a0a9
EI		 307}
308
d059c172
EI		 309/* 32bit branch-free binary search for counting leading zeros. */
310static void t_gen_lz_i32(TCGv d, TCGv x)
311{
312 TCGv y, m, n;
313
314 y = tcg_temp_new(TCG_TYPE_I32);
315 m = tcg_temp_new(TCG_TYPE_I32);
316 n = tcg_temp_new(TCG_TYPE_I32);
317
318 /* y = -(x >> 16) */
319 tcg_gen_shri_i32(y, x, 16);
390efc54 320 tcg_gen_neg_i32(y, y);
d059c172
EI		 321
322 /* m = (y >> 16) & 16 */
323 tcg_gen_sari_i32(m, y, 16);
324 tcg_gen_andi_i32(m, m, 16);
325
326 /* n = 16 - m */
327 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
328 /* x = x >> m */
329 tcg_gen_shr_i32(x, x, m);
330
331 /* y = x - 0x100 */
332 tcg_gen_subi_i32(y, x, 0x100);
333 /* m = (y >> 16) & 8 */
334 tcg_gen_sari_i32(m, y, 16);
335 tcg_gen_andi_i32(m, m, 8);
336 /* n = n + m */
337 tcg_gen_add_i32(n, n, m);
338 /* x = x << m */
339 tcg_gen_shl_i32(x, x, m);
340
341 /* y = x - 0x1000 */
342 tcg_gen_subi_i32(y, x, 0x1000);
343 /* m = (y >> 16) & 4 */
344 tcg_gen_sari_i32(m, y, 16);
345 tcg_gen_andi_i32(m, m, 4);
346 /* n = n + m */
347 tcg_gen_add_i32(n, n, m);
348 /* x = x << m */
349 tcg_gen_shl_i32(x, x, m);
350
351 /* y = x - 0x4000 */
352 tcg_gen_subi_i32(y, x, 0x4000);
353 /* m = (y >> 16) & 2 */
354 tcg_gen_sari_i32(m, y, 16);
355 tcg_gen_andi_i32(m, m, 2);
356 /* n = n + m */
357 tcg_gen_add_i32(n, n, m);
358 /* x = x << m */
359 tcg_gen_shl_i32(x, x, m);
360
361 /* y = x >> 14 */
362 tcg_gen_shri_i32(y, x, 14);
363 /* m = y & ~(y >> 1) */
364 tcg_gen_sari_i32(m, y, 1);
d1896336 365 tcg_gen_not_i32(m, m);
d059c172
EI		 366 tcg_gen_and_i32(m, m, y);
367
368 /* d = n + 2 - m */
369 tcg_gen_addi_i32(d, n, 2);
370 tcg_gen_sub_i32(d, d, m);
371
30abcfc7
EI		 372 tcg_temp_free(y);
373 tcg_temp_free(m);
374 tcg_temp_free(n);
d059c172
EI		 375}
376
30abcfc7 377static void t_gen_btst(TCGv d, TCGv a, TCGv b)
dceaf394
EI		 378{
379 TCGv sbit;
380 TCGv bset;
30abcfc7 381 TCGv t0;
dceaf394
EI		 382 int l1;
383
384 /* des ref:
385 The N flag is set according to the selected bit in the dest reg.
386 The Z flag is set if the selected bit and all bits to the right are
387 zero.
388 The X flag is cleared.
389 Other flags are left untouched.
390 The destination reg is not affected.
391
392 unsigned int fz, sbit, bset, mask, masked_t0;
393
394 sbit = T1 & 31;
395 bset = !!(T0 & (1 << sbit));
396 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
397 masked_t0 = T0 & mask;
398 fz = !(masked_t0 | bset);
399
400 // Clear the X, N and Z flags.
401 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
402 // Set the N and Z flags accordingly.
403 T0 |= (bset << 3) | (fz << 2);
404 */
405
406 l1 = gen_new_label();
407 sbit = tcg_temp_new(TCG_TYPE_TL);
408 bset = tcg_temp_new(TCG_TYPE_TL);
30abcfc7 409 t0 = tcg_temp_new(TCG_TYPE_TL);
dceaf394
EI		 410
411 /* Compute bset and sbit. */
30abcfc7
EI		 412 tcg_gen_andi_tl(sbit, b, 31);
413 tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
414 tcg_gen_and_tl(bset, a, t0);
dceaf394
EI		 415 tcg_gen_shr_tl(bset, bset, sbit);
416 /* Displace to N_FLAG. */
417 tcg_gen_shli_tl(bset, bset, 3);
418
419 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
420 tcg_gen_subi_tl(sbit, sbit, 1);
30abcfc7 421 tcg_gen_and_tl(sbit, a, sbit);
dceaf394
EI		 422
423 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
424 /* or in the N_FLAG. */
425 tcg_gen_or_tl(d, d, bset);
cb63669a 426 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
dceaf394
EI		 427 /* or in the Z_FLAG. */
428 tcg_gen_ori_tl(d, d, Z_FLAG);
429 gen_set_label(l1);
430
30abcfc7
EI		 431 tcg_temp_free(sbit);
432 tcg_temp_free(bset);
dceaf394
EI		 433}
434
30abcfc7 435static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
aae6b32a
EI		 436{
437 int l1;
438
439 l1 = gen_new_label();
440
441 /*
442 * d <<= 1
443 * if (d >= s)
444 * d -= s;
445 */
30abcfc7
EI		 446 tcg_gen_shli_tl(d, a, 1);
447 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
448 tcg_gen_sub_tl(d, d, b);
aae6b32a
EI		 449 gen_set_label(l1);
450}
451
3157a0a9
EI		 452/* Extended arithmetics on CRIS. */
453static inline void t_gen_add_flag(TCGv d, int flag)
454{
455 TCGv c;
456
457 c = tcg_temp_new(TCG_TYPE_TL);
458 t_gen_mov_TN_preg(c, PR_CCS);
459 /* Propagate carry into d. */
460 tcg_gen_andi_tl(c, c, 1 << flag);
461 if (flag)
462 tcg_gen_shri_tl(c, c, flag);
463 tcg_gen_add_tl(d, d, c);
30abcfc7 464 tcg_temp_free(c);
3157a0a9
EI		 465}
466
30abcfc7 467static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
3157a0a9 468{
30abcfc7
EI		 469 if (dc->flagx_known) {
470 if (dc->flags_x) {
471 TCGv c;
472
473 c = tcg_temp_new(TCG_TYPE_TL);
474 t_gen_mov_TN_preg(c, PR_CCS);
475 /* C flag is already at bit 0. */
476 tcg_gen_andi_tl(c, c, C_FLAG);
477 tcg_gen_add_tl(d, d, c);
478 tcg_temp_free(c);
479 }
480 } else {
481 TCGv x, c;
3157a0a9 482
30abcfc7
EI		 483 x = tcg_temp_new(TCG_TYPE_TL);
484 c = tcg_temp_new(TCG_TYPE_TL);
485 t_gen_mov_TN_preg(x, PR_CCS);
486 tcg_gen_mov_tl(c, x);
3157a0a9 487
30abcfc7
EI		 488 /* Propagate carry into d if X is set. Branch free. */
489 tcg_gen_andi_tl(c, c, C_FLAG);
490 tcg_gen_andi_tl(x, x, X_FLAG);
491 tcg_gen_shri_tl(x, x, 4);
3157a0a9 492
30abcfc7
EI		 493 tcg_gen_and_tl(x, x, c);
494 tcg_gen_add_tl(d, d, x);
495 tcg_temp_free(x);
496 tcg_temp_free(c);
497 }
3157a0a9
EI		 498}
499
a39f8f3a 500static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
3157a0a9 501{
30abcfc7
EI		 502 if (dc->flagx_known) {
503 if (dc->flags_x) {
504 TCGv c;
505
506 c = tcg_temp_new(TCG_TYPE_TL);
507 t_gen_mov_TN_preg(c, PR_CCS);
508 /* C flag is already at bit 0. */
509 tcg_gen_andi_tl(c, c, C_FLAG);
510 tcg_gen_sub_tl(d, d, c);
511 tcg_temp_free(c);
512 }
513 } else {
a39f8f3a
EI		 514 TCGv x, c;
515
516 x = tcg_temp_new(TCG_TYPE_TL);
517 c = tcg_temp_new(TCG_TYPE_TL);
518 t_gen_mov_TN_preg(x, PR_CCS);
519 tcg_gen_mov_tl(c, x);
520
521 /* Propagate carry into d if X is set. Branch free. */
522 tcg_gen_andi_tl(c, c, C_FLAG);
523 tcg_gen_andi_tl(x, x, X_FLAG);
524 tcg_gen_shri_tl(x, x, 4);
525
526 tcg_gen_and_tl(x, x, c);
527 tcg_gen_sub_tl(d, d, x);
30abcfc7
EI		 528 tcg_temp_free(x);
529 tcg_temp_free(c);
a39f8f3a 530 }
3157a0a9
EI		 531}
532
533/* Swap the two bytes within each half word of the s operand.
534 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
535static inline void t_gen_swapb(TCGv d, TCGv s)
536{
537 TCGv t, org_s;
538
539 t = tcg_temp_new(TCG_TYPE_TL);
540 org_s = tcg_temp_new(TCG_TYPE_TL);
541
542 /* d and s may refer to the same object. */
543 tcg_gen_mov_tl(org_s, s);
544 tcg_gen_shli_tl(t, org_s, 8);
545 tcg_gen_andi_tl(d, t, 0xff00ff00);
546 tcg_gen_shri_tl(t, org_s, 8);
547 tcg_gen_andi_tl(t, t, 0x00ff00ff);
548 tcg_gen_or_tl(d, d, t);
30abcfc7
EI		 549 tcg_temp_free(t);
550 tcg_temp_free(org_s);
3157a0a9
EI		 551}
552
553/* Swap the halfwords of the s operand. */
554static inline void t_gen_swapw(TCGv d, TCGv s)
555{
556 TCGv t;
557 /* d and s refer the same object. */
558 t = tcg_temp_new(TCG_TYPE_TL);
559 tcg_gen_mov_tl(t, s);
560 tcg_gen_shli_tl(d, t, 16);
561 tcg_gen_shri_tl(t, t, 16);
562 tcg_gen_or_tl(d, d, t);
30abcfc7 563 tcg_temp_free(t);
3157a0a9
EI		 564}
565
566/* Reverse the within each byte.
567 T0 = (((T0 << 7) & 0x80808080) |
568 ((T0 << 5) & 0x40404040) |
569 ((T0 << 3) & 0x20202020) |
570 ((T0 << 1) & 0x10101010) |
571 ((T0 >> 1) & 0x08080808) |
572 ((T0 >> 3) & 0x04040404) |
573 ((T0 >> 5) & 0x02020202) |
574 ((T0 >> 7) & 0x01010101));
575 */
576static inline void t_gen_swapr(TCGv d, TCGv s)
577{
578 struct {
579 int shift; /* LSL when positive, LSR when negative. */
580 uint32_t mask;
581 } bitrev [] = {
582 {7, 0x80808080},
583 {5, 0x40404040},
584 {3, 0x20202020},
585 {1, 0x10101010},
586 {-1, 0x08080808},
587 {-3, 0x04040404},
588 {-5, 0x02020202},
589 {-7, 0x01010101}
590 };
591 int i;
592 TCGv t, org_s;
593
594 /* d and s refer the same object. */
595 t = tcg_temp_new(TCG_TYPE_TL);
596 org_s = tcg_temp_new(TCG_TYPE_TL);
597 tcg_gen_mov_tl(org_s, s);
598
599 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
600 tcg_gen_andi_tl(d, t, bitrev[0].mask);
601 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
602 if (bitrev[i].shift >= 0) {
603 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
604 } else {
605 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
606 }
607 tcg_gen_andi_tl(t, t, bitrev[i].mask);
608 tcg_gen_or_tl(d, d, t);
609 }
30abcfc7
EI		 610 tcg_temp_free(t);
611 tcg_temp_free(org_s);
3157a0a9
EI		 612}
613
cf1d97f0 614static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
17ac9754
EI		 615{
616 TCGv btaken;
617 int l1;
618
619 l1 = gen_new_label();
620 btaken = tcg_temp_new(TCG_TYPE_TL);
621
622 /* Conditional jmp. */
2a44f7f1 623 tcg_gen_mov_tl(btaken, env_btaken);
cf1d97f0 624 tcg_gen_mov_tl(env_pc, pc_false);
cb63669a 625 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
cf1d97f0 626 tcg_gen_mov_tl(env_pc, pc_true);
17ac9754
EI		 627 gen_set_label(l1);
628
30abcfc7 629 tcg_temp_free(btaken);
17ac9754
EI		 630}
631
8170028d
TS		 632static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
633{
634 TranslationBlock *tb;
635 tb = dc->tb;
636 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
05ba7d5f 637 tcg_gen_goto_tb(n);
50cfa95c 638 tcg_gen_movi_tl(env_pc, dest);
05ba7d5f 639 tcg_gen_exit_tb((long)tb + n);
8170028d 640 } else {
2a44f7f1 641 tcg_gen_movi_tl(env_pc, dest);
05ba7d5f 642 tcg_gen_exit_tb(0);
8170028d 643 }
8170028d
TS		 644}
645
646/* Sign extend at translation time. */
647static int sign_extend(unsigned int val, unsigned int width)
648{
649 int sval;
650
651 /* LSL. */
652 val <<= 31 - width;
653 sval = val;
654 /* ASR. */
655 sval >>= 31 - width;
656 return sval;
657}
658
05ba7d5f
EI		 659static inline void cris_clear_x_flag(DisasContext *dc)
660{
2a44f7f1
EI		 661 if (dc->flagx_known && dc->flags_x)
662 dc->flags_uptodate = 0;
663
30abcfc7 664 dc->flagx_known = 1;
b41f7df0 665 dc->flags_x = 0;
05ba7d5f
EI		 666}
667
30abcfc7 668static void cris_flush_cc_state(DisasContext *dc)
8170028d 669{
30abcfc7 670 if (dc->cc_size_uptodate != dc->cc_size) {
b41f7df0 671 tcg_gen_movi_tl(cc_size, dc->cc_size);
30abcfc7
EI		 672 dc->cc_size_uptodate = dc->cc_size;
673 }
674 tcg_gen_movi_tl(cc_op, dc->cc_op);
675 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
676}
677
678static void cris_evaluate_flags(DisasContext *dc)
679{
680 if (!dc->flags_uptodate) {
681 cris_flush_cc_state(dc);
b41f7df0 682
8170028d
TS		 683 switch (dc->cc_op)
684 {
685 case CC_OP_MCP:
b41f7df0 686 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
8170028d
TS		 687 break;
688 case CC_OP_MULS:
b41f7df0 689 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
8170028d
TS		 690 break;
691 case CC_OP_MULU:
b41f7df0 692 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
8170028d
TS		 693 break;
694 case CC_OP_MOVE:
30abcfc7
EI		 695 case CC_OP_AND:
696 case CC_OP_OR:
697 case CC_OP_XOR:
698 case CC_OP_ASR:
699 case CC_OP_LSR:
700 case CC_OP_LSL:
8170028d
TS		 701 switch (dc->cc_size)
702 {
703 case 4:
b41f7df0 704 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
8170028d
TS		 705 break;
706 case 2:
b41f7df0 707 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
8170028d
TS		 708 break;
709 default:
b41f7df0 710 tcg_gen_helper_0_0(helper_evaluate_flags);
8170028d
TS		 711 break;
712 }
713 break;
b41f7df0
EI		 714 case CC_OP_FLAGS:
715 /* live. */
716 break;
8170028d
TS		 717 default:
718 {
719 switch (dc->cc_size)
720 {
721 case 4:
b41f7df0 722 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
8170028d
TS		 723 break;
724 default:
b41f7df0 725 tcg_gen_helper_0_0(helper_evaluate_flags);
8170028d
TS		 726 break;
727 }
728 }
729 break;
730 }
2a44f7f1
EI		 731 if (dc->flagx_known) {
732 if (dc->flags_x)
733 tcg_gen_ori_tl(cpu_PR[PR_CCS],
734 cpu_PR[PR_CCS], X_FLAG);
735 else
736 tcg_gen_andi_tl(cpu_PR[PR_CCS],
737 cpu_PR[PR_CCS], ~X_FLAG);
a7cfbba0 738 }
2a44f7f1 739
30abcfc7 740 dc->flags_uptodate = 1;
8170028d
TS		 741 }
742}
743
744static void cris_cc_mask(DisasContext *dc, unsigned int mask)
745{
746 uint32_t ovl;
747
2a44f7f1
EI		 748 if (!mask) {
749 dc->update_cc = 0;
750 return;
751 }
752
fd56059f
AZ		 753 /* Check if we need to evaluate the condition codes due to
754 CC overlaying. */
8170028d
TS		 755 ovl = (dc->cc_mask ^ mask) & ~mask;
756 if (ovl) {
757 /* TODO: optimize this case. It trigs all the time. */
758 cris_evaluate_flags (dc);
759 }
760 dc->cc_mask = mask;
8170028d 761 dc->update_cc = 1;
8170028d
TS		 762}
763
b41f7df0 764static void cris_update_cc_op(DisasContext *dc, int op, int size)
8170028d
TS		 765{
766 dc->cc_op = op;
8170028d 767 dc->cc_size = size;
30abcfc7 768 dc->flags_uptodate = 0;
8170028d
TS		 769}
770
30abcfc7
EI		 771static inline void cris_update_cc_x(DisasContext *dc)
772{
773 /* Save the x flag state at the time of the cc snapshot. */
774 if (dc->flagx_known) {
775 if (dc->cc_x_uptodate == (2 | dc->flags_x))
776 return;
777 tcg_gen_movi_tl(cc_x, dc->flags_x);
778 dc->cc_x_uptodate = 2 | dc->flags_x;
779 }
780 else {
781 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
782 dc->cc_x_uptodate = 1;
783 }
784}
785
786/* Update cc prior to executing ALU op. Needs source operands untouched. */
787static void cris_pre_alu_update_cc(DisasContext *dc, int op,
788 TCGv dst, TCGv src, int size)
8170028d 789{
8170028d 790 if (dc->update_cc) {
b41f7df0 791 cris_update_cc_op(dc, op, size);
30abcfc7
EI		 792 tcg_gen_mov_tl(cc_src, src);
793
794 if (op != CC_OP_MOVE
795 && op != CC_OP_AND
796 && op != CC_OP_OR
797 && op != CC_OP_XOR
798 && op != CC_OP_ASR
799 && op != CC_OP_LSR
800 && op != CC_OP_LSL)
801 tcg_gen_mov_tl(cc_dest, dst);
802
803 cris_update_cc_x(dc);
804 }
805}
3157a0a9 806
30abcfc7
EI		 807/* Update cc after executing ALU op. needs the result. */
808static inline void cris_update_result(DisasContext *dc, TCGv res)
809{
810 if (dc->update_cc) {
811 if (dc->cc_size == 4 &&
812 (dc->cc_op == CC_OP_SUB
813 || dc->cc_op == CC_OP_ADD))
814 return;
815 tcg_gen_mov_tl(cc_result, res);
8170028d 816 }
30abcfc7 817}
8170028d 818
30abcfc7
EI		 819/* Returns one if the write back stage should execute. */
820static void cris_alu_op_exec(DisasContext *dc, int op,
821 TCGv dst, TCGv a, TCGv b, int size)
822{
8170028d
TS		 823 /* Emit the ALU insns. */
824 switch (op)
825 {
826 case CC_OP_ADD:
30abcfc7 827 tcg_gen_add_tl(dst, a, b);
8170028d 828 /* Extended arithmetics. */
30abcfc7 829 t_gen_addx_carry(dc, dst);
8170028d
TS		 830 break;
831 case CC_OP_ADDC:
30abcfc7
EI		 832 tcg_gen_add_tl(dst, a, b);
833 t_gen_add_flag(dst, 0); /* C_FLAG. */
8170028d
TS		 834 break;
835 case CC_OP_MCP:
30abcfc7
EI		 836 tcg_gen_add_tl(dst, a, b);
837 t_gen_add_flag(dst, 8); /* R_FLAG. */
8170028d
TS		 838 break;
839 case CC_OP_SUB:
30abcfc7 840 tcg_gen_sub_tl(dst, a, b);
8170028d 841 /* Extended arithmetics. */
30abcfc7 842 t_gen_subx_carry(dc, dst);
8170028d
TS		 843 break;
844 case CC_OP_MOVE:
30abcfc7 845 tcg_gen_mov_tl(dst, b);
8170028d
TS		 846 break;
847 case CC_OP_OR:
30abcfc7 848 tcg_gen_or_tl(dst, a, b);
8170028d
TS		 849 break;
850 case CC_OP_AND:
30abcfc7 851 tcg_gen_and_tl(dst, a, b);
8170028d
TS		 852 break;
853 case CC_OP_XOR:
30abcfc7 854 tcg_gen_xor_tl(dst, a, b);
8170028d
TS		 855 break;
856 case CC_OP_LSL:
30abcfc7 857 t_gen_lsl(dst, a, b);
8170028d
TS		 858 break;
859 case CC_OP_LSR:
30abcfc7 860 t_gen_lsr(dst, a, b);
8170028d
TS		 861 break;
862 case CC_OP_ASR:
30abcfc7 863 t_gen_asr(dst, a, b);
8170028d
TS		 864 break;
865 case CC_OP_NEG:
30abcfc7 866 tcg_gen_neg_tl(dst, b);
8170028d 867 /* Extended arithmetics. */
30abcfc7 868 t_gen_subx_carry(dc, dst);
8170028d
TS		 869 break;
870 case CC_OP_LZ:
30abcfc7 871 t_gen_lz_i32(dst, b);
8170028d
TS		 872 break;
873 case CC_OP_BTST:
30abcfc7 874 t_gen_btst(dst, a, b);
8170028d
TS		 875 break;
876 case CC_OP_MULS:
30abcfc7
EI		 877 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
878 break;
8170028d 879 case CC_OP_MULU:
30abcfc7
EI		 880 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
881 break;
8170028d 882 case CC_OP_DSTEP:
30abcfc7 883 t_gen_cris_dstep(dst, a, b);
8170028d
TS		 884 break;
885 case CC_OP_BOUND:
3157a0a9
EI		 886 {
887 int l1;
888 l1 = gen_new_label();
30abcfc7
EI		 889 tcg_gen_mov_tl(dst, a);
890 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
891 tcg_gen_mov_tl(dst, b);
3157a0a9
EI		 892 gen_set_label(l1);
893 }
894 break;
8170028d 895 case CC_OP_CMP:
30abcfc7 896 tcg_gen_sub_tl(dst, a, b);
8170028d 897 /* Extended arithmetics. */
30abcfc7 898 t_gen_subx_carry(dc, dst);
8170028d
TS		 899 break;
900 default:
901 fprintf (logfile, "illegal ALU op.\n");
902 BUG();
903 break;
904 }
905
8170028d 906 if (size == 1)
30abcfc7 907 tcg_gen_andi_tl(dst, dst, 0xff);
8170028d 908 else if (size == 2)
30abcfc7
EI		 909 tcg_gen_andi_tl(dst, dst, 0xffff);
910}
911
912static void cris_alu(DisasContext *dc, int op,
913 TCGv d, TCGv op_a, TCGv op_b, int size)
914{
915 TCGv tmp;
916 int writeback;
917
918 writeback = 1;
919 tmp = cpu_T[0];
920 if (op == CC_OP_CMP)
921 writeback = 0;
922 else if (size == 4) {
923 tmp = d;
924 writeback = 0;
925 }
926
927 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
928 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
929 cris_update_result(dc, tmp);
05ba7d5f 930
8170028d
TS		 931 /* Writeback. */
932 if (writeback) {
30abcfc7
EI		 933 if (size == 1)
934 tcg_gen_andi_tl(d, d, ~0xff);
935 else
936 tcg_gen_andi_tl(d, d, ~0xffff);
937 tcg_gen_or_tl(d, d, tmp);
8170028d 938 }
8170028d
TS		 939}
940
941static int arith_cc(DisasContext *dc)
942{
943 if (dc->update_cc) {
944 switch (dc->cc_op) {
30abcfc7 945 case CC_OP_ADDC: return 1;
8170028d
TS		 946 case CC_OP_ADD: return 1;
947 case CC_OP_SUB: return 1;
30abcfc7 948 case CC_OP_DSTEP: return 1;
8170028d
TS		 949 case CC_OP_LSL: return 1;
950 case CC_OP_LSR: return 1;
951 case CC_OP_ASR: return 1;
952 case CC_OP_CMP: return 1;
30abcfc7
EI		 953 case CC_OP_NEG: return 1;
954 case CC_OP_OR: return 1;
955 case CC_OP_XOR: return 1;
956 case CC_OP_MULU: return 1;
957 case CC_OP_MULS: return 1;
8170028d
TS		 958 default:
959 return 0;
960 }
961 }
962 return 0;
963}
964
965static void gen_tst_cc (DisasContext *dc, int cond)
966{
2a44f7f1 967 int arith_opt, move_opt;
8170028d
TS		 968
969 /* TODO: optimize more condition codes. */
dceaf394
EI		 970
971 /*
972 * If the flags are live, we've gotta look into the bits of CCS.
973 * Otherwise, if we just did an arithmetic operation we try to
974 * evaluate the condition code faster.
975 *
976 * When this function is done, T0 should be non-zero if the condition
977 * code is true.
978 */
30abcfc7 979 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
2a44f7f1 980 move_opt = (dc->cc_op == CC_OP_MOVE) && !dc->flags_uptodate;
8170028d
TS		 981 switch (cond) {
982 case CC_EQ:
2a44f7f1 983 if (arith_opt || move_opt) {
dceaf394
EI		 984 /* If cc_result is zero, T0 should be
985 non-zero otherwise T0 should be zero. */
986 int l1;
987 l1 = gen_new_label();
988 tcg_gen_movi_tl(cpu_T[0], 0);
cb63669a
PB		 989 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
990 0, l1);
dceaf394
EI		 991 tcg_gen_movi_tl(cpu_T[0], 1);
992 gen_set_label(l1);
993 }
8170028d
TS		 994 else {
995 cris_evaluate_flags(dc);
dceaf394
EI		 996 tcg_gen_andi_tl(cpu_T[0],
997 cpu_PR[PR_CCS], Z_FLAG);
8170028d
TS		 998 }
999 break;
1000 case CC_NE:
2a44f7f1 1001 if (arith_opt || move_opt)
dceaf394 1002 tcg_gen_mov_tl(cpu_T[0], cc_result);
8170028d
TS		 1003 else {
1004 cris_evaluate_flags(dc);
dceaf394
EI		 1005 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1006 Z_FLAG);
1007 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
8170028d
TS		 1008 }
1009 break;
1010 case CC_CS:
1011 cris_evaluate_flags(dc);
dceaf394 1012 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
8170028d
TS		 1013 break;
1014 case CC_CC:
1015 cris_evaluate_flags(dc);
2a44f7f1 1016 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
dceaf394 1017 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
8170028d
TS		 1018 break;
1019 case CC_VS:
1020 cris_evaluate_flags(dc);
dceaf394 1021 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
8170028d
TS		 1022 break;
1023 case CC_VC:
1024 cris_evaluate_flags(dc);
dceaf394
EI		 1025 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1026 V_FLAG);
1027 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
8170028d
TS		 1028 break;
1029 case CC_PL:
2a44f7f1
EI		 1030 if (arith_opt || move_opt) {
1031 int bits = 31;
1032
1033 if (dc->cc_size == 1)
1034 bits = 7;
1035 else if (dc->cc_size == 2)
1036 bits = 15;
1037
1038 tcg_gen_shri_tl(cpu_T[0], cc_result, bits);
1039 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
1040 } else {
8170028d 1041 cris_evaluate_flags(dc);
dceaf394
EI		 1042 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
1043 N_FLAG);
1044 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 1045 }
1046 break;
1047 case CC_MI:
2a44f7f1
EI		 1048 if (arith_opt || move_opt) {
1049 int bits = 31;
1050
1051 if (dc->cc_size == 1)
1052 bits = 7;
1053 else if (dc->cc_size == 2)
1054 bits = 15;
1055
1056 tcg_gen_shri_tl(cpu_T[0], cc_result, 31);
dceaf394 1057 }
8170028d
TS		 1058 else {
1059 cris_evaluate_flags(dc);
dceaf394
EI		 1060 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1061 N_FLAG);
8170028d
TS		 1062 }
1063 break;
1064 case CC_LS:
1065 cris_evaluate_flags(dc);
dceaf394
EI		 1066 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
1067 C_FLAG | Z_FLAG);
8170028d
TS		 1068 break;
1069 case CC_HI:
1070 cris_evaluate_flags(dc);
dceaf394
EI		 1071 {
1072 TCGv tmp;
1073
1074 tmp = tcg_temp_new(TCG_TYPE_TL);
1075 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1076 C_FLAG | Z_FLAG);
1077 /* Overlay the C flag on top of the Z. */
1078 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
1079 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
1080 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1081
30abcfc7 1082 tcg_temp_free(tmp);
dceaf394 1083 }
8170028d
TS		 1084 break;
1085 case CC_GE:
1086 cris_evaluate_flags(dc);
dceaf394
EI		 1087 /* Overlay the V flag on top of the N. */
1088 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1089 tcg_gen_xor_tl(cpu_T[0],
1090 cpu_PR[PR_CCS], cpu_T[0]);
1091 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1092 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 1093 break;
1094 case CC_LT:
1095 cris_evaluate_flags(dc);
dceaf394
EI		 1096 /* Overlay the V flag on top of the N. */
1097 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1098 tcg_gen_xor_tl(cpu_T[0],
1099 cpu_PR[PR_CCS], cpu_T[0]);
1100 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 1101 break;
1102 case CC_GT:
1103 cris_evaluate_flags(dc);
dceaf394
EI		 1104 {
1105 TCGv n, z;
1106
1107 n = tcg_temp_new(TCG_TYPE_TL);
1108 z = tcg_temp_new(TCG_TYPE_TL);
1109
1110 /* To avoid a shift we overlay everything on
1111 the V flag. */
1112 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1113 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1114 /* invert Z. */
1115 tcg_gen_xori_tl(z, z, 2);
1116
1117 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1118 tcg_gen_xori_tl(n, n, 2);
1119 tcg_gen_and_tl(cpu_T[0], z, n);
1120 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1121
30abcfc7
EI		 1122 tcg_temp_free(n);
1123 tcg_temp_free(z);
dceaf394 1124 }
8170028d
TS		 1125 break;
1126 case CC_LE:
1127 cris_evaluate_flags(dc);
dceaf394
EI		 1128 {
1129 TCGv n, z;
1130
1131 n = tcg_temp_new(TCG_TYPE_TL);
1132 z = tcg_temp_new(TCG_TYPE_TL);
1133
1134 /* To avoid a shift we overlay everything on
1135 the V flag. */
1136 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1137 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1138
1139 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1140 tcg_gen_or_tl(cpu_T[0], z, n);
1141 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1142
30abcfc7
EI		 1143 tcg_temp_free(n);
1144 tcg_temp_free(z);
dceaf394 1145 }
8170028d
TS		 1146 break;
1147 case CC_P:
1148 cris_evaluate_flags(dc);
dceaf394 1149 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
8170028d
TS		 1150 break;
1151 case CC_A:
17ac9754 1152 tcg_gen_movi_tl(cpu_T[0], 1);
8170028d
TS		 1153 break;
1154 default:
1155 BUG();
1156 break;
1157 };
1158}
1159
2a44f7f1
EI		 1160static void cris_store_direct_jmp(DisasContext *dc)
1161{
1162 /* Store the direct jmp state into the cpu-state. */
1163 if (dc->jmp == JMP_DIRECT) {
1164 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1165 tcg_gen_movi_tl(env_btaken, 1);
1166 }
1167}
1168
1169static void cris_prepare_cc_branch (DisasContext *dc,
1170 int offset, int cond)
8170028d
TS		 1171{
1172 /* This helps us re-schedule the micro-code to insns in delay-slots
1173 before the actual jump. */
1174 dc->delayed_branch = 2;
2a44f7f1
EI		 1175 dc->jmp_pc = dc->pc + offset;
1176
8170028d
TS		 1177 if (cond != CC_A)
1178 {
2a44f7f1 1179 dc->jmp = JMP_INDIRECT;
8170028d 1180 gen_tst_cc (dc, cond);
2a44f7f1
EI		 1181 tcg_gen_mov_tl(env_btaken, cpu_T[0]);
1182 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1183 } else {
1184 /* Allow chaining. */
1185 dc->jmp = JMP_DIRECT;
1186 }
8170028d
TS		 1187}
1188
b41f7df0 1189
2a44f7f1
EI		 1190/* jumps, when the dest is in a live reg for example. Direct should be set
1191 when the dest addr is constant to allow tb chaining. */
1192static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
8170028d
TS		 1193{
1194 /* This helps us re-schedule the micro-code to insns in delay-slots
1195 before the actual jump. */
1196 dc->delayed_branch = 2;
2a44f7f1
EI		 1197 dc->jmp = type;
1198 if (type == JMP_INDIRECT)
1199 tcg_gen_movi_tl(env_btaken, 1);
8170028d
TS		 1200}
1201
b41f7df0
EI		 1202void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1203 unsigned int size, int sign)
8170028d 1204{
b41f7df0
EI		 1205 int mem_index = cpu_mmu_index(dc->env);
1206
2a44f7f1
EI		 1207 /* If we get a fault on a delayslot we must keep the jmp state in
1208 the cpu-state to be able to re-execute the jmp. */
1209 if (dc->delayed_branch == 1)
1210 cris_store_direct_jmp(dc);
1211
8170028d
TS		 1212 if (size == 1) {
1213 if (sign)
b41f7df0 1214 tcg_gen_qemu_ld8s(dst, addr, mem_index);
8170028d 1215 else
b41f7df0 1216 tcg_gen_qemu_ld8u(dst, addr, mem_index);
8170028d
TS		 1217 }
1218 else if (size == 2) {
1219 if (sign)
b41f7df0 1220 tcg_gen_qemu_ld16s(dst, addr, mem_index);
8170028d 1221 else
b41f7df0 1222 tcg_gen_qemu_ld16u(dst, addr, mem_index);
8170028d
TS		 1223 }
1224 else {
30abcfc7 1225 tcg_gen_qemu_ld32u(dst, addr, mem_index);
8170028d
TS		 1226 }
1227}
1228
17ac9754
EI		 1229void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1230 unsigned int size)
8170028d 1231{
b41f7df0
EI		 1232 int mem_index = cpu_mmu_index(dc->env);
1233
2a44f7f1
EI		 1234 /* If we get a fault on a delayslot we must keep the jmp state in
1235 the cpu-state to be able to re-execute the jmp. */
1236 if (dc->delayed_branch == 1)
1237 cris_store_direct_jmp(dc);
1238
1239
1240 /* Conditional writes. We only support the kind were X and P are known
1241 at translation time. */
1242 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1243 dc->postinc = 0;
1244 cris_evaluate_flags(dc);
1245 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1246 return;
1247 }
1248
8170028d 1249 /* Remember, operands are flipped. CRIS has reversed order. */
b41f7df0 1250 if (size == 1)
17ac9754 1251 tcg_gen_qemu_st8(val, addr, mem_index);
b41f7df0 1252 else if (size == 2)
17ac9754 1253 tcg_gen_qemu_st16(val, addr, mem_index);
8170028d 1254 else
17ac9754 1255 tcg_gen_qemu_st32(val, addr, mem_index);
2a44f7f1
EI		 1256
1257 if (dc->flagx_known && dc->flags_x) {
1258 cris_evaluate_flags(dc);
1259 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1260 }
8170028d
TS		 1261}
1262
05ba7d5f 1263static inline void t_gen_sext(TCGv d, TCGv s, int size)
8170028d
TS		 1264{
1265 if (size == 1)
05ba7d5f 1266 tcg_gen_ext8s_i32(d, s);
8170028d 1267 else if (size == 2)
05ba7d5f 1268 tcg_gen_ext16s_i32(d, s);
30abcfc7 1269 else if(d != s)
50cfa95c 1270 tcg_gen_mov_tl(d, s);
8170028d
TS		 1271}
1272
05ba7d5f 1273static inline void t_gen_zext(TCGv d, TCGv s, int size)
8170028d
TS		 1274{
1275 if (size == 1)
86831435 1276 tcg_gen_ext8u_i32(d, s);
8170028d 1277 else if (size == 2)
86831435 1278 tcg_gen_ext16u_i32(d, s);
30abcfc7 1279 else if (d != s)
50cfa95c 1280 tcg_gen_mov_tl(d, s);
8170028d
TS		 1281}
1282
1283#if DISAS_CRIS
1284static char memsize_char(int size)
1285{
1286 switch (size)
1287 {
1288 case 1: return 'b'; break;
1289 case 2: return 'w'; break;
1290 case 4: return 'd'; break;
1291 default:
1292 return 'x';
1293 break;
1294 }
1295}
1296#endif
1297
30abcfc7 1298static inline unsigned int memsize_z(DisasContext *dc)
8170028d
TS		 1299{
1300 return dc->zsize + 1;
1301}
1302
30abcfc7 1303static inline unsigned int memsize_zz(DisasContext *dc)
8170028d
TS		 1304{
1305 switch (dc->zzsize)
1306 {
1307 case 0: return 1;
1308 case 1: return 2;
1309 default:
1310 return 4;
1311 }
1312}
1313
c7d05695 1314static inline void do_postinc (DisasContext *dc, int size)
8170028d 1315{
c7d05695
EI		 1316 if (dc->postinc)
1317 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
8170028d
TS		 1318}
1319
30abcfc7
EI		 1320static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1321 int size, int s_ext, TCGv dst)
8170028d 1322{
8170028d 1323 if (s_ext)
30abcfc7 1324 t_gen_sext(dst, cpu_R[rs], size);
8170028d 1325 else
30abcfc7 1326 t_gen_zext(dst, cpu_R[rs], size);
8170028d
TS		 1327}
1328
1329/* Prepare T0 and T1 for a register alu operation.
1330 s_ext decides if the operand1 should be sign-extended or zero-extended when
1331 needed. */
1332static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1333 int size, int s_ext)
1334{
30abcfc7 1335 dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);
8170028d 1336
8170028d 1337 if (s_ext)
50cfa95c 1338 t_gen_sext(cpu_T[0], cpu_R[rd], size);
8170028d 1339 else
50cfa95c 1340 t_gen_zext(cpu_T[0], cpu_R[rd], size);
8170028d
TS		 1341}
1342
30abcfc7
EI		 1343static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1344 TCGv dst)
8170028d
TS		 1345{
1346 unsigned int rs, rd;
1347 uint32_t imm;
1348 int is_imm;
1349 int insn_len = 2;
1350
1351 rs = dc->op1;
1352 rd = dc->op2;
1353 is_imm = rs == 15 && dc->postinc;
1354
1355 /* Load [$rs] onto T1. */
1356 if (is_imm) {
1357 insn_len = 2 + memsize;
1358 if (memsize == 1)
1359 insn_len++;
1360
8170028d
TS		 1361 if (memsize != 4) {
1362 if (s_ext) {
17ac9754
EI		 1363 if (memsize == 1)
1364 imm = ldsb_code(dc->pc + 2);
1365 else
1366 imm = ldsw_code(dc->pc + 2);
8170028d
TS		 1367 } else {
1368 if (memsize == 1)
17ac9754 1369 imm = ldub_code(dc->pc + 2);
8170028d 1370 else
17ac9754 1371 imm = lduw_code(dc->pc + 2);
8170028d 1372 }
17ac9754
EI		 1373 } else
1374 imm = ldl_code(dc->pc + 2);
1375
8170028d 1376 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
cf1d97f0 1377 imm, rd, s_ext, memsize));
30abcfc7 1378 tcg_gen_movi_tl(dst, imm);
8170028d
TS		 1379 dc->postinc = 0;
1380 } else {
30abcfc7
EI		 1381 cris_flush_cc_state(dc);
1382 gen_load(dc, dst, cpu_R[rs], memsize, 0);
8170028d 1383 if (s_ext)
30abcfc7 1384 t_gen_sext(dst, dst, memsize);
8170028d 1385 else
30abcfc7 1386 t_gen_zext(dst, dst, memsize);
8170028d 1387 }
cf1d97f0
EI		 1388 return insn_len;
1389}
1390
1391/* Prepare T0 and T1 for a memory + alu operation.
1392 s_ext decides if the operand1 should be sign-extended or zero-extended when
1393 needed. */
1394static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1395{
1396 int insn_len;
1397
30abcfc7 1398 insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
8170028d
TS		 1399
1400 /* put dest in T0. */
cf1d97f0 1401 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
8170028d
TS		 1402 return insn_len;
1403}
1404
1405#if DISAS_CRIS
1406static const char *cc_name(int cc)
1407{
1408 static char *cc_names[16] = {
1409 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1410 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1411 };
1412 assert(cc < 16);
1413 return cc_names[cc];
1414}
1415#endif
1416
b41f7df0
EI		 1417/* Start of insn decoders. */
1418
8170028d
TS		 1419static unsigned int dec_bccq(DisasContext *dc)
1420{
1421 int32_t offset;
1422 int sign;
1423 uint32_t cond = dc->op2;
1424 int tmp;
1425
1426 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1427 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1428
1429 offset *= 2;
1430 offset |= sign << 8;
1431 tmp = offset;
1432 offset = sign_extend(offset, 8);
1433
2a44f7f1
EI		 1434 DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
1435
8170028d
TS		 1436 /* op2 holds the condition-code. */
1437 cris_cc_mask(dc, 0);
1438 cris_prepare_cc_branch (dc, offset, cond);
1439 return 2;
1440}
1441static unsigned int dec_addoq(DisasContext *dc)
1442{
b41f7df0 1443 int32_t imm;
8170028d
TS		 1444
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1446 imm = sign_extend(dc->op1, 7);
1447
1448 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1449 cris_cc_mask(dc, 0);
1450 /* Fetch register operand, */
b41f7df0 1451 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
8170028d
TS		 1452 return 2;
1453}
1454static unsigned int dec_addq(DisasContext *dc)
1455{
1456 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1457
1458 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1459
1460 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 1461
1462 cris_alu(dc, CC_OP_ADD,
1463 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
8170028d
TS		 1464 return 2;
1465}
1466static unsigned int dec_moveq(DisasContext *dc)
1467{
1468 uint32_t imm;
1469
1470 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1471 imm = sign_extend(dc->op1, 5);
1472 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1473
a39f8f3a 1474 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
8170028d
TS		 1475 return 2;
1476}
1477static unsigned int dec_subq(DisasContext *dc)
1478{
1479 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1480
1481 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1482
1483 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 1484 cris_alu(dc, CC_OP_SUB,
1485 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
8170028d
TS		 1486 return 2;
1487}
1488static unsigned int dec_cmpq(DisasContext *dc)
1489{
1490 uint32_t imm;
1491 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1492 imm = sign_extend(dc->op1, 5);
1493
1494 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1495 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 1496
1497 cris_alu(dc, CC_OP_CMP,
1498 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
8170028d
TS		 1499 return 2;
1500}
1501static unsigned int dec_andq(DisasContext *dc)
1502{
1503 uint32_t imm;
1504 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1505 imm = sign_extend(dc->op1, 5);
1506
1507 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1508 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 1509
1510 cris_alu(dc, CC_OP_AND,
1511 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
8170028d
TS		 1512 return 2;
1513}
1514static unsigned int dec_orq(DisasContext *dc)
1515{
1516 uint32_t imm;
1517 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1518 imm = sign_extend(dc->op1, 5);
1519 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1520 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 1521
1522 cris_alu(dc, CC_OP_OR,
1523 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
8170028d
TS		 1524 return 2;
1525}
1526static unsigned int dec_btstq(DisasContext *dc)
1527{
1528 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1529 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
17ac9754 1530
8170028d 1531 cris_cc_mask(dc, CC_MASK_NZ);
8170028d 1532
30abcfc7
EI		 1533 cris_alu(dc, CC_OP_BTST,
1534 cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
b41f7df0 1535 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
cf1d97f0 1536 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
30abcfc7 1537 dc->flags_uptodate = 1;
8170028d
TS		 1538 return 2;
1539}
1540static unsigned int dec_asrq(DisasContext *dc)
1541{
1542 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1543 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1544 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1545
2a44f7f1
EI		 1546 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1547 cris_alu(dc, CC_OP_MOVE,
30abcfc7 1548 cpu_R[dc->op2],
2a44f7f1 1549 cpu_R[dc->op2], cpu_R[dc->op2], 4);
8170028d
TS		 1550 return 2;
1551}
1552static unsigned int dec_lslq(DisasContext *dc)
1553{
1554 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1555 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1556
1557 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1558
2a44f7f1
EI		 1559 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1560
1561 cris_alu(dc, CC_OP_MOVE,
30abcfc7 1562 cpu_R[dc->op2],
2a44f7f1 1563 cpu_R[dc->op2], cpu_R[dc->op2], 4);
8170028d
TS		 1564 return 2;
1565}
1566static unsigned int dec_lsrq(DisasContext *dc)
1567{
1568 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1569 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1570
1571 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1572
2a44f7f1
EI		 1573 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1574 cris_alu(dc, CC_OP_MOVE,
30abcfc7 1575 cpu_R[dc->op2],
2a44f7f1 1576 cpu_R[dc->op2], cpu_R[dc->op2], 4);
8170028d
TS		 1577 return 2;
1578}
1579
1580static unsigned int dec_move_r(DisasContext *dc)
1581{
1582 int size = memsize_zz(dc);
1583
1584 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1585 memsize_char(size), dc->op1, dc->op2));
1586
1587 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 1588 if (size == 4) {
1589 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1590 cris_cc_mask(dc, CC_MASK_NZ);
1591 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1592 cris_update_cc_x(dc);
1593 cris_update_result(dc, cpu_R[dc->op2]);
1594 }
1595 else {
1596 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1597 cris_alu(dc, CC_OP_MOVE,
1598 cpu_R[dc->op2],
1599 cpu_R[dc->op2], cpu_T[1], size);
1600 }
8170028d
TS		 1601 return 2;
1602}
1603
1604static unsigned int dec_scc_r(DisasContext *dc)
1605{
1606 int cond = dc->op2;
1607
1608 DIS(fprintf (logfile, "s%s $r%u\n",
1609 cc_name(cond), dc->op1));
1610
1611 if (cond != CC_A)
1612 {
dceaf394
EI		 1613 int l1;
1614
8170028d 1615 gen_tst_cc (dc, cond);
dceaf394
EI		 1616
1617 l1 = gen_new_label();
1618 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
cb63669a 1619 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
dceaf394
EI		 1620 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1621 gen_set_label(l1);
8170028d
TS		 1622 }
1623 else
dceaf394 1624 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
8170028d
TS		 1625
1626 cris_cc_mask(dc, 0);
8170028d
TS		 1627 return 2;
1628}
1629
1630static unsigned int dec_and_r(DisasContext *dc)
1631{
1632 int size = memsize_zz(dc);
1633
1634 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1635 memsize_char(size), dc->op1, dc->op2));
1636 cris_cc_mask(dc, CC_MASK_NZ);
1637 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1638
1639 cris_alu(dc, CC_OP_AND,
1640 cpu_R[dc->op2],
1641 cpu_R[dc->op2], cpu_T[1], size);
8170028d
TS		 1642 return 2;
1643}
1644
1645static unsigned int dec_lz_r(DisasContext *dc)
1646{
1647 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1648 dc->op1, dc->op2));
1649 cris_cc_mask(dc, CC_MASK_NZ);
1650 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
30abcfc7
EI		 1651 cris_alu(dc, CC_OP_LZ,
1652 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 1653 return 2;
1654}
1655
1656static unsigned int dec_lsl_r(DisasContext *dc)
1657{
1658 int size = memsize_zz(dc);
1659
1660 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1661 memsize_char(size), dc->op1, dc->op2));
1662 cris_cc_mask(dc, CC_MASK_NZ);
1663 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1664 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
30abcfc7
EI		 1665
1666 cris_alu(dc, CC_OP_LSL,
1667 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1668 return 2;
1669}
1670
1671static unsigned int dec_lsr_r(DisasContext *dc)
1672{
1673 int size = memsize_zz(dc);
1674
1675 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1676 memsize_char(size), dc->op1, dc->op2));
1677 cris_cc_mask(dc, CC_MASK_NZ);
1678 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1679 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
30abcfc7
EI		 1680
1681 cris_alu(dc, CC_OP_LSR,
1682 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1683 return 2;
1684}
1685
1686static unsigned int dec_asr_r(DisasContext *dc)
1687{
1688 int size = memsize_zz(dc);
1689
1690 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1691 memsize_char(size), dc->op1, dc->op2));
1692 cris_cc_mask(dc, CC_MASK_NZ);
1693 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
05ba7d5f 1694 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
30abcfc7
EI		 1695
1696 cris_alu(dc, CC_OP_ASR,
1697 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1698 return 2;
1699}
1700
1701static unsigned int dec_muls_r(DisasContext *dc)
1702{
1703 int size = memsize_zz(dc);
1704
1705 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1706 memsize_char(size), dc->op1, dc->op2));
1707 cris_cc_mask(dc, CC_MASK_NZV);
1708 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
30abcfc7
EI		 1709
1710 cris_alu(dc, CC_OP_MULS,
1711 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 1712 return 2;
1713}
1714
1715static unsigned int dec_mulu_r(DisasContext *dc)
1716{
1717 int size = memsize_zz(dc);
1718
1719 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1720 memsize_char(size), dc->op1, dc->op2));
1721 cris_cc_mask(dc, CC_MASK_NZV);
1722 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1723
1724 cris_alu(dc, CC_OP_MULU,
1725 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 1726 return 2;
1727}
1728
1729
1730static unsigned int dec_dstep_r(DisasContext *dc)
1731{
1732 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1733 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 1734 cris_alu(dc, CC_OP_DSTEP,
1735 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
8170028d
TS		 1736 return 2;
1737}
1738
1739static unsigned int dec_xor_r(DisasContext *dc)
1740{
1741 int size = memsize_zz(dc);
1742 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1743 memsize_char(size), dc->op1, dc->op2));
1744 BUG_ON(size != 4); /* xor is dword. */
1745 cris_cc_mask(dc, CC_MASK_NZ);
1746 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1747
1748 cris_alu(dc, CC_OP_XOR,
1749 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 1750 return 2;
1751}
1752
1753static unsigned int dec_bound_r(DisasContext *dc)
1754{
1755 int size = memsize_zz(dc);
1756 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1757 memsize_char(size), dc->op1, dc->op2));
1758 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 1759 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1760 cris_alu(dc, CC_OP_BOUND,
1761 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 1762 return 2;
1763}
1764
1765static unsigned int dec_cmp_r(DisasContext *dc)
1766{
1767 int size = memsize_zz(dc);
1768 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1769 memsize_char(size), dc->op1, dc->op2));
1770 cris_cc_mask(dc, CC_MASK_NZVC);
1771 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1772
1773 cris_alu(dc, CC_OP_CMP,
1774 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1775 return 2;
1776}
1777
1778static unsigned int dec_abs_r(DisasContext *dc)
1779{
3157a0a9
EI		 1780 int l1;
1781
8170028d
TS		 1782 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1783 dc->op1, dc->op2));
1784 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1785 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[1]);
3157a0a9
EI		 1786
1787 /* TODO: consider a branch free approach. */
1788 l1 = gen_new_label();
cb63669a 1789 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
390efc54 1790 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
3157a0a9 1791 gen_set_label(l1);
30abcfc7
EI		 1792 cris_alu(dc, CC_OP_MOVE,
1793 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 1794 return 2;
1795}
1796
1797static unsigned int dec_add_r(DisasContext *dc)
1798{
1799 int size = memsize_zz(dc);
1800 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1801 memsize_char(size), dc->op1, dc->op2));
1802 cris_cc_mask(dc, CC_MASK_NZVC);
1803 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1804
1805 cris_alu(dc, CC_OP_ADD,
1806 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1807 return 2;
1808}
1809
1810static unsigned int dec_addc_r(DisasContext *dc)
1811{
1812 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1813 dc->op1, dc->op2));
1814 cris_evaluate_flags(dc);
1815 cris_cc_mask(dc, CC_MASK_NZVC);
1816 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
30abcfc7
EI		 1817 cris_alu(dc, CC_OP_ADDC,
1818 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 1819 return 2;
1820}
1821
1822static unsigned int dec_mcp_r(DisasContext *dc)
1823{
1824 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1825 dc->op2, dc->op1));
1826 cris_evaluate_flags(dc);
1827 cris_cc_mask(dc, CC_MASK_RNZV);
30abcfc7
EI		 1828 cris_alu(dc, CC_OP_MCP,
1829 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
8170028d
TS		 1830 return 2;
1831}
1832
1833#if DISAS_CRIS
1834static char * swapmode_name(int mode, char *modename) {
1835 int i = 0;
1836 if (mode & 8)
1837 modename[i++] = 'n';
1838 if (mode & 4)
1839 modename[i++] = 'w';
1840 if (mode & 2)
1841 modename[i++] = 'b';
1842 if (mode & 1)
1843 modename[i++] = 'r';
1844 modename[i++] = 0;
1845 return modename;
1846}
1847#endif
1848
1849static unsigned int dec_swap_r(DisasContext *dc)
1850{
cf1d97f0
EI		 1851#if DISAS_CRIS
1852 char modename[4];
1853#endif
8170028d
TS		 1854 DIS(fprintf (logfile, "swap%s $r%u\n",
1855 swapmode_name(dc->op2, modename), dc->op1));
1856
1857 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1858 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
8170028d 1859 if (dc->op2 & 8)
d1896336 1860 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
8170028d 1861 if (dc->op2 & 4)
3157a0a9 1862 t_gen_swapw(cpu_T[0], cpu_T[0]);
8170028d 1863 if (dc->op2 & 2)
3157a0a9 1864 t_gen_swapb(cpu_T[0], cpu_T[0]);
8170028d 1865 if (dc->op2 & 1)
3157a0a9 1866 t_gen_swapr(cpu_T[0], cpu_T[0]);
30abcfc7
EI		 1867 cris_alu(dc, CC_OP_MOVE,
1868 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0], 4);
1869
8170028d
TS		 1870 return 2;
1871}
1872
1873static unsigned int dec_or_r(DisasContext *dc)
1874{
1875 int size = memsize_zz(dc);
1876 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1877 memsize_char(size), dc->op1, dc->op2));
1878 cris_cc_mask(dc, CC_MASK_NZ);
1879 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1880
1881 cris_alu(dc, CC_OP_OR,
1882 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1883 return 2;
1884}
1885
1886static unsigned int dec_addi_r(DisasContext *dc)
1887{
1888 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1889 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1890 cris_cc_mask(dc, 0);
30abcfc7
EI		 1891 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1892 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0]);
8170028d
TS		 1893 return 2;
1894}
1895
1896static unsigned int dec_addi_acr(DisasContext *dc)
1897{
1898 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
b41f7df0 1899 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
8170028d 1900 cris_cc_mask(dc, 0);
30abcfc7
EI		 1901 tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1902 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], cpu_T[0]);
8170028d
TS		 1903 return 2;
1904}
1905
1906static unsigned int dec_neg_r(DisasContext *dc)
1907{
1908 int size = memsize_zz(dc);
1909 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1910 memsize_char(size), dc->op1, dc->op2));
1911 cris_cc_mask(dc, CC_MASK_NZVC);
1912 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1913
1914 cris_alu(dc, CC_OP_NEG,
1915 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1916 return 2;
1917}
1918
1919static unsigned int dec_btst_r(DisasContext *dc)
1920{
1921 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1922 dc->op1, dc->op2));
8170028d
TS		 1923 cris_cc_mask(dc, CC_MASK_NZ);
1924 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
8170028d 1925
30abcfc7
EI		 1926 cris_alu(dc, CC_OP_BTST,
1927 cpu_T[0], cpu_T[0], cpu_T[1], 4);
b41f7df0 1928 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
cf1d97f0 1929 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
30abcfc7 1930 dc->flags_uptodate = 1;
8170028d
TS		 1931 return 2;
1932}
1933
1934static unsigned int dec_sub_r(DisasContext *dc)
1935{
1936 int size = memsize_zz(dc);
1937 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1938 memsize_char(size), dc->op1, dc->op2));
1939 cris_cc_mask(dc, CC_MASK_NZVC);
1940 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
30abcfc7
EI		 1941 cris_alu(dc, CC_OP_SUB,
1942 cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
8170028d
TS		 1943 return 2;
1944}
1945
1946/* Zero extension. From size to dword. */
1947static unsigned int dec_movu_r(DisasContext *dc)
1948{
1949 int size = memsize_z(dc);
1950 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1951 memsize_char(size),
1952 dc->op1, dc->op2));
1953
1954 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 1955 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
1956 cris_alu(dc, CC_OP_MOVE,
1957 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 1958 return 2;
1959}
1960
1961/* Sign extension. From size to dword. */
1962static unsigned int dec_movs_r(DisasContext *dc)
1963{
1964 int size = memsize_z(dc);
1965 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1966 memsize_char(size),
1967 dc->op1, dc->op2));
1968
1969 cris_cc_mask(dc, CC_MASK_NZ);
8170028d 1970 /* Size can only be qi or hi. */
30abcfc7
EI		 1971 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
1972 cris_alu(dc, CC_OP_MOVE,
a7cfbba0 1973 cpu_R[dc->op2], cpu_R[dc->op1], cpu_T[1], 4);
8170028d
TS		 1974 return 2;
1975}
1976
1977/* zero extension. From size to dword. */
1978static unsigned int dec_addu_r(DisasContext *dc)
1979{
1980 int size = memsize_z(dc);
1981 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1982 memsize_char(size),
1983 dc->op1, dc->op2));
1984
1985 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d 1986 /* Size can only be qi or hi. */
30abcfc7
EI		 1987 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
1988 cris_alu(dc, CC_OP_ADD,
1989 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 1990 return 2;
1991}
05ba7d5f 1992
8170028d
TS		 1993/* Sign extension. From size to dword. */
1994static unsigned int dec_adds_r(DisasContext *dc)
1995{
1996 int size = memsize_z(dc);
1997 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1998 memsize_char(size),
1999 dc->op1, dc->op2));
2000
2001 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d 2002 /* Size can only be qi or hi. */
30abcfc7
EI		 2003 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2004 cris_alu(dc, CC_OP_ADD,
2005 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2006 return 2;
2007}
2008
2009/* Zero extension. From size to dword. */
2010static unsigned int dec_subu_r(DisasContext *dc)
2011{
2012 int size = memsize_z(dc);
2013 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
2014 memsize_char(size),
2015 dc->op1, dc->op2));
2016
2017 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d 2018 /* Size can only be qi or hi. */
30abcfc7
EI		 2019 t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
2020 cris_alu(dc, CC_OP_SUB,
2021 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2022 return 2;
2023}
2024
2025/* Sign extension. From size to dword. */
2026static unsigned int dec_subs_r(DisasContext *dc)
2027{
2028 int size = memsize_z(dc);
2029 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
2030 memsize_char(size),
2031 dc->op1, dc->op2));
2032
2033 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d 2034 /* Size can only be qi or hi. */
30abcfc7
EI		 2035 t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
2036 cris_alu(dc, CC_OP_SUB,
2037 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2038 return 2;
2039}
2040
2041static unsigned int dec_setclrf(DisasContext *dc)
2042{
2043 uint32_t flags;
2044 int set = (~dc->opcode >> 2) & 1;
2045
2046 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2047 | EXTRACT_FIELD(dc->ir, 0, 3);
cf1d97f0 2048 if (set && flags == 0) {
8170028d 2049 DIS(fprintf (logfile, "nop\n"));
30abcfc7 2050 return 2;
cf1d97f0 2051 } else if (!set && (flags & 0x20)) {
8170028d 2052 DIS(fprintf (logfile, "di\n"));
cf1d97f0
EI		 2053 }
2054 else {
8170028d 2055 DIS(fprintf (logfile, "%sf %x\n",
cf1d97f0 2056 set ? "set" : "clr",
8170028d 2057 flags));
cf1d97f0 2058 }
8170028d 2059
2a44f7f1
EI		 2060 /* User space is not allowed to touch these. Silently ignore. */
2061 if (dc->tb_flags & U_FLAG) {
2062 flags &= ~(I_FLAG | U_FLAG);
2063 }
2064
2065 if (flags & X_FLAG) {
30abcfc7 2066 dc->flagx_known = 1;
2a44f7f1
EI		 2067 if (set)
2068 dc->flags_x = X_FLAG;
2069 else
2070 dc->flags_x = 0;
8170028d
TS		 2071 }
2072
2a44f7f1
EI		 2073 /* Break the TB if the P flag changes. */
2074 if (flags & P_FLAG) {
2075 if ((set && !(dc->tb_flags & P_FLAG))
2076 || (!set && (dc->tb_flags & P_FLAG))) {
2077 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2078 dc->is_jmp = DISAS_UPDATE;
2079 dc->cpustate_changed = 1;
2080 }
2081 }
2082
2083
8170028d
TS		 2084 /* Simply decode the flags. */
2085 cris_evaluate_flags (dc);
b41f7df0 2086 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
30abcfc7 2087 cris_update_cc_x(dc);
b41f7df0
EI		 2088 tcg_gen_movi_tl(cc_op, dc->cc_op);
2089
dceaf394 2090 if (set) {
2a44f7f1 2091 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
dceaf394
EI		 2092 /* Enter user mode. */
2093 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2094 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2a44f7f1 2095 dc->cpustate_changed = 1;
dceaf394
EI		 2096 }
2097 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2098 }
8170028d 2099 else
dceaf394
EI		 2100 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2101
30abcfc7 2102 dc->flags_uptodate = 1;
b41f7df0 2103 dc->clear_x = 0;
8170028d
TS		 2104 return 2;
2105}
2106
2107static unsigned int dec_move_rs(DisasContext *dc)
2108{
2109 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
2110 cris_cc_mask(dc, 0);
dceaf394
EI		 2111 tcg_gen_helper_0_2(helper_movl_sreg_reg,
2112 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
8170028d
TS		 2113 return 2;
2114}
2115static unsigned int dec_move_sr(DisasContext *dc)
2116{
05ba7d5f 2117 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
8170028d 2118 cris_cc_mask(dc, 0);
dceaf394
EI		 2119 tcg_gen_helper_0_2(helper_movl_reg_sreg,
2120 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
8170028d
TS		 2121 return 2;
2122}
dceaf394 2123
8170028d
TS		 2124static unsigned int dec_move_rp(DisasContext *dc)
2125{
2126 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
2127 cris_cc_mask(dc, 0);
b41f7df0
EI		 2128
2129 if (dc->op2 == PR_CCS) {
2130 cris_evaluate_flags(dc);
2131 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2a44f7f1 2132 if (dc->tb_flags & U_FLAG) {
b41f7df0
EI		 2133 /* User space is not allowed to touch all flags. */
2134 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
2135 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
2136 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
2137 }
2138 }
2139 else
2140 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2141
cf1d97f0 2142 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
b41f7df0
EI		 2143 if (dc->op2 == PR_CCS) {
2144 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
30abcfc7 2145 dc->flags_uptodate = 1;
b41f7df0 2146 }
8170028d
TS		 2147 return 2;
2148}
2149static unsigned int dec_move_pr(DisasContext *dc)
2150{
2151 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
2152 cris_cc_mask(dc, 0);
2a44f7f1
EI		 2153
2154 if (dc->op2 == PR_CCS)
b41f7df0 2155 cris_evaluate_flags(dc);
2a44f7f1
EI		 2156
2157 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2158 cris_alu(dc, CC_OP_MOVE,
30abcfc7
EI		 2159 cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
2160 preg_sizes[dc->op2]);
8170028d
TS		 2161 return 2;
2162}
2163
2164static unsigned int dec_move_mr(DisasContext *dc)
2165{
2166 int memsize = memsize_zz(dc);
2167 int insn_len;
2168 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2169 memsize_char(memsize),
2170 dc->op1, dc->postinc ? "+]" : "]",
2171 dc->op2));
2172
30abcfc7
EI		 2173 if (memsize == 4) {
2174 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2175 cris_cc_mask(dc, CC_MASK_NZ);
2176 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2177 cris_update_cc_x(dc);
2178 cris_update_result(dc, cpu_R[dc->op2]);
2179 }
2180 else {
2181 insn_len = dec_prep_move_m(dc, 0, memsize, cpu_T[1]);
2182 cris_cc_mask(dc, CC_MASK_NZ);
2183 cris_alu(dc, CC_OP_MOVE,
2184 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], memsize);
2185 }
8170028d
TS		 2186 do_postinc(dc, memsize);
2187 return insn_len;
2188}
2189
2190static unsigned int dec_movs_m(DisasContext *dc)
2191{
2192 int memsize = memsize_z(dc);
2193 int insn_len;
2194 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2195 memsize_char(memsize),
2196 dc->op1, dc->postinc ? "+]" : "]",
2197 dc->op2));
2198
2199 /* sign extend. */
8170028d 2200 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2201 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 2202 cris_alu(dc, CC_OP_MOVE,
2203 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2204 do_postinc(dc, memsize);
2205 return insn_len;
2206}
2207
2208static unsigned int dec_addu_m(DisasContext *dc)
2209{
2210 int memsize = memsize_z(dc);
2211 int insn_len;
2212 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2213 memsize_char(memsize),
2214 dc->op1, dc->postinc ? "+]" : "]",
2215 dc->op2));
2216
2217 /* sign extend. */
8170028d 2218 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2219 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2220 cris_alu(dc, CC_OP_ADD,
2221 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2222 do_postinc(dc, memsize);
2223 return insn_len;
2224}
2225
2226static unsigned int dec_adds_m(DisasContext *dc)
2227{
2228 int memsize = memsize_z(dc);
2229 int insn_len;
2230 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2231 memsize_char(memsize),
2232 dc->op1, dc->postinc ? "+]" : "]",
2233 dc->op2));
2234
2235 /* sign extend. */
8170028d 2236 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2237 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2238 cris_alu(dc, CC_OP_ADD,
2239 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2240 do_postinc(dc, memsize);
2241 return insn_len;
2242}
2243
2244static unsigned int dec_subu_m(DisasContext *dc)
2245{
2246 int memsize = memsize_z(dc);
2247 int insn_len;
2248 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2249 memsize_char(memsize),
2250 dc->op1, dc->postinc ? "+]" : "]",
2251 dc->op2));
2252
2253 /* sign extend. */
8170028d 2254 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2255 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2256 cris_alu(dc, CC_OP_SUB,
2257 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2258 do_postinc(dc, memsize);
2259 return insn_len;
2260}
2261
2262static unsigned int dec_subs_m(DisasContext *dc)
2263{
2264 int memsize = memsize_z(dc);
2265 int insn_len;
2266 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2267 memsize_char(memsize),
2268 dc->op1, dc->postinc ? "+]" : "]",
2269 dc->op2));
2270
2271 /* sign extend. */
8170028d 2272 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2273 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2274 cris_alu(dc, CC_OP_SUB,
2275 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2276 do_postinc(dc, memsize);
2277 return insn_len;
2278}
2279
2280static unsigned int dec_movu_m(DisasContext *dc)
2281{
2282 int memsize = memsize_z(dc);
2283 int insn_len;
2284
2285 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2286 memsize_char(memsize),
2287 dc->op1, dc->postinc ? "+]" : "]",
2288 dc->op2));
2289
8170028d 2290 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2291 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 2292 cris_alu(dc, CC_OP_MOVE,
2293 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2294 do_postinc(dc, memsize);
2295 return insn_len;
2296}
2297
2298static unsigned int dec_cmpu_m(DisasContext *dc)
2299{
2300 int memsize = memsize_z(dc);
2301 int insn_len;
2302 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2303 memsize_char(memsize),
2304 dc->op1, dc->postinc ? "+]" : "]",
2305 dc->op2));
2306
8170028d 2307 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2308 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2309 cris_alu(dc, CC_OP_CMP,
2310 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
8170028d
TS		 2311 do_postinc(dc, memsize);
2312 return insn_len;
2313}
2314
2315static unsigned int dec_cmps_m(DisasContext *dc)
2316{
2317 int memsize = memsize_z(dc);
2318 int insn_len;
2319 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2320 memsize_char(memsize),
2321 dc->op1, dc->postinc ? "+]" : "]",
2322 dc->op2));
2323
8170028d 2324 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2325 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2326 cris_alu(dc, CC_OP_CMP,
2327 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2328 memsize_zz(dc));
8170028d
TS		 2329 do_postinc(dc, memsize);
2330 return insn_len;
2331}
2332
2333static unsigned int dec_cmp_m(DisasContext *dc)
2334{
2335 int memsize = memsize_zz(dc);
2336 int insn_len;
2337 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2338 memsize_char(memsize),
2339 dc->op1, dc->postinc ? "+]" : "]",
2340 dc->op2));
2341
8170028d 2342 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2343 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2344 cris_alu(dc, CC_OP_CMP,
2345 cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
2346 memsize_zz(dc));
8170028d
TS		 2347 do_postinc(dc, memsize);
2348 return insn_len;
2349}
2350
2351static unsigned int dec_test_m(DisasContext *dc)
2352{
2353 int memsize = memsize_zz(dc);
2354 int insn_len;
2355 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2356 memsize_char(memsize),
2357 dc->op1, dc->postinc ? "+]" : "]",
2358 dc->op2));
2359
dceaf394
EI		 2360 cris_evaluate_flags(dc);
2361
b41f7df0 2362 insn_len = dec_prep_alu_m(dc, 0, memsize);
8170028d 2363 cris_cc_mask(dc, CC_MASK_NZ);
dceaf394 2364 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
b41f7df0 2365
30abcfc7
EI		 2366 cris_alu(dc, CC_OP_CMP,
2367 cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
2368 memsize_zz(dc));
8170028d
TS		 2369 do_postinc(dc, memsize);
2370 return insn_len;
2371}
2372
2373static unsigned int dec_and_m(DisasContext *dc)
2374{
2375 int memsize = memsize_zz(dc);
2376 int insn_len;
2377 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2378 memsize_char(memsize),
2379 dc->op1, dc->postinc ? "+]" : "]",
2380 dc->op2));
2381
8170028d 2382 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2383 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 2384 cris_alu(dc, CC_OP_AND,
2385 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2386 memsize_zz(dc));
8170028d
TS		 2387 do_postinc(dc, memsize);
2388 return insn_len;
2389}
2390
2391static unsigned int dec_add_m(DisasContext *dc)
2392{
2393 int memsize = memsize_zz(dc);
2394 int insn_len;
2395 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2396 memsize_char(memsize),
2397 dc->op1, dc->postinc ? "+]" : "]",
2398 dc->op2));
2399
8170028d 2400 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2401 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2402 cris_alu(dc, CC_OP_ADD,
2403 cpu_R[dc->op2], cpu_T[0], cpu_T[1],
2404 memsize_zz(dc));
8170028d
TS		 2405 do_postinc(dc, memsize);
2406 return insn_len;
2407}
2408
2409static unsigned int dec_addo_m(DisasContext *dc)
2410{
2411 int memsize = memsize_zz(dc);
2412 int insn_len;
2413 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2414 memsize_char(memsize),
2415 dc->op1, dc->postinc ? "+]" : "]",
2416 dc->op2));
2417
8170028d 2418 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2419 cris_cc_mask(dc, 0);
30abcfc7
EI		 2420 cris_alu(dc, CC_OP_ADD,
2421 cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 2422 do_postinc(dc, memsize);
2423 return insn_len;
2424}
2425
2426static unsigned int dec_bound_m(DisasContext *dc)
2427{
2428 int memsize = memsize_zz(dc);
2429 int insn_len;
2430 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2431 memsize_char(memsize),
2432 dc->op1, dc->postinc ? "+]" : "]",
2433 dc->op2));
2434
8170028d 2435 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2436 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 2437 cris_alu(dc, CC_OP_BOUND,
2438 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 2439 do_postinc(dc, memsize);
2440 return insn_len;
2441}
2442
2443static unsigned int dec_addc_mr(DisasContext *dc)
2444{
2445 int insn_len = 2;
2446 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2447 dc->op1, dc->postinc ? "+]" : "]",
2448 dc->op2));
2449
2450 cris_evaluate_flags(dc);
8170028d 2451 insn_len = dec_prep_alu_m(dc, 0, 4);
b41f7df0 2452 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2453 cris_alu(dc, CC_OP_ADDC,
2454 cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
8170028d
TS		 2455 do_postinc(dc, 4);
2456 return insn_len;
2457}
2458
2459static unsigned int dec_sub_m(DisasContext *dc)
2460{
2461 int memsize = memsize_zz(dc);
2462 int insn_len;
2463 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2464 memsize_char(memsize),
2465 dc->op1, dc->postinc ? "+]" : "]",
2466 dc->op2, dc->ir, dc->zzsize));
2467
8170028d 2468 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2469 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7
EI		 2470 cris_alu(dc, CC_OP_SUB,
2471 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
8170028d
TS		 2472 do_postinc(dc, memsize);
2473 return insn_len;
2474}
2475
2476static unsigned int dec_or_m(DisasContext *dc)
2477{
2478 int memsize = memsize_zz(dc);
2479 int insn_len;
2480 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2481 memsize_char(memsize),
2482 dc->op1, dc->postinc ? "+]" : "]",
2483 dc->op2, dc->pc));
2484
8170028d 2485 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2486 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7
EI		 2487 cris_alu(dc, CC_OP_OR,
2488 cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
8170028d
TS		 2489 do_postinc(dc, memsize);
2490 return insn_len;
2491}
2492
2493static unsigned int dec_move_mp(DisasContext *dc)
2494{
2495 int memsize = memsize_zz(dc);
2496 int insn_len = 2;
2497
2498 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2499 memsize_char(memsize),
2500 dc->op1,
2501 dc->postinc ? "+]" : "]",
2502 dc->op2));
2503
8170028d 2504 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0
EI		 2505 cris_cc_mask(dc, 0);
2506 if (dc->op2 == PR_CCS) {
2507 cris_evaluate_flags(dc);
2a44f7f1 2508 if (dc->tb_flags & U_FLAG) {
b41f7df0
EI		 2509 /* User space is not allowed to touch all flags. */
2510 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2511 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2512 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2513 }
2514 }
2515
cf1d97f0 2516 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
8170028d
TS		 2517
2518 do_postinc(dc, memsize);
2519 return insn_len;
2520}
2521
2522static unsigned int dec_move_pm(DisasContext *dc)
2523{
2524 int memsize;
2525
2526 memsize = preg_sizes[dc->op2];
2527
fd56059f
AZ		 2528 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2529 memsize_char(memsize),
2530 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
8170028d 2531
fd56059f 2532 /* prepare store. Address in T0, value in T1. */
17ac9754
EI		 2533 if (dc->op2 == PR_CCS)
2534 cris_evaluate_flags(dc);
05ba7d5f 2535 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
30abcfc7 2536 cris_flush_cc_state(dc);
17ac9754
EI		 2537 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2538
b41f7df0 2539 cris_cc_mask(dc, 0);
8170028d 2540 if (dc->postinc)
17ac9754 2541 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
8170028d
TS		 2542 return 2;
2543}
2544
2545static unsigned int dec_movem_mr(DisasContext *dc)
2546{
17ac9754 2547 TCGv tmp[16];
8170028d
TS		 2548 int i;
2549
2550 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2551 dc->postinc ? "+]" : "]", dc->op2));
2552
05ba7d5f 2553 /* fetch the address into T0 and T1. */
30abcfc7 2554 cris_flush_cc_state(dc);
8170028d 2555 for (i = 0; i <= dc->op2; i++) {
17ac9754 2556 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
8170028d 2557 /* Perform the load onto regnum i. Always dword wide. */
17ac9754
EI		 2558 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2559 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
8170028d 2560 }
17ac9754
EI		 2561
2562 for (i = 0; i <= dc->op2; i++) {
2563 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
30abcfc7 2564 tcg_temp_free(tmp[i]);
17ac9754
EI		 2565 }
2566
05ba7d5f
EI		 2567 /* writeback the updated pointer value. */
2568 if (dc->postinc)
17ac9754 2569 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
b41f7df0
EI		 2570
2571 /* gen_load might want to evaluate the previous insns flags. */
2572 cris_cc_mask(dc, 0);
8170028d
TS		 2573 return 2;
2574}
2575
2576static unsigned int dec_movem_rm(DisasContext *dc)
2577{
30abcfc7 2578 TCGv tmp;
8170028d
TS		 2579 int i;
2580
2581 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2582 dc->postinc ? "+]" : "]"));
2583
30abcfc7
EI		 2584 cris_flush_cc_state(dc);
2585
2586 tmp = tcg_temp_new(TCG_TYPE_TL);
2587 tcg_gen_movi_tl(tmp, 4);
2588 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
8170028d 2589 for (i = 0; i <= dc->op2; i++) {
17ac9754 2590 /* Displace addr. */
8170028d 2591 /* Perform the store. */
17ac9754 2592 gen_store(dc, cpu_T[0], cpu_R[i], 4);
30abcfc7 2593 tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
8170028d 2594 }
17ac9754 2595 if (dc->postinc)
30abcfc7 2596 tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
b41f7df0 2597 cris_cc_mask(dc, 0);
30abcfc7 2598 tcg_temp_free(tmp);
8170028d
TS		 2599 return 2;
2600}
2601
2602static unsigned int dec_move_rm(DisasContext *dc)
2603{
2604 int memsize;
2605
2606 memsize = memsize_zz(dc);
2607
2608 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2609 memsize, dc->op2, dc->op1));
2610
8170028d 2611 /* prepare store. */
30abcfc7 2612 cris_flush_cc_state(dc);
17ac9754
EI		 2613 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2614
8170028d 2615 if (dc->postinc)
17ac9754 2616 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
b41f7df0 2617 cris_cc_mask(dc, 0);
8170028d
TS		 2618 return 2;
2619}
2620
8170028d
TS		 2621static unsigned int dec_lapcq(DisasContext *dc)
2622{
2623 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2624 dc->pc + dc->op1*2, dc->op2));
2625 cris_cc_mask(dc, 0);
30abcfc7 2626 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
8170028d
TS		 2627 return 2;
2628}
2629
2630static unsigned int dec_lapc_im(DisasContext *dc)
2631{
2632 unsigned int rd;
2633 int32_t imm;
b41f7df0 2634 int32_t pc;
8170028d
TS		 2635
2636 rd = dc->op2;
2637
2638 cris_cc_mask(dc, 0);
2639 imm = ldl_code(dc->pc + 2);
2640 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
b41f7df0
EI		 2641
2642 pc = dc->pc;
2643 pc += imm;
2644 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
05ba7d5f 2645 return 6;
8170028d
TS		 2646}
2647
2648/* Jump to special reg. */
2649static unsigned int dec_jump_p(DisasContext *dc)
2650{
2651 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
b41f7df0 2652
17ac9754
EI		 2653 if (dc->op2 == PR_CCS)
2654 cris_evaluate_flags(dc);
05ba7d5f 2655 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
b41f7df0
EI		 2656 /* rete will often have low bit set to indicate delayslot. */
2657 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
17ac9754 2658 cris_cc_mask(dc, 0);
2a44f7f1 2659 cris_prepare_jmp(dc, JMP_INDIRECT);
8170028d
TS		 2660 return 2;
2661}
2662
2663/* Jump and save. */
2664static unsigned int dec_jas_r(DisasContext *dc)
2665{
2666 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2667 cris_cc_mask(dc, 0);
b41f7df0
EI		 2668 /* Store the return address in Pd. */
2669 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2670 if (dc->op2 > 15)
2671 abort();
30abcfc7 2672 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
b41f7df0 2673
2a44f7f1 2674 cris_prepare_jmp(dc, JMP_INDIRECT);
8170028d
TS		 2675 return 2;
2676}
2677
2678static unsigned int dec_jas_im(DisasContext *dc)
2679{
2680 uint32_t imm;
2681
2682 imm = ldl_code(dc->pc + 2);
2683
2684 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2685 cris_cc_mask(dc, 0);
17ac9754 2686 /* Store the return address in Pd. */
cf1d97f0 2687 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2a44f7f1
EI		 2688
2689 dc->jmp_pc = imm;
2690 cris_prepare_jmp(dc, JMP_DIRECT);
8170028d
TS		 2691 return 6;
2692}
2693
2694static unsigned int dec_jasc_im(DisasContext *dc)
2695{
2696 uint32_t imm;
2697
2698 imm = ldl_code(dc->pc + 2);
2699
2700 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2701 cris_cc_mask(dc, 0);
17ac9754 2702 /* Store the return address in Pd. */
2a44f7f1
EI		 2703 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2704
2705 dc->jmp_pc = imm;
2706 cris_prepare_jmp(dc, JMP_DIRECT);
8170028d
TS		 2707 return 6;
2708}
2709
2710static unsigned int dec_jasc_r(DisasContext *dc)
2711{
2712 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2713 cris_cc_mask(dc, 0);
17ac9754 2714 /* Store the return address in Pd. */
2a44f7f1
EI		 2715 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2716 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2717 cris_prepare_jmp(dc, JMP_INDIRECT);
8170028d
TS		 2718 return 2;
2719}
2720
2721static unsigned int dec_bcc_im(DisasContext *dc)
2722{
2723 int32_t offset;
2724 uint32_t cond = dc->op2;
2725
17ac9754 2726 offset = ldsw_code(dc->pc + 2);
8170028d
TS		 2727
2728 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2729 cc_name(cond), offset,
2730 dc->pc, dc->pc + offset));
2731
2732 cris_cc_mask(dc, 0);
2733 /* op2 holds the condition-code. */
2734 cris_prepare_cc_branch (dc, offset, cond);
2735 return 4;
2736}
2737
2738static unsigned int dec_bas_im(DisasContext *dc)
2739{
2740 int32_t simm;
2741
2742
2743 simm = ldl_code(dc->pc + 2);
2744
2745 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2746 cris_cc_mask(dc, 0);
2a44f7f1
EI		 2747 /* Store the return address in Pd. */
2748 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2749
2750 dc->jmp_pc = dc->pc + simm;
2751 cris_prepare_jmp(dc, JMP_DIRECT);
8170028d
TS		 2752 return 6;
2753}
2754
2755static unsigned int dec_basc_im(DisasContext *dc)
2756{
2757 int32_t simm;
2758 simm = ldl_code(dc->pc + 2);
2759
2760 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2761 cris_cc_mask(dc, 0);
2a44f7f1
EI		 2762 /* Store the return address in Pd. */
2763 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2764
2765 dc->jmp_pc = dc->pc + simm;
2766 cris_prepare_jmp(dc, JMP_DIRECT);
8170028d
TS		 2767 return 6;
2768}
2769
2770static unsigned int dec_rfe_etc(DisasContext *dc)
2771{
2772 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2773 dc->opcode, dc->pc, dc->op1, dc->op2));
2774
2775 cris_cc_mask(dc, 0);
2776
2777 if (dc->op2 == 15) /* ignore halt. */
05ba7d5f 2778 return 2;
8170028d
TS		 2779
2780 switch (dc->op2 & 7) {
2781 case 2:
2782 /* rfe. */
2783 cris_evaluate_flags(dc);
b41f7df0
EI		 2784 tcg_gen_helper_0_0(helper_rfe);
2785 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2786 break;
2787 case 5:
2788 /* rfn. */
a7cfbba0
EI		 2789 cris_evaluate_flags(dc);
2790 tcg_gen_helper_0_0(helper_rfn);
2791 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2792 break;
2793 case 6:
2794 /* break. */
2a44f7f1 2795 tcg_gen_movi_tl(env_pc, dc->pc);
8170028d 2796 /* Breaks start at 16 in the exception vector. */
dceaf394
EI		 2797 t_gen_mov_env_TN(trap_vector,
2798 tcg_const_tl(dc->op1 + 16));
2799 t_gen_raise_exception(EXCP_BREAK);
b41f7df0 2800 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2801 break;
2802 default:
2803 printf ("op2=%x\n", dc->op2);
2804 BUG();
2805 break;
2806
2807 }
8170028d
TS		 2808 return 2;
2809}
2810
5d4a534d
EI		 2811static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2812{
2813 /* Ignore D-cache flushes. */
2814 return 2;
2815}
2816
2817static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2818{
2819 /* Ignore I-cache flushes. */
2820 return 2;
2821}
2822
8170028d
TS		 2823static unsigned int dec_null(DisasContext *dc)
2824{
2825 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2826 dc->pc, dc->opcode, dc->op1, dc->op2);
2827 fflush(NULL);
2828 BUG();
2829 return 2;
2830}
2831
2832struct decoder_info {
2833 struct {
2834 uint32_t bits;
2835 uint32_t mask;
2836 };
2837 unsigned int (*dec)(DisasContext *dc);
2838} decinfo[] = {
2839 /* Order matters here. */
2840 {DEC_MOVEQ, dec_moveq},
2841 {DEC_BTSTQ, dec_btstq},
2842 {DEC_CMPQ, dec_cmpq},
2843 {DEC_ADDOQ, dec_addoq},
2844 {DEC_ADDQ, dec_addq},
2845 {DEC_SUBQ, dec_subq},
2846 {DEC_ANDQ, dec_andq},
2847 {DEC_ORQ, dec_orq},
2848 {DEC_ASRQ, dec_asrq},
2849 {DEC_LSLQ, dec_lslq},
2850 {DEC_LSRQ, dec_lsrq},
2851 {DEC_BCCQ, dec_bccq},
2852
2853 {DEC_BCC_IM, dec_bcc_im},
2854 {DEC_JAS_IM, dec_jas_im},
2855 {DEC_JAS_R, dec_jas_r},
2856 {DEC_JASC_IM, dec_jasc_im},
2857 {DEC_JASC_R, dec_jasc_r},
2858 {DEC_BAS_IM, dec_bas_im},
2859 {DEC_BASC_IM, dec_basc_im},
2860 {DEC_JUMP_P, dec_jump_p},
2861 {DEC_LAPC_IM, dec_lapc_im},
2862 {DEC_LAPCQ, dec_lapcq},
2863
2864 {DEC_RFE_ETC, dec_rfe_etc},
2865 {DEC_ADDC_MR, dec_addc_mr},
2866
2867 {DEC_MOVE_MP, dec_move_mp},
2868 {DEC_MOVE_PM, dec_move_pm},
2869 {DEC_MOVEM_MR, dec_movem_mr},
2870 {DEC_MOVEM_RM, dec_movem_rm},
2871 {DEC_MOVE_PR, dec_move_pr},
2872 {DEC_SCC_R, dec_scc_r},
2873 {DEC_SETF, dec_setclrf},
2874 {DEC_CLEARF, dec_setclrf},
2875
2876 {DEC_MOVE_SR, dec_move_sr},
2877 {DEC_MOVE_RP, dec_move_rp},
2878 {DEC_SWAP_R, dec_swap_r},
2879 {DEC_ABS_R, dec_abs_r},
2880 {DEC_LZ_R, dec_lz_r},
2881 {DEC_MOVE_RS, dec_move_rs},
2882 {DEC_BTST_R, dec_btst_r},
2883 {DEC_ADDC_R, dec_addc_r},
2884
2885 {DEC_DSTEP_R, dec_dstep_r},
2886 {DEC_XOR_R, dec_xor_r},
2887 {DEC_MCP_R, dec_mcp_r},
2888 {DEC_CMP_R, dec_cmp_r},
2889
2890 {DEC_ADDI_R, dec_addi_r},
2891 {DEC_ADDI_ACR, dec_addi_acr},
2892
2893 {DEC_ADD_R, dec_add_r},
2894 {DEC_SUB_R, dec_sub_r},
2895
2896 {DEC_ADDU_R, dec_addu_r},
2897 {DEC_ADDS_R, dec_adds_r},
2898 {DEC_SUBU_R, dec_subu_r},
2899 {DEC_SUBS_R, dec_subs_r},
2900 {DEC_LSL_R, dec_lsl_r},
2901
2902 {DEC_AND_R, dec_and_r},
2903 {DEC_OR_R, dec_or_r},
2904 {DEC_BOUND_R, dec_bound_r},
2905 {DEC_ASR_R, dec_asr_r},
2906 {DEC_LSR_R, dec_lsr_r},
2907
2908 {DEC_MOVU_R, dec_movu_r},
2909 {DEC_MOVS_R, dec_movs_r},
2910 {DEC_NEG_R, dec_neg_r},
2911 {DEC_MOVE_R, dec_move_r},
2912
5d4a534d
EI		 2913 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2914 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
8170028d
TS		 2915
2916 {DEC_MULS_R, dec_muls_r},
2917 {DEC_MULU_R, dec_mulu_r},
2918
2919 {DEC_ADDU_M, dec_addu_m},
2920 {DEC_ADDS_M, dec_adds_m},
2921 {DEC_SUBU_M, dec_subu_m},
2922 {DEC_SUBS_M, dec_subs_m},
2923
2924 {DEC_CMPU_M, dec_cmpu_m},
2925 {DEC_CMPS_M, dec_cmps_m},
2926 {DEC_MOVU_M, dec_movu_m},
2927 {DEC_MOVS_M, dec_movs_m},
2928
2929 {DEC_CMP_M, dec_cmp_m},
2930 {DEC_ADDO_M, dec_addo_m},
2931 {DEC_BOUND_M, dec_bound_m},
2932 {DEC_ADD_M, dec_add_m},
2933 {DEC_SUB_M, dec_sub_m},
2934 {DEC_AND_M, dec_and_m},
2935 {DEC_OR_M, dec_or_m},
2936 {DEC_MOVE_RM, dec_move_rm},
2937 {DEC_TEST_M, dec_test_m},
2938 {DEC_MOVE_MR, dec_move_mr},
2939
2940 {{0, 0}, dec_null}
2941};
2942
2943static inline unsigned int
2944cris_decoder(DisasContext *dc)
2945{
2946 unsigned int insn_len = 2;
8170028d
TS		 2947 int i;
2948
2949 /* Load a halfword onto the instruction register. */
17ac9754 2950 dc->ir = lduw_code(dc->pc);
8170028d
TS		 2951
2952 /* Now decode it. */
2953 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2954 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2955 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2956 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2957 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2958 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2959
2960 /* Large switch for all insns. */
2961 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2962 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2963 {
2964 insn_len = decinfo[i].dec(dc);
2965 break;
2966 }
2967 }
2968
2969 return insn_len;
2970}
2971
2972static void check_breakpoint(CPUState *env, DisasContext *dc)
2973{
2974 int j;
2975 if (env->nb_breakpoints > 0) {
2976 for(j = 0; j < env->nb_breakpoints; j++) {
2977 if (env->breakpoints[j] == dc->pc) {
2978 cris_evaluate_flags (dc);
2a44f7f1 2979 tcg_gen_movi_tl(env_pc, dc->pc);
dceaf394 2980 t_gen_raise_exception(EXCP_DEBUG);
8170028d
TS		 2981 dc->is_jmp = DISAS_UPDATE;
2982 }
2983 }
2984 }
2985}
2986
cf1d97f0
EI		 2987
2988/*
2989 * Delay slots on QEMU/CRIS.
2990 *
2991 * If an exception hits on a delayslot, the core will let ERP (the Exception
2992 * Return Pointer) point to the branch (the previous) insn and set the lsb to
2993 * to give SW a hint that the exception actually hit on the dslot.
2994 *
2995 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
2996 * the core and any jmp to an odd addresses will mask off that lsb. It is
2997 * simply there to let sw know there was an exception on a dslot.
2998 *
2999 * When the software returns from an exception, the branch will re-execute.
3000 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3001 * and the branch and delayslot dont share pages.
3002 *
3003 * The TB contaning the branch insn will set up env->btarget and evaluate
3004 * env->btaken. When the translation loop exits we will note that the branch
3005 * sequence is broken and let env->dslot be the size of the branch insn (those
3006 * vary in length).
3007 *
3008 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3009 * set). It will also expect to have env->dslot setup with the size of the
3010 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3011 * will execute the dslot and take the branch, either to btarget or just one
3012 * insn ahead.
3013 *
3014 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3015 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3016 * branch and set lsb). Then env->dslot gets cleared so that the exception
3017 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3018 * masked off and we will reexecute the branch insn.
3019 *
3020 */
3021
8170028d 3022/* generate intermediate code for basic block 'tb'. */
8170028d
TS		 3023static int
3024gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3025 int search_pc)
3026{
3027 uint16_t *gen_opc_end;
3028 uint32_t pc_start;
3029 unsigned int insn_len;
3030 int j, lj;
cf1d97f0 3031 struct DisasContext ctx;
8170028d
TS		 3032 struct DisasContext *dc = &ctx;
3033 uint32_t next_page_start;
2a44f7f1 3034 target_ulong npc;
8170028d 3035
a825e703
EI		 3036 if (!logfile)
3037 logfile = stderr;
3038
73e51723
EI		 3039 /* Odd PC indicates that branch is rexecuting due to exception in the
3040 * delayslot, like in real hw.
73e51723
EI		 3041 */
3042 pc_start = tb->pc & ~1;
8170028d
TS		 3043 dc->env = env;
3044 dc->tb = tb;
3045
8170028d 3046 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8170028d
TS		 3047
3048 dc->is_jmp = DISAS_NEXT;
b41f7df0 3049 dc->ppc = pc_start;
8170028d
TS		 3050 dc->pc = pc_start;
3051 dc->singlestep_enabled = env->singlestep_enabled;
30abcfc7
EI		 3052 dc->flags_uptodate = 1;
3053 dc->flagx_known = 1;
3054 dc->flags_x = tb->flags & X_FLAG;
3055 dc->cc_x_uptodate = 0;
b41f7df0 3056 dc->cc_mask = 0;
cf1d97f0 3057 dc->update_cc = 0;
30abcfc7 3058
b41f7df0 3059 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
30abcfc7 3060 dc->cc_size_uptodate = -1;
b41f7df0 3061
cf1d97f0 3062 /* Decode TB flags. */
2a44f7f1 3063 dc->tb_flags = tb->flags & (P_FLAG | U_FLAG | X_FLAG);
cf1d97f0 3064 dc->delayed_branch = !!(tb->flags & 7);
2a44f7f1
EI		 3065 if (dc->delayed_branch)
3066 dc->jmp = JMP_INDIRECT;
3067 else
3068 dc->jmp = JMP_NOJMP;
3069
3070 dc->cpustate_changed = 0;
b41f7df0
EI		 3071
3072 if (loglevel & CPU_LOG_TB_IN_ASM) {
3073 fprintf(logfile,
2a44f7f1 3074 "srch=%d pc=%x %x flg=%llx bt=%x ds=%lld ccs=%x\n"
30abcfc7 3075 "pid=%x usp=%x\n"
b41f7df0
EI		 3076 "%x.%x.%x.%x\n"
3077 "%x.%x.%x.%x\n"
3078 "%x.%x.%x.%x\n"
3079 "%x.%x.%x.%x\n",
2a44f7f1 3080 search_pc, dc->pc, dc->ppc, tb->flags,
cf1d97f0
EI		 3081 env->btarget, tb->flags & 7,
3082 env->pregs[PR_CCS],
b41f7df0
EI		 3083 env->pregs[PR_PID], env->pregs[PR_USP],
3084 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3085 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3086 env->regs[8], env->regs[9],
3087 env->regs[10], env->regs[11],
3088 env->regs[12], env->regs[13],
3089 env->regs[14], env->regs[15]);
3090
3091 }
3157a0a9 3092
8170028d
TS		 3093 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3094 lj = -1;
3095 do
3096 {
3097 check_breakpoint(env, dc);
8170028d
TS		 3098
3099 if (search_pc) {
3100 j = gen_opc_ptr - gen_opc_buf;
3101 if (lj < j) {
3102 lj++;
3103 while (lj < j)
3104 gen_opc_instr_start[lj++] = 0;
3105 }
cf1d97f0 3106 if (dc->delayed_branch == 1)
b41f7df0 3107 gen_opc_pc[lj] = dc->ppc | 1;
cf1d97f0 3108 else
b41f7df0 3109 gen_opc_pc[lj] = dc->pc;
cf1d97f0
EI		 3110 gen_opc_instr_start[lj] = 1;
3111 }
3112
3113 /* Pretty disas. */
3114 DIS(fprintf(logfile, "%x ", dc->pc));
3115 if (search_pc) {
3116 DIS(fprintf(logfile, "%x ", dc->pc));
8170028d
TS		 3117 }
3118
b41f7df0 3119 dc->clear_x = 1;
30abcfc7
EI		 3120 if (unlikely(loglevel & CPU_LOG_TB_OP))
3121 tcg_gen_debug_insn_start(dc->pc);
8170028d 3122 insn_len = cris_decoder(dc);
b41f7df0 3123 dc->ppc = dc->pc;
8170028d 3124 dc->pc += insn_len;
b41f7df0
EI		 3125 if (dc->clear_x)
3126 cris_clear_x_flag(dc);
8170028d
TS		 3127
3128 /* Check for delayed branches here. If we do it before
3129 actually genereating any host code, the simulator will just
3130 loop doing nothing for on this program location. */
3131 if (dc->delayed_branch) {
3132 dc->delayed_branch--;
3133 if (dc->delayed_branch == 0)
3134 {
2a44f7f1
EI		 3135 if (tb->flags & 7)
3136 t_gen_mov_env_TN(dslot,
3137 tcg_const_tl(0));
3138 if (dc->jmp == JMP_DIRECT) {
3139 dc->is_jmp = DISAS_NEXT;
3140 } else {
3141 t_gen_cc_jmp(env_btarget,
3142 tcg_const_tl(dc->pc));
3143 dc->is_jmp = DISAS_JUMP;
3144 }
3145 break;
8170028d
TS		 3146 }
3147 }
3148
73e51723
EI		 3149 /* If we are rexecuting a branch due to exceptions on
3150 delay slots dont break. */
3151 if (!(tb->pc & 1) && env->singlestep_enabled)
8170028d
TS		 3152 break;
3153 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
cf1d97f0 3154 && (dc->pc < next_page_start));
b41f7df0 3155
2a44f7f1
EI		 3156 npc = dc->pc;
3157 if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
3158 npc = dc->jmp_pc;
3159
3160 /* Force an update if the per-tb cpu state has changed. */
3161 if (dc->is_jmp == DISAS_NEXT
3162 && (dc->cpustate_changed || !dc->flagx_known
3163 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3164 dc->is_jmp = DISAS_UPDATE;
3165 tcg_gen_movi_tl(env_pc, npc);
3166 }
cf1d97f0 3167 /* Broken branch+delayslot sequence. */
b41f7df0 3168 if (dc->delayed_branch == 1) {
cf1d97f0
EI		 3169 /* Set env->dslot to the size of the branch insn. */
3170 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
2a44f7f1 3171 cris_store_direct_jmp(dc);
8170028d
TS		 3172 }
3173
3174 cris_evaluate_flags (dc);
2a44f7f1 3175
8170028d 3176 if (__builtin_expect(env->singlestep_enabled, 0)) {
2a44f7f1 3177 tcg_gen_movi_tl(env_pc, npc);
dceaf394 3178 t_gen_raise_exception(EXCP_DEBUG);
8170028d
TS		 3179 } else {
3180 switch(dc->is_jmp) {
3181 case DISAS_NEXT:
2a44f7f1 3182 gen_goto_tb(dc, 1, npc);
8170028d
TS		 3183 break;
3184 default:
3185 case DISAS_JUMP:
3186 case DISAS_UPDATE:
3187 /* indicate that the hash table must be used
3188 to find the next TB */
57fec1fe 3189 tcg_gen_exit_tb(0);
8170028d 3190 break;
4f400ab5 3191 case DISAS_SWI:
8170028d
TS		 3192 case DISAS_TB_JUMP:
3193 /* nothing more to generate */
3194 break;
3195 }
3196 }
3197 *gen_opc_ptr = INDEX_op_end;
3198 if (search_pc) {
3199 j = gen_opc_ptr - gen_opc_buf;
3200 lj++;
3201 while (lj <= j)
3202 gen_opc_instr_start[lj++] = 0;
3203 } else {
3204 tb->size = dc->pc - pc_start;
3205 }
3206
3207#ifdef DEBUG_DISAS
3208 if (loglevel & CPU_LOG_TB_IN_ASM) {
3209 fprintf(logfile, "--------------\n");
3210 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
17ac9754 3211 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
b41f7df0
EI		 3212 fprintf(logfile, "\nisize=%d osize=%d\n",
3213 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
8170028d
TS		 3214 }
3215#endif
3216 return 0;
3217}
3218
3219int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3220{
3221 return gen_intermediate_code_internal(env, tb, 0);
3222}
3223
3224int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3225{
3226 return gen_intermediate_code_internal(env, tb, 1);
3227}
3228
3229void cpu_dump_state (CPUState *env, FILE *f,
3230 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3231 int flags)
3232{
3233 int i;
3234 uint32_t srs;
3235
3236 if (!env || !f)
3237 return;
3238
3239 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
30abcfc7 3240 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
9004627f 3241 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
8170028d 3242 env->cc_op,
30abcfc7
EI		 3243 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3244
8170028d
TS		 3245
3246 for (i = 0; i < 16; i++) {
3247 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3248 if ((i + 1) % 4 == 0)
3249 cpu_fprintf(f, "\n");
3250 }
3251 cpu_fprintf(f, "\nspecial regs:\n");
3252 for (i = 0; i < 16; i++) {
3253 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3254 if ((i + 1) % 4 == 0)
3255 cpu_fprintf(f, "\n");
3256 }
9004627f 3257 srs = env->pregs[PR_SRS];
b41f7df0 3258 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
8170028d
TS		 3259 if (srs < 256) {
3260 for (i = 0; i < 16; i++) {
3261 cpu_fprintf(f, "s%2.2d=%8.8x ",
3262 i, env->sregs[srs][i]);
3263 if ((i + 1) % 4 == 0)
3264 cpu_fprintf(f, "\n");
3265 }
3266 }
3267 cpu_fprintf(f, "\n\n");
3268
3269}
3270
aaed909a 3271CPUCRISState *cpu_cris_init (const char *cpu_model)
8170028d
TS		 3272{
3273 CPUCRISState *env;
a7cfbba0 3274 static int tcg_initialized = 0;
a825e703 3275 int i;
8170028d
TS		 3276
3277 env = qemu_mallocz(sizeof(CPUCRISState));
3278 if (!env)
3279 return NULL;
a7cfbba0 3280
8170028d 3281 cpu_exec_init(env);
a7cfbba0
EI		 3282 cpu_reset(env);
3283
3284 if (tcg_initialized)
3285 return env;
3286
3287 tcg_initialized = 1;
05ba7d5f 3288
05ba7d5f
EI		 3289 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3290#if TARGET_LONG_BITS > HOST_LONG_BITS
3291 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3292 TCG_AREG0, offsetof(CPUState, t0), "T0");
3293 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3294 TCG_AREG0, offsetof(CPUState, t1), "T1");
3295#else
3296 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3297 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3298#endif
3299
30abcfc7
EI		 3300 cc_x = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3301 offsetof(CPUState, cc_x), "cc_x");
3302 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
a825e703 3303 offsetof(CPUState, cc_src), "cc_src");
30abcfc7
EI		 3304 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3305 offsetof(CPUState, cc_dest),
a825e703 3306 "cc_dest");
30abcfc7
EI		 3307 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3308 offsetof(CPUState, cc_result),
a825e703 3309 "cc_result");
30abcfc7 3310 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
a825e703 3311 offsetof(CPUState, cc_op), "cc_op");
30abcfc7
EI		 3312 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3313 offsetof(CPUState, cc_size),
a825e703 3314 "cc_size");
30abcfc7 3315 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
a825e703
EI		 3316 offsetof(CPUState, cc_mask),
3317 "cc_mask");
3318
b41f7df0 3319 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
30abcfc7
EI		 3320 offsetof(CPUState, pc),
3321 "pc");
3322 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3323 offsetof(CPUState, btarget),
3324 "btarget");
2a44f7f1
EI		 3325 env_btaken = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3326 offsetof(CPUState, btaken),
3327 "btaken");
a825e703 3328 for (i = 0; i < 16; i++) {
30abcfc7
EI		 3329 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3330 offsetof(CPUState, regs[i]),
a825e703
EI		 3331 regnames[i]);
3332 }
3333 for (i = 0; i < 16; i++) {
30abcfc7
EI		 3334 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3335 offsetof(CPUState, pregs[i]),
a825e703
EI		 3336 pregnames[i]);
3337 }
3338
dceaf394 3339 TCG_HELPER(helper_raise_exception);
b41f7df0
EI		 3340 TCG_HELPER(helper_store);
3341 TCG_HELPER(helper_dump);
3342 TCG_HELPER(helper_dummy);
3343
cf1d97f0 3344 TCG_HELPER(helper_tlb_flush_pid);
dceaf394
EI		 3345 TCG_HELPER(helper_movl_sreg_reg);
3346 TCG_HELPER(helper_movl_reg_sreg);
3347 TCG_HELPER(helper_rfe);
a7cfbba0 3348 TCG_HELPER(helper_rfn);
dceaf394 3349
b41f7df0
EI		 3350 TCG_HELPER(helper_evaluate_flags_muls);
3351 TCG_HELPER(helper_evaluate_flags_mulu);
3352 TCG_HELPER(helper_evaluate_flags_mcp);
3353 TCG_HELPER(helper_evaluate_flags_alu_4);
3354 TCG_HELPER(helper_evaluate_flags_move_4);
3355 TCG_HELPER(helper_evaluate_flags_move_2);
3356 TCG_HELPER(helper_evaluate_flags);
30abcfc7 3357 TCG_HELPER(helper_top_evaluate_flags);
8170028d
TS		 3358 return env;
3359}
3360
3361void cpu_reset (CPUCRISState *env)
3362{
3363 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3364 tlb_flush(env, 1);
b41f7df0
EI		 3365
3366#if defined(CONFIG_USER_ONLY)
3367 /* start in user mode with interrupts enabled. */
3368 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3369#else
3370 env->pregs[PR_CCS] = 0;
3371#endif
8170028d 3372}
d2856f1a
AJ		 3373
3374void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3375 unsigned long searched_pc, int pc_pos, void *puc)
3376{
17ac9754 3377 env->pc = gen_opc_pc[pc_pos];
d2856f1a 3378}
Qemu copy for testing