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kvm: add support for -machine kernel_irqchip=split
[mirror_qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15#include <sys/types.h>
16#include <sys/ioctl.h>
17#include <sys/mman.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
9c17d615 24#include "sysemu/sysemu.h"
6410848b 25#include "sysemu/kvm_int.h"
1d31f66b 26#include "kvm_i386.h"
05330448 27#include "cpu.h"
50efe82c
AS		 28#include "hyperv.h"
29
022c62cb 30#include "exec/gdbstub.h"
1de7afc9
PB		 31#include "qemu/host-utils.h"
32#include "qemu/config-file.h"
1c4a55db 33#include "qemu/error-report.h"
0d09e41a
PB		 34#include "hw/i386/pc.h"
35#include "hw/i386/apic.h"
e0723c45
PB		 36#include "hw/i386/apic_internal.h"
37#include "hw/i386/apic-msidef.h"
50efe82c 38
022c62cb 39#include "exec/ioport.h"
73aa529a 40#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 41#include "hw/pci/pci.h"
68bfd0ad 42#include "migration/migration.h"
4c663752 43#include "exec/memattrs.h"
05330448
AL		 44
45//#define DEBUG_KVM
46
47#ifdef DEBUG_KVM
8c0d577e 48#define DPRINTF(fmt, ...) \
05330448
AL		 49 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
50#else
8c0d577e 51#define DPRINTF(fmt, ...) \
05330448
AL		 52 do { } while (0)
53#endif
54
1a03675d
GC		 55#define MSR_KVM_WALL_CLOCK 0x11
56#define MSR_KVM_SYSTEM_TIME 0x12
57
c0532a76
MT		 58#ifndef BUS_MCEERR_AR
59#define BUS_MCEERR_AR 4
60#endif
61#ifndef BUS_MCEERR_AO
62#define BUS_MCEERR_AO 5
63#endif
64
94a8d39a
JK		 65const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
66 KVM_CAP_INFO(SET_TSS_ADDR),
67 KVM_CAP_INFO(EXT_CPUID),
68 KVM_CAP_INFO(MP_STATE),
69 KVM_CAP_LAST_INFO
70};
25d2e361 71
c3a3a7d3
JK		 72static bool has_msr_star;
73static bool has_msr_hsave_pa;
c9b8f6b6 74static bool has_msr_tsc_aux;
f28558d3 75static bool has_msr_tsc_adjust;
aa82ba54 76static bool has_msr_tsc_deadline;
df67696e 77static bool has_msr_feature_control;
c5999bfc 78static bool has_msr_async_pf_en;
bc9a839d 79static bool has_msr_pv_eoi_en;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
917367aa 83static bool has_msr_kvm_steal_time;
25d2e361 84static int lm_capable_kernel;
7bc3d711
PB		 85static bool has_msr_hv_hypercall;
86static bool has_msr_hv_vapic;
48a5f3bc 87static bool has_msr_hv_tsc;
f2a53c9e 88static bool has_msr_hv_crash;
744b8a94 89static bool has_msr_hv_reset;
8c145d7c 90static bool has_msr_hv_vpindex;
46eb8f98 91static bool has_msr_hv_runtime;
866eea9a 92static bool has_msr_hv_synic;
ff99aa64 93static bool has_msr_hv_stimer;
d1ae67f6 94static bool has_msr_mtrr;
18cd2c17 95static bool has_msr_xss;
b827df58 96
0d894367
PB		 97static bool has_msr_architectural_pmu;
98static uint32_t num_architectural_pmu_counters;
99
28143b40
TH		 100static int has_xsave;
101static int has_xcrs;
102static int has_pit_state2;
103
104int kvm_has_pit_state2(void)
105{
106 return has_pit_state2;
107}
108
355023f2
PB		 109bool kvm_has_smm(void)
110{
111 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
112}
113
1d31f66b
PM		 114bool kvm_allows_irq0_override(void)
115{
116 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
117}
118
0fd7e098
LL		 119static int kvm_get_tsc(CPUState *cs)
120{
121 X86CPU *cpu = X86_CPU(cs);
122 CPUX86State *env = &cpu->env;
123 struct {
124 struct kvm_msrs info;
125 struct kvm_msr_entry entries[1];
126 } msr_data;
127 int ret;
128
129 if (env->tsc_valid) {
130 return 0;
131 }
132
133 msr_data.info.nmsrs = 1;
134 msr_data.entries[0].index = MSR_IA32_TSC;
135 env->tsc_valid = !runstate_is_running();
136
137 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
138 if (ret < 0) {
139 return ret;
140 }
141
142 env->tsc = msr_data.entries[0].data;
143 return 0;
144}
145
146static inline void do_kvm_synchronize_tsc(void *arg)
147{
148 CPUState *cpu = arg;
149
150 kvm_get_tsc(cpu);
151}
152
153void kvm_synchronize_all_tsc(void)
154{
155 CPUState *cpu;
156
157 if (kvm_enabled()) {
158 CPU_FOREACH(cpu) {
159 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
160 }
161 }
162}
163
b827df58
AK		 164static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
165{
166 struct kvm_cpuid2 *cpuid;
167 int r, size;
168
169 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 170 cpuid = g_malloc0(size);
b827df58
AK		 171 cpuid->nent = max;
172 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 173 if (r == 0 && cpuid->nent >= max) {
174 r = -E2BIG;
175 }
b827df58
AK		 176 if (r < 0) {
177 if (r == -E2BIG) {
7267c094 178 g_free(cpuid);
b827df58
AK		 179 return NULL;
180 } else {
181 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
182 strerror(-r));
183 exit(1);
184 }
185 }
186 return cpuid;
187}
188
dd87f8a6
EH		 189/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
190 * for all entries.
191 */
192static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
193{
194 struct kvm_cpuid2 *cpuid;
195 int max = 1;
196 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
197 max *= 2;
198 }
199 return cpuid;
200}
201
a443bc34 202static const struct kvm_para_features {
0c31b744
GC		 203 int cap;
204 int feature;
205} para_features[] = {
206 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
207 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
208 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 209 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 210};
211
ba9bc59e 212static int get_para_features(KVMState *s)
0c31b744
GC		 213{
214 int i, features = 0;
215
8e03c100 216 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 217 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 218 features |= (1 << para_features[i].feature);
219 }
220 }
221
222 return features;
223}
0c31b744
GC		 224
225
829ae2f9
EH		 226/* Returns the value for a specific register on the cpuid entry
227 */
228static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
229{
230 uint32_t ret = 0;
231 switch (reg) {
232 case R_EAX:
233 ret = entry->eax;
234 break;
235 case R_EBX:
236 ret = entry->ebx;
237 break;
238 case R_ECX:
239 ret = entry->ecx;
240 break;
241 case R_EDX:
242 ret = entry->edx;
243 break;
244 }
245 return ret;
246}
247
4fb73f1d
EH		 248/* Find matching entry for function/index on kvm_cpuid2 struct
249 */
250static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
251 uint32_t function,
252 uint32_t index)
253{
254 int i;
255 for (i = 0; i < cpuid->nent; ++i) {
256 if (cpuid->entries[i].function == function &&
257 cpuid->entries[i].index == index) {
258 return &cpuid->entries[i];
259 }
260 }
261 /* not found: */
262 return NULL;
263}
264
ba9bc59e 265uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 266 uint32_t index, int reg)
b827df58
AK		 267{
268 struct kvm_cpuid2 *cpuid;
b827df58
AK		 269 uint32_t ret = 0;
270 uint32_t cpuid_1_edx;
8c723b79 271 bool found = false;
b827df58 272
dd87f8a6 273 cpuid = get_supported_cpuid(s);
b827df58 274
4fb73f1d
EH		 275 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
276 if (entry) {
277 found = true;
278 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 279 }
280
7b46e5ce
EH		 281 /* Fixups for the data returned by KVM, below */
282
c2acb022
EH		 283 if (function == 1 && reg == R_EDX) {
284 /* KVM before 2.6.30 misreports the following features */
285 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 286 } else if (function == 1 && reg == R_ECX) {
287 /* We can set the hypervisor flag, even if KVM does not return it on
288 * GET_SUPPORTED_CPUID
289 */
290 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 291 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
292 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
293 * and the irqchip is in the kernel.
294 */
295 if (kvm_irqchip_in_kernel() &&
296 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
297 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
298 }
41e5e76d
EH		 299
300 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
301 * without the in-kernel irqchip
302 */
303 if (!kvm_irqchip_in_kernel()) {
304 ret &= ~CPUID_EXT_X2APIC;
b827df58 305 }
28b8e4d0
JK		 306 } else if (function == 6 && reg == R_EAX) {
307 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 308 } else if (function == 0x80000001 && reg == R_EDX) {
309 /* On Intel, kvm returns cpuid according to the Intel spec,
310 * so add missing bits according to the AMD spec:
311 */
312 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
313 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 314 }
315
7267c094 316 g_free(cpuid);
b827df58 317
0c31b744 318 /* fallback for older kernels */
8c723b79 319 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 320 ret = get_para_features(s);
b9bec74b 321 }
0c31b744
GC		 322
323 return ret;
bb0300dc 324}
bb0300dc 325
3c85e74f
HY		 326typedef struct HWPoisonPage {
327 ram_addr_t ram_addr;
328 QLIST_ENTRY(HWPoisonPage) list;
329} HWPoisonPage;
330
331static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
332 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
333
334static void kvm_unpoison_all(void *param)
335{
336 HWPoisonPage *page, *next_page;
337
338 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
339 QLIST_REMOVE(page, list);
340 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 341 g_free(page);
3c85e74f
HY		 342 }
343}
344
3c85e74f
HY		 345static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
346{
347 HWPoisonPage *page;
348
349 QLIST_FOREACH(page, &hwpoison_page_list, list) {
350 if (page->ram_addr == ram_addr) {
351 return;
352 }
353 }
ab3ad07f 354 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 355 page->ram_addr = ram_addr;
356 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
357}
358
e7701825
MT		 359static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
360 int *max_banks)
361{
362 int r;
363
14a09518 364 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 365 if (r > 0) {
366 *max_banks = r;
367 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
368 }
369 return -ENOSYS;
370}
371
bee615d4 372static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 373{
bee615d4 374 CPUX86State *env = &cpu->env;
c34d440a
JK		 375 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
376 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
377 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 378
c34d440a
JK		 379 if (code == BUS_MCEERR_AR) {
380 status |= MCI_STATUS_AR | 0x134;
381 mcg_status |= MCG_STATUS_EIPV;
382 } else {
383 status |= 0xc0;
384 mcg_status |= MCG_STATUS_RIPV;
419fb20a 385 }
8c5cf3b6 386 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 387 (MCM_ADDR_PHYS << 6) | 0xc,
388 cpu_x86_support_mca_broadcast(env) ?
389 MCE_INJECT_BROADCAST : 0);
419fb20a 390}
419fb20a
JK		 391
392static void hardware_memory_error(void)
393{
394 fprintf(stderr, "Hardware memory error!\n");
395 exit(1);
396}
397
20d695a9 398int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 399{
20d695a9
AF		 400 X86CPU *cpu = X86_CPU(c);
401 CPUX86State *env = &cpu->env;
419fb20a 402 ram_addr_t ram_addr;
a8170e5e 403 hwaddr paddr;
419fb20a
JK		 404
405 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 406 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
1b5ec234 407 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
a60f24b5 408 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 409 fprintf(stderr, "Hardware memory error for memory used by "
410 "QEMU itself instead of guest system!\n");
411 /* Hope we are lucky for AO MCE */
412 if (code == BUS_MCEERR_AO) {
413 return 0;
414 } else {
415 hardware_memory_error();
416 }
417 }
3c85e74f 418 kvm_hwpoison_page_add(ram_addr);
bee615d4 419 kvm_mce_inject(cpu, paddr, code);
e56ff191 420 } else {
419fb20a
JK		 421 if (code == BUS_MCEERR_AO) {
422 return 0;
423 } else if (code == BUS_MCEERR_AR) {
424 hardware_memory_error();
425 } else {
426 return 1;
427 }
428 }
429 return 0;
430}
431
432int kvm_arch_on_sigbus(int code, void *addr)
433{
182735ef
AF		 434 X86CPU *cpu = X86_CPU(first_cpu);
435
436 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 437 ram_addr_t ram_addr;
a8170e5e 438 hwaddr paddr;
419fb20a
JK		 439
440 /* Hope we are lucky for AO MCE */
1b5ec234 441 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
182735ef 442 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 443 addr, &paddr)) {
419fb20a
JK		 444 fprintf(stderr, "Hardware memory error for memory used by "
445 "QEMU itself instead of guest system!: %p\n", addr);
446 return 0;
447 }
3c85e74f 448 kvm_hwpoison_page_add(ram_addr);
182735ef 449 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 450 } else {
419fb20a
JK		 451 if (code == BUS_MCEERR_AO) {
452 return 0;
453 } else if (code == BUS_MCEERR_AR) {
454 hardware_memory_error();
455 } else {
456 return 1;
457 }
458 }
459 return 0;
460}
e7701825 461
1bc22652 462static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 463{
1bc22652
AF		 464 CPUX86State *env = &cpu->env;
465
ab443475
JK		 466 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
467 unsigned int bank, bank_num = env->mcg_cap & 0xff;
468 struct kvm_x86_mce mce;
469
470 env->exception_injected = -1;
471
472 /*
473 * There must be at least one bank in use if an MCE is pending.
474 * Find it and use its values for the event injection.
475 */
476 for (bank = 0; bank < bank_num; bank++) {
477 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
478 break;
479 }
480 }
481 assert(bank < bank_num);
482
483 mce.bank = bank;
484 mce.status = env->mce_banks[bank * 4 + 1];
485 mce.mcg_status = env->mcg_status;
486 mce.addr = env->mce_banks[bank * 4 + 2];
487 mce.misc = env->mce_banks[bank * 4 + 3];
488
1bc22652 489 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 490 }
ab443475
JK		 491 return 0;
492}
493
1dfb4dd9 494static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 495{
317ac620 496 CPUX86State *env = opaque;
b8cc45d6
GC		 497
498 if (running) {
499 env->tsc_valid = false;
500 }
501}
502
83b17af5 503unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 504{
83b17af5 505 X86CPU *cpu = X86_CPU(cs);
7e72a45c 506 return cpu->apic_id;
b164e48e
EH		 507}
508
92067bf4
IM		 509#ifndef KVM_CPUID_SIGNATURE_NEXT
510#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
511#endif
512
513static bool hyperv_hypercall_available(X86CPU *cpu)
514{
515 return cpu->hyperv_vapic ||
516 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
517}
518
519static bool hyperv_enabled(X86CPU *cpu)
520{
7bc3d711
PB		 521 CPUState *cs = CPU(cpu);
522 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
523 (hyperv_hypercall_available(cpu) ||
48a5f3bc 524 cpu->hyperv_time ||
f2a53c9e 525 cpu->hyperv_relaxed_timing ||
744b8a94 526 cpu->hyperv_crash ||
8c145d7c 527 cpu->hyperv_reset ||
46eb8f98 528 cpu->hyperv_vpindex ||
866eea9a 529 cpu->hyperv_runtime ||
ff99aa64
AS		 530 cpu->hyperv_synic ||
531 cpu->hyperv_stimer);
92067bf4
IM		 532}
533
68bfd0ad
MT		 534static Error *invtsc_mig_blocker;
535
f8bb0565 536#define KVM_MAX_CPUID_ENTRIES 100
0893d460 537
20d695a9 538int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 539{
540 struct {
486bd5a2 541 struct kvm_cpuid2 cpuid;
f8bb0565 542 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 543 } QEMU_PACKED cpuid_data;
20d695a9
AF		 544 X86CPU *cpu = X86_CPU(cs);
545 CPUX86State *env = &cpu->env;
486bd5a2 546 uint32_t limit, i, j, cpuid_i;
a33609ca 547 uint32_t unused;
bb0300dc 548 struct kvm_cpuid_entry2 *c;
bb0300dc 549 uint32_t signature[3];
234cc647 550 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 551 int r;
05330448 552
ef4cbe14
SW		 553 memset(&cpuid_data, 0, sizeof(cpuid_data));
554
05330448
AL		 555 cpuid_i = 0;
556
bb0300dc 557 /* Paravirtualization CPUIDs */
234cc647
PB		 558 if (hyperv_enabled(cpu)) {
559 c = &cpuid_data.entries[cpuid_i++];
560 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 561 if (!cpu->hyperv_vendor_id) {
562 memcpy(signature, "Microsoft Hv", 12);
563 } else {
564 size_t len = strlen(cpu->hyperv_vendor_id);
565
566 if (len > 12) {
567 error_report("hv-vendor-id truncated to 12 characters");
568 len = 12;
569 }
570 memset(signature, 0, 12);
571 memcpy(signature, cpu->hyperv_vendor_id, len);
572 }
eab70139 573 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 574 c->ebx = signature[0];
575 c->ecx = signature[1];
576 c->edx = signature[2];
0c31b744 577
234cc647
PB		 578 c = &cpuid_data.entries[cpuid_i++];
579 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 580 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
581 c->eax = signature[0];
234cc647
PB		 582 c->ebx = 0;
583 c->ecx = 0;
584 c->edx = 0;
eab70139
VR		 585
586 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 587 c->function = HYPERV_CPUID_VERSION;
588 c->eax = 0x00001bbc;
589 c->ebx = 0x00060001;
590
591 c = &cpuid_data.entries[cpuid_i++];
eab70139 592 c->function = HYPERV_CPUID_FEATURES;
92067bf4 593 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 594 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
595 }
92067bf4 596 if (cpu->hyperv_vapic) {
eab70139
VR		 597 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
598 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
7bc3d711 599 has_msr_hv_vapic = true;
eab70139 600 }
48a5f3bc
VR		 601 if (cpu->hyperv_time &&
602 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
603 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
604 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
605 c->eax |= 0x200;
606 has_msr_hv_tsc = true;
607 }
f2a53c9e
AS		 608 if (cpu->hyperv_crash && has_msr_hv_crash) {
609 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
610 }
744b8a94
AS		 611 if (cpu->hyperv_reset && has_msr_hv_reset) {
612 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
613 }
8c145d7c
AS		 614 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
615 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
616 }
46eb8f98
AS		 617 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
618 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
619 }
866eea9a
AS		 620 if (cpu->hyperv_synic) {
621 int sint;
622
623 if (!has_msr_hv_synic ||
624 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
625 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
626 return -ENOSYS;
627 }
628
629 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
630 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
631 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
632 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
633 }
634 }
ff99aa64
AS		 635 if (cpu->hyperv_stimer) {
636 if (!has_msr_hv_stimer) {
637 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
638 return -ENOSYS;
639 }
640 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
641 }
eab70139 642 c = &cpuid_data.entries[cpuid_i++];
eab70139 643 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 644 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 645 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
646 }
7bc3d711 647 if (has_msr_hv_vapic) {
eab70139
VR		 648 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
649 }
92067bf4 650 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 651
652 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 653 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
654 c->eax = 0x40;
655 c->ebx = 0x40;
656
234cc647 657 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 658 has_msr_hv_hypercall = true;
eab70139
VR		 659 }
660
f522d2ac
AW		 661 if (cpu->expose_kvm) {
662 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
663 c = &cpuid_data.entries[cpuid_i++];
664 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 665 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 666 c->ebx = signature[0];
667 c->ecx = signature[1];
668 c->edx = signature[2];
234cc647 669
f522d2ac
AW		 670 c = &cpuid_data.entries[cpuid_i++];
671 c->function = KVM_CPUID_FEATURES | kvm_base;
672 c->eax = env->features[FEAT_KVM];
234cc647 673
f522d2ac 674 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 675
f522d2ac 676 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 677
f522d2ac
AW		 678 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
679 }
917367aa 680
a33609ca 681 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 682
683 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 684 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
685 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
686 abort();
687 }
bb0300dc 688 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 689
690 switch (i) {
a36b1029
AL		 691 case 2: {
692 /* Keep reading function 2 till all the input is received */
693 int times;
694
a36b1029 695 c->function = i;
a33609ca
AL		 696 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
697 KVM_CPUID_FLAG_STATE_READ_NEXT;
698 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
699 times = c->eax & 0xff;
a36b1029
AL		 700
701 for (j = 1; j < times; ++j) {
f8bb0565
IM		 702 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
703 fprintf(stderr, "cpuid_data is full, no space for "
704 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
705 abort();
706 }
a33609ca 707 c = &cpuid_data.entries[cpuid_i++];
a36b1029 708 c->function = i;
a33609ca
AL		 709 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
710 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 711 }
712 break;
713 }
486bd5a2
AL		 714 case 4:
715 case 0xb:
716 case 0xd:
717 for (j = 0; ; j++) {
31e8c696
AP		 718 if (i == 0xd && j == 64) {
719 break;
720 }
486bd5a2
AL		 721 c->function = i;
722 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
723 c->index = j;
a33609ca 724 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 725
b9bec74b 726 if (i == 4 && c->eax == 0) {
486bd5a2 727 break;
b9bec74b
JK		 728 }
729 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 730 break;
b9bec74b
JK		 731 }
732 if (i == 0xd && c->eax == 0) {
31e8c696 733 continue;
b9bec74b 734 }
f8bb0565
IM		 735 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
736 fprintf(stderr, "cpuid_data is full, no space for "
737 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
738 abort();
739 }
a33609ca 740 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 741 }
742 break;
743 default:
486bd5a2 744 c->function = i;
a33609ca
AL		 745 c->flags = 0;
746 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 747 break;
748 }
05330448 749 }
0d894367
PB		 750
751 if (limit >= 0x0a) {
752 uint32_t ver;
753
754 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
755 if ((ver & 0xff) > 0) {
756 has_msr_architectural_pmu = true;
757 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
758
759 /* Shouldn't be more than 32, since that's the number of bits
760 * available in EBX to tell us _which_ counters are available.
761 * Play it safe.
762 */
763 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
764 num_architectural_pmu_counters = MAX_GP_COUNTERS;
765 }
766 }
767 }
768
a33609ca 769 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 770
771 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 772 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
773 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
774 abort();
775 }
bb0300dc 776 c = &cpuid_data.entries[cpuid_i++];
05330448 777
05330448 778 c->function = i;
a33609ca
AL		 779 c->flags = 0;
780 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 781 }
782
b3baa152
BW		 783 /* Call Centaur's CPUID instructions they are supported. */
784 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 785 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
786
787 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 788 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
789 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
790 abort();
791 }
b3baa152
BW		 792 c = &cpuid_data.entries[cpuid_i++];
793
794 c->function = i;
795 c->flags = 0;
796 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
797 }
798 }
799
05330448
AL		 800 cpuid_data.cpuid.nent = cpuid_i;
801
e7701825 802 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 803 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 804 (CPUID_MCE | CPUID_MCA)
a60f24b5 805 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 806 uint64_t mcg_cap, unsupported_caps;
e7701825 807 int banks;
32a42024 808 int ret;
e7701825 809
a60f24b5 810 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 811 if (ret < 0) {
812 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
813 return ret;
e7701825 814 }
75d49497 815
2590f15b 816 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 817 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 818 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 819 return -ENOTSUP;
75d49497 820 }
49b69cbf 821
5120901a
EH		 822 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
823 if (unsupported_caps) {
824 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
825 unsupported_caps);
826 }
827
2590f15b
EH		 828 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
829 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 830 if (ret < 0) {
831 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
832 return ret;
833 }
e7701825 834 }
e7701825 835
b8cc45d6
GC		 836 qemu_add_vm_change_state_handler(cpu_update_state, env);
837
df67696e
LJ		 838 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
839 if (c) {
840 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
841 !!(c->ecx & CPUID_EXT_SMX);
842 }
843
68bfd0ad
MT		 844 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
845 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
846 /* for migration */
847 error_setg(&invtsc_mig_blocker,
848 "State blocked by non-migratable CPU device"
849 " (invtsc flag)");
850 migrate_add_blocker(invtsc_mig_blocker);
851 /* for savevm */
852 vmstate_x86_cpu.unmigratable = 1;
853 }
854
7e680753 855 cpuid_data.cpuid.padding = 0;
1bc22652 856 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 857 if (r) {
858 return r;
859 }
e7429073 860
a60f24b5 861 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
e7429073 862 if (r && env->tsc_khz) {
1bc22652 863 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
e7429073
JR		 864 if (r < 0) {
865 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
866 return r;
867 }
868 }
e7429073 869
28143b40 870 if (has_xsave) {
fabacc0f
JK		 871 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
872 }
873
d1ae67f6
AW		 874 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
875 has_msr_mtrr = true;
876 }
877
e7429073 878 return 0;
05330448
AL		 879}
880
50a2c6e5 881void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 882{
20d695a9 883 CPUX86State *env = &cpu->env;
dd673288 884
e73223a5 885 env->exception_injected = -1;
0e607a80 886 env->interrupt_injected = -1;
1a5e9d2f 887 env->xcr0 = 1;
ddced198 888 if (kvm_irqchip_in_kernel()) {
dd673288 889 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 890 KVM_MP_STATE_UNINITIALIZED;
891 } else {
892 env->mp_state = KVM_MP_STATE_RUNNABLE;
893 }
caa5af0f
JK		 894}
895
e0723c45
PB		 896void kvm_arch_do_init_vcpu(X86CPU *cpu)
897{
898 CPUX86State *env = &cpu->env;
899
900 /* APs get directly into wait-for-SIPI state. */
901 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
902 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
903 }
904}
905
c3a3a7d3 906static int kvm_get_supported_msrs(KVMState *s)
05330448 907{
75b10c43 908 static int kvm_supported_msrs;
c3a3a7d3 909 int ret = 0;
05330448
AL		 910
911 /* first time */
75b10c43 912 if (kvm_supported_msrs == 0) {
05330448
AL		 913 struct kvm_msr_list msr_list, *kvm_msr_list;
914
75b10c43 915 kvm_supported_msrs = -1;
05330448
AL		 916
917 /* Obtain MSR list from KVM. These are the MSRs that we must
918 * save/restore */
4c9f7372 919 msr_list.nmsrs = 0;
c3a3a7d3 920 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 921 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 922 return ret;
6fb6d245 923 }
d9db889f
JK		 924 /* Old kernel modules had a bug and could write beyond the provided
925 memory. Allocate at least a safe amount of 1K. */
7267c094 926 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 927 msr_list.nmsrs *
928 sizeof(msr_list.indices[0])));
05330448 929
55308450 930 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 931 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 932 if (ret >= 0) {
933 int i;
934
935 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
936 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 937 has_msr_star = true;
75b10c43
MT		 938 continue;
939 }
940 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 941 has_msr_hsave_pa = true;
75b10c43 942 continue;
05330448 943 }
c9b8f6b6
AS		 944 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
945 has_msr_tsc_aux = true;
946 continue;
947 }
f28558d3
WA		 948 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
949 has_msr_tsc_adjust = true;
950 continue;
951 }
aa82ba54
LJ		 952 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
953 has_msr_tsc_deadline = true;
954 continue;
955 }
fc12d72e
PB		 956 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
957 has_msr_smbase = true;
958 continue;
959 }
21e87c46
AK		 960 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
961 has_msr_misc_enable = true;
962 continue;
963 }
79e9ebeb
LJ		 964 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
965 has_msr_bndcfgs = true;
966 continue;
967 }
18cd2c17
WL		 968 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
969 has_msr_xss = true;
970 continue;
971 }
f2a53c9e
AS		 972 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
973 has_msr_hv_crash = true;
974 continue;
975 }
744b8a94
AS		 976 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
977 has_msr_hv_reset = true;
978 continue;
979 }
8c145d7c
AS		 980 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
981 has_msr_hv_vpindex = true;
982 continue;
983 }
46eb8f98
AS		 984 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
985 has_msr_hv_runtime = true;
986 continue;
987 }
866eea9a
AS		 988 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
989 has_msr_hv_synic = true;
990 continue;
991 }
ff99aa64
AS		 992 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
993 has_msr_hv_stimer = true;
994 continue;
995 }
05330448
AL		 996 }
997 }
998
7267c094 999 g_free(kvm_msr_list);
05330448
AL		 1000 }
1001
c3a3a7d3 1002 return ret;
05330448
AL		 1003}
1004
6410848b
PB		 1005static Notifier smram_machine_done;
1006static KVMMemoryListener smram_listener;
1007static AddressSpace smram_address_space;
1008static MemoryRegion smram_as_root;
1009static MemoryRegion smram_as_mem;
1010
1011static void register_smram_listener(Notifier *n, void *unused)
1012{
1013 MemoryRegion *smram =
1014 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1015
1016 /* Outer container... */
1017 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1018 memory_region_set_enabled(&smram_as_root, true);
1019
1020 /* ... with two regions inside: normal system memory with low
1021 * priority, and...
1022 */
1023 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1024 get_system_memory(), 0, ~0ull);
1025 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1026 memory_region_set_enabled(&smram_as_mem, true);
1027
1028 if (smram) {
1029 /* ... SMRAM with higher priority */
1030 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1031 memory_region_set_enabled(smram, true);
1032 }
1033
1034 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1035 kvm_memory_listener_register(kvm_state, &smram_listener,
1036 &smram_address_space, 1);
1037}
1038
b16565b3 1039int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1040{
11076198 1041 uint64_t identity_base = 0xfffbc000;
39d6960a 1042 uint64_t shadow_mem;
20420430 1043 int ret;
25d2e361 1044 struct utsname utsname;
20420430 1045
28143b40
TH		 1046#ifdef KVM_CAP_XSAVE
1047 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1048#endif
1049
1050#ifdef KVM_CAP_XCRS
1051 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1052#endif
1053
1054#ifdef KVM_CAP_PIT_STATE2
1055 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1056#endif
1057
c3a3a7d3 1058 ret = kvm_get_supported_msrs(s);
20420430 1059 if (ret < 0) {
20420430
SY		 1060 return ret;
1061 }
25d2e361
MT		 1062
1063 uname(&utsname);
1064 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1065
4c5b10b7 1066 /*
11076198
JK		 1067 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1068 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1069 * Since these must be part of guest physical memory, we need to allocate
1070 * them, both by setting their start addresses in the kernel and by
1071 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1072 *
1073 * Older KVM versions may not support setting the identity map base. In
1074 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1075 * size.
4c5b10b7 1076 */
11076198
JK		 1077 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1078 /* Allows up to 16M BIOSes. */
1079 identity_base = 0xfeffc000;
1080
1081 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1082 if (ret < 0) {
1083 return ret;
1084 }
4c5b10b7 1085 }
e56ff191 1086
11076198
JK		 1087 /* Set TSS base one page after EPT identity map. */
1088 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1089 if (ret < 0) {
1090 return ret;
1091 }
1092
11076198
JK		 1093 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1094 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1095 if (ret < 0) {
11076198 1096 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1097 return ret;
1098 }
3c85e74f 1099 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1100
4689b77b 1101 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1102 if (shadow_mem != -1) {
1103 shadow_mem /= 4096;
1104 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1105 if (ret < 0) {
1106 return ret;
39d6960a
JK		 1107 }
1108 }
6410848b
PB		 1109
1110 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1111 smram_machine_done.notify = register_smram_listener;
1112 qemu_add_machine_init_done_notifier(&smram_machine_done);
1113 }
11076198 1114 return 0;
05330448 1115}
b9bec74b 1116
05330448
AL		 1117static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1118{
1119 lhs->selector = rhs->selector;
1120 lhs->base = rhs->base;
1121 lhs->limit = rhs->limit;
1122 lhs->type = 3;
1123 lhs->present = 1;
1124 lhs->dpl = 3;
1125 lhs->db = 0;
1126 lhs->s = 1;
1127 lhs->l = 0;
1128 lhs->g = 0;
1129 lhs->avl = 0;
1130 lhs->unusable = 0;
1131}
1132
1133static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1134{
1135 unsigned flags = rhs->flags;
1136 lhs->selector = rhs->selector;
1137 lhs->base = rhs->base;
1138 lhs->limit = rhs->limit;
1139 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1140 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1141 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1142 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1143 lhs->s = (flags & DESC_S_MASK) != 0;
1144 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1145 lhs->g = (flags & DESC_G_MASK) != 0;
1146 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1147 lhs->unusable = 0;
7e680753 1148 lhs->padding = 0;
05330448
AL		 1149}
1150
1151static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1152{
1153 lhs->selector = rhs->selector;
1154 lhs->base = rhs->base;
1155 lhs->limit = rhs->limit;
b9bec74b
JK		 1156 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1157 (rhs->present * DESC_P_MASK) |
1158 (rhs->dpl << DESC_DPL_SHIFT) |
1159 (rhs->db << DESC_B_SHIFT) |
1160 (rhs->s * DESC_S_MASK) |
1161 (rhs->l << DESC_L_SHIFT) |
1162 (rhs->g * DESC_G_MASK) |
1163 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1164}
1165
1166static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1167{
b9bec74b 1168 if (set) {
05330448 1169 *kvm_reg = *qemu_reg;
b9bec74b 1170 } else {
05330448 1171 *qemu_reg = *kvm_reg;
b9bec74b 1172 }
05330448
AL		 1173}
1174
1bc22652 1175static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1176{
1bc22652 1177 CPUX86State *env = &cpu->env;
05330448
AL		 1178 struct kvm_regs regs;
1179 int ret = 0;
1180
1181 if (!set) {
1bc22652 1182 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1183 if (ret < 0) {
05330448 1184 return ret;
b9bec74b 1185 }
05330448
AL		 1186 }
1187
1188 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1189 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1190 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1191 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1192 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1193 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1194 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1195 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1196#ifdef TARGET_X86_64
1197 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1198 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1199 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1200 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1201 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1202 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1203 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1204 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1205#endif
1206
1207 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1208 kvm_getput_reg(&regs.rip, &env->eip, set);
1209
b9bec74b 1210 if (set) {
1bc22652 1211 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1212 }
05330448
AL		 1213
1214 return ret;
1215}
1216
1bc22652 1217static int kvm_put_fpu(X86CPU *cpu)
05330448 1218{
1bc22652 1219 CPUX86State *env = &cpu->env;
05330448
AL		 1220 struct kvm_fpu fpu;
1221 int i;
1222
1223 memset(&fpu, 0, sizeof fpu);
1224 fpu.fsw = env->fpus & ~(7 << 11);
1225 fpu.fsw |= (env->fpstt & 7) << 11;
1226 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1227 fpu.last_opcode = env->fpop;
1228 fpu.last_ip = env->fpip;
1229 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1230 for (i = 0; i < 8; ++i) {
1231 fpu.ftwx |= (!env->fptags[i]) << i;
1232 }
05330448 1233 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887
PB		 1234 for (i = 0; i < CPU_NB_REGS; i++) {
1235 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1236 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1237 }
05330448
AL		 1238 fpu.mxcsr = env->mxcsr;
1239
1bc22652 1240 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1241}
1242
6b42494b
JK		 1243#define XSAVE_FCW_FSW 0
1244#define XSAVE_FTW_FOP 1
f1665b21
SY		 1245#define XSAVE_CWD_RIP 2
1246#define XSAVE_CWD_RDP 4
1247#define XSAVE_MXCSR 6
1248#define XSAVE_ST_SPACE 8
1249#define XSAVE_XMM_SPACE 40
1250#define XSAVE_XSTATE_BV 128
1251#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1252#define XSAVE_BNDREGS 240
1253#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1254#define XSAVE_OPMASK 272
1255#define XSAVE_ZMM_Hi256 288
1256#define XSAVE_Hi16_ZMM 416
f1665b21 1257
1bc22652 1258static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1259{
1bc22652 1260 CPUX86State *env = &cpu->env;
fabacc0f 1261 struct kvm_xsave* xsave = env->kvm_xsave_buf;
42cc8fa6 1262 uint16_t cwd, swd, twd;
b7711471 1263 uint8_t *xmm, *ymmh, *zmmh;
fabacc0f 1264 int i, r;
f1665b21 1265
28143b40 1266 if (!has_xsave) {
1bc22652 1267 return kvm_put_fpu(cpu);
b9bec74b 1268 }
f1665b21 1269
f1665b21 1270 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1271 twd = 0;
f1665b21
SY		 1272 swd = env->fpus & ~(7 << 11);
1273 swd |= (env->fpstt & 7) << 11;
1274 cwd = env->fpuc;
b9bec74b 1275 for (i = 0; i < 8; ++i) {
f1665b21 1276 twd |= (!env->fptags[i]) << i;
b9bec74b 1277 }
6b42494b
JK		 1278 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1279 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
42cc8fa6
JK		 1280 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1281 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
f1665b21
SY		 1282 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1283 sizeof env->fpregs);
f1665b21
SY		 1284 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1285 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
79e9ebeb
LJ		 1286 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1287 sizeof env->bnd_regs);
1288 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1289 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1290 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1291 sizeof env->opmask_regs);
bee81887
PB		 1292
1293 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1294 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1295 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1296 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1297 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1298 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
b7711471
PB		 1299 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1300 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1301 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1302 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1303 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1304 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
bee81887
PB		 1305 }
1306
9aecd6f8 1307#ifdef TARGET_X86_64
b7711471
PB		 1308 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1309 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1310#endif
1bc22652 1311 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
0f53994f 1312 return r;
f1665b21
SY		 1313}
1314
1bc22652 1315static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1316{
1bc22652 1317 CPUX86State *env = &cpu->env;
bdfc8480 1318 struct kvm_xcrs xcrs = {};
f1665b21 1319
28143b40 1320 if (!has_xcrs) {
f1665b21 1321 return 0;
b9bec74b 1322 }
f1665b21
SY		 1323
1324 xcrs.nr_xcrs = 1;
1325 xcrs.flags = 0;
1326 xcrs.xcrs[0].xcr = 0;
1327 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1328 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1329}
1330
1bc22652 1331static int kvm_put_sregs(X86CPU *cpu)
05330448 1332{
1bc22652 1333 CPUX86State *env = &cpu->env;
05330448
AL		 1334 struct kvm_sregs sregs;
1335
0e607a80
JK		 1336 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1337 if (env->interrupt_injected >= 0) {
1338 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1339 (uint64_t)1 << (env->interrupt_injected % 64);
1340 }
05330448
AL		 1341
1342 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1343 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1344 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1345 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1346 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1347 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1348 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1349 } else {
b9bec74b
JK		 1350 set_seg(&sregs.cs, &env->segs[R_CS]);
1351 set_seg(&sregs.ds, &env->segs[R_DS]);
1352 set_seg(&sregs.es, &env->segs[R_ES]);
1353 set_seg(&sregs.fs, &env->segs[R_FS]);
1354 set_seg(&sregs.gs, &env->segs[R_GS]);
1355 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1356 }
1357
1358 set_seg(&sregs.tr, &env->tr);
1359 set_seg(&sregs.ldt, &env->ldt);
1360
1361 sregs.idt.limit = env->idt.limit;
1362 sregs.idt.base = env->idt.base;
7e680753 1363 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1364 sregs.gdt.limit = env->gdt.limit;
1365 sregs.gdt.base = env->gdt.base;
7e680753 1366 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1367
1368 sregs.cr0 = env->cr[0];
1369 sregs.cr2 = env->cr[2];
1370 sregs.cr3 = env->cr[3];
1371 sregs.cr4 = env->cr[4];
1372
02e51483
CF		 1373 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1374 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1375
1376 sregs.efer = env->efer;
1377
1bc22652 1378 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1379}
1380
1381static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1382 uint32_t index, uint64_t value)
1383{
1384 entry->index = index;
c7fe4b12 1385 entry->reserved = 0;
05330448
AL		 1386 entry->data = value;
1387}
1388
7477cd38
MT		 1389static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1390{
1391 CPUX86State *env = &cpu->env;
1392 struct {
1393 struct kvm_msrs info;
1394 struct kvm_msr_entry entries[1];
1395 } msr_data;
1396 struct kvm_msr_entry *msrs = msr_data.entries;
1397
1398 if (!has_msr_tsc_deadline) {
1399 return 0;
1400 }
1401
1402 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1403
c7fe4b12
CB		 1404 msr_data.info = (struct kvm_msrs) {
1405 .nmsrs = 1,
1406 };
7477cd38
MT		 1407
1408 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1409}
1410
6bdf863d
JK		 1411/*
1412 * Provide a separate write service for the feature control MSR in order to
1413 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1414 * before writing any other state because forcibly leaving nested mode
1415 * invalidates the VCPU state.
1416 */
1417static int kvm_put_msr_feature_control(X86CPU *cpu)
1418{
1419 struct {
1420 struct kvm_msrs info;
1421 struct kvm_msr_entry entry;
1422 } msr_data;
1423
1424 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1425 cpu->env.msr_ia32_feature_control);
c7fe4b12
CB		 1426
1427 msr_data.info = (struct kvm_msrs) {
1428 .nmsrs = 1,
1429 };
1430
6bdf863d
JK		 1431 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1432}
1433
1bc22652 1434static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1435{
1bc22652 1436 CPUX86State *env = &cpu->env;
05330448
AL		 1437 struct {
1438 struct kvm_msrs info;
d1ae67f6 1439 struct kvm_msr_entry entries[150];
05330448
AL		 1440 } msr_data;
1441 struct kvm_msr_entry *msrs = msr_data.entries;
0d894367 1442 int n = 0, i;
05330448
AL		 1443
1444 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1445 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1446 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
0c03266a 1447 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
c3a3a7d3 1448 if (has_msr_star) {
b9bec74b
JK		 1449 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1450 }
c3a3a7d3 1451 if (has_msr_hsave_pa) {
75b10c43 1452 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1453 }
c9b8f6b6
AS		 1454 if (has_msr_tsc_aux) {
1455 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1456 }
f28558d3
WA		 1457 if (has_msr_tsc_adjust) {
1458 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1459 }
21e87c46
AK		 1460 if (has_msr_misc_enable) {
1461 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1462 env->msr_ia32_misc_enable);
1463 }
fc12d72e
PB		 1464 if (has_msr_smbase) {
1465 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1466 }
439d19f2
PB		 1467 if (has_msr_bndcfgs) {
1468 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1469 }
18cd2c17
WL		 1470 if (has_msr_xss) {
1471 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1472 }
05330448 1473#ifdef TARGET_X86_64
25d2e361
MT		 1474 if (lm_capable_kernel) {
1475 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1476 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1477 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1478 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1479 }
05330448 1480#endif
ff5c186b 1481 /*
0d894367
PB		 1482 * The following MSRs have side effects on the guest or are too heavy
1483 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1484 */
1485 if (level >= KVM_PUT_RESET_STATE) {
0522604b 1486 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
ea643051
JK		 1487 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1488 env->system_time_msr);
1489 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc
JK		 1490 if (has_msr_async_pf_en) {
1491 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1492 env->async_pf_en_msr);
1493 }
bc9a839d
MT		 1494 if (has_msr_pv_eoi_en) {
1495 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1496 env->pv_eoi_en_msr);
1497 }
917367aa
MT		 1498 if (has_msr_kvm_steal_time) {
1499 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1500 env->steal_time_msr);
1501 }
0d894367
PB		 1502 if (has_msr_architectural_pmu) {
1503 /* Stop the counter. */
1504 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1505 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1506
1507 /* Set the counter values. */
1508 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1509 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1510 env->msr_fixed_counters[i]);
1511 }
1512 for (i = 0; i < num_architectural_pmu_counters; i++) {
1513 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1514 env->msr_gp_counters[i]);
1515 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1516 env->msr_gp_evtsel[i]);
1517 }
1518 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1519 env->msr_global_status);
1520 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1521 env->msr_global_ovf_ctrl);
1522
1523 /* Now start the PMU. */
1524 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1525 env->msr_fixed_ctr_ctrl);
1526 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1527 env->msr_global_ctrl);
1528 }
7bc3d711 1529 if (has_msr_hv_hypercall) {
1c90ef26
VR		 1530 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1531 env->msr_hv_guest_os_id);
1532 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1533 env->msr_hv_hypercall);
eab70139 1534 }
7bc3d711 1535 if (has_msr_hv_vapic) {
5ef68987
VR		 1536 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1537 env->msr_hv_vapic);
eab70139 1538 }
48a5f3bc
VR		 1539 if (has_msr_hv_tsc) {
1540 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1541 env->msr_hv_tsc);
1542 }
f2a53c9e
AS		 1543 if (has_msr_hv_crash) {
1544 int j;
1545
1546 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1547 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1548 env->msr_hv_crash_params[j]);
1549
1550 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1551 HV_X64_MSR_CRASH_CTL_NOTIFY);
1552 }
46eb8f98
AS		 1553 if (has_msr_hv_runtime) {
1554 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1555 env->msr_hv_runtime);
1556 }
866eea9a
AS		 1557 if (cpu->hyperv_synic) {
1558 int j;
1559
1560 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1561 env->msr_hv_synic_control);
1562 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1563 env->msr_hv_synic_version);
1564 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1565 env->msr_hv_synic_evt_page);
1566 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1567 env->msr_hv_synic_msg_page);
1568
1569 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1570 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1571 env->msr_hv_synic_sint[j]);
1572 }
1573 }
ff99aa64
AS		 1574 if (has_msr_hv_stimer) {
1575 int j;
1576
1577 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1578 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2,
1579 env->msr_hv_stimer_config[j]);
1580 }
1581
1582 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1583 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2,
1584 env->msr_hv_stimer_count[j]);
1585 }
1586 }
d1ae67f6
AW		 1587 if (has_msr_mtrr) {
1588 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1589 kvm_msr_entry_set(&msrs[n++],
1590 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1591 kvm_msr_entry_set(&msrs[n++],
1592 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1593 kvm_msr_entry_set(&msrs[n++],
1594 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1595 kvm_msr_entry_set(&msrs[n++],
1596 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1597 kvm_msr_entry_set(&msrs[n++],
1598 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1599 kvm_msr_entry_set(&msrs[n++],
1600 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1601 kvm_msr_entry_set(&msrs[n++],
1602 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1603 kvm_msr_entry_set(&msrs[n++],
1604 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1605 kvm_msr_entry_set(&msrs[n++],
1606 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1607 kvm_msr_entry_set(&msrs[n++],
1608 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1609 kvm_msr_entry_set(&msrs[n++],
1610 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1611 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1612 kvm_msr_entry_set(&msrs[n++],
1613 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1614 kvm_msr_entry_set(&msrs[n++],
1615 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1616 }
1617 }
6bdf863d
JK		 1618
1619 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1620 * kvm_put_msr_feature_control. */
ea643051 1621 }
57780495 1622 if (env->mcg_cap) {
d8da8574 1623 int i;
b9bec74b 1624
c34d440a
JK		 1625 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1626 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1627 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1628 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1629 }
1630 }
1a03675d 1631
c7fe4b12
CB		 1632 msr_data.info = (struct kvm_msrs) {
1633 .nmsrs = n,
1634 };
05330448 1635
1bc22652 1636 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
05330448
AL		 1637
1638}
1639
1640
1bc22652 1641static int kvm_get_fpu(X86CPU *cpu)
05330448 1642{
1bc22652 1643 CPUX86State *env = &cpu->env;
05330448
AL		 1644 struct kvm_fpu fpu;
1645 int i, ret;
1646
1bc22652 1647 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1648 if (ret < 0) {
05330448 1649 return ret;
b9bec74b 1650 }
05330448
AL		 1651
1652 env->fpstt = (fpu.fsw >> 11) & 7;
1653 env->fpus = fpu.fsw;
1654 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1655 env->fpop = fpu.last_opcode;
1656 env->fpip = fpu.last_ip;
1657 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1658 for (i = 0; i < 8; ++i) {
1659 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1660 }
05330448 1661 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887
PB		 1662 for (i = 0; i < CPU_NB_REGS; i++) {
1663 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1664 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1665 }
05330448
AL		 1666 env->mxcsr = fpu.mxcsr;
1667
1668 return 0;
1669}
1670
1bc22652 1671static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1672{
1bc22652 1673 CPUX86State *env = &cpu->env;
fabacc0f 1674 struct kvm_xsave* xsave = env->kvm_xsave_buf;
f1665b21 1675 int ret, i;
b7711471 1676 const uint8_t *xmm, *ymmh, *zmmh;
42cc8fa6 1677 uint16_t cwd, swd, twd;
f1665b21 1678
28143b40 1679 if (!has_xsave) {
1bc22652 1680 return kvm_get_fpu(cpu);
b9bec74b 1681 }
f1665b21 1682
1bc22652 1683 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1684 if (ret < 0) {
f1665b21 1685 return ret;
0f53994f 1686 }
f1665b21 1687
6b42494b
JK		 1688 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1689 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1690 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1691 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
f1665b21
SY		 1692 env->fpstt = (swd >> 11) & 7;
1693 env->fpus = swd;
1694 env->fpuc = cwd;
b9bec74b 1695 for (i = 0; i < 8; ++i) {
f1665b21 1696 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1697 }
42cc8fa6
JK		 1698 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1699 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
f1665b21
SY		 1700 env->mxcsr = xsave->region[XSAVE_MXCSR];
1701 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1702 sizeof env->fpregs);
f1665b21 1703 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
79e9ebeb
LJ		 1704 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1705 sizeof env->bnd_regs);
1706 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1707 sizeof(env->bndcs_regs));
9aecd6f8
CP		 1708 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1709 sizeof env->opmask_regs);
bee81887
PB		 1710
1711 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
b7711471
PB		 1712 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1713 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1714 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
bee81887
PB		 1715 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1716 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
b7711471
PB		 1717 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1718 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1719 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1720 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1721 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1722 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1723 }
1724
9aecd6f8 1725#ifdef TARGET_X86_64
b7711471
PB		 1726 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1727 16 * sizeof env->xmm_regs[16]);
9aecd6f8 1728#endif
f1665b21 1729 return 0;
f1665b21
SY		 1730}
1731
1bc22652 1732static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1733{
1bc22652 1734 CPUX86State *env = &cpu->env;
f1665b21
SY		 1735 int i, ret;
1736 struct kvm_xcrs xcrs;
1737
28143b40 1738 if (!has_xcrs) {
f1665b21 1739 return 0;
b9bec74b 1740 }
f1665b21 1741
1bc22652 1742 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1743 if (ret < 0) {
f1665b21 1744 return ret;
b9bec74b 1745 }
f1665b21 1746
b9bec74b 1747 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1748 /* Only support xcr0 now */
0fd53fec
PB		 1749 if (xcrs.xcrs[i].xcr == 0) {
1750 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1751 break;
1752 }
b9bec74b 1753 }
f1665b21 1754 return 0;
f1665b21
SY		 1755}
1756
1bc22652 1757static int kvm_get_sregs(X86CPU *cpu)
05330448 1758{
1bc22652 1759 CPUX86State *env = &cpu->env;
05330448
AL		 1760 struct kvm_sregs sregs;
1761 uint32_t hflags;
0e607a80 1762 int bit, i, ret;
05330448 1763
1bc22652 1764 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1765 if (ret < 0) {
05330448 1766 return ret;
b9bec74b 1767 }
05330448 1768
0e607a80
JK		 1769 /* There can only be one pending IRQ set in the bitmap at a time, so try
1770 to find it and save its number instead (-1 for none). */
1771 env->interrupt_injected = -1;
1772 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1773 if (sregs.interrupt_bitmap[i]) {
1774 bit = ctz64(sregs.interrupt_bitmap[i]);
1775 env->interrupt_injected = i * 64 + bit;
1776 break;
1777 }
1778 }
05330448
AL		 1779
1780 get_seg(&env->segs[R_CS], &sregs.cs);
1781 get_seg(&env->segs[R_DS], &sregs.ds);
1782 get_seg(&env->segs[R_ES], &sregs.es);
1783 get_seg(&env->segs[R_FS], &sregs.fs);
1784 get_seg(&env->segs[R_GS], &sregs.gs);
1785 get_seg(&env->segs[R_SS], &sregs.ss);
1786
1787 get_seg(&env->tr, &sregs.tr);
1788 get_seg(&env->ldt, &sregs.ldt);
1789
1790 env->idt.limit = sregs.idt.limit;
1791 env->idt.base = sregs.idt.base;
1792 env->gdt.limit = sregs.gdt.limit;
1793 env->gdt.base = sregs.gdt.base;
1794
1795 env->cr[0] = sregs.cr0;
1796 env->cr[2] = sregs.cr2;
1797 env->cr[3] = sregs.cr3;
1798 env->cr[4] = sregs.cr4;
1799
05330448 1800 env->efer = sregs.efer;
cce47516
JK		 1801
1802 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1803
b9bec74b
JK		 1804#define HFLAG_COPY_MASK \
1805 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1806 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1807 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1808 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1809
7125c937 1810 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1811 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1812 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1813 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448
AL		 1814 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1815 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
b9bec74b 1816 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
05330448
AL		 1817
1818 if (env->efer & MSR_EFER_LMA) {
1819 hflags |= HF_LMA_MASK;
1820 }
1821
1822 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1823 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1824 } else {
1825 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1826 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1827 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1828 (DESC_B_SHIFT - HF_SS32_SHIFT);
1829 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1830 !(hflags & HF_CS32_MASK)) {
1831 hflags |= HF_ADDSEG_MASK;
1832 } else {
1833 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1834 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1835 }
05330448
AL		 1836 }
1837 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
05330448
AL		 1838
1839 return 0;
1840}
1841
1bc22652 1842static int kvm_get_msrs(X86CPU *cpu)
05330448 1843{
1bc22652 1844 CPUX86State *env = &cpu->env;
05330448
AL		 1845 struct {
1846 struct kvm_msrs info;
d1ae67f6 1847 struct kvm_msr_entry entries[150];
05330448
AL		 1848 } msr_data;
1849 struct kvm_msr_entry *msrs = msr_data.entries;
1850 int ret, i, n;
1851
1852 n = 0;
1853 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1854 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1855 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
0c03266a 1856 msrs[n++].index = MSR_PAT;
c3a3a7d3 1857 if (has_msr_star) {
b9bec74b
JK		 1858 msrs[n++].index = MSR_STAR;
1859 }
c3a3a7d3 1860 if (has_msr_hsave_pa) {
75b10c43 1861 msrs[n++].index = MSR_VM_HSAVE_PA;
b9bec74b 1862 }
c9b8f6b6
AS		 1863 if (has_msr_tsc_aux) {
1864 msrs[n++].index = MSR_TSC_AUX;
1865 }
f28558d3
WA		 1866 if (has_msr_tsc_adjust) {
1867 msrs[n++].index = MSR_TSC_ADJUST;
1868 }
aa82ba54
LJ		 1869 if (has_msr_tsc_deadline) {
1870 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1871 }
21e87c46
AK		 1872 if (has_msr_misc_enable) {
1873 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1874 }
fc12d72e
PB		 1875 if (has_msr_smbase) {
1876 msrs[n++].index = MSR_IA32_SMBASE;
1877 }
df67696e
LJ		 1878 if (has_msr_feature_control) {
1879 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1880 }
79e9ebeb
LJ		 1881 if (has_msr_bndcfgs) {
1882 msrs[n++].index = MSR_IA32_BNDCFGS;
1883 }
18cd2c17
WL		 1884 if (has_msr_xss) {
1885 msrs[n++].index = MSR_IA32_XSS;
1886 }
1887
b8cc45d6
GC		 1888
1889 if (!env->tsc_valid) {
1890 msrs[n++].index = MSR_IA32_TSC;
1354869c 1891 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1892 }
1893
05330448 1894#ifdef TARGET_X86_64
25d2e361
MT		 1895 if (lm_capable_kernel) {
1896 msrs[n++].index = MSR_CSTAR;
1897 msrs[n++].index = MSR_KERNELGSBASE;
1898 msrs[n++].index = MSR_FMASK;
1899 msrs[n++].index = MSR_LSTAR;
1900 }
05330448 1901#endif
1a03675d
GC		 1902 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1903 msrs[n++].index = MSR_KVM_WALL_CLOCK;
c5999bfc
JK		 1904 if (has_msr_async_pf_en) {
1905 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1906 }
bc9a839d
MT		 1907 if (has_msr_pv_eoi_en) {
1908 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1909 }
917367aa
MT		 1910 if (has_msr_kvm_steal_time) {
1911 msrs[n++].index = MSR_KVM_STEAL_TIME;
1912 }
0d894367
PB		 1913 if (has_msr_architectural_pmu) {
1914 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1915 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1916 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1917 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1918 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1919 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1920 }
1921 for (i = 0; i < num_architectural_pmu_counters; i++) {
1922 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1923 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1924 }
1925 }
1a03675d 1926
57780495
MT		 1927 if (env->mcg_cap) {
1928 msrs[n++].index = MSR_MCG_STATUS;
1929 msrs[n++].index = MSR_MCG_CTL;
b9bec74b 1930 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
57780495 1931 msrs[n++].index = MSR_MC0_CTL + i;
b9bec74b 1932 }
57780495 1933 }
57780495 1934
1c90ef26
VR		 1935 if (has_msr_hv_hypercall) {
1936 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1937 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1938 }
5ef68987
VR		 1939 if (has_msr_hv_vapic) {
1940 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1941 }
48a5f3bc
VR		 1942 if (has_msr_hv_tsc) {
1943 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1944 }
f2a53c9e
AS		 1945 if (has_msr_hv_crash) {
1946 int j;
1947
1948 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1949 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1950 }
1951 }
46eb8f98
AS		 1952 if (has_msr_hv_runtime) {
1953 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
1954 }
866eea9a
AS		 1955 if (cpu->hyperv_synic) {
1956 uint32_t msr;
1957
1958 msrs[n++].index = HV_X64_MSR_SCONTROL;
1959 msrs[n++].index = HV_X64_MSR_SVERSION;
1960 msrs[n++].index = HV_X64_MSR_SIEFP;
1961 msrs[n++].index = HV_X64_MSR_SIMP;
1962 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
1963 msrs[n++].index = msr;
1964 }
1965 }
ff99aa64
AS		 1966 if (has_msr_hv_stimer) {
1967 uint32_t msr;
1968
1969 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
1970 msr++) {
1971 msrs[n++].index = msr;
1972 }
1973 }
d1ae67f6
AW		 1974 if (has_msr_mtrr) {
1975 msrs[n++].index = MSR_MTRRdefType;
1976 msrs[n++].index = MSR_MTRRfix64K_00000;
1977 msrs[n++].index = MSR_MTRRfix16K_80000;
1978 msrs[n++].index = MSR_MTRRfix16K_A0000;
1979 msrs[n++].index = MSR_MTRRfix4K_C0000;
1980 msrs[n++].index = MSR_MTRRfix4K_C8000;
1981 msrs[n++].index = MSR_MTRRfix4K_D0000;
1982 msrs[n++].index = MSR_MTRRfix4K_D8000;
1983 msrs[n++].index = MSR_MTRRfix4K_E0000;
1984 msrs[n++].index = MSR_MTRRfix4K_E8000;
1985 msrs[n++].index = MSR_MTRRfix4K_F0000;
1986 msrs[n++].index = MSR_MTRRfix4K_F8000;
1987 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1988 msrs[n++].index = MSR_MTRRphysBase(i);
1989 msrs[n++].index = MSR_MTRRphysMask(i);
1990 }
1991 }
5ef68987 1992
d19ae73e
CB		 1993 msr_data.info = (struct kvm_msrs) {
1994 .nmsrs = n,
1995 };
1996
1bc22652 1997 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
b9bec74b 1998 if (ret < 0) {
05330448 1999 return ret;
b9bec74b 2000 }
05330448
AL		 2001
2002 for (i = 0; i < ret; i++) {
0d894367
PB		 2003 uint32_t index = msrs[i].index;
2004 switch (index) {
05330448
AL		 2005 case MSR_IA32_SYSENTER_CS:
2006 env->sysenter_cs = msrs[i].data;
2007 break;
2008 case MSR_IA32_SYSENTER_ESP:
2009 env->sysenter_esp = msrs[i].data;
2010 break;
2011 case MSR_IA32_SYSENTER_EIP:
2012 env->sysenter_eip = msrs[i].data;
2013 break;
0c03266a
JK		 2014 case MSR_PAT:
2015 env->pat = msrs[i].data;
2016 break;
05330448
AL		 2017 case MSR_STAR:
2018 env->star = msrs[i].data;
2019 break;
2020#ifdef TARGET_X86_64
2021 case MSR_CSTAR:
2022 env->cstar = msrs[i].data;
2023 break;
2024 case MSR_KERNELGSBASE:
2025 env->kernelgsbase = msrs[i].data;
2026 break;
2027 case MSR_FMASK:
2028 env->fmask = msrs[i].data;
2029 break;
2030 case MSR_LSTAR:
2031 env->lstar = msrs[i].data;
2032 break;
2033#endif
2034 case MSR_IA32_TSC:
2035 env->tsc = msrs[i].data;
2036 break;
c9b8f6b6
AS		 2037 case MSR_TSC_AUX:
2038 env->tsc_aux = msrs[i].data;
2039 break;
f28558d3
WA		 2040 case MSR_TSC_ADJUST:
2041 env->tsc_adjust = msrs[i].data;
2042 break;
aa82ba54
LJ		 2043 case MSR_IA32_TSCDEADLINE:
2044 env->tsc_deadline = msrs[i].data;
2045 break;
aa851e36
MT		 2046 case MSR_VM_HSAVE_PA:
2047 env->vm_hsave = msrs[i].data;
2048 break;
1a03675d
GC		 2049 case MSR_KVM_SYSTEM_TIME:
2050 env->system_time_msr = msrs[i].data;
2051 break;
2052 case MSR_KVM_WALL_CLOCK:
2053 env->wall_clock_msr = msrs[i].data;
2054 break;
57780495
MT		 2055 case MSR_MCG_STATUS:
2056 env->mcg_status = msrs[i].data;
2057 break;
2058 case MSR_MCG_CTL:
2059 env->mcg_ctl = msrs[i].data;
2060 break;
21e87c46
AK		 2061 case MSR_IA32_MISC_ENABLE:
2062 env->msr_ia32_misc_enable = msrs[i].data;
2063 break;
fc12d72e
PB		 2064 case MSR_IA32_SMBASE:
2065 env->smbase = msrs[i].data;
2066 break;
0779caeb
ACL		 2067 case MSR_IA32_FEATURE_CONTROL:
2068 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2069 break;
79e9ebeb
LJ		 2070 case MSR_IA32_BNDCFGS:
2071 env->msr_bndcfgs = msrs[i].data;
2072 break;
18cd2c17
WL		 2073 case MSR_IA32_XSS:
2074 env->xss = msrs[i].data;
2075 break;
57780495 2076 default:
57780495
MT		 2077 if (msrs[i].index >= MSR_MC0_CTL &&
2078 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2079 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2080 }
d8da8574 2081 break;
f6584ee2
GN		 2082 case MSR_KVM_ASYNC_PF_EN:
2083 env->async_pf_en_msr = msrs[i].data;
2084 break;
bc9a839d
MT		 2085 case MSR_KVM_PV_EOI_EN:
2086 env->pv_eoi_en_msr = msrs[i].data;
2087 break;
917367aa
MT		 2088 case MSR_KVM_STEAL_TIME:
2089 env->steal_time_msr = msrs[i].data;
2090 break;
0d894367
PB		 2091 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2092 env->msr_fixed_ctr_ctrl = msrs[i].data;
2093 break;
2094 case MSR_CORE_PERF_GLOBAL_CTRL:
2095 env->msr_global_ctrl = msrs[i].data;
2096 break;
2097 case MSR_CORE_PERF_GLOBAL_STATUS:
2098 env->msr_global_status = msrs[i].data;
2099 break;
2100 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2101 env->msr_global_ovf_ctrl = msrs[i].data;
2102 break;
2103 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2104 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2105 break;
2106 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2107 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2108 break;
2109 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2110 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2111 break;
1c90ef26
VR		 2112 case HV_X64_MSR_HYPERCALL:
2113 env->msr_hv_hypercall = msrs[i].data;
2114 break;
2115 case HV_X64_MSR_GUEST_OS_ID:
2116 env->msr_hv_guest_os_id = msrs[i].data;
2117 break;
5ef68987
VR		 2118 case HV_X64_MSR_APIC_ASSIST_PAGE:
2119 env->msr_hv_vapic = msrs[i].data;
2120 break;
48a5f3bc
VR		 2121 case HV_X64_MSR_REFERENCE_TSC:
2122 env->msr_hv_tsc = msrs[i].data;
2123 break;
f2a53c9e
AS		 2124 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2125 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2126 break;
46eb8f98
AS		 2127 case HV_X64_MSR_VP_RUNTIME:
2128 env->msr_hv_runtime = msrs[i].data;
2129 break;
866eea9a
AS		 2130 case HV_X64_MSR_SCONTROL:
2131 env->msr_hv_synic_control = msrs[i].data;
2132 break;
2133 case HV_X64_MSR_SVERSION:
2134 env->msr_hv_synic_version = msrs[i].data;
2135 break;
2136 case HV_X64_MSR_SIEFP:
2137 env->msr_hv_synic_evt_page = msrs[i].data;
2138 break;
2139 case HV_X64_MSR_SIMP:
2140 env->msr_hv_synic_msg_page = msrs[i].data;
2141 break;
2142 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2143 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2144 break;
2145 case HV_X64_MSR_STIMER0_CONFIG:
2146 case HV_X64_MSR_STIMER1_CONFIG:
2147 case HV_X64_MSR_STIMER2_CONFIG:
2148 case HV_X64_MSR_STIMER3_CONFIG:
2149 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2150 msrs[i].data;
2151 break;
2152 case HV_X64_MSR_STIMER0_COUNT:
2153 case HV_X64_MSR_STIMER1_COUNT:
2154 case HV_X64_MSR_STIMER2_COUNT:
2155 case HV_X64_MSR_STIMER3_COUNT:
2156 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2157 msrs[i].data;
866eea9a 2158 break;
d1ae67f6
AW		 2159 case MSR_MTRRdefType:
2160 env->mtrr_deftype = msrs[i].data;
2161 break;
2162 case MSR_MTRRfix64K_00000:
2163 env->mtrr_fixed[0] = msrs[i].data;
2164 break;
2165 case MSR_MTRRfix16K_80000:
2166 env->mtrr_fixed[1] = msrs[i].data;
2167 break;
2168 case MSR_MTRRfix16K_A0000:
2169 env->mtrr_fixed[2] = msrs[i].data;
2170 break;
2171 case MSR_MTRRfix4K_C0000:
2172 env->mtrr_fixed[3] = msrs[i].data;
2173 break;
2174 case MSR_MTRRfix4K_C8000:
2175 env->mtrr_fixed[4] = msrs[i].data;
2176 break;
2177 case MSR_MTRRfix4K_D0000:
2178 env->mtrr_fixed[5] = msrs[i].data;
2179 break;
2180 case MSR_MTRRfix4K_D8000:
2181 env->mtrr_fixed[6] = msrs[i].data;
2182 break;
2183 case MSR_MTRRfix4K_E0000:
2184 env->mtrr_fixed[7] = msrs[i].data;
2185 break;
2186 case MSR_MTRRfix4K_E8000:
2187 env->mtrr_fixed[8] = msrs[i].data;
2188 break;
2189 case MSR_MTRRfix4K_F0000:
2190 env->mtrr_fixed[9] = msrs[i].data;
2191 break;
2192 case MSR_MTRRfix4K_F8000:
2193 env->mtrr_fixed[10] = msrs[i].data;
2194 break;
2195 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2196 if (index & 1) {
2197 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2198 } else {
2199 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2200 }
2201 break;
05330448
AL		 2202 }
2203 }
2204
2205 return 0;
2206}
2207
1bc22652 2208static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2209{
1bc22652 2210 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2211
1bc22652 2212 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2213}
2214
23d02d9b 2215static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2216{
259186a7 2217 CPUState *cs = CPU(cpu);
23d02d9b 2218 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2219 struct kvm_mp_state mp_state;
2220 int ret;
2221
259186a7 2222 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2223 if (ret < 0) {
2224 return ret;
2225 }
2226 env->mp_state = mp_state.mp_state;
c14750e8 2227 if (kvm_irqchip_in_kernel()) {
259186a7 2228 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2229 }
9bdbe550
HB		 2230 return 0;
2231}
2232
1bc22652 2233static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2234{
02e51483 2235 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2236 struct kvm_lapic_state kapic;
2237 int ret;
2238
3d4b2649 2239 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2240 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2241 if (ret < 0) {
2242 return ret;
2243 }
2244
2245 kvm_get_apic_state(apic, &kapic);
2246 }
2247 return 0;
2248}
2249
1bc22652 2250static int kvm_put_apic(X86CPU *cpu)
680c1c6f 2251{
02e51483 2252 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2253 struct kvm_lapic_state kapic;
2254
3d4b2649 2255 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 2256 kvm_put_apic_state(apic, &kapic);
2257
1bc22652 2258 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 2259 }
2260 return 0;
2261}
2262
1bc22652 2263static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2264{
fc12d72e 2265 CPUState *cs = CPU(cpu);
1bc22652 2266 CPUX86State *env = &cpu->env;
076796f8 2267 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2268
2269 if (!kvm_has_vcpu_events()) {
2270 return 0;
2271 }
2272
31827373
JK		 2273 events.exception.injected = (env->exception_injected >= 0);
2274 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2275 events.exception.has_error_code = env->has_error_code;
2276 events.exception.error_code = env->error_code;
7e680753 2277 events.exception.pad = 0;
a0fb002c
JK		 2278
2279 events.interrupt.injected = (env->interrupt_injected >= 0);
2280 events.interrupt.nr = env->interrupt_injected;
2281 events.interrupt.soft = env->soft_interrupt;
2282
2283 events.nmi.injected = env->nmi_injected;
2284 events.nmi.pending = env->nmi_pending;
2285 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2286 events.nmi.pad = 0;
a0fb002c
JK		 2287
2288 events.sipi_vector = env->sipi_vector;
2289
fc12d72e
PB		 2290 if (has_msr_smbase) {
2291 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2292 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2293 if (kvm_irqchip_in_kernel()) {
2294 /* As soon as these are moved to the kernel, remove them
2295 * from cs->interrupt_request.
2296 */
2297 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2298 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2299 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2300 } else {
2301 /* Keep these in cs->interrupt_request. */
2302 events.smi.pending = 0;
2303 events.smi.latched_init = 0;
2304 }
2305 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2306 }
2307
ea643051
JK		 2308 events.flags = 0;
2309 if (level >= KVM_PUT_RESET_STATE) {
2310 events.flags |=
2311 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2312 }
aee028b9 2313
1bc22652 2314 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2315}
2316
1bc22652 2317static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2318{
1bc22652 2319 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2320 struct kvm_vcpu_events events;
2321 int ret;
2322
2323 if (!kvm_has_vcpu_events()) {
2324 return 0;
2325 }
2326
fc12d72e 2327 memset(&events, 0, sizeof(events));
1bc22652 2328 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2329 if (ret < 0) {
2330 return ret;
2331 }
31827373 2332 env->exception_injected =
a0fb002c
JK		 2333 events.exception.injected ? events.exception.nr : -1;
2334 env->has_error_code = events.exception.has_error_code;
2335 env->error_code = events.exception.error_code;
2336
2337 env->interrupt_injected =
2338 events.interrupt.injected ? events.interrupt.nr : -1;
2339 env->soft_interrupt = events.interrupt.soft;
2340
2341 env->nmi_injected = events.nmi.injected;
2342 env->nmi_pending = events.nmi.pending;
2343 if (events.nmi.masked) {
2344 env->hflags2 |= HF2_NMI_MASK;
2345 } else {
2346 env->hflags2 &= ~HF2_NMI_MASK;
2347 }
2348
fc12d72e
PB		 2349 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2350 if (events.smi.smm) {
2351 env->hflags |= HF_SMM_MASK;
2352 } else {
2353 env->hflags &= ~HF_SMM_MASK;
2354 }
2355 if (events.smi.pending) {
2356 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2357 } else {
2358 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2359 }
2360 if (events.smi.smm_inside_nmi) {
2361 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2362 } else {
2363 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2364 }
2365 if (events.smi.latched_init) {
2366 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2367 } else {
2368 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2369 }
2370 }
2371
a0fb002c 2372 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2373
2374 return 0;
2375}
2376
1bc22652 2377static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2378{
ed2803da 2379 CPUState *cs = CPU(cpu);
1bc22652 2380 CPUX86State *env = &cpu->env;
b0b1d690 2381 int ret = 0;
b0b1d690
JK		 2382 unsigned long reinject_trap = 0;
2383
2384 if (!kvm_has_vcpu_events()) {
2385 if (env->exception_injected == 1) {
2386 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2387 } else if (env->exception_injected == 3) {
2388 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2389 }
2390 env->exception_injected = -1;
2391 }
2392
2393 /*
2394 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2395 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2396 * by updating the debug state once again if single-stepping is on.
2397 * Another reason to call kvm_update_guest_debug here is a pending debug
2398 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2399 * reinject them via SET_GUEST_DEBUG.
2400 */
2401 if (reinject_trap ||
ed2803da 2402 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2403 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2404 }
b0b1d690
JK		 2405 return ret;
2406}
2407
1bc22652 2408static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2409{
1bc22652 2410 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2411 struct kvm_debugregs dbgregs;
2412 int i;
2413
2414 if (!kvm_has_debugregs()) {
2415 return 0;
2416 }
2417
2418 for (i = 0; i < 4; i++) {
2419 dbgregs.db[i] = env->dr[i];
2420 }
2421 dbgregs.dr6 = env->dr[6];
2422 dbgregs.dr7 = env->dr[7];
2423 dbgregs.flags = 0;
2424
1bc22652 2425 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2426}
2427
1bc22652 2428static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2429{
1bc22652 2430 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2431 struct kvm_debugregs dbgregs;
2432 int i, ret;
2433
2434 if (!kvm_has_debugregs()) {
2435 return 0;
2436 }
2437
1bc22652 2438 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2439 if (ret < 0) {
b9bec74b 2440 return ret;
ff44f1a3
JK		 2441 }
2442 for (i = 0; i < 4; i++) {
2443 env->dr[i] = dbgregs.db[i];
2444 }
2445 env->dr[4] = env->dr[6] = dbgregs.dr6;
2446 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2447
2448 return 0;
2449}
2450
20d695a9 2451int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2452{
20d695a9 2453 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2454 int ret;
2455
2fa45344 2456 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2457
6bdf863d
JK		 2458 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2459 ret = kvm_put_msr_feature_control(x86_cpu);
2460 if (ret < 0) {
2461 return ret;
2462 }
2463 }
2464
1bc22652 2465 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2466 if (ret < 0) {
05330448 2467 return ret;
b9bec74b 2468 }
1bc22652 2469 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2470 if (ret < 0) {
f1665b21 2471 return ret;
b9bec74b 2472 }
1bc22652 2473 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2474 if (ret < 0) {
05330448 2475 return ret;
b9bec74b 2476 }
1bc22652 2477 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2478 if (ret < 0) {
05330448 2479 return ret;
b9bec74b 2480 }
ab443475 2481 /* must be before kvm_put_msrs */
1bc22652 2482 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2483 if (ret < 0) {
2484 return ret;
2485 }
1bc22652 2486 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2487 if (ret < 0) {
05330448 2488 return ret;
b9bec74b 2489 }
ea643051 2490 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2491 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2492 if (ret < 0) {
ea643051 2493 return ret;
b9bec74b 2494 }
1bc22652 2495 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2496 if (ret < 0) {
2497 return ret;
2498 }
ea643051 2499 }
7477cd38
MT		 2500
2501 ret = kvm_put_tscdeadline_msr(x86_cpu);
2502 if (ret < 0) {
2503 return ret;
2504 }
2505
1bc22652 2506 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2507 if (ret < 0) {
a0fb002c 2508 return ret;
b9bec74b 2509 }
1bc22652 2510 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2511 if (ret < 0) {
b0b1d690 2512 return ret;
b9bec74b 2513 }
b0b1d690 2514 /* must be last */
1bc22652 2515 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2516 if (ret < 0) {
ff44f1a3 2517 return ret;
b9bec74b 2518 }
05330448
AL		 2519 return 0;
2520}
2521
20d695a9 2522int kvm_arch_get_registers(CPUState *cs)
05330448 2523{
20d695a9 2524 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2525 int ret;
2526
20d695a9 2527 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2528
1bc22652 2529 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2530 if (ret < 0) {
05330448 2531 return ret;
b9bec74b 2532 }
1bc22652 2533 ret = kvm_get_xsave(cpu);
b9bec74b 2534 if (ret < 0) {
f1665b21 2535 return ret;
b9bec74b 2536 }
1bc22652 2537 ret = kvm_get_xcrs(cpu);
b9bec74b 2538 if (ret < 0) {
05330448 2539 return ret;
b9bec74b 2540 }
1bc22652 2541 ret = kvm_get_sregs(cpu);
b9bec74b 2542 if (ret < 0) {
05330448 2543 return ret;
b9bec74b 2544 }
1bc22652 2545 ret = kvm_get_msrs(cpu);
b9bec74b 2546 if (ret < 0) {
05330448 2547 return ret;
b9bec74b 2548 }
23d02d9b 2549 ret = kvm_get_mp_state(cpu);
b9bec74b 2550 if (ret < 0) {
5a2e3c2e 2551 return ret;
b9bec74b 2552 }
1bc22652 2553 ret = kvm_get_apic(cpu);
680c1c6f
JK		 2554 if (ret < 0) {
2555 return ret;
2556 }
1bc22652 2557 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2558 if (ret < 0) {
a0fb002c 2559 return ret;
b9bec74b 2560 }
1bc22652 2561 ret = kvm_get_debugregs(cpu);
b9bec74b 2562 if (ret < 0) {
ff44f1a3 2563 return ret;
b9bec74b 2564 }
05330448
AL		 2565 return 0;
2566}
2567
20d695a9 2568void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2569{
20d695a9
AF		 2570 X86CPU *x86_cpu = X86_CPU(cpu);
2571 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2572 int ret;
2573
276ce815 2574 /* Inject NMI */
fc12d72e
PB		 2575 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2576 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2577 qemu_mutex_lock_iothread();
2578 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2579 qemu_mutex_unlock_iothread();
2580 DPRINTF("injected NMI\n");
2581 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2582 if (ret < 0) {
2583 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2584 strerror(-ret));
2585 }
2586 }
2587 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2588 qemu_mutex_lock_iothread();
2589 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2590 qemu_mutex_unlock_iothread();
2591 DPRINTF("injected SMI\n");
2592 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2593 if (ret < 0) {
2594 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2595 strerror(-ret));
2596 }
ce377af3 2597 }
276ce815
LJ		 2598 }
2599
4b8523ee
JK		 2600 if (!kvm_irqchip_in_kernel()) {
2601 qemu_mutex_lock_iothread();
2602 }
2603
e0723c45
PB		 2604 /* Force the VCPU out of its inner loop to process any INIT requests
2605 * or (for userspace APIC, but it is cheap to combine the checks here)
2606 * pending TPR access reports.
2607 */
2608 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2609 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2610 !(env->hflags & HF_SMM_MASK)) {
2611 cpu->exit_request = 1;
2612 }
2613 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2614 cpu->exit_request = 1;
2615 }
e0723c45 2616 }
05330448 2617
e0723c45 2618 if (!kvm_irqchip_in_kernel()) {
db1669bc
JK		 2619 /* Try to inject an interrupt if the guest can accept it */
2620 if (run->ready_for_interrupt_injection &&
259186a7 2621 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2622 (env->eflags & IF_MASK)) {
2623 int irq;
2624
259186a7 2625 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2626 irq = cpu_get_pic_interrupt(env);
2627 if (irq >= 0) {
2628 struct kvm_interrupt intr;
2629
2630 intr.irq = irq;
db1669bc 2631 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2632 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2633 if (ret < 0) {
2634 fprintf(stderr,
2635 "KVM: injection failed, interrupt lost (%s)\n",
2636 strerror(-ret));
2637 }
db1669bc
JK		 2638 }
2639 }
05330448 2640
db1669bc
JK		 2641 /* If we have an interrupt but the guest is not ready to receive an
2642 * interrupt, request an interrupt window exit. This will
2643 * cause a return to userspace as soon as the guest is ready to
2644 * receive interrupts. */
259186a7 2645 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2646 run->request_interrupt_window = 1;
2647 } else {
2648 run->request_interrupt_window = 0;
2649 }
2650
2651 DPRINTF("setting tpr\n");
02e51483 2652 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2653
2654 qemu_mutex_unlock_iothread();
db1669bc 2655 }
05330448
AL		 2656}
2657
4c663752 2658MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2659{
20d695a9
AF		 2660 X86CPU *x86_cpu = X86_CPU(cpu);
2661 CPUX86State *env = &x86_cpu->env;
2662
fc12d72e
PB		 2663 if (run->flags & KVM_RUN_X86_SMM) {
2664 env->hflags |= HF_SMM_MASK;
2665 } else {
2666 env->hflags &= HF_SMM_MASK;
2667 }
b9bec74b 2668 if (run->if_flag) {
05330448 2669 env->eflags |= IF_MASK;
b9bec74b 2670 } else {
05330448 2671 env->eflags &= ~IF_MASK;
b9bec74b 2672 }
4b8523ee
JK		 2673
2674 /* We need to protect the apic state against concurrent accesses from
2675 * different threads in case the userspace irqchip is used. */
2676 if (!kvm_irqchip_in_kernel()) {
2677 qemu_mutex_lock_iothread();
2678 }
02e51483
CF		 2679 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2680 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2681 if (!kvm_irqchip_in_kernel()) {
2682 qemu_mutex_unlock_iothread();
2683 }
f794aa4a 2684 return cpu_get_mem_attrs(env);
05330448
AL		 2685}
2686
20d695a9 2687int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2688{
20d695a9
AF		 2689 X86CPU *cpu = X86_CPU(cs);
2690 CPUX86State *env = &cpu->env;
232fc23b 2691
259186a7 2692 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2693 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2694 assert(env->mcg_cap);
2695
259186a7 2696 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2697
dd1750d7 2698 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2699
2700 if (env->exception_injected == EXCP08_DBLE) {
2701 /* this means triple fault */
2702 qemu_system_reset_request();
fcd7d003 2703 cs->exit_request = 1;
ab443475
JK		 2704 return 0;
2705 }
2706 env->exception_injected = EXCP12_MCHK;
2707 env->has_error_code = 0;
2708
259186a7 2709 cs->halted = 0;
ab443475
JK		 2710 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2711 env->mp_state = KVM_MP_STATE_RUNNABLE;
2712 }
2713 }
2714
fc12d72e
PB		 2715 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2716 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2717 kvm_cpu_synchronize_state(cs);
2718 do_cpu_init(cpu);
2719 }
2720
db1669bc
JK		 2721 if (kvm_irqchip_in_kernel()) {
2722 return 0;
2723 }
2724
259186a7
AF		 2725 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2726 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2727 apic_poll_irq(cpu->apic_state);
5d62c43a 2728 }
259186a7 2729 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2730 (env->eflags & IF_MASK)) ||
259186a7
AF		 2731 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2732 cs->halted = 0;
6792a57b 2733 }
259186a7 2734 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2735 kvm_cpu_synchronize_state(cs);
232fc23b 2736 do_cpu_sipi(cpu);
0af691d7 2737 }
259186a7
AF		 2738 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2739 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2740 kvm_cpu_synchronize_state(cs);
02e51483 2741 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2742 env->tpr_access_type);
2743 }
0af691d7 2744
259186a7 2745 return cs->halted;
0af691d7
MT		 2746}
2747
839b5630 2748static int kvm_handle_halt(X86CPU *cpu)
05330448 2749{
259186a7 2750 CPUState *cs = CPU(cpu);
839b5630
AF		 2751 CPUX86State *env = &cpu->env;
2752
259186a7 2753 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2754 (env->eflags & IF_MASK)) &&
259186a7
AF		 2755 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2756 cs->halted = 1;
bb4ea393 2757 return EXCP_HLT;
05330448
AL		 2758 }
2759
bb4ea393 2760 return 0;
05330448
AL		 2761}
2762
f7575c96 2763static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2764{
f7575c96
AF		 2765 CPUState *cs = CPU(cpu);
2766 struct kvm_run *run = cs->kvm_run;
d362e757 2767
02e51483 2768 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2769 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2770 : TPR_ACCESS_READ);
2771 return 1;
2772}
2773
f17ec444 2774int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2775{
38972938 2776 static const uint8_t int3 = 0xcc;
64bf3f4e 2777
f17ec444
AF		 2778 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2779 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2780 return -EINVAL;
b9bec74b 2781 }
e22a25c9
AL		 2782 return 0;
2783}
2784
f17ec444 2785int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2786{
2787 uint8_t int3;
2788
f17ec444
AF		 2789 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2790 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2791 return -EINVAL;
b9bec74b 2792 }
e22a25c9
AL		 2793 return 0;
2794}
2795
2796static struct {
2797 target_ulong addr;
2798 int len;
2799 int type;
2800} hw_breakpoint[4];
2801
2802static int nb_hw_breakpoint;
2803
2804static int find_hw_breakpoint(target_ulong addr, int len, int type)
2805{
2806 int n;
2807
b9bec74b 2808 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2809 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2810 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2811 return n;
b9bec74b
JK		 2812 }
2813 }
e22a25c9
AL		 2814 return -1;
2815}
2816
2817int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2818 target_ulong len, int type)
2819{
2820 switch (type) {
2821 case GDB_BREAKPOINT_HW:
2822 len = 1;
2823 break;
2824 case GDB_WATCHPOINT_WRITE:
2825 case GDB_WATCHPOINT_ACCESS:
2826 switch (len) {
2827 case 1:
2828 break;
2829 case 2:
2830 case 4:
2831 case 8:
b9bec74b 2832 if (addr & (len - 1)) {
e22a25c9 2833 return -EINVAL;
b9bec74b 2834 }
e22a25c9
AL		 2835 break;
2836 default:
2837 return -EINVAL;
2838 }
2839 break;
2840 default:
2841 return -ENOSYS;
2842 }
2843
b9bec74b 2844 if (nb_hw_breakpoint == 4) {
e22a25c9 2845 return -ENOBUFS;
b9bec74b
JK		 2846 }
2847 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2848 return -EEXIST;
b9bec74b 2849 }
e22a25c9
AL		 2850 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2851 hw_breakpoint[nb_hw_breakpoint].len = len;
2852 hw_breakpoint[nb_hw_breakpoint].type = type;
2853 nb_hw_breakpoint++;
2854
2855 return 0;
2856}
2857
2858int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2859 target_ulong len, int type)
2860{
2861 int n;
2862
2863 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2864 if (n < 0) {
e22a25c9 2865 return -ENOENT;
b9bec74b 2866 }
e22a25c9
AL		 2867 nb_hw_breakpoint--;
2868 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2869
2870 return 0;
2871}
2872
2873void kvm_arch_remove_all_hw_breakpoints(void)
2874{
2875 nb_hw_breakpoint = 0;
2876}
2877
2878static CPUWatchpoint hw_watchpoint;
2879
a60f24b5 2880static int kvm_handle_debug(X86CPU *cpu,
48405526 2881 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2882{
ed2803da 2883 CPUState *cs = CPU(cpu);
a60f24b5 2884 CPUX86State *env = &cpu->env;
f2574737 2885 int ret = 0;
e22a25c9
AL		 2886 int n;
2887
2888 if (arch_info->exception == 1) {
2889 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2890 if (cs->singlestep_enabled) {
f2574737 2891 ret = EXCP_DEBUG;
b9bec74b 2892 }
e22a25c9 2893 } else {
b9bec74b
JK		 2894 for (n = 0; n < 4; n++) {
2895 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 2896 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2897 case 0x0:
f2574737 2898 ret = EXCP_DEBUG;
e22a25c9
AL		 2899 break;
2900 case 0x1:
f2574737 2901 ret = EXCP_DEBUG;
ff4700b0 2902 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2903 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2904 hw_watchpoint.flags = BP_MEM_WRITE;
2905 break;
2906 case 0x3:
f2574737 2907 ret = EXCP_DEBUG;
ff4700b0 2908 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2909 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2910 hw_watchpoint.flags = BP_MEM_ACCESS;
2911 break;
2912 }
b9bec74b
JK		 2913 }
2914 }
e22a25c9 2915 }
ff4700b0 2916 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 2917 ret = EXCP_DEBUG;
b9bec74b 2918 }
f2574737 2919 if (ret == 0) {
ff4700b0 2920 cpu_synchronize_state(cs);
48405526 2921 assert(env->exception_injected == -1);
b0b1d690 2922
f2574737 2923 /* pass to guest */
48405526
BS		 2924 env->exception_injected = arch_info->exception;
2925 env->has_error_code = 0;
b0b1d690 2926 }
e22a25c9 2927
f2574737 2928 return ret;
e22a25c9
AL		 2929}
2930
20d695a9 2931void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 2932{
2933 const uint8_t type_code[] = {
2934 [GDB_BREAKPOINT_HW] = 0x0,
2935 [GDB_WATCHPOINT_WRITE] = 0x1,
2936 [GDB_WATCHPOINT_ACCESS] = 0x3
2937 };
2938 const uint8_t len_code[] = {
2939 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2940 };
2941 int n;
2942
a60f24b5 2943 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 2944 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 2945 }
e22a25c9
AL		 2946 if (nb_hw_breakpoint > 0) {
2947 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2948 dbg->arch.debugreg[7] = 0x0600;
2949 for (n = 0; n < nb_hw_breakpoint; n++) {
2950 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2951 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2952 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 2953 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 2954 }
2955 }
2956}
4513d923 2957
2a4dac83
JK		 2958static bool host_supports_vmx(void)
2959{
2960 uint32_t ecx, unused;
2961
2962 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2963 return ecx & CPUID_EXT_VMX;
2964}
2965
2966#define VMX_INVALID_GUEST_STATE 0x80000021
2967
20d695a9 2968int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 2969{
20d695a9 2970 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 2971 uint64_t code;
2972 int ret;
2973
2974 switch (run->exit_reason) {
2975 case KVM_EXIT_HLT:
2976 DPRINTF("handle_hlt\n");
4b8523ee 2977 qemu_mutex_lock_iothread();
839b5630 2978 ret = kvm_handle_halt(cpu);
4b8523ee 2979 qemu_mutex_unlock_iothread();
2a4dac83
JK		 2980 break;
2981 case KVM_EXIT_SET_TPR:
2982 ret = 0;
2983 break;
d362e757 2984 case KVM_EXIT_TPR_ACCESS:
4b8523ee 2985 qemu_mutex_lock_iothread();
f7575c96 2986 ret = kvm_handle_tpr_access(cpu);
4b8523ee 2987 qemu_mutex_unlock_iothread();
d362e757 2988 break;
2a4dac83
JK		 2989 case KVM_EXIT_FAIL_ENTRY:
2990 code = run->fail_entry.hardware_entry_failure_reason;
2991 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2992 code);
2993 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2994 fprintf(stderr,
12619721 2995 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 2996 "unrestricted mode\n"
2997 "support, the failure can be most likely due to the guest "
2998 "entering an invalid\n"
2999 "state for Intel VT. For example, the guest maybe running "
3000 "in big real mode\n"
3001 "which is not supported on less recent Intel processors."
3002 "\n\n");
3003 }
3004 ret = -1;
3005 break;
3006 case KVM_EXIT_EXCEPTION:
3007 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3008 run->ex.exception, run->ex.error_code);
3009 ret = -1;
3010 break;
f2574737
JK		 3011 case KVM_EXIT_DEBUG:
3012 DPRINTF("kvm_exit_debug\n");
4b8523ee 3013 qemu_mutex_lock_iothread();
a60f24b5 3014 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3015 qemu_mutex_unlock_iothread();
f2574737 3016 break;
50efe82c
AS		 3017 case KVM_EXIT_HYPERV:
3018 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3019 break;
2a4dac83
JK		 3020 default:
3021 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3022 ret = -1;
3023 break;
3024 }
3025
3026 return ret;
3027}
3028
20d695a9 3029bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3030{
20d695a9
AF		 3031 X86CPU *cpu = X86_CPU(cs);
3032 CPUX86State *env = &cpu->env;
3033
dd1750d7 3034 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3035 return !(env->cr[0] & CR0_PE_MASK) ||
3036 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3037}
84b058d7
JK		 3038
3039void kvm_arch_init_irq_routing(KVMState *s)
3040{
3041 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3042 /* If kernel can't do irq routing, interrupt source
3043 * override 0->2 cannot be set up as required by HPET.
3044 * So we have to disable it.
3045 */
3046 no_hpet = 1;
3047 }
cc7e0ddf 3048 /* We know at this point that we're using the in-kernel
614e41bc 3049 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3050 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3051 */
614e41bc 3052 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3053 kvm_gsi_routing_allowed = true;
84b058d7 3054}
b139bd30
JK		 3055
3056/* Classic KVM device assignment interface. Will remain x86 only. */
3057int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3058 uint32_t flags, uint32_t *dev_id)
3059{
3060 struct kvm_assigned_pci_dev dev_data = {
3061 .segnr = dev_addr->domain,
3062 .busnr = dev_addr->bus,
3063 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3064 .flags = flags,
3065 };
3066 int ret;
3067
3068 dev_data.assigned_dev_id =
3069 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3070
3071 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3072 if (ret < 0) {
3073 return ret;
3074 }
3075
3076 *dev_id = dev_data.assigned_dev_id;
3077
3078 return 0;
3079}
3080
3081int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3082{
3083 struct kvm_assigned_pci_dev dev_data = {
3084 .assigned_dev_id = dev_id,
3085 };
3086
3087 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3088}
3089
3090static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3091 uint32_t irq_type, uint32_t guest_irq)
3092{
3093 struct kvm_assigned_irq assigned_irq = {
3094 .assigned_dev_id = dev_id,
3095 .guest_irq = guest_irq,
3096 .flags = irq_type,
3097 };
3098
3099 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3100 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3101 } else {
3102 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3103 }
3104}
3105
3106int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3107 uint32_t guest_irq)
3108{
3109 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3110 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3111
3112 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3113}
3114
3115int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3116{
3117 struct kvm_assigned_pci_dev dev_data = {
3118 .assigned_dev_id = dev_id,
3119 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3120 };
3121
3122 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3123}
3124
3125static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3126 uint32_t type)
3127{
3128 struct kvm_assigned_irq assigned_irq = {
3129 .assigned_dev_id = dev_id,
3130 .flags = type,
3131 };
3132
3133 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3134}
3135
3136int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3137{
3138 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3139 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3140}
3141
3142int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3143{
3144 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3145 KVM_DEV_IRQ_GUEST_MSI, virq);
3146}
3147
3148int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3149{
3150 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3151 KVM_DEV_IRQ_HOST_MSI);
3152}
3153
3154bool kvm_device_msix_supported(KVMState *s)
3155{
3156 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3157 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3158 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3159}
3160
3161int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3162 uint32_t nr_vectors)
3163{
3164 struct kvm_assigned_msix_nr msix_nr = {
3165 .assigned_dev_id = dev_id,
3166 .entry_nr = nr_vectors,
3167 };
3168
3169 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3170}
3171
3172int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3173 int virq)
3174{
3175 struct kvm_assigned_msix_entry msix_entry = {
3176 .assigned_dev_id = dev_id,
3177 .gsi = virq,
3178 .entry = vector,
3179 };
3180
3181 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3182}
3183
3184int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3185{
3186 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3187 KVM_DEV_IRQ_GUEST_MSIX, 0);
3188}
3189
3190int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3191{
3192 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3193 KVM_DEV_IRQ_HOST_MSIX);
3194}
9e03a040
FB		 3195
3196int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3197 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 3198{
3199 return 0;
3200}
1850b6b7
EA		 3201
3202int kvm_arch_msi_data_to_gsi(uint32_t data)
3203{
3204 abort();
3205}
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