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Commit | Line | Data |
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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <sys/types.h> | |
16 | #include <sys/ioctl.h> | |
17 | #include <sys/mman.h> | |
25d2e361 | 18 | #include <sys/utsname.h> |
05330448 AL |
19 | |
20 | #include <linux/kvm.h> | |
5802e066 | 21 | #include <linux/kvm_para.h> |
05330448 AL |
22 | |
23 | #include "qemu-common.h" | |
9c17d615 | 24 | #include "sysemu/sysemu.h" |
6410848b | 25 | #include "sysemu/kvm_int.h" |
1d31f66b | 26 | #include "kvm_i386.h" |
05330448 | 27 | #include "cpu.h" |
50efe82c AS |
28 | #include "hyperv.h" |
29 | ||
022c62cb | 30 | #include "exec/gdbstub.h" |
1de7afc9 PB |
31 | #include "qemu/host-utils.h" |
32 | #include "qemu/config-file.h" | |
1c4a55db | 33 | #include "qemu/error-report.h" |
0d09e41a PB |
34 | #include "hw/i386/pc.h" |
35 | #include "hw/i386/apic.h" | |
e0723c45 PB |
36 | #include "hw/i386/apic_internal.h" |
37 | #include "hw/i386/apic-msidef.h" | |
50efe82c | 38 | |
022c62cb | 39 | #include "exec/ioport.h" |
73aa529a | 40 | #include "standard-headers/asm-x86/hyperv.h" |
a2cb15b0 | 41 | #include "hw/pci/pci.h" |
68bfd0ad | 42 | #include "migration/migration.h" |
4c663752 | 43 | #include "exec/memattrs.h" |
05330448 AL |
44 | |
45 | //#define DEBUG_KVM | |
46 | ||
47 | #ifdef DEBUG_KVM | |
8c0d577e | 48 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
49 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
50 | #else | |
8c0d577e | 51 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
52 | do { } while (0) |
53 | #endif | |
54 | ||
1a03675d GC |
55 | #define MSR_KVM_WALL_CLOCK 0x11 |
56 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
57 | ||
c0532a76 MT |
58 | #ifndef BUS_MCEERR_AR |
59 | #define BUS_MCEERR_AR 4 | |
60 | #endif | |
61 | #ifndef BUS_MCEERR_AO | |
62 | #define BUS_MCEERR_AO 5 | |
63 | #endif | |
64 | ||
94a8d39a JK |
65 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
66 | KVM_CAP_INFO(SET_TSS_ADDR), | |
67 | KVM_CAP_INFO(EXT_CPUID), | |
68 | KVM_CAP_INFO(MP_STATE), | |
69 | KVM_CAP_LAST_INFO | |
70 | }; | |
25d2e361 | 71 | |
c3a3a7d3 JK |
72 | static bool has_msr_star; |
73 | static bool has_msr_hsave_pa; | |
c9b8f6b6 | 74 | static bool has_msr_tsc_aux; |
f28558d3 | 75 | static bool has_msr_tsc_adjust; |
aa82ba54 | 76 | static bool has_msr_tsc_deadline; |
df67696e | 77 | static bool has_msr_feature_control; |
c5999bfc | 78 | static bool has_msr_async_pf_en; |
bc9a839d | 79 | static bool has_msr_pv_eoi_en; |
21e87c46 | 80 | static bool has_msr_misc_enable; |
fc12d72e | 81 | static bool has_msr_smbase; |
79e9ebeb | 82 | static bool has_msr_bndcfgs; |
917367aa | 83 | static bool has_msr_kvm_steal_time; |
25d2e361 | 84 | static int lm_capable_kernel; |
7bc3d711 PB |
85 | static bool has_msr_hv_hypercall; |
86 | static bool has_msr_hv_vapic; | |
48a5f3bc | 87 | static bool has_msr_hv_tsc; |
f2a53c9e | 88 | static bool has_msr_hv_crash; |
744b8a94 | 89 | static bool has_msr_hv_reset; |
8c145d7c | 90 | static bool has_msr_hv_vpindex; |
46eb8f98 | 91 | static bool has_msr_hv_runtime; |
866eea9a | 92 | static bool has_msr_hv_synic; |
d1ae67f6 | 93 | static bool has_msr_mtrr; |
18cd2c17 | 94 | static bool has_msr_xss; |
b827df58 | 95 | |
0d894367 PB |
96 | static bool has_msr_architectural_pmu; |
97 | static uint32_t num_architectural_pmu_counters; | |
98 | ||
28143b40 TH |
99 | static int has_xsave; |
100 | static int has_xcrs; | |
101 | static int has_pit_state2; | |
102 | ||
103 | int kvm_has_pit_state2(void) | |
104 | { | |
105 | return has_pit_state2; | |
106 | } | |
107 | ||
355023f2 PB |
108 | bool kvm_has_smm(void) |
109 | { | |
110 | return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM); | |
111 | } | |
112 | ||
1d31f66b PM |
113 | bool kvm_allows_irq0_override(void) |
114 | { | |
115 | return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing(); | |
116 | } | |
117 | ||
0fd7e098 LL |
118 | static int kvm_get_tsc(CPUState *cs) |
119 | { | |
120 | X86CPU *cpu = X86_CPU(cs); | |
121 | CPUX86State *env = &cpu->env; | |
122 | struct { | |
123 | struct kvm_msrs info; | |
124 | struct kvm_msr_entry entries[1]; | |
125 | } msr_data; | |
126 | int ret; | |
127 | ||
128 | if (env->tsc_valid) { | |
129 | return 0; | |
130 | } | |
131 | ||
132 | msr_data.info.nmsrs = 1; | |
133 | msr_data.entries[0].index = MSR_IA32_TSC; | |
134 | env->tsc_valid = !runstate_is_running(); | |
135 | ||
136 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); | |
137 | if (ret < 0) { | |
138 | return ret; | |
139 | } | |
140 | ||
141 | env->tsc = msr_data.entries[0].data; | |
142 | return 0; | |
143 | } | |
144 | ||
145 | static inline void do_kvm_synchronize_tsc(void *arg) | |
146 | { | |
147 | CPUState *cpu = arg; | |
148 | ||
149 | kvm_get_tsc(cpu); | |
150 | } | |
151 | ||
152 | void kvm_synchronize_all_tsc(void) | |
153 | { | |
154 | CPUState *cpu; | |
155 | ||
156 | if (kvm_enabled()) { | |
157 | CPU_FOREACH(cpu) { | |
158 | run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu); | |
159 | } | |
160 | } | |
161 | } | |
162 | ||
b827df58 AK |
163 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
164 | { | |
165 | struct kvm_cpuid2 *cpuid; | |
166 | int r, size; | |
167 | ||
168 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
e42a92ae | 169 | cpuid = g_malloc0(size); |
b827df58 AK |
170 | cpuid->nent = max; |
171 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
172 | if (r == 0 && cpuid->nent >= max) { |
173 | r = -E2BIG; | |
174 | } | |
b827df58 AK |
175 | if (r < 0) { |
176 | if (r == -E2BIG) { | |
7267c094 | 177 | g_free(cpuid); |
b827df58 AK |
178 | return NULL; |
179 | } else { | |
180 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
181 | strerror(-r)); | |
182 | exit(1); | |
183 | } | |
184 | } | |
185 | return cpuid; | |
186 | } | |
187 | ||
dd87f8a6 EH |
188 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough |
189 | * for all entries. | |
190 | */ | |
191 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
192 | { | |
193 | struct kvm_cpuid2 *cpuid; | |
194 | int max = 1; | |
195 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { | |
196 | max *= 2; | |
197 | } | |
198 | return cpuid; | |
199 | } | |
200 | ||
a443bc34 | 201 | static const struct kvm_para_features { |
0c31b744 GC |
202 | int cap; |
203 | int feature; | |
204 | } para_features[] = { | |
205 | { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, | |
206 | { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, | |
207 | { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, | |
0c31b744 | 208 | { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
0c31b744 GC |
209 | }; |
210 | ||
ba9bc59e | 211 | static int get_para_features(KVMState *s) |
0c31b744 GC |
212 | { |
213 | int i, features = 0; | |
214 | ||
8e03c100 | 215 | for (i = 0; i < ARRAY_SIZE(para_features); i++) { |
ba9bc59e | 216 | if (kvm_check_extension(s, para_features[i].cap)) { |
0c31b744 GC |
217 | features |= (1 << para_features[i].feature); |
218 | } | |
219 | } | |
220 | ||
221 | return features; | |
222 | } | |
0c31b744 GC |
223 | |
224 | ||
829ae2f9 EH |
225 | /* Returns the value for a specific register on the cpuid entry |
226 | */ | |
227 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
228 | { | |
229 | uint32_t ret = 0; | |
230 | switch (reg) { | |
231 | case R_EAX: | |
232 | ret = entry->eax; | |
233 | break; | |
234 | case R_EBX: | |
235 | ret = entry->ebx; | |
236 | break; | |
237 | case R_ECX: | |
238 | ret = entry->ecx; | |
239 | break; | |
240 | case R_EDX: | |
241 | ret = entry->edx; | |
242 | break; | |
243 | } | |
244 | return ret; | |
245 | } | |
246 | ||
4fb73f1d EH |
247 | /* Find matching entry for function/index on kvm_cpuid2 struct |
248 | */ | |
249 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
250 | uint32_t function, | |
251 | uint32_t index) | |
252 | { | |
253 | int i; | |
254 | for (i = 0; i < cpuid->nent; ++i) { | |
255 | if (cpuid->entries[i].function == function && | |
256 | cpuid->entries[i].index == index) { | |
257 | return &cpuid->entries[i]; | |
258 | } | |
259 | } | |
260 | /* not found: */ | |
261 | return NULL; | |
262 | } | |
263 | ||
ba9bc59e | 264 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 265 | uint32_t index, int reg) |
b827df58 AK |
266 | { |
267 | struct kvm_cpuid2 *cpuid; | |
b827df58 AK |
268 | uint32_t ret = 0; |
269 | uint32_t cpuid_1_edx; | |
8c723b79 | 270 | bool found = false; |
b827df58 | 271 | |
dd87f8a6 | 272 | cpuid = get_supported_cpuid(s); |
b827df58 | 273 | |
4fb73f1d EH |
274 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); |
275 | if (entry) { | |
276 | found = true; | |
277 | ret = cpuid_entry_get_reg(entry, reg); | |
b827df58 AK |
278 | } |
279 | ||
7b46e5ce EH |
280 | /* Fixups for the data returned by KVM, below */ |
281 | ||
c2acb022 EH |
282 | if (function == 1 && reg == R_EDX) { |
283 | /* KVM before 2.6.30 misreports the following features */ | |
284 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
84bd945c EH |
285 | } else if (function == 1 && reg == R_ECX) { |
286 | /* We can set the hypervisor flag, even if KVM does not return it on | |
287 | * GET_SUPPORTED_CPUID | |
288 | */ | |
289 | ret |= CPUID_EXT_HYPERVISOR; | |
ac67ee26 EH |
290 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it |
291 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
292 | * and the irqchip is in the kernel. | |
293 | */ | |
294 | if (kvm_irqchip_in_kernel() && | |
295 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
296 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
297 | } | |
41e5e76d EH |
298 | |
299 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
300 | * without the in-kernel irqchip | |
301 | */ | |
302 | if (!kvm_irqchip_in_kernel()) { | |
303 | ret &= ~CPUID_EXT_X2APIC; | |
b827df58 | 304 | } |
28b8e4d0 JK |
305 | } else if (function == 6 && reg == R_EAX) { |
306 | ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ | |
c2acb022 EH |
307 | } else if (function == 0x80000001 && reg == R_EDX) { |
308 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
309 | * so add missing bits according to the AMD spec: | |
310 | */ | |
311 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
312 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
b827df58 AK |
313 | } |
314 | ||
7267c094 | 315 | g_free(cpuid); |
b827df58 | 316 | |
0c31b744 | 317 | /* fallback for older kernels */ |
8c723b79 | 318 | if ((function == KVM_CPUID_FEATURES) && !found) { |
ba9bc59e | 319 | ret = get_para_features(s); |
b9bec74b | 320 | } |
0c31b744 GC |
321 | |
322 | return ret; | |
bb0300dc | 323 | } |
bb0300dc | 324 | |
3c85e74f HY |
325 | typedef struct HWPoisonPage { |
326 | ram_addr_t ram_addr; | |
327 | QLIST_ENTRY(HWPoisonPage) list; | |
328 | } HWPoisonPage; | |
329 | ||
330 | static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = | |
331 | QLIST_HEAD_INITIALIZER(hwpoison_page_list); | |
332 | ||
333 | static void kvm_unpoison_all(void *param) | |
334 | { | |
335 | HWPoisonPage *page, *next_page; | |
336 | ||
337 | QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { | |
338 | QLIST_REMOVE(page, list); | |
339 | qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); | |
7267c094 | 340 | g_free(page); |
3c85e74f HY |
341 | } |
342 | } | |
343 | ||
3c85e74f HY |
344 | static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
345 | { | |
346 | HWPoisonPage *page; | |
347 | ||
348 | QLIST_FOREACH(page, &hwpoison_page_list, list) { | |
349 | if (page->ram_addr == ram_addr) { | |
350 | return; | |
351 | } | |
352 | } | |
ab3ad07f | 353 | page = g_new(HWPoisonPage, 1); |
3c85e74f HY |
354 | page->ram_addr = ram_addr; |
355 | QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); | |
356 | } | |
357 | ||
e7701825 MT |
358 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
359 | int *max_banks) | |
360 | { | |
361 | int r; | |
362 | ||
14a09518 | 363 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
364 | if (r > 0) { |
365 | *max_banks = r; | |
366 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
367 | } | |
368 | return -ENOSYS; | |
369 | } | |
370 | ||
bee615d4 | 371 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) |
e7701825 | 372 | { |
bee615d4 | 373 | CPUX86State *env = &cpu->env; |
c34d440a JK |
374 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
375 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
376 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
e7701825 | 377 | |
c34d440a JK |
378 | if (code == BUS_MCEERR_AR) { |
379 | status |= MCI_STATUS_AR | 0x134; | |
380 | mcg_status |= MCG_STATUS_EIPV; | |
381 | } else { | |
382 | status |= 0xc0; | |
383 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 384 | } |
8c5cf3b6 | 385 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, |
c34d440a JK |
386 | (MCM_ADDR_PHYS << 6) | 0xc, |
387 | cpu_x86_support_mca_broadcast(env) ? | |
388 | MCE_INJECT_BROADCAST : 0); | |
419fb20a | 389 | } |
419fb20a JK |
390 | |
391 | static void hardware_memory_error(void) | |
392 | { | |
393 | fprintf(stderr, "Hardware memory error!\n"); | |
394 | exit(1); | |
395 | } | |
396 | ||
20d695a9 | 397 | int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) |
419fb20a | 398 | { |
20d695a9 AF |
399 | X86CPU *cpu = X86_CPU(c); |
400 | CPUX86State *env = &cpu->env; | |
419fb20a | 401 | ram_addr_t ram_addr; |
a8170e5e | 402 | hwaddr paddr; |
419fb20a JK |
403 | |
404 | if ((env->mcg_cap & MCG_SER_P) && addr | |
c34d440a | 405 | && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
1b5ec234 | 406 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
a60f24b5 | 407 | !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { |
419fb20a JK |
408 | fprintf(stderr, "Hardware memory error for memory used by " |
409 | "QEMU itself instead of guest system!\n"); | |
410 | /* Hope we are lucky for AO MCE */ | |
411 | if (code == BUS_MCEERR_AO) { | |
412 | return 0; | |
413 | } else { | |
414 | hardware_memory_error(); | |
415 | } | |
416 | } | |
3c85e74f | 417 | kvm_hwpoison_page_add(ram_addr); |
bee615d4 | 418 | kvm_mce_inject(cpu, paddr, code); |
e56ff191 | 419 | } else { |
419fb20a JK |
420 | if (code == BUS_MCEERR_AO) { |
421 | return 0; | |
422 | } else if (code == BUS_MCEERR_AR) { | |
423 | hardware_memory_error(); | |
424 | } else { | |
425 | return 1; | |
426 | } | |
427 | } | |
428 | return 0; | |
429 | } | |
430 | ||
431 | int kvm_arch_on_sigbus(int code, void *addr) | |
432 | { | |
182735ef AF |
433 | X86CPU *cpu = X86_CPU(first_cpu); |
434 | ||
435 | if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) { | |
419fb20a | 436 | ram_addr_t ram_addr; |
a8170e5e | 437 | hwaddr paddr; |
419fb20a JK |
438 | |
439 | /* Hope we are lucky for AO MCE */ | |
1b5ec234 | 440 | if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL || |
182735ef | 441 | !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, |
a60f24b5 | 442 | addr, &paddr)) { |
419fb20a JK |
443 | fprintf(stderr, "Hardware memory error for memory used by " |
444 | "QEMU itself instead of guest system!: %p\n", addr); | |
445 | return 0; | |
446 | } | |
3c85e74f | 447 | kvm_hwpoison_page_add(ram_addr); |
182735ef | 448 | kvm_mce_inject(X86_CPU(first_cpu), paddr, code); |
e56ff191 | 449 | } else { |
419fb20a JK |
450 | if (code == BUS_MCEERR_AO) { |
451 | return 0; | |
452 | } else if (code == BUS_MCEERR_AR) { | |
453 | hardware_memory_error(); | |
454 | } else { | |
455 | return 1; | |
456 | } | |
457 | } | |
458 | return 0; | |
459 | } | |
e7701825 | 460 | |
1bc22652 | 461 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) |
ab443475 | 462 | { |
1bc22652 AF |
463 | CPUX86State *env = &cpu->env; |
464 | ||
ab443475 JK |
465 | if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) { |
466 | unsigned int bank, bank_num = env->mcg_cap & 0xff; | |
467 | struct kvm_x86_mce mce; | |
468 | ||
469 | env->exception_injected = -1; | |
470 | ||
471 | /* | |
472 | * There must be at least one bank in use if an MCE is pending. | |
473 | * Find it and use its values for the event injection. | |
474 | */ | |
475 | for (bank = 0; bank < bank_num; bank++) { | |
476 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
477 | break; | |
478 | } | |
479 | } | |
480 | assert(bank < bank_num); | |
481 | ||
482 | mce.bank = bank; | |
483 | mce.status = env->mce_banks[bank * 4 + 1]; | |
484 | mce.mcg_status = env->mcg_status; | |
485 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
486 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
487 | ||
1bc22652 | 488 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); |
ab443475 | 489 | } |
ab443475 JK |
490 | return 0; |
491 | } | |
492 | ||
1dfb4dd9 | 493 | static void cpu_update_state(void *opaque, int running, RunState state) |
b8cc45d6 | 494 | { |
317ac620 | 495 | CPUX86State *env = opaque; |
b8cc45d6 GC |
496 | |
497 | if (running) { | |
498 | env->tsc_valid = false; | |
499 | } | |
500 | } | |
501 | ||
83b17af5 | 502 | unsigned long kvm_arch_vcpu_id(CPUState *cs) |
b164e48e | 503 | { |
83b17af5 | 504 | X86CPU *cpu = X86_CPU(cs); |
7e72a45c | 505 | return cpu->apic_id; |
b164e48e EH |
506 | } |
507 | ||
92067bf4 IM |
508 | #ifndef KVM_CPUID_SIGNATURE_NEXT |
509 | #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 | |
510 | #endif | |
511 | ||
512 | static bool hyperv_hypercall_available(X86CPU *cpu) | |
513 | { | |
514 | return cpu->hyperv_vapic || | |
515 | (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY); | |
516 | } | |
517 | ||
518 | static bool hyperv_enabled(X86CPU *cpu) | |
519 | { | |
7bc3d711 PB |
520 | CPUState *cs = CPU(cpu); |
521 | return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 && | |
522 | (hyperv_hypercall_available(cpu) || | |
48a5f3bc | 523 | cpu->hyperv_time || |
f2a53c9e | 524 | cpu->hyperv_relaxed_timing || |
744b8a94 | 525 | cpu->hyperv_crash || |
8c145d7c | 526 | cpu->hyperv_reset || |
46eb8f98 | 527 | cpu->hyperv_vpindex || |
866eea9a AS |
528 | cpu->hyperv_runtime || |
529 | cpu->hyperv_synic); | |
92067bf4 IM |
530 | } |
531 | ||
68bfd0ad MT |
532 | static Error *invtsc_mig_blocker; |
533 | ||
f8bb0565 | 534 | #define KVM_MAX_CPUID_ENTRIES 100 |
0893d460 | 535 | |
20d695a9 | 536 | int kvm_arch_init_vcpu(CPUState *cs) |
05330448 AL |
537 | { |
538 | struct { | |
486bd5a2 | 539 | struct kvm_cpuid2 cpuid; |
f8bb0565 | 540 | struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; |
541dc0d4 | 541 | } QEMU_PACKED cpuid_data; |
20d695a9 AF |
542 | X86CPU *cpu = X86_CPU(cs); |
543 | CPUX86State *env = &cpu->env; | |
486bd5a2 | 544 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 545 | uint32_t unused; |
bb0300dc | 546 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 547 | uint32_t signature[3]; |
234cc647 | 548 | int kvm_base = KVM_CPUID_SIGNATURE; |
e7429073 | 549 | int r; |
05330448 | 550 | |
ef4cbe14 SW |
551 | memset(&cpuid_data, 0, sizeof(cpuid_data)); |
552 | ||
05330448 AL |
553 | cpuid_i = 0; |
554 | ||
bb0300dc | 555 | /* Paravirtualization CPUIDs */ |
234cc647 PB |
556 | if (hyperv_enabled(cpu)) { |
557 | c = &cpuid_data.entries[cpuid_i++]; | |
558 | c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; | |
1c4a55db AW |
559 | if (!cpu->hyperv_vendor_id) { |
560 | memcpy(signature, "Microsoft Hv", 12); | |
561 | } else { | |
562 | size_t len = strlen(cpu->hyperv_vendor_id); | |
563 | ||
564 | if (len > 12) { | |
565 | error_report("hv-vendor-id truncated to 12 characters"); | |
566 | len = 12; | |
567 | } | |
568 | memset(signature, 0, 12); | |
569 | memcpy(signature, cpu->hyperv_vendor_id, len); | |
570 | } | |
eab70139 | 571 | c->eax = HYPERV_CPUID_MIN; |
234cc647 PB |
572 | c->ebx = signature[0]; |
573 | c->ecx = signature[1]; | |
574 | c->edx = signature[2]; | |
0c31b744 | 575 | |
234cc647 PB |
576 | c = &cpuid_data.entries[cpuid_i++]; |
577 | c->function = HYPERV_CPUID_INTERFACE; | |
eab70139 VR |
578 | memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); |
579 | c->eax = signature[0]; | |
234cc647 PB |
580 | c->ebx = 0; |
581 | c->ecx = 0; | |
582 | c->edx = 0; | |
eab70139 VR |
583 | |
584 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 VR |
585 | c->function = HYPERV_CPUID_VERSION; |
586 | c->eax = 0x00001bbc; | |
587 | c->ebx = 0x00060001; | |
588 | ||
589 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 | 590 | c->function = HYPERV_CPUID_FEATURES; |
92067bf4 | 591 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
592 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
593 | } | |
92067bf4 | 594 | if (cpu->hyperv_vapic) { |
eab70139 VR |
595 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
596 | c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; | |
7bc3d711 | 597 | has_msr_hv_vapic = true; |
eab70139 | 598 | } |
48a5f3bc VR |
599 | if (cpu->hyperv_time && |
600 | kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { | |
601 | c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; | |
602 | c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE; | |
603 | c->eax |= 0x200; | |
604 | has_msr_hv_tsc = true; | |
605 | } | |
f2a53c9e AS |
606 | if (cpu->hyperv_crash && has_msr_hv_crash) { |
607 | c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE; | |
608 | } | |
744b8a94 AS |
609 | if (cpu->hyperv_reset && has_msr_hv_reset) { |
610 | c->eax |= HV_X64_MSR_RESET_AVAILABLE; | |
611 | } | |
8c145d7c AS |
612 | if (cpu->hyperv_vpindex && has_msr_hv_vpindex) { |
613 | c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE; | |
614 | } | |
46eb8f98 AS |
615 | if (cpu->hyperv_runtime && has_msr_hv_runtime) { |
616 | c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE; | |
617 | } | |
866eea9a AS |
618 | if (cpu->hyperv_synic) { |
619 | int sint; | |
620 | ||
621 | if (!has_msr_hv_synic || | |
622 | kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) { | |
623 | fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n"); | |
624 | return -ENOSYS; | |
625 | } | |
626 | ||
627 | c->eax |= HV_X64_MSR_SYNIC_AVAILABLE; | |
628 | env->msr_hv_synic_version = HV_SYNIC_VERSION_1; | |
629 | for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) { | |
630 | env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED; | |
631 | } | |
632 | } | |
eab70139 | 633 | c = &cpuid_data.entries[cpuid_i++]; |
eab70139 | 634 | c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; |
92067bf4 | 635 | if (cpu->hyperv_relaxed_timing) { |
eab70139 VR |
636 | c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; |
637 | } | |
7bc3d711 | 638 | if (has_msr_hv_vapic) { |
eab70139 VR |
639 | c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; |
640 | } | |
92067bf4 | 641 | c->ebx = cpu->hyperv_spinlock_attempts; |
eab70139 VR |
642 | |
643 | c = &cpuid_data.entries[cpuid_i++]; | |
eab70139 VR |
644 | c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; |
645 | c->eax = 0x40; | |
646 | c->ebx = 0x40; | |
647 | ||
234cc647 | 648 | kvm_base = KVM_CPUID_SIGNATURE_NEXT; |
7bc3d711 | 649 | has_msr_hv_hypercall = true; |
eab70139 VR |
650 | } |
651 | ||
f522d2ac AW |
652 | if (cpu->expose_kvm) { |
653 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
654 | c = &cpuid_data.entries[cpuid_i++]; | |
655 | c->function = KVM_CPUID_SIGNATURE | kvm_base; | |
79b6f2f6 | 656 | c->eax = KVM_CPUID_FEATURES | kvm_base; |
f522d2ac AW |
657 | c->ebx = signature[0]; |
658 | c->ecx = signature[1]; | |
659 | c->edx = signature[2]; | |
234cc647 | 660 | |
f522d2ac AW |
661 | c = &cpuid_data.entries[cpuid_i++]; |
662 | c->function = KVM_CPUID_FEATURES | kvm_base; | |
663 | c->eax = env->features[FEAT_KVM]; | |
234cc647 | 664 | |
f522d2ac | 665 | has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF); |
bb0300dc | 666 | |
f522d2ac | 667 | has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI); |
bc9a839d | 668 | |
f522d2ac AW |
669 | has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME); |
670 | } | |
917367aa | 671 | |
a33609ca | 672 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
673 | |
674 | for (i = 0; i <= limit; i++) { | |
f8bb0565 IM |
675 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
676 | fprintf(stderr, "unsupported level value: 0x%x\n", limit); | |
677 | abort(); | |
678 | } | |
bb0300dc | 679 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
680 | |
681 | switch (i) { | |
a36b1029 AL |
682 | case 2: { |
683 | /* Keep reading function 2 till all the input is received */ | |
684 | int times; | |
685 | ||
a36b1029 | 686 | c->function = i; |
a33609ca AL |
687 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
688 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
689 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
690 | times = c->eax & 0xff; | |
a36b1029 AL |
691 | |
692 | for (j = 1; j < times; ++j) { | |
f8bb0565 IM |
693 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
694 | fprintf(stderr, "cpuid_data is full, no space for " | |
695 | "cpuid(eax:2):eax & 0xf = 0x%x\n", times); | |
696 | abort(); | |
697 | } | |
a33609ca | 698 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 699 | c->function = i; |
a33609ca AL |
700 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
701 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
702 | } |
703 | break; | |
704 | } | |
486bd5a2 AL |
705 | case 4: |
706 | case 0xb: | |
707 | case 0xd: | |
708 | for (j = 0; ; j++) { | |
31e8c696 AP |
709 | if (i == 0xd && j == 64) { |
710 | break; | |
711 | } | |
486bd5a2 AL |
712 | c->function = i; |
713 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
714 | c->index = j; | |
a33609ca | 715 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 716 | |
b9bec74b | 717 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 718 | break; |
b9bec74b JK |
719 | } |
720 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 721 | break; |
b9bec74b JK |
722 | } |
723 | if (i == 0xd && c->eax == 0) { | |
31e8c696 | 724 | continue; |
b9bec74b | 725 | } |
f8bb0565 IM |
726 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
727 | fprintf(stderr, "cpuid_data is full, no space for " | |
728 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
729 | abort(); | |
730 | } | |
a33609ca | 731 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
732 | } |
733 | break; | |
734 | default: | |
486bd5a2 | 735 | c->function = i; |
a33609ca AL |
736 | c->flags = 0; |
737 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
486bd5a2 AL |
738 | break; |
739 | } | |
05330448 | 740 | } |
0d894367 PB |
741 | |
742 | if (limit >= 0x0a) { | |
743 | uint32_t ver; | |
744 | ||
745 | cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused); | |
746 | if ((ver & 0xff) > 0) { | |
747 | has_msr_architectural_pmu = true; | |
748 | num_architectural_pmu_counters = (ver & 0xff00) >> 8; | |
749 | ||
750 | /* Shouldn't be more than 32, since that's the number of bits | |
751 | * available in EBX to tell us _which_ counters are available. | |
752 | * Play it safe. | |
753 | */ | |
754 | if (num_architectural_pmu_counters > MAX_GP_COUNTERS) { | |
755 | num_architectural_pmu_counters = MAX_GP_COUNTERS; | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
a33609ca | 760 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
761 | |
762 | for (i = 0x80000000; i <= limit; i++) { | |
f8bb0565 IM |
763 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
764 | fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); | |
765 | abort(); | |
766 | } | |
bb0300dc | 767 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 768 | |
05330448 | 769 | c->function = i; |
a33609ca AL |
770 | c->flags = 0; |
771 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
05330448 AL |
772 | } |
773 | ||
b3baa152 BW |
774 | /* Call Centaur's CPUID instructions they are supported. */ |
775 | if (env->cpuid_xlevel2 > 0) { | |
b3baa152 BW |
776 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
777 | ||
778 | for (i = 0xC0000000; i <= limit; i++) { | |
f8bb0565 IM |
779 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
780 | fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); | |
781 | abort(); | |
782 | } | |
b3baa152 BW |
783 | c = &cpuid_data.entries[cpuid_i++]; |
784 | ||
785 | c->function = i; | |
786 | c->flags = 0; | |
787 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
788 | } | |
789 | } | |
790 | ||
05330448 AL |
791 | cpuid_data.cpuid.nent = cpuid_i; |
792 | ||
e7701825 | 793 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
0514ef2f | 794 | && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == |
fc7a504c | 795 | (CPUID_MCE | CPUID_MCA) |
a60f24b5 | 796 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { |
5120901a | 797 | uint64_t mcg_cap, unsupported_caps; |
e7701825 | 798 | int banks; |
32a42024 | 799 | int ret; |
e7701825 | 800 | |
a60f24b5 | 801 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); |
75d49497 JK |
802 | if (ret < 0) { |
803 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
804 | return ret; | |
e7701825 | 805 | } |
75d49497 | 806 | |
2590f15b | 807 | if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { |
49b69cbf | 808 | error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)", |
2590f15b | 809 | (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); |
49b69cbf | 810 | return -ENOTSUP; |
75d49497 | 811 | } |
49b69cbf | 812 | |
5120901a EH |
813 | unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK); |
814 | if (unsupported_caps) { | |
815 | error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64, | |
816 | unsupported_caps); | |
817 | } | |
818 | ||
2590f15b EH |
819 | env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK; |
820 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); | |
75d49497 JK |
821 | if (ret < 0) { |
822 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
823 | return ret; | |
824 | } | |
e7701825 | 825 | } |
e7701825 | 826 | |
b8cc45d6 GC |
827 | qemu_add_vm_change_state_handler(cpu_update_state, env); |
828 | ||
df67696e LJ |
829 | c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); |
830 | if (c) { | |
831 | has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || | |
832 | !!(c->ecx & CPUID_EXT_SMX); | |
833 | } | |
834 | ||
68bfd0ad MT |
835 | c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0); |
836 | if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) { | |
837 | /* for migration */ | |
838 | error_setg(&invtsc_mig_blocker, | |
839 | "State blocked by non-migratable CPU device" | |
840 | " (invtsc flag)"); | |
841 | migrate_add_blocker(invtsc_mig_blocker); | |
842 | /* for savevm */ | |
843 | vmstate_x86_cpu.unmigratable = 1; | |
844 | } | |
845 | ||
7e680753 | 846 | cpuid_data.cpuid.padding = 0; |
1bc22652 | 847 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); |
fdc9c41a JK |
848 | if (r) { |
849 | return r; | |
850 | } | |
e7429073 | 851 | |
a60f24b5 | 852 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL); |
e7429073 | 853 | if (r && env->tsc_khz) { |
1bc22652 | 854 | r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz); |
e7429073 JR |
855 | if (r < 0) { |
856 | fprintf(stderr, "KVM_SET_TSC_KHZ failed\n"); | |
857 | return r; | |
858 | } | |
859 | } | |
e7429073 | 860 | |
28143b40 | 861 | if (has_xsave) { |
fabacc0f JK |
862 | env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); |
863 | } | |
864 | ||
d1ae67f6 AW |
865 | if (env->features[FEAT_1_EDX] & CPUID_MTRR) { |
866 | has_msr_mtrr = true; | |
867 | } | |
868 | ||
e7429073 | 869 | return 0; |
05330448 AL |
870 | } |
871 | ||
50a2c6e5 | 872 | void kvm_arch_reset_vcpu(X86CPU *cpu) |
caa5af0f | 873 | { |
20d695a9 | 874 | CPUX86State *env = &cpu->env; |
dd673288 | 875 | |
e73223a5 | 876 | env->exception_injected = -1; |
0e607a80 | 877 | env->interrupt_injected = -1; |
1a5e9d2f | 878 | env->xcr0 = 1; |
ddced198 | 879 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 880 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
881 | KVM_MP_STATE_UNINITIALIZED; |
882 | } else { | |
883 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
884 | } | |
caa5af0f JK |
885 | } |
886 | ||
e0723c45 PB |
887 | void kvm_arch_do_init_vcpu(X86CPU *cpu) |
888 | { | |
889 | CPUX86State *env = &cpu->env; | |
890 | ||
891 | /* APs get directly into wait-for-SIPI state. */ | |
892 | if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { | |
893 | env->mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
894 | } | |
895 | } | |
896 | ||
c3a3a7d3 | 897 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 898 | { |
75b10c43 | 899 | static int kvm_supported_msrs; |
c3a3a7d3 | 900 | int ret = 0; |
05330448 AL |
901 | |
902 | /* first time */ | |
75b10c43 | 903 | if (kvm_supported_msrs == 0) { |
05330448 AL |
904 | struct kvm_msr_list msr_list, *kvm_msr_list; |
905 | ||
75b10c43 | 906 | kvm_supported_msrs = -1; |
05330448 AL |
907 | |
908 | /* Obtain MSR list from KVM. These are the MSRs that we must | |
909 | * save/restore */ | |
4c9f7372 | 910 | msr_list.nmsrs = 0; |
c3a3a7d3 | 911 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
6fb6d245 | 912 | if (ret < 0 && ret != -E2BIG) { |
c3a3a7d3 | 913 | return ret; |
6fb6d245 | 914 | } |
d9db889f JK |
915 | /* Old kernel modules had a bug and could write beyond the provided |
916 | memory. Allocate at least a safe amount of 1K. */ | |
7267c094 | 917 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
d9db889f JK |
918 | msr_list.nmsrs * |
919 | sizeof(msr_list.indices[0]))); | |
05330448 | 920 | |
55308450 | 921 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
c3a3a7d3 | 922 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
05330448 AL |
923 | if (ret >= 0) { |
924 | int i; | |
925 | ||
926 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { | |
927 | if (kvm_msr_list->indices[i] == MSR_STAR) { | |
c3a3a7d3 | 928 | has_msr_star = true; |
75b10c43 MT |
929 | continue; |
930 | } | |
931 | if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) { | |
c3a3a7d3 | 932 | has_msr_hsave_pa = true; |
75b10c43 | 933 | continue; |
05330448 | 934 | } |
c9b8f6b6 AS |
935 | if (kvm_msr_list->indices[i] == MSR_TSC_AUX) { |
936 | has_msr_tsc_aux = true; | |
937 | continue; | |
938 | } | |
f28558d3 WA |
939 | if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { |
940 | has_msr_tsc_adjust = true; | |
941 | continue; | |
942 | } | |
aa82ba54 LJ |
943 | if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { |
944 | has_msr_tsc_deadline = true; | |
945 | continue; | |
946 | } | |
fc12d72e PB |
947 | if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) { |
948 | has_msr_smbase = true; | |
949 | continue; | |
950 | } | |
21e87c46 AK |
951 | if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) { |
952 | has_msr_misc_enable = true; | |
953 | continue; | |
954 | } | |
79e9ebeb LJ |
955 | if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) { |
956 | has_msr_bndcfgs = true; | |
957 | continue; | |
958 | } | |
18cd2c17 WL |
959 | if (kvm_msr_list->indices[i] == MSR_IA32_XSS) { |
960 | has_msr_xss = true; | |
961 | continue; | |
962 | } | |
f2a53c9e AS |
963 | if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) { |
964 | has_msr_hv_crash = true; | |
965 | continue; | |
966 | } | |
744b8a94 AS |
967 | if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) { |
968 | has_msr_hv_reset = true; | |
969 | continue; | |
970 | } | |
8c145d7c AS |
971 | if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) { |
972 | has_msr_hv_vpindex = true; | |
973 | continue; | |
974 | } | |
46eb8f98 AS |
975 | if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) { |
976 | has_msr_hv_runtime = true; | |
977 | continue; | |
978 | } | |
866eea9a AS |
979 | if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) { |
980 | has_msr_hv_synic = true; | |
981 | continue; | |
982 | } | |
05330448 AL |
983 | } |
984 | } | |
985 | ||
7267c094 | 986 | g_free(kvm_msr_list); |
05330448 AL |
987 | } |
988 | ||
c3a3a7d3 | 989 | return ret; |
05330448 AL |
990 | } |
991 | ||
6410848b PB |
992 | static Notifier smram_machine_done; |
993 | static KVMMemoryListener smram_listener; | |
994 | static AddressSpace smram_address_space; | |
995 | static MemoryRegion smram_as_root; | |
996 | static MemoryRegion smram_as_mem; | |
997 | ||
998 | static void register_smram_listener(Notifier *n, void *unused) | |
999 | { | |
1000 | MemoryRegion *smram = | |
1001 | (MemoryRegion *) object_resolve_path("/machine/smram", NULL); | |
1002 | ||
1003 | /* Outer container... */ | |
1004 | memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull); | |
1005 | memory_region_set_enabled(&smram_as_root, true); | |
1006 | ||
1007 | /* ... with two regions inside: normal system memory with low | |
1008 | * priority, and... | |
1009 | */ | |
1010 | memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram", | |
1011 | get_system_memory(), 0, ~0ull); | |
1012 | memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0); | |
1013 | memory_region_set_enabled(&smram_as_mem, true); | |
1014 | ||
1015 | if (smram) { | |
1016 | /* ... SMRAM with higher priority */ | |
1017 | memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10); | |
1018 | memory_region_set_enabled(smram, true); | |
1019 | } | |
1020 | ||
1021 | address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM"); | |
1022 | kvm_memory_listener_register(kvm_state, &smram_listener, | |
1023 | &smram_address_space, 1); | |
1024 | } | |
1025 | ||
b16565b3 | 1026 | int kvm_arch_init(MachineState *ms, KVMState *s) |
20420430 | 1027 | { |
11076198 | 1028 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 1029 | uint64_t shadow_mem; |
20420430 | 1030 | int ret; |
25d2e361 | 1031 | struct utsname utsname; |
20420430 | 1032 | |
28143b40 TH |
1033 | #ifdef KVM_CAP_XSAVE |
1034 | has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE); | |
1035 | #endif | |
1036 | ||
1037 | #ifdef KVM_CAP_XCRS | |
1038 | has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS); | |
1039 | #endif | |
1040 | ||
1041 | #ifdef KVM_CAP_PIT_STATE2 | |
1042 | has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2); | |
1043 | #endif | |
1044 | ||
c3a3a7d3 | 1045 | ret = kvm_get_supported_msrs(s); |
20420430 | 1046 | if (ret < 0) { |
20420430 SY |
1047 | return ret; |
1048 | } | |
25d2e361 MT |
1049 | |
1050 | uname(&utsname); | |
1051 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
1052 | ||
4c5b10b7 | 1053 | /* |
11076198 JK |
1054 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
1055 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
1056 | * Since these must be part of guest physical memory, we need to allocate | |
1057 | * them, both by setting their start addresses in the kernel and by | |
1058 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
1059 | * | |
1060 | * Older KVM versions may not support setting the identity map base. In | |
1061 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
1062 | * size. | |
4c5b10b7 | 1063 | */ |
11076198 JK |
1064 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
1065 | /* Allows up to 16M BIOSes. */ | |
1066 | identity_base = 0xfeffc000; | |
1067 | ||
1068 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
1069 | if (ret < 0) { | |
1070 | return ret; | |
1071 | } | |
4c5b10b7 | 1072 | } |
e56ff191 | 1073 | |
11076198 JK |
1074 | /* Set TSS base one page after EPT identity map. */ |
1075 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
1076 | if (ret < 0) { |
1077 | return ret; | |
1078 | } | |
1079 | ||
11076198 JK |
1080 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
1081 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 1082 | if (ret < 0) { |
11076198 | 1083 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
1084 | return ret; |
1085 | } | |
3c85e74f | 1086 | qemu_register_reset(kvm_unpoison_all, NULL); |
20420430 | 1087 | |
4689b77b | 1088 | shadow_mem = machine_kvm_shadow_mem(ms); |
36ad0e94 MA |
1089 | if (shadow_mem != -1) { |
1090 | shadow_mem /= 4096; | |
1091 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
1092 | if (ret < 0) { | |
1093 | return ret; | |
39d6960a JK |
1094 | } |
1095 | } | |
6410848b PB |
1096 | |
1097 | if (kvm_check_extension(s, KVM_CAP_X86_SMM)) { | |
1098 | smram_machine_done.notify = register_smram_listener; | |
1099 | qemu_add_machine_init_done_notifier(&smram_machine_done); | |
1100 | } | |
11076198 | 1101 | return 0; |
05330448 | 1102 | } |
b9bec74b | 1103 | |
05330448 AL |
1104 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
1105 | { | |
1106 | lhs->selector = rhs->selector; | |
1107 | lhs->base = rhs->base; | |
1108 | lhs->limit = rhs->limit; | |
1109 | lhs->type = 3; | |
1110 | lhs->present = 1; | |
1111 | lhs->dpl = 3; | |
1112 | lhs->db = 0; | |
1113 | lhs->s = 1; | |
1114 | lhs->l = 0; | |
1115 | lhs->g = 0; | |
1116 | lhs->avl = 0; | |
1117 | lhs->unusable = 0; | |
1118 | } | |
1119 | ||
1120 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
1121 | { | |
1122 | unsigned flags = rhs->flags; | |
1123 | lhs->selector = rhs->selector; | |
1124 | lhs->base = rhs->base; | |
1125 | lhs->limit = rhs->limit; | |
1126 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
1127 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 1128 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
1129 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
1130 | lhs->s = (flags & DESC_S_MASK) != 0; | |
1131 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
1132 | lhs->g = (flags & DESC_G_MASK) != 0; | |
1133 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
1134 | lhs->unusable = 0; | |
7e680753 | 1135 | lhs->padding = 0; |
05330448 AL |
1136 | } |
1137 | ||
1138 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
1139 | { | |
1140 | lhs->selector = rhs->selector; | |
1141 | lhs->base = rhs->base; | |
1142 | lhs->limit = rhs->limit; | |
b9bec74b JK |
1143 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
1144 | (rhs->present * DESC_P_MASK) | | |
1145 | (rhs->dpl << DESC_DPL_SHIFT) | | |
1146 | (rhs->db << DESC_B_SHIFT) | | |
1147 | (rhs->s * DESC_S_MASK) | | |
1148 | (rhs->l << DESC_L_SHIFT) | | |
1149 | (rhs->g * DESC_G_MASK) | | |
1150 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
1151 | } |
1152 | ||
1153 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
1154 | { | |
b9bec74b | 1155 | if (set) { |
05330448 | 1156 | *kvm_reg = *qemu_reg; |
b9bec74b | 1157 | } else { |
05330448 | 1158 | *qemu_reg = *kvm_reg; |
b9bec74b | 1159 | } |
05330448 AL |
1160 | } |
1161 | ||
1bc22652 | 1162 | static int kvm_getput_regs(X86CPU *cpu, int set) |
05330448 | 1163 | { |
1bc22652 | 1164 | CPUX86State *env = &cpu->env; |
05330448 AL |
1165 | struct kvm_regs regs; |
1166 | int ret = 0; | |
1167 | ||
1168 | if (!set) { | |
1bc22652 | 1169 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); |
b9bec74b | 1170 | if (ret < 0) { |
05330448 | 1171 | return ret; |
b9bec74b | 1172 | } |
05330448 AL |
1173 | } |
1174 | ||
1175 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
1176 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
1177 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
1178 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
1179 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
1180 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
1181 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
1182 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
1183 | #ifdef TARGET_X86_64 | |
1184 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
1185 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
1186 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
1187 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
1188 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
1189 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
1190 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
1191 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
1192 | #endif | |
1193 | ||
1194 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
1195 | kvm_getput_reg(®s.rip, &env->eip, set); | |
1196 | ||
b9bec74b | 1197 | if (set) { |
1bc22652 | 1198 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); |
b9bec74b | 1199 | } |
05330448 AL |
1200 | |
1201 | return ret; | |
1202 | } | |
1203 | ||
1bc22652 | 1204 | static int kvm_put_fpu(X86CPU *cpu) |
05330448 | 1205 | { |
1bc22652 | 1206 | CPUX86State *env = &cpu->env; |
05330448 AL |
1207 | struct kvm_fpu fpu; |
1208 | int i; | |
1209 | ||
1210 | memset(&fpu, 0, sizeof fpu); | |
1211 | fpu.fsw = env->fpus & ~(7 << 11); | |
1212 | fpu.fsw |= (env->fpstt & 7) << 11; | |
1213 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
1214 | fpu.last_opcode = env->fpop; |
1215 | fpu.last_ip = env->fpip; | |
1216 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
1217 | for (i = 0; i < 8; ++i) { |
1218 | fpu.ftwx |= (!env->fptags[i]) << i; | |
1219 | } | |
05330448 | 1220 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
bee81887 PB |
1221 | for (i = 0; i < CPU_NB_REGS; i++) { |
1222 | stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0)); | |
1223 | stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1)); | |
1224 | } | |
05330448 AL |
1225 | fpu.mxcsr = env->mxcsr; |
1226 | ||
1bc22652 | 1227 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); |
05330448 AL |
1228 | } |
1229 | ||
6b42494b JK |
1230 | #define XSAVE_FCW_FSW 0 |
1231 | #define XSAVE_FTW_FOP 1 | |
f1665b21 SY |
1232 | #define XSAVE_CWD_RIP 2 |
1233 | #define XSAVE_CWD_RDP 4 | |
1234 | #define XSAVE_MXCSR 6 | |
1235 | #define XSAVE_ST_SPACE 8 | |
1236 | #define XSAVE_XMM_SPACE 40 | |
1237 | #define XSAVE_XSTATE_BV 128 | |
1238 | #define XSAVE_YMMH_SPACE 144 | |
79e9ebeb LJ |
1239 | #define XSAVE_BNDREGS 240 |
1240 | #define XSAVE_BNDCSR 256 | |
9aecd6f8 CP |
1241 | #define XSAVE_OPMASK 272 |
1242 | #define XSAVE_ZMM_Hi256 288 | |
1243 | #define XSAVE_Hi16_ZMM 416 | |
f1665b21 | 1244 | |
1bc22652 | 1245 | static int kvm_put_xsave(X86CPU *cpu) |
f1665b21 | 1246 | { |
1bc22652 | 1247 | CPUX86State *env = &cpu->env; |
fabacc0f | 1248 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
42cc8fa6 | 1249 | uint16_t cwd, swd, twd; |
b7711471 | 1250 | uint8_t *xmm, *ymmh, *zmmh; |
fabacc0f | 1251 | int i, r; |
f1665b21 | 1252 | |
28143b40 | 1253 | if (!has_xsave) { |
1bc22652 | 1254 | return kvm_put_fpu(cpu); |
b9bec74b | 1255 | } |
f1665b21 | 1256 | |
f1665b21 | 1257 | memset(xsave, 0, sizeof(struct kvm_xsave)); |
6115c0a8 | 1258 | twd = 0; |
f1665b21 SY |
1259 | swd = env->fpus & ~(7 << 11); |
1260 | swd |= (env->fpstt & 7) << 11; | |
1261 | cwd = env->fpuc; | |
b9bec74b | 1262 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1263 | twd |= (!env->fptags[i]) << i; |
b9bec74b | 1264 | } |
6b42494b JK |
1265 | xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd; |
1266 | xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd; | |
42cc8fa6 JK |
1267 | memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip)); |
1268 | memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp)); | |
f1665b21 SY |
1269 | memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
1270 | sizeof env->fpregs); | |
f1665b21 SY |
1271 | xsave->region[XSAVE_MXCSR] = env->mxcsr; |
1272 | *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; | |
79e9ebeb LJ |
1273 | memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs, |
1274 | sizeof env->bnd_regs); | |
1275 | memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs, | |
1276 | sizeof(env->bndcs_regs)); | |
9aecd6f8 CP |
1277 | memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs, |
1278 | sizeof env->opmask_regs); | |
bee81887 PB |
1279 | |
1280 | xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE]; | |
b7711471 PB |
1281 | ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE]; |
1282 | zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256]; | |
1283 | for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) { | |
bee81887 PB |
1284 | stq_p(xmm, env->xmm_regs[i].XMM_Q(0)); |
1285 | stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1)); | |
b7711471 PB |
1286 | stq_p(ymmh, env->xmm_regs[i].XMM_Q(2)); |
1287 | stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3)); | |
1288 | stq_p(zmmh, env->xmm_regs[i].XMM_Q(4)); | |
1289 | stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5)); | |
1290 | stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6)); | |
1291 | stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7)); | |
bee81887 PB |
1292 | } |
1293 | ||
9aecd6f8 | 1294 | #ifdef TARGET_X86_64 |
b7711471 PB |
1295 | memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16], |
1296 | 16 * sizeof env->xmm_regs[16]); | |
9aecd6f8 | 1297 | #endif |
1bc22652 | 1298 | r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); |
0f53994f | 1299 | return r; |
f1665b21 SY |
1300 | } |
1301 | ||
1bc22652 | 1302 | static int kvm_put_xcrs(X86CPU *cpu) |
f1665b21 | 1303 | { |
1bc22652 | 1304 | CPUX86State *env = &cpu->env; |
bdfc8480 | 1305 | struct kvm_xcrs xcrs = {}; |
f1665b21 | 1306 | |
28143b40 | 1307 | if (!has_xcrs) { |
f1665b21 | 1308 | return 0; |
b9bec74b | 1309 | } |
f1665b21 SY |
1310 | |
1311 | xcrs.nr_xcrs = 1; | |
1312 | xcrs.flags = 0; | |
1313 | xcrs.xcrs[0].xcr = 0; | |
1314 | xcrs.xcrs[0].value = env->xcr0; | |
1bc22652 | 1315 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); |
f1665b21 SY |
1316 | } |
1317 | ||
1bc22652 | 1318 | static int kvm_put_sregs(X86CPU *cpu) |
05330448 | 1319 | { |
1bc22652 | 1320 | CPUX86State *env = &cpu->env; |
05330448 AL |
1321 | struct kvm_sregs sregs; |
1322 | ||
0e607a80 JK |
1323 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
1324 | if (env->interrupt_injected >= 0) { | |
1325 | sregs.interrupt_bitmap[env->interrupt_injected / 64] |= | |
1326 | (uint64_t)1 << (env->interrupt_injected % 64); | |
1327 | } | |
05330448 AL |
1328 | |
1329 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
1330 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
1331 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
1332 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
1333 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
1334 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
1335 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 1336 | } else { |
b9bec74b JK |
1337 | set_seg(&sregs.cs, &env->segs[R_CS]); |
1338 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
1339 | set_seg(&sregs.es, &env->segs[R_ES]); | |
1340 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
1341 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
1342 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
1343 | } |
1344 | ||
1345 | set_seg(&sregs.tr, &env->tr); | |
1346 | set_seg(&sregs.ldt, &env->ldt); | |
1347 | ||
1348 | sregs.idt.limit = env->idt.limit; | |
1349 | sregs.idt.base = env->idt.base; | |
7e680753 | 1350 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
1351 | sregs.gdt.limit = env->gdt.limit; |
1352 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 1353 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
1354 | |
1355 | sregs.cr0 = env->cr[0]; | |
1356 | sregs.cr2 = env->cr[2]; | |
1357 | sregs.cr3 = env->cr[3]; | |
1358 | sregs.cr4 = env->cr[4]; | |
1359 | ||
02e51483 CF |
1360 | sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); |
1361 | sregs.apic_base = cpu_get_apic_base(cpu->apic_state); | |
05330448 AL |
1362 | |
1363 | sregs.efer = env->efer; | |
1364 | ||
1bc22652 | 1365 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); |
05330448 AL |
1366 | } |
1367 | ||
1368 | static void kvm_msr_entry_set(struct kvm_msr_entry *entry, | |
1369 | uint32_t index, uint64_t value) | |
1370 | { | |
1371 | entry->index = index; | |
c7fe4b12 | 1372 | entry->reserved = 0; |
05330448 AL |
1373 | entry->data = value; |
1374 | } | |
1375 | ||
7477cd38 MT |
1376 | static int kvm_put_tscdeadline_msr(X86CPU *cpu) |
1377 | { | |
1378 | CPUX86State *env = &cpu->env; | |
1379 | struct { | |
1380 | struct kvm_msrs info; | |
1381 | struct kvm_msr_entry entries[1]; | |
1382 | } msr_data; | |
1383 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1384 | ||
1385 | if (!has_msr_tsc_deadline) { | |
1386 | return 0; | |
1387 | } | |
1388 | ||
1389 | kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); | |
1390 | ||
c7fe4b12 CB |
1391 | msr_data.info = (struct kvm_msrs) { |
1392 | .nmsrs = 1, | |
1393 | }; | |
7477cd38 MT |
1394 | |
1395 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); | |
1396 | } | |
1397 | ||
6bdf863d JK |
1398 | /* |
1399 | * Provide a separate write service for the feature control MSR in order to | |
1400 | * kick the VCPU out of VMXON or even guest mode on reset. This has to be done | |
1401 | * before writing any other state because forcibly leaving nested mode | |
1402 | * invalidates the VCPU state. | |
1403 | */ | |
1404 | static int kvm_put_msr_feature_control(X86CPU *cpu) | |
1405 | { | |
1406 | struct { | |
1407 | struct kvm_msrs info; | |
1408 | struct kvm_msr_entry entry; | |
1409 | } msr_data; | |
1410 | ||
1411 | kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL, | |
1412 | cpu->env.msr_ia32_feature_control); | |
c7fe4b12 CB |
1413 | |
1414 | msr_data.info = (struct kvm_msrs) { | |
1415 | .nmsrs = 1, | |
1416 | }; | |
1417 | ||
6bdf863d JK |
1418 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); |
1419 | } | |
1420 | ||
1bc22652 | 1421 | static int kvm_put_msrs(X86CPU *cpu, int level) |
05330448 | 1422 | { |
1bc22652 | 1423 | CPUX86State *env = &cpu->env; |
05330448 AL |
1424 | struct { |
1425 | struct kvm_msrs info; | |
d1ae67f6 | 1426 | struct kvm_msr_entry entries[150]; |
05330448 AL |
1427 | } msr_data; |
1428 | struct kvm_msr_entry *msrs = msr_data.entries; | |
0d894367 | 1429 | int n = 0, i; |
05330448 AL |
1430 | |
1431 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); | |
1432 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
1433 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
0c03266a | 1434 | kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
c3a3a7d3 | 1435 | if (has_msr_star) { |
b9bec74b JK |
1436 | kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
1437 | } | |
c3a3a7d3 | 1438 | if (has_msr_hsave_pa) { |
75b10c43 | 1439 | kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 1440 | } |
c9b8f6b6 AS |
1441 | if (has_msr_tsc_aux) { |
1442 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux); | |
1443 | } | |
f28558d3 WA |
1444 | if (has_msr_tsc_adjust) { |
1445 | kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); | |
1446 | } | |
21e87c46 AK |
1447 | if (has_msr_misc_enable) { |
1448 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, | |
1449 | env->msr_ia32_misc_enable); | |
1450 | } | |
fc12d72e PB |
1451 | if (has_msr_smbase) { |
1452 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase); | |
1453 | } | |
439d19f2 PB |
1454 | if (has_msr_bndcfgs) { |
1455 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs); | |
1456 | } | |
18cd2c17 WL |
1457 | if (has_msr_xss) { |
1458 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss); | |
1459 | } | |
05330448 | 1460 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1461 | if (lm_capable_kernel) { |
1462 | kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); | |
1463 | kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); | |
1464 | kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); | |
1465 | kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); | |
1466 | } | |
05330448 | 1467 | #endif |
ff5c186b | 1468 | /* |
0d894367 PB |
1469 | * The following MSRs have side effects on the guest or are too heavy |
1470 | * for normal writeback. Limit them to reset or full state updates. | |
ff5c186b JK |
1471 | */ |
1472 | if (level >= KVM_PUT_RESET_STATE) { | |
0522604b | 1473 | kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); |
ea643051 JK |
1474 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1475 | env->system_time_msr); | |
1476 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
c5999bfc JK |
1477 | if (has_msr_async_pf_en) { |
1478 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, | |
1479 | env->async_pf_en_msr); | |
1480 | } | |
bc9a839d MT |
1481 | if (has_msr_pv_eoi_en) { |
1482 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN, | |
1483 | env->pv_eoi_en_msr); | |
1484 | } | |
917367aa MT |
1485 | if (has_msr_kvm_steal_time) { |
1486 | kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME, | |
1487 | env->steal_time_msr); | |
1488 | } | |
0d894367 PB |
1489 | if (has_msr_architectural_pmu) { |
1490 | /* Stop the counter. */ | |
1491 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0); | |
1492 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
1493 | ||
1494 | /* Set the counter values. */ | |
1495 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1496 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i, | |
1497 | env->msr_fixed_counters[i]); | |
1498 | } | |
1499 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1500 | kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i, | |
1501 | env->msr_gp_counters[i]); | |
1502 | kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i, | |
1503 | env->msr_gp_evtsel[i]); | |
1504 | } | |
1505 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS, | |
1506 | env->msr_global_status); | |
1507 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1508 | env->msr_global_ovf_ctrl); | |
1509 | ||
1510 | /* Now start the PMU. */ | |
1511 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, | |
1512 | env->msr_fixed_ctr_ctrl); | |
1513 | kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, | |
1514 | env->msr_global_ctrl); | |
1515 | } | |
7bc3d711 | 1516 | if (has_msr_hv_hypercall) { |
1c90ef26 VR |
1517 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, |
1518 | env->msr_hv_guest_os_id); | |
1519 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, | |
1520 | env->msr_hv_hypercall); | |
eab70139 | 1521 | } |
7bc3d711 | 1522 | if (has_msr_hv_vapic) { |
5ef68987 VR |
1523 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, |
1524 | env->msr_hv_vapic); | |
eab70139 | 1525 | } |
48a5f3bc VR |
1526 | if (has_msr_hv_tsc) { |
1527 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC, | |
1528 | env->msr_hv_tsc); | |
1529 | } | |
f2a53c9e AS |
1530 | if (has_msr_hv_crash) { |
1531 | int j; | |
1532 | ||
1533 | for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) | |
1534 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j, | |
1535 | env->msr_hv_crash_params[j]); | |
1536 | ||
1537 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL, | |
1538 | HV_X64_MSR_CRASH_CTL_NOTIFY); | |
1539 | } | |
46eb8f98 AS |
1540 | if (has_msr_hv_runtime) { |
1541 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME, | |
1542 | env->msr_hv_runtime); | |
1543 | } | |
866eea9a AS |
1544 | if (cpu->hyperv_synic) { |
1545 | int j; | |
1546 | ||
1547 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL, | |
1548 | env->msr_hv_synic_control); | |
1549 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION, | |
1550 | env->msr_hv_synic_version); | |
1551 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP, | |
1552 | env->msr_hv_synic_evt_page); | |
1553 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP, | |
1554 | env->msr_hv_synic_msg_page); | |
1555 | ||
1556 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { | |
1557 | kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j, | |
1558 | env->msr_hv_synic_sint[j]); | |
1559 | } | |
1560 | } | |
d1ae67f6 AW |
1561 | if (has_msr_mtrr) { |
1562 | kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype); | |
1563 | kvm_msr_entry_set(&msrs[n++], | |
1564 | MSR_MTRRfix64K_00000, env->mtrr_fixed[0]); | |
1565 | kvm_msr_entry_set(&msrs[n++], | |
1566 | MSR_MTRRfix16K_80000, env->mtrr_fixed[1]); | |
1567 | kvm_msr_entry_set(&msrs[n++], | |
1568 | MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]); | |
1569 | kvm_msr_entry_set(&msrs[n++], | |
1570 | MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]); | |
1571 | kvm_msr_entry_set(&msrs[n++], | |
1572 | MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]); | |
1573 | kvm_msr_entry_set(&msrs[n++], | |
1574 | MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]); | |
1575 | kvm_msr_entry_set(&msrs[n++], | |
1576 | MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]); | |
1577 | kvm_msr_entry_set(&msrs[n++], | |
1578 | MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]); | |
1579 | kvm_msr_entry_set(&msrs[n++], | |
1580 | MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]); | |
1581 | kvm_msr_entry_set(&msrs[n++], | |
1582 | MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]); | |
1583 | kvm_msr_entry_set(&msrs[n++], | |
1584 | MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]); | |
1585 | for (i = 0; i < MSR_MTRRcap_VCNT; i++) { | |
1586 | kvm_msr_entry_set(&msrs[n++], | |
1587 | MSR_MTRRphysBase(i), env->mtrr_var[i].base); | |
1588 | kvm_msr_entry_set(&msrs[n++], | |
1589 | MSR_MTRRphysMask(i), env->mtrr_var[i].mask); | |
1590 | } | |
1591 | } | |
6bdf863d JK |
1592 | |
1593 | /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see | |
1594 | * kvm_put_msr_feature_control. */ | |
ea643051 | 1595 | } |
57780495 | 1596 | if (env->mcg_cap) { |
d8da8574 | 1597 | int i; |
b9bec74b | 1598 | |
c34d440a JK |
1599 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1600 | kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); | |
1601 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { | |
1602 | kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); | |
57780495 MT |
1603 | } |
1604 | } | |
1a03675d | 1605 | |
c7fe4b12 CB |
1606 | msr_data.info = (struct kvm_msrs) { |
1607 | .nmsrs = n, | |
1608 | }; | |
05330448 | 1609 | |
1bc22652 | 1610 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); |
05330448 AL |
1611 | |
1612 | } | |
1613 | ||
1614 | ||
1bc22652 | 1615 | static int kvm_get_fpu(X86CPU *cpu) |
05330448 | 1616 | { |
1bc22652 | 1617 | CPUX86State *env = &cpu->env; |
05330448 AL |
1618 | struct kvm_fpu fpu; |
1619 | int i, ret; | |
1620 | ||
1bc22652 | 1621 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); |
b9bec74b | 1622 | if (ret < 0) { |
05330448 | 1623 | return ret; |
b9bec74b | 1624 | } |
05330448 AL |
1625 | |
1626 | env->fpstt = (fpu.fsw >> 11) & 7; | |
1627 | env->fpus = fpu.fsw; | |
1628 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
1629 | env->fpop = fpu.last_opcode; |
1630 | env->fpip = fpu.last_ip; | |
1631 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
1632 | for (i = 0; i < 8; ++i) { |
1633 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
1634 | } | |
05330448 | 1635 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
bee81887 PB |
1636 | for (i = 0; i < CPU_NB_REGS; i++) { |
1637 | env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]); | |
1638 | env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]); | |
1639 | } | |
05330448 AL |
1640 | env->mxcsr = fpu.mxcsr; |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
1bc22652 | 1645 | static int kvm_get_xsave(X86CPU *cpu) |
f1665b21 | 1646 | { |
1bc22652 | 1647 | CPUX86State *env = &cpu->env; |
fabacc0f | 1648 | struct kvm_xsave* xsave = env->kvm_xsave_buf; |
f1665b21 | 1649 | int ret, i; |
b7711471 | 1650 | const uint8_t *xmm, *ymmh, *zmmh; |
42cc8fa6 | 1651 | uint16_t cwd, swd, twd; |
f1665b21 | 1652 | |
28143b40 | 1653 | if (!has_xsave) { |
1bc22652 | 1654 | return kvm_get_fpu(cpu); |
b9bec74b | 1655 | } |
f1665b21 | 1656 | |
1bc22652 | 1657 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); |
0f53994f | 1658 | if (ret < 0) { |
f1665b21 | 1659 | return ret; |
0f53994f | 1660 | } |
f1665b21 | 1661 | |
6b42494b JK |
1662 | cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1663 | swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16); | |
1664 | twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; | |
1665 | env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16); | |
f1665b21 SY |
1666 | env->fpstt = (swd >> 11) & 7; |
1667 | env->fpus = swd; | |
1668 | env->fpuc = cwd; | |
b9bec74b | 1669 | for (i = 0; i < 8; ++i) { |
f1665b21 | 1670 | env->fptags[i] = !((twd >> i) & 1); |
b9bec74b | 1671 | } |
42cc8fa6 JK |
1672 | memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip)); |
1673 | memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp)); | |
f1665b21 SY |
1674 | env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1675 | memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], | |
1676 | sizeof env->fpregs); | |
f1665b21 | 1677 | env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; |
79e9ebeb LJ |
1678 | memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS], |
1679 | sizeof env->bnd_regs); | |
1680 | memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR], | |
1681 | sizeof(env->bndcs_regs)); | |
9aecd6f8 CP |
1682 | memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK], |
1683 | sizeof env->opmask_regs); | |
bee81887 PB |
1684 | |
1685 | xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE]; | |
b7711471 PB |
1686 | ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE]; |
1687 | zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256]; | |
1688 | for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) { | |
bee81887 PB |
1689 | env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm); |
1690 | env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8); | |
b7711471 PB |
1691 | env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh); |
1692 | env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8); | |
1693 | env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh); | |
1694 | env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8); | |
1695 | env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16); | |
1696 | env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24); | |
bee81887 PB |
1697 | } |
1698 | ||
9aecd6f8 | 1699 | #ifdef TARGET_X86_64 |
b7711471 PB |
1700 | memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM], |
1701 | 16 * sizeof env->xmm_regs[16]); | |
9aecd6f8 | 1702 | #endif |
f1665b21 | 1703 | return 0; |
f1665b21 SY |
1704 | } |
1705 | ||
1bc22652 | 1706 | static int kvm_get_xcrs(X86CPU *cpu) |
f1665b21 | 1707 | { |
1bc22652 | 1708 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
1709 | int i, ret; |
1710 | struct kvm_xcrs xcrs; | |
1711 | ||
28143b40 | 1712 | if (!has_xcrs) { |
f1665b21 | 1713 | return 0; |
b9bec74b | 1714 | } |
f1665b21 | 1715 | |
1bc22652 | 1716 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); |
b9bec74b | 1717 | if (ret < 0) { |
f1665b21 | 1718 | return ret; |
b9bec74b | 1719 | } |
f1665b21 | 1720 | |
b9bec74b | 1721 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 | 1722 | /* Only support xcr0 now */ |
0fd53fec PB |
1723 | if (xcrs.xcrs[i].xcr == 0) { |
1724 | env->xcr0 = xcrs.xcrs[i].value; | |
f1665b21 SY |
1725 | break; |
1726 | } | |
b9bec74b | 1727 | } |
f1665b21 | 1728 | return 0; |
f1665b21 SY |
1729 | } |
1730 | ||
1bc22652 | 1731 | static int kvm_get_sregs(X86CPU *cpu) |
05330448 | 1732 | { |
1bc22652 | 1733 | CPUX86State *env = &cpu->env; |
05330448 AL |
1734 | struct kvm_sregs sregs; |
1735 | uint32_t hflags; | |
0e607a80 | 1736 | int bit, i, ret; |
05330448 | 1737 | |
1bc22652 | 1738 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); |
b9bec74b | 1739 | if (ret < 0) { |
05330448 | 1740 | return ret; |
b9bec74b | 1741 | } |
05330448 | 1742 | |
0e607a80 JK |
1743 | /* There can only be one pending IRQ set in the bitmap at a time, so try |
1744 | to find it and save its number instead (-1 for none). */ | |
1745 | env->interrupt_injected = -1; | |
1746 | for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { | |
1747 | if (sregs.interrupt_bitmap[i]) { | |
1748 | bit = ctz64(sregs.interrupt_bitmap[i]); | |
1749 | env->interrupt_injected = i * 64 + bit; | |
1750 | break; | |
1751 | } | |
1752 | } | |
05330448 AL |
1753 | |
1754 | get_seg(&env->segs[R_CS], &sregs.cs); | |
1755 | get_seg(&env->segs[R_DS], &sregs.ds); | |
1756 | get_seg(&env->segs[R_ES], &sregs.es); | |
1757 | get_seg(&env->segs[R_FS], &sregs.fs); | |
1758 | get_seg(&env->segs[R_GS], &sregs.gs); | |
1759 | get_seg(&env->segs[R_SS], &sregs.ss); | |
1760 | ||
1761 | get_seg(&env->tr, &sregs.tr); | |
1762 | get_seg(&env->ldt, &sregs.ldt); | |
1763 | ||
1764 | env->idt.limit = sregs.idt.limit; | |
1765 | env->idt.base = sregs.idt.base; | |
1766 | env->gdt.limit = sregs.gdt.limit; | |
1767 | env->gdt.base = sregs.gdt.base; | |
1768 | ||
1769 | env->cr[0] = sregs.cr0; | |
1770 | env->cr[2] = sregs.cr2; | |
1771 | env->cr[3] = sregs.cr3; | |
1772 | env->cr[4] = sregs.cr4; | |
1773 | ||
05330448 | 1774 | env->efer = sregs.efer; |
cce47516 JK |
1775 | |
1776 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
05330448 | 1777 | |
b9bec74b JK |
1778 | #define HFLAG_COPY_MASK \ |
1779 | ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ | |
1780 | HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ | |
1781 | HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ | |
1782 | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) | |
05330448 | 1783 | |
7125c937 | 1784 | hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; |
05330448 AL |
1785 | hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); |
1786 | hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & | |
b9bec74b | 1787 | (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
05330448 AL |
1788 | hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1789 | hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << | |
b9bec74b | 1790 | (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
05330448 AL |
1791 | |
1792 | if (env->efer & MSR_EFER_LMA) { | |
1793 | hflags |= HF_LMA_MASK; | |
1794 | } | |
1795 | ||
1796 | if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { | |
1797 | hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1798 | } else { | |
1799 | hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> | |
b9bec74b | 1800 | (DESC_B_SHIFT - HF_CS32_SHIFT); |
05330448 | 1801 | hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
b9bec74b JK |
1802 | (DESC_B_SHIFT - HF_SS32_SHIFT); |
1803 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || | |
1804 | !(hflags & HF_CS32_MASK)) { | |
1805 | hflags |= HF_ADDSEG_MASK; | |
1806 | } else { | |
1807 | hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | | |
1808 | env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; | |
1809 | } | |
05330448 AL |
1810 | } |
1811 | env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; | |
05330448 AL |
1812 | |
1813 | return 0; | |
1814 | } | |
1815 | ||
1bc22652 | 1816 | static int kvm_get_msrs(X86CPU *cpu) |
05330448 | 1817 | { |
1bc22652 | 1818 | CPUX86State *env = &cpu->env; |
05330448 AL |
1819 | struct { |
1820 | struct kvm_msrs info; | |
d1ae67f6 | 1821 | struct kvm_msr_entry entries[150]; |
05330448 AL |
1822 | } msr_data; |
1823 | struct kvm_msr_entry *msrs = msr_data.entries; | |
1824 | int ret, i, n; | |
1825 | ||
1826 | n = 0; | |
1827 | msrs[n++].index = MSR_IA32_SYSENTER_CS; | |
1828 | msrs[n++].index = MSR_IA32_SYSENTER_ESP; | |
1829 | msrs[n++].index = MSR_IA32_SYSENTER_EIP; | |
0c03266a | 1830 | msrs[n++].index = MSR_PAT; |
c3a3a7d3 | 1831 | if (has_msr_star) { |
b9bec74b JK |
1832 | msrs[n++].index = MSR_STAR; |
1833 | } | |
c3a3a7d3 | 1834 | if (has_msr_hsave_pa) { |
75b10c43 | 1835 | msrs[n++].index = MSR_VM_HSAVE_PA; |
b9bec74b | 1836 | } |
c9b8f6b6 AS |
1837 | if (has_msr_tsc_aux) { |
1838 | msrs[n++].index = MSR_TSC_AUX; | |
1839 | } | |
f28558d3 WA |
1840 | if (has_msr_tsc_adjust) { |
1841 | msrs[n++].index = MSR_TSC_ADJUST; | |
1842 | } | |
aa82ba54 LJ |
1843 | if (has_msr_tsc_deadline) { |
1844 | msrs[n++].index = MSR_IA32_TSCDEADLINE; | |
1845 | } | |
21e87c46 AK |
1846 | if (has_msr_misc_enable) { |
1847 | msrs[n++].index = MSR_IA32_MISC_ENABLE; | |
1848 | } | |
fc12d72e PB |
1849 | if (has_msr_smbase) { |
1850 | msrs[n++].index = MSR_IA32_SMBASE; | |
1851 | } | |
df67696e LJ |
1852 | if (has_msr_feature_control) { |
1853 | msrs[n++].index = MSR_IA32_FEATURE_CONTROL; | |
1854 | } | |
79e9ebeb LJ |
1855 | if (has_msr_bndcfgs) { |
1856 | msrs[n++].index = MSR_IA32_BNDCFGS; | |
1857 | } | |
18cd2c17 WL |
1858 | if (has_msr_xss) { |
1859 | msrs[n++].index = MSR_IA32_XSS; | |
1860 | } | |
1861 | ||
b8cc45d6 GC |
1862 | |
1863 | if (!env->tsc_valid) { | |
1864 | msrs[n++].index = MSR_IA32_TSC; | |
1354869c | 1865 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
1866 | } |
1867 | ||
05330448 | 1868 | #ifdef TARGET_X86_64 |
25d2e361 MT |
1869 | if (lm_capable_kernel) { |
1870 | msrs[n++].index = MSR_CSTAR; | |
1871 | msrs[n++].index = MSR_KERNELGSBASE; | |
1872 | msrs[n++].index = MSR_FMASK; | |
1873 | msrs[n++].index = MSR_LSTAR; | |
1874 | } | |
05330448 | 1875 | #endif |
1a03675d GC |
1876 | msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1877 | msrs[n++].index = MSR_KVM_WALL_CLOCK; | |
c5999bfc JK |
1878 | if (has_msr_async_pf_en) { |
1879 | msrs[n++].index = MSR_KVM_ASYNC_PF_EN; | |
1880 | } | |
bc9a839d MT |
1881 | if (has_msr_pv_eoi_en) { |
1882 | msrs[n++].index = MSR_KVM_PV_EOI_EN; | |
1883 | } | |
917367aa MT |
1884 | if (has_msr_kvm_steal_time) { |
1885 | msrs[n++].index = MSR_KVM_STEAL_TIME; | |
1886 | } | |
0d894367 PB |
1887 | if (has_msr_architectural_pmu) { |
1888 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL; | |
1889 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL; | |
1890 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS; | |
1891 | msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL; | |
1892 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { | |
1893 | msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i; | |
1894 | } | |
1895 | for (i = 0; i < num_architectural_pmu_counters; i++) { | |
1896 | msrs[n++].index = MSR_P6_PERFCTR0 + i; | |
1897 | msrs[n++].index = MSR_P6_EVNTSEL0 + i; | |
1898 | } | |
1899 | } | |
1a03675d | 1900 | |
57780495 MT |
1901 | if (env->mcg_cap) { |
1902 | msrs[n++].index = MSR_MCG_STATUS; | |
1903 | msrs[n++].index = MSR_MCG_CTL; | |
b9bec74b | 1904 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
57780495 | 1905 | msrs[n++].index = MSR_MC0_CTL + i; |
b9bec74b | 1906 | } |
57780495 | 1907 | } |
57780495 | 1908 | |
1c90ef26 VR |
1909 | if (has_msr_hv_hypercall) { |
1910 | msrs[n++].index = HV_X64_MSR_HYPERCALL; | |
1911 | msrs[n++].index = HV_X64_MSR_GUEST_OS_ID; | |
1912 | } | |
5ef68987 VR |
1913 | if (has_msr_hv_vapic) { |
1914 | msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE; | |
1915 | } | |
48a5f3bc VR |
1916 | if (has_msr_hv_tsc) { |
1917 | msrs[n++].index = HV_X64_MSR_REFERENCE_TSC; | |
1918 | } | |
f2a53c9e AS |
1919 | if (has_msr_hv_crash) { |
1920 | int j; | |
1921 | ||
1922 | for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) { | |
1923 | msrs[n++].index = HV_X64_MSR_CRASH_P0 + j; | |
1924 | } | |
1925 | } | |
46eb8f98 AS |
1926 | if (has_msr_hv_runtime) { |
1927 | msrs[n++].index = HV_X64_MSR_VP_RUNTIME; | |
1928 | } | |
866eea9a AS |
1929 | if (cpu->hyperv_synic) { |
1930 | uint32_t msr; | |
1931 | ||
1932 | msrs[n++].index = HV_X64_MSR_SCONTROL; | |
1933 | msrs[n++].index = HV_X64_MSR_SVERSION; | |
1934 | msrs[n++].index = HV_X64_MSR_SIEFP; | |
1935 | msrs[n++].index = HV_X64_MSR_SIMP; | |
1936 | for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { | |
1937 | msrs[n++].index = msr; | |
1938 | } | |
1939 | } | |
d1ae67f6 AW |
1940 | if (has_msr_mtrr) { |
1941 | msrs[n++].index = MSR_MTRRdefType; | |
1942 | msrs[n++].index = MSR_MTRRfix64K_00000; | |
1943 | msrs[n++].index = MSR_MTRRfix16K_80000; | |
1944 | msrs[n++].index = MSR_MTRRfix16K_A0000; | |
1945 | msrs[n++].index = MSR_MTRRfix4K_C0000; | |
1946 | msrs[n++].index = MSR_MTRRfix4K_C8000; | |
1947 | msrs[n++].index = MSR_MTRRfix4K_D0000; | |
1948 | msrs[n++].index = MSR_MTRRfix4K_D8000; | |
1949 | msrs[n++].index = MSR_MTRRfix4K_E0000; | |
1950 | msrs[n++].index = MSR_MTRRfix4K_E8000; | |
1951 | msrs[n++].index = MSR_MTRRfix4K_F0000; | |
1952 | msrs[n++].index = MSR_MTRRfix4K_F8000; | |
1953 | for (i = 0; i < MSR_MTRRcap_VCNT; i++) { | |
1954 | msrs[n++].index = MSR_MTRRphysBase(i); | |
1955 | msrs[n++].index = MSR_MTRRphysMask(i); | |
1956 | } | |
1957 | } | |
5ef68987 | 1958 | |
d19ae73e CB |
1959 | msr_data.info = (struct kvm_msrs) { |
1960 | .nmsrs = n, | |
1961 | }; | |
1962 | ||
1bc22652 | 1963 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); |
b9bec74b | 1964 | if (ret < 0) { |
05330448 | 1965 | return ret; |
b9bec74b | 1966 | } |
05330448 AL |
1967 | |
1968 | for (i = 0; i < ret; i++) { | |
0d894367 PB |
1969 | uint32_t index = msrs[i].index; |
1970 | switch (index) { | |
05330448 AL |
1971 | case MSR_IA32_SYSENTER_CS: |
1972 | env->sysenter_cs = msrs[i].data; | |
1973 | break; | |
1974 | case MSR_IA32_SYSENTER_ESP: | |
1975 | env->sysenter_esp = msrs[i].data; | |
1976 | break; | |
1977 | case MSR_IA32_SYSENTER_EIP: | |
1978 | env->sysenter_eip = msrs[i].data; | |
1979 | break; | |
0c03266a JK |
1980 | case MSR_PAT: |
1981 | env->pat = msrs[i].data; | |
1982 | break; | |
05330448 AL |
1983 | case MSR_STAR: |
1984 | env->star = msrs[i].data; | |
1985 | break; | |
1986 | #ifdef TARGET_X86_64 | |
1987 | case MSR_CSTAR: | |
1988 | env->cstar = msrs[i].data; | |
1989 | break; | |
1990 | case MSR_KERNELGSBASE: | |
1991 | env->kernelgsbase = msrs[i].data; | |
1992 | break; | |
1993 | case MSR_FMASK: | |
1994 | env->fmask = msrs[i].data; | |
1995 | break; | |
1996 | case MSR_LSTAR: | |
1997 | env->lstar = msrs[i].data; | |
1998 | break; | |
1999 | #endif | |
2000 | case MSR_IA32_TSC: | |
2001 | env->tsc = msrs[i].data; | |
2002 | break; | |
c9b8f6b6 AS |
2003 | case MSR_TSC_AUX: |
2004 | env->tsc_aux = msrs[i].data; | |
2005 | break; | |
f28558d3 WA |
2006 | case MSR_TSC_ADJUST: |
2007 | env->tsc_adjust = msrs[i].data; | |
2008 | break; | |
aa82ba54 LJ |
2009 | case MSR_IA32_TSCDEADLINE: |
2010 | env->tsc_deadline = msrs[i].data; | |
2011 | break; | |
aa851e36 MT |
2012 | case MSR_VM_HSAVE_PA: |
2013 | env->vm_hsave = msrs[i].data; | |
2014 | break; | |
1a03675d GC |
2015 | case MSR_KVM_SYSTEM_TIME: |
2016 | env->system_time_msr = msrs[i].data; | |
2017 | break; | |
2018 | case MSR_KVM_WALL_CLOCK: | |
2019 | env->wall_clock_msr = msrs[i].data; | |
2020 | break; | |
57780495 MT |
2021 | case MSR_MCG_STATUS: |
2022 | env->mcg_status = msrs[i].data; | |
2023 | break; | |
2024 | case MSR_MCG_CTL: | |
2025 | env->mcg_ctl = msrs[i].data; | |
2026 | break; | |
21e87c46 AK |
2027 | case MSR_IA32_MISC_ENABLE: |
2028 | env->msr_ia32_misc_enable = msrs[i].data; | |
2029 | break; | |
fc12d72e PB |
2030 | case MSR_IA32_SMBASE: |
2031 | env->smbase = msrs[i].data; | |
2032 | break; | |
0779caeb ACL |
2033 | case MSR_IA32_FEATURE_CONTROL: |
2034 | env->msr_ia32_feature_control = msrs[i].data; | |
df67696e | 2035 | break; |
79e9ebeb LJ |
2036 | case MSR_IA32_BNDCFGS: |
2037 | env->msr_bndcfgs = msrs[i].data; | |
2038 | break; | |
18cd2c17 WL |
2039 | case MSR_IA32_XSS: |
2040 | env->xss = msrs[i].data; | |
2041 | break; | |
57780495 | 2042 | default: |
57780495 MT |
2043 | if (msrs[i].index >= MSR_MC0_CTL && |
2044 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
2045 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 2046 | } |
d8da8574 | 2047 | break; |
f6584ee2 GN |
2048 | case MSR_KVM_ASYNC_PF_EN: |
2049 | env->async_pf_en_msr = msrs[i].data; | |
2050 | break; | |
bc9a839d MT |
2051 | case MSR_KVM_PV_EOI_EN: |
2052 | env->pv_eoi_en_msr = msrs[i].data; | |
2053 | break; | |
917367aa MT |
2054 | case MSR_KVM_STEAL_TIME: |
2055 | env->steal_time_msr = msrs[i].data; | |
2056 | break; | |
0d894367 PB |
2057 | case MSR_CORE_PERF_FIXED_CTR_CTRL: |
2058 | env->msr_fixed_ctr_ctrl = msrs[i].data; | |
2059 | break; | |
2060 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2061 | env->msr_global_ctrl = msrs[i].data; | |
2062 | break; | |
2063 | case MSR_CORE_PERF_GLOBAL_STATUS: | |
2064 | env->msr_global_status = msrs[i].data; | |
2065 | break; | |
2066 | case MSR_CORE_PERF_GLOBAL_OVF_CTRL: | |
2067 | env->msr_global_ovf_ctrl = msrs[i].data; | |
2068 | break; | |
2069 | case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: | |
2070 | env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; | |
2071 | break; | |
2072 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: | |
2073 | env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; | |
2074 | break; | |
2075 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: | |
2076 | env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; | |
2077 | break; | |
1c90ef26 VR |
2078 | case HV_X64_MSR_HYPERCALL: |
2079 | env->msr_hv_hypercall = msrs[i].data; | |
2080 | break; | |
2081 | case HV_X64_MSR_GUEST_OS_ID: | |
2082 | env->msr_hv_guest_os_id = msrs[i].data; | |
2083 | break; | |
5ef68987 VR |
2084 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
2085 | env->msr_hv_vapic = msrs[i].data; | |
2086 | break; | |
48a5f3bc VR |
2087 | case HV_X64_MSR_REFERENCE_TSC: |
2088 | env->msr_hv_tsc = msrs[i].data; | |
2089 | break; | |
f2a53c9e AS |
2090 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2091 | env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data; | |
2092 | break; | |
46eb8f98 AS |
2093 | case HV_X64_MSR_VP_RUNTIME: |
2094 | env->msr_hv_runtime = msrs[i].data; | |
2095 | break; | |
866eea9a AS |
2096 | case HV_X64_MSR_SCONTROL: |
2097 | env->msr_hv_synic_control = msrs[i].data; | |
2098 | break; | |
2099 | case HV_X64_MSR_SVERSION: | |
2100 | env->msr_hv_synic_version = msrs[i].data; | |
2101 | break; | |
2102 | case HV_X64_MSR_SIEFP: | |
2103 | env->msr_hv_synic_evt_page = msrs[i].data; | |
2104 | break; | |
2105 | case HV_X64_MSR_SIMP: | |
2106 | env->msr_hv_synic_msg_page = msrs[i].data; | |
2107 | break; | |
2108 | case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: | |
2109 | env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data; | |
2110 | break; | |
d1ae67f6 AW |
2111 | case MSR_MTRRdefType: |
2112 | env->mtrr_deftype = msrs[i].data; | |
2113 | break; | |
2114 | case MSR_MTRRfix64K_00000: | |
2115 | env->mtrr_fixed[0] = msrs[i].data; | |
2116 | break; | |
2117 | case MSR_MTRRfix16K_80000: | |
2118 | env->mtrr_fixed[1] = msrs[i].data; | |
2119 | break; | |
2120 | case MSR_MTRRfix16K_A0000: | |
2121 | env->mtrr_fixed[2] = msrs[i].data; | |
2122 | break; | |
2123 | case MSR_MTRRfix4K_C0000: | |
2124 | env->mtrr_fixed[3] = msrs[i].data; | |
2125 | break; | |
2126 | case MSR_MTRRfix4K_C8000: | |
2127 | env->mtrr_fixed[4] = msrs[i].data; | |
2128 | break; | |
2129 | case MSR_MTRRfix4K_D0000: | |
2130 | env->mtrr_fixed[5] = msrs[i].data; | |
2131 | break; | |
2132 | case MSR_MTRRfix4K_D8000: | |
2133 | env->mtrr_fixed[6] = msrs[i].data; | |
2134 | break; | |
2135 | case MSR_MTRRfix4K_E0000: | |
2136 | env->mtrr_fixed[7] = msrs[i].data; | |
2137 | break; | |
2138 | case MSR_MTRRfix4K_E8000: | |
2139 | env->mtrr_fixed[8] = msrs[i].data; | |
2140 | break; | |
2141 | case MSR_MTRRfix4K_F0000: | |
2142 | env->mtrr_fixed[9] = msrs[i].data; | |
2143 | break; | |
2144 | case MSR_MTRRfix4K_F8000: | |
2145 | env->mtrr_fixed[10] = msrs[i].data; | |
2146 | break; | |
2147 | case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): | |
2148 | if (index & 1) { | |
2149 | env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; | |
2150 | } else { | |
2151 | env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; | |
2152 | } | |
2153 | break; | |
05330448 AL |
2154 | } |
2155 | } | |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
1bc22652 | 2160 | static int kvm_put_mp_state(X86CPU *cpu) |
9bdbe550 | 2161 | { |
1bc22652 | 2162 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; |
9bdbe550 | 2163 | |
1bc22652 | 2164 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); |
9bdbe550 HB |
2165 | } |
2166 | ||
23d02d9b | 2167 | static int kvm_get_mp_state(X86CPU *cpu) |
9bdbe550 | 2168 | { |
259186a7 | 2169 | CPUState *cs = CPU(cpu); |
23d02d9b | 2170 | CPUX86State *env = &cpu->env; |
9bdbe550 HB |
2171 | struct kvm_mp_state mp_state; |
2172 | int ret; | |
2173 | ||
259186a7 | 2174 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); |
9bdbe550 HB |
2175 | if (ret < 0) { |
2176 | return ret; | |
2177 | } | |
2178 | env->mp_state = mp_state.mp_state; | |
c14750e8 | 2179 | if (kvm_irqchip_in_kernel()) { |
259186a7 | 2180 | cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
c14750e8 | 2181 | } |
9bdbe550 HB |
2182 | return 0; |
2183 | } | |
2184 | ||
1bc22652 | 2185 | static int kvm_get_apic(X86CPU *cpu) |
680c1c6f | 2186 | { |
02e51483 | 2187 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
2188 | struct kvm_lapic_state kapic; |
2189 | int ret; | |
2190 | ||
3d4b2649 | 2191 | if (apic && kvm_irqchip_in_kernel()) { |
1bc22652 | 2192 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); |
680c1c6f JK |
2193 | if (ret < 0) { |
2194 | return ret; | |
2195 | } | |
2196 | ||
2197 | kvm_get_apic_state(apic, &kapic); | |
2198 | } | |
2199 | return 0; | |
2200 | } | |
2201 | ||
1bc22652 | 2202 | static int kvm_put_apic(X86CPU *cpu) |
680c1c6f | 2203 | { |
02e51483 | 2204 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
2205 | struct kvm_lapic_state kapic; |
2206 | ||
3d4b2649 | 2207 | if (apic && kvm_irqchip_in_kernel()) { |
680c1c6f JK |
2208 | kvm_put_apic_state(apic, &kapic); |
2209 | ||
1bc22652 | 2210 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic); |
680c1c6f JK |
2211 | } |
2212 | return 0; | |
2213 | } | |
2214 | ||
1bc22652 | 2215 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) |
a0fb002c | 2216 | { |
fc12d72e | 2217 | CPUState *cs = CPU(cpu); |
1bc22652 | 2218 | CPUX86State *env = &cpu->env; |
076796f8 | 2219 | struct kvm_vcpu_events events = {}; |
a0fb002c JK |
2220 | |
2221 | if (!kvm_has_vcpu_events()) { | |
2222 | return 0; | |
2223 | } | |
2224 | ||
31827373 JK |
2225 | events.exception.injected = (env->exception_injected >= 0); |
2226 | events.exception.nr = env->exception_injected; | |
a0fb002c JK |
2227 | events.exception.has_error_code = env->has_error_code; |
2228 | events.exception.error_code = env->error_code; | |
7e680753 | 2229 | events.exception.pad = 0; |
a0fb002c JK |
2230 | |
2231 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
2232 | events.interrupt.nr = env->interrupt_injected; | |
2233 | events.interrupt.soft = env->soft_interrupt; | |
2234 | ||
2235 | events.nmi.injected = env->nmi_injected; | |
2236 | events.nmi.pending = env->nmi_pending; | |
2237 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
7e680753 | 2238 | events.nmi.pad = 0; |
a0fb002c JK |
2239 | |
2240 | events.sipi_vector = env->sipi_vector; | |
2241 | ||
fc12d72e PB |
2242 | if (has_msr_smbase) { |
2243 | events.smi.smm = !!(env->hflags & HF_SMM_MASK); | |
2244 | events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK); | |
2245 | if (kvm_irqchip_in_kernel()) { | |
2246 | /* As soon as these are moved to the kernel, remove them | |
2247 | * from cs->interrupt_request. | |
2248 | */ | |
2249 | events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; | |
2250 | events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; | |
2251 | cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); | |
2252 | } else { | |
2253 | /* Keep these in cs->interrupt_request. */ | |
2254 | events.smi.pending = 0; | |
2255 | events.smi.latched_init = 0; | |
2256 | } | |
2257 | events.flags |= KVM_VCPUEVENT_VALID_SMM; | |
2258 | } | |
2259 | ||
ea643051 JK |
2260 | events.flags = 0; |
2261 | if (level >= KVM_PUT_RESET_STATE) { | |
2262 | events.flags |= | |
2263 | KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
2264 | } | |
aee028b9 | 2265 | |
1bc22652 | 2266 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
2267 | } |
2268 | ||
1bc22652 | 2269 | static int kvm_get_vcpu_events(X86CPU *cpu) |
a0fb002c | 2270 | { |
1bc22652 | 2271 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
2272 | struct kvm_vcpu_events events; |
2273 | int ret; | |
2274 | ||
2275 | if (!kvm_has_vcpu_events()) { | |
2276 | return 0; | |
2277 | } | |
2278 | ||
fc12d72e | 2279 | memset(&events, 0, sizeof(events)); |
1bc22652 | 2280 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); |
a0fb002c JK |
2281 | if (ret < 0) { |
2282 | return ret; | |
2283 | } | |
31827373 | 2284 | env->exception_injected = |
a0fb002c JK |
2285 | events.exception.injected ? events.exception.nr : -1; |
2286 | env->has_error_code = events.exception.has_error_code; | |
2287 | env->error_code = events.exception.error_code; | |
2288 | ||
2289 | env->interrupt_injected = | |
2290 | events.interrupt.injected ? events.interrupt.nr : -1; | |
2291 | env->soft_interrupt = events.interrupt.soft; | |
2292 | ||
2293 | env->nmi_injected = events.nmi.injected; | |
2294 | env->nmi_pending = events.nmi.pending; | |
2295 | if (events.nmi.masked) { | |
2296 | env->hflags2 |= HF2_NMI_MASK; | |
2297 | } else { | |
2298 | env->hflags2 &= ~HF2_NMI_MASK; | |
2299 | } | |
2300 | ||
fc12d72e PB |
2301 | if (events.flags & KVM_VCPUEVENT_VALID_SMM) { |
2302 | if (events.smi.smm) { | |
2303 | env->hflags |= HF_SMM_MASK; | |
2304 | } else { | |
2305 | env->hflags &= ~HF_SMM_MASK; | |
2306 | } | |
2307 | if (events.smi.pending) { | |
2308 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
2309 | } else { | |
2310 | cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
2311 | } | |
2312 | if (events.smi.smm_inside_nmi) { | |
2313 | env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; | |
2314 | } else { | |
2315 | env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; | |
2316 | } | |
2317 | if (events.smi.latched_init) { | |
2318 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); | |
2319 | } else { | |
2320 | cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); | |
2321 | } | |
2322 | } | |
2323 | ||
a0fb002c | 2324 | env->sipi_vector = events.sipi_vector; |
a0fb002c JK |
2325 | |
2326 | return 0; | |
2327 | } | |
2328 | ||
1bc22652 | 2329 | static int kvm_guest_debug_workarounds(X86CPU *cpu) |
b0b1d690 | 2330 | { |
ed2803da | 2331 | CPUState *cs = CPU(cpu); |
1bc22652 | 2332 | CPUX86State *env = &cpu->env; |
b0b1d690 | 2333 | int ret = 0; |
b0b1d690 JK |
2334 | unsigned long reinject_trap = 0; |
2335 | ||
2336 | if (!kvm_has_vcpu_events()) { | |
2337 | if (env->exception_injected == 1) { | |
2338 | reinject_trap = KVM_GUESTDBG_INJECT_DB; | |
2339 | } else if (env->exception_injected == 3) { | |
2340 | reinject_trap = KVM_GUESTDBG_INJECT_BP; | |
2341 | } | |
2342 | env->exception_injected = -1; | |
2343 | } | |
2344 | ||
2345 | /* | |
2346 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
2347 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
2348 | * by updating the debug state once again if single-stepping is on. | |
2349 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
2350 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
2351 | * reinject them via SET_GUEST_DEBUG. | |
2352 | */ | |
2353 | if (reinject_trap || | |
ed2803da | 2354 | (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { |
38e478ec | 2355 | ret = kvm_update_guest_debug(cs, reinject_trap); |
b0b1d690 | 2356 | } |
b0b1d690 JK |
2357 | return ret; |
2358 | } | |
2359 | ||
1bc22652 | 2360 | static int kvm_put_debugregs(X86CPU *cpu) |
ff44f1a3 | 2361 | { |
1bc22652 | 2362 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
2363 | struct kvm_debugregs dbgregs; |
2364 | int i; | |
2365 | ||
2366 | if (!kvm_has_debugregs()) { | |
2367 | return 0; | |
2368 | } | |
2369 | ||
2370 | for (i = 0; i < 4; i++) { | |
2371 | dbgregs.db[i] = env->dr[i]; | |
2372 | } | |
2373 | dbgregs.dr6 = env->dr[6]; | |
2374 | dbgregs.dr7 = env->dr[7]; | |
2375 | dbgregs.flags = 0; | |
2376 | ||
1bc22652 | 2377 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); |
ff44f1a3 JK |
2378 | } |
2379 | ||
1bc22652 | 2380 | static int kvm_get_debugregs(X86CPU *cpu) |
ff44f1a3 | 2381 | { |
1bc22652 | 2382 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
2383 | struct kvm_debugregs dbgregs; |
2384 | int i, ret; | |
2385 | ||
2386 | if (!kvm_has_debugregs()) { | |
2387 | return 0; | |
2388 | } | |
2389 | ||
1bc22652 | 2390 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); |
ff44f1a3 | 2391 | if (ret < 0) { |
b9bec74b | 2392 | return ret; |
ff44f1a3 JK |
2393 | } |
2394 | for (i = 0; i < 4; i++) { | |
2395 | env->dr[i] = dbgregs.db[i]; | |
2396 | } | |
2397 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
2398 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
2399 | |
2400 | return 0; | |
2401 | } | |
2402 | ||
20d695a9 | 2403 | int kvm_arch_put_registers(CPUState *cpu, int level) |
05330448 | 2404 | { |
20d695a9 | 2405 | X86CPU *x86_cpu = X86_CPU(cpu); |
05330448 AL |
2406 | int ret; |
2407 | ||
2fa45344 | 2408 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); |
dbaa07c4 | 2409 | |
6bdf863d JK |
2410 | if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) { |
2411 | ret = kvm_put_msr_feature_control(x86_cpu); | |
2412 | if (ret < 0) { | |
2413 | return ret; | |
2414 | } | |
2415 | } | |
2416 | ||
1bc22652 | 2417 | ret = kvm_getput_regs(x86_cpu, 1); |
b9bec74b | 2418 | if (ret < 0) { |
05330448 | 2419 | return ret; |
b9bec74b | 2420 | } |
1bc22652 | 2421 | ret = kvm_put_xsave(x86_cpu); |
b9bec74b | 2422 | if (ret < 0) { |
f1665b21 | 2423 | return ret; |
b9bec74b | 2424 | } |
1bc22652 | 2425 | ret = kvm_put_xcrs(x86_cpu); |
b9bec74b | 2426 | if (ret < 0) { |
05330448 | 2427 | return ret; |
b9bec74b | 2428 | } |
1bc22652 | 2429 | ret = kvm_put_sregs(x86_cpu); |
b9bec74b | 2430 | if (ret < 0) { |
05330448 | 2431 | return ret; |
b9bec74b | 2432 | } |
ab443475 | 2433 | /* must be before kvm_put_msrs */ |
1bc22652 | 2434 | ret = kvm_inject_mce_oldstyle(x86_cpu); |
ab443475 JK |
2435 | if (ret < 0) { |
2436 | return ret; | |
2437 | } | |
1bc22652 | 2438 | ret = kvm_put_msrs(x86_cpu, level); |
b9bec74b | 2439 | if (ret < 0) { |
05330448 | 2440 | return ret; |
b9bec74b | 2441 | } |
ea643051 | 2442 | if (level >= KVM_PUT_RESET_STATE) { |
1bc22652 | 2443 | ret = kvm_put_mp_state(x86_cpu); |
b9bec74b | 2444 | if (ret < 0) { |
ea643051 | 2445 | return ret; |
b9bec74b | 2446 | } |
1bc22652 | 2447 | ret = kvm_put_apic(x86_cpu); |
680c1c6f JK |
2448 | if (ret < 0) { |
2449 | return ret; | |
2450 | } | |
ea643051 | 2451 | } |
7477cd38 MT |
2452 | |
2453 | ret = kvm_put_tscdeadline_msr(x86_cpu); | |
2454 | if (ret < 0) { | |
2455 | return ret; | |
2456 | } | |
2457 | ||
1bc22652 | 2458 | ret = kvm_put_vcpu_events(x86_cpu, level); |
b9bec74b | 2459 | if (ret < 0) { |
a0fb002c | 2460 | return ret; |
b9bec74b | 2461 | } |
1bc22652 | 2462 | ret = kvm_put_debugregs(x86_cpu); |
b9bec74b | 2463 | if (ret < 0) { |
b0b1d690 | 2464 | return ret; |
b9bec74b | 2465 | } |
b0b1d690 | 2466 | /* must be last */ |
1bc22652 | 2467 | ret = kvm_guest_debug_workarounds(x86_cpu); |
b9bec74b | 2468 | if (ret < 0) { |
ff44f1a3 | 2469 | return ret; |
b9bec74b | 2470 | } |
05330448 AL |
2471 | return 0; |
2472 | } | |
2473 | ||
20d695a9 | 2474 | int kvm_arch_get_registers(CPUState *cs) |
05330448 | 2475 | { |
20d695a9 | 2476 | X86CPU *cpu = X86_CPU(cs); |
05330448 AL |
2477 | int ret; |
2478 | ||
20d695a9 | 2479 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); |
dbaa07c4 | 2480 | |
1bc22652 | 2481 | ret = kvm_getput_regs(cpu, 0); |
b9bec74b | 2482 | if (ret < 0) { |
05330448 | 2483 | return ret; |
b9bec74b | 2484 | } |
1bc22652 | 2485 | ret = kvm_get_xsave(cpu); |
b9bec74b | 2486 | if (ret < 0) { |
f1665b21 | 2487 | return ret; |
b9bec74b | 2488 | } |
1bc22652 | 2489 | ret = kvm_get_xcrs(cpu); |
b9bec74b | 2490 | if (ret < 0) { |
05330448 | 2491 | return ret; |
b9bec74b | 2492 | } |
1bc22652 | 2493 | ret = kvm_get_sregs(cpu); |
b9bec74b | 2494 | if (ret < 0) { |
05330448 | 2495 | return ret; |
b9bec74b | 2496 | } |
1bc22652 | 2497 | ret = kvm_get_msrs(cpu); |
b9bec74b | 2498 | if (ret < 0) { |
05330448 | 2499 | return ret; |
b9bec74b | 2500 | } |
23d02d9b | 2501 | ret = kvm_get_mp_state(cpu); |
b9bec74b | 2502 | if (ret < 0) { |
5a2e3c2e | 2503 | return ret; |
b9bec74b | 2504 | } |
1bc22652 | 2505 | ret = kvm_get_apic(cpu); |
680c1c6f JK |
2506 | if (ret < 0) { |
2507 | return ret; | |
2508 | } | |
1bc22652 | 2509 | ret = kvm_get_vcpu_events(cpu); |
b9bec74b | 2510 | if (ret < 0) { |
a0fb002c | 2511 | return ret; |
b9bec74b | 2512 | } |
1bc22652 | 2513 | ret = kvm_get_debugregs(cpu); |
b9bec74b | 2514 | if (ret < 0) { |
ff44f1a3 | 2515 | return ret; |
b9bec74b | 2516 | } |
05330448 AL |
2517 | return 0; |
2518 | } | |
2519 | ||
20d695a9 | 2520 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 2521 | { |
20d695a9 AF |
2522 | X86CPU *x86_cpu = X86_CPU(cpu); |
2523 | CPUX86State *env = &x86_cpu->env; | |
ce377af3 JK |
2524 | int ret; |
2525 | ||
276ce815 | 2526 | /* Inject NMI */ |
fc12d72e PB |
2527 | if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { |
2528 | if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { | |
2529 | qemu_mutex_lock_iothread(); | |
2530 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
2531 | qemu_mutex_unlock_iothread(); | |
2532 | DPRINTF("injected NMI\n"); | |
2533 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); | |
2534 | if (ret < 0) { | |
2535 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
2536 | strerror(-ret)); | |
2537 | } | |
2538 | } | |
2539 | if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { | |
2540 | qemu_mutex_lock_iothread(); | |
2541 | cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; | |
2542 | qemu_mutex_unlock_iothread(); | |
2543 | DPRINTF("injected SMI\n"); | |
2544 | ret = kvm_vcpu_ioctl(cpu, KVM_SMI); | |
2545 | if (ret < 0) { | |
2546 | fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n", | |
2547 | strerror(-ret)); | |
2548 | } | |
ce377af3 | 2549 | } |
276ce815 LJ |
2550 | } |
2551 | ||
4b8523ee JK |
2552 | if (!kvm_irqchip_in_kernel()) { |
2553 | qemu_mutex_lock_iothread(); | |
2554 | } | |
2555 | ||
e0723c45 PB |
2556 | /* Force the VCPU out of its inner loop to process any INIT requests |
2557 | * or (for userspace APIC, but it is cheap to combine the checks here) | |
2558 | * pending TPR access reports. | |
2559 | */ | |
2560 | if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { | |
fc12d72e PB |
2561 | if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && |
2562 | !(env->hflags & HF_SMM_MASK)) { | |
2563 | cpu->exit_request = 1; | |
2564 | } | |
2565 | if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { | |
2566 | cpu->exit_request = 1; | |
2567 | } | |
e0723c45 | 2568 | } |
05330448 | 2569 | |
e0723c45 | 2570 | if (!kvm_irqchip_in_kernel()) { |
db1669bc JK |
2571 | /* Try to inject an interrupt if the guest can accept it */ |
2572 | if (run->ready_for_interrupt_injection && | |
259186a7 | 2573 | (cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
db1669bc JK |
2574 | (env->eflags & IF_MASK)) { |
2575 | int irq; | |
2576 | ||
259186a7 | 2577 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; |
db1669bc JK |
2578 | irq = cpu_get_pic_interrupt(env); |
2579 | if (irq >= 0) { | |
2580 | struct kvm_interrupt intr; | |
2581 | ||
2582 | intr.irq = irq; | |
db1669bc | 2583 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 2584 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); |
ce377af3 JK |
2585 | if (ret < 0) { |
2586 | fprintf(stderr, | |
2587 | "KVM: injection failed, interrupt lost (%s)\n", | |
2588 | strerror(-ret)); | |
2589 | } | |
db1669bc JK |
2590 | } |
2591 | } | |
05330448 | 2592 | |
db1669bc JK |
2593 | /* If we have an interrupt but the guest is not ready to receive an |
2594 | * interrupt, request an interrupt window exit. This will | |
2595 | * cause a return to userspace as soon as the guest is ready to | |
2596 | * receive interrupts. */ | |
259186a7 | 2597 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { |
db1669bc JK |
2598 | run->request_interrupt_window = 1; |
2599 | } else { | |
2600 | run->request_interrupt_window = 0; | |
2601 | } | |
2602 | ||
2603 | DPRINTF("setting tpr\n"); | |
02e51483 | 2604 | run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); |
4b8523ee JK |
2605 | |
2606 | qemu_mutex_unlock_iothread(); | |
db1669bc | 2607 | } |
05330448 AL |
2608 | } |
2609 | ||
4c663752 | 2610 | MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 2611 | { |
20d695a9 AF |
2612 | X86CPU *x86_cpu = X86_CPU(cpu); |
2613 | CPUX86State *env = &x86_cpu->env; | |
2614 | ||
fc12d72e PB |
2615 | if (run->flags & KVM_RUN_X86_SMM) { |
2616 | env->hflags |= HF_SMM_MASK; | |
2617 | } else { | |
2618 | env->hflags &= HF_SMM_MASK; | |
2619 | } | |
b9bec74b | 2620 | if (run->if_flag) { |
05330448 | 2621 | env->eflags |= IF_MASK; |
b9bec74b | 2622 | } else { |
05330448 | 2623 | env->eflags &= ~IF_MASK; |
b9bec74b | 2624 | } |
4b8523ee JK |
2625 | |
2626 | /* We need to protect the apic state against concurrent accesses from | |
2627 | * different threads in case the userspace irqchip is used. */ | |
2628 | if (!kvm_irqchip_in_kernel()) { | |
2629 | qemu_mutex_lock_iothread(); | |
2630 | } | |
02e51483 CF |
2631 | cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); |
2632 | cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); | |
4b8523ee JK |
2633 | if (!kvm_irqchip_in_kernel()) { |
2634 | qemu_mutex_unlock_iothread(); | |
2635 | } | |
f794aa4a | 2636 | return cpu_get_mem_attrs(env); |
05330448 AL |
2637 | } |
2638 | ||
20d695a9 | 2639 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 2640 | { |
20d695a9 AF |
2641 | X86CPU *cpu = X86_CPU(cs); |
2642 | CPUX86State *env = &cpu->env; | |
232fc23b | 2643 | |
259186a7 | 2644 | if (cs->interrupt_request & CPU_INTERRUPT_MCE) { |
ab443475 JK |
2645 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ |
2646 | assert(env->mcg_cap); | |
2647 | ||
259186a7 | 2648 | cs->interrupt_request &= ~CPU_INTERRUPT_MCE; |
ab443475 | 2649 | |
dd1750d7 | 2650 | kvm_cpu_synchronize_state(cs); |
ab443475 JK |
2651 | |
2652 | if (env->exception_injected == EXCP08_DBLE) { | |
2653 | /* this means triple fault */ | |
2654 | qemu_system_reset_request(); | |
fcd7d003 | 2655 | cs->exit_request = 1; |
ab443475 JK |
2656 | return 0; |
2657 | } | |
2658 | env->exception_injected = EXCP12_MCHK; | |
2659 | env->has_error_code = 0; | |
2660 | ||
259186a7 | 2661 | cs->halted = 0; |
ab443475 JK |
2662 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { |
2663 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
2664 | } | |
2665 | } | |
2666 | ||
fc12d72e PB |
2667 | if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && |
2668 | !(env->hflags & HF_SMM_MASK)) { | |
e0723c45 PB |
2669 | kvm_cpu_synchronize_state(cs); |
2670 | do_cpu_init(cpu); | |
2671 | } | |
2672 | ||
db1669bc JK |
2673 | if (kvm_irqchip_in_kernel()) { |
2674 | return 0; | |
2675 | } | |
2676 | ||
259186a7 AF |
2677 | if (cs->interrupt_request & CPU_INTERRUPT_POLL) { |
2678 | cs->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
02e51483 | 2679 | apic_poll_irq(cpu->apic_state); |
5d62c43a | 2680 | } |
259186a7 | 2681 | if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
4601f7b0 | 2682 | (env->eflags & IF_MASK)) || |
259186a7 AF |
2683 | (cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
2684 | cs->halted = 0; | |
6792a57b | 2685 | } |
259186a7 | 2686 | if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { |
dd1750d7 | 2687 | kvm_cpu_synchronize_state(cs); |
232fc23b | 2688 | do_cpu_sipi(cpu); |
0af691d7 | 2689 | } |
259186a7 AF |
2690 | if (cs->interrupt_request & CPU_INTERRUPT_TPR) { |
2691 | cs->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
dd1750d7 | 2692 | kvm_cpu_synchronize_state(cs); |
02e51483 | 2693 | apic_handle_tpr_access_report(cpu->apic_state, env->eip, |
d362e757 JK |
2694 | env->tpr_access_type); |
2695 | } | |
0af691d7 | 2696 | |
259186a7 | 2697 | return cs->halted; |
0af691d7 MT |
2698 | } |
2699 | ||
839b5630 | 2700 | static int kvm_handle_halt(X86CPU *cpu) |
05330448 | 2701 | { |
259186a7 | 2702 | CPUState *cs = CPU(cpu); |
839b5630 AF |
2703 | CPUX86State *env = &cpu->env; |
2704 | ||
259186a7 | 2705 | if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
05330448 | 2706 | (env->eflags & IF_MASK)) && |
259186a7 AF |
2707 | !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
2708 | cs->halted = 1; | |
bb4ea393 | 2709 | return EXCP_HLT; |
05330448 AL |
2710 | } |
2711 | ||
bb4ea393 | 2712 | return 0; |
05330448 AL |
2713 | } |
2714 | ||
f7575c96 | 2715 | static int kvm_handle_tpr_access(X86CPU *cpu) |
d362e757 | 2716 | { |
f7575c96 AF |
2717 | CPUState *cs = CPU(cpu); |
2718 | struct kvm_run *run = cs->kvm_run; | |
d362e757 | 2719 | |
02e51483 | 2720 | apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, |
d362e757 JK |
2721 | run->tpr_access.is_write ? TPR_ACCESS_WRITE |
2722 | : TPR_ACCESS_READ); | |
2723 | return 1; | |
2724 | } | |
2725 | ||
f17ec444 | 2726 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 2727 | { |
38972938 | 2728 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 2729 | |
f17ec444 AF |
2730 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
2731 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
e22a25c9 | 2732 | return -EINVAL; |
b9bec74b | 2733 | } |
e22a25c9 AL |
2734 | return 0; |
2735 | } | |
2736 | ||
f17ec444 | 2737 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 AL |
2738 | { |
2739 | uint8_t int3; | |
2740 | ||
f17ec444 AF |
2741 | if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
2742 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
e22a25c9 | 2743 | return -EINVAL; |
b9bec74b | 2744 | } |
e22a25c9 AL |
2745 | return 0; |
2746 | } | |
2747 | ||
2748 | static struct { | |
2749 | target_ulong addr; | |
2750 | int len; | |
2751 | int type; | |
2752 | } hw_breakpoint[4]; | |
2753 | ||
2754 | static int nb_hw_breakpoint; | |
2755 | ||
2756 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
2757 | { | |
2758 | int n; | |
2759 | ||
b9bec74b | 2760 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 2761 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 2762 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 2763 | return n; |
b9bec74b JK |
2764 | } |
2765 | } | |
e22a25c9 AL |
2766 | return -1; |
2767 | } | |
2768 | ||
2769 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
2770 | target_ulong len, int type) | |
2771 | { | |
2772 | switch (type) { | |
2773 | case GDB_BREAKPOINT_HW: | |
2774 | len = 1; | |
2775 | break; | |
2776 | case GDB_WATCHPOINT_WRITE: | |
2777 | case GDB_WATCHPOINT_ACCESS: | |
2778 | switch (len) { | |
2779 | case 1: | |
2780 | break; | |
2781 | case 2: | |
2782 | case 4: | |
2783 | case 8: | |
b9bec74b | 2784 | if (addr & (len - 1)) { |
e22a25c9 | 2785 | return -EINVAL; |
b9bec74b | 2786 | } |
e22a25c9 AL |
2787 | break; |
2788 | default: | |
2789 | return -EINVAL; | |
2790 | } | |
2791 | break; | |
2792 | default: | |
2793 | return -ENOSYS; | |
2794 | } | |
2795 | ||
b9bec74b | 2796 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 2797 | return -ENOBUFS; |
b9bec74b JK |
2798 | } |
2799 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 2800 | return -EEXIST; |
b9bec74b | 2801 | } |
e22a25c9 AL |
2802 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
2803 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
2804 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
2805 | nb_hw_breakpoint++; | |
2806 | ||
2807 | return 0; | |
2808 | } | |
2809 | ||
2810 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
2811 | target_ulong len, int type) | |
2812 | { | |
2813 | int n; | |
2814 | ||
2815 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 2816 | if (n < 0) { |
e22a25c9 | 2817 | return -ENOENT; |
b9bec74b | 2818 | } |
e22a25c9 AL |
2819 | nb_hw_breakpoint--; |
2820 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
2821 | ||
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | void kvm_arch_remove_all_hw_breakpoints(void) | |
2826 | { | |
2827 | nb_hw_breakpoint = 0; | |
2828 | } | |
2829 | ||
2830 | static CPUWatchpoint hw_watchpoint; | |
2831 | ||
a60f24b5 | 2832 | static int kvm_handle_debug(X86CPU *cpu, |
48405526 | 2833 | struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 2834 | { |
ed2803da | 2835 | CPUState *cs = CPU(cpu); |
a60f24b5 | 2836 | CPUX86State *env = &cpu->env; |
f2574737 | 2837 | int ret = 0; |
e22a25c9 AL |
2838 | int n; |
2839 | ||
2840 | if (arch_info->exception == 1) { | |
2841 | if (arch_info->dr6 & (1 << 14)) { | |
ed2803da | 2842 | if (cs->singlestep_enabled) { |
f2574737 | 2843 | ret = EXCP_DEBUG; |
b9bec74b | 2844 | } |
e22a25c9 | 2845 | } else { |
b9bec74b JK |
2846 | for (n = 0; n < 4; n++) { |
2847 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
2848 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
2849 | case 0x0: | |
f2574737 | 2850 | ret = EXCP_DEBUG; |
e22a25c9 AL |
2851 | break; |
2852 | case 0x1: | |
f2574737 | 2853 | ret = EXCP_DEBUG; |
ff4700b0 | 2854 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2855 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2856 | hw_watchpoint.flags = BP_MEM_WRITE; | |
2857 | break; | |
2858 | case 0x3: | |
f2574737 | 2859 | ret = EXCP_DEBUG; |
ff4700b0 | 2860 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
2861 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
2862 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
2863 | break; | |
2864 | } | |
b9bec74b JK |
2865 | } |
2866 | } | |
e22a25c9 | 2867 | } |
ff4700b0 | 2868 | } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { |
f2574737 | 2869 | ret = EXCP_DEBUG; |
b9bec74b | 2870 | } |
f2574737 | 2871 | if (ret == 0) { |
ff4700b0 | 2872 | cpu_synchronize_state(cs); |
48405526 | 2873 | assert(env->exception_injected == -1); |
b0b1d690 | 2874 | |
f2574737 | 2875 | /* pass to guest */ |
48405526 BS |
2876 | env->exception_injected = arch_info->exception; |
2877 | env->has_error_code = 0; | |
b0b1d690 | 2878 | } |
e22a25c9 | 2879 | |
f2574737 | 2880 | return ret; |
e22a25c9 AL |
2881 | } |
2882 | ||
20d695a9 | 2883 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
2884 | { |
2885 | const uint8_t type_code[] = { | |
2886 | [GDB_BREAKPOINT_HW] = 0x0, | |
2887 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
2888 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
2889 | }; | |
2890 | const uint8_t len_code[] = { | |
2891 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
2892 | }; | |
2893 | int n; | |
2894 | ||
a60f24b5 | 2895 | if (kvm_sw_breakpoints_active(cpu)) { |
e22a25c9 | 2896 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 2897 | } |
e22a25c9 AL |
2898 | if (nb_hw_breakpoint > 0) { |
2899 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
2900 | dbg->arch.debugreg[7] = 0x0600; | |
2901 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
2902 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
2903 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
2904 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 2905 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
2906 | } |
2907 | } | |
2908 | } | |
4513d923 | 2909 | |
2a4dac83 JK |
2910 | static bool host_supports_vmx(void) |
2911 | { | |
2912 | uint32_t ecx, unused; | |
2913 | ||
2914 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
2915 | return ecx & CPUID_EXT_VMX; | |
2916 | } | |
2917 | ||
2918 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
2919 | ||
20d695a9 | 2920 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
2a4dac83 | 2921 | { |
20d695a9 | 2922 | X86CPU *cpu = X86_CPU(cs); |
2a4dac83 JK |
2923 | uint64_t code; |
2924 | int ret; | |
2925 | ||
2926 | switch (run->exit_reason) { | |
2927 | case KVM_EXIT_HLT: | |
2928 | DPRINTF("handle_hlt\n"); | |
4b8523ee | 2929 | qemu_mutex_lock_iothread(); |
839b5630 | 2930 | ret = kvm_handle_halt(cpu); |
4b8523ee | 2931 | qemu_mutex_unlock_iothread(); |
2a4dac83 JK |
2932 | break; |
2933 | case KVM_EXIT_SET_TPR: | |
2934 | ret = 0; | |
2935 | break; | |
d362e757 | 2936 | case KVM_EXIT_TPR_ACCESS: |
4b8523ee | 2937 | qemu_mutex_lock_iothread(); |
f7575c96 | 2938 | ret = kvm_handle_tpr_access(cpu); |
4b8523ee | 2939 | qemu_mutex_unlock_iothread(); |
d362e757 | 2940 | break; |
2a4dac83 JK |
2941 | case KVM_EXIT_FAIL_ENTRY: |
2942 | code = run->fail_entry.hardware_entry_failure_reason; | |
2943 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
2944 | code); | |
2945 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
2946 | fprintf(stderr, | |
12619721 | 2947 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
2948 | "unrestricted mode\n" |
2949 | "support, the failure can be most likely due to the guest " | |
2950 | "entering an invalid\n" | |
2951 | "state for Intel VT. For example, the guest maybe running " | |
2952 | "in big real mode\n" | |
2953 | "which is not supported on less recent Intel processors." | |
2954 | "\n\n"); | |
2955 | } | |
2956 | ret = -1; | |
2957 | break; | |
2958 | case KVM_EXIT_EXCEPTION: | |
2959 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
2960 | run->ex.exception, run->ex.error_code); | |
2961 | ret = -1; | |
2962 | break; | |
f2574737 JK |
2963 | case KVM_EXIT_DEBUG: |
2964 | DPRINTF("kvm_exit_debug\n"); | |
4b8523ee | 2965 | qemu_mutex_lock_iothread(); |
a60f24b5 | 2966 | ret = kvm_handle_debug(cpu, &run->debug.arch); |
4b8523ee | 2967 | qemu_mutex_unlock_iothread(); |
f2574737 | 2968 | break; |
50efe82c AS |
2969 | case KVM_EXIT_HYPERV: |
2970 | ret = kvm_hv_handle_exit(cpu, &run->hyperv); | |
2971 | break; | |
2a4dac83 JK |
2972 | default: |
2973 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
2974 | ret = -1; | |
2975 | break; | |
2976 | } | |
2977 | ||
2978 | return ret; | |
2979 | } | |
2980 | ||
20d695a9 | 2981 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
4513d923 | 2982 | { |
20d695a9 AF |
2983 | X86CPU *cpu = X86_CPU(cs); |
2984 | CPUX86State *env = &cpu->env; | |
2985 | ||
dd1750d7 | 2986 | kvm_cpu_synchronize_state(cs); |
b9bec74b JK |
2987 | return !(env->cr[0] & CR0_PE_MASK) || |
2988 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 2989 | } |
84b058d7 JK |
2990 | |
2991 | void kvm_arch_init_irq_routing(KVMState *s) | |
2992 | { | |
2993 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { | |
2994 | /* If kernel can't do irq routing, interrupt source | |
2995 | * override 0->2 cannot be set up as required by HPET. | |
2996 | * So we have to disable it. | |
2997 | */ | |
2998 | no_hpet = 1; | |
2999 | } | |
cc7e0ddf | 3000 | /* We know at this point that we're using the in-kernel |
614e41bc | 3001 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 3002 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf | 3003 | */ |
614e41bc | 3004 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 3005 | kvm_gsi_routing_allowed = true; |
84b058d7 | 3006 | } |
b139bd30 JK |
3007 | |
3008 | /* Classic KVM device assignment interface. Will remain x86 only. */ | |
3009 | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr, | |
3010 | uint32_t flags, uint32_t *dev_id) | |
3011 | { | |
3012 | struct kvm_assigned_pci_dev dev_data = { | |
3013 | .segnr = dev_addr->domain, | |
3014 | .busnr = dev_addr->bus, | |
3015 | .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function), | |
3016 | .flags = flags, | |
3017 | }; | |
3018 | int ret; | |
3019 | ||
3020 | dev_data.assigned_dev_id = | |
3021 | (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn; | |
3022 | ||
3023 | ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data); | |
3024 | if (ret < 0) { | |
3025 | return ret; | |
3026 | } | |
3027 | ||
3028 | *dev_id = dev_data.assigned_dev_id; | |
3029 | ||
3030 | return 0; | |
3031 | } | |
3032 | ||
3033 | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id) | |
3034 | { | |
3035 | struct kvm_assigned_pci_dev dev_data = { | |
3036 | .assigned_dev_id = dev_id, | |
3037 | }; | |
3038 | ||
3039 | return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data); | |
3040 | } | |
3041 | ||
3042 | static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id, | |
3043 | uint32_t irq_type, uint32_t guest_irq) | |
3044 | { | |
3045 | struct kvm_assigned_irq assigned_irq = { | |
3046 | .assigned_dev_id = dev_id, | |
3047 | .guest_irq = guest_irq, | |
3048 | .flags = irq_type, | |
3049 | }; | |
3050 | ||
3051 | if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) { | |
3052 | return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq); | |
3053 | } else { | |
3054 | return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq); | |
3055 | } | |
3056 | } | |
3057 | ||
3058 | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi, | |
3059 | uint32_t guest_irq) | |
3060 | { | |
3061 | uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX | | |
3062 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX); | |
3063 | ||
3064 | return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq); | |
3065 | } | |
3066 | ||
3067 | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked) | |
3068 | { | |
3069 | struct kvm_assigned_pci_dev dev_data = { | |
3070 | .assigned_dev_id = dev_id, | |
3071 | .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0, | |
3072 | }; | |
3073 | ||
3074 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data); | |
3075 | } | |
3076 | ||
3077 | static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id, | |
3078 | uint32_t type) | |
3079 | { | |
3080 | struct kvm_assigned_irq assigned_irq = { | |
3081 | .assigned_dev_id = dev_id, | |
3082 | .flags = type, | |
3083 | }; | |
3084 | ||
3085 | return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq); | |
3086 | } | |
3087 | ||
3088 | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi) | |
3089 | { | |
3090 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX | | |
3091 | (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX)); | |
3092 | } | |
3093 | ||
3094 | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq) | |
3095 | { | |
3096 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI | | |
3097 | KVM_DEV_IRQ_GUEST_MSI, virq); | |
3098 | } | |
3099 | ||
3100 | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id) | |
3101 | { | |
3102 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI | | |
3103 | KVM_DEV_IRQ_HOST_MSI); | |
3104 | } | |
3105 | ||
3106 | bool kvm_device_msix_supported(KVMState *s) | |
3107 | { | |
3108 | /* The kernel lacks a corresponding KVM_CAP, so we probe by calling | |
3109 | * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */ | |
3110 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT; | |
3111 | } | |
3112 | ||
3113 | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id, | |
3114 | uint32_t nr_vectors) | |
3115 | { | |
3116 | struct kvm_assigned_msix_nr msix_nr = { | |
3117 | .assigned_dev_id = dev_id, | |
3118 | .entry_nr = nr_vectors, | |
3119 | }; | |
3120 | ||
3121 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr); | |
3122 | } | |
3123 | ||
3124 | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector, | |
3125 | int virq) | |
3126 | { | |
3127 | struct kvm_assigned_msix_entry msix_entry = { | |
3128 | .assigned_dev_id = dev_id, | |
3129 | .gsi = virq, | |
3130 | .entry = vector, | |
3131 | }; | |
3132 | ||
3133 | return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry); | |
3134 | } | |
3135 | ||
3136 | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id) | |
3137 | { | |
3138 | return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX | | |
3139 | KVM_DEV_IRQ_GUEST_MSIX, 0); | |
3140 | } | |
3141 | ||
3142 | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id) | |
3143 | { | |
3144 | return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX | | |
3145 | KVM_DEV_IRQ_HOST_MSIX); | |
3146 | } | |
9e03a040 FB |
3147 | |
3148 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | |
dc9f06ca | 3149 | uint64_t address, uint32_t data, PCIDevice *dev) |
9e03a040 FB |
3150 | { |
3151 | return 0; | |
3152 | } | |
1850b6b7 EA |
3153 | |
3154 | int kvm_arch_msi_data_to_gsi(uint32_t data) | |
3155 | { | |
3156 | abort(); | |
3157 | } |