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[mirror_qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c
AS		 28#include "hyperv.h"
29
022c62cb 30#include "exec/gdbstub.h"
1de7afc9
PB		 31#include "qemu/host-utils.h"
32#include "qemu/config-file.h"
1c4a55db 33#include "qemu/error-report.h"
0d09e41a
PB		 34#include "hw/i386/pc.h"
35#include "hw/i386/apic.h"
e0723c45
PB		 36#include "hw/i386/apic_internal.h"
37#include "hw/i386/apic-msidef.h"
50efe82c 38
022c62cb 39#include "exec/ioport.h"
73aa529a 40#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 41#include "hw/pci/pci.h"
15eafc2e 42#include "hw/pci/msi.h"
68bfd0ad 43#include "migration/migration.h"
4c663752 44#include "exec/memattrs.h"
05330448
AL		 45
46//#define DEBUG_KVM
47
48#ifdef DEBUG_KVM
8c0d577e 49#define DPRINTF(fmt, ...) \
05330448
AL		 50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51#else
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { } while (0)
54#endif
55
1a03675d
GC		 56#define MSR_KVM_WALL_CLOCK 0x11
57#define MSR_KVM_SYSTEM_TIME 0x12
58
d1138251
EH		 59/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
60 * 255 kvm_msr_entry structs */
61#define MSR_BUF_SIZE 4096
d71b62a1 62
c0532a76
MT		 63#ifndef BUS_MCEERR_AR
64#define BUS_MCEERR_AR 4
65#endif
66#ifndef BUS_MCEERR_AO
67#define BUS_MCEERR_AO 5
68#endif
69
94a8d39a
JK		 70const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75};
25d2e361 76
c3a3a7d3
JK		 77static bool has_msr_star;
78static bool has_msr_hsave_pa;
c9b8f6b6 79static bool has_msr_tsc_aux;
f28558d3 80static bool has_msr_tsc_adjust;
aa82ba54 81static bool has_msr_tsc_deadline;
df67696e 82static bool has_msr_feature_control;
c5999bfc 83static bool has_msr_async_pf_en;
bc9a839d 84static bool has_msr_pv_eoi_en;
21e87c46 85static bool has_msr_misc_enable;
fc12d72e 86static bool has_msr_smbase;
79e9ebeb 87static bool has_msr_bndcfgs;
917367aa 88static bool has_msr_kvm_steal_time;
25d2e361 89static int lm_capable_kernel;
7bc3d711
PB		 90static bool has_msr_hv_hypercall;
91static bool has_msr_hv_vapic;
48a5f3bc 92static bool has_msr_hv_tsc;
f2a53c9e 93static bool has_msr_hv_crash;
744b8a94 94static bool has_msr_hv_reset;
8c145d7c 95static bool has_msr_hv_vpindex;
46eb8f98 96static bool has_msr_hv_runtime;
866eea9a 97static bool has_msr_hv_synic;
ff99aa64 98static bool has_msr_hv_stimer;
d1ae67f6 99static bool has_msr_mtrr;
18cd2c17 100static bool has_msr_xss;
b827df58 101
0d894367
PB		 102static bool has_msr_architectural_pmu;
103static uint32_t num_architectural_pmu_counters;
104
28143b40
TH		 105static int has_xsave;
106static int has_xcrs;
107static int has_pit_state2;
108
494e95e9
CP		 109static struct kvm_cpuid2 *cpuid_cache;
110
28143b40
TH		 111int kvm_has_pit_state2(void)
112{
113 return has_pit_state2;
114}
115
355023f2
PB		 116bool kvm_has_smm(void)
117{
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119}
120
1d31f66b
PM		 121bool kvm_allows_irq0_override(void)
122{
123 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
124}
125
0fd7e098
LL		 126static int kvm_get_tsc(CPUState *cs)
127{
128 X86CPU *cpu = X86_CPU(cs);
129 CPUX86State *env = &cpu->env;
130 struct {
131 struct kvm_msrs info;
132 struct kvm_msr_entry entries[1];
133 } msr_data;
134 int ret;
135
136 if (env->tsc_valid) {
137 return 0;
138 }
139
140 msr_data.info.nmsrs = 1;
141 msr_data.entries[0].index = MSR_IA32_TSC;
142 env->tsc_valid = !runstate_is_running();
143
144 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
145 if (ret < 0) {
146 return ret;
147 }
148
48e1a45c 149 assert(ret == 1);
0fd7e098
LL		 150 env->tsc = msr_data.entries[0].data;
151 return 0;
152}
153
154static inline void do_kvm_synchronize_tsc(void *arg)
155{
156 CPUState *cpu = arg;
157
158 kvm_get_tsc(cpu);
159}
160
161void kvm_synchronize_all_tsc(void)
162{
163 CPUState *cpu;
164
165 if (kvm_enabled()) {
166 CPU_FOREACH(cpu) {
167 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
168 }
169 }
170}
171
b827df58
AK		 172static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
173{
174 struct kvm_cpuid2 *cpuid;
175 int r, size;
176
177 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 178 cpuid = g_malloc0(size);
b827df58
AK		 179 cpuid->nent = max;
180 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 181 if (r == 0 && cpuid->nent >= max) {
182 r = -E2BIG;
183 }
b827df58
AK		 184 if (r < 0) {
185 if (r == -E2BIG) {
7267c094 186 g_free(cpuid);
b827df58
AK		 187 return NULL;
188 } else {
189 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
190 strerror(-r));
191 exit(1);
192 }
193 }
194 return cpuid;
195}
196
dd87f8a6
EH		 197/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
198 * for all entries.
199 */
200static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
201{
202 struct kvm_cpuid2 *cpuid;
203 int max = 1;
494e95e9
CP		 204
205 if (cpuid_cache != NULL) {
206 return cpuid_cache;
207 }
dd87f8a6
EH		 208 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
209 max *= 2;
210 }
494e95e9 211 cpuid_cache = cpuid;
dd87f8a6
EH		 212 return cpuid;
213}
214
a443bc34 215static const struct kvm_para_features {
0c31b744
GC		 216 int cap;
217 int feature;
218} para_features[] = {
219 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
220 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
221 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 222 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 223};
224
ba9bc59e 225static int get_para_features(KVMState *s)
0c31b744
GC		 226{
227 int i, features = 0;
228
8e03c100 229 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 230 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 231 features |= (1 << para_features[i].feature);
232 }
233 }
234
235 return features;
236}
0c31b744
GC		 237
238
829ae2f9
EH		 239/* Returns the value for a specific register on the cpuid entry
240 */
241static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
242{
243 uint32_t ret = 0;
244 switch (reg) {
245 case R_EAX:
246 ret = entry->eax;
247 break;
248 case R_EBX:
249 ret = entry->ebx;
250 break;
251 case R_ECX:
252 ret = entry->ecx;
253 break;
254 case R_EDX:
255 ret = entry->edx;
256 break;
257 }
258 return ret;
259}
260
4fb73f1d
EH		 261/* Find matching entry for function/index on kvm_cpuid2 struct
262 */
263static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
264 uint32_t function,
265 uint32_t index)
266{
267 int i;
268 for (i = 0; i < cpuid->nent; ++i) {
269 if (cpuid->entries[i].function == function &&
270 cpuid->entries[i].index == index) {
271 return &cpuid->entries[i];
272 }
273 }
274 /* not found: */
275 return NULL;
276}
277
ba9bc59e 278uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 279 uint32_t index, int reg)
b827df58
AK		 280{
281 struct kvm_cpuid2 *cpuid;
b827df58
AK		 282 uint32_t ret = 0;
283 uint32_t cpuid_1_edx;
8c723b79 284 bool found = false;
b827df58 285
dd87f8a6 286 cpuid = get_supported_cpuid(s);
b827df58 287
4fb73f1d
EH		 288 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
289 if (entry) {
290 found = true;
291 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 292 }
293
7b46e5ce
EH		 294 /* Fixups for the data returned by KVM, below */
295
c2acb022
EH		 296 if (function == 1 && reg == R_EDX) {
297 /* KVM before 2.6.30 misreports the following features */
298 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 299 } else if (function == 1 && reg == R_ECX) {
300 /* We can set the hypervisor flag, even if KVM does not return it on
301 * GET_SUPPORTED_CPUID
302 */
303 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 304 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
305 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
306 * and the irqchip is in the kernel.
307 */
308 if (kvm_irqchip_in_kernel() &&
309 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
310 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
311 }
41e5e76d
EH		 312
313 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
314 * without the in-kernel irqchip
315 */
316 if (!kvm_irqchip_in_kernel()) {
317 ret &= ~CPUID_EXT_X2APIC;
b827df58 318 }
28b8e4d0
JK		 319 } else if (function == 6 && reg == R_EAX) {
320 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 321 } else if (function == 0x80000001 && reg == R_EDX) {
322 /* On Intel, kvm returns cpuid according to the Intel spec,
323 * so add missing bits according to the AMD spec:
324 */
325 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
326 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 327 }
328
0c31b744 329 /* fallback for older kernels */
8c723b79 330 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 331 ret = get_para_features(s);
b9bec74b 332 }
0c31b744
GC		 333
334 return ret;
bb0300dc 335}
bb0300dc 336
3c85e74f
HY		 337typedef struct HWPoisonPage {
338 ram_addr_t ram_addr;
339 QLIST_ENTRY(HWPoisonPage) list;
340} HWPoisonPage;
341
342static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
343 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
344
345static void kvm_unpoison_all(void *param)
346{
347 HWPoisonPage *page, *next_page;
348
349 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
350 QLIST_REMOVE(page, list);
351 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 352 g_free(page);
3c85e74f
HY		 353 }
354}
355
3c85e74f
HY		 356static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
357{
358 HWPoisonPage *page;
359
360 QLIST_FOREACH(page, &hwpoison_page_list, list) {
361 if (page->ram_addr == ram_addr) {
362 return;
363 }
364 }
ab3ad07f 365 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 366 page->ram_addr = ram_addr;
367 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
368}
369
e7701825
MT		 370static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
371 int *max_banks)
372{
373 int r;
374
14a09518 375 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 376 if (r > 0) {
377 *max_banks = r;
378 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
379 }
380 return -ENOSYS;
381}
382
bee615d4 383static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 384{
bee615d4 385 CPUX86State *env = &cpu->env;
c34d440a
JK		 386 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
387 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
388 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 389
c34d440a
JK		 390 if (code == BUS_MCEERR_AR) {
391 status |= MCI_STATUS_AR | 0x134;
392 mcg_status |= MCG_STATUS_EIPV;
393 } else {
394 status |= 0xc0;
395 mcg_status |= MCG_STATUS_RIPV;
419fb20a 396 }
8c5cf3b6 397 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 398 (MCM_ADDR_PHYS << 6) | 0xc,
399 cpu_x86_support_mca_broadcast(env) ?
400 MCE_INJECT_BROADCAST : 0);
419fb20a 401}
419fb20a
JK		 402
403static void hardware_memory_error(void)
404{
405 fprintf(stderr, "Hardware memory error!\n");
406 exit(1);
407}
408
20d695a9 409int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 410{
20d695a9
AF		 411 X86CPU *cpu = X86_CPU(c);
412 CPUX86State *env = &cpu->env;
419fb20a 413 ram_addr_t ram_addr;
a8170e5e 414 hwaddr paddr;
419fb20a
JK		 415
416 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 417 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
07bdaa41
PB		 418 ram_addr = qemu_ram_addr_from_host(addr);
419 if (ram_addr == RAM_ADDR_INVALID ||
a60f24b5 420 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 421 fprintf(stderr, "Hardware memory error for memory used by "
422 "QEMU itself instead of guest system!\n");
423 /* Hope we are lucky for AO MCE */
424 if (code == BUS_MCEERR_AO) {
425 return 0;
426 } else {
427 hardware_memory_error();
428 }
429 }
3c85e74f 430 kvm_hwpoison_page_add(ram_addr);
bee615d4 431 kvm_mce_inject(cpu, paddr, code);
e56ff191 432 } else {
419fb20a
JK		 433 if (code == BUS_MCEERR_AO) {
434 return 0;
435 } else if (code == BUS_MCEERR_AR) {
436 hardware_memory_error();
437 } else {
438 return 1;
439 }
440 }
441 return 0;
442}
443
444int kvm_arch_on_sigbus(int code, void *addr)
445{
182735ef
AF		 446 X86CPU *cpu = X86_CPU(first_cpu);
447
448 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 449 ram_addr_t ram_addr;
a8170e5e 450 hwaddr paddr;
419fb20a
JK		 451
452 /* Hope we are lucky for AO MCE */
07bdaa41
PB		 453 ram_addr = qemu_ram_addr_from_host(addr);
454 if (ram_addr == RAM_ADDR_INVALID ||
182735ef 455 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 456 addr, &paddr)) {
419fb20a
JK		 457 fprintf(stderr, "Hardware memory error for memory used by "
458 "QEMU itself instead of guest system!: %p\n", addr);
459 return 0;
460 }
3c85e74f 461 kvm_hwpoison_page_add(ram_addr);
182735ef 462 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 463 } else {
419fb20a
JK		 464 if (code == BUS_MCEERR_AO) {
465 return 0;
466 } else if (code == BUS_MCEERR_AR) {
467 hardware_memory_error();
468 } else {
469 return 1;
470 }
471 }
472 return 0;
473}
e7701825 474
1bc22652 475static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 476{
1bc22652
AF		 477 CPUX86State *env = &cpu->env;
478
ab443475
JK		 479 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
480 unsigned int bank, bank_num = env->mcg_cap & 0xff;
481 struct kvm_x86_mce mce;
482
483 env->exception_injected = -1;
484
485 /*
486 * There must be at least one bank in use if an MCE is pending.
487 * Find it and use its values for the event injection.
488 */
489 for (bank = 0; bank < bank_num; bank++) {
490 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
491 break;
492 }
493 }
494 assert(bank < bank_num);
495
496 mce.bank = bank;
497 mce.status = env->mce_banks[bank * 4 + 1];
498 mce.mcg_status = env->mcg_status;
499 mce.addr = env->mce_banks[bank * 4 + 2];
500 mce.misc = env->mce_banks[bank * 4 + 3];
501
1bc22652 502 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 503 }
ab443475
JK		 504 return 0;
505}
506
1dfb4dd9 507static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 508{
317ac620 509 CPUX86State *env = opaque;
b8cc45d6
GC		 510
511 if (running) {
512 env->tsc_valid = false;
513 }
514}
515
83b17af5 516unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 517{
83b17af5 518 X86CPU *cpu = X86_CPU(cs);
7e72a45c 519 return cpu->apic_id;
b164e48e
EH		 520}
521
92067bf4
IM		 522#ifndef KVM_CPUID_SIGNATURE_NEXT
523#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
524#endif
525
526static bool hyperv_hypercall_available(X86CPU *cpu)
527{
528 return cpu->hyperv_vapic ||
529 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
530}
531
532static bool hyperv_enabled(X86CPU *cpu)
533{
7bc3d711
PB		 534 CPUState *cs = CPU(cpu);
535 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
536 (hyperv_hypercall_available(cpu) ||
48a5f3bc 537 cpu->hyperv_time ||
f2a53c9e 538 cpu->hyperv_relaxed_timing ||
744b8a94 539 cpu->hyperv_crash ||
8c145d7c 540 cpu->hyperv_reset ||
46eb8f98 541 cpu->hyperv_vpindex ||
866eea9a 542 cpu->hyperv_runtime ||
ff99aa64
AS		 543 cpu->hyperv_synic ||
544 cpu->hyperv_stimer);
92067bf4
IM		 545}
546
5031283d
HZ		 547static int kvm_arch_set_tsc_khz(CPUState *cs)
548{
549 X86CPU *cpu = X86_CPU(cs);
550 CPUX86State *env = &cpu->env;
551 int r;
552
553 if (!env->tsc_khz) {
554 return 0;
555 }
556
557 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
558 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
559 -ENOTSUP;
560 if (r < 0) {
561 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
562 * TSC frequency doesn't match the one we want.
563 */
564 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
565 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
566 -ENOTSUP;
567 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
568 error_report("warning: TSC frequency mismatch between "
569 "VM and host, and TSC scaling unavailable");
570 return r;
571 }
572 }
573
574 return 0;
575}
576
68bfd0ad
MT		 577static Error *invtsc_mig_blocker;
578
f8bb0565 579#define KVM_MAX_CPUID_ENTRIES 100
0893d460 580
20d695a9 581int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 582{
583 struct {
486bd5a2 584 struct kvm_cpuid2 cpuid;
f8bb0565 585 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 586 } QEMU_PACKED cpuid_data;
20d695a9
AF		 587 X86CPU *cpu = X86_CPU(cs);
588 CPUX86State *env = &cpu->env;
486bd5a2 589 uint32_t limit, i, j, cpuid_i;
a33609ca 590 uint32_t unused;
bb0300dc 591 struct kvm_cpuid_entry2 *c;
bb0300dc 592 uint32_t signature[3];
234cc647 593 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 594 int r;
05330448 595
ef4cbe14
SW		 596 memset(&cpuid_data, 0, sizeof(cpuid_data));
597
05330448
AL		 598 cpuid_i = 0;
599
bb0300dc 600 /* Paravirtualization CPUIDs */
234cc647
PB		 601 if (hyperv_enabled(cpu)) {
602 c = &cpuid_data.entries[cpuid_i++];
603 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 604 if (!cpu->hyperv_vendor_id) {
605 memcpy(signature, "Microsoft Hv", 12);
606 } else {
607 size_t len = strlen(cpu->hyperv_vendor_id);
608
609 if (len > 12) {
610 error_report("hv-vendor-id truncated to 12 characters");
611 len = 12;
612 }
613 memset(signature, 0, 12);
614 memcpy(signature, cpu->hyperv_vendor_id, len);
615 }
eab70139 616 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 617 c->ebx = signature[0];
618 c->ecx = signature[1];
619 c->edx = signature[2];
0c31b744 620
234cc647
PB		 621 c = &cpuid_data.entries[cpuid_i++];
622 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 623 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
624 c->eax = signature[0];
234cc647
PB		 625 c->ebx = 0;
626 c->ecx = 0;
627 c->edx = 0;
eab70139
VR		 628
629 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 630 c->function = HYPERV_CPUID_VERSION;
631 c->eax = 0x00001bbc;
632 c->ebx = 0x00060001;
633
634 c = &cpuid_data.entries[cpuid_i++];
eab70139 635 c->function = HYPERV_CPUID_FEATURES;
92067bf4 636 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 637 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
638 }
92067bf4 639 if (cpu->hyperv_vapic) {
eab70139
VR		 640 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
641 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
7bc3d711 642 has_msr_hv_vapic = true;
eab70139 643 }
48a5f3bc
VR		 644 if (cpu->hyperv_time &&
645 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
646 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
647 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
648 c->eax |= 0x200;
649 has_msr_hv_tsc = true;
650 }
f2a53c9e
AS		 651 if (cpu->hyperv_crash && has_msr_hv_crash) {
652 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
653 }
4467c6c1 654 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
744b8a94
AS		 655 if (cpu->hyperv_reset && has_msr_hv_reset) {
656 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
657 }
8c145d7c
AS		 658 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
659 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
660 }
46eb8f98
AS		 661 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
662 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
663 }
866eea9a
AS		 664 if (cpu->hyperv_synic) {
665 int sint;
666
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
673 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
674 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
675 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
676 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
677 }
678 }
ff99aa64
AS		 679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
684 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
685 }
eab70139 686 c = &cpuid_data.entries[cpuid_i++];
eab70139 687 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 688 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 689 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
690 }
7bc3d711 691 if (has_msr_hv_vapic) {
eab70139
VR		 692 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
693 }
92067bf4 694 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 695
696 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 697 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
698 c->eax = 0x40;
699 c->ebx = 0x40;
700
234cc647 701 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 702 has_msr_hv_hypercall = true;
eab70139
VR		 703 }
704
f522d2ac
AW		 705 if (cpu->expose_kvm) {
706 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
707 c = &cpuid_data.entries[cpuid_i++];
708 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 709 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 710 c->ebx = signature[0];
711 c->ecx = signature[1];
712 c->edx = signature[2];
234cc647 713
f522d2ac
AW		 714 c = &cpuid_data.entries[cpuid_i++];
715 c->function = KVM_CPUID_FEATURES | kvm_base;
716 c->eax = env->features[FEAT_KVM];
234cc647 717
f522d2ac 718 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 719
f522d2ac 720 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 721
f522d2ac
AW		 722 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
723 }
917367aa 724
a33609ca 725 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 726
727 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 728 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
729 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
730 abort();
731 }
bb0300dc 732 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 733
734 switch (i) {
a36b1029
AL		 735 case 2: {
736 /* Keep reading function 2 till all the input is received */
737 int times;
738
a36b1029 739 c->function = i;
a33609ca
AL		 740 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
741 KVM_CPUID_FLAG_STATE_READ_NEXT;
742 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
743 times = c->eax & 0xff;
a36b1029
AL		 744
745 for (j = 1; j < times; ++j) {
f8bb0565
IM		 746 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
747 fprintf(stderr, "cpuid_data is full, no space for "
748 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
749 abort();
750 }
a33609ca 751 c = &cpuid_data.entries[cpuid_i++];
a36b1029 752 c->function = i;
a33609ca
AL		 753 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
754 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 755 }
756 break;
757 }
486bd5a2
AL		 758 case 4:
759 case 0xb:
760 case 0xd:
761 for (j = 0; ; j++) {
31e8c696
AP		 762 if (i == 0xd && j == 64) {
763 break;
764 }
486bd5a2
AL		 765 c->function = i;
766 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
767 c->index = j;
a33609ca 768 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 769
b9bec74b 770 if (i == 4 && c->eax == 0) {
486bd5a2 771 break;
b9bec74b
JK		 772 }
773 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 774 break;
b9bec74b
JK		 775 }
776 if (i == 0xd && c->eax == 0) {
31e8c696 777 continue;
b9bec74b 778 }
f8bb0565
IM		 779 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
780 fprintf(stderr, "cpuid_data is full, no space for "
781 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
782 abort();
783 }
a33609ca 784 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 785 }
786 break;
787 default:
486bd5a2 788 c->function = i;
a33609ca
AL		 789 c->flags = 0;
790 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 791 break;
792 }
05330448 793 }
0d894367
PB		 794
795 if (limit >= 0x0a) {
796 uint32_t ver;
797
798 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
799 if ((ver & 0xff) > 0) {
800 has_msr_architectural_pmu = true;
801 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
802
803 /* Shouldn't be more than 32, since that's the number of bits
804 * available in EBX to tell us _which_ counters are available.
805 * Play it safe.
806 */
807 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
808 num_architectural_pmu_counters = MAX_GP_COUNTERS;
809 }
810 }
811 }
812
a33609ca 813 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 814
815 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 816 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
817 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
818 abort();
819 }
bb0300dc 820 c = &cpuid_data.entries[cpuid_i++];
05330448 821
05330448 822 c->function = i;
a33609ca
AL		 823 c->flags = 0;
824 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 825 }
826
b3baa152
BW		 827 /* Call Centaur's CPUID instructions they are supported. */
828 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 829 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
830
831 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 832 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
833 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
834 abort();
835 }
b3baa152
BW		 836 c = &cpuid_data.entries[cpuid_i++];
837
838 c->function = i;
839 c->flags = 0;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
841 }
842 }
843
05330448
AL		 844 cpuid_data.cpuid.nent = cpuid_i;
845
e7701825 846 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 847 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 848 (CPUID_MCE | CPUID_MCA)
a60f24b5 849 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 850 uint64_t mcg_cap, unsupported_caps;
e7701825 851 int banks;
32a42024 852 int ret;
e7701825 853
a60f24b5 854 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 855 if (ret < 0) {
856 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
857 return ret;
e7701825 858 }
75d49497 859
2590f15b 860 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 861 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 862 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 863 return -ENOTSUP;
75d49497 864 }
49b69cbf 865
5120901a
EH		 866 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
867 if (unsupported_caps) {
868 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
869 unsupported_caps);
870 }
871
2590f15b
EH		 872 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
873 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 874 if (ret < 0) {
875 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
876 return ret;
877 }
e7701825 878 }
e7701825 879
b8cc45d6
GC		 880 qemu_add_vm_change_state_handler(cpu_update_state, env);
881
df67696e
LJ		 882 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
883 if (c) {
884 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
885 !!(c->ecx & CPUID_EXT_SMX);
886 }
887
68bfd0ad
MT		 888 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
889 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
890 /* for migration */
891 error_setg(&invtsc_mig_blocker,
892 "State blocked by non-migratable CPU device"
893 " (invtsc flag)");
894 migrate_add_blocker(invtsc_mig_blocker);
895 /* for savevm */
896 vmstate_x86_cpu.unmigratable = 1;
897 }
898
7e680753 899 cpuid_data.cpuid.padding = 0;
1bc22652 900 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 901 if (r) {
902 return r;
903 }
e7429073 904
5031283d
HZ		 905 r = kvm_arch_set_tsc_khz(cs);
906 if (r < 0) {
907 return r;
e7429073 908 }
e7429073 909
bcffbeeb
HZ		 910 /* vcpu's TSC frequency is either specified by user, or following
911 * the value used by KVM if the former is not present. In the
912 * latter case, we query it from KVM and record in env->tsc_khz,
913 * so that vcpu's TSC frequency can be migrated later via this field.
914 */
915 if (!env->tsc_khz) {
916 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
917 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
918 -ENOTSUP;
919 if (r > 0) {
920 env->tsc_khz = r;
921 }
922 }
923
28143b40 924 if (has_xsave) {
fabacc0f
JK		 925 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
926 }
d71b62a1 927 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 928
d1ae67f6
AW		 929 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
930 has_msr_mtrr = true;
931 }
273c515c
PB		 932 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
933 has_msr_tsc_aux = false;
934 }
d1ae67f6 935
e7429073 936 return 0;
05330448
AL		 937}
938
50a2c6e5 939void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 940{
20d695a9 941 CPUX86State *env = &cpu->env;
dd673288 942
e73223a5 943 env->exception_injected = -1;
0e607a80 944 env->interrupt_injected = -1;
1a5e9d2f 945 env->xcr0 = 1;
ddced198 946 if (kvm_irqchip_in_kernel()) {
dd673288 947 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 948 KVM_MP_STATE_UNINITIALIZED;
949 } else {
950 env->mp_state = KVM_MP_STATE_RUNNABLE;
951 }
caa5af0f
JK		 952}
953
e0723c45
PB		 954void kvm_arch_do_init_vcpu(X86CPU *cpu)
955{
956 CPUX86State *env = &cpu->env;
957
958 /* APs get directly into wait-for-SIPI state. */
959 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
960 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
961 }
962}
963
c3a3a7d3 964static int kvm_get_supported_msrs(KVMState *s)
05330448 965{
75b10c43 966 static int kvm_supported_msrs;
c3a3a7d3 967 int ret = 0;
05330448
AL		 968
969 /* first time */
75b10c43 970 if (kvm_supported_msrs == 0) {
05330448
AL		 971 struct kvm_msr_list msr_list, *kvm_msr_list;
972
75b10c43 973 kvm_supported_msrs = -1;
05330448
AL		 974
975 /* Obtain MSR list from KVM. These are the MSRs that we must
976 * save/restore */
4c9f7372 977 msr_list.nmsrs = 0;
c3a3a7d3 978 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 979 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 980 return ret;
6fb6d245 981 }
d9db889f
JK		 982 /* Old kernel modules had a bug and could write beyond the provided
983 memory. Allocate at least a safe amount of 1K. */
7267c094 984 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 985 msr_list.nmsrs *
986 sizeof(msr_list.indices[0])));
05330448 987
55308450 988 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 989 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 990 if (ret >= 0) {
991 int i;
992
993 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
994 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 995 has_msr_star = true;
75b10c43
MT		 996 continue;
997 }
998 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 999 has_msr_hsave_pa = true;
75b10c43 1000 continue;
05330448 1001 }
c9b8f6b6
AS		 1002 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1003 has_msr_tsc_aux = true;
1004 continue;
1005 }
f28558d3
WA		 1006 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1007 has_msr_tsc_adjust = true;
1008 continue;
1009 }
aa82ba54
LJ		 1010 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1011 has_msr_tsc_deadline = true;
1012 continue;
1013 }
fc12d72e
PB		 1014 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1015 has_msr_smbase = true;
1016 continue;
1017 }
21e87c46
AK		 1018 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1019 has_msr_misc_enable = true;
1020 continue;
1021 }
79e9ebeb
LJ		 1022 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1023 has_msr_bndcfgs = true;
1024 continue;
1025 }
18cd2c17
WL		 1026 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1027 has_msr_xss = true;
1028 continue;
1029 }
f2a53c9e
AS		 1030 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1031 has_msr_hv_crash = true;
1032 continue;
1033 }
744b8a94
AS		 1034 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1035 has_msr_hv_reset = true;
1036 continue;
1037 }
8c145d7c
AS		 1038 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1039 has_msr_hv_vpindex = true;
1040 continue;
1041 }
46eb8f98
AS		 1042 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1043 has_msr_hv_runtime = true;
1044 continue;
1045 }
866eea9a
AS		 1046 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1047 has_msr_hv_synic = true;
1048 continue;
1049 }
ff99aa64
AS		 1050 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1051 has_msr_hv_stimer = true;
1052 continue;
1053 }
05330448
AL		 1054 }
1055 }
1056
7267c094 1057 g_free(kvm_msr_list);
05330448
AL		 1058 }
1059
c3a3a7d3 1060 return ret;
05330448
AL		 1061}
1062
6410848b
PB		 1063static Notifier smram_machine_done;
1064static KVMMemoryListener smram_listener;
1065static AddressSpace smram_address_space;
1066static MemoryRegion smram_as_root;
1067static MemoryRegion smram_as_mem;
1068
1069static void register_smram_listener(Notifier *n, void *unused)
1070{
1071 MemoryRegion *smram =
1072 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1073
1074 /* Outer container... */
1075 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1076 memory_region_set_enabled(&smram_as_root, true);
1077
1078 /* ... with two regions inside: normal system memory with low
1079 * priority, and...
1080 */
1081 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1082 get_system_memory(), 0, ~0ull);
1083 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1084 memory_region_set_enabled(&smram_as_mem, true);
1085
1086 if (smram) {
1087 /* ... SMRAM with higher priority */
1088 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1089 memory_region_set_enabled(smram, true);
1090 }
1091
1092 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1093 kvm_memory_listener_register(kvm_state, &smram_listener,
1094 &smram_address_space, 1);
1095}
1096
b16565b3 1097int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1098{
11076198 1099 uint64_t identity_base = 0xfffbc000;
39d6960a 1100 uint64_t shadow_mem;
20420430 1101 int ret;
25d2e361 1102 struct utsname utsname;
20420430 1103
28143b40
TH		 1104#ifdef KVM_CAP_XSAVE
1105 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1106#endif
1107
1108#ifdef KVM_CAP_XCRS
1109 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1110#endif
1111
1112#ifdef KVM_CAP_PIT_STATE2
1113 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1114#endif
1115
c3a3a7d3 1116 ret = kvm_get_supported_msrs(s);
20420430 1117 if (ret < 0) {
20420430
SY		 1118 return ret;
1119 }
25d2e361
MT		 1120
1121 uname(&utsname);
1122 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1123
4c5b10b7 1124 /*
11076198
JK		 1125 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1126 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1127 * Since these must be part of guest physical memory, we need to allocate
1128 * them, both by setting their start addresses in the kernel and by
1129 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1130 *
1131 * Older KVM versions may not support setting the identity map base. In
1132 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1133 * size.
4c5b10b7 1134 */
11076198
JK		 1135 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1136 /* Allows up to 16M BIOSes. */
1137 identity_base = 0xfeffc000;
1138
1139 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1140 if (ret < 0) {
1141 return ret;
1142 }
4c5b10b7 1143 }
e56ff191 1144
11076198
JK		 1145 /* Set TSS base one page after EPT identity map. */
1146 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1147 if (ret < 0) {
1148 return ret;
1149 }
1150
11076198
JK		 1151 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1152 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1153 if (ret < 0) {
11076198 1154 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1155 return ret;
1156 }
3c85e74f 1157 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1158
4689b77b 1159 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1160 if (shadow_mem != -1) {
1161 shadow_mem /= 4096;
1162 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1163 if (ret < 0) {
1164 return ret;
39d6960a
JK		 1165 }
1166 }
6410848b
PB		 1167
1168 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1169 smram_machine_done.notify = register_smram_listener;
1170 qemu_add_machine_init_done_notifier(&smram_machine_done);
1171 }
11076198 1172 return 0;
05330448 1173}
b9bec74b 1174
05330448
AL		 1175static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1176{
1177 lhs->selector = rhs->selector;
1178 lhs->base = rhs->base;
1179 lhs->limit = rhs->limit;
1180 lhs->type = 3;
1181 lhs->present = 1;
1182 lhs->dpl = 3;
1183 lhs->db = 0;
1184 lhs->s = 1;
1185 lhs->l = 0;
1186 lhs->g = 0;
1187 lhs->avl = 0;
1188 lhs->unusable = 0;
1189}
1190
1191static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1192{
1193 unsigned flags = rhs->flags;
1194 lhs->selector = rhs->selector;
1195 lhs->base = rhs->base;
1196 lhs->limit = rhs->limit;
1197 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1198 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1199 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1200 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1201 lhs->s = (flags & DESC_S_MASK) != 0;
1202 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1203 lhs->g = (flags & DESC_G_MASK) != 0;
1204 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1205 lhs->unusable = !lhs->present;
7e680753 1206 lhs->padding = 0;
05330448
AL		 1207}
1208
1209static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1210{
1211 lhs->selector = rhs->selector;
1212 lhs->base = rhs->base;
1213 lhs->limit = rhs->limit;
4cae9c97
MC		 1214 if (rhs->unusable) {
1215 lhs->flags = 0;
1216 } else {
1217 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1218 (rhs->present * DESC_P_MASK) |
1219 (rhs->dpl << DESC_DPL_SHIFT) |
1220 (rhs->db << DESC_B_SHIFT) |
1221 (rhs->s * DESC_S_MASK) |
1222 (rhs->l << DESC_L_SHIFT) |
1223 (rhs->g * DESC_G_MASK) |
1224 (rhs->avl * DESC_AVL_MASK);
1225 }
05330448
AL		 1226}
1227
1228static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1229{
b9bec74b 1230 if (set) {
05330448 1231 *kvm_reg = *qemu_reg;
b9bec74b 1232 } else {
05330448 1233 *qemu_reg = *kvm_reg;
b9bec74b 1234 }
05330448
AL		 1235}
1236
1bc22652 1237static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1238{
1bc22652 1239 CPUX86State *env = &cpu->env;
05330448
AL		 1240 struct kvm_regs regs;
1241 int ret = 0;
1242
1243 if (!set) {
1bc22652 1244 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1245 if (ret < 0) {
05330448 1246 return ret;
b9bec74b 1247 }
05330448
AL		 1248 }
1249
1250 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1251 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1252 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1253 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1254 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1255 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1256 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1257 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1258#ifdef TARGET_X86_64
1259 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1260 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1261 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1262 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1263 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1264 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1265 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1266 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1267#endif
1268
1269 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1270 kvm_getput_reg(&regs.rip, &env->eip, set);
1271
b9bec74b 1272 if (set) {
1bc22652 1273 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1274 }
05330448
AL		 1275
1276 return ret;
1277}
1278
1bc22652 1279static int kvm_put_fpu(X86CPU *cpu)
05330448 1280{
1bc22652 1281 CPUX86State *env = &cpu->env;
05330448
AL		 1282 struct kvm_fpu fpu;
1283 int i;
1284
1285 memset(&fpu, 0, sizeof fpu);
1286 fpu.fsw = env->fpus & ~(7 << 11);
1287 fpu.fsw |= (env->fpstt & 7) << 11;
1288 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1289 fpu.last_opcode = env->fpop;
1290 fpu.last_ip = env->fpip;
1291 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1292 for (i = 0; i < 8; ++i) {
1293 fpu.ftwx |= (!env->fptags[i]) << i;
1294 }
05330448 1295 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1296 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1297 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1298 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1299 }
05330448
AL		 1300 fpu.mxcsr = env->mxcsr;
1301
1bc22652 1302 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1303}
1304
6b42494b
JK		 1305#define XSAVE_FCW_FSW 0
1306#define XSAVE_FTW_FOP 1
f1665b21
SY		 1307#define XSAVE_CWD_RIP 2
1308#define XSAVE_CWD_RDP 4
1309#define XSAVE_MXCSR 6
1310#define XSAVE_ST_SPACE 8
1311#define XSAVE_XMM_SPACE 40
1312#define XSAVE_XSTATE_BV 128
1313#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1314#define XSAVE_BNDREGS 240
1315#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1316#define XSAVE_OPMASK 272
1317#define XSAVE_ZMM_Hi256 288
1318#define XSAVE_Hi16_ZMM 416
f74eefe0 1319#define XSAVE_PKRU 672
f1665b21 1320
b503717d
EH		 1321#define XSAVE_BYTE_OFFSET(word_offset) \
1322 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1323
1324#define ASSERT_OFFSET(word_offset, field) \
1325 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1326 offsetof(X86XSaveArea, field))
1327
1328ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1329ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1330ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1331ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1332ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1333ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1334ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1335ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1336ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1337ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1338ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1339ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1340ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1341ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1342ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1343
1bc22652 1344static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1345{
1bc22652 1346 CPUX86State *env = &cpu->env;
86cd2ea0 1347 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1348 uint16_t cwd, swd, twd;
fabacc0f 1349 int i, r;
f1665b21 1350
28143b40 1351 if (!has_xsave) {
1bc22652 1352 return kvm_put_fpu(cpu);
b9bec74b 1353 }
f1665b21 1354
f1665b21 1355 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1356 twd = 0;
f1665b21
SY		 1357 swd = env->fpus & ~(7 << 11);
1358 swd |= (env->fpstt & 7) << 11;
1359 cwd = env->fpuc;
b9bec74b 1360 for (i = 0; i < 8; ++i) {
f1665b21 1361 twd |= (!env->fptags[i]) << i;
b9bec74b 1362 }
86cd2ea0
EH		 1363 xsave->legacy.fcw = cwd;
1364 xsave->legacy.fsw = swd;
1365 xsave->legacy.ftw = twd;
1366 xsave->legacy.fpop = env->fpop;
1367 xsave->legacy.fpip = env->fpip;
1368 xsave->legacy.fpdp = env->fpdp;
1369 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1370 sizeof env->fpregs);
86cd2ea0
EH		 1371 xsave->legacy.mxcsr = env->mxcsr;
1372 xsave->header.xstate_bv = env->xstate_bv;
1373 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1374 sizeof env->bnd_regs);
86cd2ea0
EH		 1375 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1376 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1377 sizeof env->opmask_regs);
bee81887 1378
86cd2ea0
EH		 1379 for (i = 0; i < CPU_NB_REGS; i++) {
1380 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1381 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1382 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1383 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1384 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1385 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1386 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1387 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1388 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1389 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1390 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1391 }
1392
9aecd6f8 1393#ifdef TARGET_X86_64
86cd2ea0 1394 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1395 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1396 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1397#endif
1bc22652 1398 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
0f53994f 1399 return r;
f1665b21
SY		 1400}
1401
1bc22652 1402static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1403{
1bc22652 1404 CPUX86State *env = &cpu->env;
bdfc8480 1405 struct kvm_xcrs xcrs = {};
f1665b21 1406
28143b40 1407 if (!has_xcrs) {
f1665b21 1408 return 0;
b9bec74b 1409 }
f1665b21
SY		 1410
1411 xcrs.nr_xcrs = 1;
1412 xcrs.flags = 0;
1413 xcrs.xcrs[0].xcr = 0;
1414 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1415 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1416}
1417
1bc22652 1418static int kvm_put_sregs(X86CPU *cpu)
05330448 1419{
1bc22652 1420 CPUX86State *env = &cpu->env;
05330448
AL		 1421 struct kvm_sregs sregs;
1422
0e607a80
JK		 1423 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1424 if (env->interrupt_injected >= 0) {
1425 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1426 (uint64_t)1 << (env->interrupt_injected % 64);
1427 }
05330448
AL		 1428
1429 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1430 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1431 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1432 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1433 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1434 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1435 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1436 } else {
b9bec74b
JK		 1437 set_seg(&sregs.cs, &env->segs[R_CS]);
1438 set_seg(&sregs.ds, &env->segs[R_DS]);
1439 set_seg(&sregs.es, &env->segs[R_ES]);
1440 set_seg(&sregs.fs, &env->segs[R_FS]);
1441 set_seg(&sregs.gs, &env->segs[R_GS]);
1442 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1443 }
1444
1445 set_seg(&sregs.tr, &env->tr);
1446 set_seg(&sregs.ldt, &env->ldt);
1447
1448 sregs.idt.limit = env->idt.limit;
1449 sregs.idt.base = env->idt.base;
7e680753 1450 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1451 sregs.gdt.limit = env->gdt.limit;
1452 sregs.gdt.base = env->gdt.base;
7e680753 1453 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1454
1455 sregs.cr0 = env->cr[0];
1456 sregs.cr2 = env->cr[2];
1457 sregs.cr3 = env->cr[3];
1458 sregs.cr4 = env->cr[4];
1459
02e51483
CF		 1460 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1461 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1462
1463 sregs.efer = env->efer;
1464
1bc22652 1465 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1466}
1467
d71b62a1
EH		 1468static void kvm_msr_buf_reset(X86CPU *cpu)
1469{
1470 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1471}
1472
9c600a84
EH		 1473static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1474{
1475 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1476 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1477 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1478
1479 assert((void *)(entry + 1) <= limit);
1480
1abc2cae
EH		 1481 entry->index = index;
1482 entry->reserved = 0;
1483 entry->data = value;
9c600a84
EH		 1484 msrs->nmsrs++;
1485}
1486
7477cd38
MT		 1487static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1488{
1489 CPUX86State *env = &cpu->env;
48e1a45c 1490 int ret;
7477cd38
MT		 1491
1492 if (!has_msr_tsc_deadline) {
1493 return 0;
1494 }
1495
e25ffda7
EH		 1496 kvm_msr_buf_reset(cpu);
1497 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
7477cd38 1498
e25ffda7 1499 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1500 if (ret < 0) {
1501 return ret;
1502 }
1503
1504 assert(ret == 1);
1505 return 0;
7477cd38
MT		 1506}
1507
6bdf863d
JK		 1508/*
1509 * Provide a separate write service for the feature control MSR in order to
1510 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1511 * before writing any other state because forcibly leaving nested mode
1512 * invalidates the VCPU state.
1513 */
1514static int kvm_put_msr_feature_control(X86CPU *cpu)
1515{
48e1a45c
PB		 1516 int ret;
1517
1518 if (!has_msr_feature_control) {
1519 return 0;
1520 }
6bdf863d 1521
e25ffda7
EH		 1522 kvm_msr_buf_reset(cpu);
1523 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
6bdf863d 1524 cpu->env.msr_ia32_feature_control);
c7fe4b12 1525
e25ffda7 1526 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1527 if (ret < 0) {
1528 return ret;
1529 }
1530
1531 assert(ret == 1);
1532 return 0;
6bdf863d
JK		 1533}
1534
1bc22652 1535static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1536{
1bc22652 1537 CPUX86State *env = &cpu->env;
9c600a84 1538 int i;
48e1a45c 1539 int ret;
05330448 1540
d71b62a1
EH		 1541 kvm_msr_buf_reset(cpu);
1542
9c600a84
EH		 1543 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1544 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1545 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1546 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1547 if (has_msr_star) {
9c600a84 1548 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1549 }
c3a3a7d3 1550 if (has_msr_hsave_pa) {
9c600a84 1551 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1552 }
c9b8f6b6 1553 if (has_msr_tsc_aux) {
9c600a84 1554 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1555 }
f28558d3 1556 if (has_msr_tsc_adjust) {
9c600a84 1557 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1558 }
21e87c46 1559 if (has_msr_misc_enable) {
9c600a84 1560 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1561 env->msr_ia32_misc_enable);
1562 }
fc12d72e 1563 if (has_msr_smbase) {
9c600a84 1564 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1565 }
439d19f2 1566 if (has_msr_bndcfgs) {
9c600a84 1567 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1568 }
18cd2c17 1569 if (has_msr_xss) {
9c600a84 1570 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1571 }
05330448 1572#ifdef TARGET_X86_64
25d2e361 1573 if (lm_capable_kernel) {
9c600a84
EH		 1574 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1575 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1576 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1577 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1578 }
05330448 1579#endif
ff5c186b 1580 /*
0d894367
PB		 1581 * The following MSRs have side effects on the guest or are too heavy
1582 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1583 */
1584 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1585 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1586 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1587 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc 1588 if (has_msr_async_pf_en) {
9c600a84 1589 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1590 }
bc9a839d 1591 if (has_msr_pv_eoi_en) {
9c600a84 1592 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1593 }
917367aa 1594 if (has_msr_kvm_steal_time) {
9c600a84 1595 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1596 }
0d894367
PB		 1597 if (has_msr_architectural_pmu) {
1598 /* Stop the counter. */
9c600a84
EH		 1599 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1600 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1601
1602 /* Set the counter values. */
1603 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1604 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1605 env->msr_fixed_counters[i]);
1606 }
1607 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1608 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1609 env->msr_gp_counters[i]);
9c600a84 1610 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1611 env->msr_gp_evtsel[i]);
1612 }
9c600a84 1613 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1614 env->msr_global_status);
9c600a84 1615 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1616 env->msr_global_ovf_ctrl);
1617
1618 /* Now start the PMU. */
9c600a84 1619 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1620 env->msr_fixed_ctr_ctrl);
9c600a84 1621 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1622 env->msr_global_ctrl);
1623 }
7bc3d711 1624 if (has_msr_hv_hypercall) {
9c600a84 1625 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1626 env->msr_hv_guest_os_id);
9c600a84 1627 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1628 env->msr_hv_hypercall);
eab70139 1629 }
7bc3d711 1630 if (has_msr_hv_vapic) {
9c600a84 1631 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1632 env->msr_hv_vapic);
eab70139 1633 }
48a5f3bc 1634 if (has_msr_hv_tsc) {
9c600a84 1635 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1636 }
f2a53c9e
AS		 1637 if (has_msr_hv_crash) {
1638 int j;
1639
1640 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1641 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1642 env->msr_hv_crash_params[j]);
1643
9c600a84 1644 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1645 HV_X64_MSR_CRASH_CTL_NOTIFY);
1646 }
46eb8f98 1647 if (has_msr_hv_runtime) {
9c600a84 1648 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1649 }
866eea9a
AS		 1650 if (cpu->hyperv_synic) {
1651 int j;
1652
9c600a84 1653 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1654 env->msr_hv_synic_control);
9c600a84 1655 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1656 env->msr_hv_synic_version);
9c600a84 1657 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1658 env->msr_hv_synic_evt_page);
9c600a84 1659 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1660 env->msr_hv_synic_msg_page);
1661
1662 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1663 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1664 env->msr_hv_synic_sint[j]);
1665 }
1666 }
ff99aa64
AS		 1667 if (has_msr_hv_stimer) {
1668 int j;
1669
1670 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1671 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1672 env->msr_hv_stimer_config[j]);
1673 }
1674
1675 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1676 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1677 env->msr_hv_stimer_count[j]);
1678 }
1679 }
d1ae67f6 1680 if (has_msr_mtrr) {
9c600a84
EH		 1681 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1682 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1683 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1684 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1685 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1686 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1687 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1688 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1689 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1690 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1691 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1692 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1693 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 1694 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1695 env->mtrr_var[i].base);
1696 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
1697 env->mtrr_var[i].mask);
d1ae67f6
AW		 1698 }
1699 }
6bdf863d
JK		 1700
1701 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1702 * kvm_put_msr_feature_control. */
ea643051 1703 }
57780495 1704 if (env->mcg_cap) {
d8da8574 1705 int i;
b9bec74b 1706
9c600a84
EH		 1707 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1708 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
c34d440a 1709 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1710 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1711 }
1712 }
1a03675d 1713
d71b62a1 1714 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1715 if (ret < 0) {
1716 return ret;
1717 }
05330448 1718
9c600a84 1719 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1720 return 0;
05330448
AL		 1721}
1722
1723
1bc22652 1724static int kvm_get_fpu(X86CPU *cpu)
05330448 1725{
1bc22652 1726 CPUX86State *env = &cpu->env;
05330448
AL		 1727 struct kvm_fpu fpu;
1728 int i, ret;
1729
1bc22652 1730 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1731 if (ret < 0) {
05330448 1732 return ret;
b9bec74b 1733 }
05330448
AL		 1734
1735 env->fpstt = (fpu.fsw >> 11) & 7;
1736 env->fpus = fpu.fsw;
1737 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1738 env->fpop = fpu.last_opcode;
1739 env->fpip = fpu.last_ip;
1740 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1741 for (i = 0; i < 8; ++i) {
1742 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1743 }
05330448 1744 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1745 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1746 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1747 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1748 }
05330448
AL		 1749 env->mxcsr = fpu.mxcsr;
1750
1751 return 0;
1752}
1753
1bc22652 1754static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1755{
1bc22652 1756 CPUX86State *env = &cpu->env;
86cd2ea0 1757 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1758 int ret, i;
42cc8fa6 1759 uint16_t cwd, swd, twd;
f1665b21 1760
28143b40 1761 if (!has_xsave) {
1bc22652 1762 return kvm_get_fpu(cpu);
b9bec74b 1763 }
f1665b21 1764
1bc22652 1765 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1766 if (ret < 0) {
f1665b21 1767 return ret;
0f53994f 1768 }
f1665b21 1769
86cd2ea0
EH		 1770 cwd = xsave->legacy.fcw;
1771 swd = xsave->legacy.fsw;
1772 twd = xsave->legacy.ftw;
1773 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1774 env->fpstt = (swd >> 11) & 7;
1775 env->fpus = swd;
1776 env->fpuc = cwd;
b9bec74b 1777 for (i = 0; i < 8; ++i) {
f1665b21 1778 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1779 }
86cd2ea0
EH		 1780 env->fpip = xsave->legacy.fpip;
1781 env->fpdp = xsave->legacy.fpdp;
1782 env->mxcsr = xsave->legacy.mxcsr;
1783 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1784 sizeof env->fpregs);
86cd2ea0
EH		 1785 env->xstate_bv = xsave->header.xstate_bv;
1786 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1787 sizeof env->bnd_regs);
86cd2ea0
EH		 1788 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1789 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1790 sizeof env->opmask_regs);
bee81887 1791
86cd2ea0
EH		 1792 for (i = 0; i < CPU_NB_REGS; i++) {
1793 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1794 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1795 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1796 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1797 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1798 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1799 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1800 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1801 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1802 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1803 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1804 }
1805
9aecd6f8 1806#ifdef TARGET_X86_64
86cd2ea0 1807 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1808 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1809 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1810#endif
f1665b21 1811 return 0;
f1665b21
SY		 1812}
1813
1bc22652 1814static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1815{
1bc22652 1816 CPUX86State *env = &cpu->env;
f1665b21
SY		 1817 int i, ret;
1818 struct kvm_xcrs xcrs;
1819
28143b40 1820 if (!has_xcrs) {
f1665b21 1821 return 0;
b9bec74b 1822 }
f1665b21 1823
1bc22652 1824 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1825 if (ret < 0) {
f1665b21 1826 return ret;
b9bec74b 1827 }
f1665b21 1828
b9bec74b 1829 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1830 /* Only support xcr0 now */
0fd53fec
PB		 1831 if (xcrs.xcrs[i].xcr == 0) {
1832 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1833 break;
1834 }
b9bec74b 1835 }
f1665b21 1836 return 0;
f1665b21
SY		 1837}
1838
1bc22652 1839static int kvm_get_sregs(X86CPU *cpu)
05330448 1840{
1bc22652 1841 CPUX86State *env = &cpu->env;
05330448
AL		 1842 struct kvm_sregs sregs;
1843 uint32_t hflags;
0e607a80 1844 int bit, i, ret;
05330448 1845
1bc22652 1846 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1847 if (ret < 0) {
05330448 1848 return ret;
b9bec74b 1849 }
05330448 1850
0e607a80
JK		 1851 /* There can only be one pending IRQ set in the bitmap at a time, so try
1852 to find it and save its number instead (-1 for none). */
1853 env->interrupt_injected = -1;
1854 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1855 if (sregs.interrupt_bitmap[i]) {
1856 bit = ctz64(sregs.interrupt_bitmap[i]);
1857 env->interrupt_injected = i * 64 + bit;
1858 break;
1859 }
1860 }
05330448
AL		 1861
1862 get_seg(&env->segs[R_CS], &sregs.cs);
1863 get_seg(&env->segs[R_DS], &sregs.ds);
1864 get_seg(&env->segs[R_ES], &sregs.es);
1865 get_seg(&env->segs[R_FS], &sregs.fs);
1866 get_seg(&env->segs[R_GS], &sregs.gs);
1867 get_seg(&env->segs[R_SS], &sregs.ss);
1868
1869 get_seg(&env->tr, &sregs.tr);
1870 get_seg(&env->ldt, &sregs.ldt);
1871
1872 env->idt.limit = sregs.idt.limit;
1873 env->idt.base = sregs.idt.base;
1874 env->gdt.limit = sregs.gdt.limit;
1875 env->gdt.base = sregs.gdt.base;
1876
1877 env->cr[0] = sregs.cr0;
1878 env->cr[2] = sregs.cr2;
1879 env->cr[3] = sregs.cr3;
1880 env->cr[4] = sregs.cr4;
1881
05330448 1882 env->efer = sregs.efer;
cce47516
JK		 1883
1884 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1885
b9bec74b
JK		 1886#define HFLAG_COPY_MASK \
1887 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1888 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1889 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1890 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1891
19dc85db
RH		 1892 hflags = env->hflags & HFLAG_COPY_MASK;
1893 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1894 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1895 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1896 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1897 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1898
1899 if (env->cr[4] & CR4_OSFXSR_MASK) {
1900 hflags |= HF_OSFXSR_MASK;
1901 }
05330448
AL		 1902
1903 if (env->efer & MSR_EFER_LMA) {
1904 hflags |= HF_LMA_MASK;
1905 }
1906
1907 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1908 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1909 } else {
1910 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1911 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1912 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1913 (DESC_B_SHIFT - HF_SS32_SHIFT);
1914 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1915 !(hflags & HF_CS32_MASK)) {
1916 hflags |= HF_ADDSEG_MASK;
1917 } else {
1918 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1919 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1920 }
05330448 1921 }
19dc85db 1922 env->hflags = hflags;
05330448
AL		 1923
1924 return 0;
1925}
1926
1bc22652 1927static int kvm_get_msrs(X86CPU *cpu)
05330448 1928{
1bc22652 1929 CPUX86State *env = &cpu->env;
d71b62a1 1930 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1931 int ret, i;
05330448 1932
d71b62a1
EH		 1933 kvm_msr_buf_reset(cpu);
1934
9c600a84
EH		 1935 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1936 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1937 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1938 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1939 if (has_msr_star) {
9c600a84 1940 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1941 }
c3a3a7d3 1942 if (has_msr_hsave_pa) {
9c600a84 1943 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1944 }
c9b8f6b6 1945 if (has_msr_tsc_aux) {
9c600a84 1946 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 1947 }
f28558d3 1948 if (has_msr_tsc_adjust) {
9c600a84 1949 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 1950 }
aa82ba54 1951 if (has_msr_tsc_deadline) {
9c600a84 1952 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 1953 }
21e87c46 1954 if (has_msr_misc_enable) {
9c600a84 1955 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 1956 }
fc12d72e 1957 if (has_msr_smbase) {
9c600a84 1958 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 1959 }
df67696e 1960 if (has_msr_feature_control) {
9c600a84 1961 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 1962 }
79e9ebeb 1963 if (has_msr_bndcfgs) {
9c600a84 1964 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 1965 }
18cd2c17 1966 if (has_msr_xss) {
9c600a84 1967 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 1968 }
1969
b8cc45d6
GC		 1970
1971 if (!env->tsc_valid) {
9c600a84 1972 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 1973 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1974 }
1975
05330448 1976#ifdef TARGET_X86_64
25d2e361 1977 if (lm_capable_kernel) {
9c600a84
EH		 1978 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
1979 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
1980 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
1981 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 1982 }
05330448 1983#endif
9c600a84
EH		 1984 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
1985 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
c5999bfc 1986 if (has_msr_async_pf_en) {
9c600a84 1987 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 1988 }
bc9a839d 1989 if (has_msr_pv_eoi_en) {
9c600a84 1990 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 1991 }
917367aa 1992 if (has_msr_kvm_steal_time) {
9c600a84 1993 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 1994 }
0d894367 1995 if (has_msr_architectural_pmu) {
9c600a84
EH		 1996 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1997 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1998 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
1999 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2000 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2001 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2002 }
2003 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2004 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2005 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2006 }
2007 }
1a03675d 2008
57780495 2009 if (env->mcg_cap) {
9c600a84
EH		 2010 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2011 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
b9bec74b 2012 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2013 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2014 }
57780495 2015 }
57780495 2016
1c90ef26 2017 if (has_msr_hv_hypercall) {
9c600a84
EH		 2018 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2019 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2020 }
5ef68987 2021 if (has_msr_hv_vapic) {
9c600a84 2022 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2023 }
48a5f3bc 2024 if (has_msr_hv_tsc) {
9c600a84 2025 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2026 }
f2a53c9e
AS		 2027 if (has_msr_hv_crash) {
2028 int j;
2029
2030 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2031 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2032 }
2033 }
46eb8f98 2034 if (has_msr_hv_runtime) {
9c600a84 2035 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2036 }
866eea9a
AS		 2037 if (cpu->hyperv_synic) {
2038 uint32_t msr;
2039
9c600a84
EH		 2040 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2041 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2042 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2043 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2044 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2045 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2046 }
2047 }
ff99aa64
AS		 2048 if (has_msr_hv_stimer) {
2049 uint32_t msr;
2050
2051 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2052 msr++) {
9c600a84 2053 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2054 }
2055 }
d1ae67f6 2056 if (has_msr_mtrr) {
9c600a84
EH		 2057 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2058 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2059 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2060 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2061 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2062 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2063 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2064 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2065 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2066 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2067 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2068 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2069 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2070 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2071 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2072 }
2073 }
5ef68987 2074
d71b62a1 2075 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2076 if (ret < 0) {
05330448 2077 return ret;
b9bec74b 2078 }
05330448 2079
9c600a84 2080 assert(ret == cpu->kvm_msr_buf->nmsrs);
05330448 2081 for (i = 0; i < ret; i++) {
0d894367
PB		 2082 uint32_t index = msrs[i].index;
2083 switch (index) {
05330448
AL		 2084 case MSR_IA32_SYSENTER_CS:
2085 env->sysenter_cs = msrs[i].data;
2086 break;
2087 case MSR_IA32_SYSENTER_ESP:
2088 env->sysenter_esp = msrs[i].data;
2089 break;
2090 case MSR_IA32_SYSENTER_EIP:
2091 env->sysenter_eip = msrs[i].data;
2092 break;
0c03266a
JK		 2093 case MSR_PAT:
2094 env->pat = msrs[i].data;
2095 break;
05330448
AL		 2096 case MSR_STAR:
2097 env->star = msrs[i].data;
2098 break;
2099#ifdef TARGET_X86_64
2100 case MSR_CSTAR:
2101 env->cstar = msrs[i].data;
2102 break;
2103 case MSR_KERNELGSBASE:
2104 env->kernelgsbase = msrs[i].data;
2105 break;
2106 case MSR_FMASK:
2107 env->fmask = msrs[i].data;
2108 break;
2109 case MSR_LSTAR:
2110 env->lstar = msrs[i].data;
2111 break;
2112#endif
2113 case MSR_IA32_TSC:
2114 env->tsc = msrs[i].data;
2115 break;
c9b8f6b6
AS		 2116 case MSR_TSC_AUX:
2117 env->tsc_aux = msrs[i].data;
2118 break;
f28558d3
WA		 2119 case MSR_TSC_ADJUST:
2120 env->tsc_adjust = msrs[i].data;
2121 break;
aa82ba54
LJ		 2122 case MSR_IA32_TSCDEADLINE:
2123 env->tsc_deadline = msrs[i].data;
2124 break;
aa851e36
MT		 2125 case MSR_VM_HSAVE_PA:
2126 env->vm_hsave = msrs[i].data;
2127 break;
1a03675d
GC		 2128 case MSR_KVM_SYSTEM_TIME:
2129 env->system_time_msr = msrs[i].data;
2130 break;
2131 case MSR_KVM_WALL_CLOCK:
2132 env->wall_clock_msr = msrs[i].data;
2133 break;
57780495
MT		 2134 case MSR_MCG_STATUS:
2135 env->mcg_status = msrs[i].data;
2136 break;
2137 case MSR_MCG_CTL:
2138 env->mcg_ctl = msrs[i].data;
2139 break;
21e87c46
AK		 2140 case MSR_IA32_MISC_ENABLE:
2141 env->msr_ia32_misc_enable = msrs[i].data;
2142 break;
fc12d72e
PB		 2143 case MSR_IA32_SMBASE:
2144 env->smbase = msrs[i].data;
2145 break;
0779caeb
ACL		 2146 case MSR_IA32_FEATURE_CONTROL:
2147 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2148 break;
79e9ebeb
LJ		 2149 case MSR_IA32_BNDCFGS:
2150 env->msr_bndcfgs = msrs[i].data;
2151 break;
18cd2c17
WL		 2152 case MSR_IA32_XSS:
2153 env->xss = msrs[i].data;
2154 break;
57780495 2155 default:
57780495
MT		 2156 if (msrs[i].index >= MSR_MC0_CTL &&
2157 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2158 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2159 }
d8da8574 2160 break;
f6584ee2
GN		 2161 case MSR_KVM_ASYNC_PF_EN:
2162 env->async_pf_en_msr = msrs[i].data;
2163 break;
bc9a839d
MT		 2164 case MSR_KVM_PV_EOI_EN:
2165 env->pv_eoi_en_msr = msrs[i].data;
2166 break;
917367aa
MT		 2167 case MSR_KVM_STEAL_TIME:
2168 env->steal_time_msr = msrs[i].data;
2169 break;
0d894367
PB		 2170 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2171 env->msr_fixed_ctr_ctrl = msrs[i].data;
2172 break;
2173 case MSR_CORE_PERF_GLOBAL_CTRL:
2174 env->msr_global_ctrl = msrs[i].data;
2175 break;
2176 case MSR_CORE_PERF_GLOBAL_STATUS:
2177 env->msr_global_status = msrs[i].data;
2178 break;
2179 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2180 env->msr_global_ovf_ctrl = msrs[i].data;
2181 break;
2182 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2183 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2184 break;
2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2186 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2187 break;
2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2189 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2190 break;
1c90ef26
VR		 2191 case HV_X64_MSR_HYPERCALL:
2192 env->msr_hv_hypercall = msrs[i].data;
2193 break;
2194 case HV_X64_MSR_GUEST_OS_ID:
2195 env->msr_hv_guest_os_id = msrs[i].data;
2196 break;
5ef68987
VR		 2197 case HV_X64_MSR_APIC_ASSIST_PAGE:
2198 env->msr_hv_vapic = msrs[i].data;
2199 break;
48a5f3bc
VR		 2200 case HV_X64_MSR_REFERENCE_TSC:
2201 env->msr_hv_tsc = msrs[i].data;
2202 break;
f2a53c9e
AS		 2203 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2204 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2205 break;
46eb8f98
AS		 2206 case HV_X64_MSR_VP_RUNTIME:
2207 env->msr_hv_runtime = msrs[i].data;
2208 break;
866eea9a
AS		 2209 case HV_X64_MSR_SCONTROL:
2210 env->msr_hv_synic_control = msrs[i].data;
2211 break;
2212 case HV_X64_MSR_SVERSION:
2213 env->msr_hv_synic_version = msrs[i].data;
2214 break;
2215 case HV_X64_MSR_SIEFP:
2216 env->msr_hv_synic_evt_page = msrs[i].data;
2217 break;
2218 case HV_X64_MSR_SIMP:
2219 env->msr_hv_synic_msg_page = msrs[i].data;
2220 break;
2221 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2222 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2223 break;
2224 case HV_X64_MSR_STIMER0_CONFIG:
2225 case HV_X64_MSR_STIMER1_CONFIG:
2226 case HV_X64_MSR_STIMER2_CONFIG:
2227 case HV_X64_MSR_STIMER3_CONFIG:
2228 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2229 msrs[i].data;
2230 break;
2231 case HV_X64_MSR_STIMER0_COUNT:
2232 case HV_X64_MSR_STIMER1_COUNT:
2233 case HV_X64_MSR_STIMER2_COUNT:
2234 case HV_X64_MSR_STIMER3_COUNT:
2235 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2236 msrs[i].data;
866eea9a 2237 break;
d1ae67f6
AW		 2238 case MSR_MTRRdefType:
2239 env->mtrr_deftype = msrs[i].data;
2240 break;
2241 case MSR_MTRRfix64K_00000:
2242 env->mtrr_fixed[0] = msrs[i].data;
2243 break;
2244 case MSR_MTRRfix16K_80000:
2245 env->mtrr_fixed[1] = msrs[i].data;
2246 break;
2247 case MSR_MTRRfix16K_A0000:
2248 env->mtrr_fixed[2] = msrs[i].data;
2249 break;
2250 case MSR_MTRRfix4K_C0000:
2251 env->mtrr_fixed[3] = msrs[i].data;
2252 break;
2253 case MSR_MTRRfix4K_C8000:
2254 env->mtrr_fixed[4] = msrs[i].data;
2255 break;
2256 case MSR_MTRRfix4K_D0000:
2257 env->mtrr_fixed[5] = msrs[i].data;
2258 break;
2259 case MSR_MTRRfix4K_D8000:
2260 env->mtrr_fixed[6] = msrs[i].data;
2261 break;
2262 case MSR_MTRRfix4K_E0000:
2263 env->mtrr_fixed[7] = msrs[i].data;
2264 break;
2265 case MSR_MTRRfix4K_E8000:
2266 env->mtrr_fixed[8] = msrs[i].data;
2267 break;
2268 case MSR_MTRRfix4K_F0000:
2269 env->mtrr_fixed[9] = msrs[i].data;
2270 break;
2271 case MSR_MTRRfix4K_F8000:
2272 env->mtrr_fixed[10] = msrs[i].data;
2273 break;
2274 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2275 if (index & 1) {
2276 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2277 } else {
2278 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2279 }
2280 break;
05330448
AL		 2281 }
2282 }
2283
2284 return 0;
2285}
2286
1bc22652 2287static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2288{
1bc22652 2289 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2290
1bc22652 2291 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2292}
2293
23d02d9b 2294static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2295{
259186a7 2296 CPUState *cs = CPU(cpu);
23d02d9b 2297 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2298 struct kvm_mp_state mp_state;
2299 int ret;
2300
259186a7 2301 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2302 if (ret < 0) {
2303 return ret;
2304 }
2305 env->mp_state = mp_state.mp_state;
c14750e8 2306 if (kvm_irqchip_in_kernel()) {
259186a7 2307 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2308 }
9bdbe550
HB		 2309 return 0;
2310}
2311
1bc22652 2312static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2313{
02e51483 2314 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2315 struct kvm_lapic_state kapic;
2316 int ret;
2317
3d4b2649 2318 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2319 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2320 if (ret < 0) {
2321 return ret;
2322 }
2323
2324 kvm_get_apic_state(apic, &kapic);
2325 }
2326 return 0;
2327}
2328
1bc22652 2329static int kvm_put_apic(X86CPU *cpu)
680c1c6f 2330{
02e51483 2331 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2332 struct kvm_lapic_state kapic;
2333
3d4b2649 2334 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 2335 kvm_put_apic_state(apic, &kapic);
2336
1bc22652 2337 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 2338 }
2339 return 0;
2340}
2341
1bc22652 2342static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2343{
fc12d72e 2344 CPUState *cs = CPU(cpu);
1bc22652 2345 CPUX86State *env = &cpu->env;
076796f8 2346 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2347
2348 if (!kvm_has_vcpu_events()) {
2349 return 0;
2350 }
2351
31827373
JK		 2352 events.exception.injected = (env->exception_injected >= 0);
2353 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2354 events.exception.has_error_code = env->has_error_code;
2355 events.exception.error_code = env->error_code;
7e680753 2356 events.exception.pad = 0;
a0fb002c
JK		 2357
2358 events.interrupt.injected = (env->interrupt_injected >= 0);
2359 events.interrupt.nr = env->interrupt_injected;
2360 events.interrupt.soft = env->soft_interrupt;
2361
2362 events.nmi.injected = env->nmi_injected;
2363 events.nmi.pending = env->nmi_pending;
2364 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2365 events.nmi.pad = 0;
a0fb002c
JK		 2366
2367 events.sipi_vector = env->sipi_vector;
2368
fc12d72e
PB		 2369 if (has_msr_smbase) {
2370 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2371 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2372 if (kvm_irqchip_in_kernel()) {
2373 /* As soon as these are moved to the kernel, remove them
2374 * from cs->interrupt_request.
2375 */
2376 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2377 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2378 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2379 } else {
2380 /* Keep these in cs->interrupt_request. */
2381 events.smi.pending = 0;
2382 events.smi.latched_init = 0;
2383 }
2384 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2385 }
2386
ea643051
JK		 2387 events.flags = 0;
2388 if (level >= KVM_PUT_RESET_STATE) {
2389 events.flags |=
2390 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2391 }
aee028b9 2392
1bc22652 2393 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2394}
2395
1bc22652 2396static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2397{
1bc22652 2398 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2399 struct kvm_vcpu_events events;
2400 int ret;
2401
2402 if (!kvm_has_vcpu_events()) {
2403 return 0;
2404 }
2405
fc12d72e 2406 memset(&events, 0, sizeof(events));
1bc22652 2407 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2408 if (ret < 0) {
2409 return ret;
2410 }
31827373 2411 env->exception_injected =
a0fb002c
JK		 2412 events.exception.injected ? events.exception.nr : -1;
2413 env->has_error_code = events.exception.has_error_code;
2414 env->error_code = events.exception.error_code;
2415
2416 env->interrupt_injected =
2417 events.interrupt.injected ? events.interrupt.nr : -1;
2418 env->soft_interrupt = events.interrupt.soft;
2419
2420 env->nmi_injected = events.nmi.injected;
2421 env->nmi_pending = events.nmi.pending;
2422 if (events.nmi.masked) {
2423 env->hflags2 |= HF2_NMI_MASK;
2424 } else {
2425 env->hflags2 &= ~HF2_NMI_MASK;
2426 }
2427
fc12d72e
PB		 2428 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2429 if (events.smi.smm) {
2430 env->hflags |= HF_SMM_MASK;
2431 } else {
2432 env->hflags &= ~HF_SMM_MASK;
2433 }
2434 if (events.smi.pending) {
2435 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2436 } else {
2437 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2438 }
2439 if (events.smi.smm_inside_nmi) {
2440 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2441 } else {
2442 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2443 }
2444 if (events.smi.latched_init) {
2445 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2446 } else {
2447 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2448 }
2449 }
2450
a0fb002c 2451 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2452
2453 return 0;
2454}
2455
1bc22652 2456static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2457{
ed2803da 2458 CPUState *cs = CPU(cpu);
1bc22652 2459 CPUX86State *env = &cpu->env;
b0b1d690 2460 int ret = 0;
b0b1d690
JK		 2461 unsigned long reinject_trap = 0;
2462
2463 if (!kvm_has_vcpu_events()) {
2464 if (env->exception_injected == 1) {
2465 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2466 } else if (env->exception_injected == 3) {
2467 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2468 }
2469 env->exception_injected = -1;
2470 }
2471
2472 /*
2473 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2474 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2475 * by updating the debug state once again if single-stepping is on.
2476 * Another reason to call kvm_update_guest_debug here is a pending debug
2477 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2478 * reinject them via SET_GUEST_DEBUG.
2479 */
2480 if (reinject_trap ||
ed2803da 2481 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2482 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2483 }
b0b1d690
JK		 2484 return ret;
2485}
2486
1bc22652 2487static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2488{
1bc22652 2489 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2490 struct kvm_debugregs dbgregs;
2491 int i;
2492
2493 if (!kvm_has_debugregs()) {
2494 return 0;
2495 }
2496
2497 for (i = 0; i < 4; i++) {
2498 dbgregs.db[i] = env->dr[i];
2499 }
2500 dbgregs.dr6 = env->dr[6];
2501 dbgregs.dr7 = env->dr[7];
2502 dbgregs.flags = 0;
2503
1bc22652 2504 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2505}
2506
1bc22652 2507static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2508{
1bc22652 2509 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2510 struct kvm_debugregs dbgregs;
2511 int i, ret;
2512
2513 if (!kvm_has_debugregs()) {
2514 return 0;
2515 }
2516
1bc22652 2517 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2518 if (ret < 0) {
b9bec74b 2519 return ret;
ff44f1a3
JK		 2520 }
2521 for (i = 0; i < 4; i++) {
2522 env->dr[i] = dbgregs.db[i];
2523 }
2524 env->dr[4] = env->dr[6] = dbgregs.dr6;
2525 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2526
2527 return 0;
2528}
2529
20d695a9 2530int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2531{
20d695a9 2532 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2533 int ret;
2534
2fa45344 2535 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2536
48e1a45c 2537 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2538 ret = kvm_put_msr_feature_control(x86_cpu);
2539 if (ret < 0) {
2540 return ret;
2541 }
2542 }
2543
36f96c4b
HZ		 2544 if (level == KVM_PUT_FULL_STATE) {
2545 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2546 * because TSC frequency mismatch shouldn't abort migration,
2547 * unless the user explicitly asked for a more strict TSC
2548 * setting (e.g. using an explicit "tsc-freq" option).
2549 */
2550 kvm_arch_set_tsc_khz(cpu);
2551 }
2552
1bc22652 2553 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2554 if (ret < 0) {
05330448 2555 return ret;
b9bec74b 2556 }
1bc22652 2557 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2558 if (ret < 0) {
f1665b21 2559 return ret;
b9bec74b 2560 }
1bc22652 2561 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2562 if (ret < 0) {
05330448 2563 return ret;
b9bec74b 2564 }
1bc22652 2565 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2566 if (ret < 0) {
05330448 2567 return ret;
b9bec74b 2568 }
ab443475 2569 /* must be before kvm_put_msrs */
1bc22652 2570 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2571 if (ret < 0) {
2572 return ret;
2573 }
1bc22652 2574 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2575 if (ret < 0) {
05330448 2576 return ret;
b9bec74b 2577 }
ea643051 2578 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2579 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2580 if (ret < 0) {
ea643051 2581 return ret;
b9bec74b 2582 }
1bc22652 2583 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2584 if (ret < 0) {
2585 return ret;
2586 }
ea643051 2587 }
7477cd38
MT		 2588
2589 ret = kvm_put_tscdeadline_msr(x86_cpu);
2590 if (ret < 0) {
2591 return ret;
2592 }
2593
1bc22652 2594 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2595 if (ret < 0) {
a0fb002c 2596 return ret;
b9bec74b 2597 }
1bc22652 2598 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2599 if (ret < 0) {
b0b1d690 2600 return ret;
b9bec74b 2601 }
b0b1d690 2602 /* must be last */
1bc22652 2603 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2604 if (ret < 0) {
ff44f1a3 2605 return ret;
b9bec74b 2606 }
05330448
AL		 2607 return 0;
2608}
2609
20d695a9 2610int kvm_arch_get_registers(CPUState *cs)
05330448 2611{
20d695a9 2612 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2613 int ret;
2614
20d695a9 2615 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2616
1bc22652 2617 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2618 if (ret < 0) {
f4f1110e 2619 goto out;
b9bec74b 2620 }
1bc22652 2621 ret = kvm_get_xsave(cpu);
b9bec74b 2622 if (ret < 0) {
f4f1110e 2623 goto out;
b9bec74b 2624 }
1bc22652 2625 ret = kvm_get_xcrs(cpu);
b9bec74b 2626 if (ret < 0) {
f4f1110e 2627 goto out;
b9bec74b 2628 }
1bc22652 2629 ret = kvm_get_sregs(cpu);
b9bec74b 2630 if (ret < 0) {
f4f1110e 2631 goto out;
b9bec74b 2632 }
1bc22652 2633 ret = kvm_get_msrs(cpu);
b9bec74b 2634 if (ret < 0) {
f4f1110e 2635 goto out;
b9bec74b 2636 }
23d02d9b 2637 ret = kvm_get_mp_state(cpu);
b9bec74b 2638 if (ret < 0) {
f4f1110e 2639 goto out;
b9bec74b 2640 }
1bc22652 2641 ret = kvm_get_apic(cpu);
680c1c6f 2642 if (ret < 0) {
f4f1110e 2643 goto out;
680c1c6f 2644 }
1bc22652 2645 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2646 if (ret < 0) {
f4f1110e 2647 goto out;
b9bec74b 2648 }
1bc22652 2649 ret = kvm_get_debugregs(cpu);
b9bec74b 2650 if (ret < 0) {
f4f1110e 2651 goto out;
b9bec74b 2652 }
f4f1110e
RH		 2653 ret = 0;
2654 out:
2655 cpu_sync_bndcs_hflags(&cpu->env);
2656 return ret;
05330448
AL		 2657}
2658
20d695a9 2659void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2660{
20d695a9
AF		 2661 X86CPU *x86_cpu = X86_CPU(cpu);
2662 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2663 int ret;
2664
276ce815 2665 /* Inject NMI */
fc12d72e
PB		 2666 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2667 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2668 qemu_mutex_lock_iothread();
2669 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2670 qemu_mutex_unlock_iothread();
2671 DPRINTF("injected NMI\n");
2672 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2673 if (ret < 0) {
2674 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2675 strerror(-ret));
2676 }
2677 }
2678 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2679 qemu_mutex_lock_iothread();
2680 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2681 qemu_mutex_unlock_iothread();
2682 DPRINTF("injected SMI\n");
2683 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2684 if (ret < 0) {
2685 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2686 strerror(-ret));
2687 }
ce377af3 2688 }
276ce815
LJ		 2689 }
2690
15eafc2e 2691 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2692 qemu_mutex_lock_iothread();
2693 }
2694
e0723c45
PB		 2695 /* Force the VCPU out of its inner loop to process any INIT requests
2696 * or (for userspace APIC, but it is cheap to combine the checks here)
2697 * pending TPR access reports.
2698 */
2699 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2700 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2701 !(env->hflags & HF_SMM_MASK)) {
2702 cpu->exit_request = 1;
2703 }
2704 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2705 cpu->exit_request = 1;
2706 }
e0723c45 2707 }
05330448 2708
15eafc2e 2709 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2710 /* Try to inject an interrupt if the guest can accept it */
2711 if (run->ready_for_interrupt_injection &&
259186a7 2712 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2713 (env->eflags & IF_MASK)) {
2714 int irq;
2715
259186a7 2716 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2717 irq = cpu_get_pic_interrupt(env);
2718 if (irq >= 0) {
2719 struct kvm_interrupt intr;
2720
2721 intr.irq = irq;
db1669bc 2722 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2723 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2724 if (ret < 0) {
2725 fprintf(stderr,
2726 "KVM: injection failed, interrupt lost (%s)\n",
2727 strerror(-ret));
2728 }
db1669bc
JK		 2729 }
2730 }
05330448 2731
db1669bc
JK		 2732 /* If we have an interrupt but the guest is not ready to receive an
2733 * interrupt, request an interrupt window exit. This will
2734 * cause a return to userspace as soon as the guest is ready to
2735 * receive interrupts. */
259186a7 2736 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2737 run->request_interrupt_window = 1;
2738 } else {
2739 run->request_interrupt_window = 0;
2740 }
2741
2742 DPRINTF("setting tpr\n");
02e51483 2743 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2744
2745 qemu_mutex_unlock_iothread();
db1669bc 2746 }
05330448
AL		 2747}
2748
4c663752 2749MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2750{
20d695a9
AF		 2751 X86CPU *x86_cpu = X86_CPU(cpu);
2752 CPUX86State *env = &x86_cpu->env;
2753
fc12d72e
PB		 2754 if (run->flags & KVM_RUN_X86_SMM) {
2755 env->hflags |= HF_SMM_MASK;
2756 } else {
2757 env->hflags &= HF_SMM_MASK;
2758 }
b9bec74b 2759 if (run->if_flag) {
05330448 2760 env->eflags |= IF_MASK;
b9bec74b 2761 } else {
05330448 2762 env->eflags &= ~IF_MASK;
b9bec74b 2763 }
4b8523ee
JK		 2764
2765 /* We need to protect the apic state against concurrent accesses from
2766 * different threads in case the userspace irqchip is used. */
2767 if (!kvm_irqchip_in_kernel()) {
2768 qemu_mutex_lock_iothread();
2769 }
02e51483
CF		 2770 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2771 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2772 if (!kvm_irqchip_in_kernel()) {
2773 qemu_mutex_unlock_iothread();
2774 }
f794aa4a 2775 return cpu_get_mem_attrs(env);
05330448
AL		 2776}
2777
20d695a9 2778int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2779{
20d695a9
AF		 2780 X86CPU *cpu = X86_CPU(cs);
2781 CPUX86State *env = &cpu->env;
232fc23b 2782
259186a7 2783 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2784 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2785 assert(env->mcg_cap);
2786
259186a7 2787 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2788
dd1750d7 2789 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2790
2791 if (env->exception_injected == EXCP08_DBLE) {
2792 /* this means triple fault */
2793 qemu_system_reset_request();
fcd7d003 2794 cs->exit_request = 1;
ab443475
JK		 2795 return 0;
2796 }
2797 env->exception_injected = EXCP12_MCHK;
2798 env->has_error_code = 0;
2799
259186a7 2800 cs->halted = 0;
ab443475
JK		 2801 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2802 env->mp_state = KVM_MP_STATE_RUNNABLE;
2803 }
2804 }
2805
fc12d72e
PB		 2806 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2807 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2808 kvm_cpu_synchronize_state(cs);
2809 do_cpu_init(cpu);
2810 }
2811
db1669bc
JK		 2812 if (kvm_irqchip_in_kernel()) {
2813 return 0;
2814 }
2815
259186a7
AF		 2816 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2817 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2818 apic_poll_irq(cpu->apic_state);
5d62c43a 2819 }
259186a7 2820 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2821 (env->eflags & IF_MASK)) ||
259186a7
AF		 2822 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2823 cs->halted = 0;
6792a57b 2824 }
259186a7 2825 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2826 kvm_cpu_synchronize_state(cs);
232fc23b 2827 do_cpu_sipi(cpu);
0af691d7 2828 }
259186a7
AF		 2829 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2830 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2831 kvm_cpu_synchronize_state(cs);
02e51483 2832 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2833 env->tpr_access_type);
2834 }
0af691d7 2835
259186a7 2836 return cs->halted;
0af691d7
MT		 2837}
2838
839b5630 2839static int kvm_handle_halt(X86CPU *cpu)
05330448 2840{
259186a7 2841 CPUState *cs = CPU(cpu);
839b5630
AF		 2842 CPUX86State *env = &cpu->env;
2843
259186a7 2844 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2845 (env->eflags & IF_MASK)) &&
259186a7
AF		 2846 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2847 cs->halted = 1;
bb4ea393 2848 return EXCP_HLT;
05330448
AL		 2849 }
2850
bb4ea393 2851 return 0;
05330448
AL		 2852}
2853
f7575c96 2854static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2855{
f7575c96
AF		 2856 CPUState *cs = CPU(cpu);
2857 struct kvm_run *run = cs->kvm_run;
d362e757 2858
02e51483 2859 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2860 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2861 : TPR_ACCESS_READ);
2862 return 1;
2863}
2864
f17ec444 2865int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2866{
38972938 2867 static const uint8_t int3 = 0xcc;
64bf3f4e 2868
f17ec444
AF		 2869 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2870 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2871 return -EINVAL;
b9bec74b 2872 }
e22a25c9
AL		 2873 return 0;
2874}
2875
f17ec444 2876int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2877{
2878 uint8_t int3;
2879
f17ec444
AF		 2880 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2881 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2882 return -EINVAL;
b9bec74b 2883 }
e22a25c9
AL		 2884 return 0;
2885}
2886
2887static struct {
2888 target_ulong addr;
2889 int len;
2890 int type;
2891} hw_breakpoint[4];
2892
2893static int nb_hw_breakpoint;
2894
2895static int find_hw_breakpoint(target_ulong addr, int len, int type)
2896{
2897 int n;
2898
b9bec74b 2899 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2900 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2901 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2902 return n;
b9bec74b
JK		 2903 }
2904 }
e22a25c9
AL		 2905 return -1;
2906}
2907
2908int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2909 target_ulong len, int type)
2910{
2911 switch (type) {
2912 case GDB_BREAKPOINT_HW:
2913 len = 1;
2914 break;
2915 case GDB_WATCHPOINT_WRITE:
2916 case GDB_WATCHPOINT_ACCESS:
2917 switch (len) {
2918 case 1:
2919 break;
2920 case 2:
2921 case 4:
2922 case 8:
b9bec74b 2923 if (addr & (len - 1)) {
e22a25c9 2924 return -EINVAL;
b9bec74b 2925 }
e22a25c9
AL		 2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930 break;
2931 default:
2932 return -ENOSYS;
2933 }
2934
b9bec74b 2935 if (nb_hw_breakpoint == 4) {
e22a25c9 2936 return -ENOBUFS;
b9bec74b
JK		 2937 }
2938 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2939 return -EEXIST;
b9bec74b 2940 }
e22a25c9
AL		 2941 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2942 hw_breakpoint[nb_hw_breakpoint].len = len;
2943 hw_breakpoint[nb_hw_breakpoint].type = type;
2944 nb_hw_breakpoint++;
2945
2946 return 0;
2947}
2948
2949int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2950 target_ulong len, int type)
2951{
2952 int n;
2953
2954 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2955 if (n < 0) {
e22a25c9 2956 return -ENOENT;
b9bec74b 2957 }
e22a25c9
AL		 2958 nb_hw_breakpoint--;
2959 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2960
2961 return 0;
2962}
2963
2964void kvm_arch_remove_all_hw_breakpoints(void)
2965{
2966 nb_hw_breakpoint = 0;
2967}
2968
2969static CPUWatchpoint hw_watchpoint;
2970
a60f24b5 2971static int kvm_handle_debug(X86CPU *cpu,
48405526 2972 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2973{
ed2803da 2974 CPUState *cs = CPU(cpu);
a60f24b5 2975 CPUX86State *env = &cpu->env;
f2574737 2976 int ret = 0;
e22a25c9
AL		 2977 int n;
2978
2979 if (arch_info->exception == 1) {
2980 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2981 if (cs->singlestep_enabled) {
f2574737 2982 ret = EXCP_DEBUG;
b9bec74b 2983 }
e22a25c9 2984 } else {
b9bec74b
JK		 2985 for (n = 0; n < 4; n++) {
2986 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 2987 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2988 case 0x0:
f2574737 2989 ret = EXCP_DEBUG;
e22a25c9
AL		 2990 break;
2991 case 0x1:
f2574737 2992 ret = EXCP_DEBUG;
ff4700b0 2993 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2994 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2995 hw_watchpoint.flags = BP_MEM_WRITE;
2996 break;
2997 case 0x3:
f2574737 2998 ret = EXCP_DEBUG;
ff4700b0 2999 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3000 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3001 hw_watchpoint.flags = BP_MEM_ACCESS;
3002 break;
3003 }
b9bec74b
JK		 3004 }
3005 }
e22a25c9 3006 }
ff4700b0 3007 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3008 ret = EXCP_DEBUG;
b9bec74b 3009 }
f2574737 3010 if (ret == 0) {
ff4700b0 3011 cpu_synchronize_state(cs);
48405526 3012 assert(env->exception_injected == -1);
b0b1d690 3013
f2574737 3014 /* pass to guest */
48405526
BS		 3015 env->exception_injected = arch_info->exception;
3016 env->has_error_code = 0;
b0b1d690 3017 }
e22a25c9 3018
f2574737 3019 return ret;
e22a25c9
AL		 3020}
3021
20d695a9 3022void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3023{
3024 const uint8_t type_code[] = {
3025 [GDB_BREAKPOINT_HW] = 0x0,
3026 [GDB_WATCHPOINT_WRITE] = 0x1,
3027 [GDB_WATCHPOINT_ACCESS] = 0x3
3028 };
3029 const uint8_t len_code[] = {
3030 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3031 };
3032 int n;
3033
a60f24b5 3034 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3035 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3036 }
e22a25c9
AL		 3037 if (nb_hw_breakpoint > 0) {
3038 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3039 dbg->arch.debugreg[7] = 0x0600;
3040 for (n = 0; n < nb_hw_breakpoint; n++) {
3041 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3042 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3043 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3044 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3045 }
3046 }
3047}
4513d923 3048
2a4dac83
JK		 3049static bool host_supports_vmx(void)
3050{
3051 uint32_t ecx, unused;
3052
3053 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3054 return ecx & CPUID_EXT_VMX;
3055}
3056
3057#define VMX_INVALID_GUEST_STATE 0x80000021
3058
20d695a9 3059int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3060{
20d695a9 3061 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3062 uint64_t code;
3063 int ret;
3064
3065 switch (run->exit_reason) {
3066 case KVM_EXIT_HLT:
3067 DPRINTF("handle_hlt\n");
4b8523ee 3068 qemu_mutex_lock_iothread();
839b5630 3069 ret = kvm_handle_halt(cpu);
4b8523ee 3070 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3071 break;
3072 case KVM_EXIT_SET_TPR:
3073 ret = 0;
3074 break;
d362e757 3075 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3076 qemu_mutex_lock_iothread();
f7575c96 3077 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3078 qemu_mutex_unlock_iothread();
d362e757 3079 break;
2a4dac83
JK		 3080 case KVM_EXIT_FAIL_ENTRY:
3081 code = run->fail_entry.hardware_entry_failure_reason;
3082 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3083 code);
3084 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3085 fprintf(stderr,
12619721 3086 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3087 "unrestricted mode\n"
3088 "support, the failure can be most likely due to the guest "
3089 "entering an invalid\n"
3090 "state for Intel VT. For example, the guest maybe running "
3091 "in big real mode\n"
3092 "which is not supported on less recent Intel processors."
3093 "\n\n");
3094 }
3095 ret = -1;
3096 break;
3097 case KVM_EXIT_EXCEPTION:
3098 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3099 run->ex.exception, run->ex.error_code);
3100 ret = -1;
3101 break;
f2574737
JK		 3102 case KVM_EXIT_DEBUG:
3103 DPRINTF("kvm_exit_debug\n");
4b8523ee 3104 qemu_mutex_lock_iothread();
a60f24b5 3105 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3106 qemu_mutex_unlock_iothread();
f2574737 3107 break;
50efe82c
AS		 3108 case KVM_EXIT_HYPERV:
3109 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3110 break;
15eafc2e
PB		 3111 case KVM_EXIT_IOAPIC_EOI:
3112 ioapic_eoi_broadcast(run->eoi.vector);
3113 ret = 0;
3114 break;
2a4dac83
JK		 3115 default:
3116 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3117 ret = -1;
3118 break;
3119 }
3120
3121 return ret;
3122}
3123
20d695a9 3124bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3125{
20d695a9
AF		 3126 X86CPU *cpu = X86_CPU(cs);
3127 CPUX86State *env = &cpu->env;
3128
dd1750d7 3129 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3130 return !(env->cr[0] & CR0_PE_MASK) ||
3131 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3132}
84b058d7
JK		 3133
3134void kvm_arch_init_irq_routing(KVMState *s)
3135{
3136 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3137 /* If kernel can't do irq routing, interrupt source
3138 * override 0->2 cannot be set up as required by HPET.
3139 * So we have to disable it.
3140 */
3141 no_hpet = 1;
3142 }
cc7e0ddf 3143 /* We know at this point that we're using the in-kernel
614e41bc 3144 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3145 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3146 */
614e41bc 3147 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3148 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3149
3150 if (kvm_irqchip_is_split()) {
3151 int i;
3152
3153 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3154 MSI routes for signaling interrupts to the local apics. */
3155 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3156 struct MSIMessage msg = { 0x0, 0x0 };
3157 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3158 error_report("Could not enable split IRQ mode.");
3159 exit(1);
3160 }
3161 }
3162 }
3163}
3164
3165int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3166{
3167 int ret;
3168 if (machine_kernel_irqchip_split(ms)) {
3169 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3170 if (ret) {
3171 error_report("Could not enable split irqchip mode: %s\n",
3172 strerror(-ret));
3173 exit(1);
3174 } else {
3175 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3176 kvm_split_irqchip = true;
3177 return 1;
3178 }
3179 } else {
3180 return 0;
3181 }
84b058d7 3182}
b139bd30
JK		 3183
3184/* Classic KVM device assignment interface. Will remain x86 only. */
3185int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3186 uint32_t flags, uint32_t *dev_id)
3187{
3188 struct kvm_assigned_pci_dev dev_data = {
3189 .segnr = dev_addr->domain,
3190 .busnr = dev_addr->bus,
3191 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3192 .flags = flags,
3193 };
3194 int ret;
3195
3196 dev_data.assigned_dev_id =
3197 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3198
3199 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3200 if (ret < 0) {
3201 return ret;
3202 }
3203
3204 *dev_id = dev_data.assigned_dev_id;
3205
3206 return 0;
3207}
3208
3209int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3210{
3211 struct kvm_assigned_pci_dev dev_data = {
3212 .assigned_dev_id = dev_id,
3213 };
3214
3215 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3216}
3217
3218static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3219 uint32_t irq_type, uint32_t guest_irq)
3220{
3221 struct kvm_assigned_irq assigned_irq = {
3222 .assigned_dev_id = dev_id,
3223 .guest_irq = guest_irq,
3224 .flags = irq_type,
3225 };
3226
3227 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3228 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3229 } else {
3230 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3231 }
3232}
3233
3234int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3235 uint32_t guest_irq)
3236{
3237 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3238 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3239
3240 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3241}
3242
3243int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3244{
3245 struct kvm_assigned_pci_dev dev_data = {
3246 .assigned_dev_id = dev_id,
3247 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3248 };
3249
3250 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3251}
3252
3253static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3254 uint32_t type)
3255{
3256 struct kvm_assigned_irq assigned_irq = {
3257 .assigned_dev_id = dev_id,
3258 .flags = type,
3259 };
3260
3261 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3262}
3263
3264int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3265{
3266 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3267 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3268}
3269
3270int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3271{
3272 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3273 KVM_DEV_IRQ_GUEST_MSI, virq);
3274}
3275
3276int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3277{
3278 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3279 KVM_DEV_IRQ_HOST_MSI);
3280}
3281
3282bool kvm_device_msix_supported(KVMState *s)
3283{
3284 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3285 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3286 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3287}
3288
3289int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3290 uint32_t nr_vectors)
3291{
3292 struct kvm_assigned_msix_nr msix_nr = {
3293 .assigned_dev_id = dev_id,
3294 .entry_nr = nr_vectors,
3295 };
3296
3297 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3298}
3299
3300int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3301 int virq)
3302{
3303 struct kvm_assigned_msix_entry msix_entry = {
3304 .assigned_dev_id = dev_id,
3305 .gsi = virq,
3306 .entry = vector,
3307 };
3308
3309 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3310}
3311
3312int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3313{
3314 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3315 KVM_DEV_IRQ_GUEST_MSIX, 0);
3316}
3317
3318int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3319{
3320 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3321 KVM_DEV_IRQ_HOST_MSIX);
3322}
9e03a040
FB		 3323
3324int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3325 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 3326{
3327 return 0;
3328}
1850b6b7
EA		 3329
3330int kvm_arch_msi_data_to_gsi(uint32_t data)
3331{
3332 abort();
3333}
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