[mirror_ubuntu-zesty-kernel.git] / virt / kvm / arm / vgic / vgic-v3.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <kvm/arm_vgic.h>
#include <asm/kvm_mmu.h>
#include <asm/kvm_asm.h>

#include "vgic.h"

void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;

	if (cpuif->vgic_misr & ICH_MISR_EOI) {
		unsigned long eisr_bmap = cpuif->vgic_eisr;
		int lr;

		for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
			u32 intid;
			u64 val = cpuif->vgic_lr[lr];

			if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
				intid = val & ICH_LR_VIRTUAL_ID_MASK;
			else
				intid = val & GICH_LR_VIRTUALID;

			WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);

			/* Only SPIs require notification */
			if (vgic_valid_spi(vcpu->kvm, intid))
				kvm_notify_acked_irq(vcpu->kvm, 0,
						     intid - VGIC_NR_PRIVATE_IRQS);
		}

		/*
		 * In the next iterations of the vcpu loop, if we sync
		 * the vgic state after flushing it, but before
		 * entering the guest (this happens for pending
		 * signals and vmid rollovers), then make sure we
		 * don't pick up any old maintenance interrupts here.
		 */
		cpuif->vgic_eisr = 0;
	}

	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
}

static bool group0_trap;
static bool group1_trap;
static bool common_trap;

void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;

	cpuif->vgic_hcr |= ICH_HCR_UIE;
}

void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	int lr;

	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
		u64 val = cpuif->vgic_lr[lr];
		u32 intid;
		struct vgic_irq *irq;

		if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
			intid = val & ICH_LR_VIRTUAL_ID_MASK;
		else
			intid = val & GICH_LR_VIRTUALID;
		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
		if (!irq)	/* An LPI could have been unmapped. */
			continue;

		spin_lock(&irq->irq_lock);

		/* Always preserve the active bit */
		irq->active = !!(val & ICH_LR_ACTIVE_BIT);

		/* Edge is the only case where we preserve the pending bit */
		if (irq->config == VGIC_CONFIG_EDGE &&
		    (val & ICH_LR_PENDING_BIT)) {
			irq->pending = true;

			if (vgic_irq_is_sgi(intid) &&
			    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
				u32 cpuid = val & GICH_LR_PHYSID_CPUID;

				cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
				irq->source |= (1 << cpuid);
			}
		}

		/*
		 * Clear soft pending state when level irqs have been acked.
		 * Always regenerate the pending state.
		 */
		if (irq->config == VGIC_CONFIG_LEVEL) {
			if (!(val & ICH_LR_PENDING_BIT))
				irq->soft_pending = false;

			irq->pending = irq->line_level || irq->soft_pending;
		}

		spin_unlock(&irq->irq_lock);
		vgic_put_irq(vcpu->kvm, irq);
	}
}

/* Requires the irq to be locked already */
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
{
	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	u64 val = irq->intid;

	if (irq->pending) {
		val |= ICH_LR_PENDING_BIT;

		if (irq->config == VGIC_CONFIG_EDGE)
			irq->pending = false;

		if (vgic_irq_is_sgi(irq->intid) &&
		    model == KVM_DEV_TYPE_ARM_VGIC_V2) {
			u32 src = ffs(irq->source);

			BUG_ON(!src);
			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
			irq->source &= ~(1 << (src - 1));
			if (irq->source)
				irq->pending = true;
		}
	}

	if (irq->active)
		val |= ICH_LR_ACTIVE_BIT;

	if (irq->hw) {
		val |= ICH_LR_HW;
		val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
	} else {
		if (irq->config == VGIC_CONFIG_LEVEL)
			val |= ICH_LR_EOI;
	}

	/*
	 * We currently only support Group1 interrupts, which is a
	 * known defect. This needs to be addressed at some point.
	 */
	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
		val |= ICH_LR_GROUP;

	val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
}

void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
{
	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
}

void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr;

	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;

	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
}

void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;

	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
}

#define INITIAL_PENDBASER_VALUE						  \
	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)		| \
	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)	| \
	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))

void vgic_v3_enable(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;

	/*
	 * By forcing VMCR to zero, the GIC will restore the binary
	 * points to their reset values. Anything else resets to zero
	 * anyway.
	 */
	vgic_v3->vgic_vmcr = 0;
	vgic_v3->vgic_elrsr = ~0;

	/*
	 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
	 * way, so we force SRE to 1 to demonstrate this to the guest.
	 * This goes with the spec allowing the value to be RAO/WI.
	 */
	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
		vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
		vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
	} else {
		vgic_v3->vgic_sre = 0;
	}

	/* Get the show on the road... */
	vgic_v3->vgic_hcr = ICH_HCR_EN;
	if (group0_trap)
		vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
	if (group1_trap)
		vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
	if (common_trap)
		vgic_v3->vgic_hcr |= ICH_HCR_TC;
}

/* check for overlapping regions and for regions crossing the end of memory */
static bool vgic_v3_check_base(struct kvm *kvm)
{
	struct vgic_dist *d = &kvm->arch.vgic;
	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;

	redist_size *= atomic_read(&kvm->online_vcpus);

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
		return false;
	if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
		return false;

	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
		return true;
	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
		return true;

	return false;
}

int vgic_v3_map_resources(struct kvm *kvm)
{
	int ret = 0;
	struct vgic_dist *dist = &kvm->arch.vgic;

	if (vgic_ready(kvm))
		goto out;

	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
	    IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
		kvm_err("Need to set vgic distributor addresses first\n");
		ret = -ENXIO;
		goto out;
	}

	if (!vgic_v3_check_base(kvm)) {
		kvm_err("VGIC redist and dist frames overlap\n");
		ret = -EINVAL;
		goto out;
	}

	/*
	 * For a VGICv3 we require the userland to explicitly initialize
	 * the VGIC before we need to use it.
	 */
	if (!vgic_initialized(kvm)) {
		ret = -EBUSY;
		goto out;
	}

	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	if (ret) {
		kvm_err("Unable to register VGICv3 dist MMIO regions\n");
		goto out;
	}

	ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
	if (ret) {
		kvm_err("Unable to register VGICv3 redist MMIO regions\n");
		goto out;
	}

	if (vgic_has_its(kvm)) {
		ret = vgic_register_its_iodevs(kvm);
		if (ret) {
			kvm_err("Unable to register VGIC ITS MMIO regions\n");
			goto out;
		}
	}

	dist->ready = true;

out:
	return ret;
}

DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);

static int __init early_group0_trap_cfg(char *buf)
{
	return strtobool(buf, &group0_trap);
}
early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);

static int __init early_group1_trap_cfg(char *buf)
{
	return strtobool(buf, &group1_trap);
}
early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);

static int __init early_common_trap_cfg(char *buf)
{
	return strtobool(buf, &common_trap);
}
early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);

/**
 * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 * @node:	pointer to the DT node
 *
 * Returns 0 if a GICv3 has been found, returns an error code otherwise
 */
int vgic_v3_probe(const struct gic_kvm_info *info)
{
	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
	int ret;

	/*
	 * The ListRegs field is 5 bits, but there is a architectural
	 * maximum of 16 list registers. Just ignore bit 4...
	 */
	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	kvm_vgic_global_state.can_emulate_gicv2 = false;

	if (!info->vcpu.start) {
		kvm_info("GICv3: no GICV resource entry\n");
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
		pr_warn("GICV physical address 0x%llx not page aligned\n",
			(unsigned long long)info->vcpu.start);
		kvm_vgic_global_state.vcpu_base = 0;
	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
		pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
			(unsigned long long)resource_size(&info->vcpu),
			PAGE_SIZE);
		kvm_vgic_global_state.vcpu_base = 0;
	} else {
		kvm_vgic_global_state.vcpu_base = info->vcpu.start;
		kvm_vgic_global_state.can_emulate_gicv2 = true;
		ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
		if (ret) {
			kvm_err("Cannot register GICv2 KVM device.\n");
			return ret;
		}
		kvm_info("vgic-v2@%llx\n", info->vcpu.start);
	}
	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	if (ret) {
		kvm_err("Cannot register GICv3 KVM device.\n");
		kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
		return ret;
	}

	if (kvm_vgic_global_state.vcpu_base == 0)
		kvm_info("disabling GICv2 emulation\n");

#ifdef CONFIG_ARM64
	if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
		group0_trap = true;
		group1_trap = true;
	}
#endif

	if (group0_trap || group1_trap || common_trap) {
		kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n");
		static_branch_enable(&vgic_v3_cpuif_trap);
	}

	kvm_vgic_global_state.vctrl_base = NULL;
	kvm_vgic_global_state.type = VGIC_V3;
	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;

	return 0;
}
Commit	Line	Data
59529f69 MZ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License version 2 as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	13	*/
	14
	15	#include <linux/irqchip/arm-gic-v3.h>
	16	#include <linux/kvm.h>
	17	#include <linux/kvm_host.h>
90977732 EA	18	#include <kvm/arm_vgic.h>
	19	#include <asm/kvm_mmu.h>
	20	#include <asm/kvm_asm.h>
59529f69 MZ	21
	22	#include "vgic.h"
	23
	24	void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
	25	{
	26	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	27	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	28
	29	if (cpuif->vgic_misr & ICH_MISR_EOI) {
	30	unsigned long eisr_bmap = cpuif->vgic_eisr;
	31	int lr;
	32
	33	for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
	34	u32 intid;
	35	u64 val = cpuif->vgic_lr[lr];
	36
	37	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	38	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	39	else
	40	intid = val & GICH_LR_VIRTUALID;
	41
	42	WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
	43
8ca18eec MZ	44	/* Only SPIs require notification */
	45	if (vgic_valid_spi(vcpu->kvm, intid))
	46	kvm_notify_acked_irq(vcpu->kvm, 0,
	47	intid - VGIC_NR_PRIVATE_IRQS);
59529f69 MZ	48	}
	49
	50	/*
	51	* In the next iterations of the vcpu loop, if we sync
	52	* the vgic state after flushing it, but before
	53	* entering the guest (this happens for pending
	54	* signals and vmid rollovers), then make sure we
	55	* don't pick up any old maintenance interrupts here.
	56	*/
	57	cpuif->vgic_eisr = 0;
	58	}
	59
	60	cpuif->vgic_hcr &= ~ICH_HCR_UIE;
	61	}
	62
ae48fae1	63	static bool group0_trap;
14adc6b1	64	static bool group1_trap;
d55d2201	65	static bool common_trap;
14adc6b1	66
59529f69 MZ	67	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
	68	{
	69	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	70
	71	cpuif->vgic_hcr \|= ICH_HCR_UIE;
	72	}
	73
	74	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
	75	{
	76	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
	77	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	78	int lr;
	79
	80	for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
	81	u64 val = cpuif->vgic_lr[lr];
	82	u32 intid;
	83	struct vgic_irq *irq;
	84
	85	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	86	intid = val & ICH_LR_VIRTUAL_ID_MASK;
	87	else
	88	intid = val & GICH_LR_VIRTUALID;
	89	irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
3802411d AP	90	if (!irq) /* An LPI could have been unmapped. */
3802411d AP	91	continue;
59529f69 MZ	92
	93	spin_lock(&irq->irq_lock);
	94
	95	/* Always preserve the active bit */
	96	irq->active = !!(val & ICH_LR_ACTIVE_BIT);
	97
	98	/* Edge is the only case where we preserve the pending bit */
	99	if (irq->config == VGIC_CONFIG_EDGE &&
	100	(val & ICH_LR_PENDING_BIT)) {
	101	irq->pending = true;
	102
	103	if (vgic_irq_is_sgi(intid) &&
	104	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	105	u32 cpuid = val & GICH_LR_PHYSID_CPUID;
	106
	107	cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
	108	irq->source \|= (1 << cpuid);
	109	}
	110	}
	111
637d122b MZ	112	/*
	113	* Clear soft pending state when level irqs have been acked.
	114	* Always regenerate the pending state.
	115	*/
	116	if (irq->config == VGIC_CONFIG_LEVEL) {
	117	if (!(val & ICH_LR_PENDING_BIT))
	118	irq->soft_pending = false;
	119
	120	irq->pending = irq->line_level \|\| irq->soft_pending;
59529f69 MZ	121	}
	122
	123	spin_unlock(&irq->irq_lock);
5dd4b924	124	vgic_put_irq(vcpu->kvm, irq);
59529f69 MZ	125	}
	126	}
	127
	128	/* Requires the irq to be locked already */
	129	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr)
	130	{
	131	u32 model = vcpu->kvm->arch.vgic.vgic_model;
	132	u64 val = irq->intid;
	133
	134	if (irq->pending) {
	135	val \|= ICH_LR_PENDING_BIT;
	136
	137	if (irq->config == VGIC_CONFIG_EDGE)
	138	irq->pending = false;
	139
	140	if (vgic_irq_is_sgi(irq->intid) &&
	141	model == KVM_DEV_TYPE_ARM_VGIC_V2) {
	142	u32 src = ffs(irq->source);
	143
	144	BUG_ON(!src);
	145	val \|= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
	146	irq->source &= ~(1 << (src - 1));
	147	if (irq->source)
	148	irq->pending = true;
	149	}
	150	}
	151
	152	if (irq->active)
	153	val \|= ICH_LR_ACTIVE_BIT;
	154
	155	if (irq->hw) {
	156	val \|= ICH_LR_HW;
	157	val \|= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
	158	} else {
	159	if (irq->config == VGIC_CONFIG_LEVEL)
	160	val \|= ICH_LR_EOI;
	161	}
	162
	163	/*
	164	* We currently only support Group1 interrupts, which is a
	165	* known defect. This needs to be addressed at some point.
	166	*/
	167	if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
	168	val \|= ICH_LR_GROUP;
	169
	170	val \|= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
	171
	172	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
	173	}
	174
	175	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
	176	{
	177	vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
	178	}
e4823a7a AP	179
	180	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	181	{
	182	u32 vmcr;
	183
	184	vmcr = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
	185	vmcr \|= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
	186	vmcr \|= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
	187	vmcr \|= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
	188
	189	vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
	190	}
	191
	192	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcrp)
	193	{
	194	u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
	195
	196	vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
	197	vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
	198	vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
	199	vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
	200	}
90977732	201
0aa1de57 AP	202	#define INITIAL_PENDBASER_VALUE \
	203	(GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) \| \
	204	GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) \| \
	205	GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
	206
ad275b8b EA	207	void vgic_v3_enable(struct kvm_vcpu *vcpu)
ad275b8b EA	208	{
f7b6985c EA	209	struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
	210
	211	/*
	212	* By forcing VMCR to zero, the GIC will restore the binary
	213	* points to their reset values. Anything else resets to zero
	214	* anyway.
	215	*/
	216	vgic_v3->vgic_vmcr = 0;
	217	vgic_v3->vgic_elrsr = ~0;
	218
	219	/*
	220	* If we are emulating a GICv3, we do it in an non-GICv2-compatible
	221	* way, so we force SRE to 1 to demonstrate this to the guest.
	222	* This goes with the spec allowing the value to be RAO/WI.
	223	*/
0aa1de57	224	if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
f7b6985c	225	vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
0aa1de57 AP	226	vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
0aa1de57 AP	227	} else {
f7b6985c	228	vgic_v3->vgic_sre = 0;
0aa1de57	229	}
f7b6985c EA	230
	231	/* Get the show on the road... */
	232	vgic_v3->vgic_hcr = ICH_HCR_EN;
ae48fae1 MZ	233	if (group0_trap)
ae48fae1 MZ	234	vgic_v3->vgic_hcr \|= ICH_HCR_TALL0;
14adc6b1 MZ	235	if (group1_trap)
14adc6b1 MZ	236	vgic_v3->vgic_hcr \|= ICH_HCR_TALL1;
d55d2201 MZ	237	if (common_trap)
d55d2201 MZ	238	vgic_v3->vgic_hcr \|= ICH_HCR_TC;
ad275b8b EA	239	}
ad275b8b EA	240
b0442ee2 EA	241	/* check for overlapping regions and for regions crossing the end of memory */
	242	static bool vgic_v3_check_base(struct kvm *kvm)
	243	{
	244	struct vgic_dist *d = &kvm->arch.vgic;
	245	gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
	246
	247	redist_size *= atomic_read(&kvm->online_vcpus);
	248
	249	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
	250	return false;
	251	if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
	252	return false;
	253
	254	if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
	255	return true;
	256	if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
	257	return true;
	258
	259	return false;
	260	}
	261
	262	int vgic_v3_map_resources(struct kvm *kvm)
	263	{
	264	int ret = 0;
	265	struct vgic_dist *dist = &kvm->arch.vgic;
	266
	267	if (vgic_ready(kvm))
	268	goto out;
	269
	270	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) \|\|
	271	IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
	272	kvm_err("Need to set vgic distributor addresses first\n");
	273	ret = -ENXIO;
	274	goto out;
	275	}
	276
	277	if (!vgic_v3_check_base(kvm)) {
	278	kvm_err("VGIC redist and dist frames overlap\n");
	279	ret = -EINVAL;
	280	goto out;
	281	}
	282
	283	/*
	284	* For a VGICv3 we require the userland to explicitly initialize
	285	* the VGIC before we need to use it.
	286	*/
	287	if (!vgic_initialized(kvm)) {
	288	ret = -EBUSY;
	289	goto out;
	290	}
	291
	292	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
	293	if (ret) {
	294	kvm_err("Unable to register VGICv3 dist MMIO regions\n");
	295	goto out;
	296	}
	297
	298	ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
	299	if (ret) {
	300	kvm_err("Unable to register VGICv3 redist MMIO regions\n");
	301	goto out;
	302	}
	303
c7735769 AP	304	if (vgic_has_its(kvm)) {
	305	ret = vgic_register_its_iodevs(kvm);
	306	if (ret) {
	307	kvm_err("Unable to register VGIC ITS MMIO regions\n");
	308	goto out;
	309	}
	310	}
	311
b0442ee2 EA	312	dist->ready = true;
	313
	314	out:
b0442ee2 EA	315	return ret;
	316	}
	317
0c94a05f MZ	318	DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
0c94a05f MZ	319
97afa480 MZ	320	static int __init early_group0_trap_cfg(char *buf)
	321	{
	322	return strtobool(buf, &group0_trap);
	323	}
	324	early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
	325
243f60e0 MZ	326	static int __init early_group1_trap_cfg(char *buf)
	327	{
	328	return strtobool(buf, &group1_trap);
	329	}
	330	early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
	331
d55d2201 MZ	332	static int __init early_common_trap_cfg(char *buf)
	333	{
	334	return strtobool(buf, &common_trap);
	335	}
	336	early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
	337
90977732 EA	338	/**
	339	* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
	340	* @node: pointer to the DT node
	341	*
	342	* Returns 0 if a GICv3 has been found, returns an error code otherwise
	343	*/
	344	int vgic_v3_probe(const struct gic_kvm_info *info)
	345	{
	346	u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
42c8870f	347	int ret;
90977732 EA	348
	349	/*
	350	* The ListRegs field is 5 bits, but there is a architectural
	351	* maximum of 16 list registers. Just ignore bit 4...
	352	*/
	353	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
	354	kvm_vgic_global_state.can_emulate_gicv2 = false;
	355
	356	if (!info->vcpu.start) {
	357	kvm_info("GICv3: no GICV resource entry\n");
	358	kvm_vgic_global_state.vcpu_base = 0;
	359	} else if (!PAGE_ALIGNED(info->vcpu.start)) {
	360	pr_warn("GICV physical address 0x%llx not page aligned\n",
	361	(unsigned long long)info->vcpu.start);
	362	kvm_vgic_global_state.vcpu_base = 0;
	363	} else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
	364	pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
	365	(unsigned long long)resource_size(&info->vcpu),
	366	PAGE_SIZE);
	367	kvm_vgic_global_state.vcpu_base = 0;
	368	} else {
	369	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
	370	kvm_vgic_global_state.can_emulate_gicv2 = true;
42c8870f AP	371	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
	372	if (ret) {
	373	kvm_err("Cannot register GICv2 KVM device.\n");
	374	return ret;
	375	}
90977732 EA	376	kvm_info("vgic-v2@%llx\n", info->vcpu.start);
90977732 EA	377	}
42c8870f AP	378	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
	379	if (ret) {
	380	kvm_err("Cannot register GICv3 KVM device.\n");
	381	kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
	382	return ret;
	383	}
	384
90977732 EA	385	if (kvm_vgic_global_state.vcpu_base == 0)
90977732 EA	386	kvm_info("disabling GICv2 emulation\n");
90977732	387
8b760f81 DD	388	#ifdef CONFIG_ARM64
	389	if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
	390	group0_trap = true;
	391	group1_trap = true;
	392	}
	393	#endif
	394
d55d2201	395	if (group0_trap \|\| group1_trap \|\| common_trap) {
243f60e0 MZ	396	kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n");
	397	static_branch_enable(&vgic_v3_cpuif_trap);
	398	}
	399
90977732 EA	400	kvm_vgic_global_state.vctrl_base = NULL;
	401	kvm_vgic_global_state.type = VGIC_V3;
	402	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
	403
	404	return 0;
	405	}