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soft mmu support
[qemu.git] / vl.c
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0824d6fc 1/*
1df912cf 2 * QEMU PC System Emulator
0824d6fc 3 *
1df912cf 4 * Copyright (c) 2003 Fabrice Bellard
0824d6fc 5 *
1df912cf
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
0824d6fc
FB		 23 */
24#include <stdlib.h>
25#include <stdio.h>
1df912cf 26#include <stdarg.h>
0824d6fc
FB		 27#include <string.h>
28#include <getopt.h>
29#include <inttypes.h>
30#include <unistd.h>
31#include <sys/mman.h>
32#include <fcntl.h>
33#include <signal.h>
34#include <time.h>
35#include <sys/time.h>
36#include <malloc.h>
37#include <termios.h>
38#include <sys/poll.h>
39#include <errno.h>
f1510b2c
FB		 40#include <sys/wait.h>
41
42#include <sys/ioctl.h>
43#include <sys/socket.h>
44#include <linux/if.h>
45#include <linux/if_tun.h>
0824d6fc
FB		 46
47#include "cpu-i386.h"
48#include "disas.h"
fc01f7e7
FB		 49#include "thunk.h"
50
51#include "vl.h"
0824d6fc
FB		 52
53#define DEBUG_LOGFILE "/tmp/vl.log"
f1510b2c 54#define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
330d0414
FB		 55#define BIOS_FILENAME "bios.bin"
56#define VGABIOS_FILENAME "vgabios.bin"
f1510b2c 57
0824d6fc 58//#define DEBUG_UNUSED_IOPORT
330d0414 59
c9159e53 60//#define DEBUG_IRQ_LATENCY
0824d6fc 61
330d0414
FB		 62/* output Bochs bios info messages */
63//#define DEBUG_BIOS
64
65/* debug IDE devices */
66//#define DEBUG_IDE
67
68/* debug PIC */
69//#define DEBUG_PIC
70
71/* debug NE2000 card */
72//#define DEBUG_NE2000
73
74/* debug PC keyboard */
75//#define DEBUG_KBD
76
7916e224
FB		 77#define PHYS_RAM_BASE 0xac000000
78#define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
79
0824d6fc
FB		 80#define KERNEL_LOAD_ADDR 0x00100000
81#define INITRD_LOAD_ADDR 0x00400000
82#define KERNEL_PARAMS_ADDR 0x00090000
83
33e3963e
FB		 84#define MAX_DISKS 2
85
0824d6fc
FB		 86/* from plex86 (BSD license) */
87struct __attribute__ ((packed)) linux_params {
88 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
89 // I just padded out the VESA parts, rather than define them.
90
91 /* 0x000 */ uint8_t orig_x;
92 /* 0x001 */ uint8_t orig_y;
93 /* 0x002 */ uint16_t ext_mem_k;
94 /* 0x004 */ uint16_t orig_video_page;
95 /* 0x006 */ uint8_t orig_video_mode;
96 /* 0x007 */ uint8_t orig_video_cols;
97 /* 0x008 */ uint16_t unused1;
98 /* 0x00a */ uint16_t orig_video_ega_bx;
99 /* 0x00c */ uint16_t unused2;
100 /* 0x00e */ uint8_t orig_video_lines;
101 /* 0x00f */ uint8_t orig_video_isVGA;
102 /* 0x010 */ uint16_t orig_video_points;
103 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
104 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
105 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
106 // is calculated as 0x90000 + cl_offset, bu
107 // only if cl_magic == 0xA33F.
108 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
109
110 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
111 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
112
113 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
114 // Might be truncated?
115 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
116 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
117
118 // System description table truncated to 16 bytes
119 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
120 /* 0x0a0 */ uint16_t sys_description_len;
121 /* 0x0a2 */ uint8_t sys_description_table[14];
122 // [0] machine id
123 // [1] machine submodel id
124 // [2] BIOS revision
125 // [3] bit1: MCA bus
126
127 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
128 /* 0x1e0 */ uint32_t alt_mem_k;
129 /* 0x1e4 */ uint8_t pad4[4];
130 /* 0x1e8 */ uint8_t e820map_entries;
131 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
132 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
133 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
134 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
135 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
136 // (b)zImage-file (in 16 byte units, rounded up)
137 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
138 /* 0x1f8 */ uint16_t ramdisk_flags;
139 /* 0x1fa */ uint16_t vga_mode; // (old one)
140 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
141 /* 0x1fe */ uint8_t pad6[1];
142 /* 0x1ff */ uint8_t aux_device_info;
143 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
144 // aka "reserved" field.
145 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
146 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
147 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
148 // boot loaders, look there.
149 /* 0x210 */ uint8_t loader_type;
150 // 0 for old one.
151 // else 0xTV:
152 // T=0: LILO
153 // T=1: Loadlin
154 // T=2: bootsect-loader
155 // T=3: SYSLINUX
156 // T=4: ETHERBOOT
157 // V=version
158 /* 0x211 */ uint8_t loadflags;
159 // bit0 = 1: kernel is loaded high (bzImage)
160 // bit7 = 1: Heap and pointer (see below) set by boot
161 // loader.
162 /* 0x212 */ uint16_t setup_S_temp1;
163 /* 0x214 */ uint32_t kernel_start;
164 /* 0x218 */ uint32_t initrd_start;
165 /* 0x21c */ uint32_t initrd_size;
166 /* 0x220 */ uint8_t setup_S_temp2[4];
167 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
168 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
169
170 /* 0x2d0 : Int 15, ax=e820 memory map. */
171 // (linux/include/asm-i386/e820.h, 'struct e820entry')
172#define E820MAX 32
173#define E820_RAM 1
174#define E820_RESERVED 2
175#define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
176#define E820_NVS 4
177 struct {
178 uint64_t addr;
179 uint64_t size;
180 uint32_t type;
181 } e820map[E820MAX];
182
183 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
184
185 // BIOS Enhanced Disk Drive Services.
186 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
187 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
188 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
189
190 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
191 /* 0x800 */ uint8_t commandline[0x800];
192
193 /* 0x1000 */
194 uint64_t gdt_table[256];
195 uint64_t idt_table[48];
196};
197
198#define KERNEL_CS 0x10
199#define KERNEL_DS 0x18
200
201typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data);
202typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
203
fc01f7e7 204#define MAX_IOPORTS 4096
0824d6fc 205
330d0414 206static const char *interp_prefix = CONFIG_QEMU_PREFIX;
0824d6fc
FB		 207char phys_ram_file[1024];
208CPUX86State *global_env;
1df912cf 209CPUX86State *cpu_single_env;
0824d6fc
FB		 210FILE *logfile = NULL;
211int loglevel;
fc01f7e7
FB		 212IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
213IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
33e3963e 214BlockDriverState *bs_table[MAX_DISKS];
0824d6fc
FB		 215
216/***********************************************************/
217/* x86 io ports */
218
219uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
220{
221#ifdef DEBUG_UNUSED_IOPORT
222 fprintf(stderr, "inb: port=0x%04x\n", address);
223#endif
fc01f7e7 224 return 0xff;
0824d6fc
FB		 225}
226
227void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
228{
229#ifdef DEBUG_UNUSED_IOPORT
230 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
231#endif
232}
233
234/* default is to make two byte accesses */
235uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
236{
237 uint32_t data;
330d0414
FB		 238 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
239 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
0824d6fc
FB		 240 return data;
241}
242
243void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
244{
330d0414
FB		 245 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
246 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
0824d6fc
FB		 247}
248
fc01f7e7 249uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
0824d6fc 250{
fc01f7e7
FB		 251#ifdef DEBUG_UNUSED_IOPORT
252 fprintf(stderr, "inl: port=0x%04x\n", address);
253#endif
254 return 0xffffffff;
0824d6fc
FB		 255}
256
fc01f7e7 257void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
0824d6fc 258{
fc01f7e7
FB		 259#ifdef DEBUG_UNUSED_IOPORT
260 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
261#endif
0824d6fc
FB		 262}
263
fc01f7e7 264void init_ioports(void)
0824d6fc
FB		 265{
266 int i;
267
fc01f7e7
FB		 268 for(i = 0; i < MAX_IOPORTS; i++) {
269 ioport_read_table[0][i] = default_ioport_readb;
270 ioport_write_table[0][i] = default_ioport_writeb;
271 ioport_read_table[1][i] = default_ioport_readw;
272 ioport_write_table[1][i] = default_ioport_writew;
273 ioport_read_table[2][i] = default_ioport_readl;
274 ioport_write_table[2][i] = default_ioport_writel;
275 }
0824d6fc
FB		 276}
277
fc01f7e7
FB		 278/* size is the word size in byte */
279int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
f1510b2c 280{
fc01f7e7 281 int i, bsize;
f1510b2c 282
fc01f7e7
FB		 283 if (size == 1)
284 bsize = 0;
285 else if (size == 2)
286 bsize = 1;
287 else if (size == 4)
288 bsize = 2;
289 else
290 return -1;
291 for(i = start; i < start + length; i += size)
292 ioport_read_table[bsize][i] = func;
f1510b2c
FB		 293 return 0;
294}
295
fc01f7e7
FB		 296/* size is the word size in byte */
297int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
f1510b2c 298{
fc01f7e7 299 int i, bsize;
f1510b2c 300
fc01f7e7
FB		 301 if (size == 1)
302 bsize = 0;
303 else if (size == 2)
304 bsize = 1;
305 else if (size == 4)
306 bsize = 2;
307 else
308 return -1;
309 for(i = start; i < start + length; i += size)
310 ioport_write_table[bsize][i] = func;
f1510b2c
FB		 311 return 0;
312}
313
0824d6fc
FB		 314void pstrcpy(char *buf, int buf_size, const char *str)
315{
316 int c;
317 char *q = buf;
318
319 if (buf_size <= 0)
320 return;
321
322 for(;;) {
323 c = *str++;
324 if (c == 0 || q >= buf + buf_size - 1)
325 break;
326 *q++ = c;
327 }
328 *q = '\0';
329}
330
331/* strcat and truncate. */
332char *pstrcat(char *buf, int buf_size, const char *s)
333{
334 int len;
335 len = strlen(buf);
336 if (len < buf_size)
337 pstrcpy(buf + len, buf_size - len, s);
338 return buf;
339}
340
341int load_kernel(const char *filename, uint8_t *addr)
342{
343 int fd, size, setup_sects;
344 uint8_t bootsect[512];
345
346 fd = open(filename, O_RDONLY);
347 if (fd < 0)
348 return -1;
349 if (read(fd, bootsect, 512) != 512)
350 goto fail;
351 setup_sects = bootsect[0x1F1];
352 if (!setup_sects)
353 setup_sects = 4;
354 /* skip 16 bit setup code */
355 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
356 size = read(fd, addr, 16 * 1024 * 1024);
357 if (size < 0)
358 goto fail;
359 close(fd);
360 return size;
361 fail:
362 close(fd);
363 return -1;
364}
365
366/* return the size or -1 if error */
367int load_image(const char *filename, uint8_t *addr)
368{
369 int fd, size;
370 fd = open(filename, O_RDONLY);
371 if (fd < 0)
372 return -1;
373 size = lseek(fd, 0, SEEK_END);
374 lseek(fd, 0, SEEK_SET);
375 if (read(fd, addr, size) != size) {
376 close(fd);
377 return -1;
378 }
379 close(fd);
380 return size;
381}
382
383void cpu_x86_outb(CPUX86State *env, int addr, int val)
384{
fc01f7e7 385 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
0824d6fc
FB		 386}
387
388void cpu_x86_outw(CPUX86State *env, int addr, int val)
389{
fc01f7e7 390 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
0824d6fc
FB		 391}
392
393void cpu_x86_outl(CPUX86State *env, int addr, int val)
394{
fc01f7e7 395 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
0824d6fc
FB		 396}
397
398int cpu_x86_inb(CPUX86State *env, int addr)
399{
fc01f7e7 400 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
0824d6fc
FB		 401}
402
403int cpu_x86_inw(CPUX86State *env, int addr)
404{
fc01f7e7 405 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
0824d6fc
FB		 406}
407
408int cpu_x86_inl(CPUX86State *env, int addr)
409{
fc01f7e7 410 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
0824d6fc
FB		 411}
412
413/***********************************************************/
414void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
415{
416}
417
418void hw_error(const char *fmt, ...)
419{
420 va_list ap;
421
422 va_start(ap, fmt);
423 fprintf(stderr, "qemu: hardware error: ");
424 vfprintf(stderr, fmt, ap);
425 fprintf(stderr, "\n");
426#ifdef TARGET_I386
427 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
428#endif
429 va_end(ap);
430 abort();
431}
432
433/***********************************************************/
434/* vga emulation */
435static uint8_t vga_index;
436static uint8_t vga_regs[256];
437static int last_cursor_pos;
438
439void update_console_messages(void)
440{
441 int c, i, cursor_pos, eol;
442
443 cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8);
444 eol = 0;
445 for(i = last_cursor_pos; i < cursor_pos; i++) {
446 c = phys_ram_base[0xb8000 + (i) * 2];
447 if (c >= ' ') {
448 putchar(c);
449 eol = 0;
450 } else {
451 if (!eol)
452 putchar('\n');
453 eol = 1;
454 }
455 }
456 fflush(stdout);
457 last_cursor_pos = cursor_pos;
458}
459
460/* just to see first Linux console messages, we intercept cursor position */
461void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
462{
463 switch(addr) {
464 case 0x3d4:
465 vga_index = data;
466 break;
467 case 0x3d5:
468 vga_regs[vga_index] = data;
469 if (vga_index == 0x0f)
470 update_console_messages();
471 break;
472 }
473
474}
475
476/***********************************************************/
477/* cmos emulation */
478
479#define RTC_SECONDS 0
480#define RTC_SECONDS_ALARM 1
481#define RTC_MINUTES 2
482#define RTC_MINUTES_ALARM 3
483#define RTC_HOURS 4
484#define RTC_HOURS_ALARM 5
485#define RTC_ALARM_DONT_CARE 0xC0
486
487#define RTC_DAY_OF_WEEK 6
488#define RTC_DAY_OF_MONTH 7
489#define RTC_MONTH 8
490#define RTC_YEAR 9
491
492#define RTC_REG_A 10
493#define RTC_REG_B 11
494#define RTC_REG_C 12
495#define RTC_REG_D 13
496
497/* PC cmos mappings */
498#define REG_EQUIPMENT_BYTE 0x14
499
500uint8_t cmos_data[128];
501uint8_t cmos_index;
502
503void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
504{
505 if (addr == 0x70) {
506 cmos_index = data & 0x7f;
507 }
508}
509
510uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
511{
512 int ret;
513
514 if (addr == 0x70) {
515 return 0xff;
516 } else {
517 /* toggle update-in-progress bit for Linux (same hack as
518 plex86) */
519 ret = cmos_data[cmos_index];
520 if (cmos_index == RTC_REG_A)
521 cmos_data[RTC_REG_A] ^= 0x80;
522 else if (cmos_index == RTC_REG_C)
523 cmos_data[RTC_REG_C] = 0x00;
524 return ret;
525 }
526}
527
528
529static inline int to_bcd(int a)
530{
531 return ((a / 10) << 4) | (a % 10);
532}
533
534void cmos_init(void)
535{
536 struct tm *tm;
537 time_t ti;
330d0414 538 int val;
0824d6fc
FB		 539
540 ti = time(NULL);
541 tm = gmtime(&ti);
542 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
543 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
544 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
545 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
546 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
abd0aaff 547 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
0824d6fc
FB		 548 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
549
550 cmos_data[RTC_REG_A] = 0x26;
551 cmos_data[RTC_REG_B] = 0x02;
552 cmos_data[RTC_REG_C] = 0x00;
553 cmos_data[RTC_REG_D] = 0x80;
554
330d0414
FB		 555 /* various important CMOS locations needed by PC/Bochs bios */
556
0824d6fc
FB		 557 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
558
330d0414
FB		 559 /* memory size */
560 val = (phys_ram_size / 1024) - 1024;
561 if (val > 65535)
562 val = 65535;
563 cmos_data[0x17] = val;
564 cmos_data[0x18] = val >> 8;
565 cmos_data[0x30] = val;
566 cmos_data[0x31] = val >> 8;
567
568 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
569 if (val > 65535)
570 val = 65535;
571 cmos_data[0x34] = val;
572 cmos_data[0x35] = val >> 8;
573
574 cmos_data[0x3d] = 0x02; /* hard drive boot */
575
fc01f7e7
FB		 576 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
577 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
0824d6fc
FB		 578}
579
580/***********************************************************/
581/* 8259 pic emulation */
582
583typedef struct PicState {
584 uint8_t last_irr; /* edge detection */
585 uint8_t irr; /* interrupt request register */
586 uint8_t imr; /* interrupt mask register */
587 uint8_t isr; /* interrupt service register */
588 uint8_t priority_add; /* used to compute irq priority */
589 uint8_t irq_base;
590 uint8_t read_reg_select;
591 uint8_t special_mask;
592 uint8_t init_state;
593 uint8_t auto_eoi;
594 uint8_t rotate_on_autoeoi;
595 uint8_t init4; /* true if 4 byte init */
596} PicState;
597
598/* 0 is master pic, 1 is slave pic */
599PicState pics[2];
600int pic_irq_requested;
601
602/* set irq level. If an edge is detected, then the IRR is set to 1 */
603static inline void pic_set_irq1(PicState *s, int irq, int level)
604{
605 int mask;
606 mask = 1 << irq;
607 if (level) {
608 if ((s->last_irr & mask) == 0)
609 s->irr |= mask;
610 s->last_irr |= mask;
611 } else {
612 s->last_irr &= ~mask;
613 }
614}
615
616static inline int get_priority(PicState *s, int mask)
617{
618 int priority;
619 if (mask == 0)
620 return -1;
621 priority = 7;
622 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
623 priority--;
624 return priority;
625}
626
627/* return the pic wanted interrupt. return -1 if none */
628static int pic_get_irq(PicState *s)
629{
630 int mask, cur_priority, priority;
631
632 mask = s->irr & ~s->imr;
633 priority = get_priority(s, mask);
634 if (priority < 0)
635 return -1;
636 /* compute current priority */
637 cur_priority = get_priority(s, s->isr);
638 if (priority > cur_priority) {
639 /* higher priority found: an irq should be generated */
640 return priority;
641 } else {
642 return -1;
643 }
644}
645
c9159e53
FB		 646/* raise irq to CPU if necessary. must be called every time the active
647 irq may change */
648static void pic_update_irq(void)
0824d6fc
FB		 649{
650 int irq2, irq;
651
652 /* first look at slave pic */
653 irq2 = pic_get_irq(&pics[1]);
654 if (irq2 >= 0) {
655 /* if irq request by slave pic, signal master PIC */
656 pic_set_irq1(&pics[0], 2, 1);
657 pic_set_irq1(&pics[0], 2, 0);
658 }
659 /* look at requested irq */
660 irq = pic_get_irq(&pics[0]);
661 if (irq >= 0) {
662 if (irq == 2) {
663 /* from slave pic */
664 pic_irq_requested = 8 + irq2;
665 } else {
666 /* from master pic */
667 pic_irq_requested = irq;
668 }
c9159e53 669 cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
0824d6fc
FB		 670 }
671}
672
c9159e53
FB		 673#ifdef DEBUG_IRQ_LATENCY
674int64_t irq_time[16];
675int64_t cpu_get_ticks(void);
676#endif
b118d61e
FB		 677#ifdef DEBUG_PIC
678int irq_level[16];
679#endif
c9159e53
FB		 680
681void pic_set_irq(int irq, int level)
682{
b118d61e
FB		 683#ifdef DEBUG_PIC
684 if (level != irq_level[irq]) {
685 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
686 irq_level[irq] = level;
687 }
688#endif
c9159e53
FB		 689#ifdef DEBUG_IRQ_LATENCY
690 if (level) {
691 irq_time[irq] = cpu_get_ticks();
692 }
693#endif
694 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
695 pic_update_irq();
696}
697
0824d6fc
FB		 698int cpu_x86_get_pic_interrupt(CPUX86State *env)
699{
700 int irq, irq2, intno;
701
702 /* signal the pic that the irq was acked by the CPU */
703 irq = pic_irq_requested;
c9159e53
FB		 704#ifdef DEBUG_IRQ_LATENCY
705 printf("IRQ%d latency=%Ld\n", irq, cpu_get_ticks() - irq_time[irq]);
706#endif
b118d61e
FB		 707#ifdef DEBUG_PIC
708 printf("pic_interrupt: irq=%d\n", irq);
709#endif
c9159e53 710
0824d6fc
FB		 711 if (irq >= 8) {
712 irq2 = irq & 7;
713 pics[1].isr |= (1 << irq2);
714 pics[1].irr &= ~(1 << irq2);
715 irq = 2;
716 intno = pics[1].irq_base + irq2;
717 } else {
718 intno = pics[0].irq_base + irq;
719 }
720 pics[0].isr |= (1 << irq);
721 pics[0].irr &= ~(1 << irq);
722 return intno;
723}
724
725void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
726{
727 PicState *s;
728 int priority;
729
b118d61e
FB		 730#ifdef DEBUG_PIC
731 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
732#endif
0824d6fc
FB		 733 s = &pics[addr >> 7];
734 addr &= 1;
735 if (addr == 0) {
736 if (val & 0x10) {
737 /* init */
738 memset(s, 0, sizeof(PicState));
739 s->init_state = 1;
740 s->init4 = val & 1;
741 if (val & 0x02)
742 hw_error("single mode not supported");
743 if (val & 0x08)
744 hw_error("level sensitive irq not supported");
745 } else if (val & 0x08) {
746 if (val & 0x02)
747 s->read_reg_select = val & 1;
748 if (val & 0x40)
749 s->special_mask = (val >> 5) & 1;
750 } else {
751 switch(val) {
752 case 0x00:
753 case 0x80:
754 s->rotate_on_autoeoi = val >> 7;
755 break;
756 case 0x20: /* end of interrupt */
757 case 0xa0:
758 priority = get_priority(s, s->isr);
759 if (priority >= 0) {
760 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
761 }
762 if (val == 0xa0)
763 s->priority_add = (s->priority_add + 1) & 7;
764 break;
765 case 0x60 ... 0x67:
766 priority = val & 7;
767 s->isr &= ~(1 << priority);
768 break;
769 case 0xc0 ... 0xc7:
770 s->priority_add = (val + 1) & 7;
771 break;
772 case 0xe0 ... 0xe7:
773 priority = val & 7;
774 s->isr &= ~(1 << priority);
775 s->priority_add = (priority + 1) & 7;
776 break;
777 }
778 }
779 } else {
780 switch(s->init_state) {
781 case 0:
782 /* normal mode */
783 s->imr = val;
c9159e53 784 pic_update_irq();
0824d6fc
FB		 785 break;
786 case 1:
787 s->irq_base = val & 0xf8;
788 s->init_state = 2;
789 break;
790 case 2:
791 if (s->init4) {
792 s->init_state = 3;
793 } else {
794 s->init_state = 0;
795 }
796 break;
797 case 3:
798 s->auto_eoi = (val >> 1) & 1;
799 s->init_state = 0;
800 break;
801 }
802 }
803}
804
b118d61e 805uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1)
0824d6fc
FB		 806{
807 PicState *s;
b118d61e
FB		 808 unsigned int addr;
809 int ret;
810
811 addr = addr1;
0824d6fc
FB		 812 s = &pics[addr >> 7];
813 addr &= 1;
814 if (addr == 0) {
815 if (s->read_reg_select)
b118d61e 816 ret = s->isr;
0824d6fc 817 else
b118d61e 818 ret = s->irr;
0824d6fc 819 } else {
b118d61e 820 ret = s->imr;
0824d6fc 821 }
b118d61e
FB		 822#ifdef DEBUG_PIC
823 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
824#endif
825 return ret;
0824d6fc
FB		 826}
827
828void pic_init(void)
829{
fc01f7e7
FB		 830 register_ioport_write(0x20, 2, pic_ioport_write, 1);
831 register_ioport_read(0x20, 2, pic_ioport_read, 1);
832 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
833 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
0824d6fc
FB		 834}
835
836/***********************************************************/
837/* 8253 PIT emulation */
838
839#define PIT_FREQ 1193182
840
841#define RW_STATE_LSB 0
842#define RW_STATE_MSB 1
843#define RW_STATE_WORD0 2
844#define RW_STATE_WORD1 3
845#define RW_STATE_LATCHED_WORD0 4
846#define RW_STATE_LATCHED_WORD1 5
847
848typedef struct PITChannelState {
87858c89 849 int count; /* can be 65536 */
0824d6fc
FB		 850 uint16_t latched_count;
851 uint8_t rw_state;
852 uint8_t mode;
853 uint8_t bcd; /* not supported */
854 uint8_t gate; /* timer start */
855 int64_t count_load_time;
87858c89 856 int64_t count_last_edge_check_time;
0824d6fc
FB		 857} PITChannelState;
858
859PITChannelState pit_channels[3];
860int speaker_data_on;
61a2ad53 861int dummy_refresh_clock;
87858c89 862int pit_min_timer_count = 0;
0824d6fc
FB		 863
864int64_t ticks_per_sec;
865
866int64_t get_clock(void)
867{
868 struct timeval tv;
869 gettimeofday(&tv, NULL);
870 return tv.tv_sec * 1000000LL + tv.tv_usec;
871}
872
873int64_t cpu_get_ticks(void)
874{
875 int64_t val;
876 asm("rdtsc" : "=A" (val));
877 return val;
878}
879
880void cpu_calibrate_ticks(void)
881{
882 int64_t usec, ticks;
883
884 usec = get_clock();
885 ticks = cpu_get_ticks();
886 usleep(50 * 1000);
887 usec = get_clock() - usec;
888 ticks = cpu_get_ticks() - ticks;
889 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
890}
891
87858c89
FB		 892/* compute with 96 bit intermediate result: (a*b)/c */
893static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
894{
895 union {
896 uint64_t ll;
897 struct {
898#ifdef WORDS_BIGENDIAN
899 uint32_t high, low;
900#else
901 uint32_t low, high;
902#endif
903 } l;
904 } u, res;
905 uint64_t rl, rh;
906
907 u.ll = a;
908 rl = (uint64_t)u.l.low * (uint64_t)b;
909 rh = (uint64_t)u.l.high * (uint64_t)b;
910 rh += (rl >> 32);
911 res.l.high = rh / c;
912 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
913 return res.ll;
914}
915
0824d6fc
FB		 916static int pit_get_count(PITChannelState *s)
917{
87858c89 918 uint64_t d;
0824d6fc
FB		 919 int counter;
920
87858c89 921 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
0824d6fc
FB		 922 switch(s->mode) {
923 case 0:
924 case 1:
925 case 4:
926 case 5:
927 counter = (s->count - d) & 0xffff;
928 break;
929 default:
930 counter = s->count - (d % s->count);
931 break;
932 }
933 return counter;
934}
935
936/* get pit output bit */
937static int pit_get_out(PITChannelState *s)
938{
87858c89 939 uint64_t d;
0824d6fc
FB		 940 int out;
941
87858c89 942 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
0824d6fc
FB		 943 switch(s->mode) {
944 default:
945 case 0:
946 out = (d >= s->count);
947 break;
948 case 1:
949 out = (d < s->count);
950 break;
951 case 2:
952 if ((d % s->count) == 0 && d != 0)
953 out = 1;
954 else
955 out = 0;
956 break;
957 case 3:
958 out = (d % s->count) < (s->count >> 1);
959 break;
960 case 4:
961 case 5:
962 out = (d == s->count);
963 break;
964 }
965 return out;
966}
967
87858c89
FB		 968/* get the number of 0 to 1 transitions we had since we call this
969 function */
970/* XXX: maybe better to use ticks precision to avoid getting edges
971 twice if checks are done at very small intervals */
972static int pit_get_out_edges(PITChannelState *s)
973{
974 uint64_t d1, d2;
975 int64_t ticks;
976 int ret, v;
977
978 ticks = cpu_get_ticks();
979 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
980 PIT_FREQ, ticks_per_sec);
981 d2 = muldiv64(ticks - s->count_load_time,
982 PIT_FREQ, ticks_per_sec);
983 s->count_last_edge_check_time = ticks;
984 switch(s->mode) {
985 default:
986 case 0:
987 if (d1 < s->count && d2 >= s->count)
988 ret = 1;
989 else
990 ret = 0;
991 break;
992 case 1:
993 ret = 0;
994 break;
995 case 2:
996 d1 /= s->count;
997 d2 /= s->count;
998 ret = d2 - d1;
999 break;
1000 case 3:
1001 v = s->count - (s->count >> 1);
1002 d1 = (d1 + v) / s->count;
1003 d2 = (d2 + v) / s->count;
1004 ret = d2 - d1;
1005 break;
1006 case 4:
1007 case 5:
1008 if (d1 < s->count && d2 >= s->count)
1009 ret = 1;
1010 else
1011 ret = 0;
1012 break;
1013 }
1014 return ret;
1015}
1016
1017static inline void pit_load_count(PITChannelState *s, int val)
1018{
1019 if (val == 0)
1020 val = 0x10000;
1021 s->count_load_time = cpu_get_ticks();
1022 s->count_last_edge_check_time = s->count_load_time;
1023 s->count = val;
1024 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
1025 fprintf(stderr,
1026 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
1027 PIT_FREQ / pit_min_timer_count);
1028 }
1029}
1030
0824d6fc
FB		 1031void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1032{
1033 int channel, access;
1034 PITChannelState *s;
87858c89 1035
0824d6fc
FB		 1036 addr &= 3;
1037 if (addr == 3) {
1038 channel = val >> 6;
1039 if (channel == 3)
1040 return;
1041 s = &pit_channels[channel];
1042 access = (val >> 4) & 3;
1043 switch(access) {
1044 case 0:
1045 s->latched_count = pit_get_count(s);
1046 s->rw_state = RW_STATE_LATCHED_WORD0;
1047 break;
1048 default:
87858c89
FB		 1049 s->mode = (val >> 1) & 7;
1050 s->bcd = val & 1;
0824d6fc
FB		 1051 s->rw_state = access - 1 + RW_STATE_LSB;
1052 break;
1053 }
0824d6fc
FB		 1054 } else {
1055 s = &pit_channels[addr];
1056 switch(s->rw_state) {
1057 case RW_STATE_LSB:
87858c89 1058 pit_load_count(s, val);
0824d6fc
FB		 1059 break;
1060 case RW_STATE_MSB:
87858c89 1061 pit_load_count(s, val << 8);
0824d6fc
FB		 1062 break;
1063 case RW_STATE_WORD0:
1064 case RW_STATE_WORD1:
1065 if (s->rw_state & 1) {
87858c89 1066 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
0824d6fc
FB		 1067 } else {
1068 s->latched_count = val;
1069 }
1070 s->rw_state ^= 1;
1071 break;
1072 }
1073 }
1074}
1075
1076uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
1077{
1078 int ret, count;
1079 PITChannelState *s;
1080
1081 addr &= 3;
1082 s = &pit_channels[addr];
1083 switch(s->rw_state) {
1084 case RW_STATE_LSB:
1085 case RW_STATE_MSB:
1086 case RW_STATE_WORD0:
1087 case RW_STATE_WORD1:
1088 count = pit_get_count(s);
1089 if (s->rw_state & 1)
1090 ret = (count >> 8) & 0xff;
1091 else
1092 ret = count & 0xff;
1093 if (s->rw_state & 2)
1094 s->rw_state ^= 1;
1095 break;
1096 default:
1097 case RW_STATE_LATCHED_WORD0:
1098 case RW_STATE_LATCHED_WORD1:
1099 if (s->rw_state & 1)
1100 ret = s->latched_count >> 8;
1101 else
1102 ret = s->latched_count & 0xff;
1103 s->rw_state ^= 1;
1104 break;
1105 }
1106 return ret;
1107}
1108
1109void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1110{
1111 speaker_data_on = (val >> 1) & 1;
1112 pit_channels[2].gate = val & 1;
1113}
1114
1115uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1116{
1117 int out;
1118 out = pit_get_out(&pit_channels[2]);
61a2ad53
FB		 1119 dummy_refresh_clock ^= 1;
1120 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1121 (dummy_refresh_clock << 4);
0824d6fc
FB		 1122}
1123
1124void pit_init(void)
1125{
87858c89
FB		 1126 PITChannelState *s;
1127 int i;
1128
1129 cpu_calibrate_ticks();
1130
1131 for(i = 0;i < 3; i++) {
1132 s = &pit_channels[i];
1133 s->mode = 3;
1134 s->gate = (i != 2);
1135 pit_load_count(s, 0);
1136 }
1137
fc01f7e7
FB		 1138 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1139 register_ioport_read(0x40, 3, pit_ioport_read, 1);
0824d6fc 1140
fc01f7e7
FB		 1141 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1142 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
0824d6fc
FB		 1143}
1144
1145/***********************************************************/
1146/* serial port emulation */
1147
1148#define UART_IRQ 4
1149
1150#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1151
1152#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1153#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1154#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1155#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1156
1157#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1158#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1159
1160#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1161#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1162#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1163#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1164
1165#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1166#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1167#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1168#define UART_LSR_FE 0x08 /* Frame error indicator */
1169#define UART_LSR_PE 0x04 /* Parity error indicator */
1170#define UART_LSR_OE 0x02 /* Overrun error indicator */
1171#define UART_LSR_DR 0x01 /* Receiver data ready */
1172
1173typedef struct SerialState {
1174 uint8_t divider;
1175 uint8_t rbr; /* receive register */
1176 uint8_t ier;
1177 uint8_t iir; /* read only */
1178 uint8_t lcr;
1179 uint8_t mcr;
1180 uint8_t lsr; /* read only */
1181 uint8_t msr;
1182 uint8_t scr;
1183} SerialState;
1184
1185SerialState serial_ports[1];
1186
1187void serial_update_irq(void)
1188{
1189 SerialState *s = &serial_ports[0];
1190
1191 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1192 s->iir = UART_IIR_RDI;
1193 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
1194 s->iir = UART_IIR_THRI;
1195 } else {
1196 s->iir = UART_IIR_NO_INT;
1197 }
1198 if (s->iir != UART_IIR_NO_INT) {
1199 pic_set_irq(UART_IRQ, 1);
1200 } else {
1201 pic_set_irq(UART_IRQ, 0);
1202 }
1203}
1204
1205void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1206{
1207 SerialState *s = &serial_ports[0];
1208 unsigned char ch;
1209 int ret;
1210
1211 addr &= 7;
1212 switch(addr) {
1213 default:
1214 case 0:
1215 if (s->lcr & UART_LCR_DLAB) {
1216 s->divider = (s->divider & 0xff00) | val;
1217 } else {
1218 s->lsr &= ~UART_LSR_THRE;
1219 serial_update_irq();
1220
1221 ch = val;
1222 do {
1223 ret = write(1, &ch, 1);
1224 } while (ret != 1);
1225 s->lsr |= UART_LSR_THRE;
1226 s->lsr |= UART_LSR_TEMT;
1227 serial_update_irq();
1228 }
1229 break;
1230 case 1:
1231 if (s->lcr & UART_LCR_DLAB) {
1232 s->divider = (s->divider & 0x00ff) | (val << 8);
1233 } else {
1234 s->ier = val;
1235 serial_update_irq();
1236 }
1237 break;
1238 case 2:
1239 break;
1240 case 3:
1241 s->lcr = val;
1242 break;
1243 case 4:
1244 s->mcr = val;
1245 break;
1246 case 5:
1247 break;
1248 case 6:
1249 s->msr = val;
1250 break;
1251 case 7:
1252 s->scr = val;
1253 break;
1254 }
1255}
1256
1257uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1258{
1259 SerialState *s = &serial_ports[0];
1260 uint32_t ret;
1261
1262 addr &= 7;
1263 switch(addr) {
1264 default:
1265 case 0:
1266 if (s->lcr & UART_LCR_DLAB) {
1267 ret = s->divider & 0xff;
1268 } else {
1269 ret = s->rbr;
1270 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1271 serial_update_irq();
1272 }
1273 break;
1274 case 1:
1275 if (s->lcr & UART_LCR_DLAB) {
1276 ret = (s->divider >> 8) & 0xff;
1277 } else {
1278 ret = s->ier;
1279 }
1280 break;
1281 case 2:
1282 ret = s->iir;
1283 break;
1284 case 3:
1285 ret = s->lcr;
1286 break;
1287 case 4:
1288 ret = s->mcr;
1289 break;
1290 case 5:
1291 ret = s->lsr;
1292 break;
1293 case 6:
1294 ret = s->msr;
1295 break;
1296 case 7:
1297 ret = s->scr;
1298 break;
1299 }
1300 return ret;
1301}
1302
1303#define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1304static int term_got_escape;
1305
1306void term_print_help(void)
1307{
1308 printf("\n"
1309 "C-a h print this help\n"
1310 "C-a x exit emulatior\n"
33e3963e 1311 "C-a s save disk data back to file (if -snapshot)\n"
0824d6fc
FB		 1312 "C-a b send break (magic sysrq)\n"
1313 "C-a C-a send C-a\n"
1314 );
1315}
1316
1317/* called when a char is received */
1318void serial_received_byte(SerialState *s, int ch)
1319{
1320 if (term_got_escape) {
1321 term_got_escape = 0;
1322 switch(ch) {
1323 case 'h':
1324 term_print_help();
1325 break;
1326 case 'x':
1327 exit(0);
1328 break;
33e3963e
FB		 1329 case 's':
1330 {
1331 int i;
1332 for (i = 0; i < MAX_DISKS; i++) {
1333 if (bs_table[i])
1334 bdrv_commit(bs_table[i]);
1335 }
1336 }
1337 break;
0824d6fc
FB		 1338 case 'b':
1339 /* send break */
1340 s->rbr = 0;
1341 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1342 serial_update_irq();
1343 break;
1344 case TERM_ESCAPE:
1345 goto send_char;
1346 }
1347 } else if (ch == TERM_ESCAPE) {
1348 term_got_escape = 1;
1349 } else {
1350 send_char:
1351 s->rbr = ch;
1352 s->lsr |= UART_LSR_DR;
1353 serial_update_irq();
1354 }
1355}
1356
1357/* init terminal so that we can grab keys */
1358static struct termios oldtty;
1359
1360static void term_exit(void)
1361{
1362 tcsetattr (0, TCSANOW, &oldtty);
1363}
1364
1365static void term_init(void)
1366{
1367 struct termios tty;
1368
1369 tcgetattr (0, &tty);
1370 oldtty = tty;
1371
1372 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
1373 |INLCR|IGNCR|ICRNL|IXON);
1374 tty.c_oflag |= OPOST;
1375 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
1376 tty.c_cflag &= ~(CSIZE|PARENB);
1377 tty.c_cflag |= CS8;
1378 tty.c_cc[VMIN] = 1;
1379 tty.c_cc[VTIME] = 0;
1380
1381 tcsetattr (0, TCSANOW, &tty);
1382
1383 atexit(term_exit);
1384
1385 fcntl(0, F_SETFL, O_NONBLOCK);
1386}
1387
1388void serial_init(void)
1389{
1390 SerialState *s = &serial_ports[0];
1391
1392 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1393
fc01f7e7
FB		 1394 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1395 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
0824d6fc
FB		 1396
1397 term_init();
1398}
1399
f1510b2c
FB		 1400/***********************************************************/
1401/* ne2000 emulation */
1402
f1510b2c
FB		 1403#define NE2000_IOPORT 0x300
1404#define NE2000_IRQ 9
1405
1406#define MAX_ETH_FRAME_SIZE 1514
1407
1408#define E8390_CMD 0x00 /* The command register (for all pages) */
1409/* Page 0 register offsets. */
1410#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1411#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1412#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1413#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1414#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1415#define EN0_TSR 0x04 /* Transmit status reg RD */
1416#define EN0_TPSR 0x04 /* Transmit starting page WR */
1417#define EN0_NCR 0x05 /* Number of collision reg RD */
1418#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1419#define EN0_FIFO 0x06 /* FIFO RD */
1420#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1421#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1422#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1423#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1424#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1425#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1426#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1427#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1428#define EN0_RSR 0x0c /* rx status reg RD */
1429#define EN0_RXCR 0x0c /* RX configuration reg WR */
1430#define EN0_TXCR 0x0d /* TX configuration reg WR */
1431#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1432#define EN0_DCFG 0x0e /* Data configuration reg WR */
1433#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1434#define EN0_IMR 0x0f /* Interrupt mask reg WR */
1435#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1436
1437#define EN1_PHYS 0x11
1438#define EN1_CURPAG 0x17
1439#define EN1_MULT 0x18
1440
1441/* Register accessed at EN_CMD, the 8390 base addr. */
1442#define E8390_STOP 0x01 /* Stop and reset the chip */
1443#define E8390_START 0x02 /* Start the chip, clear reset */
1444#define E8390_TRANS 0x04 /* Transmit a frame */
1445#define E8390_RREAD 0x08 /* Remote read */
1446#define E8390_RWRITE 0x10 /* Remote write */
1447#define E8390_NODMA 0x20 /* Remote DMA */
1448#define E8390_PAGE0 0x00 /* Select page chip registers */
1449#define E8390_PAGE1 0x40 /* using the two high-order bits */
1450#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1451
1452/* Bits in EN0_ISR - Interrupt status register */
1453#define ENISR_RX 0x01 /* Receiver, no error */
1454#define ENISR_TX 0x02 /* Transmitter, no error */
1455#define ENISR_RX_ERR 0x04 /* Receiver, with error */
1456#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1457#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1458#define ENISR_COUNTERS 0x20 /* Counters need emptying */
1459#define ENISR_RDC 0x40 /* remote dma complete */
1460#define ENISR_RESET 0x80 /* Reset completed */
1461#define ENISR_ALL 0x3f /* Interrupts we will enable */
1462
1463/* Bits in received packet status byte and EN0_RSR*/
1464#define ENRSR_RXOK 0x01 /* Received a good packet */
1465#define ENRSR_CRC 0x02 /* CRC error */
1466#define ENRSR_FAE 0x04 /* frame alignment error */
1467#define ENRSR_FO 0x08 /* FIFO overrun */
1468#define ENRSR_MPA 0x10 /* missed pkt */
1469#define ENRSR_PHY 0x20 /* physical/multicast address */
1470#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1471#define ENRSR_DEF 0x80 /* deferring */
1472
1473/* Transmitted packet status, EN0_TSR. */
1474#define ENTSR_PTX 0x01 /* Packet transmitted without error */
1475#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1476#define ENTSR_COL 0x04 /* The transmit collided at least once. */
1477#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1478#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1479#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1480#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1481#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1482
1483#define NE2000_MEM_SIZE 32768
1484
1485typedef struct NE2000State {
1486 uint8_t cmd;
1487 uint32_t start;
1488 uint32_t stop;
1489 uint8_t boundary;
1490 uint8_t tsr;
1491 uint8_t tpsr;
1492 uint16_t tcnt;
1493 uint16_t rcnt;
1494 uint32_t rsar;
1495 uint8_t isr;
1496 uint8_t dcfg;
1497 uint8_t imr;
1498 uint8_t phys[6]; /* mac address */
1499 uint8_t curpag;
1500 uint8_t mult[8]; /* multicast mask array */
1501 uint8_t mem[NE2000_MEM_SIZE];
1502} NE2000State;
1503
1504NE2000State ne2000_state;
1505int net_fd = -1;
1506char network_script[1024];
1507
1508void ne2000_reset(void)
1509{
1510 NE2000State *s = &ne2000_state;
1511 int i;
1512
1513 s->isr = ENISR_RESET;
1514 s->mem[0] = 0x52;
1515 s->mem[1] = 0x54;
1516 s->mem[2] = 0x00;
1517 s->mem[3] = 0x12;
1518 s->mem[4] = 0x34;
1519 s->mem[5] = 0x56;
1520 s->mem[14] = 0x57;
1521 s->mem[15] = 0x57;
1522
1523 /* duplicate prom data */
1524 for(i = 15;i >= 0; i--) {
1525 s->mem[2 * i] = s->mem[i];
1526 s->mem[2 * i + 1] = s->mem[i];
1527 }
1528}
1529
1530void ne2000_update_irq(NE2000State *s)
1531{
1532 int isr;
1533 isr = s->isr & s->imr;
1534 if (isr)
1535 pic_set_irq(NE2000_IRQ, 1);
1536 else
1537 pic_set_irq(NE2000_IRQ, 0);
1538}
1539
1540int net_init(void)
1541{
1542 struct ifreq ifr;
1543 int fd, ret, pid, status;
1544
1545 fd = open("/dev/net/tun", O_RDWR);
1546 if (fd < 0) {
1547 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1548 return -1;
1549 }
1550 memset(&ifr, 0, sizeof(ifr));
1551 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1552 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1553 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1554 if (ret != 0) {
1555 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1556 close(fd);
1557 return -1;
1558 }
fc01f7e7 1559 printf("Connected to host network interface: %s\n", ifr.ifr_name);
f1510b2c
FB		 1560 fcntl(fd, F_SETFL, O_NONBLOCK);
1561 net_fd = fd;
1562
1563 /* try to launch network init script */
1564 pid = fork();
1565 if (pid >= 0) {
1566 if (pid == 0) {
1567 execl(network_script, network_script, ifr.ifr_name, NULL);
1568 exit(1);
1569 }
1570 while (waitpid(pid, &status, 0) != pid);
1571 if (!WIFEXITED(status) ||
1572 WEXITSTATUS(status) != 0) {
1573 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1574 network_script, ifr.ifr_name);
1575 }
1576 }
1577 return 0;
1578}
1579
1580void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1581{
1582#ifdef DEBUG_NE2000
1583 printf("NE2000: sending packet size=%d\n", size);
1584#endif
1585 write(net_fd, buf, size);
1586}
1587
1588/* return true if the NE2000 can receive more data */
1589int ne2000_can_receive(NE2000State *s)
1590{
1591 int avail, index, boundary;
1592
1593 if (s->cmd & E8390_STOP)
1594 return 0;
1595 index = s->curpag << 8;
1596 boundary = s->boundary << 8;
1597 if (index < boundary)
1598 avail = boundary - index;
1599 else
1600 avail = (s->stop - s->start) - (index - boundary);
1601 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1602 return 0;
1603 return 1;
1604}
1605
1606void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1607{
1608 uint8_t *p;
1609 int total_len, next, avail, len, index;
1610
1611#if defined(DEBUG_NE2000)
1612 printf("NE2000: received len=%d\n", size);
1613#endif
1614
1615 index = s->curpag << 8;
1616 /* 4 bytes for header */
1617 total_len = size + 4;
1618 /* address for next packet (4 bytes for CRC) */
1619 next = index + ((total_len + 4 + 255) & ~0xff);
1620 if (next >= s->stop)
1621 next -= (s->stop - s->start);
1622 /* prepare packet header */
1623 p = s->mem + index;
1624 p[0] = ENRSR_RXOK; /* receive status */
1625 p[1] = next >> 8;
1626 p[2] = total_len;
1627 p[3] = total_len >> 8;
1628 index += 4;
1629
1630 /* write packet data */
1631 while (size > 0) {
1632 avail = s->stop - index;
1633 len = size;
1634 if (len > avail)
1635 len = avail;
1636 memcpy(s->mem + index, buf, len);
1637 buf += len;
1638 index += len;
1639 if (index == s->stop)
1640 index = s->start;
1641 size -= len;
1642 }
1643 s->curpag = next >> 8;
1644
1645 /* now we can signal we have receive something */
1646 s->isr |= ENISR_RX;
1647 ne2000_update_irq(s);
1648}
1649
1650void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1651{
1652 NE2000State *s = &ne2000_state;
1653 int offset, page;
1654
1655 addr &= 0xf;
1656#ifdef DEBUG_NE2000
1657 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1658#endif
1659 if (addr == E8390_CMD) {
1660 /* control register */
1661 s->cmd = val;
1662 if (val & E8390_START) {
1663 /* test specific case: zero length transfert */
1664 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1665 s->rcnt == 0) {
1666 s->isr |= ENISR_RDC;
1667 ne2000_update_irq(s);
1668 }
1669 if (val & E8390_TRANS) {
1670 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1671 /* signal end of transfert */
1672 s->tsr = ENTSR_PTX;
1673 s->isr |= ENISR_TX;
1674 ne2000_update_irq(s);
1675 }
1676 }
1677 } else {
1678 page = s->cmd >> 6;
1679 offset = addr | (page << 4);
1680 switch(offset) {
1681 case EN0_STARTPG:
1682 s->start = val << 8;
1683 break;
1684 case EN0_STOPPG:
1685 s->stop = val << 8;
1686 break;
1687 case EN0_BOUNDARY:
1688 s->boundary = val;
1689 break;
1690 case EN0_IMR:
1691 s->imr = val;
1692 ne2000_update_irq(s);
1693 break;
1694 case EN0_TPSR:
1695 s->tpsr = val;
1696 break;
1697 case EN0_TCNTLO:
1698 s->tcnt = (s->tcnt & 0xff00) | val;
1699 break;
1700 case EN0_TCNTHI:
1701 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1702 break;
1703 case EN0_RSARLO:
1704 s->rsar = (s->rsar & 0xff00) | val;
1705 break;
1706 case EN0_RSARHI:
1707 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1708 break;
1709 case EN0_RCNTLO:
1710 s->rcnt = (s->rcnt & 0xff00) | val;
1711 break;
1712 case EN0_RCNTHI:
1713 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1714 break;
1715 case EN0_DCFG:
1716 s->dcfg = val;
1717 break;
1718 case EN0_ISR:
1719 s->isr &= ~val;
1720 ne2000_update_irq(s);
1721 break;
1722 case EN1_PHYS ... EN1_PHYS + 5:
1723 s->phys[offset - EN1_PHYS] = val;
1724 break;
1725 case EN1_CURPAG:
1726 s->curpag = val;
1727 break;
1728 case EN1_MULT ... EN1_MULT + 7:
1729 s->mult[offset - EN1_MULT] = val;
1730 break;
1731 }
1732 }
1733}
1734
1735uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1736{
1737 NE2000State *s = &ne2000_state;
1738 int offset, page, ret;
1739
1740 addr &= 0xf;
1741 if (addr == E8390_CMD) {
1742 ret = s->cmd;
1743 } else {
1744 page = s->cmd >> 6;
1745 offset = addr | (page << 4);
1746 switch(offset) {
1747 case EN0_TSR:
1748 ret = s->tsr;
1749 break;
1750 case EN0_BOUNDARY:
1751 ret = s->boundary;
1752 break;
1753 case EN0_ISR:
1754 ret = s->isr;
1755 break;
1756 case EN1_PHYS ... EN1_PHYS + 5:
1757 ret = s->phys[offset - EN1_PHYS];
1758 break;
1759 case EN1_CURPAG:
1760 ret = s->curpag;
1761 break;
1762 case EN1_MULT ... EN1_MULT + 7:
1763 ret = s->mult[offset - EN1_MULT];
1764 break;
1765 default:
1766 ret = 0x00;
1767 break;
1768 }
1769 }
1770#ifdef DEBUG_NE2000
1771 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1772#endif
1773 return ret;
1774}
1775
1776void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1777{
1778 NE2000State *s = &ne2000_state;
1779 uint8_t *p;
1780
1781#ifdef DEBUG_NE2000
1782 printf("NE2000: asic write val=0x%04x\n", val);
1783#endif
1784 p = s->mem + s->rsar;
1785 if (s->dcfg & 0x01) {
1786 /* 16 bit access */
1787 p[0] = val;
1788 p[1] = val >> 8;
1789 s->rsar += 2;
1790 s->rcnt -= 2;
1791 } else {
1792 /* 8 bit access */
1793 p[0] = val;
1794 s->rsar++;
1795 s->rcnt--;
1796 }
1797 /* wrap */
1798 if (s->rsar == s->stop)
1799 s->rsar = s->start;
1800 if (s->rcnt == 0) {
1801 /* signal end of transfert */
1802 s->isr |= ENISR_RDC;
1803 ne2000_update_irq(s);
1804 }
1805}
1806
1807uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1808{
1809 NE2000State *s = &ne2000_state;
1810 uint8_t *p;
1811 int ret;
1812
1813 p = s->mem + s->rsar;
1814 if (s->dcfg & 0x01) {
1815 /* 16 bit access */
1816 ret = p[0] | (p[1] << 8);
1817 s->rsar += 2;
1818 s->rcnt -= 2;
1819 } else {
1820 /* 8 bit access */
1821 ret = p[0];
1822 s->rsar++;
1823 s->rcnt--;
1824 }
1825 /* wrap */
1826 if (s->rsar == s->stop)
1827 s->rsar = s->start;
1828 if (s->rcnt == 0) {
1829 /* signal end of transfert */
1830 s->isr |= ENISR_RDC;
1831 ne2000_update_irq(s);
1832 }
1833#ifdef DEBUG_NE2000
1834 printf("NE2000: asic read val=0x%04x\n", ret);
1835#endif
1836 return ret;
1837}
1838
1839void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1840{
1841 /* nothing to do (end of reset pulse) */
1842}
1843
1844uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1845{
1846 ne2000_reset();
1847 return 0;
1848}
1849
1850void ne2000_init(void)
1851{
fc01f7e7
FB		 1852 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1853 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
f1510b2c 1854
fc01f7e7
FB		 1855 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1856 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1857 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1858 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
f1510b2c 1859
fc01f7e7
FB		 1860 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1861 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
f1510b2c
FB		 1862 ne2000_reset();
1863}
1864
fc01f7e7
FB		 1865/***********************************************************/
1866/* ide emulation */
1867
fc01f7e7
FB		 1868/* Bits of HD_STATUS */
1869#define ERR_STAT 0x01
1870#define INDEX_STAT 0x02
1871#define ECC_STAT 0x04 /* Corrected error */
1872#define DRQ_STAT 0x08
1873#define SEEK_STAT 0x10
1874#define SRV_STAT 0x10
1875#define WRERR_STAT 0x20
1876#define READY_STAT 0x40
1877#define BUSY_STAT 0x80
1878
1879/* Bits for HD_ERROR */
1880#define MARK_ERR 0x01 /* Bad address mark */
1881#define TRK0_ERR 0x02 /* couldn't find track 0 */
1882#define ABRT_ERR 0x04 /* Command aborted */
1883#define MCR_ERR 0x08 /* media change request */
1884#define ID_ERR 0x10 /* ID field not found */
1885#define MC_ERR 0x20 /* media changed */
1886#define ECC_ERR 0x40 /* Uncorrectable ECC error */
1887#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1888#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1889
1890/* Bits of HD_NSECTOR */
1891#define CD 0x01
1892#define IO 0x02
1893#define REL 0x04
1894#define TAG_MASK 0xf8
1895
1896#define IDE_CMD_RESET 0x04
1897#define IDE_CMD_DISABLE_IRQ 0x02
1898
1899/* ATA/ATAPI Commands pre T13 Spec */
1900#define WIN_NOP 0x00
1901/*
1902 * 0x01->0x02 Reserved
1903 */
1904#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1905/*
1906 * 0x04->0x07 Reserved
1907 */
1908#define WIN_SRST 0x08 /* ATAPI soft reset command */
1909#define WIN_DEVICE_RESET 0x08
1910/*
1911 * 0x09->0x0F Reserved
1912 */
1913#define WIN_RECAL 0x10
1914#define WIN_RESTORE WIN_RECAL
1915/*
1916 * 0x10->0x1F Reserved
1917 */
1918#define WIN_READ 0x20 /* 28-Bit */
1919#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1920#define WIN_READ_LONG 0x22 /* 28-Bit */
1921#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1922#define WIN_READ_EXT 0x24 /* 48-Bit */
1923#define WIN_READDMA_EXT 0x25 /* 48-Bit */
1924#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1925#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1926/*
1927 * 0x28
1928 */
1929#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1930/*
1931 * 0x2A->0x2F Reserved
1932 */
1933#define WIN_WRITE 0x30 /* 28-Bit */
1934#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1935#define WIN_WRITE_LONG 0x32 /* 28-Bit */
1936#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1937#define WIN_WRITE_EXT 0x34 /* 48-Bit */
1938#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1939#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1940#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1941#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1942#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1943/*
1944 * 0x3A->0x3B Reserved
1945 */
1946#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1947/*
1948 * 0x3D->0x3F Reserved
1949 */
1950#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1951#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1952#define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1953/*
1954 * 0x43->0x4F Reserved
1955 */
1956#define WIN_FORMAT 0x50
1957/*
1958 * 0x51->0x5F Reserved
1959 */
1960#define WIN_INIT 0x60
1961/*
1962 * 0x61->0x5F Reserved
1963 */
1964#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1965#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1966#define WIN_DIAGNOSE 0x90
1967#define WIN_SPECIFY 0x91 /* set drive geometry translation */
1968#define WIN_DOWNLOAD_MICROCODE 0x92
1969#define WIN_STANDBYNOW2 0x94
1970#define WIN_STANDBY2 0x96
1971#define WIN_SETIDLE2 0x97
1972#define WIN_CHECKPOWERMODE2 0x98
1973#define WIN_SLEEPNOW2 0x99
1974/*
1975 * 0x9A VENDOR
1976 */
1977#define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1978#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1979#define WIN_QUEUED_SERVICE 0xA2
1980#define WIN_SMART 0xB0 /* self-monitoring and reporting */
1981#define CFA_ERASE_SECTORS 0xC0
1982#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1983#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1984#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1985#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1986#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1987#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1988#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1989#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1990#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1991#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1992#define WIN_GETMEDIASTATUS 0xDA
1993#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1994#define WIN_POSTBOOT 0xDC
1995#define WIN_PREBOOT 0xDD
1996#define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1997#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1998#define WIN_STANDBYNOW1 0xE0
1999#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
2000#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
2001#define WIN_SETIDLE1 0xE3
2002#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
2003#define WIN_CHECKPOWERMODE1 0xE5
2004#define WIN_SLEEPNOW1 0xE6
2005#define WIN_FLUSH_CACHE 0xE7
2006#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
2007#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
2008 /* SET_FEATURES 0x22 or 0xDD */
2009#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
2010#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
2011#define WIN_MEDIAEJECT 0xED
2012#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
2013#define WIN_SETFEATURES 0xEF /* set special drive features */
2014#define EXABYTE_ENABLE_NEST 0xF0
2015#define WIN_SECURITY_SET_PASS 0xF1
2016#define WIN_SECURITY_UNLOCK 0xF2
2017#define WIN_SECURITY_ERASE_PREPARE 0xF3
2018#define WIN_SECURITY_ERASE_UNIT 0xF4
2019#define WIN_SECURITY_FREEZE_LOCK 0xF5
2020#define WIN_SECURITY_DISABLE 0xF6
2021#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
2022#define WIN_SET_MAX 0xF9
2023#define DISABLE_SEAGATE 0xFB
2024
c9159e53
FB		 2025/* set to 1 set disable mult support */
2026#define MAX_MULT_SECTORS 8
fc01f7e7 2027
fc01f7e7
FB		 2028struct IDEState;
2029
2030typedef void EndTransferFunc(struct IDEState *);
2031
2032typedef struct IDEState {
2033 /* ide config */
2034 int cylinders, heads, sectors;
2035 int64_t nb_sectors;
2036 int mult_sectors;
2037 int irq;
2038 /* ide regs */
2039 uint8_t feature;
2040 uint8_t error;
c9159e53 2041 uint16_t nsector; /* 0 is 256 to ease computations */
fc01f7e7
FB		 2042 uint8_t sector;
2043 uint8_t lcyl;
2044 uint8_t hcyl;
2045 uint8_t select;
2046 uint8_t status;
2047 /* 0x3f6 command, only meaningful for drive 0 */
2048 uint8_t cmd;
2049 /* depends on bit 4 in select, only meaningful for drive 0 */
2050 struct IDEState *cur_drive;
2051 BlockDriverState *bs;
c9159e53 2052 int req_nb_sectors; /* number of sectors per interrupt */
fc01f7e7
FB		 2053 EndTransferFunc *end_transfer_func;
2054 uint8_t *data_ptr;
2055 uint8_t *data_end;
2056 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
2057} IDEState;
2058
fc01f7e7
FB		 2059IDEState ide_state[MAX_DISKS];
2060
2061static void padstr(char *str, const char *src, int len)
2062{
2063 int i, v;
2064 for(i = 0; i < len; i++) {
2065 if (*src)
2066 v = *src++;
2067 else
2068 v = ' ';
2069 *(char *)((long)str ^ 1) = v;
2070 str++;
2071 }
2072}
2073
2074static void ide_identify(IDEState *s)
2075{
2076 uint16_t *p;
2077 unsigned int oldsize;
2078
2079 memset(s->io_buffer, 0, 512);
2080 p = (uint16_t *)s->io_buffer;
2081 stw(p + 0, 0x0040);
2082 stw(p + 1, s->cylinders);
2083 stw(p + 3, s->heads);
2084 stw(p + 4, 512 * s->sectors); /* sectors */
2085 stw(p + 5, 512); /* sector size */
2086 stw(p + 6, s->sectors);
2087 stw(p + 20, 3); /* buffer type */
2088 stw(p + 21, 512); /* cache size in sectors */
2089 stw(p + 22, 4); /* ecc bytes */
2090 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40);
c9159e53
FB		 2091#if MAX_MULT_SECTORS > 1
2092 stw(p + 47, MAX_MULT_SECTORS);
2093#endif
fc01f7e7
FB		 2094 stw(p + 48, 1); /* dword I/O */
2095 stw(p + 49, 1 << 9); /* LBA supported, no DMA */
2096 stw(p + 51, 0x200); /* PIO transfer cycle */
2097 stw(p + 52, 0x200); /* DMA transfer cycle */
2098 stw(p + 54, s->cylinders);
2099 stw(p + 55, s->heads);
2100 stw(p + 56, s->sectors);
2101 oldsize = s->cylinders * s->heads * s->sectors;
2102 stw(p + 57, oldsize);
2103 stw(p + 58, oldsize >> 16);
2104 if (s->mult_sectors)
2105 stw(p + 59, 0x100 | s->mult_sectors);
2106 stw(p + 60, s->nb_sectors);
2107 stw(p + 61, s->nb_sectors >> 16);
2108 stw(p + 80, (1 << 1) | (1 << 2));
2109 stw(p + 82, (1 << 14));
2110 stw(p + 83, (1 << 14));
2111 stw(p + 84, (1 << 14));
2112 stw(p + 85, (1 << 14));
2113 stw(p + 86, 0);
2114 stw(p + 87, (1 << 14));
2115}
2116
2117static inline void ide_abort_command(IDEState *s)
2118{
2119 s->status = READY_STAT | ERR_STAT;
2120 s->error = ABRT_ERR;
2121}
2122
2123static inline void ide_set_irq(IDEState *s)
2124{
2125 if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) {
2126 pic_set_irq(s->irq, 1);
fc01f7e7
FB		 2127 }
2128}
2129
2130/* prepare data transfer and tell what to do after */
2131static void ide_transfer_start(IDEState *s, int size,
2132 EndTransferFunc *end_transfer_func)
2133{
2134 s->end_transfer_func = end_transfer_func;
2135 s->data_ptr = s->io_buffer;
2136 s->data_end = s->io_buffer + size;
2137 s->status |= DRQ_STAT;
2138}
2139
2140static void ide_transfer_stop(IDEState *s)
2141{
2142 s->end_transfer_func = ide_transfer_stop;
2143 s->data_ptr = s->io_buffer;
2144 s->data_end = s->io_buffer;
2145 s->status &= ~DRQ_STAT;
2146}
2147
2148static int64_t ide_get_sector(IDEState *s)
2149{
2150 int64_t sector_num;
2151 if (s->select & 0x40) {
2152 /* lba */
2153 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
2154 (s->lcyl << 8) | s->sector;
2155 } else {
2156 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
2157 (s->select & 0x0f) * s->sectors +
2158 (s->sector - 1);
2159 }
2160 return sector_num;
2161}
2162
2163static void ide_set_sector(IDEState *s, int64_t sector_num)
2164{
2165 unsigned int cyl, r;
2166 if (s->select & 0x40) {
2167 s->select = (s->select & 0xf0) | (sector_num >> 24);
2168 s->hcyl = (sector_num >> 16);
2169 s->lcyl = (sector_num >> 8);
2170 s->sector = (sector_num);
2171 } else {
2172 cyl = sector_num / (s->heads * s->sectors);
2173 r = sector_num % (s->heads * s->sectors);
2174 s->hcyl = cyl >> 8;
2175 s->lcyl = cyl;
2176 s->select = (s->select & 0xf0) | (r / s->sectors);
2177 s->sector = (r % s->sectors) + 1;
2178 }
2179}
2180
2181static void ide_sector_read(IDEState *s)
2182{
2183 int64_t sector_num;
c9159e53 2184 int ret, n;
fc01f7e7
FB		 2185
2186 s->status = READY_STAT | SEEK_STAT;
2187 sector_num = ide_get_sector(s);
c9159e53
FB		 2188 n = s->nsector;
2189 if (n == 0) {
fc01f7e7
FB		 2190 /* no more sector to read from disk */
2191 ide_transfer_stop(s);
2192 } else {
2193#if defined(DEBUG_IDE)
2194 printf("read sector=%Ld\n", sector_num);
2195#endif
c9159e53
FB		 2196 if (n > s->req_nb_sectors)
2197 n = s->req_nb_sectors;
2198 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
2199 ide_transfer_start(s, 512 * n, ide_sector_read);
fc01f7e7 2200 ide_set_irq(s);
c9159e53
FB		 2201 ide_set_sector(s, sector_num + n);
2202 s->nsector -= n;
fc01f7e7 2203 }
fc01f7e7
FB		 2204}
2205
2206static void ide_sector_write(IDEState *s)
2207{
2208 int64_t sector_num;
c9159e53 2209 int ret, n, n1;
fc01f7e7
FB		 2210
2211 s->status = READY_STAT | SEEK_STAT;
2212 sector_num = ide_get_sector(s);
2213#if defined(DEBUG_IDE)
2214 printf("write sector=%Ld\n", sector_num);
2215#endif
c9159e53
FB		 2216 n = s->nsector;
2217 if (n > s->req_nb_sectors)
2218 n = s->req_nb_sectors;
2219 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
2220 s->nsector -= n;
fc01f7e7
FB		 2221 if (s->nsector == 0) {
2222 /* no more sector to write */
2223 ide_transfer_stop(s);
2224 } else {
c9159e53
FB		 2225 n1 = s->nsector;
2226 if (n1 > s->req_nb_sectors)
2227 n1 = s->req_nb_sectors;
2228 ide_transfer_start(s, 512 * n1, ide_sector_write);
fc01f7e7 2229 }
c9159e53 2230 ide_set_sector(s, sector_num + n);
fc01f7e7
FB		 2231 ide_set_irq(s);
2232}
2233
2234void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
2235{
2236 IDEState *s = ide_state[0].cur_drive;
c9159e53 2237 int unit, n;
fc01f7e7
FB		 2238
2239 addr &= 7;
2240#ifdef DEBUG_IDE
2241 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
2242#endif
2243 switch(addr) {
2244 case 0:
2245 break;
2246 case 1:
2247 s->feature = val;
2248 break;
2249 case 2:
c9159e53
FB		 2250 if (val == 0)
2251 val = 256;
fc01f7e7
FB		 2252 s->nsector = val;
2253 break;
2254 case 3:
2255 s->sector = val;
2256 break;
2257 case 4:
2258 s->lcyl = val;
2259 break;
2260 case 5:
2261 s->hcyl = val;
2262 break;
2263 case 6:
2264 /* select drive */
2265 unit = (val >> 4) & 1;
2266 s = &ide_state[unit];
2267 ide_state[0].cur_drive = s;
2268 s->select = val;
2269 break;
2270 default:
2271 case 7:
2272 /* command */
2273#if defined(DEBUG_IDE)
2274 printf("ide: CMD=%02x\n", val);
2275#endif
2276 switch(val) {
2277 case WIN_PIDENTIFY:
2278 case WIN_IDENTIFY:
2279 if (s->bs) {
2280 ide_identify(s);
2281 s->status = READY_STAT;
2282 ide_transfer_start(s, 512, ide_transfer_stop);
2283 } else {
2284 ide_abort_command(s);
2285 }
2286 ide_set_irq(s);
2287 break;
2288 case WIN_SPECIFY:
2289 case WIN_RECAL:
2290 s->status = READY_STAT;
2291 ide_set_irq(s);
2292 break;
2293 case WIN_SETMULT:
2294 if (s->nsector > MAX_MULT_SECTORS ||
2295 s->nsector == 0 ||
2296 (s->nsector & (s->nsector - 1)) != 0) {
2297 ide_abort_command(s);
2298 } else {
2299 s->mult_sectors = s->nsector;
2300 s->status = READY_STAT;
2301 }
2302 ide_set_irq(s);
2303 break;
2304 case WIN_READ:
2305 case WIN_READ_ONCE:
c9159e53 2306 s->req_nb_sectors = 1;
fc01f7e7
FB		 2307 ide_sector_read(s);
2308 break;
2309 case WIN_WRITE:
2310 case WIN_WRITE_ONCE:
2311 s->status = SEEK_STAT;
c9159e53 2312 s->req_nb_sectors = 1;
fc01f7e7
FB		 2313 ide_transfer_start(s, 512, ide_sector_write);
2314 break;
c9159e53
FB		 2315 case WIN_MULTREAD:
2316 if (!s->mult_sectors)
2317 goto abort_cmd;
2318 s->req_nb_sectors = s->mult_sectors;
2319 ide_sector_read(s);
2320 break;
2321 case WIN_MULTWRITE:
2322 if (!s->mult_sectors)
2323 goto abort_cmd;
2324 s->status = SEEK_STAT;
2325 s->req_nb_sectors = s->mult_sectors;
2326 n = s->nsector;
2327 if (n > s->req_nb_sectors)
2328 n = s->req_nb_sectors;
2329 ide_transfer_start(s, 512 * n, ide_sector_write);
2330 break;
cd4c3e88
FB		 2331 case WIN_READ_NATIVE_MAX:
2332 ide_set_sector(s, s->nb_sectors - 1);
2333 s->status = READY_STAT;
2334 ide_set_irq(s);
2335 break;
fc01f7e7 2336 default:
c9159e53 2337 abort_cmd:
fc01f7e7
FB		 2338 ide_abort_command(s);
2339 ide_set_irq(s);
2340 break;
2341 }
2342 }
2343}
2344
2345uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr)
2346{
2347 IDEState *s = ide_state[0].cur_drive;
2348 int ret;
2349
2350 addr &= 7;
2351 switch(addr) {
2352 case 0:
2353 ret = 0xff;
2354 break;
2355 case 1:
2356 ret = s->error;
2357 break;
2358 case 2:
c9159e53 2359 ret = s->nsector & 0xff;
fc01f7e7
FB		 2360 break;
2361 case 3:
2362 ret = s->sector;
2363 break;
2364 case 4:
2365 ret = s->lcyl;
2366 break;
2367 case 5:
2368 ret = s->hcyl;
2369 break;
2370 case 6:
2371 ret = s->select;
2372 break;
2373 default:
2374 case 7:
2375 ret = s->status;
2376 pic_set_irq(s->irq, 0);
2377 break;
2378 }
2379#ifdef DEBUG_IDE
2380 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2381#endif
2382 return ret;
2383}
2384
2385uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
2386{
2387 IDEState *s = ide_state[0].cur_drive;
2388 int ret;
2389 ret = s->status;
2390#ifdef DEBUG_IDE
330d0414 2391 printf("ide: read status val=%02x\n", ret);
fc01f7e7
FB		 2392#endif
2393 return ret;
2394}
2395
2396void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
2397{
330d0414
FB		 2398 IDEState *s;
2399 int i;
2400
2401#ifdef DEBUG_IDE
2402 printf("ide: write control val=%02x\n", val);
2403#endif
fc01f7e7 2404 /* common for both drives */
330d0414
FB		 2405 if (!(ide_state[0].cmd & IDE_CMD_RESET) &&
2406 (val & IDE_CMD_RESET)) {
2407 /* reset low to high */
2408 for(i = 0;i < 2; i++) {
2409 s = &ide_state[i];
2410 s->status = BUSY_STAT | SEEK_STAT;
2411 s->error = 0x01;
2412 }
2413 } else if ((ide_state[0].cmd & IDE_CMD_RESET) &&
2414 !(val & IDE_CMD_RESET)) {
2415 /* high to low */
2416 for(i = 0;i < 2; i++) {
2417 s = &ide_state[i];
2418 s->status = READY_STAT;
2419 /* set hard disk drive ID */
2420 s->select &= 0xf0; /* clear head */
2421 s->nsector = 1;
2422 s->sector = 1;
2423 if (s->nb_sectors == 0) {
2424 /* no disk present */
2425 s->lcyl = 0x12;
2426 s->hcyl = 0x34;
2427 } else {
2428 s->lcyl = 0;
2429 s->hcyl = 0;
2430 }
2431 }
2432 }
2433
2434 ide_state[0].cmd = val;
fc01f7e7
FB		 2435}
2436
2437void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
2438{
2439 IDEState *s = ide_state[0].cur_drive;
2440 uint8_t *p;
2441
2442 p = s->data_ptr;
2443 *(uint16_t *)p = tswap16(val);
2444 p += 2;
2445 s->data_ptr = p;
2446 if (p >= s->data_end)
2447 s->end_transfer_func(s);
2448}
2449
2450uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
2451{
2452 IDEState *s = ide_state[0].cur_drive;
2453 uint8_t *p;
2454 int ret;
2455
2456 p = s->data_ptr;
2457 ret = tswap16(*(uint16_t *)p);
2458 p += 2;
2459 s->data_ptr = p;
2460 if (p >= s->data_end)
2461 s->end_transfer_func(s);
2462 return ret;
2463}
2464
2465void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
2466{
2467 IDEState *s = ide_state[0].cur_drive;
2468 uint8_t *p;
2469
2470 p = s->data_ptr;
2471 *(uint32_t *)p = tswap32(val);
2472 p += 4;
2473 s->data_ptr = p;
2474 if (p >= s->data_end)
2475 s->end_transfer_func(s);
2476}
2477
2478uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
2479{
2480 IDEState *s = ide_state[0].cur_drive;
2481 uint8_t *p;
2482 int ret;
2483
2484 p = s->data_ptr;
2485 ret = tswap32(*(uint32_t *)p);
2486 p += 4;
2487 s->data_ptr = p;
2488 if (p >= s->data_end)
2489 s->end_transfer_func(s);
2490 return ret;
2491}
2492
2493void ide_reset(IDEState *s)
2494{
2495 s->mult_sectors = MAX_MULT_SECTORS;
2496 s->status = READY_STAT;
2497 s->cur_drive = s;
2498 s->select = 0xa0;
2499}
2500
2501void ide_init(void)
2502{
2503 IDEState *s;
2504 int i, cylinders;
2505 int64_t nb_sectors;
2506
2507 for(i = 0; i < MAX_DISKS; i++) {
2508 s = &ide_state[i];
2509 s->bs = bs_table[i];
2510 if (s->bs) {
2511 bdrv_get_geometry(s->bs, &nb_sectors);
330d0414
FB		 2512 if (s->cylinders == 0) {
2513 /* if no geometry, use a LBA compatible one */
2514 cylinders = nb_sectors / (16 * 63);
2515 if (cylinders > 16383)
2516 cylinders = 16383;
2517 else if (cylinders < 2)
2518 cylinders = 2;
2519 s->cylinders = cylinders;
2520 s->heads = 16;
2521 s->sectors = 63;
2522 }
fc01f7e7
FB		 2523 s->nb_sectors = nb_sectors;
2524 }
2525 s->irq = 14;
2526 ide_reset(s);
2527 }
2528 register_ioport_write(0x1f0, 8, ide_ioport_write, 1);
2529 register_ioport_read(0x1f0, 8, ide_ioport_read, 1);
2530 register_ioport_read(0x3f6, 1, ide_status_read, 1);
2531 register_ioport_write(0x3f6, 1, ide_cmd_write, 1);
2532
2533 /* data ports */
2534 register_ioport_write(0x1f0, 2, ide_data_writew, 2);
2535 register_ioport_read(0x1f0, 2, ide_data_readw, 2);
2536 register_ioport_write(0x1f0, 4, ide_data_writel, 4);
2537 register_ioport_read(0x1f0, 4, ide_data_readl, 4);
2538}
2539
cd4c3e88 2540/***********************************************************/
330d0414
FB		 2541/* keyboard emulation */
2542
2543/* Keyboard Controller Commands */
2544#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
2545#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
2546#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
2547#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
2548#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2549#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2550#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2551#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2552#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2553#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2554#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2555#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2556#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2557#define KBD_CCMD_WRITE_OBUF 0xD2
2558#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2559 initiated by the auxiliary device */
2560#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
2561#define KBD_CCMD_ENABLE_A20 0xDD
2562#define KBD_CCMD_DISABLE_A20 0xDF
2563#define KBD_CCMD_RESET 0xFE
2564
2565/* Keyboard Commands */
2566#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2567#define KBD_CMD_ECHO 0xEE
2568#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2569#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2570#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2571#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2572#define KBD_CMD_RESET 0xFF /* Reset */
2573
2574/* Keyboard Replies */
2575#define KBD_REPLY_POR 0xAA /* Power on reset */
2576#define KBD_REPLY_ACK 0xFA /* Command ACK */
2577#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2578
2579/* Status Register Bits */
2580#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2581#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2582#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2583#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2584#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2585#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2586#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2587#define KBD_STAT_PERR 0x80 /* Parity error */
2588
2589/* Controller Mode Register Bits */
2590#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2591#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2592#define KBD_MODE_SYS 0x04 /* The system flag (?) */
2593#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2594#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2595#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2596#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2597#define KBD_MODE_RFU 0x80
2598
2599/* Mouse Commands */
2600#define AUX_SET_RES 0xE8 /* Set resolution */
2601#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2602#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
2603#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2604#define AUX_SET_STREAM 0xEA /* Set stream mode */
2605#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2606#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2607#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
2608#define AUX_RESET 0xFF /* Reset aux device */
2609#define AUX_ACK 0xFA /* Command byte ACK. */
2610
2611#define KBD_QUEUE_SIZE 64
2612
2613typedef struct {
2614 uint8_t data[KBD_QUEUE_SIZE];
2615 int rptr, wptr, count;
2616} KBDQueue;
2617
2618enum KBDWriteState {
2619 KBD_STATE_CMD = 0,
2620 KBD_STATE_LED,
2621};
cd4c3e88 2622
330d0414
FB		 2623typedef struct KBDState {
2624 KBDQueue queues[2];
2625 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
2626 uint8_t status;
2627 uint8_t mode;
2628 int kbd_write_cmd;
2629 int scan_enabled;
2630} KBDState;
2631
2632KBDState kbd_state;
cd4c3e88 2633int reset_requested;
330d0414
FB		 2634int a20_enabled;
2635
2636static void kbd_update_irq(KBDState *s)
2637{
2638 int level;
2639
2640 level = ((s->status & KBD_STAT_OBF) && (s->mode & KBD_MODE_KBD_INT));
2641 pic_set_irq(1, level);
2642
2643 level = ((s->status & KBD_STAT_MOUSE_OBF) && (s->mode & KBD_MODE_MOUSE_INT));
2644 pic_set_irq(12, level);
2645}
2646
2647static void kbd_queue(KBDState *s, int b, int aux)
2648{
2649 KBDQueue *q = &kbd_state.queues[aux];
2650
2651 if (q->count >= KBD_QUEUE_SIZE)
2652 return;
2653 q->data[q->wptr] = b;
2654 if (++q->wptr == KBD_QUEUE_SIZE)
2655 q->wptr = 0;
2656 q->count++;
2657 s->status |= KBD_STAT_OBF;
2658 if (aux)
2659 s->status |= KBD_STAT_MOUSE_OBF;
2660 kbd_update_irq(s);
2661}
cd4c3e88
FB		 2662
2663uint32_t kbd_read_status(CPUX86State *env, uint32_t addr)
2664{
330d0414
FB		 2665 KBDState *s = &kbd_state;
2666 int val;
2667 val = s->status;
2668#if defined(DEBUG_KBD) && 0
2669 printf("kbd: read status=0x%02x\n", val);
2670#endif
2671 return val;
cd4c3e88
FB		 2672}
2673
2674void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
2675{
330d0414
FB		 2676 KBDState *s = &kbd_state;
2677
2678#ifdef DEBUG_KBD
2679 printf("kbd: write cmd=0x%02x\n", val);
2680#endif
cd4c3e88 2681 switch(val) {
330d0414
FB		 2682 case KBD_CCMD_READ_MODE:
2683 kbd_queue(s, s->mode, 0);
2684 break;
2685 case KBD_CCMD_WRITE_MODE:
2686 case KBD_CCMD_WRITE_OBUF:
2687 case KBD_CCMD_WRITE_AUX_OBUF:
2688 case KBD_CCMD_WRITE_MOUSE:
2689 case KBD_CCMD_WRITE_OUTPORT:
2690 s->write_cmd = val;
2691 break;
2692 case KBD_CCMD_MOUSE_DISABLE:
2693 s->mode |= KBD_MODE_DISABLE_MOUSE;
2694 break;
2695 case KBD_CCMD_MOUSE_ENABLE:
2696 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2697 break;
2698 case KBD_CCMD_TEST_MOUSE:
2699 kbd_queue(s, 0x00, 0);
2700 break;
2701 case KBD_CCMD_SELF_TEST:
2702 s->status |= KBD_STAT_SELFTEST;
2703 kbd_queue(s, 0x55, 0);
2704 break;
2705 case KBD_CCMD_KBD_TEST:
2706 kbd_queue(s, 0x00, 0);
2707 break;
2708 case KBD_CCMD_KBD_DISABLE:
2709 s->mode |= KBD_MODE_DISABLE_KBD;
2710 break;
2711 case KBD_CCMD_KBD_ENABLE:
2712 s->mode &= ~KBD_MODE_DISABLE_KBD;
2713 break;
2714 case KBD_CCMD_READ_INPORT:
2715 kbd_queue(s, 0x00, 0);
2716 break;
2717 case KBD_CCMD_READ_OUTPORT:
2718 /* XXX: check that */
2719 val = 0x01 | (a20_enabled << 1);
2720 if (s->status & KBD_STAT_OBF)
2721 val |= 0x10;
2722 if (s->status & KBD_STAT_MOUSE_OBF)
2723 val |= 0x20;
2724 kbd_queue(s, val, 0);
2725 break;
2726 case KBD_CCMD_ENABLE_A20:
2727 a20_enabled = 1;
2728 break;
2729 case KBD_CCMD_DISABLE_A20:
2730 a20_enabled = 0;
2731 break;
2732 case KBD_CCMD_RESET:
cd4c3e88
FB		 2733 reset_requested = 1;
2734 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2735 break;
330d0414
FB		 2736 default:
2737 fprintf(stderr, "vl: unsupported keyboard cmd=0x%02x\n", val);
2738 break;
2739 }
2740}
2741
2742uint32_t kbd_read_data(CPUX86State *env, uint32_t addr)
2743{
2744 KBDState *s = &kbd_state;
2745 KBDQueue *q;
2746 int val;
2747
2748 q = &s->queues[1]; /* first check AUX data */
2749 if (q->count == 0)
2750 q = &s->queues[0]; /* then check KBD data */
2751 if (q->count == 0) {
2752 /* XXX: return something else ? */
2753 val = 0;
2754 } else {
2755 val = q->data[q->rptr];
2756 if (++q->rptr == KBD_QUEUE_SIZE)
2757 q->rptr = 0;
2758 q->count--;
2759 }
2760 if (s->queues[1].count == 0) {
2761 s->status &= ~KBD_STAT_MOUSE_OBF;
2762 if (s->queues[0].count == 0)
2763 s->status &= ~KBD_STAT_OBF;
2764 kbd_update_irq(s);
2765 }
2766
2767#ifdef DEBUG_KBD
2768 printf("kbd: read data=0x%02x\n", val);
2769#endif
2770 return val;
2771}
2772
2773static void kbd_reset_keyboard(KBDState *s)
2774{
2775 s->scan_enabled = 1;
2776}
2777
2778static void kbd_write_keyboard(KBDState *s, int val)
2779{
2780 switch(s->kbd_write_cmd) {
2781 default:
2782 case -1:
2783 switch(val) {
2784 case 0x00:
2785 kbd_queue(s, KBD_REPLY_ACK, 0);
2786 break;
2787 case 0x05:
2788 kbd_queue(s, KBD_REPLY_RESEND, 0);
2789 break;
2790 case KBD_CMD_ECHO:
2791 kbd_queue(s, KBD_CMD_ECHO, 0);
2792 break;
2793 case KBD_CMD_ENABLE:
2794 s->scan_enabled = 1;
2795 kbd_queue(s, KBD_REPLY_ACK, 0);
2796 break;
2797 case KBD_CMD_SET_LEDS:
2798 case KBD_CMD_SET_RATE:
2799 s->kbd_write_cmd = val;
2800 break;
2801 case KBD_CMD_RESET_DISABLE:
2802 kbd_reset_keyboard(s);
2803 s->scan_enabled = 0;
2804 kbd_queue(s, KBD_REPLY_ACK, 0);
2805 break;
2806 case KBD_CMD_RESET_ENABLE:
2807 kbd_reset_keyboard(s);
2808 s->scan_enabled = 1;
2809 kbd_queue(s, KBD_REPLY_ACK, 0);
2810 break;
2811 case KBD_CMD_RESET:
2812 kbd_reset_keyboard(s);
2813 kbd_queue(s, KBD_REPLY_ACK, 0);
2814 kbd_queue(s, KBD_REPLY_POR, 0);
2815 break;
2816 default:
2817 kbd_queue(s, KBD_REPLY_ACK, 0);
2818 break;
2819 }
2820 break;
2821 case KBD_CMD_SET_LEDS:
2822 kbd_queue(s, KBD_REPLY_ACK, 0);
2823 break;
2824 case KBD_CMD_SET_RATE:
2825 kbd_queue(s, KBD_REPLY_ACK, 0);
2826 break;
2827 }
2828 s->kbd_write_cmd = -1;
2829}
2830
2831void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
2832{
2833 KBDState *s = &kbd_state;
2834
2835#ifdef DEBUG_KBD
2836 printf("kbd: write data=0x%02x\n", val);
2837#endif
2838
2839 switch(s->write_cmd) {
2840 case 0:
2841 kbd_write_keyboard(s, val);
2842 break;
2843 case KBD_CCMD_WRITE_MODE:
2844 s->mode = val;
2845 kbd_update_irq(s);
2846 break;
2847 case KBD_CCMD_WRITE_OBUF:
2848 kbd_queue(s, val, 0);
2849 break;
2850 case KBD_CCMD_WRITE_AUX_OBUF:
2851 kbd_queue(s, val, 1);
2852 break;
2853 case KBD_CCMD_WRITE_OUTPORT:
2854 a20_enabled = (val >> 1) & 1;
2855 if (!(val & 1)) {
2856 reset_requested = 1;
2857 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2858 }
2859 break;
cd4c3e88
FB		 2860 default:
2861 break;
2862 }
330d0414
FB		 2863 s->write_cmd = 0;
2864}
2865
2866void kbd_reset(KBDState *s)
2867{
2868 KBDQueue *q;
2869 int i;
2870
2871 s->kbd_write_cmd = -1;
2872 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
2873 s->status = KBD_MODE_SYS | KBD_MODE_NO_KEYLOCK;
2874 for(i = 0; i < 2; i++) {
2875 q = &s->queues[i];
2876 q->rptr = 0;
2877 q->wptr = 0;
2878 q->count = 0;
2879 }
cd4c3e88
FB		 2880}
2881
2882void kbd_init(void)
2883{
330d0414
FB		 2884 kbd_reset(&kbd_state);
2885 register_ioport_read(0x60, 1, kbd_read_data, 1);
2886 register_ioport_write(0x60, 1, kbd_write_data, 1);
cd4c3e88
FB		 2887 register_ioport_read(0x64, 1, kbd_read_status, 1);
2888 register_ioport_write(0x64, 1, kbd_write_command, 1);
2889}
2890
330d0414
FB		 2891/***********************************************************/
2892/* Bochs BIOS debug ports */
2893
2894void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
2895{
2896 switch(addr) {
2897 /* Bochs BIOS messages */
2898 case 0x400:
2899 case 0x401:
2900 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
2901 exit(1);
2902 case 0x402:
2903 case 0x403:
2904#ifdef DEBUG_BIOS
2905 fprintf(stderr, "%c", val);
2906#endif
2907 break;
2908
2909 /* LGPL'ed VGA BIOS messages */
2910 case 0x501:
2911 case 0x502:
2912 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
2913 exit(1);
2914 case 0x500:
2915 case 0x503:
2916#ifdef DEBUG_BIOS
2917 fprintf(stderr, "%c", val);
2918#endif
2919 break;
2920 }
2921}
2922
2923void bochs_bios_init(void)
2924{
2925 register_ioport_write(0x400, 1, bochs_bios_write, 2);
2926 register_ioport_write(0x401, 1, bochs_bios_write, 2);
2927 register_ioport_write(0x402, 1, bochs_bios_write, 1);
2928 register_ioport_write(0x403, 1, bochs_bios_write, 1);
2929
2930 register_ioport_write(0x501, 1, bochs_bios_write, 2);
2931 register_ioport_write(0x502, 1, bochs_bios_write, 2);
2932 register_ioport_write(0x500, 1, bochs_bios_write, 1);
2933 register_ioport_write(0x503, 1, bochs_bios_write, 1);
2934}
2935
f1510b2c 2936/***********************************************************/
0824d6fc
FB		 2937/* cpu signal handler */
2938static void host_segv_handler(int host_signum, siginfo_t *info,
2939 void *puc)
2940{
2941 if (cpu_signal_handler(host_signum, info, puc))
2942 return;
2943 term_exit();
2944 abort();
2945}
2946
2947static int timer_irq_pending;
87858c89 2948static int timer_irq_count;
0824d6fc
FB		 2949
2950static void host_alarm_handler(int host_signum, siginfo_t *info,
2951 void *puc)
2952{
87858c89
FB		 2953 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2954 some drift between cpu_get_ticks() and the interrupt time. So
2955 we queue some interrupts to avoid missing some */
2956 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
2957 if (timer_irq_count) {
2958 if (timer_irq_count > 2)
2959 timer_irq_count = 2;
2960 timer_irq_count--;
2961 /* just exit from the cpu to have a chance to handle timers */
c9159e53 2962 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
87858c89
FB		 2963 timer_irq_pending = 1;
2964 }
0824d6fc
FB		 2965}
2966
33e3963e
FB		 2967unsigned long mmap_addr = PHYS_RAM_BASE;
2968
2969void *get_mmap_addr(unsigned long size)
2970{
2971 unsigned long addr;
2972 addr = mmap_addr;
2973 mmap_addr += ((size + 4095) & ~4095) + 4096;
2974 return (void *)addr;
2975}
2976
b4608c04
FB		 2977/* main execution loop */
2978
2979CPUState *cpu_gdbstub_get_env(void *opaque)
2980{
2981 return global_env;
2982}
2983
4c3a88a2 2984int main_loop(void *opaque)
b4608c04
FB		 2985{
2986 struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
2987 int ret, n, timeout;
2988 uint8_t ch;
2989 CPUState *env = global_env;
2990
2991 for(;;) {
2992
2993 ret = cpu_x86_exec(env);
cd4c3e88
FB		 2994 if (reset_requested)
2995 break;
4c3a88a2
FB		 2996 if (ret == EXCP_DEBUG)
2997 return EXCP_DEBUG;
b4608c04
FB		 2998 /* if hlt instruction, we wait until the next IRQ */
2999 if (ret == EXCP_HLT)
3000 timeout = 10;
3001 else
3002 timeout = 0;
3003 /* poll any events */
3004 serial_ufd = NULL;
3005 pf = ufds;
3006 if (!(serial_ports[0].lsr & UART_LSR_DR)) {
3007 serial_ufd = pf;
3008 pf->fd = 0;
3009 pf->events = POLLIN;
3010 pf++;
3011 }
3012 net_ufd = NULL;
3013 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
3014 net_ufd = pf;
3015 pf->fd = net_fd;
3016 pf->events = POLLIN;
3017 pf++;
3018 }
3019 gdb_ufd = NULL;
3020 if (gdbstub_fd > 0) {
3021 gdb_ufd = pf;
3022 pf->fd = gdbstub_fd;
3023 pf->events = POLLIN;
3024 pf++;
3025 }
3026
3027 ret = poll(ufds, pf - ufds, timeout);
3028 if (ret > 0) {
3029 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
3030 n = read(0, &ch, 1);
3031 if (n == 1) {
3032 serial_received_byte(&serial_ports[0], ch);
3033 }
3034 }
3035 if (net_ufd && (net_ufd->revents & POLLIN)) {
3036 uint8_t buf[MAX_ETH_FRAME_SIZE];
3037
3038 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
3039 if (n > 0) {
3040 if (n < 60) {
3041 memset(buf + n, 0, 60 - n);
3042 n = 60;
3043 }
3044 ne2000_receive(&ne2000_state, buf, n);
3045 }
3046 }
3047 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
3048 uint8_t buf[1];
3049 /* stop emulation if requested by gdb */
3050 n = read(gdbstub_fd, buf, 1);
3051 if (n == 1)
3052 break;
3053 }
3054 }
3055
3056 /* timer IRQ */
3057 if (timer_irq_pending) {
3058 pic_set_irq(0, 1);
3059 pic_set_irq(0, 0);
3060 timer_irq_pending = 0;
3061 }
b4608c04 3062 }
4c3a88a2 3063 return EXCP_INTERRUPT;
b4608c04
FB		 3064}
3065
0824d6fc
FB		 3066void help(void)
3067{
3068 printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
330d0414 3069 "usage: vl [options] [bzImage [kernel parameters...]]\n"
0824d6fc
FB		 3070 "\n"
3071 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
3072 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
fc01f7e7
FB		 3073 "\n"
3074 "General options:\n"
3075 "-initrd file use 'file' as initial ram disk\n"
3076 "-hda file use 'file' as hard disk 0 image\n"
3077 "-hdb file use 'file' as hard disk 1 image\n"
33e3963e 3078 "-snapshot write to temporary files instead of disk image files\n"
fc01f7e7
FB		 3079 "-m megs set virtual RAM size to megs MB\n"
3080 "-n script set network init script [default=%s]\n"
3081 "\n"
330d0414 3082 "Debug/Expert options:\n"
fc01f7e7
FB		 3083 "-s wait gdb connection to port %d\n"
3084 "-p port change gdb connection port\n"
3085 "-d output log in /tmp/vl.log\n"
330d0414
FB		 3086 "-hdachs c,h,s force hard disk 0 geometry for non LBA disk images\n"
3087 "-L path set the directory for the BIOS and VGA BIOS\n"
0824d6fc 3088 "\n"
f1510b2c 3089 "During emulation, use C-a h to get terminal commands:\n",
b4608c04 3090 DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT);
0824d6fc
FB		 3091 term_print_help();
3092 exit(1);
3093}
3094
fc01f7e7
FB		 3095struct option long_options[] = {
3096 { "initrd", 1, NULL, 0, },
3097 { "hda", 1, NULL, 0, },
3098 { "hdb", 1, NULL, 0, },
33e3963e 3099 { "snapshot", 0, NULL, 0, },
330d0414 3100 { "hdachs", 1, NULL, 0, },
fc01f7e7
FB		 3101 { NULL, 0, NULL, 0 },
3102};
3103
0824d6fc
FB		 3104int main(int argc, char **argv)
3105{
fc01f7e7 3106 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
330d0414 3107 int snapshot, linux_boot;
0824d6fc
FB		 3108 struct linux_params *params;
3109 struct sigaction act;
3110 struct itimerval itv;
3111 CPUX86State *env;
fc01f7e7
FB		 3112 const char *tmpdir, *initrd_filename;
3113 const char *hd_filename[MAX_DISKS];
87858c89 3114
0824d6fc
FB		 3115 /* we never want that malloc() uses mmap() */
3116 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
fc01f7e7
FB		 3117 initrd_filename = NULL;
3118 for(i = 0; i < MAX_DISKS; i++)
3119 hd_filename[i] = NULL;
0824d6fc 3120 phys_ram_size = 32 * 1024 * 1024;
f1510b2c 3121 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
b4608c04
FB		 3122 use_gdbstub = 0;
3123 gdbstub_port = DEFAULT_GDBSTUB_PORT;
33e3963e 3124 snapshot = 0;
330d0414 3125 linux_boot = 0;
0824d6fc 3126 for(;;) {
330d0414 3127 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
0824d6fc
FB		 3128 if (c == -1)
3129 break;
3130 switch(c) {
fc01f7e7
FB		 3131 case 0:
3132 switch(long_index) {
3133 case 0:
3134 initrd_filename = optarg;
3135 break;
3136 case 1:
3137 hd_filename[0] = optarg;
3138 break;
3139 case 2:
3140 hd_filename[1] = optarg;
3141 break;
33e3963e
FB		 3142 case 3:
3143 snapshot = 1;
3144 break;
330d0414
FB		 3145 case 4:
3146 {
3147 int cyls, heads, secs;
3148 const char *p;
3149 p = optarg;
3150 cyls = strtol(p, (char **)&p, 0);
3151 if (*p != ',')
3152 goto chs_fail;
3153 p++;
3154 heads = strtol(p, (char **)&p, 0);
3155 if (*p != ',')
3156 goto chs_fail;
3157 p++;
3158 secs = strtol(p, (char **)&p, 0);
3159 if (*p != '\0')
3160 goto chs_fail;
3161 ide_state[0].cylinders = cyls;
3162 ide_state[0].heads = heads;
3163 ide_state[0].sectors = secs;
3164 chs_fail: ;
3165 }
3166 break;
fc01f7e7
FB		 3167 }
3168 break;
0824d6fc
FB		 3169 case 'h':
3170 help();
3171 break;
3172 case 'm':
3173 phys_ram_size = atoi(optarg) * 1024 * 1024;
3174 if (phys_ram_size <= 0)
3175 help();
7916e224
FB		 3176 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
3177 fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
3178 PHYS_RAM_MAX_SIZE / (1024 * 1024));
3179 exit(1);
3180 }
0824d6fc
FB		 3181 break;
3182 case 'd':
3183 loglevel = 1;
3184 break;
f1510b2c
FB		 3185 case 'n':
3186 pstrcpy(network_script, sizeof(network_script), optarg);
3187 break;
b4608c04
FB		 3188 case 's':
3189 use_gdbstub = 1;
3190 break;
3191 case 'p':
3192 gdbstub_port = atoi(optarg);
3193 break;
330d0414
FB		 3194 case 'L':
3195 interp_prefix = optarg;
3196 break;
0824d6fc
FB		 3197 }
3198 }
330d0414
FB		 3199
3200 linux_boot = (optind < argc);
3201
3202 if (!linux_boot && hd_filename[0] == '\0')
0824d6fc
FB		 3203 help();
3204
3205 /* init debug */
b118d61e 3206 setvbuf(stdout, NULL, _IOLBF, 0);
0824d6fc
FB		 3207 if (loglevel) {
3208 logfile = fopen(DEBUG_LOGFILE, "w");
3209 if (!logfile) {
3210 perror(DEBUG_LOGFILE);
3211 _exit(1);
3212 }
3213 setvbuf(logfile, NULL, _IOLBF, 0);
3214 }
3215
f1510b2c
FB		 3216 /* init network tun interface */
3217 net_init();
3218
0824d6fc 3219 /* init the memory */
87858c89
FB		 3220 tmpdir = getenv("VLTMPDIR");
3221 if (!tmpdir)
3222 tmpdir = "/tmp";
3223 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
0824d6fc 3224 if (mkstemp(phys_ram_file) < 0) {
87858c89
FB		 3225 fprintf(stderr, "Could not create temporary memory file '%s'\n",
3226 phys_ram_file);
0824d6fc
FB		 3227 exit(1);
3228 }
3229 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
3230 if (phys_ram_fd < 0) {
87858c89
FB		 3231 fprintf(stderr, "Could not open temporary memory file '%s'\n",
3232 phys_ram_file);
0824d6fc
FB		 3233 exit(1);
3234 }
3235 ftruncate(phys_ram_fd, phys_ram_size);
3236 unlink(phys_ram_file);
33e3963e 3237 phys_ram_base = mmap(get_mmap_addr(phys_ram_size), phys_ram_size,
0824d6fc
FB		 3238 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
3239 phys_ram_fd, 0);
3240 if (phys_ram_base == MAP_FAILED) {
3241 fprintf(stderr, "Could not map physical memory\n");
3242 exit(1);
3243 }
3244
33e3963e
FB		 3245 /* open the virtual block devices */
3246 for(i = 0; i < MAX_DISKS; i++) {
3247 if (hd_filename[i]) {
3248 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3249 if (!bs_table[i]) {
3250 fprintf(stderr, "vl: could not open hard disk image '%s\n",
3251 hd_filename[i]);
3252 exit(1);
3253 }
3254 }
3255 }
3256
330d0414
FB		 3257 /* init CPU state */
3258 env = cpu_init();
3259 global_env = env;
3260 cpu_single_env = env;
3261
3262 init_ioports();
0824d6fc 3263
330d0414
FB		 3264 if (linux_boot) {
3265 /* now we can load the kernel */
3266 ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
3267 if (ret < 0) {
3268 fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
fc01f7e7
FB		 3269 exit(1);
3270 }
330d0414
FB		 3271
3272 /* load initrd */
3273 initrd_size = 0;
3274 if (initrd_filename) {
3275 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3276 if (initrd_size < 0) {
3277 fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
3278 initrd_filename);
3279 exit(1);
3280 }
3281 }
3282
3283 /* init kernel params */
3284 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3285 memset(params, 0, sizeof(struct linux_params));
3286 params->mount_root_rdonly = 0;
3287 params->cl_magic = 0xA33F;
3288 params->cl_offset = params->commandline - (uint8_t *)params;
3289 params->alt_mem_k = (phys_ram_size / 1024) - 1024;
3290 for(i = optind + 1; i < argc; i++) {
3291 if (i != optind + 1)
3292 pstrcat(params->commandline, sizeof(params->commandline), " ");
3293 pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
3294 }
3295 params->loader_type = 0x01;
3296 if (initrd_size > 0) {
3297 params->initrd_start = INITRD_LOAD_ADDR;
3298 params->initrd_size = initrd_size;
3299 }
3300 params->orig_video_lines = 25;
3301 params->orig_video_cols = 80;
3302
3303 /* setup basic memory access */
3304 env->cr[0] = 0x00000033;
3305 cpu_x86_init_mmu(env);
3306
3307 memset(params->idt_table, 0, sizeof(params->idt_table));
3308
3309 params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
3310 params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
3311
3312 env->idt.base = (void *)params->idt_table;
3313 env->idt.limit = sizeof(params->idt_table) - 1;
3314 env->gdt.base = (void *)params->gdt_table;
3315 env->gdt.limit = sizeof(params->gdt_table) - 1;
3316
3317 cpu_x86_load_seg(env, R_CS, KERNEL_CS);
3318 cpu_x86_load_seg(env, R_DS, KERNEL_DS);
3319 cpu_x86_load_seg(env, R_ES, KERNEL_DS);
3320 cpu_x86_load_seg(env, R_SS, KERNEL_DS);
3321 cpu_x86_load_seg(env, R_FS, KERNEL_DS);
3322 cpu_x86_load_seg(env, R_GS, KERNEL_DS);
3323
3324 env->eip = KERNEL_LOAD_ADDR;
3325 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3326 env->eflags = 0x2;
0824d6fc 3327
330d0414
FB		 3328 } else {
3329 char buf[1024];
3330
3331 /* RAW PC boot */
3332
3333 /* BIOS load */
3334 snprintf(buf, sizeof(buf), "%s/%s", interp_prefix, BIOS_FILENAME);
3335 ret = load_image(buf, phys_ram_base + 0x000f0000);
3336 if (ret != 0x10000) {
3337 fprintf(stderr, "vl: could not load PC bios '%s'\n", BIOS_FILENAME);
3338 exit(1);
3339 }
3340
3341 /* VGA BIOS load */
3342 snprintf(buf, sizeof(buf), "%s/%s", interp_prefix, VGABIOS_FILENAME);
3343 ret = load_image(buf, phys_ram_base + 0x000c0000);
3344
3345 /* setup basic memory access */
3346 env->cr[0] = 0x60000010;
3347 cpu_x86_init_mmu(env);
3348
3349 env->idt.limit = 0xffff;
3350 env->gdt.limit = 0xffff;
3351 env->ldt.limit = 0xffff;
3352
3353 /* not correct (CS base=0xffff0000) */
3354 cpu_x86_load_seg(env, R_CS, 0xf000);
3355 cpu_x86_load_seg(env, R_DS, 0);
3356 cpu_x86_load_seg(env, R_ES, 0);
3357 cpu_x86_load_seg(env, R_SS, 0);
3358 cpu_x86_load_seg(env, R_FS, 0);
3359 cpu_x86_load_seg(env, R_GS, 0);
3360
3361 env->eip = 0xfff0;
3362 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3363
3364 env->eflags = 0x2;
3365
3366 bochs_bios_init();
0824d6fc 3367 }
0824d6fc
FB		 3368
3369 /* init basic PC hardware */
fc01f7e7 3370 register_ioport_write(0x80, 1, ioport80_write, 1);
0824d6fc 3371
fc01f7e7 3372 register_ioport_write(0x3d4, 2, vga_ioport_write, 1);
0824d6fc
FB		 3373
3374 cmos_init();
3375 pic_init();
3376 pit_init();
3377 serial_init();
f1510b2c 3378 ne2000_init();
fc01f7e7 3379 ide_init();
cd4c3e88 3380 kbd_init();
0824d6fc
FB		 3381
3382 /* setup cpu signal handlers for MMU / self modifying code handling */
3383 sigfillset(&act.sa_mask);
3384 act.sa_flags = SA_SIGINFO;
3385 act.sa_sigaction = host_segv_handler;
3386 sigaction(SIGSEGV, &act, NULL);
3387 sigaction(SIGBUS, &act, NULL);
3388
3389 act.sa_sigaction = host_alarm_handler;
3390 sigaction(SIGALRM, &act, NULL);
3391
0824d6fc 3392 itv.it_interval.tv_sec = 0;
87858c89 3393 itv.it_interval.tv_usec = 1000;
0824d6fc
FB		 3394 itv.it_value.tv_sec = 0;
3395 itv.it_value.tv_usec = 10 * 1000;
3396 setitimer(ITIMER_REAL, &itv, NULL);
87858c89
FB		 3397 /* we probe the tick duration of the kernel to inform the user if
3398 the emulated kernel requested a too high timer frequency */
3399 getitimer(ITIMER_REAL, &itv);
3400 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3401 1000000;
b4608c04
FB		 3402
3403 if (use_gdbstub) {
3404 cpu_gdbstub(NULL, main_loop, gdbstub_port);
3405 } else {
3406 main_loop(NULL);
0824d6fc 3407 }
0824d6fc
FB		 3408 return 0;
3409}
Qemu copy for testing