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1 | #/** @file\r | |
2 | # ARM processor package.\r | |
3 | #\r | |
4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r | |
5 | # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r | |
6 | #\r | |
7 | # This program and the accompanying materials\r | |
8 | # are licensed and made available under the terms and conditions of the BSD License\r | |
9 | # which accompanies this distribution. The full text of the license may be found at\r | |
10 | # http://opensource.org/licenses/bsd-license.php\r | |
11 | #\r | |
12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | #\r | |
15 | #**/\r | |
16 | \r | |
17 | [Defines]\r | |
18 | DEC_SPECIFICATION = 0x00010005\r | |
19 | PACKAGE_NAME = ArmPkg\r | |
20 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r | |
21 | PACKAGE_VERSION = 0.1\r | |
22 | \r | |
23 | ################################################################################\r | |
24 | #\r | |
25 | # Include Section - list of Include Paths that are provided by this package.\r | |
26 | # Comments are used for Keywords and Module Types.\r | |
27 | #\r | |
28 | # Supported Module Types:\r | |
29 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
30 | #\r | |
31 | ################################################################################\r | |
32 | [Includes.common]\r | |
33 | Include # Root include for the package\r | |
34 | \r | |
35 | [LibraryClasses.common]\r | |
36 | ArmLib|Include/Library/ArmLib.h\r | |
37 | SemihostLib|Include/Library/Semihosting.h\r | |
38 | UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r | |
39 | DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r | |
40 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r | |
41 | \r | |
42 | [Guids.common]\r | |
43 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r | |
44 | \r | |
45 | ## ARM MPCore table\r | |
46 | # Include/Guid/ArmMpCoreInfo.h\r | |
47 | gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r | |
48 | \r | |
49 | [Ppis]\r | |
50 | ## Include/Ppi/ArmMpCoreInfo.h\r | |
51 | gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r | |
52 | \r | |
53 | [Protocols.common]\r | |
54 | gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r | |
55 | \r | |
56 | [PcdsFeatureFlag.common]\r | |
57 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r | |
58 | \r | |
59 | # On ARM Architecture with the Security Extension, the address for the\r | |
60 | # Vector Table can be mapped anywhere in the memory map. It means we can\r | |
61 | # point the Exception Vector Table to its location in CpuDxe.\r | |
62 | # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)\r | |
63 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r | |
64 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r | |
65 | # it has been configured by the CPU DXE\r | |
66 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r | |
67 | \r | |
68 | # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware\r | |
69 | gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033\r | |
70 | \r | |
71 | [PcdsFixedAtBuild.common]\r | |
72 | gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r | |
73 | \r | |
74 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r | |
75 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r | |
76 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r | |
77 | \r | |
78 | gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r | |
79 | gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r | |
80 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r | |
81 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r | |
82 | \r | |
83 | #\r | |
84 | # ARM PL390 General Interrupt Controller\r | |
85 | #\r | |
86 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r | |
87 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r | |
88 | gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r | |
89 | \r | |
90 | #\r | |
91 | # ARM Secure Firmware PCDs\r | |
92 | #\r | |
93 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015\r | |
94 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r | |
95 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F\r | |
96 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r | |
97 | \r | |
98 | #\r | |
99 | # ARM Normal (or Non Secure) Firmware PCDs\r | |
100 | #\r | |
101 | gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B\r | |
102 | gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r | |
103 | gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D\r | |
104 | gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r | |
105 | \r | |
106 | #\r | |
107 | # ARM Hypervisor Firmware PCDs\r | |
108 | # \r | |
109 | gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r | |
110 | gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r | |
111 | gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r | |
112 | gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r | |
113 | \r | |
114 | #\r | |
115 | # ARM Security Extension\r | |
116 | #\r | |
117 | \r | |
118 | # Secure Configuration Register\r | |
119 | # - BIT0 : NS - Non Secure bit \r | |
120 | # - BIT1 : IRQ Handler\r | |
121 | # - BIT2 : FIQ Handler\r | |
122 | # - BIT3 : EA - External Abort\r | |
123 | # - BIT4 : FW - F bit writable\r | |
124 | # - BIT5 : AW - A bit writable\r | |
125 | # - BIT6 : nET - Not Early Termination\r | |
126 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
127 | # - BIT8 : HCE - Hyp Call enable\r | |
128 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
129 | # 0x31 = NS | EA | FW\r | |
130 | gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r | |
131 | \r | |
132 | # Non Secure Access Control Register\r | |
133 | # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r | |
134 | # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 \r | |
135 | # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r | |
136 | # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r | |
137 | # 0xC00 = cp10 | cp11\r | |
138 | gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r | |
139 | \r | |
140 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r | |
141 | # Some platforms can get DRAM extensions, these additional regions will be declared\r | |
142 | # to UEFI by ArmPLatformPlib \r | |
143 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r | |
144 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r | |
145 | \r | |
146 | # Use ClusterId + CoreId to identify the PrimaryCore\r | |
147 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r | |
148 | # The Primary Core is ClusterId[0] & CoreId[0] \r | |
149 | gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r | |
150 | \r | |
151 | #\r | |
152 | # ARM L2x0 PCDs\r | |
153 | #\r | |
154 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r | |
155 | \r | |
156 | # \r | |
157 | # BdsLib\r | |
158 | #\r | |
159 | gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E\r | |
160 | # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r | |
161 | gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r | |
162 | \r | |
163 | #\r | |
164 | # ARM Architectural Timer\r | |
165 | #\r | |
166 | gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r | |
167 | # ARM Architectural Timer Interrupt(GIC PPI) number\r | |
168 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 \r | |
169 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r | |
170 | \r | |
171 | [PcdsFixedAtBuild.ARM]\r | |
172 | # By default we do not do a transition to non-secure mode\r | |
173 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r | |
174 | \r | |
175 | # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r | |
176 | gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r | |
177 | \r | |
178 | # If the fixed FDT address is not available, then it should be loaded below the kernel.\r | |
179 | # The recommendation from the Linux kernel is to have the FDT below 16KB.\r | |
180 | # (see the kernel doc: Documentation/arm/Booting)\r | |
181 | gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r | |
182 | # The FDT blob must be loaded at a 64bit aligned address.\r | |
183 | gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r | |
184 | \r | |
185 | [PcdsFixedAtBuild.AARCH64]\r | |
186 | # By default we do transition to EL2 non-secure mode with Stack for EL2.\r | |
187 | # Mode Description Bits\r | |
188 | # NS EL2 SP2 all interupts disabled = 0x3c9\r | |
189 | # NS EL1 SP1 all interupts disabled = 0x3c5\r | |
190 | # Other modes include using SP0 or switching to Aarch32, but these are\r | |
191 | # not currently supported.\r | |
192 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r |