| | 1 | #/** @file\r |
| | 2 | # ARM processor package.\r |
| | 3 | #\r |
| | 4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r |
| | 5 | # Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.\r |
| | 6 | # Copyright (c) 2021, Ampere Computing LLC. All rights reserved.\r |
| | 7 | #\r |
| | 8 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 9 | #\r |
| | 10 | #**/\r |
| | 11 | \r |
| | 12 | [Defines]\r |
| | 13 | DEC_SPECIFICATION = 0x00010005\r |
| | 14 | PACKAGE_NAME = ArmPkg\r |
| | 15 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r |
| | 16 | PACKAGE_VERSION = 0.1\r |
| | 17 | \r |
| | 18 | ################################################################################\r |
| | 19 | #\r |
| | 20 | # Include Section - list of Include Paths that are provided by this package.\r |
| | 21 | # Comments are used for Keywords and Module Types.\r |
| | 22 | #\r |
| | 23 | # Supported Module Types:\r |
| | 24 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r |
| | 25 | #\r |
| | 26 | ################################################################################\r |
| | 27 | [Includes.common]\r |
| | 28 | Include # Root include for the package\r |
| | 29 | \r |
| | 30 | [LibraryClasses.common]\r |
| | 31 | ## @libraryclass Convert Arm instructions to a human readable format.\r |
| | 32 | #\r |
| | 33 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r |
| | 34 | \r |
| | 35 | ## @libraryclass Provides an interface to Arm generic counters.\r |
| | 36 | #\r |
| | 37 | ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h\r |
| | 38 | \r |
| | 39 | ## @libraryclass Provides an interface to initialize a\r |
| | 40 | # Generic Interrupt Controller (GIC).\r |
| | 41 | #\r |
| | 42 | ArmGicArchLib|Include/Library/ArmGicArchLib.h\r |
| | 43 | \r |
| | 44 | ## @libraryclass Provides a Generic Interrupt Controller (GIC)\r |
| | 45 | # configuration interface.\r |
| | 46 | #\r |
| | 47 | ArmGicLib|Include/Library/ArmGicLib.h\r |
| | 48 | \r |
| | 49 | ## @libraryclass Provides a HyperVisor Call (HVC) interface.\r |
| | 50 | #\r |
| | 51 | ArmHvcLib|Include/Library/ArmHvcLib.h\r |
| | 52 | \r |
| | 53 | ## @libraryclass Provides an interface to Arm registers.\r |
| | 54 | #\r |
| | 55 | ArmLib|Include/Library/ArmLib.h\r |
| | 56 | \r |
| | 57 | ## @libraryclass Provides a Mmu interface.\r |
| | 58 | #\r |
| | 59 | ArmMmuLib|Include/Library/ArmMmuLib.h\r |
| | 60 | \r |
| | 61 | ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface\r |
| | 62 | # for the System Control and Management Interface (SCMI).\r |
| | 63 | #\r |
| | 64 | ArmMtlLib|Include/Library/ArmMtlLib.h\r |
| | 65 | \r |
| | 66 | ## @libraryclass Provides a System Monitor Call (SMC) interface.\r |
| | 67 | #\r |
| | 68 | ArmSmcLib|Include/Library/ArmSmcLib.h\r |
| | 69 | \r |
| | 70 | ## @libraryclass Provides a SuperVisor Call (SVC) interface.\r |
| | 71 | #\r |
| | 72 | ArmSvcLib|Include/Library/ArmSvcLib.h\r |
| | 73 | \r |
| | 74 | ## @libraryclass Provides a Monitor Call interface that will use the\r |
| | 75 | # default conduit (HVC or SMC).\r |
| | 76 | #\r |
| | 77 | ArmMonitorLib|Include/Library/ArmMonitorLib.h\r |
| | 78 | \r |
| | 79 | ## @libraryclass Provides a default exception handler.\r |
| | 80 | #\r |
| | 81 | DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r |
| | 82 | \r |
| | 83 | ## @libraryclass Provides an interface to query miscellaneous OEM\r |
| | 84 | # information.\r |
| | 85 | #\r |
| | 86 | OemMiscLib|Include/Library/OemMiscLib.h\r |
| | 87 | \r |
| | 88 | ## @libraryclass Provides an OpTee interface.\r |
| | 89 | #\r |
| | 90 | OpteeLib|Include/Library/OpteeLib.h\r |
| | 91 | \r |
| | 92 | ## @libraryclass Provides a semihosting interface.\r |
| | 93 | #\r |
| | 94 | SemihostLib|Include/Library/SemihostLib.h\r |
| | 95 | \r |
| | 96 | ## @libraryclass Provides an interface for a StandaloneMm Mmu.\r |
| | 97 | #\r |
| | 98 | StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r |
| | 99 | \r |
| | 100 | [Guids.common]\r |
| | 101 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r |
| | 102 | \r |
| | 103 | ## ARM MPCore table\r |
| | 104 | # Include/Guid/ArmMpCoreInfo.h\r |
| | 105 | gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r |
| | 106 | \r |
| | 107 | gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }\r |
| | 108 | \r |
| | 109 | [Protocols.common]\r |
| | 110 | ## Arm System Control and Management Interface(SCMI) Base protocol\r |
| | 111 | ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r |
| | 112 | gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r |
| | 113 | \r |
| | 114 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r |
| | 115 | ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r |
| | 116 | gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r |
| | 117 | gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r |
| | 118 | \r |
| | 119 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r |
| | 120 | ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r |
| | 121 | gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r |
| | 122 | \r |
| | 123 | [Ppis]\r |
| | 124 | ## Include/Ppi/ArmMpCoreInfo.h\r |
| | 125 | gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r |
| | 126 | \r |
| | 127 | [PcdsFeatureFlag.common]\r |
| | 128 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r |
| | 129 | \r |
| | 130 | # On ARM Architecture with the Security Extension, the address for the\r |
| | 131 | # Vector Table can be mapped anywhere in the memory map. It means we can\r |
| | 132 | # point the Exception Vector Table to its location in CpuDxe.\r |
| | 133 | # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r |
| | 134 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r |
| | 135 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r |
| | 136 | # it has been configured by the CPU DXE\r |
| | 137 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r |
| | 138 | \r |
| | 139 | # Define if the GICv3 controller should use the GICv2 legacy\r |
| | 140 | gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r |
| | 141 | \r |
| | 142 | ## Define the conduit to use for monitor calls.\r |
| | 143 | # Default PcdMonitorConduitHvc = FALSE, conduit = SMC\r |
| | 144 | # If PcdMonitorConduitHvc = TRUE, conduit = HVC\r |
| | 145 | gArmTokenSpaceGuid.PcdMonitorConduitHvc|FALSE|BOOLEAN|0x00000047\r |
| | 146 | \r |
| | 147 | [PcdsFeatureFlag.ARM]\r |
| | 148 | # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r |
| | 149 | # TRUE may be appropriate to fix performance problems if you don't care about\r |
| | 150 | # hardware coherency (i.e., no virtualization or cache coherent DMA)\r |
| | 151 | gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r |
| | 152 | \r |
| | 153 | [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]\r |
| | 154 | ## Used to select method for requesting services from S-EL1.<BR><BR>\r |
| | 155 | # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>\r |
| | 156 | # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>\r |
| | 157 | # @Prompt Enable FF-A support.\r |
| | 158 | gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B\r |
| | 159 | \r |
| | 160 | [PcdsFixedAtBuild.common]\r |
| | 161 | gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r |
| | 162 | \r |
| | 163 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r |
| | 164 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r |
| | 165 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r |
| | 166 | \r |
| | 167 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r |
| | 168 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r |
| | 169 | \r |
| | 170 | #\r |
| | 171 | # ARM Secure Firmware PCDs\r |
| | 172 | #\r |
| | 173 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r |
| | 174 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r |
| | 175 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r |
| | 176 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r |
| | 177 | \r |
| | 178 | #\r |
| | 179 | # ARM Hypervisor Firmware PCDs\r |
| | 180 | #\r |
| | 181 | gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r |
| | 182 | gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r |
| | 183 | gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r |
| | 184 | gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r |
| | 185 | \r |
| | 186 | # Use ClusterId + CoreId to identify the PrimaryCore\r |
| | 187 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r |
| | 188 | # The Primary Core is ClusterId[0] & CoreId[0]\r |
| | 189 | gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r |
| | 190 | \r |
| | 191 | #\r |
| | 192 | # SMBIOS PCDs\r |
| | 193 | #\r |
| | 194 | gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r |
| | 195 | gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r |
| | 196 | gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r |
| | 197 | gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r |
| | 198 | gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r |
| | 199 | gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r |
| | 200 | gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r |
| | 201 | gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r |
| | 202 | gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r |
| | 203 | gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r |
| | 204 | \r |
| | 205 | #\r |
| | 206 | # ARM L2x0 PCDs\r |
| | 207 | #\r |
| | 208 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r |
| | 209 | \r |
| | 210 | #\r |
| | 211 | # ARM Normal (or Non Secure) Firmware PCDs\r |
| | 212 | #\r |
| | 213 | gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r |
| | 214 | gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r |
| | 215 | \r |
| | 216 | #\r |
| | 217 | # Value to add to a host address to obtain a device address, using\r |
| | 218 | # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r |
| | 219 | # means we can rely on truncation on overflow to specify negative\r |
| | 220 | # offsets.\r |
| | 221 | #\r |
| | 222 | gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r |
| | 223 | \r |
| | 224 | [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r |
| | 225 | gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r |
| | 226 | gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r |
| | 227 | \r |
| | 228 | [PcdsFixedAtBuild.ARM]\r |
| | 229 | #\r |
| | 230 | # ARM Security Extension\r |
| | 231 | #\r |
| | 232 | \r |
| | 233 | # Secure Configuration Register\r |
| | 234 | # - BIT0 : NS - Non Secure bit\r |
| | 235 | # - BIT1 : IRQ Handler\r |
| | 236 | # - BIT2 : FIQ Handler\r |
| | 237 | # - BIT3 : EA - External Abort\r |
| | 238 | # - BIT4 : FW - F bit writable\r |
| | 239 | # - BIT5 : AW - A bit writable\r |
| | 240 | # - BIT6 : nET - Not Early Termination\r |
| | 241 | # - BIT7 : SCD - Secure Monitor Call Disable\r |
| | 242 | # - BIT8 : HCE - Hyp Call enable\r |
| | 243 | # - BIT9 : SIF - Secure Instruction Fetch\r |
| | 244 | # 0x31 = NS | EA | FW\r |
| | 245 | gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r |
| | 246 | \r |
| | 247 | # By default we do not do a transition to non-secure mode\r |
| | 248 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r |
| | 249 | \r |
| | 250 | # Non Secure Access Control Register\r |
| | 251 | # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r |
| | 252 | # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r |
| | 253 | # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r |
| | 254 | # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r |
| | 255 | # 0xC00 = cp10 | cp11\r |
| | 256 | gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r |
| | 257 | \r |
| | 258 | [PcdsFixedAtBuild.AARCH64]\r |
| | 259 | #\r |
| | 260 | # AArch64 Security Extension\r |
| | 261 | #\r |
| | 262 | \r |
| | 263 | # Secure Configuration Register\r |
| | 264 | # - BIT0 : NS - Non Secure bit\r |
| | 265 | # - BIT1 : IRQ Handler\r |
| | 266 | # - BIT2 : FIQ Handler\r |
| | 267 | # - BIT3 : EA - External Abort\r |
| | 268 | # - BIT4 : FW - F bit writable\r |
| | 269 | # - BIT5 : AW - A bit writable\r |
| | 270 | # - BIT6 : nET - Not Early Termination\r |
| | 271 | # - BIT7 : SCD - Secure Monitor Call Disable\r |
| | 272 | # - BIT8 : HCE - Hyp Call enable\r |
| | 273 | # - BIT9 : SIF - Secure Instruction Fetch\r |
| | 274 | # - BIT10: RW - Register width control for lower exception levels\r |
| | 275 | # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r |
| | 276 | # - BIT12: TWI - Trap WFI\r |
| | 277 | # - BIT13: TWE - Trap WFE\r |
| | 278 | # 0x501 = NS | HCE | RW\r |
| | 279 | gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r |
| | 280 | \r |
| | 281 | # By default we do transition to EL2 non-secure mode with Stack for EL2.\r |
| | 282 | # Mode Description Bits\r |
| | 283 | # NS EL2 SP2 all interrupts disabled = 0x3c9\r |
| | 284 | # NS EL1 SP1 all interrupts disabled = 0x3c5\r |
| | 285 | # Other modes include using SP0 or switching to Aarch32, but these are\r |
| | 286 | # not currently supported.\r |
| | 287 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r |
| | 288 | \r |
| | 289 | \r |
| | 290 | #\r |
| | 291 | # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r |
| | 292 | # redefined when using UEFI in a context of virtual machine.\r |
| | 293 | #\r |
| | 294 | [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r |
| | 295 | \r |
| | 296 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r |
| | 297 | # Some platforms can get DRAM extensions, these additional regions may be\r |
| | 298 | # declared to UEFI using separate resource descriptor HOBs\r |
| | 299 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r |
| | 300 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r |
| | 301 | \r |
| | 302 | gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r |
| | 303 | gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r |
| | 304 | \r |
| | 305 | gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r |
| | 306 | gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r |
| | 307 | \r |
| | 308 | [PcdsFixedAtBuild.common, PcdsDynamic.common]\r |
| | 309 | #\r |
| | 310 | # ARM Architectural Timer\r |
| | 311 | #\r |
| | 312 | gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r |
| | 313 | \r |
| | 314 | # ARM Architectural Timer Interrupt(GIC PPI) numbers\r |
| | 315 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r |
| | 316 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r |
| | 317 | gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r |
| | 318 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r |
| | 319 | \r |
| | 320 | #\r |
| | 321 | # ARM Generic Watchdog\r |
| | 322 | #\r |
| | 323 | \r |
| | 324 | gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r |
| | 325 | gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r |
| | 326 | gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r |
| | 327 | \r |
| | 328 | #\r |
| | 329 | # ARM Generic Interrupt Controller\r |
| | 330 | #\r |
| | 331 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r |
| | 332 | # Base address for the GIC Redistributor region that contains the boot CPU\r |
| | 333 | gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r |
| | 334 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r |
| | 335 | gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r |
| | 336 | \r |
| | 337 | #\r |
| | 338 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r |
| | 339 | # Note that "IO" is just another MMIO range that simulates IO space; there\r |
| | 340 | # are no special instructions to access it.\r |
| | 341 | #\r |
| | 342 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r |
| | 343 | # specific to their containing address spaces. In order to get the physical\r |
| | 344 | # address for the CPU, for a given access, the respective translation value\r |
| | 345 | # has to be added.\r |
| | 346 | #\r |
| | 347 | # The translations always have to be initialized like this, using UINT64:\r |
| | 348 | #\r |
| | 349 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r |
| | 350 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r |
| | 351 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r |
| | 352 | #\r |
| | 353 | # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r |
| | 354 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r |
| | 355 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r |
| | 356 | #\r |
| | 357 | # because (a) the target address space (ie. the cpu-physical space) is\r |
| | 358 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r |
| | 359 | # arithmetic.\r |
| | 360 | #\r |
| | 361 | # Accordingly, the translation itself needs to be implemented as:\r |
| | 362 | #\r |
| | 363 | # UINT64 UntranslatedIoAddress; // input parameter\r |
| | 364 | # UINT32 UntranslatedMmio32Address; // input parameter\r |
| | 365 | # UINT64 UntranslatedMmio64Address; // input parameter\r |
| | 366 | #\r |
| | 367 | # UINT64 TranslatedIoAddress; // output parameter\r |
| | 368 | # UINT64 TranslatedMmio32Address; // output parameter\r |
| | 369 | # UINT64 TranslatedMmio64Address; // output parameter\r |
| | 370 | #\r |
| | 371 | # TranslatedIoAddress = UntranslatedIoAddress +\r |
| | 372 | # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;\r |
| | 373 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r |
| | 374 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;\r |
| | 375 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r |
| | 376 | # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;\r |
| | 377 | #\r |
| | 378 | # The modular arithmetic performed in UINT64 ensures that the translation\r |
| | 379 | # works correctly regardless of the relation between IoCpuBase and\r |
| | 380 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r |
| | 381 | # PcdPciMmio64Base.\r |
| | 382 | #\r |
| | 383 | gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r |
| | 384 | gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r |
| | 385 | gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r |
| | 386 | gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r |
| | 387 | gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r |
| | 388 | gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r |
| | 389 | \r |
| | 390 | #\r |
| | 391 | # Inclusive range of allowed PCI buses.\r |
| | 392 | #\r |
| | 393 | gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r |
| | 394 | gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r |
| | 395 | \r |
| | 396 | [PcdsDynamicEx]\r |
| | 397 | #\r |
| | 398 | # This dynamic PCD hold the GUID of a firmware FFS which contains\r |
| | 399 | # the LinuxBoot payload.\r |
| | 400 | #\r |
| | 401 | gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C\r |
projects / mirror_edk2.git / blame_incremental