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1 | /** @file\r | |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __ARM_V7_H__\r | |
16 | #define __ARM_V7_H__\r | |
17 | \r | |
18 | #include <Chipset/ArmV7Mmu.h>\r | |
19 | \r | |
20 | // Domain Access Control Register\r | |
21 | #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r | |
22 | #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r | |
23 | #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r | |
24 | #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r | |
25 | #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r | |
26 | \r | |
27 | // Cortex A9 feature bit definitions\r | |
28 | #define A9_FEATURE_PARITY (1<<9)\r | |
29 | #define A9_FEATURE_AOW (1<<8)\r | |
30 | #define A9_FEATURE_EXCL (1<<7)\r | |
31 | #define A9_FEATURE_SMP (1<<6)\r | |
32 | #define A9_FEATURE_FOZ (1<<3)\r | |
33 | #define A9_FEATURE_DPREF (1<<2)\r | |
34 | #define A9_FEATURE_HINT (1<<1)\r | |
35 | #define A9_FEATURE_FWD (1<<0)\r | |
36 | \r | |
37 | // SCU register offsets & masks\r | |
38 | #define SCU_CONTROL_OFFSET 0x0\r | |
39 | #define SCU_CONFIG_OFFSET 0x4\r | |
40 | #define SCU_INVALL_OFFSET 0xC\r | |
41 | #define SCU_FILT_START_OFFSET 0x40\r | |
42 | #define SCU_FILT_END_OFFSET 0x44\r | |
43 | #define SCU_SACR_OFFSET 0x50\r | |
44 | #define SCU_SSACR_OFFSET 0x54\r | |
45 | \r | |
46 | #define SMP_GIC_CPUIF_BASE 0x100\r | |
47 | #define SMP_GIC_DIST_BASE 0x1000\r | |
48 | \r | |
49 | // CPACR - Coprocessor Access Control Register definitions\r | |
50 | #define CPACR_CP_DENIED(cp) 0x00\r | |
51 | #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
52 | #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
53 | #define CPACR_ASEDIS (1 << 31)\r | |
54 | #define CPACR_D32DIS (1 << 30)\r | |
55 | #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r | |
56 | \r | |
57 | // NSACR - Non-Secure Access Control Register definitions\r | |
58 | #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r | |
59 | #define NSACR_NSD32DIS (1 << 14)\r | |
60 | #define NSACR_NSASEDIS (1 << 15)\r | |
61 | #define NSACR_PLE (1 << 16)\r | |
62 | #define NSACR_TL (1 << 17)\r | |
63 | #define NSACR_NS_SMP (1 << 18)\r | |
64 | #define NSACR_RFR (1 << 19)\r | |
65 | \r | |
66 | // SCR - Secure Configuration Register definitions\r | |
67 | #define SCR_NS (1 << 0)\r | |
68 | #define SCR_IRQ (1 << 1)\r | |
69 | #define SCR_FIQ (1 << 2)\r | |
70 | #define SCR_EA (1 << 3)\r | |
71 | #define SCR_FW (1 << 4)\r | |
72 | #define SCR_AW (1 << 5)\r | |
73 | \r | |
74 | VOID\r | |
75 | EFIAPI\r | |
76 | ArmEnableSWPInstruction (\r | |
77 | VOID\r | |
78 | );\r | |
79 | \r | |
80 | VOID\r | |
81 | EFIAPI\r | |
82 | ArmWriteNsacr (\r | |
83 | IN UINT32 SetWayFormat\r | |
84 | );\r | |
85 | \r | |
86 | VOID\r | |
87 | EFIAPI\r | |
88 | ArmWriteScr (\r | |
89 | IN UINT32 SetWayFormat\r | |
90 | );\r | |
91 | \r | |
92 | VOID\r | |
93 | EFIAPI\r | |
94 | ArmWriteVMBar (\r | |
95 | IN UINT32 SetWayFormat\r | |
96 | );\r | |
97 | \r | |
98 | VOID\r | |
99 | EFIAPI\r | |
100 | ArmWriteVBar (\r | |
101 | IN UINT32 SetWayFormat\r | |
102 | );\r | |
103 | \r | |
104 | UINT32\r | |
105 | EFIAPI\r | |
106 | ArmReadVBar (\r | |
107 | VOID\r | |
108 | );\r | |
109 | \r | |
110 | VOID\r | |
111 | EFIAPI\r | |
112 | ArmWriteCPACR (\r | |
113 | IN UINT32 SetWayFormat\r | |
114 | );\r | |
115 | \r | |
116 | VOID\r | |
117 | EFIAPI\r | |
118 | ArmEnableVFP (\r | |
119 | VOID\r | |
120 | );\r | |
121 | \r | |
122 | VOID\r | |
123 | EFIAPI\r | |
124 | ArmCallWFI (\r | |
125 | VOID\r | |
126 | );\r | |
127 | \r | |
128 | VOID\r | |
129 | EFIAPI\r | |
130 | ArmInvalidScu (\r | |
131 | VOID\r | |
132 | );\r | |
133 | \r | |
134 | UINTN\r | |
135 | EFIAPI\r | |
136 | ArmGetScuBaseAddress (\r | |
137 | VOID\r | |
138 | );\r | |
139 | \r | |
140 | UINT32\r | |
141 | EFIAPI\r | |
142 | ArmIsScuEnable (\r | |
143 | VOID\r | |
144 | );\r | |
145 | \r | |
146 | VOID\r | |
147 | EFIAPI\r | |
148 | ArmWriteAuxCr (\r | |
149 | IN UINT32 Bit\r | |
150 | );\r | |
151 | \r | |
152 | UINT32\r | |
153 | EFIAPI\r | |
154 | ArmReadAuxCr (\r | |
155 | VOID\r | |
156 | );\r | |
157 | \r | |
158 | VOID\r | |
159 | EFIAPI\r | |
160 | ArmSetAuxCrBit (\r | |
161 | IN UINT32 Bits\r | |
162 | );\r | |
163 | \r | |
164 | VOID\r | |
165 | EFIAPI\r | |
166 | ArmSetupSmpNonSecure (\r | |
167 | IN UINTN CoreId\r | |
168 | );\r | |
169 | \r | |
170 | UINTN \r | |
171 | EFIAPI\r | |
172 | ArmReadCbar (\r | |
173 | VOID\r | |
174 | );\r | |
175 | \r | |
176 | VOID\r | |
177 | EFIAPI\r | |
178 | ArmInvalidateInstructionAndDataTlb (\r | |
179 | VOID\r | |
180 | );\r | |
181 | \r | |
182 | \r | |
183 | UINTN\r | |
184 | EFIAPI\r | |
185 | ArmReadMpidr (\r | |
186 | VOID\r | |
187 | );\r | |
188 | \r | |
189 | UINTN\r | |
190 | EFIAPI\r | |
191 | ArmReadTpidrurw (\r | |
192 | VOID\r | |
193 | );\r | |
194 | \r | |
195 | VOID\r | |
196 | EFIAPI\r | |
197 | ArmWriteTpidrurw (\r | |
198 | UINTN Value\r | |
199 | );\r | |
200 | \r | |
201 | #endif // __ARM_V7_H__\r |