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1 | /** @file | |
2 | ||
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #ifndef __ARM_LIB__ | |
16 | #define __ARM_LIB__ | |
17 | ||
18 | #ifdef ARM_CPU_ARMv6 | |
19 | #include <Chipset/ARM1176JZ-S.h> | |
20 | #else | |
21 | #include <Chipset/ArmV7.h> | |
22 | #endif | |
23 | ||
24 | typedef enum { | |
25 | ARM_CACHE_TYPE_WRITE_BACK, | |
26 | ARM_CACHE_TYPE_UNKNOWN | |
27 | } ARM_CACHE_TYPE; | |
28 | ||
29 | typedef enum { | |
30 | ARM_CACHE_ARCHITECTURE_UNIFIED, | |
31 | ARM_CACHE_ARCHITECTURE_SEPARATE, | |
32 | ARM_CACHE_ARCHITECTURE_UNKNOWN | |
33 | } ARM_CACHE_ARCHITECTURE; | |
34 | ||
35 | typedef struct { | |
36 | ARM_CACHE_TYPE Type; | |
37 | ARM_CACHE_ARCHITECTURE Architecture; | |
38 | BOOLEAN DataCachePresent; | |
39 | UINTN DataCacheSize; | |
40 | UINTN DataCacheAssociativity; | |
41 | UINTN DataCacheLineLength; | |
42 | BOOLEAN InstructionCachePresent; | |
43 | UINTN InstructionCacheSize; | |
44 | UINTN InstructionCacheAssociativity; | |
45 | UINTN InstructionCacheLineLength; | |
46 | } ARM_CACHE_INFO; | |
47 | ||
48 | typedef enum { | |
49 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, | |
50 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED, | |
51 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, | |
52 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK, | |
53 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, | |
54 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH, | |
55 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE, | |
56 | ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE | |
57 | } ARM_MEMORY_REGION_ATTRIBUTES; | |
58 | ||
59 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1) | |
60 | ||
61 | typedef struct { | |
62 | UINT32 PhysicalBase; | |
63 | UINT32 VirtualBase; | |
64 | UINT32 Length; | |
65 | ARM_MEMORY_REGION_ATTRIBUTES Attributes; | |
66 | } ARM_MEMORY_REGION_DESCRIPTOR; | |
67 | ||
68 | typedef VOID (*CACHE_OPERATION)(VOID); | |
69 | typedef VOID (*LINE_OPERATION)(UINTN); | |
70 | ||
71 | typedef enum { | |
72 | ARM_PROCESSOR_MODE_USER = 0x10, | |
73 | ARM_PROCESSOR_MODE_FIQ = 0x11, | |
74 | ARM_PROCESSOR_MODE_IRQ = 0x12, | |
75 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13, | |
76 | ARM_PROCESSOR_MODE_ABORT = 0x17, | |
77 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B, | |
78 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F, | |
79 | ARM_PROCESSOR_MODE_MASK = 0x1F | |
80 | } ARM_PROCESSOR_MODE; | |
81 | ||
82 | #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) | |
83 | #define GET_CORE_ID(MpId) ((MpId) & 0x3) | |
84 | #define GET_CLUSTER_ID(MpId) (((MpId) >> 8) & 0x3C) | |
85 | // Get the position of the core for the Stack Offset (4 Core per Cluster) | |
86 | // Position = (ClusterId * 4) + CoreId | |
87 | #define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3)) | |
88 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0x3) | |
89 | ||
90 | ARM_CACHE_TYPE | |
91 | EFIAPI | |
92 | ArmCacheType ( | |
93 | VOID | |
94 | ); | |
95 | ||
96 | ARM_CACHE_ARCHITECTURE | |
97 | EFIAPI | |
98 | ArmCacheArchitecture ( | |
99 | VOID | |
100 | ); | |
101 | ||
102 | VOID | |
103 | EFIAPI | |
104 | ArmCacheInformation ( | |
105 | OUT ARM_CACHE_INFO *CacheInfo | |
106 | ); | |
107 | ||
108 | BOOLEAN | |
109 | EFIAPI | |
110 | ArmDataCachePresent ( | |
111 | VOID | |
112 | ); | |
113 | ||
114 | UINTN | |
115 | EFIAPI | |
116 | ArmDataCacheSize ( | |
117 | VOID | |
118 | ); | |
119 | ||
120 | UINTN | |
121 | EFIAPI | |
122 | ArmDataCacheAssociativity ( | |
123 | VOID | |
124 | ); | |
125 | ||
126 | UINTN | |
127 | EFIAPI | |
128 | ArmDataCacheLineLength ( | |
129 | VOID | |
130 | ); | |
131 | ||
132 | BOOLEAN | |
133 | EFIAPI | |
134 | ArmInstructionCachePresent ( | |
135 | VOID | |
136 | ); | |
137 | ||
138 | UINTN | |
139 | EFIAPI | |
140 | ArmInstructionCacheSize ( | |
141 | VOID | |
142 | ); | |
143 | ||
144 | UINTN | |
145 | EFIAPI | |
146 | ArmInstructionCacheAssociativity ( | |
147 | VOID | |
148 | ); | |
149 | ||
150 | UINTN | |
151 | EFIAPI | |
152 | ArmInstructionCacheLineLength ( | |
153 | VOID | |
154 | ); | |
155 | ||
156 | UINT32 | |
157 | EFIAPI | |
158 | Cp15IdCode ( | |
159 | VOID | |
160 | ); | |
161 | ||
162 | UINT32 | |
163 | EFIAPI | |
164 | Cp15CacheInfo ( | |
165 | VOID | |
166 | ); | |
167 | ||
168 | BOOLEAN | |
169 | EFIAPI | |
170 | ArmIsMpCore ( | |
171 | VOID | |
172 | ); | |
173 | ||
174 | VOID | |
175 | EFIAPI | |
176 | ArmInvalidateDataCache ( | |
177 | VOID | |
178 | ); | |
179 | ||
180 | ||
181 | VOID | |
182 | EFIAPI | |
183 | ArmCleanInvalidateDataCache ( | |
184 | VOID | |
185 | ); | |
186 | ||
187 | VOID | |
188 | EFIAPI | |
189 | ArmCleanDataCache ( | |
190 | VOID | |
191 | ); | |
192 | ||
193 | VOID | |
194 | EFIAPI | |
195 | ArmCleanDataCacheToPoU ( | |
196 | VOID | |
197 | ); | |
198 | ||
199 | VOID | |
200 | EFIAPI | |
201 | ArmInvalidateInstructionCache ( | |
202 | VOID | |
203 | ); | |
204 | ||
205 | VOID | |
206 | EFIAPI | |
207 | ArmInvalidateDataCacheEntryByMVA ( | |
208 | IN UINTN Address | |
209 | ); | |
210 | ||
211 | VOID | |
212 | EFIAPI | |
213 | ArmCleanDataCacheEntryByMVA ( | |
214 | IN UINTN Address | |
215 | ); | |
216 | ||
217 | VOID | |
218 | EFIAPI | |
219 | ArmCleanInvalidateDataCacheEntryByMVA ( | |
220 | IN UINTN Address | |
221 | ); | |
222 | ||
223 | VOID | |
224 | EFIAPI | |
225 | ArmEnableDataCache ( | |
226 | VOID | |
227 | ); | |
228 | ||
229 | VOID | |
230 | EFIAPI | |
231 | ArmDisableDataCache ( | |
232 | VOID | |
233 | ); | |
234 | ||
235 | VOID | |
236 | EFIAPI | |
237 | ArmEnableInstructionCache ( | |
238 | VOID | |
239 | ); | |
240 | ||
241 | VOID | |
242 | EFIAPI | |
243 | ArmDisableInstructionCache ( | |
244 | VOID | |
245 | ); | |
246 | ||
247 | VOID | |
248 | EFIAPI | |
249 | ArmEnableMmu ( | |
250 | VOID | |
251 | ); | |
252 | ||
253 | VOID | |
254 | EFIAPI | |
255 | ArmDisableMmu ( | |
256 | VOID | |
257 | ); | |
258 | ||
259 | VOID | |
260 | EFIAPI | |
261 | ArmDisableCachesAndMmu ( | |
262 | VOID | |
263 | ); | |
264 | ||
265 | VOID | |
266 | EFIAPI | |
267 | ArmInvalidateInstructionAndDataTlb ( | |
268 | VOID | |
269 | ); | |
270 | ||
271 | VOID | |
272 | EFIAPI | |
273 | ArmEnableInterrupts ( | |
274 | VOID | |
275 | ); | |
276 | ||
277 | UINTN | |
278 | EFIAPI | |
279 | ArmDisableInterrupts ( | |
280 | VOID | |
281 | ); | |
282 | ||
283 | BOOLEAN | |
284 | EFIAPI | |
285 | ArmGetInterruptState ( | |
286 | VOID | |
287 | ); | |
288 | ||
289 | VOID | |
290 | EFIAPI | |
291 | ArmEnableFiq ( | |
292 | VOID | |
293 | ); | |
294 | ||
295 | UINTN | |
296 | EFIAPI | |
297 | ArmDisableFiq ( | |
298 | VOID | |
299 | ); | |
300 | ||
301 | BOOLEAN | |
302 | EFIAPI | |
303 | ArmGetFiqState ( | |
304 | VOID | |
305 | ); | |
306 | ||
307 | VOID | |
308 | EFIAPI | |
309 | ArmInvalidateTlb ( | |
310 | VOID | |
311 | ); | |
312 | ||
313 | VOID | |
314 | EFIAPI | |
315 | ArmUpdateTranslationTableEntry ( | |
316 | IN VOID *TranslationTableEntry, | |
317 | IN VOID *Mva | |
318 | ); | |
319 | ||
320 | VOID | |
321 | EFIAPI | |
322 | ArmSetDomainAccessControl ( | |
323 | IN UINT32 Domain | |
324 | ); | |
325 | ||
326 | VOID | |
327 | EFIAPI | |
328 | ArmSetTTBR0 ( | |
329 | IN VOID *TranslationTableBase | |
330 | ); | |
331 | ||
332 | VOID * | |
333 | EFIAPI | |
334 | ArmGetTTBR0BaseAddress ( | |
335 | VOID | |
336 | ); | |
337 | ||
338 | VOID | |
339 | EFIAPI | |
340 | ArmConfigureMmu ( | |
341 | IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, | |
342 | OUT VOID **TranslationTableBase OPTIONAL, | |
343 | OUT UINTN *TranslationTableSize OPTIONAL | |
344 | ); | |
345 | ||
346 | BOOLEAN | |
347 | EFIAPI | |
348 | ArmMmuEnabled ( | |
349 | VOID | |
350 | ); | |
351 | ||
352 | VOID | |
353 | EFIAPI | |
354 | ArmSwitchProcessorMode ( | |
355 | IN ARM_PROCESSOR_MODE Mode | |
356 | ); | |
357 | ||
358 | ARM_PROCESSOR_MODE | |
359 | EFIAPI | |
360 | ArmProcessorMode ( | |
361 | VOID | |
362 | ); | |
363 | ||
364 | VOID | |
365 | EFIAPI | |
366 | ArmEnableBranchPrediction ( | |
367 | VOID | |
368 | ); | |
369 | ||
370 | VOID | |
371 | EFIAPI | |
372 | ArmDisableBranchPrediction ( | |
373 | VOID | |
374 | ); | |
375 | ||
376 | VOID | |
377 | EFIAPI | |
378 | ArmSetLowVectors ( | |
379 | VOID | |
380 | ); | |
381 | ||
382 | VOID | |
383 | EFIAPI | |
384 | ArmSetHighVectors ( | |
385 | VOID | |
386 | ); | |
387 | ||
388 | VOID | |
389 | EFIAPI | |
390 | ArmDataMemoryBarrier ( | |
391 | VOID | |
392 | ); | |
393 | ||
394 | VOID | |
395 | EFIAPI | |
396 | ArmDataSyncronizationBarrier ( | |
397 | VOID | |
398 | ); | |
399 | ||
400 | VOID | |
401 | EFIAPI | |
402 | ArmInstructionSynchronizationBarrier ( | |
403 | VOID | |
404 | ); | |
405 | ||
406 | VOID | |
407 | EFIAPI | |
408 | ArmWriteVBar ( | |
409 | IN UINT32 VectorBase | |
410 | ); | |
411 | ||
412 | UINT32 | |
413 | EFIAPI | |
414 | ArmReadVBar ( | |
415 | VOID | |
416 | ); | |
417 | ||
418 | VOID | |
419 | EFIAPI | |
420 | ArmWriteAuxCr ( | |
421 | IN UINT32 Bit | |
422 | ); | |
423 | ||
424 | UINT32 | |
425 | EFIAPI | |
426 | ArmReadAuxCr ( | |
427 | VOID | |
428 | ); | |
429 | ||
430 | VOID | |
431 | EFIAPI | |
432 | ArmSetAuxCrBit ( | |
433 | IN UINT32 Bits | |
434 | ); | |
435 | ||
436 | VOID | |
437 | EFIAPI | |
438 | ArmCallWFI ( | |
439 | VOID | |
440 | ); | |
441 | ||
442 | UINTN | |
443 | EFIAPI | |
444 | ArmReadMpidr ( | |
445 | VOID | |
446 | ); | |
447 | ||
448 | VOID | |
449 | EFIAPI | |
450 | ArmWriteCPACR ( | |
451 | IN UINT32 Access | |
452 | ); | |
453 | ||
454 | VOID | |
455 | EFIAPI | |
456 | ArmEnableVFP ( | |
457 | VOID | |
458 | ); | |
459 | ||
460 | VOID | |
461 | EFIAPI | |
462 | ArmWriteNsacr ( | |
463 | IN UINT32 SetWayFormat | |
464 | ); | |
465 | ||
466 | VOID | |
467 | EFIAPI | |
468 | ArmWriteScr ( | |
469 | IN UINT32 SetWayFormat | |
470 | ); | |
471 | ||
472 | VOID | |
473 | EFIAPI | |
474 | ArmWriteVMBar ( | |
475 | IN UINT32 VectorMonitorBase | |
476 | ); | |
477 | ||
478 | #endif // __ARM_LIB__ |