| | 1 | /** @file\r |
| | 2 | \r |
| | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| | 4 | Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r |
| | 5 | Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r |
| | 6 | \r |
| | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 8 | \r |
| | 9 | **/\r |
| | 10 | \r |
| | 11 | #ifndef ARM_LIB_H_\r |
| | 12 | #define ARM_LIB_H_\r |
| | 13 | \r |
| | 14 | #include <Uefi/UefiBaseType.h>\r |
| | 15 | \r |
| | 16 | #ifdef MDE_CPU_ARM\r |
| | 17 | #include <Chipset/ArmV7.h>\r |
| | 18 | #elif defined (MDE_CPU_AARCH64)\r |
| | 19 | #include <Chipset/AArch64.h>\r |
| | 20 | #else\r |
| | 21 | #error "Unknown chipset."\r |
| | 22 | #endif\r |
| | 23 | \r |
| | 24 | #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r |
| | 25 | EFI_MEMORY_WT | EFI_MEMORY_WB | \\r |
| | 26 | EFI_MEMORY_UCE)\r |
| | 27 | \r |
| | 28 | /**\r |
| | 29 | * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r |
| | 30 | *\r |
| | 31 | * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r |
| | 32 | * be used in Secure World to distinguished Secure to Non-Secure memory.\r |
| | 33 | */\r |
| | 34 | typedef enum {\r |
| | 35 | ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r |
| | 36 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r |
| | 37 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r |
| | 38 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r |
| | 39 | \r |
| | 40 | // On some platforms, memory mapped flash region is designed as not supporting\r |
| | 41 | // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r |
| | 42 | // need.\r |
| | 43 | // Do NOT use below two attributes if you are not sure.\r |
| | 44 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r |
| | 45 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r |
| | 46 | \r |
| | 47 | ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r |
| | 48 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r |
| | 49 | ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r |
| | 50 | ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r |
| | 51 | } ARM_MEMORY_REGION_ATTRIBUTES;\r |
| | 52 | \r |
| | 53 | #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r |
| | 54 | \r |
| | 55 | typedef struct {\r |
| | 56 | EFI_PHYSICAL_ADDRESS PhysicalBase;\r |
| | 57 | EFI_VIRTUAL_ADDRESS VirtualBase;\r |
| | 58 | UINT64 Length;\r |
| | 59 | ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r |
| | 60 | } ARM_MEMORY_REGION_DESCRIPTOR;\r |
| | 61 | \r |
| | 62 | typedef VOID (*CACHE_OPERATION)(\r |
| | 63 | VOID\r |
| | 64 | );\r |
| | 65 | typedef VOID (*LINE_OPERATION)(\r |
| | 66 | UINTN\r |
| | 67 | );\r |
| | 68 | \r |
| | 69 | //\r |
| | 70 | // ARM Processor Mode\r |
| | 71 | //\r |
| | 72 | typedef enum {\r |
| | 73 | ARM_PROCESSOR_MODE_USER = 0x10,\r |
| | 74 | ARM_PROCESSOR_MODE_FIQ = 0x11,\r |
| | 75 | ARM_PROCESSOR_MODE_IRQ = 0x12,\r |
| | 76 | ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r |
| | 77 | ARM_PROCESSOR_MODE_ABORT = 0x17,\r |
| | 78 | ARM_PROCESSOR_MODE_HYP = 0x1A,\r |
| | 79 | ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r |
| | 80 | ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r |
| | 81 | ARM_PROCESSOR_MODE_MASK = 0x1F\r |
| | 82 | } ARM_PROCESSOR_MODE;\r |
| | 83 | \r |
| | 84 | //\r |
| | 85 | // ARM Cpu IDs\r |
| | 86 | //\r |
| | 87 | #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r |
| | 88 | #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r |
| | 89 | #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r |
| | 90 | #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r |
| | 91 | #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r |
| | 92 | #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r |
| | 93 | \r |
| | 94 | #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r |
| | 95 | #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r |
| | 96 | #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r |
| | 97 | #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r |
| | 98 | #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r |
| | 99 | #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r |
| | 100 | \r |
| | 101 | //\r |
| | 102 | // ARM MP Core IDs\r |
| | 103 | //\r |
| | 104 | #define ARM_CORE_AFF0 0xFF\r |
| | 105 | #define ARM_CORE_AFF1 (0xFF << 8)\r |
| | 106 | #define ARM_CORE_AFF2 (0xFF << 16)\r |
| | 107 | #define ARM_CORE_AFF3 (0xFFULL << 32)\r |
| | 108 | \r |
| | 109 | #define ARM_CORE_MASK ARM_CORE_AFF0\r |
| | 110 | #define ARM_CLUSTER_MASK ARM_CORE_AFF1\r |
| | 111 | #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r |
| | 112 | #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r |
| | 113 | #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r |
| | 114 | #define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)\r |
| | 115 | #define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)\r |
| | 116 | #define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)\r |
| | 117 | #define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)\r |
| | 118 | #define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)\r |
| | 119 | #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r |
| | 120 | #define MPIDR_MT_BIT BIT24\r |
| | 121 | \r |
| | 122 | /** Reads the CCSIDR register for the specified cache.\r |
| | 123 | \r |
| | 124 | @param CSSELR The CSSELR cache selection register value.\r |
| | 125 | \r |
| | 126 | @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r |
| | 127 | Returns the contents of the CCSIDR register in AARCH32 mode.\r |
| | 128 | **/\r |
| | 129 | UINTN\r |
| | 130 | ReadCCSIDR (\r |
| | 131 | IN UINT32 CSSELR\r |
| | 132 | );\r |
| | 133 | \r |
| | 134 | /** Reads the CCSIDR2 for the specified cache.\r |
| | 135 | \r |
| | 136 | @param CSSELR The CSSELR cache selection register value\r |
| | 137 | \r |
| | 138 | @return The contents of the CCSIDR2 register for the specified cache.\r |
| | 139 | **/\r |
| | 140 | UINT32\r |
| | 141 | ReadCCSIDR2 (\r |
| | 142 | IN UINT32 CSSELR\r |
| | 143 | );\r |
| | 144 | \r |
| | 145 | /** Reads the Cache Level ID (CLIDR) register.\r |
| | 146 | \r |
| | 147 | @return The contents of the CLIDR_EL1 register.\r |
| | 148 | **/\r |
| | 149 | UINT32\r |
| | 150 | ReadCLIDR (\r |
| | 151 | VOID\r |
| | 152 | );\r |
| | 153 | \r |
| | 154 | UINTN\r |
| | 155 | EFIAPI\r |
| | 156 | ArmDataCacheLineLength (\r |
| | 157 | VOID\r |
| | 158 | );\r |
| | 159 | \r |
| | 160 | UINTN\r |
| | 161 | EFIAPI\r |
| | 162 | ArmInstructionCacheLineLength (\r |
| | 163 | VOID\r |
| | 164 | );\r |
| | 165 | \r |
| | 166 | UINTN\r |
| | 167 | EFIAPI\r |
| | 168 | ArmCacheWritebackGranule (\r |
| | 169 | VOID\r |
| | 170 | );\r |
| | 171 | \r |
| | 172 | UINTN\r |
| | 173 | EFIAPI\r |
| | 174 | ArmIsArchTimerImplemented (\r |
| | 175 | VOID\r |
| | 176 | );\r |
| | 177 | \r |
| | 178 | UINTN\r |
| | 179 | EFIAPI\r |
| | 180 | ArmCacheInfo (\r |
| | 181 | VOID\r |
| | 182 | );\r |
| | 183 | \r |
| | 184 | BOOLEAN\r |
| | 185 | EFIAPI\r |
| | 186 | ArmIsMpCore (\r |
| | 187 | VOID\r |
| | 188 | );\r |
| | 189 | \r |
| | 190 | VOID\r |
| | 191 | EFIAPI\r |
| | 192 | ArmInvalidateDataCache (\r |
| | 193 | VOID\r |
| | 194 | );\r |
| | 195 | \r |
| | 196 | VOID\r |
| | 197 | EFIAPI\r |
| | 198 | ArmCleanInvalidateDataCache (\r |
| | 199 | VOID\r |
| | 200 | );\r |
| | 201 | \r |
| | 202 | VOID\r |
| | 203 | EFIAPI\r |
| | 204 | ArmCleanDataCache (\r |
| | 205 | VOID\r |
| | 206 | );\r |
| | 207 | \r |
| | 208 | VOID\r |
| | 209 | EFIAPI\r |
| | 210 | ArmInvalidateInstructionCache (\r |
| | 211 | VOID\r |
| | 212 | );\r |
| | 213 | \r |
| | 214 | VOID\r |
| | 215 | EFIAPI\r |
| | 216 | ArmInvalidateDataCacheEntryByMVA (\r |
| | 217 | IN UINTN Address\r |
| | 218 | );\r |
| | 219 | \r |
| | 220 | VOID\r |
| | 221 | EFIAPI\r |
| | 222 | ArmCleanDataCacheEntryToPoUByMVA (\r |
| | 223 | IN UINTN Address\r |
| | 224 | );\r |
| | 225 | \r |
| | 226 | VOID\r |
| | 227 | EFIAPI\r |
| | 228 | ArmInvalidateInstructionCacheEntryToPoUByMVA (\r |
| | 229 | IN UINTN Address\r |
| | 230 | );\r |
| | 231 | \r |
| | 232 | VOID\r |
| | 233 | EFIAPI\r |
| | 234 | ArmCleanDataCacheEntryByMVA (\r |
| | 235 | IN UINTN Address\r |
| | 236 | );\r |
| | 237 | \r |
| | 238 | VOID\r |
| | 239 | EFIAPI\r |
| | 240 | ArmCleanInvalidateDataCacheEntryByMVA (\r |
| | 241 | IN UINTN Address\r |
| | 242 | );\r |
| | 243 | \r |
| | 244 | VOID\r |
| | 245 | EFIAPI\r |
| | 246 | ArmEnableDataCache (\r |
| | 247 | VOID\r |
| | 248 | );\r |
| | 249 | \r |
| | 250 | VOID\r |
| | 251 | EFIAPI\r |
| | 252 | ArmDisableDataCache (\r |
| | 253 | VOID\r |
| | 254 | );\r |
| | 255 | \r |
| | 256 | VOID\r |
| | 257 | EFIAPI\r |
| | 258 | ArmEnableInstructionCache (\r |
| | 259 | VOID\r |
| | 260 | );\r |
| | 261 | \r |
| | 262 | VOID\r |
| | 263 | EFIAPI\r |
| | 264 | ArmDisableInstructionCache (\r |
| | 265 | VOID\r |
| | 266 | );\r |
| | 267 | \r |
| | 268 | VOID\r |
| | 269 | EFIAPI\r |
| | 270 | ArmEnableMmu (\r |
| | 271 | VOID\r |
| | 272 | );\r |
| | 273 | \r |
| | 274 | VOID\r |
| | 275 | EFIAPI\r |
| | 276 | ArmDisableMmu (\r |
| | 277 | VOID\r |
| | 278 | );\r |
| | 279 | \r |
| | 280 | VOID\r |
| | 281 | EFIAPI\r |
| | 282 | ArmEnableCachesAndMmu (\r |
| | 283 | VOID\r |
| | 284 | );\r |
| | 285 | \r |
| | 286 | VOID\r |
| | 287 | EFIAPI\r |
| | 288 | ArmDisableCachesAndMmu (\r |
| | 289 | VOID\r |
| | 290 | );\r |
| | 291 | \r |
| | 292 | VOID\r |
| | 293 | EFIAPI\r |
| | 294 | ArmEnableInterrupts (\r |
| | 295 | VOID\r |
| | 296 | );\r |
| | 297 | \r |
| | 298 | UINTN\r |
| | 299 | EFIAPI\r |
| | 300 | ArmDisableInterrupts (\r |
| | 301 | VOID\r |
| | 302 | );\r |
| | 303 | \r |
| | 304 | BOOLEAN\r |
| | 305 | EFIAPI\r |
| | 306 | ArmGetInterruptState (\r |
| | 307 | VOID\r |
| | 308 | );\r |
| | 309 | \r |
| | 310 | VOID\r |
| | 311 | EFIAPI\r |
| | 312 | ArmEnableAsynchronousAbort (\r |
| | 313 | VOID\r |
| | 314 | );\r |
| | 315 | \r |
| | 316 | UINTN\r |
| | 317 | EFIAPI\r |
| | 318 | ArmDisableAsynchronousAbort (\r |
| | 319 | VOID\r |
| | 320 | );\r |
| | 321 | \r |
| | 322 | VOID\r |
| | 323 | EFIAPI\r |
| | 324 | ArmEnableIrq (\r |
| | 325 | VOID\r |
| | 326 | );\r |
| | 327 | \r |
| | 328 | UINTN\r |
| | 329 | EFIAPI\r |
| | 330 | ArmDisableIrq (\r |
| | 331 | VOID\r |
| | 332 | );\r |
| | 333 | \r |
| | 334 | VOID\r |
| | 335 | EFIAPI\r |
| | 336 | ArmEnableFiq (\r |
| | 337 | VOID\r |
| | 338 | );\r |
| | 339 | \r |
| | 340 | UINTN\r |
| | 341 | EFIAPI\r |
| | 342 | ArmDisableFiq (\r |
| | 343 | VOID\r |
| | 344 | );\r |
| | 345 | \r |
| | 346 | BOOLEAN\r |
| | 347 | EFIAPI\r |
| | 348 | ArmGetFiqState (\r |
| | 349 | VOID\r |
| | 350 | );\r |
| | 351 | \r |
| | 352 | /**\r |
| | 353 | * Invalidate Data and Instruction TLBs\r |
| | 354 | */\r |
| | 355 | VOID\r |
| | 356 | EFIAPI\r |
| | 357 | ArmInvalidateTlb (\r |
| | 358 | VOID\r |
| | 359 | );\r |
| | 360 | \r |
| | 361 | VOID\r |
| | 362 | EFIAPI\r |
| | 363 | ArmUpdateTranslationTableEntry (\r |
| | 364 | IN VOID *TranslationTableEntry,\r |
| | 365 | IN VOID *Mva\r |
| | 366 | );\r |
| | 367 | \r |
| | 368 | VOID\r |
| | 369 | EFIAPI\r |
| | 370 | ArmSetDomainAccessControl (\r |
| | 371 | IN UINT32 Domain\r |
| | 372 | );\r |
| | 373 | \r |
| | 374 | VOID\r |
| | 375 | EFIAPI\r |
| | 376 | ArmSetTTBR0 (\r |
| | 377 | IN VOID *TranslationTableBase\r |
| | 378 | );\r |
| | 379 | \r |
| | 380 | VOID\r |
| | 381 | EFIAPI\r |
| | 382 | ArmSetTTBCR (\r |
| | 383 | IN UINT32 Bits\r |
| | 384 | );\r |
| | 385 | \r |
| | 386 | VOID *\r |
| | 387 | EFIAPI\r |
| | 388 | ArmGetTTBR0BaseAddress (\r |
| | 389 | VOID\r |
| | 390 | );\r |
| | 391 | \r |
| | 392 | BOOLEAN\r |
| | 393 | EFIAPI\r |
| | 394 | ArmMmuEnabled (\r |
| | 395 | VOID\r |
| | 396 | );\r |
| | 397 | \r |
| | 398 | VOID\r |
| | 399 | EFIAPI\r |
| | 400 | ArmEnableBranchPrediction (\r |
| | 401 | VOID\r |
| | 402 | );\r |
| | 403 | \r |
| | 404 | VOID\r |
| | 405 | EFIAPI\r |
| | 406 | ArmDisableBranchPrediction (\r |
| | 407 | VOID\r |
| | 408 | );\r |
| | 409 | \r |
| | 410 | VOID\r |
| | 411 | EFIAPI\r |
| | 412 | ArmSetLowVectors (\r |
| | 413 | VOID\r |
| | 414 | );\r |
| | 415 | \r |
| | 416 | VOID\r |
| | 417 | EFIAPI\r |
| | 418 | ArmSetHighVectors (\r |
| | 419 | VOID\r |
| | 420 | );\r |
| | 421 | \r |
| | 422 | VOID\r |
| | 423 | EFIAPI\r |
| | 424 | ArmDataMemoryBarrier (\r |
| | 425 | VOID\r |
| | 426 | );\r |
| | 427 | \r |
| | 428 | VOID\r |
| | 429 | EFIAPI\r |
| | 430 | ArmDataSynchronizationBarrier (\r |
| | 431 | VOID\r |
| | 432 | );\r |
| | 433 | \r |
| | 434 | VOID\r |
| | 435 | EFIAPI\r |
| | 436 | ArmInstructionSynchronizationBarrier (\r |
| | 437 | VOID\r |
| | 438 | );\r |
| | 439 | \r |
| | 440 | VOID\r |
| | 441 | EFIAPI\r |
| | 442 | ArmWriteVBar (\r |
| | 443 | IN UINTN VectorBase\r |
| | 444 | );\r |
| | 445 | \r |
| | 446 | UINTN\r |
| | 447 | EFIAPI\r |
| | 448 | ArmReadVBar (\r |
| | 449 | VOID\r |
| | 450 | );\r |
| | 451 | \r |
| | 452 | VOID\r |
| | 453 | EFIAPI\r |
| | 454 | ArmWriteAuxCr (\r |
| | 455 | IN UINT32 Bit\r |
| | 456 | );\r |
| | 457 | \r |
| | 458 | UINT32\r |
| | 459 | EFIAPI\r |
| | 460 | ArmReadAuxCr (\r |
| | 461 | VOID\r |
| | 462 | );\r |
| | 463 | \r |
| | 464 | VOID\r |
| | 465 | EFIAPI\r |
| | 466 | ArmSetAuxCrBit (\r |
| | 467 | IN UINT32 Bits\r |
| | 468 | );\r |
| | 469 | \r |
| | 470 | VOID\r |
| | 471 | EFIAPI\r |
| | 472 | ArmUnsetAuxCrBit (\r |
| | 473 | IN UINT32 Bits\r |
| | 474 | );\r |
| | 475 | \r |
| | 476 | VOID\r |
| | 477 | EFIAPI\r |
| | 478 | ArmCallSEV (\r |
| | 479 | VOID\r |
| | 480 | );\r |
| | 481 | \r |
| | 482 | VOID\r |
| | 483 | EFIAPI\r |
| | 484 | ArmCallWFE (\r |
| | 485 | VOID\r |
| | 486 | );\r |
| | 487 | \r |
| | 488 | VOID\r |
| | 489 | EFIAPI\r |
| | 490 | ArmCallWFI (\r |
| | 491 | \r |
| | 492 | VOID\r |
| | 493 | );\r |
| | 494 | \r |
| | 495 | UINTN\r |
| | 496 | EFIAPI\r |
| | 497 | ArmReadMpidr (\r |
| | 498 | VOID\r |
| | 499 | );\r |
| | 500 | \r |
| | 501 | UINTN\r |
| | 502 | EFIAPI\r |
| | 503 | ArmReadMidr (\r |
| | 504 | VOID\r |
| | 505 | );\r |
| | 506 | \r |
| | 507 | UINT32\r |
| | 508 | EFIAPI\r |
| | 509 | ArmReadCpacr (\r |
| | 510 | VOID\r |
| | 511 | );\r |
| | 512 | \r |
| | 513 | VOID\r |
| | 514 | EFIAPI\r |
| | 515 | ArmWriteCpacr (\r |
| | 516 | IN UINT32 Access\r |
| | 517 | );\r |
| | 518 | \r |
| | 519 | VOID\r |
| | 520 | EFIAPI\r |
| | 521 | ArmEnableVFP (\r |
| | 522 | VOID\r |
| | 523 | );\r |
| | 524 | \r |
| | 525 | /**\r |
| | 526 | Get the Secure Configuration Register value\r |
| | 527 | \r |
| | 528 | @return Value read from the Secure Configuration Register\r |
| | 529 | \r |
| | 530 | **/\r |
| | 531 | UINT32\r |
| | 532 | EFIAPI\r |
| | 533 | ArmReadScr (\r |
| | 534 | VOID\r |
| | 535 | );\r |
| | 536 | \r |
| | 537 | /**\r |
| | 538 | Set the Secure Configuration Register\r |
| | 539 | \r |
| | 540 | @param Value Value to write to the Secure Configuration Register\r |
| | 541 | \r |
| | 542 | **/\r |
| | 543 | VOID\r |
| | 544 | EFIAPI\r |
| | 545 | ArmWriteScr (\r |
| | 546 | IN UINT32 Value\r |
| | 547 | );\r |
| | 548 | \r |
| | 549 | UINT32\r |
| | 550 | EFIAPI\r |
| | 551 | ArmReadMVBar (\r |
| | 552 | VOID\r |
| | 553 | );\r |
| | 554 | \r |
| | 555 | VOID\r |
| | 556 | EFIAPI\r |
| | 557 | ArmWriteMVBar (\r |
| | 558 | IN UINT32 VectorMonitorBase\r |
| | 559 | );\r |
| | 560 | \r |
| | 561 | UINT32\r |
| | 562 | EFIAPI\r |
| | 563 | ArmReadSctlr (\r |
| | 564 | VOID\r |
| | 565 | );\r |
| | 566 | \r |
| | 567 | VOID\r |
| | 568 | EFIAPI\r |
| | 569 | ArmWriteSctlr (\r |
| | 570 | IN UINT32 Value\r |
| | 571 | );\r |
| | 572 | \r |
| | 573 | UINTN\r |
| | 574 | EFIAPI\r |
| | 575 | ArmReadHVBar (\r |
| | 576 | VOID\r |
| | 577 | );\r |
| | 578 | \r |
| | 579 | VOID\r |
| | 580 | EFIAPI\r |
| | 581 | ArmWriteHVBar (\r |
| | 582 | IN UINTN HypModeVectorBase\r |
| | 583 | );\r |
| | 584 | \r |
| | 585 | //\r |
| | 586 | // Helper functions for accessing CPU ACTLR\r |
| | 587 | //\r |
| | 588 | \r |
| | 589 | UINTN\r |
| | 590 | EFIAPI\r |
| | 591 | ArmReadCpuActlr (\r |
| | 592 | VOID\r |
| | 593 | );\r |
| | 594 | \r |
| | 595 | VOID\r |
| | 596 | EFIAPI\r |
| | 597 | ArmWriteCpuActlr (\r |
| | 598 | IN UINTN Val\r |
| | 599 | );\r |
| | 600 | \r |
| | 601 | VOID\r |
| | 602 | EFIAPI\r |
| | 603 | ArmSetCpuActlrBit (\r |
| | 604 | IN UINTN Bits\r |
| | 605 | );\r |
| | 606 | \r |
| | 607 | VOID\r |
| | 608 | EFIAPI\r |
| | 609 | ArmUnsetCpuActlrBit (\r |
| | 610 | IN UINTN Bits\r |
| | 611 | );\r |
| | 612 | \r |
| | 613 | //\r |
| | 614 | // Accessors for the architected generic timer registers\r |
| | 615 | //\r |
| | 616 | \r |
| | 617 | #define ARM_ARCH_TIMER_ENABLE (1 << 0)\r |
| | 618 | #define ARM_ARCH_TIMER_IMASK (1 << 1)\r |
| | 619 | #define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r |
| | 620 | \r |
| | 621 | UINTN\r |
| | 622 | EFIAPI\r |
| | 623 | ArmReadCntFrq (\r |
| | 624 | VOID\r |
| | 625 | );\r |
| | 626 | \r |
| | 627 | VOID\r |
| | 628 | EFIAPI\r |
| | 629 | ArmWriteCntFrq (\r |
| | 630 | UINTN FreqInHz\r |
| | 631 | );\r |
| | 632 | \r |
| | 633 | UINT64\r |
| | 634 | EFIAPI\r |
| | 635 | ArmReadCntPct (\r |
| | 636 | VOID\r |
| | 637 | );\r |
| | 638 | \r |
| | 639 | UINTN\r |
| | 640 | EFIAPI\r |
| | 641 | ArmReadCntkCtl (\r |
| | 642 | VOID\r |
| | 643 | );\r |
| | 644 | \r |
| | 645 | VOID\r |
| | 646 | EFIAPI\r |
| | 647 | ArmWriteCntkCtl (\r |
| | 648 | UINTN Val\r |
| | 649 | );\r |
| | 650 | \r |
| | 651 | UINTN\r |
| | 652 | EFIAPI\r |
| | 653 | ArmReadCntpTval (\r |
| | 654 | VOID\r |
| | 655 | );\r |
| | 656 | \r |
| | 657 | VOID\r |
| | 658 | EFIAPI\r |
| | 659 | ArmWriteCntpTval (\r |
| | 660 | UINTN Val\r |
| | 661 | );\r |
| | 662 | \r |
| | 663 | UINTN\r |
| | 664 | EFIAPI\r |
| | 665 | ArmReadCntpCtl (\r |
| | 666 | VOID\r |
| | 667 | );\r |
| | 668 | \r |
| | 669 | VOID\r |
| | 670 | EFIAPI\r |
| | 671 | ArmWriteCntpCtl (\r |
| | 672 | UINTN Val\r |
| | 673 | );\r |
| | 674 | \r |
| | 675 | UINTN\r |
| | 676 | EFIAPI\r |
| | 677 | ArmReadCntvTval (\r |
| | 678 | VOID\r |
| | 679 | );\r |
| | 680 | \r |
| | 681 | VOID\r |
| | 682 | EFIAPI\r |
| | 683 | ArmWriteCntvTval (\r |
| | 684 | UINTN Val\r |
| | 685 | );\r |
| | 686 | \r |
| | 687 | UINTN\r |
| | 688 | EFIAPI\r |
| | 689 | ArmReadCntvCtl (\r |
| | 690 | VOID\r |
| | 691 | );\r |
| | 692 | \r |
| | 693 | VOID\r |
| | 694 | EFIAPI\r |
| | 695 | ArmWriteCntvCtl (\r |
| | 696 | UINTN Val\r |
| | 697 | );\r |
| | 698 | \r |
| | 699 | UINT64\r |
| | 700 | EFIAPI\r |
| | 701 | ArmReadCntvCt (\r |
| | 702 | VOID\r |
| | 703 | );\r |
| | 704 | \r |
| | 705 | UINT64\r |
| | 706 | EFIAPI\r |
| | 707 | ArmReadCntpCval (\r |
| | 708 | VOID\r |
| | 709 | );\r |
| | 710 | \r |
| | 711 | VOID\r |
| | 712 | EFIAPI\r |
| | 713 | ArmWriteCntpCval (\r |
| | 714 | UINT64 Val\r |
| | 715 | );\r |
| | 716 | \r |
| | 717 | UINT64\r |
| | 718 | EFIAPI\r |
| | 719 | ArmReadCntvCval (\r |
| | 720 | VOID\r |
| | 721 | );\r |
| | 722 | \r |
| | 723 | VOID\r |
| | 724 | EFIAPI\r |
| | 725 | ArmWriteCntvCval (\r |
| | 726 | UINT64 Val\r |
| | 727 | );\r |
| | 728 | \r |
| | 729 | UINT64\r |
| | 730 | EFIAPI\r |
| | 731 | ArmReadCntvOff (\r |
| | 732 | VOID\r |
| | 733 | );\r |
| | 734 | \r |
| | 735 | VOID\r |
| | 736 | EFIAPI\r |
| | 737 | ArmWriteCntvOff (\r |
| | 738 | UINT64 Val\r |
| | 739 | );\r |
| | 740 | \r |
| | 741 | UINTN\r |
| | 742 | EFIAPI\r |
| | 743 | ArmGetPhysicalAddressBits (\r |
| | 744 | VOID\r |
| | 745 | );\r |
| | 746 | \r |
| | 747 | ///\r |
| | 748 | /// ID Register Helper functions\r |
| | 749 | ///\r |
| | 750 | \r |
| | 751 | /**\r |
| | 752 | Check whether the CPU supports the GIC system register interface (any version)\r |
| | 753 | \r |
| | 754 | @return Whether GIC System Register Interface is supported\r |
| | 755 | \r |
| | 756 | **/\r |
| | 757 | BOOLEAN\r |
| | 758 | EFIAPI\r |
| | 759 | ArmHasGicSystemRegisters (\r |
| | 760 | VOID\r |
| | 761 | );\r |
| | 762 | \r |
| | 763 | /** Checks if CCIDX is implemented.\r |
| | 764 | \r |
| | 765 | @retval TRUE CCIDX is implemented.\r |
| | 766 | @retval FALSE CCIDX is not implemented.\r |
| | 767 | **/\r |
| | 768 | BOOLEAN\r |
| | 769 | EFIAPI\r |
| | 770 | ArmHasCcidx (\r |
| | 771 | VOID\r |
| | 772 | );\r |
| | 773 | \r |
| | 774 | #ifdef MDE_CPU_ARM\r |
| | 775 | ///\r |
| | 776 | /// AArch32-only ID Register Helper functions\r |
| | 777 | ///\r |
| | 778 | \r |
| | 779 | /**\r |
| | 780 | Check whether the CPU supports the Security extensions\r |
| | 781 | \r |
| | 782 | @return Whether the Security extensions are implemented\r |
| | 783 | \r |
| | 784 | **/\r |
| | 785 | BOOLEAN\r |
| | 786 | EFIAPI\r |
| | 787 | ArmHasSecurityExtensions (\r |
| | 788 | VOID\r |
| | 789 | );\r |
| | 790 | \r |
| | 791 | #endif // MDE_CPU_ARM\r |
| | 792 | \r |
| | 793 | #endif // ARM_LIB_H_\r |
projects / mirror_edk2.git / blame_incremental