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1 | /** @file\r | |
2 | \r | |
3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
4 | Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | **/\r | |
9 | #include <Base.h>\r | |
10 | #include <Library/ArmLib.h>\r | |
11 | #include <Library/DebugLib.h>\r | |
12 | #include <Library/PcdLib.h>\r | |
13 | \r | |
14 | STATIC\r | |
15 | VOID\r | |
16 | CacheRangeOperation (\r | |
17 | IN VOID *Start,\r | |
18 | IN UINTN Length,\r | |
19 | IN LINE_OPERATION LineOperation,\r | |
20 | IN UINTN LineLength\r | |
21 | )\r | |
22 | {\r | |
23 | UINTN ArmCacheLineAlignmentMask;\r | |
24 | // Align address (rounding down)\r | |
25 | UINTN AlignedAddress;\r | |
26 | UINTN EndAddress;\r | |
27 | \r | |
28 | ArmCacheLineAlignmentMask = LineLength - 1;\r | |
29 | AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);\r | |
30 | EndAddress = (UINTN)Start + Length;\r | |
31 | \r | |
32 | // Perform the line operation on an address in each cache line\r | |
33 | while (AlignedAddress < EndAddress) {\r | |
34 | LineOperation (AlignedAddress);\r | |
35 | AlignedAddress += LineLength;\r | |
36 | }\r | |
37 | \r | |
38 | ArmDataSynchronizationBarrier ();\r | |
39 | }\r | |
40 | \r | |
41 | VOID\r | |
42 | EFIAPI\r | |
43 | InvalidateInstructionCache (\r | |
44 | VOID\r | |
45 | )\r | |
46 | {\r | |
47 | ASSERT (FALSE);\r | |
48 | }\r | |
49 | \r | |
50 | VOID\r | |
51 | EFIAPI\r | |
52 | InvalidateDataCache (\r | |
53 | VOID\r | |
54 | )\r | |
55 | {\r | |
56 | ASSERT (FALSE);\r | |
57 | }\r | |
58 | \r | |
59 | VOID *\r | |
60 | EFIAPI\r | |
61 | InvalidateInstructionCacheRange (\r | |
62 | IN VOID *Address,\r | |
63 | IN UINTN Length\r | |
64 | )\r | |
65 | {\r | |
66 | CacheRangeOperation (\r | |
67 | Address,\r | |
68 | Length,\r | |
69 | ArmCleanDataCacheEntryToPoUByMVA,\r | |
70 | ArmDataCacheLineLength ()\r | |
71 | );\r | |
72 | CacheRangeOperation (\r | |
73 | Address,\r | |
74 | Length,\r | |
75 | ArmInvalidateInstructionCacheEntryToPoUByMVA,\r | |
76 | ArmInstructionCacheLineLength ()\r | |
77 | );\r | |
78 | \r | |
79 | ArmInstructionSynchronizationBarrier ();\r | |
80 | \r | |
81 | return Address;\r | |
82 | }\r | |
83 | \r | |
84 | VOID\r | |
85 | EFIAPI\r | |
86 | WriteBackInvalidateDataCache (\r | |
87 | VOID\r | |
88 | )\r | |
89 | {\r | |
90 | ASSERT (FALSE);\r | |
91 | }\r | |
92 | \r | |
93 | VOID *\r | |
94 | EFIAPI\r | |
95 | WriteBackInvalidateDataCacheRange (\r | |
96 | IN VOID *Address,\r | |
97 | IN UINTN Length\r | |
98 | )\r | |
99 | {\r | |
100 | CacheRangeOperation (\r | |
101 | Address,\r | |
102 | Length,\r | |
103 | ArmCleanInvalidateDataCacheEntryByMVA,\r | |
104 | ArmDataCacheLineLength ()\r | |
105 | );\r | |
106 | return Address;\r | |
107 | }\r | |
108 | \r | |
109 | VOID\r | |
110 | EFIAPI\r | |
111 | WriteBackDataCache (\r | |
112 | VOID\r | |
113 | )\r | |
114 | {\r | |
115 | ASSERT (FALSE);\r | |
116 | }\r | |
117 | \r | |
118 | VOID *\r | |
119 | EFIAPI\r | |
120 | WriteBackDataCacheRange (\r | |
121 | IN VOID *Address,\r | |
122 | IN UINTN Length\r | |
123 | )\r | |
124 | {\r | |
125 | CacheRangeOperation (\r | |
126 | Address,\r | |
127 | Length,\r | |
128 | ArmCleanDataCacheEntryByMVA,\r | |
129 | ArmDataCacheLineLength ()\r | |
130 | );\r | |
131 | return Address;\r | |
132 | }\r | |
133 | \r | |
134 | VOID *\r | |
135 | EFIAPI\r | |
136 | InvalidateDataCacheRange (\r | |
137 | IN VOID *Address,\r | |
138 | IN UINTN Length\r | |
139 | )\r | |
140 | {\r | |
141 | CacheRangeOperation (\r | |
142 | Address,\r | |
143 | Length,\r | |
144 | ArmInvalidateDataCacheEntryByMVA,\r | |
145 | ArmDataCacheLineLength ()\r | |
146 | );\r | |
147 | return Address;\r | |
148 | }\r |