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1 | ;; @file\r | |
2 | ; Provide FSP API entry points.\r | |
3 | ;\r | |
4 | ; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r | |
5 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | ;;\r | |
7 | \r | |
8 | SECTION .text\r | |
9 | \r | |
10 | %include "SaveRestoreSseNasm.inc"\r | |
11 | %include "MicrocodeLoadNasm.inc"\r | |
12 | \r | |
13 | ;\r | |
14 | ; Following are fixed PCDs\r | |
15 | ;\r | |
16 | extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))\r | |
17 | extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))\r | |
18 | extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))\r | |
19 | \r | |
20 | ;\r | |
21 | ; Following functions will be provided in PlatformSecLib\r | |
22 | ;\r | |
23 | extern ASM_PFX(AsmGetFspBaseAddress)\r | |
24 | extern ASM_PFX(AsmGetFspInfoHeader)\r | |
25 | ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation\r | |
26 | extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation\r | |
27 | extern ASM_PFX(SecCarInit)\r | |
28 | \r | |
29 | ;\r | |
30 | ; Define the data length that we saved on the stack top\r | |
31 | ;\r | |
32 | DATA_LEN_OF_PER0 EQU 18h\r | |
33 | DATA_LEN_OF_MCUD EQU 18h\r | |
34 | DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r | |
35 | \r | |
36 | ;\r | |
37 | ; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid\r | |
38 | ; build error. This needs to be fixed later on.\r | |
39 | ;\r | |
40 | struc MicrocodeHdr\r | |
41 | .MicrocodeHdrVersion: resd 1\r | |
42 | .MicrocodeHdrRevision: resd 1\r | |
43 | .MicrocodeHdrDate: resd 1\r | |
44 | .MicrocodeHdrProcessor: resd 1\r | |
45 | .MicrocodeHdrChecksum: resd 1\r | |
46 | .MicrocodeHdrLoader: resd 1\r | |
47 | .MicrocodeHdrFlags: resd 1\r | |
48 | .MicrocodeHdrDataSize: resd 1\r | |
49 | .MicrocodeHdrTotalSize: resd 1\r | |
50 | .MicrocodeHdrRsvd: resd 3\r | |
51 | .size:\r | |
52 | endstruc\r | |
53 | \r | |
54 | struc ExtSigHdr\r | |
55 | .ExtSigHdrCount: resd 1\r | |
56 | .ExtSigHdrChecksum: resd 1\r | |
57 | .ExtSigHdrRsvd: resd 3\r | |
58 | .size:\r | |
59 | endstruc\r | |
60 | \r | |
61 | struc ExtSig\r | |
62 | .ExtSigProcessor: resd 1\r | |
63 | .ExtSigFlags: resd 1\r | |
64 | .ExtSigChecksum: resd 1\r | |
65 | .size:\r | |
66 | endstruc\r | |
67 | \r | |
68 | struc LoadMicrocodeParams\r | |
69 | ; FSP_UPD_HEADER {\r | |
70 | .FspUpdHeader: resd 8\r | |
71 | ; }\r | |
72 | ; FSPT_CORE_UPD {\r | |
73 | .MicrocodeCodeAddr: resd 1\r | |
74 | .MicrocodeCodeSize: resd 1\r | |
75 | .CodeRegionBase: resd 1\r | |
76 | .CodeRegionSize: resd 1\r | |
77 | ; }\r | |
78 | .size:\r | |
79 | endstruc\r | |
80 | \r | |
81 | struc LoadMicrocodeParamsFsp22\r | |
82 | ; FSP_UPD_HEADER {\r | |
83 | .FspUpdHeaderSignature: resd 2\r | |
84 | .FspUpdHeaderRevision: resb 1\r | |
85 | .FspUpdHeaderReserved: resb 23\r | |
86 | ; }\r | |
87 | ; FSPT_ARCH_UPD {\r | |
88 | .FsptArchRevision: resb 1\r | |
89 | .FsptArchReserved: resb 3\r | |
90 | .FsptArchUpd: resd 7\r | |
91 | ; }\r | |
92 | ; FSPT_CORE_UPD {\r | |
93 | .MicrocodeCodeAddr: resd 1\r | |
94 | .MicrocodeCodeSize: resd 1\r | |
95 | .CodeRegionBase: resd 1\r | |
96 | .CodeRegionSize: resd 1\r | |
97 | ; }\r | |
98 | .size:\r | |
99 | endstruc\r | |
100 | \r | |
101 | struc LoadMicrocodeParamsFsp24\r | |
102 | ; FSP_UPD_HEADER {\r | |
103 | .FspUpdHeaderSignature: resd 2\r | |
104 | .FspUpdHeaderRevision: resb 1\r | |
105 | .FspUpdHeaderReserved: resb 23\r | |
106 | ; }\r | |
107 | ; FSPT_ARCH2_UPD {\r | |
108 | .FsptArchRevision: resb 1\r | |
109 | .FsptArchReserved: resb 3\r | |
110 | .FsptArchLength: resd 1\r | |
111 | .FspDebugHandler resq 1\r | |
112 | .FsptArchUpd: resd 4\r | |
113 | ; }\r | |
114 | ; FSPT_CORE_UPD {\r | |
115 | .MicrocodeCodeAddr: resq 1\r | |
116 | .MicrocodeCodeSize: resq 1\r | |
117 | .CodeRegionBase: resq 1\r | |
118 | .CodeRegionSize: resq 1\r | |
119 | ; }\r | |
120 | .size:\r | |
121 | endstruc\r | |
122 | \r | |
123 | ;\r | |
124 | ; Define SSE macros\r | |
125 | ;\r | |
126 | ;\r | |
127 | ;args 1: ReturnAddress 2:MmxRegister\r | |
128 | ;\r | |
129 | %macro LOAD_MMX_EXT 2\r | |
130 | mov esi, %1\r | |
131 | movd %2, esi ; save ReturnAddress into MMX\r | |
132 | %endmacro\r | |
133 | \r | |
134 | ;\r | |
135 | ;args 1: RoutineLabel 2:MmxRegister\r | |
136 | ;\r | |
137 | %macro CALL_MMX_EXT 2\r | |
138 | mov esi, %%ReturnAddress\r | |
139 | movd %2, esi ; save ReturnAddress into MMX\r | |
140 | jmp %1\r | |
141 | %%ReturnAddress:\r | |
142 | %endmacro\r | |
143 | \r | |
144 | ;\r | |
145 | ;arg 1:MmxRegister\r | |
146 | ;\r | |
147 | %macro RET_ESI_EXT 1\r | |
148 | movd esi, %1 ; move ReturnAddress from MMX to ESI\r | |
149 | jmp esi\r | |
150 | %endmacro\r | |
151 | \r | |
152 | ;\r | |
153 | ;arg 1:RoutineLabel\r | |
154 | ;\r | |
155 | %macro CALL_MMX 1\r | |
156 | CALL_MMX_EXT %1, mm7\r | |
157 | %endmacro\r | |
158 | \r | |
159 | %macro RET_ESI 0\r | |
160 | RET_ESI_EXT mm7\r | |
161 | %endmacro\r | |
162 | \r | |
163 | ;\r | |
164 | ; @todo: The strong/weak implementation does not work.\r | |
165 | ; This needs to be reviewed later.\r | |
166 | ;\r | |
167 | ;------------------------------------------------------------------------------\r | |
168 | ;\r | |
169 | ;;global ASM_PFX(SecPlatformInitDefault)\r | |
170 | ;ASM_PFX(SecPlatformInitDefault):\r | |
171 | ; ; Inputs:\r | |
172 | ; ; mm7 -> Return address\r | |
173 | ; ; Outputs:\r | |
174 | ; ; eax -> 0 - Successful, Non-zero - Failed.\r | |
175 | ; ; Register Usage:\r | |
176 | ; ; eax is cleared and ebp is used for return address.\r | |
177 | ; ; All others reserved.\r | |
178 | ;\r | |
179 | ; ; Save return address to EBP\r | |
180 | ; movd ebp, mm7\r | |
181 | ;\r | |
182 | ; xor eax, eax\r | |
183 | ;Exit1:\r | |
184 | ; jmp ebp\r | |
185 | \r | |
186 | ;------------------------------------------------------------------------------\r | |
187 | global ASM_PFX(LoadMicrocodeDefault)\r | |
188 | ASM_PFX(LoadMicrocodeDefault):\r | |
189 | ; Inputs:\r | |
190 | ; esp -> LoadMicrocodeParams pointer\r | |
191 | ; Register Usage:\r | |
192 | ; esp Preserved\r | |
193 | ; All others destroyed\r | |
194 | ; Assumptions:\r | |
195 | ; No memory available, stack is hard-coded and used for return address\r | |
196 | ; Executed by SBSP and NBSP\r | |
197 | ; Beginning of microcode update region starts on paragraph boundary\r | |
198 | \r | |
199 | ;\r | |
200 | ; Save return address to EBP\r | |
201 | ;\r | |
202 | movd ebp, mm7\r | |
203 | \r | |
204 | cmp esp, 0\r | |
205 | jz ParamError\r | |
206 | mov eax, dword [esp + 4] ; Parameter pointer\r | |
207 | cmp eax, 0\r | |
208 | jz ParamError\r | |
209 | mov esp, eax\r | |
210 | \r | |
211 | ; skip loading Microcode if the MicrocodeCodeSize is zero\r | |
212 | ; and report error if size is less than 2k\r | |
213 | ; first check UPD header revision\r | |
214 | cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r | |
215 | jb Fsp20UpdHeader\r | |
216 | cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r | |
217 | je Fsp24UpdHeader\r | |
218 | jmp Fsp22UpdHeader\r | |
219 | \r | |
220 | Fsp20UpdHeader:\r | |
221 | ; UPD structure is compliant with FSP spec 2.0/2.1\r | |
222 | mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r | |
223 | cmp eax, 0\r | |
224 | jz Exit2\r | |
225 | cmp eax, 0800h\r | |
226 | jl ParamError\r | |
227 | \r | |
228 | mov esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r | |
229 | cmp esi, 0\r | |
230 | jnz CheckMainHeader\r | |
231 | jmp ParamError\r | |
232 | \r | |
233 | Fsp22UpdHeader:\r | |
234 | ; UPD structure is compliant with FSP spec 2.2\r | |
235 | mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r | |
236 | cmp eax, 0\r | |
237 | jz Exit2\r | |
238 | cmp eax, 0800h\r | |
239 | jl ParamError\r | |
240 | \r | |
241 | mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r | |
242 | cmp esi, 0\r | |
243 | jnz CheckMainHeader\r | |
244 | jmp ParamError\r | |
245 | \r | |
246 | Fsp24UpdHeader:\r | |
247 | ; UPD structure is compliant with FSP spec 2.4\r | |
248 | mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r | |
249 | cmp eax, 0\r | |
250 | jz Exit2\r | |
251 | cmp eax, 0800h\r | |
252 | jl ParamError\r | |
253 | \r | |
254 | mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r | |
255 | cmp esi, 0\r | |
256 | jnz CheckMainHeader\r | |
257 | \r | |
258 | ParamError:\r | |
259 | mov eax, 080000002h\r | |
260 | jmp Exit2\r | |
261 | \r | |
262 | CheckMainHeader:\r | |
263 | ; Get processor signature and platform ID from the installed processor\r | |
264 | ; and save into registers for later use\r | |
265 | ; ebx = processor signature\r | |
266 | ; edx = platform ID\r | |
267 | mov eax, 1\r | |
268 | cpuid\r | |
269 | mov ebx, eax\r | |
270 | mov ecx, MSR_IA32_PLATFORM_ID\r | |
271 | rdmsr\r | |
272 | mov ecx, edx\r | |
273 | shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits\r | |
274 | and ecx, 7h ; platform id at bit[52..50]\r | |
275 | mov edx, 1\r | |
276 | shl edx, cl\r | |
277 | \r | |
278 | ; Current register usage\r | |
279 | ; esp -> stack with parameters\r | |
280 | ; esi -> microcode update to check\r | |
281 | ; ebx = processor signature\r | |
282 | ; edx = platform ID\r | |
283 | \r | |
284 | ; Check for valid microcode header\r | |
285 | ; Minimal test checking for header version and loader version as 1\r | |
286 | mov eax, dword 1\r | |
287 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax\r | |
288 | jne AdvanceFixedSize\r | |
289 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax\r | |
290 | jne AdvanceFixedSize\r | |
291 | \r | |
292 | ; Check if signature and plaform ID match\r | |
293 | cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]\r | |
294 | jne LoadMicrocodeDefault1\r | |
295 | test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]\r | |
296 | jnz LoadCheck ; Jif signature and platform ID match\r | |
297 | \r | |
298 | LoadMicrocodeDefault1:\r | |
299 | ; Check if extended header exists\r | |
300 | ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r | |
301 | xor eax, eax\r | |
302 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r | |
303 | je NextMicrocode\r | |
304 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax\r | |
305 | je NextMicrocode\r | |
306 | \r | |
307 | ; Then verify total size - sizeof header > data size\r | |
308 | mov ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r | |
309 | sub ecx, MicrocodeHdr.size\r | |
310 | cmp ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r | |
311 | jng NextMicrocode ; Jif extended header does not exist\r | |
312 | \r | |
313 | ; Set edi -> extended header\r | |
314 | mov edi, esi\r | |
315 | add edi, MicrocodeHdr.size\r | |
316 | add edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r | |
317 | \r | |
318 | ; Get count of extended structures\r | |
319 | mov ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]\r | |
320 | \r | |
321 | ; Move pointer to first signature structure\r | |
322 | add edi, ExtSigHdr.size\r | |
323 | \r | |
324 | CheckExtSig:\r | |
325 | ; Check if extended signature and platform ID match\r | |
326 | cmp dword [edi + ExtSig.ExtSigProcessor], ebx\r | |
327 | jne LoadMicrocodeDefault2\r | |
328 | test dword [edi + ExtSig.ExtSigFlags], edx\r | |
329 | jnz LoadCheck ; Jif signature and platform ID match\r | |
330 | LoadMicrocodeDefault2:\r | |
331 | ; Check if any more extended signatures exist\r | |
332 | add edi, ExtSig.size\r | |
333 | loop CheckExtSig\r | |
334 | \r | |
335 | NextMicrocode:\r | |
336 | ; Advance just after end of this microcode\r | |
337 | xor eax, eax\r | |
338 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r | |
339 | je LoadMicrocodeDefault3\r | |
340 | add esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r | |
341 | jmp CheckAddress\r | |
342 | LoadMicrocodeDefault3:\r | |
343 | add esi, dword 2048\r | |
344 | jmp CheckAddress\r | |
345 | \r | |
346 | AdvanceFixedSize:\r | |
347 | ; Advance by 4X dwords\r | |
348 | add esi, dword 1024\r | |
349 | \r | |
350 | CheckAddress:\r | |
351 | ; Check UPD header revision\r | |
352 | cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r | |
353 | jb Fsp20UpdHeader1\r | |
354 | cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r | |
355 | je Fsp24UpdHeader1;\r | |
356 | jmp Fsp22UpdHeader1\r | |
357 | \r | |
358 | Fsp20UpdHeader1:\r | |
359 | ; UPD structure is compliant with FSP spec 2.0/2.1\r | |
360 | ; Is automatic size detection ?\r | |
361 | mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r | |
362 | cmp eax, 0ffffffffh\r | |
363 | jz LoadMicrocodeDefault4\r | |
364 | \r | |
365 | ; Address >= microcode region address + microcode region size?\r | |
366 | add eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r | |
367 | cmp esi, eax\r | |
368 | jae Done ;Jif address is outside of microcode region\r | |
369 | jmp CheckMainHeader\r | |
370 | \r | |
371 | Fsp22UpdHeader1:\r | |
372 | ; UPD structure is compliant with FSP spec 2.2\r | |
373 | ; Is automatic size detection ?\r | |
374 | mov eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r | |
375 | cmp eax, 0ffffffffh\r | |
376 | jz LoadMicrocodeDefault4\r | |
377 | \r | |
378 | ; Address >= microcode region address + microcode region size?\r | |
379 | add eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r | |
380 | cmp esi, eax\r | |
381 | jae Done ;Jif address is outside of microcode region\r | |
382 | jmp CheckMainHeader\r | |
383 | \r | |
384 | Fsp24UpdHeader1:\r | |
385 | ; UPD structure is compliant with FSP spec 2.4\r | |
386 | ; Is automatic size detection ?\r | |
387 | mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r | |
388 | cmp eax, 0ffffffffh\r | |
389 | jz LoadMicrocodeDefault4\r | |
390 | \r | |
391 | ; Address >= microcode region address + microcode region size?\r | |
392 | add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r | |
393 | cmp esi, eax\r | |
394 | jae Done ;Jif address is outside of microcode region\r | |
395 | jmp CheckMainHeader\r | |
396 | \r | |
397 | LoadMicrocodeDefault4:\r | |
398 | ; Is valid Microcode start point ?\r | |
399 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r | |
400 | jz Done\r | |
401 | \r | |
402 | LoadCheck:\r | |
403 | ; Get the revision of the current microcode update loaded\r | |
404 | mov ecx, MSR_IA32_BIOS_SIGN_ID\r | |
405 | xor eax, eax ; Clear EAX\r | |
406 | xor edx, edx ; Clear EDX\r | |
407 | wrmsr ; Load 0 to MSR at 8Bh\r | |
408 | \r | |
409 | mov eax, 1\r | |
410 | cpuid\r | |
411 | mov ecx, MSR_IA32_BIOS_SIGN_ID\r | |
412 | rdmsr ; Get current microcode signature\r | |
413 | \r | |
414 | ; Verify this microcode update is not already loaded\r | |
415 | cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r | |
416 | je Continue\r | |
417 | \r | |
418 | LoadMicrocode:\r | |
419 | ; EAX contains the linear address of the start of the Update Data\r | |
420 | ; EDX contains zero\r | |
421 | ; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r | |
422 | ; Start microcode load with wrmsr\r | |
423 | mov eax, esi\r | |
424 | add eax, MicrocodeHdr.size\r | |
425 | xor edx, edx\r | |
426 | mov ecx, MSR_IA32_BIOS_UPDT_TRIG\r | |
427 | wrmsr\r | |
428 | mov eax, 1\r | |
429 | cpuid\r | |
430 | \r | |
431 | Continue:\r | |
432 | jmp NextMicrocode\r | |
433 | \r | |
434 | Done:\r | |
435 | mov eax, 1\r | |
436 | cpuid\r | |
437 | mov ecx, MSR_IA32_BIOS_SIGN_ID\r | |
438 | rdmsr ; Get current microcode signature\r | |
439 | xor eax, eax\r | |
440 | cmp edx, 0\r | |
441 | jnz Exit2\r | |
442 | mov eax, 08000000Eh\r | |
443 | \r | |
444 | Exit2:\r | |
445 | jmp ebp\r | |
446 | \r | |
447 | \r | |
448 | global ASM_PFX(EstablishStackFsp)\r | |
449 | ASM_PFX(EstablishStackFsp):\r | |
450 | ;\r | |
451 | ; Save parameter pointer in edx\r | |
452 | ;\r | |
453 | mov edx, dword [esp + 4]\r | |
454 | \r | |
455 | ;\r | |
456 | ; Enable FSP STACK\r | |
457 | ;\r | |
458 | mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r | |
459 | add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r | |
460 | \r | |
461 | push DATA_LEN_OF_MCUD ; Size of the data region\r | |
462 | push 4455434Dh ; Signature of the data region 'MCUD'\r | |
463 | \r | |
464 | ; check UPD structure revision (edx + 8)\r | |
465 | cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r | |
466 | jb Fsp20UpdHeader2\r | |
467 | cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r | |
468 | je Fsp24UpdHeader2\r | |
469 | jmp Fsp22UpdHeader2\r | |
470 | \r | |
471 | Fsp20UpdHeader2:\r | |
472 | ; UPD structure is compliant with FSP spec 2.0/2.1\r | |
473 | push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r | |
474 | push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r | |
475 | push dword [edx + LoadMicrocodeParams.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r | |
476 | push dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r | |
477 | jmp ContinueAfterUpdPush\r | |
478 | \r | |
479 | Fsp22UpdHeader2:\r | |
480 | ; UPD structure is compliant with FSP spec 2.2\r | |
481 | push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r | |
482 | push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r | |
483 | push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r | |
484 | push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r | |
485 | jmp ContinueAfterUpdPush\r | |
486 | \r | |
487 | Fsp24UpdHeader2:\r | |
488 | ; UPD structure is compliant with FSP spec 2.4\r | |
489 | push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 24\r | |
490 | push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 16\r | |
491 | push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 8\r | |
492 | push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r | |
493 | \r | |
494 | ContinueAfterUpdPush:\r | |
495 | ;\r | |
496 | ; Save API entry/exit timestamp into stack\r | |
497 | ;\r | |
498 | push DATA_LEN_OF_PER0 ; Size of the data region\r | |
499 | push 30524550h ; Signature of the data region 'PER0'\r | |
500 | rdtsc\r | |
501 | push edx\r | |
502 | push eax\r | |
503 | LOAD_EDX\r | |
504 | push edx\r | |
505 | LOAD_EAX\r | |
506 | push eax\r | |
507 | \r | |
508 | ;\r | |
509 | ; Terminator for the data on stack\r | |
510 | ;\r | |
511 | push 0\r | |
512 | \r | |
513 | ;\r | |
514 | ; Set ECX/EDX to the BootLoader temporary memory range\r | |
515 | ;\r | |
516 | mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r | |
517 | mov edx, ecx\r | |
518 | add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r | |
519 | sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]\r | |
520 | \r | |
521 | cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.\r | |
522 | jb EstablishStackFspSuccess\r | |
523 | mov eax, 80000003h ;EFI_UNSUPPORTED\r | |
524 | jmp EstablishStackFspExit\r | |
525 | EstablishStackFspSuccess:\r | |
526 | xor eax, eax\r | |
527 | \r | |
528 | EstablishStackFspExit:\r | |
529 | RET_ESI\r | |
530 | \r | |
531 | ;----------------------------------------------------------------------------\r | |
532 | ; TempRamInit API\r | |
533 | ;\r | |
534 | ; This FSP API will load the microcode update, enable code caching for the\r | |
535 | ; region specified by the boot loader and also setup a temporary stack to be\r | |
536 | ; used till main memory is initialized.\r | |
537 | ;\r | |
538 | ;----------------------------------------------------------------------------\r | |
539 | global ASM_PFX(TempRamInitApi)\r | |
540 | ASM_PFX(TempRamInitApi):\r | |
541 | ;\r | |
542 | ; Ensure SSE is enabled\r | |
543 | ;\r | |
544 | ENABLE_SSE\r | |
545 | \r | |
546 | ;\r | |
547 | ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6\r | |
548 | ;\r | |
549 | SAVE_REGS\r | |
550 | \r | |
551 | ;\r | |
552 | ; Save timestamp into XMM6\r | |
553 | ;\r | |
554 | rdtsc\r | |
555 | SAVE_EAX\r | |
556 | SAVE_EDX\r | |
557 | \r | |
558 | ;\r | |
559 | ; Check Parameter\r | |
560 | ;\r | |
561 | mov eax, dword [esp + 4]\r | |
562 | cmp eax, 0\r | |
563 | mov eax, 80000002h\r | |
564 | jz TempRamInitExit\r | |
565 | \r | |
566 | ;\r | |
567 | ; Sec Platform Init\r | |
568 | ;\r | |
569 | CALL_MMX ASM_PFX(SecPlatformInit)\r | |
570 | cmp eax, 0\r | |
571 | jnz TempRamInitExit\r | |
572 | \r | |
573 | ; Load microcode\r | |
574 | LOAD_ESP\r | |
575 | CALL_MMX ASM_PFX(LoadMicrocodeDefault)\r | |
576 | SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.\r | |
577 | ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r | |
578 | \r | |
579 | ; Call Sec CAR Init\r | |
580 | LOAD_ESP\r | |
581 | CALL_MMX ASM_PFX(SecCarInit)\r | |
582 | cmp eax, 0\r | |
583 | jnz TempRamInitExit\r | |
584 | \r | |
585 | LOAD_ESP\r | |
586 | CALL_MMX ASM_PFX(EstablishStackFsp)\r | |
587 | cmp eax, 0\r | |
588 | jnz TempRamInitExit\r | |
589 | \r | |
590 | LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r | |
591 | \r | |
592 | TempRamInitExit:\r | |
593 | mov bl, al ; save al data in bl\r | |
594 | mov al, 07Fh ; API exit postcode 7f\r | |
595 | out 080h, al\r | |
596 | mov al, bl ; restore al data from bl\r | |
597 | \r | |
598 | ;\r | |
599 | ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r | |
600 | ;\r | |
601 | LOAD_REGS\r | |
602 | ret\r | |
603 | \r | |
604 | ;----------------------------------------------------------------------------\r | |
605 | ; Module Entrypoint API\r | |
606 | ;----------------------------------------------------------------------------\r | |
607 | global ASM_PFX(_ModuleEntryPoint)\r | |
608 | ASM_PFX(_ModuleEntryPoint):\r | |
609 | jmp $\r |