;; @file\r
; Provide FSP API entry points.\r
;\r
-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;;\r
\r
.size:\r
endstruc\r
\r
+struc FSPM_UPD_COMMON_FSP24\r
+ ; FSP_UPD_HEADER {\r
+ .FspUpdHeader: resd 8\r
+ ; }\r
+ ; FSPM_ARCH2_UPD {\r
+ .Revision: resb 1\r
+ .Reserved: resb 3\r
+ .Length resd 1\r
+ .StackBase: resq 1\r
+ .StackSize: resq 1\r
+ .BootLoaderTolumSize: resd 1\r
+ .BootMode: resd 1\r
+ .FspEventHandler resq 1\r
+ .Reserved1: resb 24\r
+ ; }\r
+ .size:\r
+endstruc\r
+\r
;\r
; Following functions will be provided in C\r
;\r
pop eax\r
\r
FspStackSetup:\r
+ mov ecx, [edx + FSPM_UPD_COMMON.Revision]\r
+ cmp ecx, 3\r
+ jae FspmUpdCommon2\r
+\r
;\r
; StackBase = temp memory base, StackSize = temp memory size\r
;\r
mov edi, [edx + FSPM_UPD_COMMON.StackBase]\r
mov ecx, [edx + FSPM_UPD_COMMON.StackSize]\r
+ jmp ChkFspHeapSize\r
+\r
+FspmUpdCommon2:\r
+ mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]\r
+ mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]\r
\r
+ChkFspHeapSize:\r
;\r
; Keep using bootloader stack if heap size % is 0\r
;\r
global ASM_PFX(FspPeiCoreEntryOff)\r
ASM_PFX(FspPeiCoreEntryOff):\r
;\r
- ; This value will be pached by the build script\r
+ ; This value will be patched by the build script\r
;\r
DD 0x12345678\r
\r
;; @file\r
; Provide FSP API entry points.\r
;\r
-; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;;\r
\r
.FspUpdHeaderRevision: resb 1\r
.FspUpdHeaderReserved: resb 23\r
; }\r
- ; FSPT_ARCH_UPD{\r
- .FsptArchUpd: resd 8\r
+ ; FSPT_ARCH_UPD {\r
+ .FsptArchRevision: resb 1\r
+ .FsptArchReserved: resb 3\r
+ .FsptArchUpd: resd 7\r
; }\r
; FSPT_CORE_UPD {\r
.MicrocodeCodeAddr: resd 1\r
.size:\r
endstruc\r
\r
+struc LoadMicrocodeParamsFsp24\r
+ ; FSP_UPD_HEADER {\r
+ .FspUpdHeaderSignature: resd 2\r
+ .FspUpdHeaderRevision: resb 1\r
+ .FspUpdHeaderReserved: resb 23\r
+ ; }\r
+ ; FSPT_ARCH2_UPD {\r
+ .FsptArchRevision: resb 1\r
+ .FsptArchReserved: resb 3\r
+ .FsptArchLength: resd 1\r
+ .FspDebugHandler resq 1\r
+ .FsptArchUpd: resd 4\r
+ ; }\r
+ ; FSPT_CORE_UPD {\r
+ .MicrocodeCodeAddr: resq 1\r
+ .MicrocodeCodeSize: resq 1\r
+ .CodeRegionBase: resq 1\r
+ .CodeRegionSize: resq 1\r
+ ; }\r
+ .size:\r
+endstruc\r
+\r
;\r
; Define SSE macros\r
;\r
; Executed by SBSP and NBSP\r
; Beginning of microcode update region starts on paragraph boundary\r
\r
- ;\r
;\r
; Save return address to EBP\r
+ ;\r
movd ebp, mm7\r
\r
cmp esp, 0\r
; and report error if size is less than 2k\r
; first check UPD header revision\r
cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
- jae Fsp22UpdHeader\r
+ jb Fsp20UpdHeader\r
+ cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
+ je Fsp24UpdHeader\r
+ jmp Fsp22UpdHeader\r
\r
+Fsp20UpdHeader:\r
; UPD structure is compliant with FSP spec 2.0/2.1\r
mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
cmp eax, 0\r
mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
cmp esi, 0\r
jnz CheckMainHeader\r
+ jmp ParamError\r
+\r
+Fsp24UpdHeader:\r
+ ; UPD structure is compliant with FSP spec 2.4\r
+ mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
+ cmp eax, 0\r
+ jz Exit2\r
+ cmp eax, 0800h\r
+ jl ParamError\r
+\r
+ mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
+ cmp esi, 0\r
+ jnz CheckMainHeader\r
\r
ParamError:\r
mov eax, 080000002h\r
\r
CheckAddress:\r
; Check UPD header revision\r
- cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
- jae Fsp22UpdHeader1\r
+ cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+ jb Fsp20UpdHeader1\r
+ cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
+ je Fsp24UpdHeader1;\r
+ jmp Fsp22UpdHeader1\r
\r
+Fsp20UpdHeader1:\r
; UPD structure is compliant with FSP spec 2.0/2.1\r
; Is automatic size detection ?\r
mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
jae Done ;Jif address is outside of microcode region\r
jmp CheckMainHeader\r
\r
+Fsp24UpdHeader1:\r
+ ; UPD structure is compliant with FSP spec 2.4\r
+ ; Is automatic size detection ?\r
+ mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
+ cmp eax, 0ffffffffh\r
+ jz LoadMicrocodeDefault4\r
+\r
+ ; Address >= microcode region address + microcode region size?\r
+ add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
+ cmp esi, eax\r
+ jae Done ;Jif address is outside of microcode region\r
+ jmp CheckMainHeader\r
+\r
LoadMicrocodeDefault4:\r
; Is valid Microcode start point ?\r
cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
mov eax, 1\r
cpuid\r
mov ecx, MSR_IA32_BIOS_SIGN_ID\r
- rdmsr ; Get current microcode signature\r
+ rdmsr ; Get current microcode signature\r
\r
; Verify this microcode update is not already loaded\r
cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
\r
; check UPD structure revision (edx + 8)\r
cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
- jae Fsp22UpdHeader2\r
+ jb Fsp20UpdHeader2\r
+ cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
+ je Fsp24UpdHeader2\r
+ jmp Fsp22UpdHeader2\r
\r
+Fsp20UpdHeader2:\r
; UPD structure is compliant with FSP spec 2.0/2.1\r
push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 12\r
push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 8\r
push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 4\r
push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
+ jmp ContinueAfterUpdPush\r
+\r
+Fsp24UpdHeader2:\r
+ ; UPD structure is compliant with FSP spec 2.4\r
+ push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Code size sizeof(FSPT_UPD_COMMON) + 24\r
+ push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Code base sizeof(FSPT_UPD_COMMON) + 16\r
+ push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Microcode size sizeof(FSPT_UPD_COMMON) + 8\r
+ push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Microcode base sizeof(FSPT_UPD_COMMON) + 0\r
\r
ContinueAfterUpdPush:\r
;\r
cmp eax, 0\r
jnz TempRamInitExit\r
\r
- LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
+ LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
\r
TempRamInitExit:\r
- mov bl, al ; save al data in bl\r
- mov al, 07Fh ; API exit postcode 7f\r
- out 080h, al\r
- mov al, bl ; restore al data from bl\r
+ mov bl, al ; save al data in bl\r
+ mov al, 07Fh ; API exit postcode 7f\r
+ out 080h, al\r
+ mov al, bl ; restore al data from bl\r
\r
;\r
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
Intel FSP API definition from Intel Firmware Support Package External\r
Architecture Specification v2.0 - v2.2\r
\r
- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
///\r
typedef struct {\r
///\r
- /// Revision Revision of the structure is 1 for this version of the specification.\r
+ /// Revision of the structure is 1 for this version of the specification.\r
///\r
UINT8 Revision;\r
UINT8 Reserved[3];\r
///\r
- /// Length Length of the structure in bytes. The current value for this field is 32.\r
+ /// Length of the structure in bytes. The current value for this field is 32.\r
///\r
UINT32 Length;\r
///\r
UINT8 Reserved1[20];\r
} FSPT_ARCH_UPD;\r
\r
+///\r
+/// FSPT_ARCH2_UPD Configuration.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Revision of the structure is 2 for this version of the specification.\r
+ ///\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
+ ///\r
+ /// Length of the structure in bytes. The current value for this field is 32.\r
+ ///\r
+ UINT32 Length;\r
+ ///\r
+ /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
+ /// occurring during FSP execution.\r
+ ///\r
+ EFI_PHYSICAL_ADDRESS FspDebugHandler;\r
+ UINT8 Reserved1[16];\r
+} FSPT_ARCH2_UPD;\r
+\r
///\r
/// FSPM_ARCH_UPD Configuration.\r
///\r
UINT8 Reserved1[4];\r
} FSPM_ARCH_UPD;\r
\r
+///\r
+/// FSPM_ARCH2_UPD Configuration.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Revision of the structure is 3 for this version of the specification.\r
+ ///\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
+ ///\r
+ /// Length of the structure in bytes. The current value for this field is 64.\r
+ ///\r
+ UINT32 Length;\r
+ ///\r
+ /// Pointer to the temporary stack base address to be\r
+ /// consumed inside FspMemoryInit() API.\r
+ ///\r
+ EFI_PHYSICAL_ADDRESS StackBase;\r
+ ///\r
+ /// Temporary stack size to be consumed inside\r
+ /// FspMemoryInit() API.\r
+ ///\r
+ UINT64 StackSize;\r
+ ///\r
+ /// Size of memory to be reserved by FSP below "top\r
+ /// of low usable memory" for bootloader usage.\r
+ ///\r
+ UINT32 BootLoaderTolumSize;\r
+ ///\r
+ /// Current boot mode.\r
+ ///\r
+ UINT32 BootMode;\r
+ ///\r
+ /// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r
+ /// This value is only valid if Revision is >= 2.\r
+ ///\r
+ EFI_PHYSICAL_ADDRESS FspEventHandler;\r
+ UINT8 Reserved1[24];\r
+} FSPM_ARCH2_UPD;\r
+\r
+///\r
+/// FSPS_ARCH_UPD Configuration.\r
+///\r
typedef struct {\r
///\r
- /// Revision Revision of the structure is 1 for this version of the specification.\r
+ /// Revision of the structure is 1 for this version of the specification.\r
///\r
UINT8 Revision;\r
UINT8 Reserved[3];\r
///\r
- /// Length Length of the structure in bytes. The current value for this field is 32.\r
+ /// Length of the structure in bytes. The current value for this field is 32.\r
///\r
UINT32 Length;\r
///\r
UINT8 Reserved1[19];\r
} FSPS_ARCH_UPD;\r
\r
+///\r
+/// FSPS_ARCH2_UPD Configuration.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// Revision of the structure is 2 for this version of the specification.\r
+ ///\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
+ ///\r
+ /// Length of the structure in bytes. The current value for this field is 32.\r
+ ///\r
+ UINT32 Length;\r
+ ///\r
+ /// FspEventHandler Optional event handler for the bootloader to be informed of events\r
+ /// occurring during FSP execution.\r
+ ///\r
+ EFI_PHYSICAL_ADDRESS FspEventHandler;\r
+ UINT8 Reserved1[16];\r
+} FSPS_ARCH2_UPD;\r
+\r
///\r
/// FSPT_UPD_COMMON Configuration.\r
///\r
FSPT_ARCH_UPD FsptArchUpd;\r
} FSPT_UPD_COMMON_FSP22;\r
\r
+///\r
+/// FSPT_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// FSP_UPD_HEADER Configuration.\r
+ ///\r
+ FSP_UPD_HEADER FspUpdHeader;\r
+\r
+ ///\r
+ /// FSPT_ARCH2_UPD Configuration.\r
+ ///\r
+ FSPT_ARCH2_UPD FsptArchUpd;\r
+} FSPT_UPD_COMMON_FSP24;\r
+\r
///\r
/// FSPM_UPD_COMMON Configuration.\r
///\r
FSPM_ARCH_UPD FspmArchUpd;\r
} FSPM_UPD_COMMON;\r
\r
+///\r
+/// FSPM_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// FSP_UPD_HEADER Configuration.\r
+ ///\r
+ FSP_UPD_HEADER FspUpdHeader;\r
+ ///\r
+ /// FSPM_ARCH2_UPD Configuration.\r
+ ///\r
+ FSPM_ARCH2_UPD FspmArchUpd;\r
+} FSPM_UPD_COMMON_FSP24;\r
+\r
///\r
/// FSPS_UPD_COMMON Configuration.\r
///\r
FSPS_ARCH_UPD FspsArchUpd;\r
} FSPS_UPD_COMMON_FSP22;\r
\r
+///\r
+/// FSPS_UPD_COMMON Configuration for FSP spec. 2.4 and above.\r
+///\r
+typedef struct {\r
+ ///\r
+ /// FSP_UPD_HEADER Configuration.\r
+ ///\r
+ FSP_UPD_HEADER FspUpdHeader;\r
+\r
+ ///\r
+ /// FSPS_ARCH2_UPD Configuration.\r
+ ///\r
+ FSPS_ARCH2_UPD FspsArchUpd;\r
+} FSPS_UPD_COMMON_FSP24;\r
+\r
///\r
/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.\r
///\r
## @ GenCfgOpt.py\r
#\r
-# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG\r
UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE']\r
ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD']\r
+ ExcludedSpecificUpd1 = ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSPS_ARCH2_UPD']\r
\r
IncLines = []\r
if InputHeaderFile != '':\r
if Match:\r
StartIndex = Index - 1\r
Match = re.match("}\s([_A-Z0-9]+);", Line)\r
- if Match and (UpdRegionCheck[item] in Match.group(1) or UpdConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in Match.group(1)):\r
+ if Match and (UpdRegionCheck[item] in Match.group(1) or UpdConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in Match.group(1)) and (ExcludedSpecificUpd1[item] not in Match.group(1)):\r
EndIndex = Index\r
StructStart.append(StartIndex)\r
StructEnd.append(EndIndex)\r
\r
\r
def Usage():\r
- print ("GenCfgOpt Version 0.56")\r
+ print ("GenCfgOpt Version 0.57")\r
print ("Usage:")\r
print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir [-D Macros]")\r
print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile [-D Macros]")\r
projects / mirror_edk2.git / commitdiff