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1 | ;; @file\r | |
2 | ; This is the code that goes from real-mode to protected mode.\r | |
3 | ; It consumes the reset vector, configures the stack.\r | |
4 | ;\r | |
5 | ; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r | |
6 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | ;;\r | |
8 | \r | |
9 | ;\r | |
10 | ; Define assembler characteristics\r | |
11 | ;\r | |
12 | \r | |
13 | extern ASM_PFX(TempRamInitApi)\r | |
14 | \r | |
15 | SECTION .text\r | |
16 | \r | |
17 | %macro RET_ESI 0\r | |
18 | \r | |
19 | movd esi, mm7 ; restore ESP from MM7\r | |
20 | jmp esi\r | |
21 | \r | |
22 | %endmacro\r | |
23 | \r | |
24 | ;\r | |
25 | ; Perform early platform initialization\r | |
26 | ;\r | |
27 | global ASM_PFX(SecPlatformInit)\r | |
28 | ASM_PFX(SecPlatformInit):\r | |
29 | \r | |
30 | RET_ESI\r | |
31 | \r | |
32 | ;\r | |
33 | ; Protected mode portion initializes stack, configures cache, and calls C entry point\r | |
34 | ;\r | |
35 | \r | |
36 | ;----------------------------------------------------------------------------\r | |
37 | ;\r | |
38 | ; Procedure: ProtectedModeEntryPoint\r | |
39 | ;\r | |
40 | ; Input: Executing in 32 Bit Protected (flat) mode\r | |
41 | ; cs: 0-4GB\r | |
42 | ; ds: 0-4GB\r | |
43 | ; es: 0-4GB\r | |
44 | ; fs: 0-4GB\r | |
45 | ; gs: 0-4GB\r | |
46 | ; ss: 0-4GB\r | |
47 | ;\r | |
48 | ; Output: This function never returns\r | |
49 | ;\r | |
50 | ; Destroys:\r | |
51 | ; ecx\r | |
52 | ; edi\r | |
53 | ; esi\r | |
54 | ; esp\r | |
55 | ;\r | |
56 | ; Description:\r | |
57 | ; Perform any essential early platform initialisation\r | |
58 | ; Setup a stack\r | |
59 | ;\r | |
60 | ;----------------------------------------------------------------------------\r | |
61 | global ASM_PFX(ProtectedModeEntryPoint)\r | |
62 | ASM_PFX(ProtectedModeEntryPoint):\r | |
63 | ;\r | |
64 | ; Dummy function. Consume 2 API to make sure they can be linked.\r | |
65 | ;\r | |
66 | mov eax, ASM_PFX(TempRamInitApi)\r | |
67 | \r | |
68 | ; Should never return\r | |
69 | jmp $\r | |
70 | \r | |
71 | ;\r | |
72 | ; ROM-based Global-Descriptor Table for the PEI Phase\r | |
73 | ;\r | |
74 | align 16\r | |
75 | global ASM_PFX(BootGdtTable)\r | |
76 | \r | |
77 | ;\r | |
78 | ; GDT[0]: 0x00: Null entry, never used.\r | |
79 | ;\r | |
80 | NULL_SEL equ $ - GDT_BASE ; Selector [0]\r | |
81 | GDT_BASE:\r | |
82 | ASM_PFX(BootGdtTable): DD 0\r | |
83 | DD 0\r | |
84 | ;\r | |
85 | ; Linear code segment descriptor\r | |
86 | ;\r | |
87 | LINEAR_CODE_SEL equ $ - GDT_BASE ; Selector [0x8]\r | |
88 | DW 0FFFFh ; limit 0xFFFF\r | |
89 | DW 0 ; base 0\r | |
90 | DB 0\r | |
91 | DB 09Bh ; present, ring 0, data, expand-up, not-writable\r | |
92 | DB 0CFh ; page-granular, 32-bit\r | |
93 | DB 0\r | |
94 | ;\r | |
95 | ; System data segment descriptor\r | |
96 | ;\r | |
97 | SYS_DATA_SEL equ $ - GDT_BASE ; Selector [0x10]\r | |
98 | DW 0FFFFh ; limit 0xFFFF\r | |
99 | DW 0 ; base 0\r | |
100 | DB 0\r | |
101 | DB 093h ; present, ring 0, data, expand-up, not-writable\r | |
102 | DB 0CFh ; page-granular, 32-bit\r | |
103 | DB 0\r | |
104 | \r | |
105 | GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes\r | |
106 | \r | |
107 | ;\r | |
108 | ; GDT Descriptor\r | |
109 | ;\r | |
110 | GdtDesc: ; GDT descriptor\r | |
111 | DW GDT_SIZE - 1 ; GDT limit\r | |
112 | DD GDT_BASE ; GDT base address\r | |
113 | \r | |
114 | global ASM_PFX(ProtectedModeEntryLinearAddress)\r | |
115 | global ASM_PFX(ProtectedModeEntryLinearOffset)\r | |
116 | \r | |
117 | ASM_PFX(ProtectedModeEntryLinearAddress):\r | |
118 | ASM_PFX(ProtectedModeEntryLinearOffset):\r | |
119 | DD ASM_PFX(ProtectedModeEntryPoint) ; Offset of our 32 bit code\r | |
120 | DW LINEAR_CODE_SEL\r | |
121 | \r |