Fix various typos in IntelFsp2Pkg.
Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
\r
;\r
; Pass BFV into the PEI Core\r
- ; It uses relative address to calucate the actual boot FV base\r
+ ; It uses relative address to calculate the actual boot FV base\r
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and\r
- ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,\r
+ ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,\r
; they are different. The code below can handle both cases.\r
;\r
call ASM_PFX(AsmGetFspBaseAddress)\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Abstract:\r
fldcw [ASM_PFX(mFpuControlWord)]\r
\r
;\r
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
; whether the processor supports SSE instruction.\r
;\r
mov eax, 1\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Abstract:\r
fldcw [FpuControlWord]\r
\r
;\r
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
; whether the processor supports SSE instruction.\r
;\r
mov eax, 1\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Abstract:\r
mov esp, eax ; From now, esp is pointed to permanent memory\r
\r
;\r
- ; Fixup the ebp point to permenent memory\r
+ ; Fixup the ebp point to permanent memory\r
;\r
mov eax, ebp\r
sub eax, ebx\r
/** @file\r
\r
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
SerialPortInitialize ();\r
\r
//\r
- // Ensure the golbal data pointer is valid\r
+ // Ensure the global data pointer is valid\r
//\r
ASSERT (GetFspGlobalDataPointer () == PeiFspData);\r
\r
// |-------------------|---->\r
// | |\r
// | |\r
- // | Heap | PeiTemporayRamSize\r
+ // | Heap | PeiTemporaryRamSize\r
// | |\r
// | |\r
// |-------------------|----> TempRamBase\r
; Reset Vector Data structure\r
; This structure is located at 0xFFFFFFC0\r
;\r
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
;;\r
;\r
; Jmp Rel16 instruction\r
; Use machine code directly in case of the assembler optimization\r
- ; SEC entry point relatvie address will be fixed up by some build tool.\r
+ ; SEC entry point relative address will be fixed up by some build tool.\r
;\r
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in\r
; SecEntry.asm\r
Intel FSP API definition from Intel Firmware Support Package External\r
Architecture Specification v2.0.\r
\r
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
each FSP release.\r
After FspMemInit completes its execution, it passes the pointer to the HobList and\r
returns to the boot loader from where it was called. BootLoader is responsible to\r
- migrate it's stack and data to Memory.\r
+ migrate its stack and data to Memory.\r
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to\r
complete the silicon initialization and provides bootloader an opportunity to get\r
control after system memory is available and before the temporary RAM is torn down.\r
\r
- @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data sructure.\r
+ @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure.\r
@param[out] HobListPtr Pointer to receive the address of the HOB list.\r
\r
@retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
@retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
@retval EFI_DEVICE_ERROR FSP initialization failed.\r
- @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3.\r
+ @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
**/\r
typedef\r
EFI_STATUS\r
/** @file\r
\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
);\r
\r
/**\r
- This function check the signture of UPD.\r
+ This function check the signature of UPD.\r
\r
@param[in] ApiIdx Internal index of the FSP API.\r
@param[in] ApiParam Parameter of the FSP API.\r
/** @file\r
\r
- Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
@param[in] BaseAddress Base address.\r
@param[in] Size Size.\r
\r
- @retval Zero Alligned.\r
- @retval Non-Zero Not alligned.\r
+ @retval Zero Aligned.\r
+ @retval Non-Zero Not aligned.\r
\r
**/\r
UINT32\r
}\r
\r
//\r
- // Compute inital power of 2 size to return\r
+ // Compute initial power of 2 size to return\r
//\r
Result = GetPowerOfTwo64(MemoryLength);\r
\r
@param[in] BaseAddress Base address.\r
@param[in] Size Size.\r
\r
- @retval Zero Alligned.\r
- @retval Non-Zero Not alligned.\r
+ @retval Zero Aligned.\r
+ @retval Non-Zero Not aligned.\r
\r
**/\r
UINT32\r
}\r
\r
/**\r
- Convert an UINT32 value into HEX string sepcified by Buffer.\r
+ Convert an UINT32 value into HEX string specified by Buffer.\r
\r
@param Value The HEX value to convert to string\r
@param Buffer The pointer to the target buffer to be filled with HEX string\r
\r
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"\r
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of\r
- PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if\r
- DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then\r
+ PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if\r
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then\r
CpuDeadLoop() is called. If neither of these bits are set, then this function\r
returns immediately after the message is printed to the debug output device.\r
DebugAssert() must actively prevent recursion. If DebugAssert() is called while\r
\r
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"\r
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of\r
- PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if\r
- DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then\r
+ PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if\r
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then\r
CpuDeadLoop() is called. If neither of these bits are set, then this function\r
returns immediately after the message is printed to the debug output device.\r
DebugAssert() must actively prevent recursion. If DebugAssert() is called while\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Abstract:\r
;\r
-; Switch the stack from temporary memory to permenent memory.\r
+; Switch the stack from temporary memory to permanent memory.\r
;\r
;------------------------------------------------------------------------------\r
\r
; This is the code that goes from real-mode to protected mode.\r
; It consumes the reset vector, configures the stack.\r
;\r
-; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;;\r
\r
; esp\r
;\r
; Description:\r
-; Perform any essential early platform initilaisation\r
+; Perform any essential early platform initialisation\r
; Setup a stack\r
;\r
;----------------------------------------------------------------------------\r
/** @file\r
Null instance of Platform Sec Lib.\r
\r
- Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#include <Library/FspCommonLib.h>\r
\r
/**\r
- This function check the signture of UPD.\r
+ This function check the signature of UPD.\r
\r
@param[in] ApiIdx Internal index of the FSP API.\r
@param[in] ApiParam Parameter of the FSP API.\r
Offset = 0\r
else:\r
if DscLine.startswith('!'):\r
- print("ERROR: Unrecoginized directive for line '%s'" % DscLine)\r
+ print("ERROR: Unrecognized directive for line '%s'" % DscLine)\r
raise SystemExit\r
if not Handle:\r
continue\r
#\r
def createDicts (self, fvDir, fvNames):\r
#\r
- # If the fvDir is not a dirctory, then raise an exception\r
+ # If the fvDir is not a directory, then raise an exception\r
#\r
if not os.path.isdir(fvDir):\r
raise Exception ("'%s' is not a valid directory!" % FvDir)\r
```@Bsf NAME:{Variable 1} TYPE:{Combo}```\r
\r
There is a special **None** type that puts the variable in the **StructDef**\r
-region of the BSF, but doesn?t put it in any **Page** section. This makes the\r
+region of the BSF, but doesn't put it in any **Page** section. This makes the\r
variable visible to BCT, but not to the end user.\r
\r
###HELP\r
\r
The example used contains Windows batch script %VARIABLES%.\r
\r
-#FvFileBaseNames (Argument 2: 0ptional Part 1)\r
+#FvFileBaseNames (Argument 2: Optional Part 1)\r
The firmware volume file base names (**_FvFileBaseNames_**) are the independent\r
Fv?s that are to be patched within the FD. (0 or more in the form\r
**FVFILEBASENAME:**) The colon **:** is used for delimiting the single\r
projects / mirror_edk2.git / commitdiff