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1/** @file\r
2 EFI PCI IO protocol functions declaration for PCI Bus module.\r
3\r
4Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
5SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
7**/\r
8\r
9#ifndef _EFI_PCI_IO_PROTOCOL_H_\r
10#define _EFI_PCI_IO_PROTOCOL_H_\r
11\r
12/**\r
13 Initializes a PCI I/O Instance.\r
14\r
15 @param PciIoDevice Pci device instance.\r
16\r
17**/\r
18VOID\r
19InitializePciIoInstance (\r
20 IN PCI_IO_DEVICE *PciIoDevice\r
21 );\r
22\r
23/**\r
24 Verifies access to a PCI Base Address Register (BAR).\r
25\r
26 @param PciIoDevice Pci device instance.\r
27 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
28 base address for the memory or I/O operation to perform.\r
29 @param Type Operation type could be memory or I/O.\r
30 @param Width Signifies the width of the memory or I/O operations.\r
31 @param Count The number of memory or I/O operations to perform.\r
32 @param Offset The offset within the PCI configuration space for the PCI controller.\r
33\r
34 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
35 @retval EFI_SUCCESS Successfully verified.\r
36\r
37**/\r
38EFI_STATUS\r
39PciIoVerifyBarAccess (\r
40 IN PCI_IO_DEVICE *PciIoDevice,\r
41 IN UINT8 BarIndex,\r
42 IN PCI_BAR_TYPE Type,\r
43 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
44 IN IN UINTN Count,\r
45 IN UINT64 *Offset\r
46 );\r
47\r
48/**\r
49 Verifies access to a PCI Configuration Header.\r
50\r
51 @param PciIoDevice Pci device instance.\r
52 @param Width Signifies the width of the memory or I/O operations.\r
53 @param Count The number of memory or I/O operations to perform.\r
54 @param Offset The offset within the PCI configuration space for the PCI controller.\r
55\r
56 @retval EFI_INVALID_PARAMETER Invalid Width\r
57 @retval EFI_UNSUPPORTED Offset overflowed.\r
58 @retval EFI_SUCCESS Successfully verified.\r
59\r
60**/\r
61EFI_STATUS\r
62PciIoVerifyConfigAccess (\r
63 IN PCI_IO_DEVICE *PciIoDevice,\r
64 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
65 IN UINTN Count,\r
66 IN UINT64 *Offset\r
67 );\r
68\r
69/**\r
70 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
71 satisfied or after a defined duration.\r
72\r
73 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
74 @param Width Signifies the width of the memory or I/O operations.\r
75 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
76 base address for the memory operation to perform.\r
77 @param Offset The offset within the selected BAR to start the memory operation.\r
78 @param Mask Mask used for the polling criteria.\r
79 @param Value The comparison value used for the polling exit criteria.\r
80 @param Delay The number of 100 ns units to poll.\r
81 @param Result Pointer to the last value read from the memory location.\r
82\r
83 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
84 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
85 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
86 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
87 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
88 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
89\r
90**/\r
91EFI_STATUS\r
92EFIAPI\r
93PciIoPollMem (\r
94 IN EFI_PCI_IO_PROTOCOL *This,\r
95 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
96 IN UINT8 BarIndex,\r
97 IN UINT64 Offset,\r
98 IN UINT64 Mask,\r
99 IN UINT64 Value,\r
100 IN UINT64 Delay,\r
101 OUT UINT64 *Result\r
102 );\r
103\r
104/**\r
105 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
106 satisfied or after a defined duration.\r
107\r
108 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
109 @param Width Signifies the width of the memory or I/O operations.\r
110 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
111 base address for the memory operation to perform.\r
112 @param Offset The offset within the selected BAR to start the memory operation.\r
113 @param Mask Mask used for the polling criteria.\r
114 @param Value The comparison value used for the polling exit criteria.\r
115 @param Delay The number of 100 ns units to poll.\r
116 @param Result Pointer to the last value read from the memory location.\r
117\r
118 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
119 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
120 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
121 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
122 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
123 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
124\r
125**/\r
126EFI_STATUS\r
127EFIAPI\r
128PciIoPollIo (\r
129 IN EFI_PCI_IO_PROTOCOL *This,\r
130 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
131 IN UINT8 BarIndex,\r
132 IN UINT64 Offset,\r
133 IN UINT64 Mask,\r
134 IN UINT64 Value,\r
135 IN UINT64 Delay,\r
136 OUT UINT64 *Result\r
137 );\r
138\r
139/**\r
140 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
141\r
142 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
143 @param Width Signifies the width of the memory or I/O operations.\r
144 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
145 base address for the memory or I/O operation to perform.\r
146 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
147 @param Count The number of memory or I/O operations to perform.\r
148 @param Buffer For read operations, the destination buffer to store the results. For write\r
149 operations, the source buffer to write data from.\r
150\r
151 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
152 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
153 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
154 valid for the PCI BAR specified by BarIndex.\r
155 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
156 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
157\r
158**/\r
159EFI_STATUS\r
160EFIAPI\r
161PciIoMemRead (\r
162 IN EFI_PCI_IO_PROTOCOL *This,\r
163 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
164 IN UINT8 BarIndex,\r
165 IN UINT64 Offset,\r
166 IN UINTN Count,\r
167 IN OUT VOID *Buffer\r
168 );\r
169\r
170/**\r
171 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
172\r
173 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
174 @param Width Signifies the width of the memory or I/O operations.\r
175 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
176 base address for the memory or I/O operation to perform.\r
177 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
178 @param Count The number of memory or I/O operations to perform.\r
179 @param Buffer For read operations, the destination buffer to store the results. For write\r
180 operations, the source buffer to write data from.\r
181\r
182 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
183 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
184 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
185 valid for the PCI BAR specified by BarIndex.\r
186 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
187 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
188\r
189**/\r
190EFI_STATUS\r
191EFIAPI\r
192PciIoMemWrite (\r
193 IN EFI_PCI_IO_PROTOCOL *This,\r
194 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
195 IN UINT8 BarIndex,\r
196 IN UINT64 Offset,\r
197 IN UINTN Count,\r
198 IN OUT VOID *Buffer\r
199 );\r
200\r
201/**\r
202 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
203\r
204 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
205 @param Width Signifies the width of the memory or I/O operations.\r
206 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
207 base address for the memory or I/O operation to perform.\r
208 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
209 @param Count The number of memory or I/O operations to perform.\r
210 @param Buffer For read operations, the destination buffer to store the results. For write\r
211 operations, the source buffer to write data from.\r
212\r
213 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
214 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
215 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
216 valid for the PCI BAR specified by BarIndex.\r
217 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
218 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
219\r
220**/\r
221EFI_STATUS\r
222EFIAPI\r
223PciIoIoRead (\r
224 IN EFI_PCI_IO_PROTOCOL *This,\r
225 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
226 IN UINT8 BarIndex,\r
227 IN UINT64 Offset,\r
228 IN UINTN Count,\r
229 IN OUT VOID *Buffer\r
230 );\r
231\r
232/**\r
233 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
234\r
235 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
236 @param Width Signifies the width of the memory or I/O operations.\r
237 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
238 base address for the memory or I/O operation to perform.\r
239 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
240 @param Count The number of memory or I/O operations to perform.\r
241 @param Buffer For read operations, the destination buffer to store the results. For write\r
242 operations, the source buffer to write data from.\r
243\r
244 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
245 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
246 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
247 valid for the PCI BAR specified by BarIndex.\r
248 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
249 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
250\r
251**/\r
252EFI_STATUS\r
253EFIAPI\r
254PciIoIoWrite (\r
255 IN EFI_PCI_IO_PROTOCOL *This,\r
256 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
257 IN UINT8 BarIndex,\r
258 IN UINT64 Offset,\r
259 IN UINTN Count,\r
260 IN OUT VOID *Buffer\r
261 );\r
262\r
263/**\r
264 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
265\r
266 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
267 @param Width Signifies the width of the memory operations.\r
268 @param Offset The offset within the PCI configuration space for the PCI controller.\r
269 @param Count The number of PCI configuration operations to perform.\r
270 @param Buffer For read operations, the destination buffer to store the results. For write\r
271 operations, the source buffer to write data from.\r
272\r
273\r
274 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
275 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
276 valid for the PCI configuration header of the PCI controller.\r
277 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
278 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
279\r
280**/\r
281EFI_STATUS\r
282EFIAPI\r
283PciIoConfigRead (\r
284 IN EFI_PCI_IO_PROTOCOL *This,\r
285 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
286 IN UINT32 Offset,\r
287 IN UINTN Count,\r
288 IN OUT VOID *Buffer\r
289 );\r
290\r
291/**\r
292 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
293\r
294 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
295 @param Width Signifies the width of the memory operations.\r
296 @param Offset The offset within the PCI configuration space for the PCI controller.\r
297 @param Count The number of PCI configuration operations to perform.\r
298 @param Buffer For read operations, the destination buffer to store the results. For write\r
299 operations, the source buffer to write data from.\r
300\r
301\r
302 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
303 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
304 valid for the PCI configuration header of the PCI controller.\r
305 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
306 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
307\r
308**/\r
309EFI_STATUS\r
310EFIAPI\r
311PciIoConfigWrite (\r
312 IN EFI_PCI_IO_PROTOCOL *This,\r
313 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
314 IN UINT32 Offset,\r
315 IN UINTN Count,\r
316 IN OUT VOID *Buffer\r
317 );\r
318\r
319/**\r
320 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
321 memory space.\r
322\r
323 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
324 @param Width Signifies the width of the memory operations.\r
325 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
326 base address for the memory operation to perform.\r
327 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
328 start the memory writes for the copy operation.\r
329 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
330 base address for the memory operation to perform.\r
331 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
332 the memory reads for the copy operation.\r
333 @param Count The number of memory operations to perform. Bytes moved is Width\r
334 size * Count, starting at DestOffset and SrcOffset.\r
335\r
336 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
337 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
338 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
339 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
340 is not valid for the PCI BAR specified by DestBarIndex.\r
341 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
342 not valid for the PCI BAR specified by SrcBarIndex.\r
343 @retval EFI_INVALID_PARAMETER Width is invalid.\r
344 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
345\r
346**/\r
347EFI_STATUS\r
348EFIAPI\r
349PciIoCopyMem (\r
350 IN EFI_PCI_IO_PROTOCOL *This,\r
351 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
352 IN UINT8 DestBarIndex,\r
353 IN UINT64 DestOffset,\r
354 IN UINT8 SrcBarIndex,\r
355 IN UINT64 SrcOffset,\r
356 IN UINTN Count\r
357 );\r
358\r
359/**\r
360 Provides the PCI controller-specific addresses needed to access system memory.\r
361\r
362 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
363 @param Operation Indicates if the bus master is going to read or write to system memory.\r
364 @param HostAddress The system memory address to map to the PCI controller.\r
365 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
366 that were mapped.\r
367 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
368 access the hosts HostAddress.\r
369 @param Mapping A resulting value to pass to Unmap().\r
370\r
371 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
372 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
373 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
374 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
375 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
376\r
377**/\r
378EFI_STATUS\r
379EFIAPI\r
380PciIoMap (\r
381 IN EFI_PCI_IO_PROTOCOL *This,\r
382 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
383 IN VOID *HostAddress,\r
384 IN OUT UINTN *NumberOfBytes,\r
385 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
386 OUT VOID **Mapping\r
387 );\r
388\r
389/**\r
390 Completes the Map() operation and releases any corresponding resources.\r
391\r
392 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
393 @param Mapping The mapping value returned from Map().\r
394\r
395 @retval EFI_SUCCESS The range was unmapped.\r
396 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
397\r
398**/\r
399EFI_STATUS\r
400EFIAPI\r
401PciIoUnmap (\r
402 IN EFI_PCI_IO_PROTOCOL *This,\r
403 IN VOID *Mapping\r
404 );\r
405\r
406/**\r
407 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
408 or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
409\r
410 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
411 @param Type This parameter is not used and must be ignored.\r
412 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
413 EfiRuntimeServicesData.\r
414 @param Pages The number of pages to allocate.\r
415 @param HostAddress A pointer to store the base system memory address of the\r
416 allocated range.\r
417 @param Attributes The requested bit mask of attributes for the allocated range.\r
418\r
419 @retval EFI_SUCCESS The requested memory pages were allocated.\r
420 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
421 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r
422 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
423 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
424\r
425**/\r
426EFI_STATUS\r
427EFIAPI\r
428PciIoAllocateBuffer (\r
429 IN EFI_PCI_IO_PROTOCOL *This,\r
430 IN EFI_ALLOCATE_TYPE Type,\r
431 IN EFI_MEMORY_TYPE MemoryType,\r
432 IN UINTN Pages,\r
433 OUT VOID **HostAddress,\r
434 IN UINT64 Attributes\r
435 );\r
436\r
437/**\r
438 Frees memory that was allocated with AllocateBuffer().\r
439\r
440 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
441 @param Pages The number of pages to free.\r
442 @param HostAddress The base system memory address of the allocated range.\r
443\r
444 @retval EFI_SUCCESS The requested memory pages were freed.\r
445 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
446 was not allocated with AllocateBuffer().\r
447\r
448**/\r
449EFI_STATUS\r
450EFIAPI\r
451PciIoFreeBuffer (\r
452 IN EFI_PCI_IO_PROTOCOL *This,\r
453 IN UINTN Pages,\r
454 IN VOID *HostAddress\r
455 );\r
456\r
457/**\r
458 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
459\r
460 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
461\r
462 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
463 bridge to system memory.\r
464 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
465 host bridge due to a hardware error.\r
466\r
467**/\r
468EFI_STATUS\r
469EFIAPI\r
470PciIoFlush (\r
471 IN EFI_PCI_IO_PROTOCOL *This\r
472 );\r
473\r
474/**\r
475 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
476\r
477 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
478 @param SegmentNumber The PCI controller's current PCI segment number.\r
479 @param BusNumber The PCI controller's current PCI bus number.\r
480 @param DeviceNumber The PCI controller's current PCI device number.\r
481 @param FunctionNumber The PCI controller's current PCI function number.\r
482\r
483 @retval EFI_SUCCESS The PCI controller location was returned.\r
484 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
485\r
486**/\r
487EFI_STATUS\r
488EFIAPI\r
489PciIoGetLocation (\r
490 IN EFI_PCI_IO_PROTOCOL *This,\r
491 OUT UINTN *Segment,\r
492 OUT UINTN *Bus,\r
493 OUT UINTN *Device,\r
494 OUT UINTN *Function\r
495 );\r
496\r
497/**\r
498 Check BAR type for PCI resource.\r
499\r
500 @param PciIoDevice PCI device instance.\r
501 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
502 base address for the memory or I/O operation to perform.\r
503 @param BarType Memory or I/O.\r
504\r
505 @retval TRUE Pci device's bar type is same with input BarType.\r
506 @retval TRUE Pci device's bar type is not same with input BarType.\r
507\r
508**/\r
509BOOLEAN\r
510CheckBarType (\r
511 IN PCI_IO_DEVICE *PciIoDevice,\r
512 IN UINT8 BarIndex,\r
513 IN PCI_BAR_TYPE BarType\r
514 );\r
515\r
516/**\r
517 Set/Disable new attributes to a Root Bridge.\r
518\r
519 @param PciIoDevice Pci device instance.\r
520 @param Attributes New attribute want to be set.\r
521 @param Operation Set or Disable.\r
522\r
523 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
524 @retval EFI_SUCCESS Successfully set new attributes.\r
525\r
526**/\r
527EFI_STATUS\r
528ModifyRootBridgeAttributes (\r
529 IN PCI_IO_DEVICE *PciIoDevice,\r
530 IN UINT64 Attributes,\r
531 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
532 );\r
533\r
534/**\r
535 Check whether this device can be enable/disable to snoop.\r
536\r
537 @param PciIoDevice Pci device instance.\r
538 @param Operation Enable/Disable.\r
539\r
540 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
541 @retval EFI_SUCCESS Snoop can be supported.\r
542\r
543**/\r
544EFI_STATUS\r
545SupportPaletteSnoopAttributes (\r
546 IN PCI_IO_DEVICE *PciIoDevice,\r
547 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
548 );\r
549\r
550/**\r
551 Performs an operation on the attributes that this PCI controller supports. The operations include\r
552 getting the set of supported attributes, retrieving the current attributes, setting the current\r
553 attributes, enabling attributes, and disabling attributes.\r
554\r
555 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
556 @param Operation The operation to perform on the attributes for this PCI controller.\r
557 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
558 operations.\r
559 @param Result A pointer to the result mask of attributes that are returned for the Get\r
560 and Supported operations.\r
561\r
562 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
563 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
564 @retval EFI_UNSUPPORTED one or more of the bits set in\r
565 Attributes are not supported by this PCI controller or one of\r
566 its parent bridges when Operation is Set, Enable or Disable.\r
567\r
568**/\r
569EFI_STATUS\r
570EFIAPI\r
571PciIoAttributes (\r
572 IN EFI_PCI_IO_PROTOCOL * This,\r
573 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
574 IN UINT64 Attributes,\r
575 OUT UINT64 *Result OPTIONAL\r
576 );\r
577\r
578/**\r
579 Gets the attributes that this PCI controller supports setting on a BAR using\r
580 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
581\r
582 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
583 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
584 base address for resource range. The legal range for this field is 0..5.\r
585 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
586 setting for this BAR with SetBarAttributes().\r
587 @param Resources A pointer to the resource descriptors that describe the current\r
588 configuration of this BAR of the PCI controller.\r
589\r
590 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
591 controller supports are returned in Supports. If Resources\r
592 is not NULL, then the resource descriptors that the PCI\r
593 controller is currently using are returned in Resources.\r
594 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
595 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
596 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
597 Resources.\r
598\r
599**/\r
600EFI_STATUS\r
601EFIAPI\r
602PciIoGetBarAttributes (\r
603 IN EFI_PCI_IO_PROTOCOL * This,\r
604 IN UINT8 BarIndex,\r
605 OUT UINT64 *Supports, OPTIONAL\r
606 OUT VOID **Resources OPTIONAL\r
607 );\r
608\r
609/**\r
610 Sets the attributes for a range of a BAR on a PCI controller.\r
611\r
612 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
613 @param Attributes The mask of attributes to set for the resource range specified by\r
614 BarIndex, Offset, and Length.\r
615 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
616 base address for resource range. The legal range for this field is 0..5.\r
617 @param Offset A pointer to the BAR relative base address of the resource range to be\r
618 modified by the attributes specified by Attributes.\r
619 @param Length A pointer to the length of the resource range to be modified by the\r
620 attributes specified by Attributes.\r
621\r
622 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
623 range specified by BarIndex, Offset, and Length were\r
624 set on the PCI controller, and the actual resource range is returned\r
625 in Offset and Length.\r
626 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
627 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
628 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
629 resource range specified by BarIndex, Offset, and\r
630 Length.\r
631\r
632**/\r
633EFI_STATUS\r
634EFIAPI\r
635PciIoSetBarAttributes (\r
636 IN EFI_PCI_IO_PROTOCOL *This,\r
637 IN UINT64 Attributes,\r
638 IN UINT8 BarIndex,\r
639 IN OUT UINT64 *Offset,\r
640 IN OUT UINT64 *Length\r
641 );\r
642\r
643\r
644/**\r
645 Test whether two Pci devices has same parent bridge.\r
646\r
647 @param PciDevice1 The first pci device for testing.\r
648 @param PciDevice2 The second pci device for testing.\r
649\r
650 @retval TRUE Two Pci device has the same parent bridge.\r
651 @retval FALSE Two Pci device has not the same parent bridge.\r
652\r
653**/\r
654BOOLEAN\r
655PciDevicesOnTheSamePath (\r
656 IN PCI_IO_DEVICE *PciDevice1,\r
657 IN PCI_IO_DEVICE *PciDevice2\r
658 );\r
659\r
660#endif\r