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MdePkg: Add definitions for the SPI protocols introduced in PI 1.6.
[mirror_edk2.git] / MdePkg / Include / Protocol / DebugSupport.h
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1/** @file\r
2 DebugSupport protocol and supporting definitions as defined in the UEFI2.4\r
3 specification.\r
4\r
5 The DebugSupport protocol is used by source level debuggers to abstract the\r
6 processor and handle context save and restore operations.\r
7\r
8Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
9Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
10\r
11This program and the accompanying materials are licensed and made available under \r
12the terms and conditions of the BSD License that accompanies this distribution. \r
13The full text of the license may be found at\r
14http://opensource.org/licenses/bsd-license.php. \r
15 \r
16THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
17WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
18\r
19**/\r
20\r
21#ifndef __DEBUG_SUPPORT_H__\r
22#define __DEBUG_SUPPORT_H__\r
23\r
24#include <IndustryStandard/PeImage.h>\r
25\r
26typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r
27\r
28///\r
29/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.\r
30///\r
31#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r
32 { \\r
33 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r
34 }\r
35\r
36///\r
37/// Processor exception to be hooked.\r
38/// All exception types for IA32, X64, Itanium and EBC processors are defined.\r
39///\r
40typedef INTN EFI_EXCEPTION_TYPE;\r
41\r
42///\r
43/// IA-32 processor exception types.\r
44///\r
45#define EXCEPT_IA32_DIVIDE_ERROR 0\r
46#define EXCEPT_IA32_DEBUG 1\r
47#define EXCEPT_IA32_NMI 2\r
48#define EXCEPT_IA32_BREAKPOINT 3\r
49#define EXCEPT_IA32_OVERFLOW 4\r
50#define EXCEPT_IA32_BOUND 5\r
51#define EXCEPT_IA32_INVALID_OPCODE 6\r
52#define EXCEPT_IA32_DOUBLE_FAULT 8\r
53#define EXCEPT_IA32_INVALID_TSS 10\r
54#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
55#define EXCEPT_IA32_STACK_FAULT 12\r
56#define EXCEPT_IA32_GP_FAULT 13\r
57#define EXCEPT_IA32_PAGE_FAULT 14\r
58#define EXCEPT_IA32_FP_ERROR 16\r
59#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
60#define EXCEPT_IA32_MACHINE_CHECK 18\r
61#define EXCEPT_IA32_SIMD 19\r
62\r
63///\r
64/// FXSAVE_STATE.\r
65/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
66///\r
67typedef struct {\r
68 UINT16 Fcw;\r
69 UINT16 Fsw;\r
70 UINT16 Ftw;\r
71 UINT16 Opcode;\r
72 UINT32 Eip;\r
73 UINT16 Cs;\r
74 UINT16 Reserved1;\r
75 UINT32 DataOffset;\r
76 UINT16 Ds;\r
77 UINT8 Reserved2[10];\r
78 UINT8 St0Mm0[10], Reserved3[6];\r
79 UINT8 St1Mm1[10], Reserved4[6];\r
80 UINT8 St2Mm2[10], Reserved5[6];\r
81 UINT8 St3Mm3[10], Reserved6[6];\r
82 UINT8 St4Mm4[10], Reserved7[6];\r
83 UINT8 St5Mm5[10], Reserved8[6];\r
84 UINT8 St6Mm6[10], Reserved9[6];\r
85 UINT8 St7Mm7[10], Reserved10[6];\r
86 UINT8 Xmm0[16];\r
87 UINT8 Xmm1[16];\r
88 UINT8 Xmm2[16];\r
89 UINT8 Xmm3[16];\r
90 UINT8 Xmm4[16];\r
91 UINT8 Xmm5[16];\r
92 UINT8 Xmm6[16];\r
93 UINT8 Xmm7[16];\r
94 UINT8 Reserved11[14 * 16];\r
95} EFI_FX_SAVE_STATE_IA32;\r
96\r
97///\r
98/// IA-32 processor context definition.\r
99///\r
100typedef struct {\r
101 UINT32 ExceptionData;\r
102 EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
103 UINT32 Dr0;\r
104 UINT32 Dr1;\r
105 UINT32 Dr2;\r
106 UINT32 Dr3;\r
107 UINT32 Dr6;\r
108 UINT32 Dr7;\r
109 UINT32 Cr0;\r
110 UINT32 Cr1; /* Reserved */\r
111 UINT32 Cr2;\r
112 UINT32 Cr3;\r
113 UINT32 Cr4;\r
114 UINT32 Eflags;\r
115 UINT32 Ldtr;\r
116 UINT32 Tr;\r
117 UINT32 Gdtr[2];\r
118 UINT32 Idtr[2];\r
119 UINT32 Eip;\r
120 UINT32 Gs;\r
121 UINT32 Fs;\r
122 UINT32 Es;\r
123 UINT32 Ds;\r
124 UINT32 Cs;\r
125 UINT32 Ss;\r
126 UINT32 Edi;\r
127 UINT32 Esi;\r
128 UINT32 Ebp;\r
129 UINT32 Esp;\r
130 UINT32 Ebx;\r
131 UINT32 Edx;\r
132 UINT32 Ecx;\r
133 UINT32 Eax;\r
134} EFI_SYSTEM_CONTEXT_IA32;\r
135\r
136///\r
137/// x64 processor exception types.\r
138///\r
139#define EXCEPT_X64_DIVIDE_ERROR 0\r
140#define EXCEPT_X64_DEBUG 1\r
141#define EXCEPT_X64_NMI 2\r
142#define EXCEPT_X64_BREAKPOINT 3\r
143#define EXCEPT_X64_OVERFLOW 4\r
144#define EXCEPT_X64_BOUND 5\r
145#define EXCEPT_X64_INVALID_OPCODE 6\r
146#define EXCEPT_X64_DOUBLE_FAULT 8\r
147#define EXCEPT_X64_INVALID_TSS 10\r
148#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
149#define EXCEPT_X64_STACK_FAULT 12\r
150#define EXCEPT_X64_GP_FAULT 13\r
151#define EXCEPT_X64_PAGE_FAULT 14\r
152#define EXCEPT_X64_FP_ERROR 16\r
153#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
154#define EXCEPT_X64_MACHINE_CHECK 18\r
155#define EXCEPT_X64_SIMD 19\r
156\r
157///\r
158/// FXSAVE_STATE.\r
159/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
160///\r
161typedef struct {\r
162 UINT16 Fcw;\r
163 UINT16 Fsw;\r
164 UINT16 Ftw;\r
165 UINT16 Opcode;\r
166 UINT64 Rip;\r
167 UINT64 DataOffset;\r
168 UINT8 Reserved1[8];\r
169 UINT8 St0Mm0[10], Reserved2[6];\r
170 UINT8 St1Mm1[10], Reserved3[6];\r
171 UINT8 St2Mm2[10], Reserved4[6];\r
172 UINT8 St3Mm3[10], Reserved5[6];\r
173 UINT8 St4Mm4[10], Reserved6[6];\r
174 UINT8 St5Mm5[10], Reserved7[6];\r
175 UINT8 St6Mm6[10], Reserved8[6];\r
176 UINT8 St7Mm7[10], Reserved9[6];\r
177 UINT8 Xmm0[16];\r
178 UINT8 Xmm1[16];\r
179 UINT8 Xmm2[16];\r
180 UINT8 Xmm3[16];\r
181 UINT8 Xmm4[16];\r
182 UINT8 Xmm5[16];\r
183 UINT8 Xmm6[16];\r
184 UINT8 Xmm7[16];\r
185 //\r
186 // NOTE: UEFI 2.0 spec definition as follows. \r
187 //\r
188 UINT8 Reserved11[14 * 16];\r
189} EFI_FX_SAVE_STATE_X64;\r
190\r
191///\r
192/// x64 processor context definition.\r
193///\r
194typedef struct {\r
195 UINT64 ExceptionData;\r
196 EFI_FX_SAVE_STATE_X64 FxSaveState;\r
197 UINT64 Dr0;\r
198 UINT64 Dr1;\r
199 UINT64 Dr2;\r
200 UINT64 Dr3;\r
201 UINT64 Dr6;\r
202 UINT64 Dr7;\r
203 UINT64 Cr0;\r
204 UINT64 Cr1; /* Reserved */\r
205 UINT64 Cr2;\r
206 UINT64 Cr3;\r
207 UINT64 Cr4;\r
208 UINT64 Cr8;\r
209 UINT64 Rflags;\r
210 UINT64 Ldtr;\r
211 UINT64 Tr;\r
212 UINT64 Gdtr[2];\r
213 UINT64 Idtr[2];\r
214 UINT64 Rip;\r
215 UINT64 Gs;\r
216 UINT64 Fs;\r
217 UINT64 Es;\r
218 UINT64 Ds;\r
219 UINT64 Cs;\r
220 UINT64 Ss;\r
221 UINT64 Rdi;\r
222 UINT64 Rsi;\r
223 UINT64 Rbp;\r
224 UINT64 Rsp;\r
225 UINT64 Rbx;\r
226 UINT64 Rdx;\r
227 UINT64 Rcx;\r
228 UINT64 Rax;\r
229 UINT64 R8;\r
230 UINT64 R9;\r
231 UINT64 R10;\r
232 UINT64 R11;\r
233 UINT64 R12;\r
234 UINT64 R13;\r
235 UINT64 R14;\r
236 UINT64 R15;\r
237} EFI_SYSTEM_CONTEXT_X64;\r
238\r
239///\r
240/// Itanium Processor Family Exception types.\r
241///\r
242#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
243#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
244#define EXCEPT_IPF_DATA_TLB 2\r
245#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
246#define EXCEPT_IPF_ALT_DATA_TLB 4\r
247#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
248#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
249#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
250#define EXCEPT_IPF_DIRTY_BIT 8\r
251#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
252#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
253#define EXCEPT_IPF_BREAKPOINT 11\r
254#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
255//\r
256// 13 - 19 reserved\r
257//\r
258#define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r
259#define EXCEPT_IPF_KEY_PERMISSION 21\r
260#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r
261#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r
262#define EXCEPT_IPF_GENERAL_EXCEPTION 24\r
263#define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r
264#define EXCEPT_IPF_NAT_CONSUMPTION 26\r
265#define EXCEPT_IPF_SPECULATION 27\r
266//\r
267// 28 reserved\r
268//\r
269#define EXCEPT_IPF_DEBUG 29\r
270#define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r
271#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r
272#define EXCEPT_IPF_FP_FAULT 32\r
273#define EXCEPT_IPF_FP_TRAP 33\r
274#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r
275#define EXCEPT_IPF_TAKEN_BRANCH 35\r
276#define EXCEPT_IPF_SINGLE_STEP 36\r
277//\r
278// 37 - 44 reserved\r
279//\r
280#define EXCEPT_IPF_IA32_EXCEPTION 45\r
281#define EXCEPT_IPF_IA32_INTERCEPT 46\r
282#define EXCEPT_IPF_IA32_INTERRUPT 47\r
283\r
284///\r
285/// IPF processor context definition.\r
286///\r
287typedef struct {\r
288 //\r
289 // The first reserved field is necessary to preserve alignment for the correct\r
290 // bits in UNAT and to insure F2 is 16 byte aligned.\r
291 //\r
292 UINT64 Reserved;\r
293 UINT64 R1;\r
294 UINT64 R2;\r
295 UINT64 R3;\r
296 UINT64 R4;\r
297 UINT64 R5;\r
298 UINT64 R6;\r
299 UINT64 R7;\r
300 UINT64 R8;\r
301 UINT64 R9;\r
302 UINT64 R10;\r
303 UINT64 R11;\r
304 UINT64 R12;\r
305 UINT64 R13;\r
306 UINT64 R14;\r
307 UINT64 R15;\r
308 UINT64 R16;\r
309 UINT64 R17;\r
310 UINT64 R18;\r
311 UINT64 R19;\r
312 UINT64 R20;\r
313 UINT64 R21;\r
314 UINT64 R22;\r
315 UINT64 R23;\r
316 UINT64 R24;\r
317 UINT64 R25;\r
318 UINT64 R26;\r
319 UINT64 R27;\r
320 UINT64 R28;\r
321 UINT64 R29;\r
322 UINT64 R30;\r
323 UINT64 R31;\r
324\r
325 UINT64 F2[2];\r
326 UINT64 F3[2];\r
327 UINT64 F4[2];\r
328 UINT64 F5[2];\r
329 UINT64 F6[2];\r
330 UINT64 F7[2];\r
331 UINT64 F8[2];\r
332 UINT64 F9[2];\r
333 UINT64 F10[2];\r
334 UINT64 F11[2];\r
335 UINT64 F12[2];\r
336 UINT64 F13[2];\r
337 UINT64 F14[2];\r
338 UINT64 F15[2];\r
339 UINT64 F16[2];\r
340 UINT64 F17[2];\r
341 UINT64 F18[2];\r
342 UINT64 F19[2];\r
343 UINT64 F20[2];\r
344 UINT64 F21[2];\r
345 UINT64 F22[2];\r
346 UINT64 F23[2];\r
347 UINT64 F24[2];\r
348 UINT64 F25[2];\r
349 UINT64 F26[2];\r
350 UINT64 F27[2];\r
351 UINT64 F28[2];\r
352 UINT64 F29[2];\r
353 UINT64 F30[2];\r
354 UINT64 F31[2];\r
355\r
356 UINT64 Pr;\r
357\r
358 UINT64 B0;\r
359 UINT64 B1;\r
360 UINT64 B2;\r
361 UINT64 B3;\r
362 UINT64 B4;\r
363 UINT64 B5;\r
364 UINT64 B6;\r
365 UINT64 B7;\r
366\r
367 //\r
368 // application registers\r
369 //\r
370 UINT64 ArRsc;\r
371 UINT64 ArBsp;\r
372 UINT64 ArBspstore;\r
373 UINT64 ArRnat;\r
374\r
375 UINT64 ArFcr;\r
376\r
377 UINT64 ArEflag;\r
378 UINT64 ArCsd;\r
379 UINT64 ArSsd;\r
380 UINT64 ArCflg;\r
381 UINT64 ArFsr;\r
382 UINT64 ArFir;\r
383 UINT64 ArFdr;\r
384\r
385 UINT64 ArCcv;\r
386\r
387 UINT64 ArUnat;\r
388\r
389 UINT64 ArFpsr;\r
390\r
391 UINT64 ArPfs;\r
392 UINT64 ArLc;\r
393 UINT64 ArEc;\r
394\r
395 //\r
396 // control registers\r
397 //\r
398 UINT64 CrDcr;\r
399 UINT64 CrItm;\r
400 UINT64 CrIva;\r
401 UINT64 CrPta;\r
402 UINT64 CrIpsr;\r
403 UINT64 CrIsr;\r
404 UINT64 CrIip;\r
405 UINT64 CrIfa;\r
406 UINT64 CrItir;\r
407 UINT64 CrIipa;\r
408 UINT64 CrIfs;\r
409 UINT64 CrIim;\r
410 UINT64 CrIha;\r
411\r
412 //\r
413 // debug registers\r
414 //\r
415 UINT64 Dbr0;\r
416 UINT64 Dbr1;\r
417 UINT64 Dbr2;\r
418 UINT64 Dbr3;\r
419 UINT64 Dbr4;\r
420 UINT64 Dbr5;\r
421 UINT64 Dbr6;\r
422 UINT64 Dbr7;\r
423\r
424 UINT64 Ibr0;\r
425 UINT64 Ibr1;\r
426 UINT64 Ibr2;\r
427 UINT64 Ibr3;\r
428 UINT64 Ibr4;\r
429 UINT64 Ibr5;\r
430 UINT64 Ibr6;\r
431 UINT64 Ibr7;\r
432\r
433 //\r
434 // virtual registers - nat bits for R1-R31\r
435 //\r
436 UINT64 IntNat;\r
437\r
438} EFI_SYSTEM_CONTEXT_IPF;\r
439\r
440///\r
441/// EBC processor exception types.\r
442///\r
443#define EXCEPT_EBC_UNDEFINED 0\r
444#define EXCEPT_EBC_DIVIDE_ERROR 1\r
445#define EXCEPT_EBC_DEBUG 2\r
446#define EXCEPT_EBC_BREAKPOINT 3\r
447#define EXCEPT_EBC_OVERFLOW 4\r
448#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
449#define EXCEPT_EBC_STACK_FAULT 6\r
450#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
451#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
452#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
453#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
454///\r
455/// For coding convenience, define the maximum valid EBC exception.\r
456///\r
457#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
458\r
459///\r
460/// EBC processor context definition.\r
461///\r
462typedef struct {\r
463 UINT64 R0;\r
464 UINT64 R1;\r
465 UINT64 R2;\r
466 UINT64 R3;\r
467 UINT64 R4;\r
468 UINT64 R5;\r
469 UINT64 R6;\r
470 UINT64 R7;\r
471 UINT64 Flags;\r
472 UINT64 ControlFlags;\r
473 UINT64 Ip;\r
474} EFI_SYSTEM_CONTEXT_EBC;\r
475\r
476\r
477\r
478///\r
479/// ARM processor exception types.\r
480///\r
481#define EXCEPT_ARM_RESET 0\r
482#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
483#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
484#define EXCEPT_ARM_PREFETCH_ABORT 3\r
485#define EXCEPT_ARM_DATA_ABORT 4\r
486#define EXCEPT_ARM_RESERVED 5\r
487#define EXCEPT_ARM_IRQ 6\r
488#define EXCEPT_ARM_FIQ 7\r
489\r
490///\r
491/// For coding convenience, define the maximum valid ARM exception.\r
492///\r
493#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
494\r
495///\r
496/// ARM processor context definition.\r
497///\r
498typedef struct {\r
499 UINT32 R0;\r
500 UINT32 R1;\r
501 UINT32 R2;\r
502 UINT32 R3;\r
503 UINT32 R4;\r
504 UINT32 R5;\r
505 UINT32 R6;\r
506 UINT32 R7;\r
507 UINT32 R8;\r
508 UINT32 R9;\r
509 UINT32 R10;\r
510 UINT32 R11;\r
511 UINT32 R12;\r
512 UINT32 SP;\r
513 UINT32 LR;\r
514 UINT32 PC;\r
515 UINT32 CPSR;\r
516 UINT32 DFSR;\r
517 UINT32 DFAR;\r
518 UINT32 IFSR;\r
519 UINT32 IFAR;\r
520} EFI_SYSTEM_CONTEXT_ARM;\r
521\r
522\r
523///\r
524/// AARCH64 processor exception types.\r
525///\r
526#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
527#define EXCEPT_AARCH64_IRQ 1\r
528#define EXCEPT_AARCH64_FIQ 2\r
529#define EXCEPT_AARCH64_SERROR 3\r
530\r
531///\r
532/// For coding convenience, define the maximum valid ARM exception.\r
533///\r
534#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
535\r
536typedef struct {\r
537 // General Purpose Registers\r
538 UINT64 X0;\r
539 UINT64 X1;\r
540 UINT64 X2;\r
541 UINT64 X3;\r
542 UINT64 X4;\r
543 UINT64 X5;\r
544 UINT64 X6;\r
545 UINT64 X7;\r
546 UINT64 X8;\r
547 UINT64 X9;\r
548 UINT64 X10;\r
549 UINT64 X11;\r
550 UINT64 X12;\r
551 UINT64 X13;\r
552 UINT64 X14;\r
553 UINT64 X15;\r
554 UINT64 X16;\r
555 UINT64 X17;\r
556 UINT64 X18;\r
557 UINT64 X19;\r
558 UINT64 X20;\r
559 UINT64 X21;\r
560 UINT64 X22;\r
561 UINT64 X23;\r
562 UINT64 X24;\r
563 UINT64 X25;\r
564 UINT64 X26;\r
565 UINT64 X27;\r
566 UINT64 X28;\r
567 UINT64 FP; // x29 - Frame pointer\r
568 UINT64 LR; // x30 - Link Register\r
569 UINT64 SP; // x31 - Stack pointer\r
570\r
571 // FP/SIMD Registers\r
572 UINT64 V0[2];\r
573 UINT64 V1[2];\r
574 UINT64 V2[2];\r
575 UINT64 V3[2];\r
576 UINT64 V4[2];\r
577 UINT64 V5[2];\r
578 UINT64 V6[2];\r
579 UINT64 V7[2];\r
580 UINT64 V8[2];\r
581 UINT64 V9[2];\r
582 UINT64 V10[2];\r
583 UINT64 V11[2];\r
584 UINT64 V12[2];\r
585 UINT64 V13[2];\r
586 UINT64 V14[2];\r
587 UINT64 V15[2];\r
588 UINT64 V16[2];\r
589 UINT64 V17[2];\r
590 UINT64 V18[2];\r
591 UINT64 V19[2];\r
592 UINT64 V20[2];\r
593 UINT64 V21[2];\r
594 UINT64 V22[2];\r
595 UINT64 V23[2];\r
596 UINT64 V24[2];\r
597 UINT64 V25[2];\r
598 UINT64 V26[2];\r
599 UINT64 V27[2];\r
600 UINT64 V28[2];\r
601 UINT64 V29[2];\r
602 UINT64 V30[2];\r
603 UINT64 V31[2];\r
604\r
605 UINT64 ELR; // Exception Link Register\r
606 UINT64 SPSR; // Saved Processor Status Register\r
607 UINT64 FPSR; // Floating Point Status Register\r
608 UINT64 ESR; // Exception syndrome register\r
609 UINT64 FAR; // Fault Address Register\r
610} EFI_SYSTEM_CONTEXT_AARCH64;\r
611\r
612\r
613///\r
614/// Universal EFI_SYSTEM_CONTEXT definition.\r
615///\r
616typedef union {\r
617 EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
618 EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
619 EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
620 EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
621 EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
622 EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
623} EFI_SYSTEM_CONTEXT;\r
624\r
625//\r
626// DebugSupport callback function prototypes\r
627//\r
628\r
629/** \r
630 Registers and enables an exception callback function for the specified exception.\r
631 \r
632 @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.\r
633 @param SystemContext Exception content.\r
634 \r
635**/\r
636typedef\r
637VOID\r
638(EFIAPI *EFI_EXCEPTION_CALLBACK)(\r
639 IN EFI_EXCEPTION_TYPE ExceptionType,\r
640 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
641 );\r
642\r
643/** \r
644 Registers and enables the on-target debug agent's periodic entry point.\r
645 \r
646 @param SystemContext Exception content.\r
647 \r
648**/\r
649typedef\r
650VOID\r
651(EFIAPI *EFI_PERIODIC_CALLBACK)(\r
652 IN OUT EFI_SYSTEM_CONTEXT SystemContext\r
653 );\r
654\r
655///\r
656/// Machine type definition\r
657///\r
658typedef enum {\r
659 IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
660 IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
661 IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
662 IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
663 IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
664 IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
665} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
666\r
667\r
668//\r
669// DebugSupport member function definitions\r
670//\r
671\r
672/** \r
673 Returns the maximum value that may be used for the ProcessorIndex parameter in\r
674 RegisterPeriodicCallback() and RegisterExceptionCallback(). \r
675 \r
676 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
677 @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r
678 processor index is returned. \r
679 \r
680 @retval EFI_SUCCESS The function completed successfully. \r
681 \r
682**/\r
683typedef\r
684EFI_STATUS\r
685(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r
686 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
687 OUT UINTN *MaxProcessorIndex\r
688 );\r
689\r
690/** \r
691 Registers a function to be called back periodically in interrupt context.\r
692 \r
693 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
694 @param ProcessorIndex Specifies which processor the callback function applies to.\r
695 @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r
696 periodic entry point of the debug agent.\r
697 \r
698 @retval EFI_SUCCESS The function completed successfully. \r
699 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
700 function was previously registered. \r
701 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
702 function. \r
703 \r
704**/\r
705typedef\r
706EFI_STATUS\r
707(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r
708 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
709 IN UINTN ProcessorIndex,\r
710 IN EFI_PERIODIC_CALLBACK PeriodicCallback\r
711 );\r
712\r
713/** \r
714 Registers a function to be called when a given processor exception occurs.\r
715 \r
716 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
717 @param ProcessorIndex Specifies which processor the callback function applies to.\r
718 @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r
719 when the processor exception specified by ExceptionType occurs. \r
720 @param ExceptionType Specifies which processor exception to hook. \r
721 \r
722 @retval EFI_SUCCESS The function completed successfully. \r
723 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r
724 function was previously registered. \r
725 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback \r
726 function. \r
727 \r
728**/\r
729typedef\r
730EFI_STATUS\r
731(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r
732 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
733 IN UINTN ProcessorIndex,\r
734 IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r
735 IN EFI_EXCEPTION_TYPE ExceptionType\r
736 );\r
737\r
738/** \r
739 Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r
740 causes a fresh memory fetch to retrieve code to be executed. \r
741 \r
742 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r
743 @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r
744 @param Start Specifies the physical base of the memory range to be invalidated. \r
745 @param Length Specifies the minimum number of bytes in the processor's instruction\r
746 cache to invalidate. \r
747 \r
748 @retval EFI_SUCCESS The function completed successfully. \r
749 \r
750**/\r
751typedef\r
752EFI_STATUS\r
753(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r
754 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
755 IN UINTN ProcessorIndex,\r
756 IN VOID *Start,\r
757 IN UINT64 Length\r
758 );\r
759\r
760///\r
761/// This protocol provides the services to allow the debug agent to register \r
762/// callback functions that are called either periodically or when specific \r
763/// processor exceptions occur.\r
764///\r
765struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r
766 ///\r
767 /// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r
768 ///\r
769 EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
770 EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
771 EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
772 EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
773 EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
774};\r
775\r
776extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
777\r
778#endif \r
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