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1 | /** @file\r | |
2 | UEFI Application to display CPUID leaf information.\r | |
3 | \r | |
4 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Uefi.h>\r | |
16 | #include <Library/BaseLib.h>\r | |
17 | #include <Library/UefiLib.h>\r | |
18 | #include <Register/Cpuid.h>\r | |
19 | \r | |
20 | ///\r | |
21 | /// Macro used to display the value of a bit field in a register returned by CPUID.\r | |
22 | ///\r | |
23 | #define PRINT_BIT_FIELD(Variable, FieldName) \\r | |
24 | Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);\r | |
25 | \r | |
26 | ///\r | |
27 | /// Macro used to display the value of a register returned by CPUID.\r | |
28 | ///\r | |
29 | #define PRINT_VALUE(Variable, Description) \\r | |
30 | Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);\r | |
31 | \r | |
32 | ///\r | |
33 | /// Structure for cache description lookup table\r | |
34 | ///\r | |
35 | typedef struct {\r | |
36 | UINT8 CacheDescriptor;\r | |
37 | CHAR8 *Type;\r | |
38 | CHAR8 *Description;\r | |
39 | } CPUID_CACHE_INFO_DESCRIPTION;\r | |
40 | \r | |
41 | ///\r | |
42 | /// Cache description lookup table\r | |
43 | ///\r | |
44 | CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {\r | |
45 | { 0x00 , "General" , "Null descriptor, this byte contains no information" },\r | |
46 | { 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r | |
47 | { 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r | |
48 | { 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r | |
49 | { 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r | |
50 | { 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r | |
51 | { 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r | |
52 | { 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r | |
53 | { 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r | |
54 | { 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r | |
55 | { 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r | |
56 | { 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r | |
57 | { 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r | |
58 | { 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r | |
59 | { 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r | |
60 | { 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r | |
61 | { 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r | |
62 | { 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
63 | { 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r | |
64 | { 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
65 | { 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
66 | { 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r | |
67 | { 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r | |
68 | { 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r | |
69 | { 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r | |
70 | { 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r | |
71 | { 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r | |
72 | { 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r | |
73 | { 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r | |
74 | { 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r | |
75 | { 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r | |
76 | { 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r | |
77 | { 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r | |
78 | { 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r | |
79 | { 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r | |
80 | { 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r | |
81 | { 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r | |
82 | { 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r | |
83 | { 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" },\r | |
84 | { 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r | |
85 | { 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r | |
86 | { 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r | |
87 | { 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r | |
88 | { 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r | |
89 | { 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r | |
90 | { 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r | |
91 | { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r | |
92 | { 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r | |
93 | { 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r | |
94 | { 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r | |
95 | { 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r | |
96 | { 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r | |
97 | { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r | |
98 | { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r | |
99 | { 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r | |
100 | { 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r | |
101 | { 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r | |
102 | { 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r | |
103 | { 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r | |
104 | { 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r | |
105 | { 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" },\r | |
106 | { 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" },\r | |
107 | { 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" },\r | |
108 | { 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" },\r | |
109 | { 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r | |
110 | { 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r | |
111 | { 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
112 | { 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
113 | { 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
114 | { 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r | |
115 | { 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r | |
116 | { 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r | |
117 | { 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r | |
118 | { 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r | |
119 | { 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r | |
120 | { 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r | |
121 | { 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r | |
122 | { 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r | |
123 | { 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r | |
124 | { 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" },\r | |
125 | { 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r | |
126 | { 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r | |
127 | { 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r | |
128 | { 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r | |
129 | { 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r | |
130 | { 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r | |
131 | { 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r | |
132 | { 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r | |
133 | { 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r | |
134 | { 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r | |
135 | { 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r | |
136 | { 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r | |
137 | { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r | |
138 | { 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r | |
139 | { 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r | |
140 | { 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r | |
141 | { 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r | |
142 | { 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r | |
143 | { 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r | |
144 | { 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r | |
145 | { 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r | |
146 | { 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r | |
147 | { 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r | |
148 | { 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r | |
149 | { 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r | |
150 | { 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r | |
151 | { 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r | |
152 | { 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r | |
153 | { 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r | |
154 | { 0xF0 , "Prefetch" , "64-Byte prefetching" },\r | |
155 | { 0xF1 , "Prefetch" , "128-Byte prefetching" },\r | |
156 | { 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r | |
157 | };\r | |
158 | \r | |
159 | ///\r | |
160 | /// The maximum supported CPUID leaf index starting from leaf 0x00000000.\r | |
161 | ///\r | |
162 | UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;\r | |
163 | \r | |
164 | ///\r | |
165 | /// The maximum supported CPUID leaf index starting from leaf 0x80000000.\r | |
166 | ///\r | |
167 | UINT32 gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;\r | |
168 | \r | |
169 | /**\r | |
170 | Display CPUID_SIGNATURE leaf.\r | |
171 | \r | |
172 | **/\r | |
173 | VOID\r | |
174 | CpuidSignature (\r | |
175 | VOID\r | |
176 | )\r | |
177 | {\r | |
178 | UINT32 Eax;\r | |
179 | UINT32 Ebx;\r | |
180 | UINT32 Ecx;\r | |
181 | UINT32 Edx;\r | |
182 | CHAR8 Signature[13];\r | |
183 | \r | |
184 | AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r | |
185 | \r | |
186 | Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);\r | |
187 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r | |
188 | PRINT_VALUE (Eax, MaximumLeaf);\r | |
189 | *(UINT32 *)(Signature + 0) = Ebx;\r | |
190 | *(UINT32 *)(Signature + 4) = Edx;\r | |
191 | *(UINT32 *)(Signature + 8) = Ecx;\r | |
192 | Signature [12] = 0;\r | |
193 | Print (L" Signature = %a\n", Signature);\r | |
194 | \r | |
195 | gMaximumBasicFunction = Eax;\r | |
196 | }\r | |
197 | \r | |
198 | /**\r | |
199 | Display CPUID_VERSION_INFO leaf.\r | |
200 | \r | |
201 | **/\r | |
202 | VOID\r | |
203 | CpuidVersionInfo (\r | |
204 | VOID\r | |
205 | )\r | |
206 | {\r | |
207 | CPUID_VERSION_INFO_EAX Eax;\r | |
208 | CPUID_VERSION_INFO_EBX Ebx;\r | |
209 | CPUID_VERSION_INFO_ECX Ecx;\r | |
210 | CPUID_VERSION_INFO_EDX Edx;\r | |
211 | UINT32 DisplayFamily;\r | |
212 | UINT32 DisplayModel;\r | |
213 | \r | |
214 | if (CPUID_VERSION_INFO > gMaximumBasicFunction) {\r | |
215 | return;\r | |
216 | }\r | |
217 | \r | |
218 | AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
219 | \r | |
220 | Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);\r | |
221 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
222 | \r | |
223 | DisplayFamily = Eax.Bits.FamilyId;\r | |
224 | if (Eax.Bits.FamilyId == 0x0F) {\r | |
225 | DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);\r | |
226 | }\r | |
227 | \r | |
228 | DisplayModel = Eax.Bits.Model;\r | |
229 | if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {\r | |
230 | DisplayModel |= (Eax.Bits.ExtendedModelId << 4);\r | |
231 | }\r | |
232 | \r | |
233 | Print (L" Family = %x Model = %x Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);\r | |
234 | \r | |
235 | PRINT_BIT_FIELD (Eax, SteppingId);\r | |
236 | PRINT_BIT_FIELD (Eax, Model);\r | |
237 | PRINT_BIT_FIELD (Eax, FamilyId);\r | |
238 | PRINT_BIT_FIELD (Eax, ProcessorType);\r | |
239 | PRINT_BIT_FIELD (Eax, ExtendedModelId);\r | |
240 | PRINT_BIT_FIELD (Eax, ExtendedFamilyId);\r | |
241 | PRINT_BIT_FIELD (Ebx, BrandIndex);\r | |
242 | PRINT_BIT_FIELD (Ebx, CacheLineSize);\r | |
243 | PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);\r | |
244 | PRINT_BIT_FIELD (Ebx, InitialLocalApicId);\r | |
245 | PRINT_BIT_FIELD (Ecx, SSE3);\r | |
246 | PRINT_BIT_FIELD (Ecx, PCLMULQDQ);\r | |
247 | PRINT_BIT_FIELD (Ecx, DTES64);\r | |
248 | PRINT_BIT_FIELD (Ecx, MONITOR);\r | |
249 | PRINT_BIT_FIELD (Ecx, DS_CPL);\r | |
250 | PRINT_BIT_FIELD (Ecx, VMX);\r | |
251 | PRINT_BIT_FIELD (Ecx, SMX);\r | |
252 | PRINT_BIT_FIELD (Ecx, TM2);\r | |
253 | PRINT_BIT_FIELD (Ecx, SSSE3);\r | |
254 | PRINT_BIT_FIELD (Ecx, CNXT_ID);\r | |
255 | PRINT_BIT_FIELD (Ecx, SDBG);\r | |
256 | PRINT_BIT_FIELD (Ecx, FMA);\r | |
257 | PRINT_BIT_FIELD (Ecx, CMPXCHG16B);\r | |
258 | PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);\r | |
259 | PRINT_BIT_FIELD (Ecx, PDCM);\r | |
260 | PRINT_BIT_FIELD (Ecx, PCID);\r | |
261 | PRINT_BIT_FIELD (Ecx, DCA);\r | |
262 | PRINT_BIT_FIELD (Ecx, SSE4_1);\r | |
263 | PRINT_BIT_FIELD (Ecx, SSE4_2);\r | |
264 | PRINT_BIT_FIELD (Ecx, x2APIC);\r | |
265 | PRINT_BIT_FIELD (Ecx, MOVBE);\r | |
266 | PRINT_BIT_FIELD (Ecx, POPCNT);\r | |
267 | PRINT_BIT_FIELD (Ecx, TSC_Deadline);\r | |
268 | PRINT_BIT_FIELD (Ecx, AESNI);\r | |
269 | PRINT_BIT_FIELD (Ecx, XSAVE);\r | |
270 | PRINT_BIT_FIELD (Ecx, OSXSAVE);\r | |
271 | PRINT_BIT_FIELD (Ecx, AVX);\r | |
272 | PRINT_BIT_FIELD (Ecx, F16C);\r | |
273 | PRINT_BIT_FIELD (Ecx, RDRAND);\r | |
274 | PRINT_BIT_FIELD (Edx, FPU);\r | |
275 | PRINT_BIT_FIELD (Edx, VME);\r | |
276 | PRINT_BIT_FIELD (Edx, DE);\r | |
277 | PRINT_BIT_FIELD (Edx, PSE);\r | |
278 | PRINT_BIT_FIELD (Edx, TSC);\r | |
279 | PRINT_BIT_FIELD (Edx, MSR);\r | |
280 | PRINT_BIT_FIELD (Edx, PAE);\r | |
281 | PRINT_BIT_FIELD (Edx, MCE);\r | |
282 | PRINT_BIT_FIELD (Edx, CX8);\r | |
283 | PRINT_BIT_FIELD (Edx, APIC);\r | |
284 | PRINT_BIT_FIELD (Edx, SEP);\r | |
285 | PRINT_BIT_FIELD (Edx, MTRR);\r | |
286 | PRINT_BIT_FIELD (Edx, PGE);\r | |
287 | PRINT_BIT_FIELD (Edx, MCA);\r | |
288 | PRINT_BIT_FIELD (Edx, CMOV);\r | |
289 | PRINT_BIT_FIELD (Edx, PAT);\r | |
290 | PRINT_BIT_FIELD (Edx, PSE_36);\r | |
291 | PRINT_BIT_FIELD (Edx, PSN);\r | |
292 | PRINT_BIT_FIELD (Edx, CLFSH);\r | |
293 | PRINT_BIT_FIELD (Edx, DS);\r | |
294 | PRINT_BIT_FIELD (Edx, ACPI);\r | |
295 | PRINT_BIT_FIELD (Edx, MMX);\r | |
296 | PRINT_BIT_FIELD (Edx, FXSR);\r | |
297 | PRINT_BIT_FIELD (Edx, SSE);\r | |
298 | PRINT_BIT_FIELD (Edx, SSE2);\r | |
299 | PRINT_BIT_FIELD (Edx, SS);\r | |
300 | PRINT_BIT_FIELD (Edx, HTT);\r | |
301 | PRINT_BIT_FIELD (Edx, TM);\r | |
302 | PRINT_BIT_FIELD (Edx, PBE);\r | |
303 | }\r | |
304 | \r | |
305 | /**\r | |
306 | Lookup a cache description string from the mCpuidCacheInfoDescription table.\r | |
307 | \r | |
308 | @param[in] CacheDescriptor Cache descriptor value from CPUID_CACHE_INFO.\r | |
309 | \r | |
310 | **/\r | |
311 | CPUID_CACHE_INFO_DESCRIPTION *\r | |
312 | LookupCacheDescription (\r | |
313 | UINT8 CacheDescriptor\r | |
314 | )\r | |
315 | {\r | |
316 | UINTN NumDescriptors;\r | |
317 | UINTN Descriptor;\r | |
318 | \r | |
319 | if (CacheDescriptor == 0x00) {\r | |
320 | return NULL;\r | |
321 | }\r | |
322 | NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);\r | |
323 | for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {\r | |
324 | if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {\r | |
325 | return &mCpuidCacheInfoDescription[Descriptor];\r | |
326 | }\r | |
327 | }\r | |
328 | return NULL;\r | |
329 | }\r | |
330 | \r | |
331 | /**\r | |
332 | Display CPUID_CACHE_INFO leaf for each supported cache descriptor.\r | |
333 | \r | |
334 | **/\r | |
335 | VOID\r | |
336 | CpuidCacheInfo (\r | |
337 | VOID\r | |
338 | )\r | |
339 | {\r | |
340 | CPUID_CACHE_INFO_CACHE_TLB Eax;\r | |
341 | CPUID_CACHE_INFO_CACHE_TLB Ebx;\r | |
342 | CPUID_CACHE_INFO_CACHE_TLB Ecx;\r | |
343 | CPUID_CACHE_INFO_CACHE_TLB Edx;\r | |
344 | UINTN Index;\r | |
345 | CPUID_CACHE_INFO_DESCRIPTION *CacheDescription;\r | |
346 | \r | |
347 | if (CPUID_CACHE_INFO > gMaximumBasicFunction) {\r | |
348 | return;\r | |
349 | }\r | |
350 | \r | |
351 | AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
352 | \r | |
353 | Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);\r | |
354 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
355 | if (Eax.Bits.NotValid == 0) {\r | |
356 | //\r | |
357 | // Process Eax.CacheDescriptor[1..3]. Ignore Eax.CacheDescriptor[0]\r | |
358 | //\r | |
359 | for (Index = 1; Index < 4; Index++) {\r | |
360 | CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);\r | |
361 | if (CacheDescription != NULL) {\r | |
362 | Print (L" %-8a %a\n",\r | |
363 | CacheDescription->Type,\r | |
364 | CacheDescription->Description\r | |
365 | );\r | |
366 | }\r | |
367 | }\r | |
368 | }\r | |
369 | if (Ebx.Bits.NotValid == 0) {\r | |
370 | //\r | |
371 | // Process Ebx.CacheDescriptor[0..3]\r | |
372 | //\r | |
373 | for (Index = 0; Index < 4; Index++) {\r | |
374 | CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);\r | |
375 | if (CacheDescription != NULL) {\r | |
376 | Print (L" %-8a %a\n",\r | |
377 | CacheDescription->Type,\r | |
378 | CacheDescription->Description\r | |
379 | );\r | |
380 | }\r | |
381 | }\r | |
382 | }\r | |
383 | if (Ecx.Bits.NotValid == 0) {\r | |
384 | //\r | |
385 | // Process Ecx.CacheDescriptor[0..3]\r | |
386 | //\r | |
387 | for (Index = 0; Index < 4; Index++) {\r | |
388 | CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);\r | |
389 | if (CacheDescription != NULL) {\r | |
390 | Print (L" %-8a %a\n",\r | |
391 | CacheDescription->Type,\r | |
392 | CacheDescription->Description\r | |
393 | );\r | |
394 | }\r | |
395 | }\r | |
396 | }\r | |
397 | if (Edx.Bits.NotValid == 0) {\r | |
398 | //\r | |
399 | // Process Edx.CacheDescriptor[0..3]\r | |
400 | //\r | |
401 | for (Index = 0; Index < 4; Index++) {\r | |
402 | CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);\r | |
403 | if (CacheDescription != NULL) {\r | |
404 | Print (L" %-8a %a\n",\r | |
405 | CacheDescription->Type,\r | |
406 | CacheDescription->Description\r | |
407 | );\r | |
408 | }\r | |
409 | }\r | |
410 | }\r | |
411 | }\r | |
412 | \r | |
413 | /**\r | |
414 | Display CPUID_SERIAL_NUMBER leaf if it is supported.\r | |
415 | \r | |
416 | **/\r | |
417 | VOID\r | |
418 | CpuidSerialNumber (\r | |
419 | VOID\r | |
420 | )\r | |
421 | {\r | |
422 | CPUID_VERSION_INFO_EDX VersionInfoEdx;\r | |
423 | UINT32 Ecx;\r | |
424 | UINT32 Edx;\r | |
425 | \r | |
426 | Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);\r | |
427 | \r | |
428 | if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {\r | |
429 | return;\r | |
430 | }\r | |
431 | \r | |
432 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r | |
433 | if (VersionInfoEdx.Bits.PSN == 0) {\r | |
434 | Print (L" Not Supported\n");\r | |
435 | return;\r | |
436 | }\r | |
437 | \r | |
438 | AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r | |
439 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx, Edx);\r | |
440 | Print (L" Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);\r | |
441 | }\r | |
442 | \r | |
443 | /**\r | |
444 | Display CPUID_CACHE_PARAMS for all supported sub-leafs.\r | |
445 | \r | |
446 | **/\r | |
447 | VOID\r | |
448 | CpuidCacheParams (\r | |
449 | VOID\r | |
450 | )\r | |
451 | {\r | |
452 | UINT32 CacheLevel;\r | |
453 | CPUID_CACHE_PARAMS_EAX Eax;\r | |
454 | CPUID_CACHE_PARAMS_EBX Ebx;\r | |
455 | UINT32 Ecx;\r | |
456 | CPUID_CACHE_PARAMS_EDX Edx;\r | |
457 | \r | |
458 | if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {\r | |
459 | return;\r | |
460 | }\r | |
461 | \r | |
462 | CacheLevel = 0;\r | |
463 | do {\r | |
464 | AsmCpuidEx (\r | |
465 | CPUID_CACHE_PARAMS, CacheLevel,\r | |
466 | &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r | |
467 | );\r | |
468 | if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {\r | |
469 | Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);\r | |
470 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);\r | |
471 | PRINT_BIT_FIELD (Eax, CacheType);\r | |
472 | PRINT_BIT_FIELD (Eax, CacheLevel);\r | |
473 | PRINT_BIT_FIELD (Eax, SelfInitializingCache);\r | |
474 | PRINT_BIT_FIELD (Eax, FullyAssociativeCache);\r | |
475 | PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);\r | |
476 | PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);\r | |
477 | PRINT_BIT_FIELD (Ebx, LineSize);\r | |
478 | PRINT_BIT_FIELD (Ebx, LinePartitions);\r | |
479 | PRINT_BIT_FIELD (Ebx, Ways);\r | |
480 | PRINT_VALUE (Ecx, NumberOfSets);\r | |
481 | PRINT_BIT_FIELD (Edx, Invalidate);\r | |
482 | PRINT_BIT_FIELD (Edx, CacheInclusiveness);\r | |
483 | PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);\r | |
484 | }\r | |
485 | CacheLevel++;\r | |
486 | } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r | |
487 | }\r | |
488 | \r | |
489 | /**\r | |
490 | Display CPUID_MONITOR_MWAIT leaf.\r | |
491 | \r | |
492 | **/\r | |
493 | VOID\r | |
494 | CpuidMonitorMwait (\r | |
495 | VOID\r | |
496 | )\r | |
497 | {\r | |
498 | CPUID_MONITOR_MWAIT_EAX Eax;\r | |
499 | CPUID_MONITOR_MWAIT_EBX Ebx;\r | |
500 | CPUID_MONITOR_MWAIT_ECX Ecx;\r | |
501 | CPUID_MONITOR_MWAIT_EDX Edx;\r | |
502 | \r | |
503 | if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {\r | |
504 | return;\r | |
505 | }\r | |
506 | \r | |
507 | AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
508 | \r | |
509 | Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);\r | |
510 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
511 | \r | |
512 | PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);\r | |
513 | PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);\r | |
514 | PRINT_BIT_FIELD (Ecx, ExtensionsSupported);\r | |
515 | PRINT_BIT_FIELD (Ecx, InterruptAsBreak);\r | |
516 | PRINT_BIT_FIELD (Edx, C0States);\r | |
517 | PRINT_BIT_FIELD (Edx, C1States);\r | |
518 | PRINT_BIT_FIELD (Edx, C2States);\r | |
519 | PRINT_BIT_FIELD (Edx, C3States);\r | |
520 | PRINT_BIT_FIELD (Edx, C4States);\r | |
521 | PRINT_BIT_FIELD (Edx, C5States);\r | |
522 | PRINT_BIT_FIELD (Edx, C6States);\r | |
523 | PRINT_BIT_FIELD (Edx, C7States);\r | |
524 | }\r | |
525 | \r | |
526 | /**\r | |
527 | Display CPUID_THERMAL_POWER_MANAGEMENT leaf.\r | |
528 | \r | |
529 | **/\r | |
530 | VOID\r | |
531 | CpuidThermalPowerManagement (\r | |
532 | VOID\r | |
533 | )\r | |
534 | {\r | |
535 | CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r | |
536 | CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r | |
537 | CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r | |
538 | \r | |
539 | if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {\r | |
540 | return;\r | |
541 | }\r | |
542 | \r | |
543 | AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r | |
544 | \r | |
545 | Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);\r | |
546 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r | |
547 | \r | |
548 | PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);\r | |
549 | PRINT_BIT_FIELD (Eax, TurboBoostTechnology);\r | |
550 | PRINT_BIT_FIELD (Eax, ARAT);\r | |
551 | PRINT_BIT_FIELD (Eax, PLN);\r | |
552 | PRINT_BIT_FIELD (Eax, ECMD);\r | |
553 | PRINT_BIT_FIELD (Eax, PTM);\r | |
554 | PRINT_BIT_FIELD (Eax, HWP);\r | |
555 | PRINT_BIT_FIELD (Eax, HWP_Notification);\r | |
556 | PRINT_BIT_FIELD (Eax, HWP_Activity_Window);\r | |
557 | PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);\r | |
558 | PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);\r | |
559 | PRINT_BIT_FIELD (Eax, HDC);\r | |
560 | PRINT_BIT_FIELD (Ebx, InterruptThresholds);\r | |
561 | PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);\r | |
562 | PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);\r | |
563 | }\r | |
564 | \r | |
565 | /**\r | |
566 | Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.\r | |
567 | \r | |
568 | **/\r | |
569 | VOID\r | |
570 | CpuidStructuredExtendedFeatureFlags (\r | |
571 | VOID\r | |
572 | )\r | |
573 | {\r | |
574 | UINT32 Eax;\r | |
575 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r | |
576 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r | |
577 | UINT32 SubLeaf;\r | |
578 | \r | |
579 | if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {\r | |
580 | return;\r | |
581 | }\r | |
582 | \r | |
583 | AsmCpuidEx (\r | |
584 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
585 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r | |
586 | &Eax, NULL, NULL, NULL\r | |
587 | );\r | |
588 | for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r | |
589 | AsmCpuidEx (\r | |
590 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
591 | SubLeaf,\r | |
592 | NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r | |
593 | );\r | |
594 | if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0) {\r | |
595 | Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);\r | |
596 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r | |
597 | PRINT_BIT_FIELD (Ebx, FSGSBASE);\r | |
598 | PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);\r | |
599 | PRINT_BIT_FIELD (Ebx, SGX);\r | |
600 | PRINT_BIT_FIELD (Ebx, BMI1);\r | |
601 | PRINT_BIT_FIELD (Ebx, HLE);\r | |
602 | PRINT_BIT_FIELD (Ebx, AVX2);\r | |
603 | PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);\r | |
604 | PRINT_BIT_FIELD (Ebx, SMEP);\r | |
605 | PRINT_BIT_FIELD (Ebx, BMI2);\r | |
606 | PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r | |
607 | PRINT_BIT_FIELD (Ebx, INVPCID);\r | |
608 | PRINT_BIT_FIELD (Ebx, RTM);\r | |
609 | PRINT_BIT_FIELD (Ebx, RDT_M);\r | |
610 | PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r | |
611 | PRINT_BIT_FIELD (Ebx, MPX);\r | |
612 | PRINT_BIT_FIELD (Ebx, RDT_A);\r | |
613 | PRINT_BIT_FIELD (Ebx, RDSEED);\r | |
614 | PRINT_BIT_FIELD (Ebx, ADX);\r | |
615 | PRINT_BIT_FIELD (Ebx, SMAP);\r | |
616 | PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r | |
617 | PRINT_BIT_FIELD (Ebx, CLWB);\r | |
618 | PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r | |
619 | PRINT_BIT_FIELD (Ebx, SHA);\r | |
620 | PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r | |
621 | PRINT_BIT_FIELD (Ecx, UMIP);\r | |
622 | PRINT_BIT_FIELD (Ecx, PKU);\r | |
623 | PRINT_BIT_FIELD (Ecx, OSPKE);\r | |
624 | PRINT_BIT_FIELD (Ecx, MAWAU);\r | |
625 | PRINT_BIT_FIELD (Ecx, RDPID);\r | |
626 | PRINT_BIT_FIELD (Ecx, SGX_LC);\r | |
627 | }\r | |
628 | }\r | |
629 | }\r | |
630 | \r | |
631 | /**\r | |
632 | Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.\r | |
633 | \r | |
634 | **/\r | |
635 | VOID\r | |
636 | CpuidDirectCacheAccessInfo (\r | |
637 | VOID\r | |
638 | )\r | |
639 | {\r | |
640 | UINT32 Eax;\r | |
641 | \r | |
642 | if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {\r | |
643 | return;\r | |
644 | }\r | |
645 | \r | |
646 | AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r | |
647 | Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);\r | |
648 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r | |
649 | }\r | |
650 | \r | |
651 | /**\r | |
652 | Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.\r | |
653 | \r | |
654 | **/\r | |
655 | VOID\r | |
656 | CpuidArchitecturalPerformanceMonitoring (\r | |
657 | VOID\r | |
658 | )\r | |
659 | {\r | |
660 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r | |
661 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r | |
662 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r | |
663 | \r | |
664 | if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {\r | |
665 | return;\r | |
666 | }\r | |
667 | \r | |
668 | AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r | |
669 | Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);\r | |
670 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);\r | |
671 | PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);\r | |
672 | PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);\r | |
673 | PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);\r | |
674 | PRINT_BIT_FIELD (Eax, EbxBitVectorLength);\r | |
675 | PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);\r | |
676 | PRINT_BIT_FIELD (Ebx, InstructionsRetired);\r | |
677 | PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);\r | |
678 | PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);\r | |
679 | PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);\r | |
680 | PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);\r | |
681 | PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);\r | |
682 | PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);\r | |
683 | PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);\r | |
684 | }\r | |
685 | \r | |
686 | /**\r | |
687 | Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.\r | |
688 | \r | |
689 | **/\r | |
690 | VOID\r | |
691 | CpuidExtendedTopology (\r | |
692 | VOID\r | |
693 | )\r | |
694 | {\r | |
695 | CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r | |
696 | CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r | |
697 | CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r | |
698 | UINT32 Edx;\r | |
699 | UINT32 LevelNumber;\r | |
700 | \r | |
701 | if (CPUID_EXTENDED_TOPOLOGY > gMaximumBasicFunction) {\r | |
702 | return;\r | |
703 | }\r | |
704 | \r | |
705 | LevelNumber = 0;\r | |
706 | do {\r | |
707 | AsmCpuidEx (\r | |
708 | CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r | |
709 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r | |
710 | );\r | |
711 | if (Eax.Bits.ApicIdShift != 0) {\r | |
712 | Print (L"CPUID_EXTENDED_TOPOLOGY (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_TOPOLOGY, LevelNumber);\r | |
713 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);\r | |
714 | PRINT_BIT_FIELD (Eax, ApicIdShift);\r | |
715 | PRINT_BIT_FIELD (Ebx, LogicalProcessors);\r | |
716 | PRINT_BIT_FIELD (Ecx, LevelNumber);\r | |
717 | PRINT_BIT_FIELD (Ecx, LevelType);\r | |
718 | PRINT_VALUE (Edx, x2APIC_ID);\r | |
719 | }\r | |
720 | LevelNumber++;\r | |
721 | } while (Eax.Bits.ApicIdShift != 0);\r | |
722 | }\r | |
723 | \r | |
724 | /**\r | |
725 | Display CPUID_EXTENDED_STATE sub-leaf.\r | |
726 | \r | |
727 | **/\r | |
728 | VOID\r | |
729 | CpuidExtendedStateSubLeaf (\r | |
730 | VOID\r | |
731 | )\r | |
732 | {\r | |
733 | CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r | |
734 | UINT32 Ebx;\r | |
735 | CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r | |
736 | UINT32 Edx;\r | |
737 | \r | |
738 | AsmCpuidEx (\r | |
739 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r | |
740 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r | |
741 | );\r | |
742 | Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);\r | |
743 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);\r | |
744 | PRINT_BIT_FIELD (Eax, XSAVEOPT);\r | |
745 | PRINT_BIT_FIELD (Eax, XSAVEC);\r | |
746 | PRINT_BIT_FIELD (Eax, XGETBV);\r | |
747 | PRINT_BIT_FIELD (Eax, XSAVES);\r | |
748 | PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r | |
749 | PRINT_BIT_FIELD (Ecx, XCR0);\r | |
750 | PRINT_BIT_FIELD (Ecx, PT);\r | |
751 | PRINT_BIT_FIELD (Ecx, XCR0_1);\r | |
752 | PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r | |
753 | }\r | |
754 | \r | |
755 | /**\r | |
756 | Display CPUID_EXTENDED_STATE size and offset information sub-leaf.\r | |
757 | \r | |
758 | **/\r | |
759 | VOID\r | |
760 | CpuidExtendedStateSizeOffset (\r | |
761 | VOID\r | |
762 | )\r | |
763 | {\r | |
764 | UINT32 Eax;\r | |
765 | UINT32 Ebx;\r | |
766 | CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r | |
767 | UINT32 Edx;\r | |
768 | UINT32 SubLeaf;\r | |
769 | \r | |
770 | for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r | |
771 | AsmCpuidEx (\r | |
772 | CPUID_EXTENDED_STATE, SubLeaf,\r | |
773 | &Eax, &Ebx, &Ecx.Uint32, &Edx\r | |
774 | );\r | |
775 | if (Edx != 0) {\r | |
776 | Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);\r | |
777 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);\r | |
778 | PRINT_VALUE (Eax, FeatureSaveStateSize);\r | |
779 | PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r | |
780 | PRINT_BIT_FIELD (Ecx, XSS);\r | |
781 | PRINT_BIT_FIELD (Ecx, Compacted);\r | |
782 | }\r | |
783 | }\r | |
784 | }\r | |
785 | \r | |
786 | /**\r | |
787 | Display CPUID_EXTENDED_STATE main leaf and sub-leafs.\r | |
788 | \r | |
789 | **/\r | |
790 | VOID\r | |
791 | CpuidExtendedStateMainLeaf (\r | |
792 | VOID\r | |
793 | )\r | |
794 | {\r | |
795 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r | |
796 | UINT32 Ebx;\r | |
797 | UINT32 Ecx;\r | |
798 | UINT32 Edx;\r | |
799 | \r | |
800 | if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {\r | |
801 | return;\r | |
802 | }\r | |
803 | \r | |
804 | AsmCpuidEx (\r | |
805 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r | |
806 | &Eax.Uint32, &Ebx, &Ecx, &Edx\r | |
807 | );\r | |
808 | Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);\r | |
809 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);\r | |
810 | PRINT_BIT_FIELD (Eax, x87);\r | |
811 | PRINT_BIT_FIELD (Eax, SSE);\r | |
812 | PRINT_BIT_FIELD (Eax, AVX);\r | |
813 | PRINT_BIT_FIELD (Eax, MPX);\r | |
814 | PRINT_BIT_FIELD (Eax, AVX_512);\r | |
815 | PRINT_BIT_FIELD (Eax, IA32_XSS);\r | |
816 | PRINT_BIT_FIELD (Eax, PKRU);\r | |
817 | PRINT_VALUE (Ebx, EnabledSaveStateSize);\r | |
818 | PRINT_VALUE (Ecx, SupportedSaveStateSize);\r | |
819 | PRINT_VALUE (Edx, XCR0_Supported_32_63);\r | |
820 | \r | |
821 | CpuidExtendedStateSubLeaf ();\r | |
822 | CpuidExtendedStateSizeOffset ();\r | |
823 | }\r | |
824 | \r | |
825 | /**\r | |
826 | Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.\r | |
827 | \r | |
828 | **/\r | |
829 | VOID\r | |
830 | CpuidIntelRdtMonitoringEnumerationSubLeaf (\r | |
831 | VOID\r | |
832 | )\r | |
833 | {\r | |
834 | UINT32 Ebx;\r | |
835 | CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r | |
836 | \r | |
837 | if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r | |
838 | return;\r | |
839 | }\r | |
840 | \r | |
841 | AsmCpuidEx (\r | |
842 | CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r | |
843 | NULL, &Ebx, NULL, &Edx.Uint32\r | |
844 | );\r | |
845 | Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r | |
846 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r | |
847 | PRINT_VALUE (Ebx, Maximum_RMID_Range);\r | |
848 | PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r | |
849 | }\r | |
850 | \r | |
851 | /**\r | |
852 | Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.\r | |
853 | \r | |
854 | **/\r | |
855 | VOID\r | |
856 | CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (\r | |
857 | VOID\r | |
858 | )\r | |
859 | {\r | |
860 | UINT32 Ebx;\r | |
861 | UINT32 Ecx;\r | |
862 | CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r | |
863 | \r | |
864 | if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r | |
865 | return;\r | |
866 | }\r | |
867 | \r | |
868 | AsmCpuidEx (\r | |
869 | CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r | |
870 | NULL, &Ebx, &Ecx, &Edx.Uint32\r | |
871 | );\r | |
872 | Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r | |
873 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r | |
874 | PRINT_VALUE (Ebx, OccupancyConversionFactor);\r | |
875 | PRINT_VALUE (Ecx, Maximum_RMID_Range);\r | |
876 | PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r | |
877 | PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r | |
878 | PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r | |
879 | }\r | |
880 | \r | |
881 | /**\r | |
882 | Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration\r | |
883 | sub-leaf.\r | |
884 | \r | |
885 | **/\r | |
886 | VOID\r | |
887 | CpuidIntelRdtAllocationL3CacheSubLeaf (\r | |
888 | VOID\r | |
889 | )\r | |
890 | {\r | |
891 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r | |
892 | UINT32 Ebx;\r | |
893 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r | |
894 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r | |
895 | \r | |
896 | AsmCpuidEx (\r | |
897 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r | |
898 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r | |
899 | );\r | |
900 | Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r | |
901 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r | |
902 | PRINT_BIT_FIELD (Eax, CapacityLength);\r | |
903 | PRINT_VALUE (Ebx, AllocationUnitBitMap);\r | |
904 | PRINT_BIT_FIELD (Ecx, CosUpdatesInfrequent);\r | |
905 | PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);\r | |
906 | PRINT_BIT_FIELD (Edx, HighestCosNumber);\r | |
907 | }\r | |
908 | \r | |
909 | /**\r | |
910 | Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration\r | |
911 | sub-leaf.\r | |
912 | \r | |
913 | **/\r | |
914 | VOID\r | |
915 | CpuidIntelRdtAllocationL2CacheSubLeaf (\r | |
916 | VOID\r | |
917 | )\r | |
918 | {\r | |
919 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r | |
920 | UINT32 Ebx;\r | |
921 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r | |
922 | \r | |
923 | AsmCpuidEx (\r | |
924 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r | |
925 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r | |
926 | );\r | |
927 | Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r | |
928 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r | |
929 | PRINT_BIT_FIELD (Eax, CapacityLength);\r | |
930 | PRINT_VALUE (Ebx, AllocationUnitBitMap);\r | |
931 | PRINT_BIT_FIELD (Edx, HighestCosNumber);\r | |
932 | }\r | |
933 | \r | |
934 | /**\r | |
935 | Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.\r | |
936 | \r | |
937 | **/\r | |
938 | VOID\r | |
939 | CpuidIntelRdtAllocationMainLeaf (\r | |
940 | VOID\r | |
941 | )\r | |
942 | {\r | |
943 | CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r | |
944 | \r | |
945 | if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {\r | |
946 | return;\r | |
947 | }\r | |
948 | \r | |
949 | AsmCpuidEx (\r | |
950 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r | |
951 | NULL, &Ebx.Uint32, NULL, NULL\r | |
952 | );\r | |
953 | Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r | |
954 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r | |
955 | PRINT_BIT_FIELD (Ebx, L3CacheAllocation);\r | |
956 | PRINT_BIT_FIELD (Ebx, L2CacheAllocation);\r | |
957 | \r | |
958 | CpuidIntelRdtAllocationL3CacheSubLeaf ();\r | |
959 | CpuidIntelRdtAllocationL2CacheSubLeaf ();\r | |
960 | }\r | |
961 | \r | |
962 | /**\r | |
963 | Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r | |
964 | \r | |
965 | **/\r | |
966 | VOID\r | |
967 | CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (\r | |
968 | VOID\r | |
969 | )\r | |
970 | {\r | |
971 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r | |
972 | UINT32 Ebx;\r | |
973 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r | |
974 | \r | |
975 | AsmCpuidEx (\r | |
976 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r | |
977 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r | |
978 | );\r | |
979 | Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r | |
980 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r | |
981 | PRINT_BIT_FIELD (Eax, SGX1);\r | |
982 | PRINT_BIT_FIELD (Eax, SGX2);\r | |
983 | PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);\r | |
984 | PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);\r | |
985 | }\r | |
986 | \r | |
987 | /**\r | |
988 | Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r | |
989 | \r | |
990 | **/\r | |
991 | VOID\r | |
992 | CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (\r | |
993 | VOID\r | |
994 | )\r | |
995 | {\r | |
996 | UINT32 Eax;\r | |
997 | UINT32 Ebx;\r | |
998 | UINT32 Ecx;\r | |
999 | UINT32 Edx;\r | |
1000 | \r | |
1001 | AsmCpuidEx (\r | |
1002 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r | |
1003 | &Eax, &Ebx, &Ecx, &Edx\r | |
1004 | );\r | |
1005 | Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r | |
1006 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r | |
1007 | }\r | |
1008 | \r | |
1009 | /**\r | |
1010 | Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r | |
1011 | \r | |
1012 | **/\r | |
1013 | VOID\r | |
1014 | CpuidEnumerationOfIntelSgxResourcesSubLeaf (\r | |
1015 | VOID\r | |
1016 | )\r | |
1017 | {\r | |
1018 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r | |
1019 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r | |
1020 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r | |
1021 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r | |
1022 | UINT32 SubLeaf;\r | |
1023 | \r | |
1024 | SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r | |
1025 | do {\r | |
1026 | AsmCpuidEx (\r | |
1027 | CPUID_INTEL_SGX, SubLeaf,\r | |
1028 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
1029 | );\r | |
1030 | if (Eax.Bits.SubLeafType == 0x1) {\r | |
1031 | Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r | |
1032 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1033 | PRINT_BIT_FIELD (Eax, SubLeafType);\r | |
1034 | PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);\r | |
1035 | PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);\r | |
1036 | PRINT_BIT_FIELD (Ecx, EpcSection);\r | |
1037 | PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r | |
1038 | PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r | |
1039 | }\r | |
1040 | SubLeaf++;\r | |
1041 | } while (Eax.Bits.SubLeafType == 0x1);\r | |
1042 | }\r | |
1043 | \r | |
1044 | /**\r | |
1045 | Display Intel SGX Resource Enumeration.\r | |
1046 | \r | |
1047 | **/\r | |
1048 | VOID\r | |
1049 | CpuidEnumerationOfIntelSgx (\r | |
1050 | VOID\r | |
1051 | )\r | |
1052 | {\r | |
1053 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r | |
1054 | \r | |
1055 | if (CPUID_INTEL_SGX > gMaximumBasicFunction) {\r | |
1056 | return;\r | |
1057 | }\r | |
1058 | \r | |
1059 | AsmCpuidEx (\r | |
1060 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
1061 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r | |
1062 | NULL, &Ebx.Uint32, NULL, NULL\r | |
1063 | );\r | |
1064 | if (Ebx.Bits.SGX != 1) {\r | |
1065 | //\r | |
1066 | // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support\r | |
1067 | // for Intel SGX.\r | |
1068 | //\r | |
1069 | return;\r | |
1070 | }\r | |
1071 | \r | |
1072 | CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();\r | |
1073 | CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();\r | |
1074 | CpuidEnumerationOfIntelSgxResourcesSubLeaf ();\r | |
1075 | }\r | |
1076 | \r | |
1077 | /**\r | |
1078 | Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.\r | |
1079 | \r | |
1080 | @param[in] MaximumSubLeaf Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.\r | |
1081 | \r | |
1082 | **/\r | |
1083 | VOID\r | |
1084 | CpuidIntelProcessorTraceSubLeaf (\r | |
1085 | UINT32 MaximumSubLeaf\r | |
1086 | )\r | |
1087 | {\r | |
1088 | UINT32 SubLeaf;\r | |
1089 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r | |
1090 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r | |
1091 | \r | |
1092 | for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r | |
1093 | AsmCpuidEx (\r | |
1094 | CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r | |
1095 | &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r | |
1096 | );\r | |
1097 | Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);\r | |
1098 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);\r | |
1099 | PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);\r | |
1100 | PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);\r | |
1101 | PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);\r | |
1102 | PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);\r | |
1103 | }\r | |
1104 | }\r | |
1105 | \r | |
1106 | /**\r | |
1107 | Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.\r | |
1108 | \r | |
1109 | **/\r | |
1110 | VOID\r | |
1111 | CpuidIntelProcessorTraceMainLeaf (\r | |
1112 | VOID\r | |
1113 | )\r | |
1114 | {\r | |
1115 | UINT32 Eax;\r | |
1116 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r | |
1117 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r | |
1118 | \r | |
1119 | if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {\r | |
1120 | return;\r | |
1121 | }\r | |
1122 | \r | |
1123 | AsmCpuidEx (\r | |
1124 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r | |
1125 | &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r | |
1126 | );\r | |
1127 | Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);\r | |
1128 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r | |
1129 | PRINT_VALUE (Eax, MaximumSubLeaf);\r | |
1130 | PRINT_BIT_FIELD (Ebx, Cr3Filter);\r | |
1131 | PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r | |
1132 | PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r | |
1133 | PRINT_BIT_FIELD (Ebx, Mtc);\r | |
1134 | PRINT_BIT_FIELD (Ebx, PTWrite);\r | |
1135 | PRINT_BIT_FIELD (Ebx, PowerEventTrace);\r | |
1136 | PRINT_BIT_FIELD (Ecx, RTIT);\r | |
1137 | PRINT_BIT_FIELD (Ecx, ToPA);\r | |
1138 | PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r | |
1139 | PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);\r | |
1140 | PRINT_BIT_FIELD (Ecx, LIP);\r | |
1141 | \r | |
1142 | CpuidIntelProcessorTraceSubLeaf (Eax);\r | |
1143 | }\r | |
1144 | \r | |
1145 | /**\r | |
1146 | Display CPUID_TIME_STAMP_COUNTER leaf.\r | |
1147 | \r | |
1148 | **/\r | |
1149 | VOID\r | |
1150 | CpuidTimeStampCounter (\r | |
1151 | VOID\r | |
1152 | )\r | |
1153 | {\r | |
1154 | UINT32 Eax;\r | |
1155 | UINT32 Ebx;\r | |
1156 | UINT32 Ecx;\r | |
1157 | \r | |
1158 | if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r | |
1159 | return;\r | |
1160 | }\r | |
1161 | \r | |
1162 | AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r | |
1163 | Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r | |
1164 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);\r | |
1165 | }\r | |
1166 | \r | |
1167 | /**\r | |
1168 | Display CPUID_PROCESSOR_FREQUENCY leaf.\r | |
1169 | \r | |
1170 | **/\r | |
1171 | VOID\r | |
1172 | CpuidProcessorFrequency (\r | |
1173 | VOID\r | |
1174 | )\r | |
1175 | {\r | |
1176 | CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r | |
1177 | CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r | |
1178 | CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r | |
1179 | \r | |
1180 | if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {\r | |
1181 | return;\r | |
1182 | }\r | |
1183 | \r | |
1184 | AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r | |
1185 | Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);\r | |
1186 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r | |
1187 | PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);\r | |
1188 | PRINT_BIT_FIELD (Ebx, MaximumFrequency);\r | |
1189 | PRINT_BIT_FIELD (Ecx, BusFrequency);\r | |
1190 | }\r | |
1191 | \r | |
1192 | /**\r | |
1193 | Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.\r | |
1194 | Also display these sub-leafs as a single SoC Vendor Brand String.\r | |
1195 | \r | |
1196 | **/\r | |
1197 | VOID\r | |
1198 | CpuidSocVendorBrandString (\r | |
1199 | VOID\r | |
1200 | )\r | |
1201 | {\r | |
1202 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
1203 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
1204 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
1205 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
1206 | //\r | |
1207 | // Array to store brand string from 3 brand string leafs with\r | |
1208 | // 4 32-bit brand string values per leaf and an extra value to\r | |
1209 | // null terminate the string.\r | |
1210 | //\r | |
1211 | UINT32 BrandString[3 * 4 + 1];\r | |
1212 | \r | |
1213 | AsmCpuidEx (\r | |
1214 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r | |
1215 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
1216 | );\r | |
1217 | Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);\r | |
1218 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1219 | BrandString[0] = Eax.Uint32;\r | |
1220 | BrandString[1] = Ebx.Uint32;\r | |
1221 | BrandString[2] = Ecx.Uint32;\r | |
1222 | BrandString[3] = Edx.Uint32;\r | |
1223 | \r | |
1224 | AsmCpuidEx (\r | |
1225 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r | |
1226 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
1227 | );\r | |
1228 | Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);\r | |
1229 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1230 | BrandString[4] = Eax.Uint32;\r | |
1231 | BrandString[5] = Ebx.Uint32;\r | |
1232 | BrandString[6] = Ecx.Uint32;\r | |
1233 | BrandString[7] = Edx.Uint32;\r | |
1234 | \r | |
1235 | AsmCpuidEx (\r | |
1236 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r | |
1237 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
1238 | );\r | |
1239 | Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);\r | |
1240 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1241 | BrandString[8] = Eax.Uint32;\r | |
1242 | BrandString[9] = Ebx.Uint32;\r | |
1243 | BrandString[10] = Ecx.Uint32;\r | |
1244 | BrandString[11] = Edx.Uint32;\r | |
1245 | \r | |
1246 | BrandString[12] = 0;\r | |
1247 | \r | |
1248 | Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);\r | |
1249 | }\r | |
1250 | \r | |
1251 | /**\r | |
1252 | Display CPUID_SOC_VENDOR main leaf and sub-leafs.\r | |
1253 | \r | |
1254 | **/\r | |
1255 | VOID\r | |
1256 | CpuidSocVendor (\r | |
1257 | VOID\r | |
1258 | )\r | |
1259 | {\r | |
1260 | UINT32 Eax;\r | |
1261 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r | |
1262 | UINT32 Ecx;\r | |
1263 | UINT32 Edx;\r | |
1264 | \r | |
1265 | if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {\r | |
1266 | return;\r | |
1267 | }\r | |
1268 | \r | |
1269 | AsmCpuidEx (\r | |
1270 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r | |
1271 | &Eax, &Ebx.Uint32, &Ecx, &Edx\r | |
1272 | );\r | |
1273 | Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);\r | |
1274 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);\r | |
1275 | if (Eax < 3) {\r | |
1276 | Print (L" Not Supported\n");\r | |
1277 | return;\r | |
1278 | }\r | |
1279 | PRINT_VALUE (Eax, MaxSOCID_Index);\r | |
1280 | PRINT_BIT_FIELD (Ebx, SocVendorId);\r | |
1281 | PRINT_BIT_FIELD (Ebx, IsVendorScheme);\r | |
1282 | PRINT_VALUE (Ecx, ProjectID);\r | |
1283 | PRINT_VALUE (Edx, SteppingID);\r | |
1284 | CpuidSocVendorBrandString ();\r | |
1285 | }\r | |
1286 | \r | |
1287 | /**\r | |
1288 | Display CPUID_EXTENDED_FUNCTION leaf.\r | |
1289 | \r | |
1290 | **/\r | |
1291 | VOID\r | |
1292 | CpuidExtendedFunction (\r | |
1293 | VOID\r | |
1294 | )\r | |
1295 | {\r | |
1296 | UINT32 Eax;\r | |
1297 | \r | |
1298 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r | |
1299 | Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);\r | |
1300 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r | |
1301 | PRINT_VALUE (Eax, MaximumExtendedFunction);\r | |
1302 | \r | |
1303 | gMaximumExtendedFunction = Eax;\r | |
1304 | }\r | |
1305 | \r | |
1306 | /**\r | |
1307 | Display CPUID_EXTENDED_CPU_SIG leaf.\r | |
1308 | \r | |
1309 | **/\r | |
1310 | VOID\r | |
1311 | CpuidExtendedCpuSig (\r | |
1312 | VOID\r | |
1313 | )\r | |
1314 | {\r | |
1315 | UINT32 Eax;\r | |
1316 | CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r | |
1317 | CPUID_EXTENDED_CPU_SIG_EDX Edx;\r | |
1318 | \r | |
1319 | if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {\r | |
1320 | return;\r | |
1321 | }\r | |
1322 | \r | |
1323 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r | |
1324 | Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);\r | |
1325 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);\r | |
1326 | PRINT_BIT_FIELD (Ecx, LAHF_SAHF);\r | |
1327 | PRINT_BIT_FIELD (Ecx, LZCNT);\r | |
1328 | PRINT_BIT_FIELD (Ecx, PREFETCHW);\r | |
1329 | PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);\r | |
1330 | PRINT_BIT_FIELD (Edx, NX);\r | |
1331 | PRINT_BIT_FIELD (Edx, Page1GB);\r | |
1332 | PRINT_BIT_FIELD (Edx, RDTSCP);\r | |
1333 | PRINT_BIT_FIELD (Edx, LM);\r | |
1334 | }\r | |
1335 | \r | |
1336 | /**\r | |
1337 | Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and CPUID_BRAND_STRING3\r | |
1338 | leafs. Also display these three leafs as a single brand string.\r | |
1339 | \r | |
1340 | **/\r | |
1341 | VOID\r | |
1342 | CpuidProcessorBrandString (\r | |
1343 | VOID\r | |
1344 | )\r | |
1345 | {\r | |
1346 | CPUID_BRAND_STRING_DATA Eax;\r | |
1347 | CPUID_BRAND_STRING_DATA Ebx;\r | |
1348 | CPUID_BRAND_STRING_DATA Ecx;\r | |
1349 | CPUID_BRAND_STRING_DATA Edx;\r | |
1350 | //\r | |
1351 | // Array to store brand string from 3 brand string leafs with\r | |
1352 | // 4 32-bit brand string values per leaf and an extra value to\r | |
1353 | // null terminate the string.\r | |
1354 | //\r | |
1355 | UINT32 BrandString[3 * 4 + 1];\r | |
1356 | \r | |
1357 | if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {\r | |
1358 | AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
1359 | Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);\r | |
1360 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1361 | BrandString[0] = Eax.Uint32;\r | |
1362 | BrandString[1] = Ebx.Uint32;\r | |
1363 | BrandString[2] = Ecx.Uint32;\r | |
1364 | BrandString[3] = Edx.Uint32;\r | |
1365 | }\r | |
1366 | \r | |
1367 | if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {\r | |
1368 | AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
1369 | Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);\r | |
1370 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1371 | BrandString[4] = Eax.Uint32;\r | |
1372 | BrandString[5] = Ebx.Uint32;\r | |
1373 | BrandString[6] = Ecx.Uint32;\r | |
1374 | BrandString[7] = Edx.Uint32;\r | |
1375 | }\r | |
1376 | \r | |
1377 | if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {\r | |
1378 | AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
1379 | Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);\r | |
1380 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r | |
1381 | BrandString[8] = Eax.Uint32;\r | |
1382 | BrandString[9] = Ebx.Uint32;\r | |
1383 | BrandString[10] = Ecx.Uint32;\r | |
1384 | BrandString[11] = Edx.Uint32;\r | |
1385 | }\r | |
1386 | \r | |
1387 | BrandString[12] = 0;\r | |
1388 | \r | |
1389 | Print (L"Brand String = %a\n", (CHAR8 *)BrandString);\r | |
1390 | }\r | |
1391 | \r | |
1392 | /**\r | |
1393 | Display CPUID_EXTENDED_CACHE_INFO leaf.\r | |
1394 | \r | |
1395 | **/\r | |
1396 | VOID\r | |
1397 | CpuidExtendedCacheInfo (\r | |
1398 | VOID\r | |
1399 | )\r | |
1400 | {\r | |
1401 | CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r | |
1402 | \r | |
1403 | if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {\r | |
1404 | return;\r | |
1405 | }\r | |
1406 | \r | |
1407 | AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r | |
1408 | Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);\r | |
1409 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx.Uint32, 0);\r | |
1410 | PRINT_BIT_FIELD (Ecx, CacheLineSize);\r | |
1411 | PRINT_BIT_FIELD (Ecx, L2Associativity);\r | |
1412 | PRINT_BIT_FIELD (Ecx, CacheSize);\r | |
1413 | }\r | |
1414 | \r | |
1415 | /**\r | |
1416 | Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.\r | |
1417 | \r | |
1418 | **/\r | |
1419 | VOID\r | |
1420 | CpuidExtendedTimeStampCounter (\r | |
1421 | VOID\r | |
1422 | )\r | |
1423 | {\r | |
1424 | CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r | |
1425 | \r | |
1426 | if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {\r | |
1427 | return;\r | |
1428 | }\r | |
1429 | \r | |
1430 | AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r | |
1431 | Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);\r | |
1432 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, 0, Edx.Uint32);\r | |
1433 | PRINT_BIT_FIELD (Edx, InvariantTsc);\r | |
1434 | }\r | |
1435 | \r | |
1436 | /**\r | |
1437 | Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.\r | |
1438 | \r | |
1439 | **/\r | |
1440 | VOID\r | |
1441 | CpuidVirPhyAddressSize (\r | |
1442 | VOID\r | |
1443 | )\r | |
1444 | {\r | |
1445 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r | |
1446 | \r | |
1447 | if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {\r | |
1448 | return;\r | |
1449 | }\r | |
1450 | \r | |
1451 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r | |
1452 | Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);\r | |
1453 | Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, 0, 0, 0);\r | |
1454 | PRINT_BIT_FIELD (Eax, PhysicalAddressBits);\r | |
1455 | PRINT_BIT_FIELD (Eax, LinearAddressBits);\r | |
1456 | }\r | |
1457 | \r | |
1458 | /**\r | |
1459 | The user Entry Point for Application. The user code starts with this function\r | |
1460 | as the real entry point for the application.\r | |
1461 | \r | |
1462 | @param[in] ImageHandle The firmware allocated handle for the EFI image.\r | |
1463 | @param[in] SystemTable A pointer to the EFI System Table.\r | |
1464 | \r | |
1465 | @retval EFI_SUCCESS The entry point is executed successfully.\r | |
1466 | @retval other Some error occurs when executing this entry point.\r | |
1467 | \r | |
1468 | **/\r | |
1469 | EFI_STATUS\r | |
1470 | EFIAPI\r | |
1471 | UefiMain (\r | |
1472 | IN EFI_HANDLE ImageHandle,\r | |
1473 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
1474 | )\r | |
1475 | {\r | |
1476 | Print (L"UEFI CPUID Version 0.5\n");\r | |
1477 | \r | |
1478 | CpuidSignature ();\r | |
1479 | CpuidVersionInfo ();\r | |
1480 | CpuidCacheInfo ();\r | |
1481 | CpuidSerialNumber ();\r | |
1482 | CpuidCacheParams();\r | |
1483 | CpuidMonitorMwait ();\r | |
1484 | CpuidThermalPowerManagement ();\r | |
1485 | CpuidStructuredExtendedFeatureFlags ();\r | |
1486 | CpuidDirectCacheAccessInfo();\r | |
1487 | CpuidArchitecturalPerformanceMonitoring ();\r | |
1488 | CpuidExtendedTopology ();\r | |
1489 | CpuidExtendedStateMainLeaf ();\r | |
1490 | CpuidIntelRdtMonitoringEnumerationSubLeaf ();\r | |
1491 | CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();\r | |
1492 | CpuidIntelRdtAllocationMainLeaf ();\r | |
1493 | CpuidEnumerationOfIntelSgx ();\r | |
1494 | CpuidIntelProcessorTraceMainLeaf ();\r | |
1495 | CpuidTimeStampCounter ();\r | |
1496 | CpuidProcessorFrequency ();\r | |
1497 | CpuidSocVendor ();\r | |
1498 | CpuidExtendedFunction ();\r | |
1499 | CpuidExtendedCpuSig ();\r | |
1500 | CpuidProcessorBrandString ();\r | |
1501 | CpuidExtendedCacheInfo ();\r | |
1502 | CpuidExtendedTimeStampCounter ();\r | |
1503 | CpuidVirPhyAddressSize ();\r | |
1504 | \r | |
1505 | return EFI_SUCCESS;\r | |
1506 | }\r |