]>
Commit | Line | Data |
---|---|---|
1 | /** @file\r | |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports xAPIC mode only.\r | |
5 | \r | |
6 | Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include <Register/LocalApic.h>\r | |
18 | \r | |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/LocalApicLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
23 | #include <Library/TimerLib.h>\r | |
24 | \r | |
25 | //\r | |
26 | // Library internal functions\r | |
27 | //\r | |
28 | \r | |
29 | /**\r | |
30 | Retrieve the base address of local APIC.\r | |
31 | \r | |
32 | @return The base address of local APIC.\r | |
33 | \r | |
34 | **/\r | |
35 | UINTN\r | |
36 | EFIAPI\r | |
37 | GetLocalApicBaseAddress (\r | |
38 | VOID\r | |
39 | )\r | |
40 | {\r | |
41 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
42 | \r | |
43 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
44 | \r | |
45 | return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r | |
46 | (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r | |
47 | }\r | |
48 | \r | |
49 | /**\r | |
50 | Set the base address of local APIC.\r | |
51 | \r | |
52 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
53 | \r | |
54 | @param[in] BaseAddress Local APIC base address to be set.\r | |
55 | \r | |
56 | **/\r | |
57 | VOID\r | |
58 | EFIAPI\r | |
59 | SetLocalApicBaseAddress (\r | |
60 | IN UINTN BaseAddress\r | |
61 | )\r | |
62 | {\r | |
63 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
64 | \r | |
65 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
66 | \r | |
67 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
68 | \r | |
69 | ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r | |
70 | ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r | |
71 | \r | |
72 | AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r | |
73 | }\r | |
74 | \r | |
75 | /**\r | |
76 | Read from a local APIC register.\r | |
77 | \r | |
78 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
79 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
80 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
81 | 32-bit read.\r | |
82 | \r | |
83 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
84 | It must be 16-byte aligned.\r | |
85 | \r | |
86 | @return 32-bit Value read from the register.\r | |
87 | **/\r | |
88 | UINT32\r | |
89 | EFIAPI\r | |
90 | ReadLocalApicReg (\r | |
91 | IN UINTN MmioOffset\r | |
92 | )\r | |
93 | {\r | |
94 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
95 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
96 | \r | |
97 | return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r | |
98 | }\r | |
99 | \r | |
100 | /**\r | |
101 | Write to a local APIC register.\r | |
102 | \r | |
103 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
104 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
105 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
106 | 32-bit write.\r | |
107 | \r | |
108 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
109 | \r | |
110 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
111 | It must be 16-byte aligned.\r | |
112 | @param Value Value to be written to the register.\r | |
113 | **/\r | |
114 | VOID\r | |
115 | EFIAPI\r | |
116 | WriteLocalApicReg (\r | |
117 | IN UINTN MmioOffset,\r | |
118 | IN UINT32 Value\r | |
119 | )\r | |
120 | {\r | |
121 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
122 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
123 | \r | |
124 | MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r | |
125 | }\r | |
126 | \r | |
127 | /**\r | |
128 | Send an IPI by writing to ICR.\r | |
129 | \r | |
130 | This function returns after the IPI has been accepted by the target processor. \r | |
131 | \r | |
132 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
133 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
134 | **/\r | |
135 | VOID\r | |
136 | SendIpi (\r | |
137 | IN UINT32 IcrLow,\r | |
138 | IN UINT32 ApicId\r | |
139 | )\r | |
140 | {\r | |
141 | LOCAL_APIC_ICR_LOW IcrLowReg;\r | |
142 | \r | |
143 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
144 | ASSERT (ApicId <= 0xff);\r | |
145 | \r | |
146 | //\r | |
147 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
148 | //\r | |
149 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r | |
150 | WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
151 | do {\r | |
152 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
153 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
154 | }\r | |
155 | \r | |
156 | //\r | |
157 | // Library API implementation functions\r | |
158 | //\r | |
159 | \r | |
160 | /**\r | |
161 | Get the current local APIC mode.\r | |
162 | \r | |
163 | If local APIC is disabled, then ASSERT.\r | |
164 | \r | |
165 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
166 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
167 | **/\r | |
168 | UINTN\r | |
169 | EFIAPI\r | |
170 | GetApicMode (\r | |
171 | VOID\r | |
172 | )\r | |
173 | {\r | |
174 | DEBUG_CODE (\r | |
175 | {\r | |
176 | MSR_IA32_APIC_BASE ApicBaseMsr;\r | |
177 | \r | |
178 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
179 | //\r | |
180 | // Local APIC should have been enabled\r | |
181 | //\r | |
182 | ASSERT (ApicBaseMsr.Bits.En != 0);\r | |
183 | ASSERT (ApicBaseMsr.Bits.Extd == 0);\r | |
184 | }\r | |
185 | );\r | |
186 | return LOCAL_APIC_MODE_XAPIC;\r | |
187 | }\r | |
188 | \r | |
189 | /**\r | |
190 | Set the current local APIC mode.\r | |
191 | \r | |
192 | If the specified local APIC mode is not valid, then ASSERT.\r | |
193 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
194 | \r | |
195 | @param ApicMode APIC mode to be set.\r | |
196 | **/\r | |
197 | VOID\r | |
198 | EFIAPI\r | |
199 | SetApicMode (\r | |
200 | IN UINTN ApicMode\r | |
201 | )\r | |
202 | {\r | |
203 | ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r | |
204 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
205 | }\r | |
206 | \r | |
207 | /**\r | |
208 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
209 | \r | |
210 | In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r | |
211 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r | |
212 | the 32-bit local APIC ID is returned as initial APIC ID.\r | |
213 | \r | |
214 | @return 32-bit initial local APIC ID of the executing processor.\r | |
215 | **/\r | |
216 | UINT32\r | |
217 | EFIAPI\r | |
218 | GetInitialApicId (\r | |
219 | VOID\r | |
220 | )\r | |
221 | {\r | |
222 | UINT32 RegEbx;\r | |
223 | \r | |
224 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
225 | \r | |
226 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r | |
227 | return RegEbx >> 24;\r | |
228 | }\r | |
229 | \r | |
230 | /**\r | |
231 | Get the local APIC ID of the executing processor.\r | |
232 | \r | |
233 | @return 32-bit local APIC ID of the executing processor.\r | |
234 | **/\r | |
235 | UINT32\r | |
236 | EFIAPI\r | |
237 | GetApicId (\r | |
238 | VOID\r | |
239 | )\r | |
240 | {\r | |
241 | UINT32 ApicId;\r | |
242 | \r | |
243 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
244 | \r | |
245 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r | |
246 | ApicId >>= 24;\r | |
247 | return ApicId;\r | |
248 | }\r | |
249 | \r | |
250 | /**\r | |
251 | Get the value of the local APIC version register.\r | |
252 | \r | |
253 | @return the value of the local APIC version register.\r | |
254 | **/\r | |
255 | UINT32\r | |
256 | EFIAPI\r | |
257 | GetApicVersion (\r | |
258 | VOID\r | |
259 | )\r | |
260 | {\r | |
261 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
262 | }\r | |
263 | \r | |
264 | /**\r | |
265 | Send a Fixed IPI to a specified target processor.\r | |
266 | \r | |
267 | This function returns after the IPI has been accepted by the target processor. \r | |
268 | \r | |
269 | @param ApicId The local APIC ID of the target processor.\r | |
270 | @param Vector The vector number of the interrupt being sent.\r | |
271 | **/\r | |
272 | VOID\r | |
273 | EFIAPI\r | |
274 | SendFixedIpi (\r | |
275 | IN UINT32 ApicId,\r | |
276 | IN UINT8 Vector\r | |
277 | )\r | |
278 | {\r | |
279 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
280 | \r | |
281 | IcrLow.Uint32 = 0;\r | |
282 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
283 | IcrLow.Bits.Level = 1;\r | |
284 | IcrLow.Bits.Vector = Vector;\r | |
285 | SendIpi (IcrLow.Uint32, ApicId);\r | |
286 | }\r | |
287 | \r | |
288 | /**\r | |
289 | Send a Fixed IPI to all processors excluding self.\r | |
290 | \r | |
291 | This function returns after the IPI has been accepted by the target processors. \r | |
292 | \r | |
293 | @param Vector The vector number of the interrupt being sent.\r | |
294 | **/\r | |
295 | VOID\r | |
296 | EFIAPI\r | |
297 | SendFixedIpiAllExcludingSelf (\r | |
298 | IN UINT8 Vector\r | |
299 | )\r | |
300 | {\r | |
301 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
302 | \r | |
303 | IcrLow.Uint32 = 0;\r | |
304 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
305 | IcrLow.Bits.Level = 1;\r | |
306 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
307 | IcrLow.Bits.Vector = Vector;\r | |
308 | SendIpi (IcrLow.Uint32, 0);\r | |
309 | }\r | |
310 | \r | |
311 | /**\r | |
312 | Send a SMI IPI to a specified target processor.\r | |
313 | \r | |
314 | This function returns after the IPI has been accepted by the target processor. \r | |
315 | \r | |
316 | @param ApicId Specify the local APIC ID of the target processor.\r | |
317 | **/\r | |
318 | VOID\r | |
319 | EFIAPI\r | |
320 | SendSmiIpi (\r | |
321 | IN UINT32 ApicId\r | |
322 | )\r | |
323 | {\r | |
324 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
325 | \r | |
326 | IcrLow.Uint32 = 0;\r | |
327 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
328 | IcrLow.Bits.Level = 1;\r | |
329 | SendIpi (IcrLow.Uint32, ApicId);\r | |
330 | }\r | |
331 | \r | |
332 | /**\r | |
333 | Send a SMI IPI to all processors excluding self.\r | |
334 | \r | |
335 | This function returns after the IPI has been accepted by the target processors. \r | |
336 | **/\r | |
337 | VOID\r | |
338 | EFIAPI\r | |
339 | SendSmiIpiAllExcludingSelf (\r | |
340 | VOID\r | |
341 | )\r | |
342 | {\r | |
343 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
344 | \r | |
345 | IcrLow.Uint32 = 0;\r | |
346 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
347 | IcrLow.Bits.Level = 1;\r | |
348 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
349 | SendIpi (IcrLow.Uint32, 0);\r | |
350 | }\r | |
351 | \r | |
352 | /**\r | |
353 | Send an INIT IPI to a specified target processor.\r | |
354 | \r | |
355 | This function returns after the IPI has been accepted by the target processor. \r | |
356 | \r | |
357 | @param ApicId Specify the local APIC ID of the target processor.\r | |
358 | **/\r | |
359 | VOID\r | |
360 | EFIAPI\r | |
361 | SendInitIpi (\r | |
362 | IN UINT32 ApicId\r | |
363 | )\r | |
364 | {\r | |
365 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
366 | \r | |
367 | IcrLow.Uint32 = 0;\r | |
368 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
369 | IcrLow.Bits.Level = 1;\r | |
370 | SendIpi (IcrLow.Uint32, ApicId);\r | |
371 | }\r | |
372 | \r | |
373 | /**\r | |
374 | Send an INIT IPI to all processors excluding self.\r | |
375 | \r | |
376 | This function returns after the IPI has been accepted by the target processors. \r | |
377 | **/\r | |
378 | VOID\r | |
379 | EFIAPI\r | |
380 | SendInitIpiAllExcludingSelf (\r | |
381 | VOID\r | |
382 | )\r | |
383 | {\r | |
384 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
385 | \r | |
386 | IcrLow.Uint32 = 0;\r | |
387 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
388 | IcrLow.Bits.Level = 1;\r | |
389 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
390 | SendIpi (IcrLow.Uint32, 0);\r | |
391 | }\r | |
392 | \r | |
393 | /**\r | |
394 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
395 | \r | |
396 | This function returns after the IPI has been accepted by the target processor. \r | |
397 | \r | |
398 | if StartupRoutine >= 1M, then ASSERT.\r | |
399 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
400 | \r | |
401 | @param ApicId Specify the local APIC ID of the target processor.\r | |
402 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
403 | address and 4K aligned.\r | |
404 | **/\r | |
405 | VOID\r | |
406 | EFIAPI\r | |
407 | SendInitSipiSipi (\r | |
408 | IN UINT32 ApicId,\r | |
409 | IN UINT32 StartupRoutine\r | |
410 | )\r | |
411 | {\r | |
412 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
413 | \r | |
414 | ASSERT (StartupRoutine < 0x100000);\r | |
415 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
416 | \r | |
417 | SendInitIpi (ApicId);\r | |
418 | MicroSecondDelay (10);\r | |
419 | IcrLow.Uint32 = 0;\r | |
420 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
421 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
422 | IcrLow.Bits.Level = 1;\r | |
423 | SendIpi (IcrLow.Uint32, ApicId);\r | |
424 | MicroSecondDelay (200);\r | |
425 | SendIpi (IcrLow.Uint32, ApicId);\r | |
426 | }\r | |
427 | \r | |
428 | /**\r | |
429 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
430 | \r | |
431 | This function returns after the IPI has been accepted by the target processors. \r | |
432 | \r | |
433 | if StartupRoutine >= 1M, then ASSERT.\r | |
434 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
435 | \r | |
436 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
437 | address and 4K aligned.\r | |
438 | **/\r | |
439 | VOID\r | |
440 | EFIAPI\r | |
441 | SendInitSipiSipiAllExcludingSelf (\r | |
442 | IN UINT32 StartupRoutine\r | |
443 | )\r | |
444 | {\r | |
445 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
446 | \r | |
447 | ASSERT (StartupRoutine < 0x100000);\r | |
448 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
449 | \r | |
450 | SendInitIpiAllExcludingSelf ();\r | |
451 | MicroSecondDelay (10);\r | |
452 | IcrLow.Uint32 = 0;\r | |
453 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
454 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
455 | IcrLow.Bits.Level = 1;\r | |
456 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
457 | SendIpi (IcrLow.Uint32, 0);\r | |
458 | MicroSecondDelay (200);\r | |
459 | SendIpi (IcrLow.Uint32, 0);\r | |
460 | }\r | |
461 | \r | |
462 | /**\r | |
463 | Programming Virtual Wire Mode.\r | |
464 | \r | |
465 | This function programs the local APIC for virtual wire mode following\r | |
466 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
467 | \r | |
468 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
469 | **/\r | |
470 | VOID\r | |
471 | EFIAPI\r | |
472 | ProgramVirtualWireMode (\r | |
473 | VOID\r | |
474 | )\r | |
475 | {\r | |
476 | LOCAL_APIC_SVR Svr;\r | |
477 | LOCAL_APIC_LVT_LINT Lint;\r | |
478 | \r | |
479 | //\r | |
480 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
481 | //\r | |
482 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
483 | Svr.Bits.SpuriousVector = 0xf;\r | |
484 | Svr.Bits.SoftwareEnable = 1;\r | |
485 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
486 | \r | |
487 | //\r | |
488 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
489 | //\r | |
490 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
491 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r | |
492 | Lint.Bits.InputPinPolarity = 0;\r | |
493 | Lint.Bits.TriggerMode = 0;\r | |
494 | Lint.Bits.Mask = 0;\r | |
495 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r | |
496 | \r | |
497 | //\r | |
498 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
499 | //\r | |
500 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
501 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r | |
502 | Lint.Bits.InputPinPolarity = 0;\r | |
503 | Lint.Bits.TriggerMode = 0;\r | |
504 | Lint.Bits.Mask = 0;\r | |
505 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r | |
506 | }\r | |
507 | \r | |
508 | /**\r | |
509 | Disable LINT0 & LINT1 interrupts.\r | |
510 | \r | |
511 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
512 | **/\r | |
513 | VOID\r | |
514 | EFIAPI\r | |
515 | DisableLvtInterrupts (\r | |
516 | VOID\r | |
517 | )\r | |
518 | {\r | |
519 | LOCAL_APIC_LVT_LINT LvtLint;\r | |
520 | \r | |
521 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
522 | LvtLint.Bits.Mask = 1;\r | |
523 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
524 | \r | |
525 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
526 | LvtLint.Bits.Mask = 1;\r | |
527 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
528 | }\r | |
529 | \r | |
530 | /**\r | |
531 | Read the initial count value from the init-count register.\r | |
532 | \r | |
533 | @return The initial count value read from the init-count register.\r | |
534 | **/\r | |
535 | UINT32\r | |
536 | EFIAPI\r | |
537 | GetApicTimerInitCount (\r | |
538 | VOID\r | |
539 | )\r | |
540 | {\r | |
541 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
542 | }\r | |
543 | \r | |
544 | /**\r | |
545 | Read the current count value from the current-count register.\r | |
546 | \r | |
547 | @return The current count value read from the current-count register.\r | |
548 | **/\r | |
549 | UINT32\r | |
550 | EFIAPI\r | |
551 | GetApicTimerCurrentCount (\r | |
552 | VOID\r | |
553 | )\r | |
554 | {\r | |
555 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
556 | }\r | |
557 | \r | |
558 | /**\r | |
559 | Initialize the local APIC timer.\r | |
560 | \r | |
561 | The local APIC timer is initialized and enabled.\r | |
562 | \r | |
563 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
564 | If it is 0, then use the current divide value in the DCR.\r | |
565 | @param InitCount The initial count value.\r | |
566 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
567 | @param Vector The timer interrupt vector number.\r | |
568 | **/\r | |
569 | VOID\r | |
570 | EFIAPI\r | |
571 | InitializeApicTimer (\r | |
572 | IN UINTN DivideValue,\r | |
573 | IN UINT32 InitCount,\r | |
574 | IN BOOLEAN PeriodicMode,\r | |
575 | IN UINT8 Vector\r | |
576 | )\r | |
577 | {\r | |
578 | LOCAL_APIC_SVR Svr;\r | |
579 | LOCAL_APIC_DCR Dcr;\r | |
580 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
581 | UINT32 Divisor;\r | |
582 | \r | |
583 | //\r | |
584 | // Ensure local APIC is in software-enabled state.\r | |
585 | //\r | |
586 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
587 | Svr.Bits.SoftwareEnable = 1;\r | |
588 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
589 | \r | |
590 | //\r | |
591 | // Program init-count register.\r | |
592 | //\r | |
593 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
594 | \r | |
595 | if (DivideValue != 0) {\r | |
596 | ASSERT (DivideValue <= 128);\r | |
597 | ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r | |
598 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r | |
599 | \r | |
600 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
601 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r | |
602 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
603 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r | |
604 | }\r | |
605 | \r | |
606 | //\r | |
607 | // Enable APIC timer interrupt with specified timer mode.\r | |
608 | //\r | |
609 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
610 | if (PeriodicMode) {\r | |
611 | LvtTimer.Bits.TimerMode = 1;\r | |
612 | } else {\r | |
613 | LvtTimer.Bits.TimerMode = 0;\r | |
614 | }\r | |
615 | LvtTimer.Bits.Mask = 0;\r | |
616 | LvtTimer.Bits.Vector = Vector;\r | |
617 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
618 | }\r | |
619 | \r | |
620 | /**\r | |
621 | Get the state of the local APIC timer.\r | |
622 | \r | |
623 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
624 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
625 | @param Vector Return the timer interrupt vector number.\r | |
626 | **/\r | |
627 | VOID\r | |
628 | EFIAPI\r | |
629 | GetApicTimerState (\r | |
630 | OUT UINTN *DivideValue OPTIONAL,\r | |
631 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
632 | OUT UINT8 *Vector OPTIONAL\r | |
633 | )\r | |
634 | {\r | |
635 | UINT32 Divisor;\r | |
636 | LOCAL_APIC_DCR Dcr;\r | |
637 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
638 | \r | |
639 | if (DivideValue != NULL) {\r | |
640 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
641 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
642 | Divisor = (Divisor + 1) & 0x7;\r | |
643 | *DivideValue = ((UINTN)1) << Divisor;\r | |
644 | }\r | |
645 | \r | |
646 | if (PeriodicMode != NULL || Vector != NULL) {\r | |
647 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
648 | if (PeriodicMode != NULL) {\r | |
649 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
650 | *PeriodicMode = TRUE;\r | |
651 | } else {\r | |
652 | *PeriodicMode = FALSE;\r | |
653 | }\r | |
654 | }\r | |
655 | if (Vector != NULL) {\r | |
656 | *Vector = (UINT8) LvtTimer.Bits.Vector;\r | |
657 | }\r | |
658 | }\r | |
659 | }\r | |
660 | \r | |
661 | /**\r | |
662 | Enable the local APIC timer interrupt.\r | |
663 | **/\r | |
664 | VOID\r | |
665 | EFIAPI\r | |
666 | EnableApicTimerInterrupt (\r | |
667 | VOID\r | |
668 | )\r | |
669 | {\r | |
670 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
671 | \r | |
672 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
673 | LvtTimer.Bits.Mask = 0;\r | |
674 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
675 | }\r | |
676 | \r | |
677 | /**\r | |
678 | Disable the local APIC timer interrupt.\r | |
679 | **/\r | |
680 | VOID\r | |
681 | EFIAPI\r | |
682 | DisableApicTimerInterrupt (\r | |
683 | VOID\r | |
684 | )\r | |
685 | {\r | |
686 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
687 | \r | |
688 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
689 | LvtTimer.Bits.Mask = 1;\r | |
690 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
691 | }\r | |
692 | \r | |
693 | /**\r | |
694 | Get the local APIC timer interrupt state.\r | |
695 | \r | |
696 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
697 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
698 | **/\r | |
699 | BOOLEAN\r | |
700 | EFIAPI\r | |
701 | GetApicTimerInterruptState (\r | |
702 | VOID\r | |
703 | )\r | |
704 | {\r | |
705 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
706 | \r | |
707 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
708 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
709 | }\r | |
710 | \r | |
711 | /**\r | |
712 | Send EOI to the local APIC.\r | |
713 | **/\r | |
714 | VOID\r | |
715 | EFIAPI\r | |
716 | SendApicEoi (\r | |
717 | VOID\r | |
718 | )\r | |
719 | {\r | |
720 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
721 | }\r | |
722 | \r | |
723 | /**\r | |
724 | Get the 32-bit address that a device should use to send a Message Signaled \r | |
725 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
726 | \r | |
727 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
728 | **/\r | |
729 | UINT32\r | |
730 | EFIAPI \r | |
731 | GetApicMsiAddress (\r | |
732 | VOID\r | |
733 | )\r | |
734 | {\r | |
735 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
736 | \r | |
737 | //\r | |
738 | // Return address for an MSI interrupt to be delivered only to the APIC ID \r | |
739 | // of the currently executing processor.\r | |
740 | //\r | |
741 | MsiAddress.Uint32 = 0;\r | |
742 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
743 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
744 | return MsiAddress.Uint32;\r | |
745 | }\r | |
746 | \r | |
747 | /**\r | |
748 | Get the 64-bit data value that a device should use to send a Message Signaled \r | |
749 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
750 | \r | |
751 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
752 | If DeliveryMode is not supported, then ASSERT().\r | |
753 | \r | |
754 | @param Vector The 8-bit interrupt vector associated with the MSI. \r | |
755 | Must be in the range 0x10..0xFE\r | |
756 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r | |
757 | is handled. The only supported values are:\r | |
758 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
759 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
760 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
761 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
762 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
763 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
764 | \r | |
765 | @param LevelTriggered TRUE specifies a level triggered interrupt. \r | |
766 | FALSE specifies an edge triggered interrupt.\r | |
767 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
768 | TRUE specifies a level triggered interrupt that active \r | |
769 | when the interrupt line is asserted.\r | |
770 | FALSE specifies a level triggered interrupt that active \r | |
771 | when the interrupt line is deasserted.\r | |
772 | \r | |
773 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
774 | **/\r | |
775 | UINT64\r | |
776 | EFIAPI \r | |
777 | GetApicMsiValue (\r | |
778 | IN UINT8 Vector,\r | |
779 | IN UINTN DeliveryMode,\r | |
780 | IN BOOLEAN LevelTriggered,\r | |
781 | IN BOOLEAN AssertionLevel\r | |
782 | )\r | |
783 | {\r | |
784 | LOCAL_APIC_MSI_DATA MsiData;\r | |
785 | \r | |
786 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
787 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
788 | \r | |
789 | MsiData.Uint64 = 0;\r | |
790 | MsiData.Bits.Vector = Vector;\r | |
791 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
792 | if (LevelTriggered) {\r | |
793 | MsiData.Bits.TriggerMode = 1;\r | |
794 | if (AssertionLevel) {\r | |
795 | MsiData.Bits.Level = 1;\r | |
796 | }\r | |
797 | }\r | |
798 | return MsiData.Uint64;\r | |
799 | }\r |